viresh kumar | bc4e814 | 2010-04-01 12:30:58 +0100 | [diff] [blame] | 1 | /* |
| 2 | * arch/arm/mach-spear3xx/spear310.c |
| 3 | * |
| 4 | * SPEAr310 machine source file |
| 5 | * |
Viresh Kumar | c5fa4fd | 2012-03-23 00:17:43 +0530 | [diff] [blame] | 6 | * Copyright (C) 2009-2012 ST Microelectronics |
| 7 | * Viresh Kumar <viresh.kumar@st.com> |
viresh kumar | bc4e814 | 2010-04-01 12:30:58 +0100 | [diff] [blame] | 8 | * |
| 9 | * This file is licensed under the terms of the GNU General Public |
| 10 | * License version 2. This program is licensed "as is" without any |
| 11 | * warranty of any kind, whether express or implied. |
| 12 | */ |
| 13 | |
Viresh Kumar | 5fb00f9 | 2012-03-26 10:39:43 +0530 | [diff] [blame] | 14 | #define pr_fmt(fmt) "SPEAr310: " fmt |
| 15 | |
Viresh Kumar | c5fa4fd | 2012-03-23 00:17:43 +0530 | [diff] [blame] | 16 | #include <linux/amba/pl08x.h> |
| 17 | #include <linux/amba/serial.h> |
| 18 | #include <linux/of_platform.h> |
| 19 | #include <asm/hardware/vic.h> |
| 20 | #include <asm/mach/arch.h> |
viresh kumar | 410782b | 2011-03-07 05:57:01 +0100 | [diff] [blame] | 21 | #include <plat/shirq.h> |
viresh kumar | bc4e814 | 2010-04-01 12:30:58 +0100 | [diff] [blame] | 22 | #include <mach/generic.h> |
Arnd Bergmann | 5019f0b | 2012-04-11 17:30:11 +0000 | [diff] [blame^] | 23 | #include <mach/spear.h> |
| 24 | |
| 25 | #define SPEAR310_UART1_BASE UL(0xB2000000) |
| 26 | #define SPEAR310_UART2_BASE UL(0xB2080000) |
| 27 | #define SPEAR310_UART3_BASE UL(0xB2100000) |
| 28 | #define SPEAR310_UART4_BASE UL(0xB2180000) |
| 29 | #define SPEAR310_UART5_BASE UL(0xB2200000) |
| 30 | #define SPEAR310_SOC_CONFIG_BASE UL(0xB4000000) |
| 31 | |
| 32 | /* Interrupt registers offsets and masks */ |
| 33 | #define SPEAR310_INT_STS_MASK_REG 0x04 |
| 34 | #define SPEAR310_SMII0_IRQ_MASK (1 << 0) |
| 35 | #define SPEAR310_SMII1_IRQ_MASK (1 << 1) |
| 36 | #define SPEAR310_SMII2_IRQ_MASK (1 << 2) |
| 37 | #define SPEAR310_SMII3_IRQ_MASK (1 << 3) |
| 38 | #define SPEAR310_WAKEUP_SMII0_IRQ_MASK (1 << 4) |
| 39 | #define SPEAR310_WAKEUP_SMII1_IRQ_MASK (1 << 5) |
| 40 | #define SPEAR310_WAKEUP_SMII2_IRQ_MASK (1 << 6) |
| 41 | #define SPEAR310_WAKEUP_SMII3_IRQ_MASK (1 << 7) |
| 42 | #define SPEAR310_UART1_IRQ_MASK (1 << 8) |
| 43 | #define SPEAR310_UART2_IRQ_MASK (1 << 9) |
| 44 | #define SPEAR310_UART3_IRQ_MASK (1 << 10) |
| 45 | #define SPEAR310_UART4_IRQ_MASK (1 << 11) |
| 46 | #define SPEAR310_UART5_IRQ_MASK (1 << 12) |
| 47 | #define SPEAR310_EMI_IRQ_MASK (1 << 13) |
| 48 | #define SPEAR310_TDM_HDLC_IRQ_MASK (1 << 14) |
| 49 | #define SPEAR310_RS485_0_IRQ_MASK (1 << 15) |
| 50 | #define SPEAR310_RS485_1_IRQ_MASK (1 << 16) |
| 51 | |
| 52 | #define SPEAR310_SHIRQ_RAS1_MASK 0x000FF |
| 53 | #define SPEAR310_SHIRQ_RAS2_MASK 0x01F00 |
| 54 | #define SPEAR310_SHIRQ_RAS3_MASK 0x02000 |
| 55 | #define SPEAR310_SHIRQ_INTRCOMM_RAS_MASK 0x1C000 |
| 56 | |
| 57 | /* SPEAr310 Virtual irq definitions */ |
| 58 | /* IRQs sharing IRQ_GEN_RAS_1 */ |
| 59 | #define SPEAR310_VIRQ_SMII0 (SPEAR3XX_VIRQ_START + 0) |
| 60 | #define SPEAR310_VIRQ_SMII1 (SPEAR3XX_VIRQ_START + 1) |
| 61 | #define SPEAR310_VIRQ_SMII2 (SPEAR3XX_VIRQ_START + 2) |
| 62 | #define SPEAR310_VIRQ_SMII3 (SPEAR3XX_VIRQ_START + 3) |
| 63 | #define SPEAR310_VIRQ_WAKEUP_SMII0 (SPEAR3XX_VIRQ_START + 4) |
| 64 | #define SPEAR310_VIRQ_WAKEUP_SMII1 (SPEAR3XX_VIRQ_START + 5) |
| 65 | #define SPEAR310_VIRQ_WAKEUP_SMII2 (SPEAR3XX_VIRQ_START + 6) |
| 66 | #define SPEAR310_VIRQ_WAKEUP_SMII3 (SPEAR3XX_VIRQ_START + 7) |
| 67 | |
| 68 | /* IRQs sharing IRQ_GEN_RAS_2 */ |
| 69 | #define SPEAR310_VIRQ_UART1 (SPEAR3XX_VIRQ_START + 8) |
| 70 | #define SPEAR310_VIRQ_UART2 (SPEAR3XX_VIRQ_START + 9) |
| 71 | #define SPEAR310_VIRQ_UART3 (SPEAR3XX_VIRQ_START + 10) |
| 72 | #define SPEAR310_VIRQ_UART4 (SPEAR3XX_VIRQ_START + 11) |
| 73 | #define SPEAR310_VIRQ_UART5 (SPEAR3XX_VIRQ_START + 12) |
| 74 | |
| 75 | /* IRQs sharing IRQ_GEN_RAS_3 */ |
| 76 | #define SPEAR310_VIRQ_EMI (SPEAR3XX_VIRQ_START + 13) |
| 77 | #define SPEAR310_VIRQ_PLGPIO (SPEAR3XX_VIRQ_START + 14) |
| 78 | |
| 79 | /* IRQs sharing IRQ_INTRCOMM_RAS_ARM */ |
| 80 | #define SPEAR310_VIRQ_TDM_HDLC (SPEAR3XX_VIRQ_START + 15) |
| 81 | #define SPEAR310_VIRQ_RS485_0 (SPEAR3XX_VIRQ_START + 16) |
| 82 | #define SPEAR310_VIRQ_RS485_1 (SPEAR3XX_VIRQ_START + 17) |
| 83 | |
viresh kumar | bc4e814 | 2010-04-01 12:30:58 +0100 | [diff] [blame] | 84 | |
viresh kumar | 70f4c0b | 2010-04-01 12:31:29 +0100 | [diff] [blame] | 85 | /* pad multiplexing support */ |
| 86 | /* muxing registers */ |
| 87 | #define PAD_MUX_CONFIG_REG 0x08 |
| 88 | |
| 89 | /* devices */ |
Ryan Mallon | 6618c3a | 2011-05-20 08:34:22 +0100 | [diff] [blame] | 90 | static struct pmx_dev_mode pmx_emi_cs_0_1_4_5_modes[] = { |
viresh kumar | 70f4c0b | 2010-04-01 12:31:29 +0100 | [diff] [blame] | 91 | { |
| 92 | .ids = 0x00, |
| 93 | .mask = PMX_TIMER_3_4_MASK, |
| 94 | }, |
| 95 | }; |
| 96 | |
Ryan Mallon | 6618c3a | 2011-05-20 08:34:22 +0100 | [diff] [blame] | 97 | struct pmx_dev spear310_pmx_emi_cs_0_1_4_5 = { |
viresh kumar | 70f4c0b | 2010-04-01 12:31:29 +0100 | [diff] [blame] | 98 | .name = "emi_cs_0_1_4_5", |
| 99 | .modes = pmx_emi_cs_0_1_4_5_modes, |
| 100 | .mode_count = ARRAY_SIZE(pmx_emi_cs_0_1_4_5_modes), |
| 101 | .enb_on_reset = 1, |
| 102 | }; |
| 103 | |
Ryan Mallon | 6618c3a | 2011-05-20 08:34:22 +0100 | [diff] [blame] | 104 | static struct pmx_dev_mode pmx_emi_cs_2_3_modes[] = { |
viresh kumar | 70f4c0b | 2010-04-01 12:31:29 +0100 | [diff] [blame] | 105 | { |
| 106 | .ids = 0x00, |
| 107 | .mask = PMX_TIMER_1_2_MASK, |
| 108 | }, |
| 109 | }; |
| 110 | |
Ryan Mallon | 6618c3a | 2011-05-20 08:34:22 +0100 | [diff] [blame] | 111 | struct pmx_dev spear310_pmx_emi_cs_2_3 = { |
viresh kumar | 70f4c0b | 2010-04-01 12:31:29 +0100 | [diff] [blame] | 112 | .name = "emi_cs_2_3", |
| 113 | .modes = pmx_emi_cs_2_3_modes, |
| 114 | .mode_count = ARRAY_SIZE(pmx_emi_cs_2_3_modes), |
| 115 | .enb_on_reset = 1, |
| 116 | }; |
| 117 | |
Ryan Mallon | 6618c3a | 2011-05-20 08:34:22 +0100 | [diff] [blame] | 118 | static struct pmx_dev_mode pmx_uart1_modes[] = { |
viresh kumar | 70f4c0b | 2010-04-01 12:31:29 +0100 | [diff] [blame] | 119 | { |
| 120 | .ids = 0x00, |
| 121 | .mask = PMX_FIRDA_MASK, |
| 122 | }, |
| 123 | }; |
| 124 | |
Ryan Mallon | 6618c3a | 2011-05-20 08:34:22 +0100 | [diff] [blame] | 125 | struct pmx_dev spear310_pmx_uart1 = { |
viresh kumar | 70f4c0b | 2010-04-01 12:31:29 +0100 | [diff] [blame] | 126 | .name = "uart1", |
| 127 | .modes = pmx_uart1_modes, |
| 128 | .mode_count = ARRAY_SIZE(pmx_uart1_modes), |
| 129 | .enb_on_reset = 1, |
| 130 | }; |
| 131 | |
Ryan Mallon | 6618c3a | 2011-05-20 08:34:22 +0100 | [diff] [blame] | 132 | static struct pmx_dev_mode pmx_uart2_modes[] = { |
viresh kumar | 70f4c0b | 2010-04-01 12:31:29 +0100 | [diff] [blame] | 133 | { |
| 134 | .ids = 0x00, |
| 135 | .mask = PMX_TIMER_1_2_MASK, |
| 136 | }, |
| 137 | }; |
| 138 | |
Ryan Mallon | 6618c3a | 2011-05-20 08:34:22 +0100 | [diff] [blame] | 139 | struct pmx_dev spear310_pmx_uart2 = { |
viresh kumar | 70f4c0b | 2010-04-01 12:31:29 +0100 | [diff] [blame] | 140 | .name = "uart2", |
| 141 | .modes = pmx_uart2_modes, |
| 142 | .mode_count = ARRAY_SIZE(pmx_uart2_modes), |
| 143 | .enb_on_reset = 1, |
| 144 | }; |
| 145 | |
Ryan Mallon | 6618c3a | 2011-05-20 08:34:22 +0100 | [diff] [blame] | 146 | static struct pmx_dev_mode pmx_uart3_4_5_modes[] = { |
viresh kumar | 70f4c0b | 2010-04-01 12:31:29 +0100 | [diff] [blame] | 147 | { |
| 148 | .ids = 0x00, |
| 149 | .mask = PMX_UART0_MODEM_MASK, |
| 150 | }, |
| 151 | }; |
| 152 | |
Ryan Mallon | 6618c3a | 2011-05-20 08:34:22 +0100 | [diff] [blame] | 153 | struct pmx_dev spear310_pmx_uart3_4_5 = { |
viresh kumar | 70f4c0b | 2010-04-01 12:31:29 +0100 | [diff] [blame] | 154 | .name = "uart3_4_5", |
| 155 | .modes = pmx_uart3_4_5_modes, |
| 156 | .mode_count = ARRAY_SIZE(pmx_uart3_4_5_modes), |
| 157 | .enb_on_reset = 1, |
| 158 | }; |
| 159 | |
Ryan Mallon | 6618c3a | 2011-05-20 08:34:22 +0100 | [diff] [blame] | 160 | static struct pmx_dev_mode pmx_fsmc_modes[] = { |
viresh kumar | 70f4c0b | 2010-04-01 12:31:29 +0100 | [diff] [blame] | 161 | { |
| 162 | .ids = 0x00, |
| 163 | .mask = PMX_SSP_CS_MASK, |
| 164 | }, |
| 165 | }; |
| 166 | |
Ryan Mallon | 6618c3a | 2011-05-20 08:34:22 +0100 | [diff] [blame] | 167 | struct pmx_dev spear310_pmx_fsmc = { |
viresh kumar | 70f4c0b | 2010-04-01 12:31:29 +0100 | [diff] [blame] | 168 | .name = "fsmc", |
| 169 | .modes = pmx_fsmc_modes, |
| 170 | .mode_count = ARRAY_SIZE(pmx_fsmc_modes), |
| 171 | .enb_on_reset = 1, |
| 172 | }; |
| 173 | |
Ryan Mallon | 6618c3a | 2011-05-20 08:34:22 +0100 | [diff] [blame] | 174 | static struct pmx_dev_mode pmx_rs485_0_1_modes[] = { |
viresh kumar | 70f4c0b | 2010-04-01 12:31:29 +0100 | [diff] [blame] | 175 | { |
| 176 | .ids = 0x00, |
| 177 | .mask = PMX_MII_MASK, |
| 178 | }, |
| 179 | }; |
| 180 | |
Ryan Mallon | 6618c3a | 2011-05-20 08:34:22 +0100 | [diff] [blame] | 181 | struct pmx_dev spear310_pmx_rs485_0_1 = { |
viresh kumar | 70f4c0b | 2010-04-01 12:31:29 +0100 | [diff] [blame] | 182 | .name = "rs485_0_1", |
| 183 | .modes = pmx_rs485_0_1_modes, |
| 184 | .mode_count = ARRAY_SIZE(pmx_rs485_0_1_modes), |
| 185 | .enb_on_reset = 1, |
| 186 | }; |
| 187 | |
Ryan Mallon | 6618c3a | 2011-05-20 08:34:22 +0100 | [diff] [blame] | 188 | static struct pmx_dev_mode pmx_tdm0_modes[] = { |
viresh kumar | 70f4c0b | 2010-04-01 12:31:29 +0100 | [diff] [blame] | 189 | { |
| 190 | .ids = 0x00, |
| 191 | .mask = PMX_MII_MASK, |
| 192 | }, |
| 193 | }; |
| 194 | |
Ryan Mallon | 6618c3a | 2011-05-20 08:34:22 +0100 | [diff] [blame] | 195 | struct pmx_dev spear310_pmx_tdm0 = { |
viresh kumar | 70f4c0b | 2010-04-01 12:31:29 +0100 | [diff] [blame] | 196 | .name = "tdm0", |
| 197 | .modes = pmx_tdm0_modes, |
| 198 | .mode_count = ARRAY_SIZE(pmx_tdm0_modes), |
| 199 | .enb_on_reset = 1, |
| 200 | }; |
| 201 | |
| 202 | /* pmx driver structure */ |
Ryan Mallon | 6618c3a | 2011-05-20 08:34:22 +0100 | [diff] [blame] | 203 | static struct pmx_driver pmx_driver = { |
viresh kumar | 70f4c0b | 2010-04-01 12:31:29 +0100 | [diff] [blame] | 204 | .mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff}, |
| 205 | }; |
| 206 | |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 207 | /* spear3xx shared irq */ |
Ryan Mallon | f6558bf | 2011-05-20 08:34:20 +0100 | [diff] [blame] | 208 | static struct shirq_dev_config shirq_ras1_config[] = { |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 209 | { |
Ryan Mallon | 61e72bc | 2011-05-20 08:34:21 +0100 | [diff] [blame] | 210 | .virq = SPEAR310_VIRQ_SMII0, |
| 211 | .status_mask = SPEAR310_SMII0_IRQ_MASK, |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 212 | }, { |
Ryan Mallon | 61e72bc | 2011-05-20 08:34:21 +0100 | [diff] [blame] | 213 | .virq = SPEAR310_VIRQ_SMII1, |
| 214 | .status_mask = SPEAR310_SMII1_IRQ_MASK, |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 215 | }, { |
Ryan Mallon | 61e72bc | 2011-05-20 08:34:21 +0100 | [diff] [blame] | 216 | .virq = SPEAR310_VIRQ_SMII2, |
| 217 | .status_mask = SPEAR310_SMII2_IRQ_MASK, |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 218 | }, { |
Ryan Mallon | 61e72bc | 2011-05-20 08:34:21 +0100 | [diff] [blame] | 219 | .virq = SPEAR310_VIRQ_SMII3, |
| 220 | .status_mask = SPEAR310_SMII3_IRQ_MASK, |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 221 | }, { |
Ryan Mallon | 61e72bc | 2011-05-20 08:34:21 +0100 | [diff] [blame] | 222 | .virq = SPEAR310_VIRQ_WAKEUP_SMII0, |
| 223 | .status_mask = SPEAR310_WAKEUP_SMII0_IRQ_MASK, |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 224 | }, { |
Ryan Mallon | 61e72bc | 2011-05-20 08:34:21 +0100 | [diff] [blame] | 225 | .virq = SPEAR310_VIRQ_WAKEUP_SMII1, |
| 226 | .status_mask = SPEAR310_WAKEUP_SMII1_IRQ_MASK, |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 227 | }, { |
Ryan Mallon | 61e72bc | 2011-05-20 08:34:21 +0100 | [diff] [blame] | 228 | .virq = SPEAR310_VIRQ_WAKEUP_SMII2, |
| 229 | .status_mask = SPEAR310_WAKEUP_SMII2_IRQ_MASK, |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 230 | }, { |
Ryan Mallon | 61e72bc | 2011-05-20 08:34:21 +0100 | [diff] [blame] | 231 | .virq = SPEAR310_VIRQ_WAKEUP_SMII3, |
| 232 | .status_mask = SPEAR310_WAKEUP_SMII3_IRQ_MASK, |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 233 | }, |
| 234 | }; |
| 235 | |
Ryan Mallon | f6558bf | 2011-05-20 08:34:20 +0100 | [diff] [blame] | 236 | static struct spear_shirq shirq_ras1 = { |
Ryan Mallon | 61e72bc | 2011-05-20 08:34:21 +0100 | [diff] [blame] | 237 | .irq = SPEAR3XX_IRQ_GEN_RAS_1, |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 238 | .dev_config = shirq_ras1_config, |
| 239 | .dev_count = ARRAY_SIZE(shirq_ras1_config), |
| 240 | .regs = { |
| 241 | .enb_reg = -1, |
Ryan Mallon | 61e72bc | 2011-05-20 08:34:21 +0100 | [diff] [blame] | 242 | .status_reg = SPEAR310_INT_STS_MASK_REG, |
| 243 | .status_reg_mask = SPEAR310_SHIRQ_RAS1_MASK, |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 244 | .clear_reg = -1, |
| 245 | }, |
| 246 | }; |
| 247 | |
Ryan Mallon | f6558bf | 2011-05-20 08:34:20 +0100 | [diff] [blame] | 248 | static struct shirq_dev_config shirq_ras2_config[] = { |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 249 | { |
Ryan Mallon | 61e72bc | 2011-05-20 08:34:21 +0100 | [diff] [blame] | 250 | .virq = SPEAR310_VIRQ_UART1, |
| 251 | .status_mask = SPEAR310_UART1_IRQ_MASK, |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 252 | }, { |
Ryan Mallon | 61e72bc | 2011-05-20 08:34:21 +0100 | [diff] [blame] | 253 | .virq = SPEAR310_VIRQ_UART2, |
| 254 | .status_mask = SPEAR310_UART2_IRQ_MASK, |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 255 | }, { |
Ryan Mallon | 61e72bc | 2011-05-20 08:34:21 +0100 | [diff] [blame] | 256 | .virq = SPEAR310_VIRQ_UART3, |
| 257 | .status_mask = SPEAR310_UART3_IRQ_MASK, |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 258 | }, { |
Ryan Mallon | 61e72bc | 2011-05-20 08:34:21 +0100 | [diff] [blame] | 259 | .virq = SPEAR310_VIRQ_UART4, |
| 260 | .status_mask = SPEAR310_UART4_IRQ_MASK, |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 261 | }, { |
Ryan Mallon | 61e72bc | 2011-05-20 08:34:21 +0100 | [diff] [blame] | 262 | .virq = SPEAR310_VIRQ_UART5, |
| 263 | .status_mask = SPEAR310_UART5_IRQ_MASK, |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 264 | }, |
| 265 | }; |
| 266 | |
Ryan Mallon | f6558bf | 2011-05-20 08:34:20 +0100 | [diff] [blame] | 267 | static struct spear_shirq shirq_ras2 = { |
Ryan Mallon | 61e72bc | 2011-05-20 08:34:21 +0100 | [diff] [blame] | 268 | .irq = SPEAR3XX_IRQ_GEN_RAS_2, |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 269 | .dev_config = shirq_ras2_config, |
| 270 | .dev_count = ARRAY_SIZE(shirq_ras2_config), |
| 271 | .regs = { |
| 272 | .enb_reg = -1, |
Ryan Mallon | 61e72bc | 2011-05-20 08:34:21 +0100 | [diff] [blame] | 273 | .status_reg = SPEAR310_INT_STS_MASK_REG, |
| 274 | .status_reg_mask = SPEAR310_SHIRQ_RAS2_MASK, |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 275 | .clear_reg = -1, |
| 276 | }, |
| 277 | }; |
| 278 | |
Ryan Mallon | f6558bf | 2011-05-20 08:34:20 +0100 | [diff] [blame] | 279 | static struct shirq_dev_config shirq_ras3_config[] = { |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 280 | { |
Ryan Mallon | 61e72bc | 2011-05-20 08:34:21 +0100 | [diff] [blame] | 281 | .virq = SPEAR310_VIRQ_EMI, |
| 282 | .status_mask = SPEAR310_EMI_IRQ_MASK, |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 283 | }, |
| 284 | }; |
| 285 | |
Ryan Mallon | f6558bf | 2011-05-20 08:34:20 +0100 | [diff] [blame] | 286 | static struct spear_shirq shirq_ras3 = { |
Ryan Mallon | 61e72bc | 2011-05-20 08:34:21 +0100 | [diff] [blame] | 287 | .irq = SPEAR3XX_IRQ_GEN_RAS_3, |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 288 | .dev_config = shirq_ras3_config, |
| 289 | .dev_count = ARRAY_SIZE(shirq_ras3_config), |
| 290 | .regs = { |
| 291 | .enb_reg = -1, |
Ryan Mallon | 61e72bc | 2011-05-20 08:34:21 +0100 | [diff] [blame] | 292 | .status_reg = SPEAR310_INT_STS_MASK_REG, |
| 293 | .status_reg_mask = SPEAR310_SHIRQ_RAS3_MASK, |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 294 | .clear_reg = -1, |
| 295 | }, |
| 296 | }; |
| 297 | |
Ryan Mallon | f6558bf | 2011-05-20 08:34:20 +0100 | [diff] [blame] | 298 | static struct shirq_dev_config shirq_intrcomm_ras_config[] = { |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 299 | { |
Ryan Mallon | 61e72bc | 2011-05-20 08:34:21 +0100 | [diff] [blame] | 300 | .virq = SPEAR310_VIRQ_TDM_HDLC, |
| 301 | .status_mask = SPEAR310_TDM_HDLC_IRQ_MASK, |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 302 | }, { |
Ryan Mallon | 61e72bc | 2011-05-20 08:34:21 +0100 | [diff] [blame] | 303 | .virq = SPEAR310_VIRQ_RS485_0, |
| 304 | .status_mask = SPEAR310_RS485_0_IRQ_MASK, |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 305 | }, { |
Ryan Mallon | 61e72bc | 2011-05-20 08:34:21 +0100 | [diff] [blame] | 306 | .virq = SPEAR310_VIRQ_RS485_1, |
| 307 | .status_mask = SPEAR310_RS485_1_IRQ_MASK, |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 308 | }, |
| 309 | }; |
| 310 | |
Ryan Mallon | f6558bf | 2011-05-20 08:34:20 +0100 | [diff] [blame] | 311 | static struct spear_shirq shirq_intrcomm_ras = { |
Ryan Mallon | 61e72bc | 2011-05-20 08:34:21 +0100 | [diff] [blame] | 312 | .irq = SPEAR3XX_IRQ_INTRCOMM_RAS_ARM, |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 313 | .dev_config = shirq_intrcomm_ras_config, |
| 314 | .dev_count = ARRAY_SIZE(shirq_intrcomm_ras_config), |
| 315 | .regs = { |
| 316 | .enb_reg = -1, |
Ryan Mallon | 61e72bc | 2011-05-20 08:34:21 +0100 | [diff] [blame] | 317 | .status_reg = SPEAR310_INT_STS_MASK_REG, |
| 318 | .status_reg_mask = SPEAR310_SHIRQ_INTRCOMM_RAS_MASK, |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 319 | .clear_reg = -1, |
| 320 | }, |
| 321 | }; |
| 322 | |
Viresh Kumar | c5fa4fd | 2012-03-23 00:17:43 +0530 | [diff] [blame] | 323 | /* padmux devices to enable */ |
| 324 | static struct pmx_dev *spear310_evb_pmx_devs[] = { |
| 325 | /* spear3xx specific devices */ |
| 326 | &spear3xx_pmx_i2c, |
| 327 | &spear3xx_pmx_ssp, |
| 328 | &spear3xx_pmx_gpio_pin0, |
| 329 | &spear3xx_pmx_gpio_pin1, |
| 330 | &spear3xx_pmx_gpio_pin2, |
| 331 | &spear3xx_pmx_gpio_pin3, |
| 332 | &spear3xx_pmx_gpio_pin4, |
| 333 | &spear3xx_pmx_gpio_pin5, |
| 334 | &spear3xx_pmx_uart0, |
viresh kumar | c2c0783 | 2011-03-07 05:57:05 +0100 | [diff] [blame] | 335 | |
Viresh Kumar | c5fa4fd | 2012-03-23 00:17:43 +0530 | [diff] [blame] | 336 | /* spear310 specific devices */ |
| 337 | &spear310_pmx_emi_cs_0_1_4_5, |
| 338 | &spear310_pmx_emi_cs_2_3, |
| 339 | &spear310_pmx_uart1, |
| 340 | &spear310_pmx_uart2, |
| 341 | &spear310_pmx_uart3_4_5, |
| 342 | &spear310_pmx_fsmc, |
| 343 | &spear310_pmx_rs485_0_1, |
| 344 | &spear310_pmx_tdm0, |
| 345 | }; |
| 346 | |
Viresh Kumar | 0b7ee71 | 2012-03-26 10:29:23 +0530 | [diff] [blame] | 347 | /* DMAC platform data's slave info */ |
| 348 | struct pl08x_channel_data spear310_dma_info[] = { |
| 349 | { |
| 350 | .bus_id = "uart0_rx", |
| 351 | .min_signal = 2, |
| 352 | .max_signal = 2, |
| 353 | .muxval = 0, |
| 354 | .cctl = 0, |
| 355 | .periph_buses = PL08X_AHB1, |
| 356 | }, { |
| 357 | .bus_id = "uart0_tx", |
| 358 | .min_signal = 3, |
| 359 | .max_signal = 3, |
| 360 | .muxval = 0, |
| 361 | .cctl = 0, |
| 362 | .periph_buses = PL08X_AHB1, |
| 363 | }, { |
| 364 | .bus_id = "ssp0_rx", |
| 365 | .min_signal = 8, |
| 366 | .max_signal = 8, |
| 367 | .muxval = 0, |
| 368 | .cctl = 0, |
| 369 | .periph_buses = PL08X_AHB1, |
| 370 | }, { |
| 371 | .bus_id = "ssp0_tx", |
| 372 | .min_signal = 9, |
| 373 | .max_signal = 9, |
| 374 | .muxval = 0, |
| 375 | .cctl = 0, |
| 376 | .periph_buses = PL08X_AHB1, |
| 377 | }, { |
| 378 | .bus_id = "i2c_rx", |
| 379 | .min_signal = 10, |
| 380 | .max_signal = 10, |
| 381 | .muxval = 0, |
| 382 | .cctl = 0, |
| 383 | .periph_buses = PL08X_AHB1, |
| 384 | }, { |
| 385 | .bus_id = "i2c_tx", |
| 386 | .min_signal = 11, |
| 387 | .max_signal = 11, |
| 388 | .muxval = 0, |
| 389 | .cctl = 0, |
| 390 | .periph_buses = PL08X_AHB1, |
| 391 | }, { |
| 392 | .bus_id = "irda", |
| 393 | .min_signal = 12, |
| 394 | .max_signal = 12, |
| 395 | .muxval = 0, |
| 396 | .cctl = 0, |
| 397 | .periph_buses = PL08X_AHB1, |
| 398 | }, { |
| 399 | .bus_id = "adc", |
| 400 | .min_signal = 13, |
| 401 | .max_signal = 13, |
| 402 | .muxval = 0, |
| 403 | .cctl = 0, |
| 404 | .periph_buses = PL08X_AHB1, |
| 405 | }, { |
| 406 | .bus_id = "to_jpeg", |
| 407 | .min_signal = 14, |
| 408 | .max_signal = 14, |
| 409 | .muxval = 0, |
| 410 | .cctl = 0, |
| 411 | .periph_buses = PL08X_AHB1, |
| 412 | }, { |
| 413 | .bus_id = "from_jpeg", |
| 414 | .min_signal = 15, |
| 415 | .max_signal = 15, |
| 416 | .muxval = 0, |
| 417 | .cctl = 0, |
| 418 | .periph_buses = PL08X_AHB1, |
| 419 | }, { |
| 420 | .bus_id = "uart1_rx", |
| 421 | .min_signal = 0, |
| 422 | .max_signal = 0, |
| 423 | .muxval = 1, |
| 424 | .cctl = 0, |
| 425 | .periph_buses = PL08X_AHB1, |
| 426 | }, { |
| 427 | .bus_id = "uart1_tx", |
| 428 | .min_signal = 1, |
| 429 | .max_signal = 1, |
| 430 | .muxval = 1, |
| 431 | .cctl = 0, |
| 432 | .periph_buses = PL08X_AHB1, |
| 433 | }, { |
| 434 | .bus_id = "uart2_rx", |
| 435 | .min_signal = 2, |
| 436 | .max_signal = 2, |
| 437 | .muxval = 1, |
| 438 | .cctl = 0, |
| 439 | .periph_buses = PL08X_AHB1, |
| 440 | }, { |
| 441 | .bus_id = "uart2_tx", |
| 442 | .min_signal = 3, |
| 443 | .max_signal = 3, |
| 444 | .muxval = 1, |
| 445 | .cctl = 0, |
| 446 | .periph_buses = PL08X_AHB1, |
| 447 | }, { |
| 448 | .bus_id = "uart3_rx", |
| 449 | .min_signal = 4, |
| 450 | .max_signal = 4, |
| 451 | .muxval = 1, |
| 452 | .cctl = 0, |
| 453 | .periph_buses = PL08X_AHB1, |
| 454 | }, { |
| 455 | .bus_id = "uart3_tx", |
| 456 | .min_signal = 5, |
| 457 | .max_signal = 5, |
| 458 | .muxval = 1, |
| 459 | .cctl = 0, |
| 460 | .periph_buses = PL08X_AHB1, |
| 461 | }, { |
| 462 | .bus_id = "uart4_rx", |
| 463 | .min_signal = 6, |
| 464 | .max_signal = 6, |
| 465 | .muxval = 1, |
| 466 | .cctl = 0, |
| 467 | .periph_buses = PL08X_AHB1, |
| 468 | }, { |
| 469 | .bus_id = "uart4_tx", |
| 470 | .min_signal = 7, |
| 471 | .max_signal = 7, |
| 472 | .muxval = 1, |
| 473 | .cctl = 0, |
| 474 | .periph_buses = PL08X_AHB1, |
| 475 | }, { |
| 476 | .bus_id = "uart5_rx", |
| 477 | .min_signal = 8, |
| 478 | .max_signal = 8, |
| 479 | .muxval = 1, |
| 480 | .cctl = 0, |
| 481 | .periph_buses = PL08X_AHB1, |
| 482 | }, { |
| 483 | .bus_id = "uart5_tx", |
| 484 | .min_signal = 9, |
| 485 | .max_signal = 9, |
| 486 | .muxval = 1, |
| 487 | .cctl = 0, |
| 488 | .periph_buses = PL08X_AHB1, |
| 489 | }, { |
| 490 | .bus_id = "ras5_rx", |
| 491 | .min_signal = 10, |
| 492 | .max_signal = 10, |
| 493 | .muxval = 1, |
| 494 | .cctl = 0, |
| 495 | .periph_buses = PL08X_AHB1, |
| 496 | }, { |
| 497 | .bus_id = "ras5_tx", |
| 498 | .min_signal = 11, |
| 499 | .max_signal = 11, |
| 500 | .muxval = 1, |
| 501 | .cctl = 0, |
| 502 | .periph_buses = PL08X_AHB1, |
| 503 | }, { |
| 504 | .bus_id = "ras6_rx", |
| 505 | .min_signal = 12, |
| 506 | .max_signal = 12, |
| 507 | .muxval = 1, |
| 508 | .cctl = 0, |
| 509 | .periph_buses = PL08X_AHB1, |
| 510 | }, { |
| 511 | .bus_id = "ras6_tx", |
| 512 | .min_signal = 13, |
| 513 | .max_signal = 13, |
| 514 | .muxval = 1, |
| 515 | .cctl = 0, |
| 516 | .periph_buses = PL08X_AHB1, |
| 517 | }, { |
| 518 | .bus_id = "ras7_rx", |
| 519 | .min_signal = 14, |
| 520 | .max_signal = 14, |
| 521 | .muxval = 1, |
| 522 | .cctl = 0, |
| 523 | .periph_buses = PL08X_AHB1, |
| 524 | }, { |
| 525 | .bus_id = "ras7_tx", |
| 526 | .min_signal = 15, |
| 527 | .max_signal = 15, |
| 528 | .muxval = 1, |
| 529 | .cctl = 0, |
| 530 | .periph_buses = PL08X_AHB1, |
| 531 | }, |
| 532 | }; |
| 533 | |
Viresh Kumar | c5fa4fd | 2012-03-23 00:17:43 +0530 | [diff] [blame] | 534 | /* uart devices plat data */ |
| 535 | static struct amba_pl011_data spear310_uart_data[] = { |
| 536 | { |
| 537 | .dma_filter = pl08x_filter_id, |
| 538 | .dma_tx_param = "uart1_tx", |
| 539 | .dma_rx_param = "uart1_rx", |
| 540 | }, { |
| 541 | .dma_filter = pl08x_filter_id, |
| 542 | .dma_tx_param = "uart2_tx", |
| 543 | .dma_rx_param = "uart2_rx", |
| 544 | }, { |
| 545 | .dma_filter = pl08x_filter_id, |
| 546 | .dma_tx_param = "uart3_tx", |
| 547 | .dma_rx_param = "uart3_rx", |
| 548 | }, { |
| 549 | .dma_filter = pl08x_filter_id, |
| 550 | .dma_tx_param = "uart4_tx", |
| 551 | .dma_rx_param = "uart4_rx", |
| 552 | }, { |
| 553 | .dma_filter = pl08x_filter_id, |
| 554 | .dma_tx_param = "uart5_tx", |
| 555 | .dma_rx_param = "uart5_rx", |
| 556 | }, |
| 557 | }; |
| 558 | |
| 559 | /* Add SPEAr310 auxdata to pass platform data */ |
| 560 | static struct of_dev_auxdata spear310_auxdata_lookup[] __initdata = { |
| 561 | OF_DEV_AUXDATA("arm,pl022", SPEAR3XX_ICM1_SSP_BASE, NULL, |
| 562 | &pl022_plat_data), |
Viresh Kumar | 0b7ee71 | 2012-03-26 10:29:23 +0530 | [diff] [blame] | 563 | OF_DEV_AUXDATA("arm,pl080", SPEAR3XX_ICM3_DMA_BASE, NULL, |
| 564 | &pl080_plat_data), |
Viresh Kumar | c5fa4fd | 2012-03-23 00:17:43 +0530 | [diff] [blame] | 565 | OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART1_BASE, NULL, |
| 566 | &spear310_uart_data[0]), |
| 567 | OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART2_BASE, NULL, |
| 568 | &spear310_uart_data[1]), |
| 569 | OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART3_BASE, NULL, |
| 570 | &spear310_uart_data[2]), |
| 571 | OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART4_BASE, NULL, |
| 572 | &spear310_uart_data[3]), |
| 573 | OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART5_BASE, NULL, |
| 574 | &spear310_uart_data[4]), |
| 575 | {} |
| 576 | }; |
| 577 | |
| 578 | static void __init spear310_dt_init(void) |
viresh kumar | bc4e814 | 2010-04-01 12:30:58 +0100 | [diff] [blame] | 579 | { |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 580 | void __iomem *base; |
| 581 | int ret = 0; |
| 582 | |
Viresh Kumar | 0b7ee71 | 2012-03-26 10:29:23 +0530 | [diff] [blame] | 583 | pl080_plat_data.slave_channels = spear310_dma_info; |
| 584 | pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear310_dma_info); |
| 585 | |
Viresh Kumar | c5fa4fd | 2012-03-23 00:17:43 +0530 | [diff] [blame] | 586 | of_platform_populate(NULL, of_default_bus_match_table, |
| 587 | spear310_auxdata_lookup, NULL); |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 588 | |
Uwe Kleine-König | b595076 | 2010-11-01 15:38:34 -0400 | [diff] [blame] | 589 | /* shared irq registration */ |
viresh kumar | 5382116 | 2011-03-07 05:57:06 +0100 | [diff] [blame] | 590 | base = ioremap(SPEAR310_SOC_CONFIG_BASE, SZ_4K); |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 591 | if (base) { |
| 592 | /* shirq 1 */ |
| 593 | shirq_ras1.regs.base = base; |
| 594 | ret = spear_shirq_register(&shirq_ras1); |
| 595 | if (ret) |
Viresh Kumar | 5fb00f9 | 2012-03-26 10:39:43 +0530 | [diff] [blame] | 596 | pr_err("Error registering Shared IRQ 1\n"); |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 597 | |
| 598 | /* shirq 2 */ |
| 599 | shirq_ras2.regs.base = base; |
| 600 | ret = spear_shirq_register(&shirq_ras2); |
| 601 | if (ret) |
Viresh Kumar | 5fb00f9 | 2012-03-26 10:39:43 +0530 | [diff] [blame] | 602 | pr_err("Error registering Shared IRQ 2\n"); |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 603 | |
| 604 | /* shirq 3 */ |
| 605 | shirq_ras3.regs.base = base; |
| 606 | ret = spear_shirq_register(&shirq_ras3); |
| 607 | if (ret) |
Viresh Kumar | 5fb00f9 | 2012-03-26 10:39:43 +0530 | [diff] [blame] | 608 | pr_err("Error registering Shared IRQ 3\n"); |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 609 | |
| 610 | /* shirq 4 */ |
| 611 | shirq_intrcomm_ras.regs.base = base; |
| 612 | ret = spear_shirq_register(&shirq_intrcomm_ras); |
| 613 | if (ret) |
Viresh Kumar | 5fb00f9 | 2012-03-26 10:39:43 +0530 | [diff] [blame] | 614 | pr_err("Error registering Shared IRQ 4\n"); |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 615 | } |
viresh kumar | 70f4c0b | 2010-04-01 12:31:29 +0100 | [diff] [blame] | 616 | |
Viresh Kumar | c5fa4fd | 2012-03-23 00:17:43 +0530 | [diff] [blame] | 617 | if (of_machine_is_compatible("st,spear310-evb")) { |
| 618 | /* pmx initialization */ |
| 619 | pmx_driver.base = base; |
| 620 | pmx_driver.mode = NULL; |
| 621 | pmx_driver.devs = spear310_evb_pmx_devs; |
| 622 | pmx_driver.devs_count = ARRAY_SIZE(spear310_evb_pmx_devs); |
Ryan Mallon | 6618c3a | 2011-05-20 08:34:22 +0100 | [diff] [blame] | 623 | |
Viresh Kumar | c5fa4fd | 2012-03-23 00:17:43 +0530 | [diff] [blame] | 624 | ret = pmx_register(&pmx_driver); |
| 625 | if (ret) |
| 626 | pr_err("padmux: registration failed. err no: %d\n", |
| 627 | ret); |
| 628 | } |
viresh kumar | 70f4c0b | 2010-04-01 12:31:29 +0100 | [diff] [blame] | 629 | } |
Viresh Kumar | c5fa4fd | 2012-03-23 00:17:43 +0530 | [diff] [blame] | 630 | |
| 631 | static const char * const spear310_dt_board_compat[] = { |
| 632 | "st,spear310", |
| 633 | "st,spear310-evb", |
| 634 | NULL, |
| 635 | }; |
| 636 | |
| 637 | static void __init spear310_map_io(void) |
| 638 | { |
| 639 | spear3xx_map_io(); |
| 640 | spear310_clk_init(); |
| 641 | } |
| 642 | |
| 643 | DT_MACHINE_START(SPEAR310_DT, "ST SPEAr310 SoC with Flattened Device Tree") |
| 644 | .map_io = spear310_map_io, |
| 645 | .init_irq = spear3xx_dt_init_irq, |
| 646 | .handle_irq = vic_handle_irq, |
| 647 | .timer = &spear3xx_timer, |
| 648 | .init_machine = spear310_dt_init, |
| 649 | .restart = spear_restart, |
| 650 | .dt_compat = spear310_dt_board_compat, |
| 651 | MACHINE_END |