Dhaval Patel | 14d46ce | 2017-01-17 16:28:12 -0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2014-2017 The Linux Foundation. All rights reserved. |
| 3 | * Copyright (C) 2013 Red Hat |
| 4 | * Author: Rob Clark <robdclark@gmail.com> |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 5 | * |
Dhaval Patel | 14d46ce | 2017-01-17 16:28:12 -0800 | [diff] [blame] | 6 | * This program is free software; you can redistribute it and/or modify it |
| 7 | * under the terms of the GNU General Public License version 2 as published by |
| 8 | * the Free Software Foundation. |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 9 | * |
Dhaval Patel | 14d46ce | 2017-01-17 16:28:12 -0800 | [diff] [blame] | 10 | * This program is distributed in the hope that it will be useful, but WITHOUT |
| 11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 13 | * more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License along with |
| 16 | * this program. If not, see <http://www.gnu.org/licenses/>. |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 17 | */ |
| 18 | |
Clarence Ip | d9f9fa6 | 2016-09-09 13:42:32 -0400 | [diff] [blame] | 19 | #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__ |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 20 | #include <linux/sort.h> |
Clarence Ip | 8f7366c | 2016-07-05 12:15:26 -0400 | [diff] [blame] | 21 | #include <linux/debugfs.h> |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 22 | #include <linux/ktime.h> |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 23 | #include <uapi/drm/sde_drm.h> |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 24 | #include <drm/drm_mode.h> |
| 25 | #include <drm/drm_crtc.h> |
| 26 | #include <drm/drm_crtc_helper.h> |
| 27 | #include <drm/drm_flip_work.h> |
| 28 | |
| 29 | #include "sde_kms.h" |
| 30 | #include "sde_hw_lm.h" |
Clarence Ip | c475b08 | 2016-06-26 09:27:23 -0400 | [diff] [blame] | 31 | #include "sde_hw_ctl.h" |
Abhijit Kulkarni | 40e3816 | 2016-06-26 22:12:09 -0400 | [diff] [blame] | 32 | #include "sde_crtc.h" |
Alan Kwong | 83285fb | 2016-10-21 20:51:17 -0400 | [diff] [blame] | 33 | #include "sde_plane.h" |
Gopikrishnaiah Anandan | e0e5e0c | 2016-05-25 11:05:33 -0700 | [diff] [blame] | 34 | #include "sde_color_processing.h" |
Alan Kwong | 83285fb | 2016-10-21 20:51:17 -0400 | [diff] [blame] | 35 | #include "sde_encoder.h" |
| 36 | #include "sde_connector.h" |
Clarence Ip | 980405d | 2017-08-08 18:33:44 -0400 | [diff] [blame] | 37 | #include "sde_vbif.h" |
Alan Kwong | 67a3f79 | 2016-11-01 23:16:53 -0400 | [diff] [blame] | 38 | #include "sde_power_handle.h" |
Alan Kwong | 9aa061c | 2016-11-06 21:17:12 -0500 | [diff] [blame] | 39 | #include "sde_core_perf.h" |
Narendra Muppalla | 77b3293 | 2017-05-10 13:53:11 -0700 | [diff] [blame] | 40 | #include "sde_trace.h" |
Abhijit Kulkarni | 1b3340c | 2017-06-22 12:39:37 -0700 | [diff] [blame] | 41 | #include <soc/qcom/scm.h> |
| 42 | #include "soc/qcom/secure_buffer.h" |
| 43 | |
| 44 | /* defines for secure channel call */ |
| 45 | #define SEC_SID_CNT 2 |
| 46 | #define SEC_SID_MASK_0 0x80881 |
| 47 | #define SEC_SID_MASK_1 0x80C81 |
| 48 | #define MEM_PROTECT_SD_CTRL_SWITCH 0x18 |
| 49 | #define MDP_DEVICE_ID 0x1A |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 50 | |
Gopikrishnaiah Anandan | de2c81b | 2017-03-15 12:41:29 -0700 | [diff] [blame] | 51 | struct sde_crtc_irq_info { |
| 52 | struct sde_irq_callback irq; |
| 53 | u32 event; |
| 54 | int (*func)(struct drm_crtc *crtc, bool en, |
| 55 | struct sde_irq_callback *irq); |
| 56 | struct list_head list; |
| 57 | }; |
| 58 | |
Gopikrishnaiah Anandan | b6b401f | 2017-03-14 16:39:49 -0700 | [diff] [blame] | 59 | struct sde_crtc_custom_events { |
| 60 | u32 event; |
| 61 | int (*func)(struct drm_crtc *crtc, bool en, |
| 62 | struct sde_irq_callback *irq); |
| 63 | }; |
| 64 | |
Gopikrishnaiah Anandan | 84b4f67 | 2017-04-26 10:28:51 -0700 | [diff] [blame] | 65 | static int sde_crtc_power_interrupt_handler(struct drm_crtc *crtc_drm, |
| 66 | bool en, struct sde_irq_callback *ad_irq); |
| 67 | |
Benjamin Chan | 9013910 | 2017-06-21 16:00:39 -0400 | [diff] [blame] | 68 | static int sde_crtc_pm_event_handler(struct drm_crtc *crtc_drm, |
| 69 | bool en, struct sde_irq_callback *noirq); |
| 70 | |
Gopikrishnaiah Anandan | b6b401f | 2017-03-14 16:39:49 -0700 | [diff] [blame] | 71 | static struct sde_crtc_custom_events custom_events[] = { |
Gopikrishnaiah Anandan | 84b4f67 | 2017-04-26 10:28:51 -0700 | [diff] [blame] | 72 | {DRM_EVENT_AD_BACKLIGHT, sde_cp_ad_interrupt}, |
Benjamin Chan | 9013910 | 2017-06-21 16:00:39 -0400 | [diff] [blame] | 73 | {DRM_EVENT_CRTC_POWER, sde_crtc_power_interrupt_handler}, |
| 74 | {DRM_EVENT_SDE_POWER, sde_crtc_pm_event_handler}, |
Gopikrishnaiah Anandan | b6b401f | 2017-03-14 16:39:49 -0700 | [diff] [blame] | 75 | }; |
| 76 | |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 77 | /* default input fence timeout, in ms */ |
Dhaval Patel | b9850c0 | 2017-08-07 22:55:47 -0700 | [diff] [blame] | 78 | #define SDE_CRTC_INPUT_FENCE_TIMEOUT 10000 |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 79 | |
Dhaval Patel | 4e57484 | 2016-08-23 15:11:37 -0700 | [diff] [blame] | 80 | /* |
| 81 | * The default input fence timeout is 2 seconds while max allowed |
| 82 | * range is 10 seconds. Any value above 10 seconds adds glitches beyond |
| 83 | * tolerance limit. |
| 84 | */ |
| 85 | #define SDE_CRTC_MAX_INPUT_FENCE_TIMEOUT 10000 |
| 86 | |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 87 | /* layer mixer index on sde_crtc */ |
| 88 | #define LEFT_MIXER 0 |
| 89 | #define RIGHT_MIXER 1 |
| 90 | |
Dhaval Patel | f9245d6 | 2017-03-28 16:24:00 -0700 | [diff] [blame] | 91 | #define MISR_BUFF_SIZE 256 |
| 92 | |
Lloyd Atkinson | 4f1c869 | 2016-09-14 14:04:25 -0400 | [diff] [blame] | 93 | static inline struct sde_kms *_sde_crtc_get_kms(struct drm_crtc *crtc) |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 94 | { |
Clarence Ip | 7f70ce4 | 2017-03-20 06:53:46 -0700 | [diff] [blame] | 95 | struct msm_drm_private *priv; |
| 96 | |
| 97 | if (!crtc || !crtc->dev || !crtc->dev->dev_private) { |
| 98 | SDE_ERROR("invalid crtc\n"); |
| 99 | return NULL; |
| 100 | } |
| 101 | priv = crtc->dev->dev_private; |
| 102 | if (!priv || !priv->kms) { |
| 103 | SDE_ERROR("invalid kms\n"); |
| 104 | return NULL; |
| 105 | } |
Abhijit Kulkarni | 40e3816 | 2016-06-26 22:12:09 -0400 | [diff] [blame] | 106 | |
Ben Chan | 78647cd | 2016-06-26 22:02:47 -0400 | [diff] [blame] | 107 | return to_sde_kms(priv->kms); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 108 | } |
| 109 | |
Dhaval Patel | f9245d6 | 2017-03-28 16:24:00 -0700 | [diff] [blame] | 110 | static inline int _sde_crtc_power_enable(struct sde_crtc *sde_crtc, bool enable) |
| 111 | { |
| 112 | struct drm_crtc *crtc; |
| 113 | struct msm_drm_private *priv; |
| 114 | struct sde_kms *sde_kms; |
| 115 | |
| 116 | if (!sde_crtc) { |
| 117 | SDE_ERROR("invalid sde crtc\n"); |
| 118 | return -EINVAL; |
| 119 | } |
| 120 | |
| 121 | crtc = &sde_crtc->base; |
| 122 | if (!crtc->dev || !crtc->dev->dev_private) { |
| 123 | SDE_ERROR("invalid drm device\n"); |
| 124 | return -EINVAL; |
| 125 | } |
| 126 | |
| 127 | priv = crtc->dev->dev_private; |
| 128 | if (!priv->kms) { |
| 129 | SDE_ERROR("invalid kms\n"); |
| 130 | return -EINVAL; |
| 131 | } |
| 132 | |
| 133 | sde_kms = to_sde_kms(priv->kms); |
| 134 | |
| 135 | return sde_power_resource_enable(&priv->phandle, sde_kms->core_client, |
| 136 | enable); |
| 137 | } |
| 138 | |
Alan Kwong | cdb2f28 | 2017-03-18 13:42:06 -0700 | [diff] [blame] | 139 | /** |
| 140 | * _sde_crtc_rp_to_crtc - get crtc from resource pool object |
| 141 | * @rp: Pointer to resource pool |
| 142 | * return: Pointer to drm crtc if success; null otherwise |
| 143 | */ |
| 144 | static struct drm_crtc *_sde_crtc_rp_to_crtc(struct sde_crtc_respool *rp) |
| 145 | { |
| 146 | if (!rp) |
| 147 | return NULL; |
| 148 | |
| 149 | return container_of(rp, struct sde_crtc_state, rp)->base.crtc; |
| 150 | } |
| 151 | |
| 152 | /** |
| 153 | * _sde_crtc_rp_reclaim - reclaim unused, or all if forced, resources in pool |
| 154 | * @rp: Pointer to resource pool |
| 155 | * @force: True to reclaim all resources; otherwise, reclaim only unused ones |
| 156 | * return: None |
| 157 | */ |
| 158 | static void _sde_crtc_rp_reclaim(struct sde_crtc_respool *rp, bool force) |
| 159 | { |
| 160 | struct sde_crtc_res *res, *next; |
| 161 | struct drm_crtc *crtc; |
| 162 | |
| 163 | crtc = _sde_crtc_rp_to_crtc(rp); |
| 164 | if (!crtc) { |
| 165 | SDE_ERROR("invalid crtc\n"); |
| 166 | return; |
| 167 | } |
| 168 | |
| 169 | SDE_DEBUG("crtc%d.%u %s\n", crtc->base.id, rp->sequence_id, |
| 170 | force ? "destroy" : "free_unused"); |
| 171 | |
| 172 | list_for_each_entry_safe(res, next, &rp->res_list, list) { |
| 173 | if (!force && !(res->flags & SDE_CRTC_RES_FLAG_FREE)) |
| 174 | continue; |
| 175 | SDE_DEBUG("crtc%d.%u reclaim res:0x%x/0x%llx/%pK/%d\n", |
| 176 | crtc->base.id, rp->sequence_id, |
| 177 | res->type, res->tag, res->val, |
| 178 | atomic_read(&res->refcount)); |
| 179 | list_del(&res->list); |
| 180 | if (res->ops.put) |
| 181 | res->ops.put(res->val); |
| 182 | kfree(res); |
| 183 | } |
| 184 | } |
| 185 | |
| 186 | /** |
| 187 | * _sde_crtc_rp_free_unused - free unused resource in pool |
| 188 | * @rp: Pointer to resource pool |
| 189 | * return: none |
| 190 | */ |
| 191 | static void _sde_crtc_rp_free_unused(struct sde_crtc_respool *rp) |
| 192 | { |
Alan Kwong | 310e9b0 | 2017-08-03 02:04:07 -0400 | [diff] [blame] | 193 | mutex_lock(rp->rp_lock); |
Alan Kwong | cdb2f28 | 2017-03-18 13:42:06 -0700 | [diff] [blame] | 194 | _sde_crtc_rp_reclaim(rp, false); |
Alan Kwong | 310e9b0 | 2017-08-03 02:04:07 -0400 | [diff] [blame] | 195 | mutex_unlock(rp->rp_lock); |
Alan Kwong | cdb2f28 | 2017-03-18 13:42:06 -0700 | [diff] [blame] | 196 | } |
| 197 | |
| 198 | /** |
| 199 | * _sde_crtc_rp_destroy - destroy resource pool |
| 200 | * @rp: Pointer to resource pool |
| 201 | * return: None |
| 202 | */ |
| 203 | static void _sde_crtc_rp_destroy(struct sde_crtc_respool *rp) |
| 204 | { |
Alan Kwong | 310e9b0 | 2017-08-03 02:04:07 -0400 | [diff] [blame] | 205 | mutex_lock(rp->rp_lock); |
| 206 | list_del_init(&rp->rp_list); |
Alan Kwong | cdb2f28 | 2017-03-18 13:42:06 -0700 | [diff] [blame] | 207 | _sde_crtc_rp_reclaim(rp, true); |
Alan Kwong | 310e9b0 | 2017-08-03 02:04:07 -0400 | [diff] [blame] | 208 | mutex_unlock(rp->rp_lock); |
Alan Kwong | cdb2f28 | 2017-03-18 13:42:06 -0700 | [diff] [blame] | 209 | } |
| 210 | |
| 211 | /** |
| 212 | * _sde_crtc_hw_blk_get - get callback for hardware block |
| 213 | * @val: Resource handle |
| 214 | * @type: Resource type |
| 215 | * @tag: Search tag for given resource |
| 216 | * return: Resource handle |
| 217 | */ |
| 218 | static void *_sde_crtc_hw_blk_get(void *val, u32 type, u64 tag) |
| 219 | { |
| 220 | SDE_DEBUG("res:%d/0x%llx/%pK\n", type, tag, val); |
| 221 | return sde_hw_blk_get(val, type, tag); |
| 222 | } |
| 223 | |
| 224 | /** |
| 225 | * _sde_crtc_hw_blk_put - put callback for hardware block |
| 226 | * @val: Resource handle |
| 227 | * return: None |
| 228 | */ |
| 229 | static void _sde_crtc_hw_blk_put(void *val) |
| 230 | { |
| 231 | SDE_DEBUG("res://%pK\n", val); |
| 232 | sde_hw_blk_put(val); |
| 233 | } |
| 234 | |
| 235 | /** |
| 236 | * _sde_crtc_rp_duplicate - duplicate resource pool and reset reference count |
| 237 | * @rp: Pointer to original resource pool |
| 238 | * @dup_rp: Pointer to duplicated resource pool |
| 239 | * return: None |
| 240 | */ |
| 241 | static void _sde_crtc_rp_duplicate(struct sde_crtc_respool *rp, |
| 242 | struct sde_crtc_respool *dup_rp) |
| 243 | { |
| 244 | struct sde_crtc_res *res, *dup_res; |
| 245 | struct drm_crtc *crtc; |
| 246 | |
Alan Kwong | 310e9b0 | 2017-08-03 02:04:07 -0400 | [diff] [blame] | 247 | if (!rp || !dup_rp || !rp->rp_head) { |
Alan Kwong | cdb2f28 | 2017-03-18 13:42:06 -0700 | [diff] [blame] | 248 | SDE_ERROR("invalid resource pool\n"); |
| 249 | return; |
| 250 | } |
| 251 | |
| 252 | crtc = _sde_crtc_rp_to_crtc(rp); |
| 253 | if (!crtc) { |
| 254 | SDE_ERROR("invalid crtc\n"); |
| 255 | return; |
| 256 | } |
| 257 | |
| 258 | SDE_DEBUG("crtc%d.%u duplicate\n", crtc->base.id, rp->sequence_id); |
| 259 | |
Alan Kwong | 310e9b0 | 2017-08-03 02:04:07 -0400 | [diff] [blame] | 260 | mutex_lock(rp->rp_lock); |
Alan Kwong | cdb2f28 | 2017-03-18 13:42:06 -0700 | [diff] [blame] | 261 | dup_rp->sequence_id = rp->sequence_id + 1; |
| 262 | INIT_LIST_HEAD(&dup_rp->res_list); |
| 263 | dup_rp->ops = rp->ops; |
| 264 | list_for_each_entry(res, &rp->res_list, list) { |
| 265 | dup_res = kzalloc(sizeof(struct sde_crtc_res), GFP_KERNEL); |
Alan Kwong | 310e9b0 | 2017-08-03 02:04:07 -0400 | [diff] [blame] | 266 | if (!dup_res) { |
| 267 | mutex_unlock(rp->rp_lock); |
Alan Kwong | cdb2f28 | 2017-03-18 13:42:06 -0700 | [diff] [blame] | 268 | return; |
Alan Kwong | 310e9b0 | 2017-08-03 02:04:07 -0400 | [diff] [blame] | 269 | } |
Alan Kwong | cdb2f28 | 2017-03-18 13:42:06 -0700 | [diff] [blame] | 270 | INIT_LIST_HEAD(&dup_res->list); |
| 271 | atomic_set(&dup_res->refcount, 0); |
| 272 | dup_res->type = res->type; |
| 273 | dup_res->tag = res->tag; |
| 274 | dup_res->val = res->val; |
| 275 | dup_res->ops = res->ops; |
| 276 | dup_res->flags = SDE_CRTC_RES_FLAG_FREE; |
| 277 | SDE_DEBUG("crtc%d.%u dup res:0x%x/0x%llx/%pK/%d\n", |
| 278 | crtc->base.id, dup_rp->sequence_id, |
| 279 | dup_res->type, dup_res->tag, dup_res->val, |
| 280 | atomic_read(&dup_res->refcount)); |
| 281 | list_add_tail(&dup_res->list, &dup_rp->res_list); |
| 282 | if (dup_res->ops.get) |
| 283 | dup_res->ops.get(dup_res->val, 0, -1); |
| 284 | } |
Alan Kwong | 310e9b0 | 2017-08-03 02:04:07 -0400 | [diff] [blame] | 285 | |
| 286 | dup_rp->rp_lock = rp->rp_lock; |
| 287 | dup_rp->rp_head = rp->rp_head; |
| 288 | INIT_LIST_HEAD(&dup_rp->rp_list); |
| 289 | list_add_tail(&dup_rp->rp_list, rp->rp_head); |
| 290 | mutex_unlock(rp->rp_lock); |
Alan Kwong | cdb2f28 | 2017-03-18 13:42:06 -0700 | [diff] [blame] | 291 | } |
| 292 | |
| 293 | /** |
| 294 | * _sde_crtc_rp_reset - reset resource pool after allocation |
| 295 | * @rp: Pointer to original resource pool |
Alan Kwong | 310e9b0 | 2017-08-03 02:04:07 -0400 | [diff] [blame] | 296 | * @rp_lock: Pointer to serialization resource pool lock |
| 297 | * @rp_head: Pointer to crtc resource pool head |
Alan Kwong | cdb2f28 | 2017-03-18 13:42:06 -0700 | [diff] [blame] | 298 | * return: None |
| 299 | */ |
Alan Kwong | 310e9b0 | 2017-08-03 02:04:07 -0400 | [diff] [blame] | 300 | static void _sde_crtc_rp_reset(struct sde_crtc_respool *rp, |
| 301 | struct mutex *rp_lock, struct list_head *rp_head) |
Alan Kwong | cdb2f28 | 2017-03-18 13:42:06 -0700 | [diff] [blame] | 302 | { |
Alan Kwong | 310e9b0 | 2017-08-03 02:04:07 -0400 | [diff] [blame] | 303 | if (!rp || !rp_lock || !rp_head) { |
Alan Kwong | cdb2f28 | 2017-03-18 13:42:06 -0700 | [diff] [blame] | 304 | SDE_ERROR("invalid resource pool\n"); |
| 305 | return; |
| 306 | } |
| 307 | |
Alan Kwong | 310e9b0 | 2017-08-03 02:04:07 -0400 | [diff] [blame] | 308 | mutex_lock(rp_lock); |
| 309 | rp->rp_lock = rp_lock; |
| 310 | rp->rp_head = rp_head; |
| 311 | INIT_LIST_HEAD(&rp->rp_list); |
Alan Kwong | cdb2f28 | 2017-03-18 13:42:06 -0700 | [diff] [blame] | 312 | rp->sequence_id = 0; |
| 313 | INIT_LIST_HEAD(&rp->res_list); |
| 314 | rp->ops.get = _sde_crtc_hw_blk_get; |
| 315 | rp->ops.put = _sde_crtc_hw_blk_put; |
Alan Kwong | 310e9b0 | 2017-08-03 02:04:07 -0400 | [diff] [blame] | 316 | list_add_tail(&rp->rp_list, rp->rp_head); |
| 317 | mutex_unlock(rp_lock); |
Alan Kwong | cdb2f28 | 2017-03-18 13:42:06 -0700 | [diff] [blame] | 318 | } |
| 319 | |
| 320 | /** |
Alan Kwong | 310e9b0 | 2017-08-03 02:04:07 -0400 | [diff] [blame] | 321 | * _sde_crtc_rp_add_no_lock - add given resource to resource pool without lock |
Alan Kwong | cdb2f28 | 2017-03-18 13:42:06 -0700 | [diff] [blame] | 322 | * @rp: Pointer to original resource pool |
| 323 | * @type: Resource type |
| 324 | * @tag: Search tag for given resource |
| 325 | * @val: Resource handle |
| 326 | * @ops: Resource callback operations |
| 327 | * return: 0 if success; error code otherwise |
| 328 | */ |
Alan Kwong | 310e9b0 | 2017-08-03 02:04:07 -0400 | [diff] [blame] | 329 | static int _sde_crtc_rp_add_no_lock(struct sde_crtc_respool *rp, u32 type, |
| 330 | u64 tag, void *val, struct sde_crtc_res_ops *ops) |
Alan Kwong | cdb2f28 | 2017-03-18 13:42:06 -0700 | [diff] [blame] | 331 | { |
| 332 | struct sde_crtc_res *res; |
| 333 | struct drm_crtc *crtc; |
| 334 | |
| 335 | if (!rp || !ops) { |
| 336 | SDE_ERROR("invalid resource pool/ops\n"); |
| 337 | return -EINVAL; |
| 338 | } |
| 339 | |
| 340 | crtc = _sde_crtc_rp_to_crtc(rp); |
| 341 | if (!crtc) { |
| 342 | SDE_ERROR("invalid crtc\n"); |
| 343 | return -EINVAL; |
| 344 | } |
| 345 | |
| 346 | list_for_each_entry(res, &rp->res_list, list) { |
| 347 | if (res->type != type || res->tag != tag) |
| 348 | continue; |
| 349 | SDE_ERROR("crtc%d.%u already exist res:0x%x/0x%llx/%pK/%d\n", |
| 350 | crtc->base.id, rp->sequence_id, |
| 351 | res->type, res->tag, res->val, |
| 352 | atomic_read(&res->refcount)); |
| 353 | return -EEXIST; |
| 354 | } |
| 355 | res = kzalloc(sizeof(struct sde_crtc_res), GFP_KERNEL); |
| 356 | if (!res) |
| 357 | return -ENOMEM; |
| 358 | INIT_LIST_HEAD(&res->list); |
| 359 | atomic_set(&res->refcount, 1); |
| 360 | res->type = type; |
| 361 | res->tag = tag; |
| 362 | res->val = val; |
| 363 | res->ops = *ops; |
| 364 | list_add_tail(&res->list, &rp->res_list); |
| 365 | SDE_DEBUG("crtc%d.%u added res:0x%x/0x%llx\n", |
| 366 | crtc->base.id, rp->sequence_id, type, tag); |
| 367 | return 0; |
| 368 | } |
| 369 | |
| 370 | /** |
Alan Kwong | 310e9b0 | 2017-08-03 02:04:07 -0400 | [diff] [blame] | 371 | * _sde_crtc_rp_add - add given resource to resource pool |
| 372 | * @rp: Pointer to original resource pool |
| 373 | * @type: Resource type |
| 374 | * @tag: Search tag for given resource |
| 375 | * @val: Resource handle |
| 376 | * @ops: Resource callback operations |
| 377 | * return: 0 if success; error code otherwise |
| 378 | */ |
| 379 | static int _sde_crtc_rp_add(struct sde_crtc_respool *rp, u32 type, u64 tag, |
| 380 | void *val, struct sde_crtc_res_ops *ops) |
| 381 | { |
| 382 | int rc; |
| 383 | |
| 384 | if (!rp) { |
| 385 | SDE_ERROR("invalid resource pool\n"); |
| 386 | return -EINVAL; |
| 387 | } |
| 388 | |
| 389 | mutex_lock(rp->rp_lock); |
| 390 | rc = _sde_crtc_rp_add_no_lock(rp, type, tag, val, ops); |
| 391 | mutex_unlock(rp->rp_lock); |
| 392 | return rc; |
| 393 | } |
| 394 | |
| 395 | /** |
Alan Kwong | cdb2f28 | 2017-03-18 13:42:06 -0700 | [diff] [blame] | 396 | * _sde_crtc_rp_get - lookup the resource from given resource pool and obtain |
| 397 | * if available; otherwise, obtain resource from global pool |
| 398 | * @rp: Pointer to original resource pool |
| 399 | * @type: Resource type |
| 400 | * @tag: Search tag for given resource |
| 401 | * return: Resource handle if success; pointer error or null otherwise |
| 402 | */ |
| 403 | static void *_sde_crtc_rp_get(struct sde_crtc_respool *rp, u32 type, u64 tag) |
| 404 | { |
Alan Kwong | 310e9b0 | 2017-08-03 02:04:07 -0400 | [diff] [blame] | 405 | struct sde_crtc_respool *old_rp; |
Alan Kwong | cdb2f28 | 2017-03-18 13:42:06 -0700 | [diff] [blame] | 406 | struct sde_crtc_res *res; |
| 407 | void *val = NULL; |
| 408 | int rc; |
| 409 | struct drm_crtc *crtc; |
| 410 | |
| 411 | if (!rp) { |
| 412 | SDE_ERROR("invalid resource pool\n"); |
| 413 | return NULL; |
| 414 | } |
| 415 | |
| 416 | crtc = _sde_crtc_rp_to_crtc(rp); |
| 417 | if (!crtc) { |
| 418 | SDE_ERROR("invalid crtc\n"); |
| 419 | return NULL; |
| 420 | } |
| 421 | |
Alan Kwong | 310e9b0 | 2017-08-03 02:04:07 -0400 | [diff] [blame] | 422 | mutex_lock(rp->rp_lock); |
Alan Kwong | cdb2f28 | 2017-03-18 13:42:06 -0700 | [diff] [blame] | 423 | list_for_each_entry(res, &rp->res_list, list) { |
| 424 | if (res->type != type || res->tag != tag) |
| 425 | continue; |
| 426 | SDE_DEBUG("crtc%d.%u found res:0x%x/0x%llx/%pK/%d\n", |
| 427 | crtc->base.id, rp->sequence_id, |
| 428 | res->type, res->tag, res->val, |
| 429 | atomic_read(&res->refcount)); |
| 430 | atomic_inc(&res->refcount); |
| 431 | res->flags &= ~SDE_CRTC_RES_FLAG_FREE; |
Alan Kwong | 310e9b0 | 2017-08-03 02:04:07 -0400 | [diff] [blame] | 432 | mutex_unlock(rp->rp_lock); |
Alan Kwong | cdb2f28 | 2017-03-18 13:42:06 -0700 | [diff] [blame] | 433 | return res->val; |
| 434 | } |
| 435 | list_for_each_entry(res, &rp->res_list, list) { |
| 436 | if (res->type != type || !(res->flags & SDE_CRTC_RES_FLAG_FREE)) |
| 437 | continue; |
| 438 | SDE_DEBUG("crtc%d.%u retag res:0x%x/0x%llx/%pK/%d\n", |
| 439 | crtc->base.id, rp->sequence_id, |
| 440 | res->type, res->tag, res->val, |
| 441 | atomic_read(&res->refcount)); |
| 442 | atomic_inc(&res->refcount); |
| 443 | res->tag = tag; |
| 444 | res->flags &= ~SDE_CRTC_RES_FLAG_FREE; |
Alan Kwong | 310e9b0 | 2017-08-03 02:04:07 -0400 | [diff] [blame] | 445 | mutex_unlock(rp->rp_lock); |
Alan Kwong | cdb2f28 | 2017-03-18 13:42:06 -0700 | [diff] [blame] | 446 | return res->val; |
| 447 | } |
Alan Kwong | 310e9b0 | 2017-08-03 02:04:07 -0400 | [diff] [blame] | 448 | /* not in this rp, try to grab from global pool */ |
Alan Kwong | cdb2f28 | 2017-03-18 13:42:06 -0700 | [diff] [blame] | 449 | if (rp->ops.get) |
| 450 | val = rp->ops.get(NULL, type, -1); |
Alan Kwong | 310e9b0 | 2017-08-03 02:04:07 -0400 | [diff] [blame] | 451 | if (!IS_ERR_OR_NULL(val)) |
| 452 | goto add_res; |
| 453 | /* |
| 454 | * Search older resource pools for hw blk with matching type, |
| 455 | * necessary when resource is being used by this object, |
| 456 | * but in previous states not yet cleaned up. |
| 457 | * |
| 458 | * This enables searching of all resources currently owned |
| 459 | * by this crtc even though the resource might not be used |
| 460 | * in the current atomic state. This allows those resources |
| 461 | * to be re-acquired by the new atomic state immediately |
| 462 | * without waiting for the resources to be fully released. |
| 463 | */ |
| 464 | else if (IS_ERR_OR_NULL(val) && (type < SDE_HW_BLK_MAX)) { |
| 465 | list_for_each_entry(old_rp, rp->rp_head, rp_list) { |
| 466 | if (old_rp == rp) |
| 467 | continue; |
| 468 | |
| 469 | list_for_each_entry(res, &old_rp->res_list, list) { |
| 470 | if (res->type != type) |
| 471 | continue; |
| 472 | SDE_DEBUG( |
| 473 | "crtc%d.%u found res:0x%x//%pK/ in crtc%d.%d\n", |
| 474 | crtc->base.id, |
| 475 | rp->sequence_id, |
| 476 | res->type, res->val, |
| 477 | crtc->base.id, |
| 478 | old_rp->sequence_id); |
| 479 | SDE_EVT32_VERBOSE(crtc->base.id, |
| 480 | rp->sequence_id, |
| 481 | res->type, res->val, |
| 482 | crtc->base.id, |
| 483 | old_rp->sequence_id); |
| 484 | if (res->ops.get) |
| 485 | res->ops.get(res->val, 0, -1); |
| 486 | val = res->val; |
| 487 | break; |
| 488 | } |
| 489 | |
| 490 | if (!IS_ERR_OR_NULL(val)) |
| 491 | break; |
| 492 | } |
| 493 | } |
Alan Kwong | cdb2f28 | 2017-03-18 13:42:06 -0700 | [diff] [blame] | 494 | if (IS_ERR_OR_NULL(val)) { |
Alan Kwong | 42e3505 | 2017-05-05 06:52:51 -0700 | [diff] [blame] | 495 | SDE_DEBUG("crtc%d.%u failed to get res:0x%x//\n", |
Alan Kwong | cdb2f28 | 2017-03-18 13:42:06 -0700 | [diff] [blame] | 496 | crtc->base.id, rp->sequence_id, type); |
Alan Kwong | 310e9b0 | 2017-08-03 02:04:07 -0400 | [diff] [blame] | 497 | mutex_unlock(rp->rp_lock); |
Alan Kwong | cdb2f28 | 2017-03-18 13:42:06 -0700 | [diff] [blame] | 498 | return NULL; |
| 499 | } |
Alan Kwong | 310e9b0 | 2017-08-03 02:04:07 -0400 | [diff] [blame] | 500 | add_res: |
| 501 | rc = _sde_crtc_rp_add_no_lock(rp, type, tag, val, &rp->ops); |
Alan Kwong | cdb2f28 | 2017-03-18 13:42:06 -0700 | [diff] [blame] | 502 | if (rc) { |
| 503 | SDE_ERROR("crtc%d.%u failed to add res:0x%x/0x%llx\n", |
| 504 | crtc->base.id, rp->sequence_id, type, tag); |
| 505 | if (rp->ops.put) |
| 506 | rp->ops.put(val); |
| 507 | val = NULL; |
| 508 | } |
Alan Kwong | 310e9b0 | 2017-08-03 02:04:07 -0400 | [diff] [blame] | 509 | mutex_unlock(rp->rp_lock); |
Alan Kwong | cdb2f28 | 2017-03-18 13:42:06 -0700 | [diff] [blame] | 510 | return val; |
| 511 | } |
| 512 | |
| 513 | /** |
| 514 | * _sde_crtc_rp_put - return given resource to resource pool |
| 515 | * @rp: Pointer to original resource pool |
| 516 | * @type: Resource type |
| 517 | * @tag: Search tag for given resource |
| 518 | * return: None |
| 519 | */ |
| 520 | static void _sde_crtc_rp_put(struct sde_crtc_respool *rp, u32 type, u64 tag) |
| 521 | { |
| 522 | struct sde_crtc_res *res, *next; |
| 523 | struct drm_crtc *crtc; |
| 524 | |
| 525 | if (!rp) { |
| 526 | SDE_ERROR("invalid resource pool\n"); |
| 527 | return; |
| 528 | } |
| 529 | |
| 530 | crtc = _sde_crtc_rp_to_crtc(rp); |
| 531 | if (!crtc) { |
| 532 | SDE_ERROR("invalid crtc\n"); |
| 533 | return; |
| 534 | } |
| 535 | |
Alan Kwong | 310e9b0 | 2017-08-03 02:04:07 -0400 | [diff] [blame] | 536 | mutex_lock(rp->rp_lock); |
Alan Kwong | cdb2f28 | 2017-03-18 13:42:06 -0700 | [diff] [blame] | 537 | list_for_each_entry_safe(res, next, &rp->res_list, list) { |
| 538 | if (res->type != type || res->tag != tag) |
| 539 | continue; |
| 540 | SDE_DEBUG("crtc%d.%u found res:0x%x/0x%llx/%pK/%d\n", |
| 541 | crtc->base.id, rp->sequence_id, |
| 542 | res->type, res->tag, res->val, |
| 543 | atomic_read(&res->refcount)); |
| 544 | if (res->flags & SDE_CRTC_RES_FLAG_FREE) |
| 545 | SDE_ERROR( |
| 546 | "crtc%d.%u already free res:0x%x/0x%llx/%pK/%d\n", |
| 547 | crtc->base.id, rp->sequence_id, |
| 548 | res->type, res->tag, res->val, |
| 549 | atomic_read(&res->refcount)); |
| 550 | else if (atomic_dec_return(&res->refcount) == 0) |
| 551 | res->flags |= SDE_CRTC_RES_FLAG_FREE; |
| 552 | |
Alan Kwong | 310e9b0 | 2017-08-03 02:04:07 -0400 | [diff] [blame] | 553 | mutex_unlock(rp->rp_lock); |
Alan Kwong | cdb2f28 | 2017-03-18 13:42:06 -0700 | [diff] [blame] | 554 | return; |
| 555 | } |
| 556 | SDE_ERROR("crtc%d.%u not found res:0x%x/0x%llx\n", |
| 557 | crtc->base.id, rp->sequence_id, type, tag); |
Alan Kwong | 310e9b0 | 2017-08-03 02:04:07 -0400 | [diff] [blame] | 558 | mutex_unlock(rp->rp_lock); |
Alan Kwong | cdb2f28 | 2017-03-18 13:42:06 -0700 | [diff] [blame] | 559 | } |
| 560 | |
| 561 | int sde_crtc_res_add(struct drm_crtc_state *state, u32 type, u64 tag, |
| 562 | void *val, struct sde_crtc_res_ops *ops) |
| 563 | { |
| 564 | struct sde_crtc_respool *rp; |
| 565 | |
| 566 | if (!state) { |
| 567 | SDE_ERROR("invalid parameters\n"); |
| 568 | return -EINVAL; |
| 569 | } |
| 570 | |
| 571 | rp = &to_sde_crtc_state(state)->rp; |
| 572 | return _sde_crtc_rp_add(rp, type, tag, val, ops); |
| 573 | } |
| 574 | |
| 575 | void *sde_crtc_res_get(struct drm_crtc_state *state, u32 type, u64 tag) |
| 576 | { |
| 577 | struct sde_crtc_respool *rp; |
| 578 | void *val; |
| 579 | |
| 580 | if (!state) { |
| 581 | SDE_ERROR("invalid parameters\n"); |
| 582 | return NULL; |
| 583 | } |
| 584 | |
| 585 | rp = &to_sde_crtc_state(state)->rp; |
| 586 | val = _sde_crtc_rp_get(rp, type, tag); |
| 587 | if (IS_ERR(val)) { |
| 588 | SDE_ERROR("failed to get res type:0x%x:0x%llx\n", |
| 589 | type, tag); |
| 590 | return NULL; |
| 591 | } |
| 592 | |
| 593 | return val; |
| 594 | } |
| 595 | |
| 596 | void sde_crtc_res_put(struct drm_crtc_state *state, u32 type, u64 tag) |
| 597 | { |
| 598 | struct sde_crtc_respool *rp; |
| 599 | |
| 600 | if (!state) { |
| 601 | SDE_ERROR("invalid parameters\n"); |
| 602 | return; |
| 603 | } |
| 604 | |
| 605 | rp = &to_sde_crtc_state(state)->rp; |
| 606 | _sde_crtc_rp_put(rp, type, tag); |
| 607 | } |
| 608 | |
Clarence Ip | a18d483 | 2017-03-13 12:35:44 -0700 | [diff] [blame] | 609 | static void _sde_crtc_deinit_events(struct sde_crtc *sde_crtc) |
| 610 | { |
| 611 | if (!sde_crtc) |
| 612 | return; |
Clarence Ip | a18d483 | 2017-03-13 12:35:44 -0700 | [diff] [blame] | 613 | } |
| 614 | |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 615 | static void sde_crtc_destroy(struct drm_crtc *crtc) |
| 616 | { |
| 617 | struct sde_crtc *sde_crtc = to_sde_crtc(crtc); |
| 618 | |
Lloyd Atkinson | 4f1c869 | 2016-09-14 14:04:25 -0400 | [diff] [blame] | 619 | SDE_DEBUG("\n"); |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 620 | |
| 621 | if (!crtc) |
| 622 | return; |
| 623 | |
Dhaval Patel | e4a5dda | 2016-10-13 19:29:30 -0700 | [diff] [blame] | 624 | if (sde_crtc->blob_info) |
| 625 | drm_property_unreference_blob(sde_crtc->blob_info); |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 626 | msm_property_destroy(&sde_crtc->property_info); |
Gopikrishnaiah Anandan | e0e5e0c | 2016-05-25 11:05:33 -0700 | [diff] [blame] | 627 | sde_cp_crtc_destroy_properties(crtc); |
Dhaval Patel | 3fbe6bf | 2016-10-20 20:00:41 -0700 | [diff] [blame] | 628 | |
Clarence Ip | 24f8066 | 2016-06-13 19:05:32 -0400 | [diff] [blame] | 629 | sde_fence_deinit(&sde_crtc->output_fence); |
Clarence Ip | a18d483 | 2017-03-13 12:35:44 -0700 | [diff] [blame] | 630 | _sde_crtc_deinit_events(sde_crtc); |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 631 | |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 632 | drm_crtc_cleanup(crtc); |
Clarence Ip | 7f70ce4 | 2017-03-20 06:53:46 -0700 | [diff] [blame] | 633 | mutex_destroy(&sde_crtc->crtc_lock); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 634 | kfree(sde_crtc); |
| 635 | } |
| 636 | |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 637 | static bool sde_crtc_mode_fixup(struct drm_crtc *crtc, |
| 638 | const struct drm_display_mode *mode, |
| 639 | struct drm_display_mode *adjusted_mode) |
| 640 | { |
Lloyd Atkinson | 4f1c869 | 2016-09-14 14:04:25 -0400 | [diff] [blame] | 641 | SDE_DEBUG("\n"); |
Lloyd Atkinson | af7952d | 2016-06-26 22:41:26 -0400 | [diff] [blame] | 642 | |
Lloyd Atkinson | 4f1c869 | 2016-09-14 14:04:25 -0400 | [diff] [blame] | 643 | if (msm_is_mode_seamless(adjusted_mode) && |
| 644 | (!crtc->enabled || crtc->state->active_changed)) { |
| 645 | SDE_ERROR("crtc state prevents seamless transition\n"); |
| 646 | return false; |
Lloyd Atkinson | af7952d | 2016-06-26 22:41:26 -0400 | [diff] [blame] | 647 | } |
| 648 | |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 649 | return true; |
| 650 | } |
| 651 | |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 652 | static void _sde_crtc_setup_blend_cfg(struct sde_crtc_mixer *mixer, |
| 653 | struct sde_plane_state *pstate, struct sde_format *format) |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 654 | { |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 655 | uint32_t blend_op, fg_alpha, bg_alpha; |
| 656 | uint32_t blend_type; |
Dhaval Patel | 44f1247 | 2016-08-29 12:19:47 -0700 | [diff] [blame] | 657 | struct sde_hw_mixer *lm = mixer->hw_lm; |
| 658 | |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 659 | /* default to opaque blending */ |
| 660 | fg_alpha = sde_plane_get_property(pstate, PLANE_PROP_ALPHA); |
| 661 | bg_alpha = 0xFF - fg_alpha; |
| 662 | blend_op = SDE_BLEND_FG_ALPHA_FG_CONST | SDE_BLEND_BG_ALPHA_BG_CONST; |
| 663 | blend_type = sde_plane_get_property(pstate, PLANE_PROP_BLEND_OP); |
Dhaval Patel | 44f1247 | 2016-08-29 12:19:47 -0700 | [diff] [blame] | 664 | |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 665 | SDE_DEBUG("blend type:0x%x blend alpha:0x%x\n", blend_type, fg_alpha); |
| 666 | |
| 667 | switch (blend_type) { |
| 668 | |
| 669 | case SDE_DRM_BLEND_OP_OPAQUE: |
| 670 | blend_op = SDE_BLEND_FG_ALPHA_FG_CONST | |
| 671 | SDE_BLEND_BG_ALPHA_BG_CONST; |
| 672 | break; |
| 673 | |
| 674 | case SDE_DRM_BLEND_OP_PREMULTIPLIED: |
| 675 | if (format->alpha_enable) { |
| 676 | blend_op = SDE_BLEND_FG_ALPHA_FG_CONST | |
| 677 | SDE_BLEND_BG_ALPHA_FG_PIXEL; |
| 678 | if (fg_alpha != 0xff) { |
| 679 | bg_alpha = fg_alpha; |
| 680 | blend_op |= SDE_BLEND_BG_MOD_ALPHA | |
| 681 | SDE_BLEND_BG_INV_MOD_ALPHA; |
| 682 | } else { |
| 683 | blend_op |= SDE_BLEND_BG_INV_ALPHA; |
| 684 | } |
| 685 | } |
| 686 | break; |
| 687 | |
| 688 | case SDE_DRM_BLEND_OP_COVERAGE: |
| 689 | if (format->alpha_enable) { |
| 690 | blend_op = SDE_BLEND_FG_ALPHA_FG_PIXEL | |
| 691 | SDE_BLEND_BG_ALPHA_FG_PIXEL; |
| 692 | if (fg_alpha != 0xff) { |
| 693 | bg_alpha = fg_alpha; |
| 694 | blend_op |= SDE_BLEND_FG_MOD_ALPHA | |
| 695 | SDE_BLEND_FG_INV_MOD_ALPHA | |
| 696 | SDE_BLEND_BG_MOD_ALPHA | |
| 697 | SDE_BLEND_BG_INV_MOD_ALPHA; |
| 698 | } else { |
| 699 | blend_op |= SDE_BLEND_BG_INV_ALPHA; |
| 700 | } |
| 701 | } |
| 702 | break; |
| 703 | default: |
| 704 | /* do nothing */ |
| 705 | break; |
Clarence Ip | d9f9fa6 | 2016-09-09 13:42:32 -0400 | [diff] [blame] | 706 | } |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 707 | |
| 708 | lm->ops.setup_blend_config(lm, pstate->stage, fg_alpha, |
| 709 | bg_alpha, blend_op); |
Dhaval Patel | 6c66662 | 2017-03-21 23:02:59 -0700 | [diff] [blame] | 710 | SDE_DEBUG( |
| 711 | "format: %4.4s, alpha_enable %u fg alpha:0x%x bg alpha:0x%x blend_op:0x%x\n", |
| 712 | (char *) &format->base.pixel_format, |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 713 | format->alpha_enable, fg_alpha, bg_alpha, blend_op); |
| 714 | } |
| 715 | |
Veera Sundaram Sankaran | 3171ff8 | 2017-01-04 14:34:47 -0800 | [diff] [blame] | 716 | static void _sde_crtc_setup_dim_layer_cfg(struct drm_crtc *crtc, |
| 717 | struct sde_crtc *sde_crtc, struct sde_crtc_mixer *mixer, |
| 718 | struct sde_hw_dim_layer *dim_layer) |
| 719 | { |
Lloyd Atkinson | a9d7e75 | 2017-01-17 16:31:43 -0500 | [diff] [blame] | 720 | struct sde_crtc_state *cstate; |
Veera Sundaram Sankaran | 3171ff8 | 2017-01-04 14:34:47 -0800 | [diff] [blame] | 721 | struct sde_hw_mixer *lm; |
Veera Sundaram Sankaran | 3171ff8 | 2017-01-04 14:34:47 -0800 | [diff] [blame] | 722 | struct sde_hw_dim_layer split_dim_layer; |
Veera Sundaram Sankaran | 3171ff8 | 2017-01-04 14:34:47 -0800 | [diff] [blame] | 723 | int i; |
| 724 | |
| 725 | if (!dim_layer->rect.w || !dim_layer->rect.h) { |
Veera Sundaram Sankaran | 2cb064f | 2017-05-05 14:12:17 -0700 | [diff] [blame] | 726 | SDE_DEBUG("empty dim_layer\n"); |
Veera Sundaram Sankaran | 3171ff8 | 2017-01-04 14:34:47 -0800 | [diff] [blame] | 727 | return; |
| 728 | } |
| 729 | |
Lloyd Atkinson | a9d7e75 | 2017-01-17 16:31:43 -0500 | [diff] [blame] | 730 | cstate = to_sde_crtc_state(crtc->state); |
Veera Sundaram Sankaran | 3171ff8 | 2017-01-04 14:34:47 -0800 | [diff] [blame] | 731 | |
Veera Sundaram Sankaran | 2cb064f | 2017-05-05 14:12:17 -0700 | [diff] [blame] | 732 | SDE_DEBUG("dim_layer - flags:%d, stage:%d\n", |
| 733 | dim_layer->flags, dim_layer->stage); |
| 734 | |
Veera Sundaram Sankaran | 3171ff8 | 2017-01-04 14:34:47 -0800 | [diff] [blame] | 735 | split_dim_layer.stage = dim_layer->stage; |
| 736 | split_dim_layer.color_fill = dim_layer->color_fill; |
| 737 | |
| 738 | /* |
| 739 | * traverse through the layer mixers attached to crtc and find the |
| 740 | * intersecting dim layer rect in each LM and program accordingly. |
| 741 | */ |
| 742 | for (i = 0; i < sde_crtc->num_mixers; i++) { |
| 743 | split_dim_layer.flags = dim_layer->flags; |
Veera Sundaram Sankaran | 3171ff8 | 2017-01-04 14:34:47 -0800 | [diff] [blame] | 744 | |
Lloyd Atkinson | a9d7e75 | 2017-01-17 16:31:43 -0500 | [diff] [blame] | 745 | sde_kms_rect_intersect(&cstate->lm_bounds[i], &dim_layer->rect, |
Lloyd Atkinson | e0e11e2 | 2017-01-17 12:08:48 -0500 | [diff] [blame] | 746 | &split_dim_layer.rect); |
Lloyd Atkinson | a9d7e75 | 2017-01-17 16:31:43 -0500 | [diff] [blame] | 747 | if (sde_kms_rect_is_null(&split_dim_layer.rect)) { |
Veera Sundaram Sankaran | 3171ff8 | 2017-01-04 14:34:47 -0800 | [diff] [blame] | 748 | /* |
| 749 | * no extra programming required for non-intersecting |
| 750 | * layer mixers with INCLUSIVE dim layer |
| 751 | */ |
Lloyd Atkinson | a9d7e75 | 2017-01-17 16:31:43 -0500 | [diff] [blame] | 752 | if (split_dim_layer.flags & SDE_DRM_DIM_LAYER_INCLUSIVE) |
Veera Sundaram Sankaran | 3171ff8 | 2017-01-04 14:34:47 -0800 | [diff] [blame] | 753 | continue; |
| 754 | |
| 755 | /* |
| 756 | * program the other non-intersecting layer mixers with |
| 757 | * INCLUSIVE dim layer of full size for uniformity |
| 758 | * with EXCLUSIVE dim layer config. |
| 759 | */ |
| 760 | split_dim_layer.flags &= ~SDE_DRM_DIM_LAYER_EXCLUSIVE; |
| 761 | split_dim_layer.flags |= SDE_DRM_DIM_LAYER_INCLUSIVE; |
Lloyd Atkinson | a9d7e75 | 2017-01-17 16:31:43 -0500 | [diff] [blame] | 762 | memcpy(&split_dim_layer.rect, &cstate->lm_bounds[i], |
| 763 | sizeof(split_dim_layer.rect)); |
Veera Sundaram Sankaran | 3171ff8 | 2017-01-04 14:34:47 -0800 | [diff] [blame] | 764 | |
| 765 | } else { |
Lloyd Atkinson | a9d7e75 | 2017-01-17 16:31:43 -0500 | [diff] [blame] | 766 | split_dim_layer.rect.x = |
| 767 | split_dim_layer.rect.x - |
Veera Sundaram Sankaran | 2cb064f | 2017-05-05 14:12:17 -0700 | [diff] [blame] | 768 | cstate->lm_bounds[i].x; |
Veera Sundaram Sankaran | 3171ff8 | 2017-01-04 14:34:47 -0800 | [diff] [blame] | 769 | } |
| 770 | |
Veera Sundaram Sankaran | 2cb064f | 2017-05-05 14:12:17 -0700 | [diff] [blame] | 771 | SDE_DEBUG("split_dim_layer - LM:%d, rect:{%d,%d,%d,%d}}\n", |
| 772 | i, split_dim_layer.rect.x, split_dim_layer.rect.y, |
| 773 | split_dim_layer.rect.w, split_dim_layer.rect.h); |
| 774 | |
Veera Sundaram Sankaran | 3171ff8 | 2017-01-04 14:34:47 -0800 | [diff] [blame] | 775 | lm = mixer[i].hw_lm; |
| 776 | mixer[i].mixer_op_mode |= 1 << split_dim_layer.stage; |
| 777 | lm->ops.setup_dim_layer(lm, &split_dim_layer); |
| 778 | } |
| 779 | } |
| 780 | |
Lloyd Atkinson | 8ba4703 | 2017-03-22 17:13:32 -0400 | [diff] [blame] | 781 | void sde_crtc_get_crtc_roi(struct drm_crtc_state *state, |
| 782 | const struct sde_rect **crtc_roi) |
| 783 | { |
| 784 | struct sde_crtc_state *crtc_state; |
| 785 | |
| 786 | if (!state || !crtc_roi) |
| 787 | return; |
| 788 | |
| 789 | crtc_state = to_sde_crtc_state(state); |
| 790 | *crtc_roi = &crtc_state->crtc_roi; |
| 791 | } |
| 792 | |
| 793 | static int _sde_crtc_set_roi_v1(struct drm_crtc_state *state, |
| 794 | void *usr_ptr) |
| 795 | { |
| 796 | struct drm_crtc *crtc; |
| 797 | struct sde_crtc_state *cstate; |
| 798 | struct sde_drm_roi_v1 roi_v1; |
| 799 | int i; |
| 800 | |
| 801 | if (!state) { |
| 802 | SDE_ERROR("invalid args\n"); |
| 803 | return -EINVAL; |
| 804 | } |
| 805 | |
| 806 | cstate = to_sde_crtc_state(state); |
| 807 | crtc = cstate->base.crtc; |
| 808 | |
| 809 | memset(&cstate->user_roi_list, 0, sizeof(cstate->user_roi_list)); |
| 810 | |
| 811 | if (!usr_ptr) { |
| 812 | SDE_DEBUG("crtc%d: rois cleared\n", DRMID(crtc)); |
| 813 | return 0; |
| 814 | } |
| 815 | |
| 816 | if (copy_from_user(&roi_v1, usr_ptr, sizeof(roi_v1))) { |
| 817 | SDE_ERROR("crtc%d: failed to copy roi_v1 data\n", DRMID(crtc)); |
| 818 | return -EINVAL; |
| 819 | } |
| 820 | |
| 821 | SDE_DEBUG("crtc%d: num_rects %d\n", DRMID(crtc), roi_v1.num_rects); |
| 822 | |
| 823 | if (roi_v1.num_rects == 0) { |
| 824 | SDE_DEBUG("crtc%d: rois cleared\n", DRMID(crtc)); |
| 825 | return 0; |
| 826 | } |
| 827 | |
| 828 | if (roi_v1.num_rects > SDE_MAX_ROI_V1) { |
| 829 | SDE_ERROR("crtc%d: too many rects specified: %d\n", DRMID(crtc), |
| 830 | roi_v1.num_rects); |
| 831 | return -EINVAL; |
| 832 | } |
| 833 | |
| 834 | cstate->user_roi_list.num_rects = roi_v1.num_rects; |
| 835 | for (i = 0; i < roi_v1.num_rects; ++i) { |
| 836 | cstate->user_roi_list.roi[i] = roi_v1.roi[i]; |
| 837 | SDE_DEBUG("crtc%d: roi%d: roi (%d,%d) (%d,%d)\n", |
| 838 | DRMID(crtc), i, |
| 839 | cstate->user_roi_list.roi[i].x1, |
| 840 | cstate->user_roi_list.roi[i].y1, |
| 841 | cstate->user_roi_list.roi[i].x2, |
| 842 | cstate->user_roi_list.roi[i].y2); |
| 843 | } |
| 844 | |
| 845 | return 0; |
| 846 | } |
| 847 | |
Ingrid Gallardo | 8353222 | 2017-06-02 16:48:51 -0700 | [diff] [blame] | 848 | static bool _sde_crtc_setup_is_3dmux_dsc(struct drm_crtc_state *state) |
| 849 | { |
| 850 | int i; |
| 851 | struct sde_crtc_state *cstate; |
| 852 | bool is_3dmux_dsc = false; |
| 853 | |
| 854 | cstate = to_sde_crtc_state(state); |
| 855 | |
| 856 | for (i = 0; i < cstate->num_connectors; i++) { |
| 857 | struct drm_connector *conn = cstate->connectors[i]; |
| 858 | |
| 859 | if (sde_connector_get_topology_name(conn) == |
| 860 | SDE_RM_TOPOLOGY_DUALPIPE_3DMERGE_DSC) |
| 861 | is_3dmux_dsc = true; |
| 862 | } |
| 863 | |
| 864 | return is_3dmux_dsc; |
| 865 | } |
| 866 | |
Lloyd Atkinson | 8ba4703 | 2017-03-22 17:13:32 -0400 | [diff] [blame] | 867 | static int _sde_crtc_set_crtc_roi(struct drm_crtc *crtc, |
| 868 | struct drm_crtc_state *state) |
| 869 | { |
| 870 | struct drm_connector *conn; |
| 871 | struct drm_connector_state *conn_state; |
| 872 | struct sde_crtc *sde_crtc; |
| 873 | struct sde_crtc_state *crtc_state; |
| 874 | struct sde_rect *crtc_roi; |
Lloyd Atkinson | 8ba4703 | 2017-03-22 17:13:32 -0400 | [diff] [blame] | 875 | int i, num_attached_conns = 0; |
| 876 | |
| 877 | if (!crtc || !state) |
| 878 | return -EINVAL; |
| 879 | |
| 880 | sde_crtc = to_sde_crtc(crtc); |
| 881 | crtc_state = to_sde_crtc_state(state); |
| 882 | crtc_roi = &crtc_state->crtc_roi; |
| 883 | |
Lloyd Atkinson | 8ba4703 | 2017-03-22 17:13:32 -0400 | [diff] [blame] | 884 | for_each_connector_in_state(state->state, conn, conn_state, i) { |
| 885 | struct sde_connector_state *sde_conn_state; |
| 886 | |
| 887 | if (!conn_state || conn_state->crtc != crtc) |
| 888 | continue; |
| 889 | |
| 890 | if (num_attached_conns) { |
| 891 | SDE_ERROR( |
| 892 | "crtc%d: unsupported: roi on crtc w/ >1 connectors\n", |
| 893 | DRMID(crtc)); |
| 894 | return -EINVAL; |
| 895 | } |
| 896 | ++num_attached_conns; |
| 897 | |
| 898 | sde_conn_state = to_sde_connector_state(conn_state); |
| 899 | |
Ingrid Gallardo | 8353222 | 2017-06-02 16:48:51 -0700 | [diff] [blame] | 900 | /* |
| 901 | * current driver only supports same connector and crtc size, |
| 902 | * but if support for different sizes is added, driver needs |
| 903 | * to check the connector roi here to make sure is full screen |
| 904 | * for dsc 3d-mux topology that doesn't support partial update. |
| 905 | */ |
Lloyd Atkinson | 8ba4703 | 2017-03-22 17:13:32 -0400 | [diff] [blame] | 906 | if (memcmp(&sde_conn_state->rois, &crtc_state->user_roi_list, |
| 907 | sizeof(crtc_state->user_roi_list))) { |
| 908 | SDE_ERROR("%s: crtc -> conn roi scaling unsupported\n", |
| 909 | sde_crtc->name); |
| 910 | return -EINVAL; |
| 911 | } |
| 912 | } |
| 913 | |
Lloyd Atkinson | c2baf41 | 2017-04-19 17:53:09 -0400 | [diff] [blame] | 914 | sde_kms_rect_merge_rectangles(&crtc_state->user_roi_list, crtc_roi); |
Lloyd Atkinson | 8ba4703 | 2017-03-22 17:13:32 -0400 | [diff] [blame] | 915 | |
Ingrid Gallardo | 8353222 | 2017-06-02 16:48:51 -0700 | [diff] [blame] | 916 | /* |
| 917 | * for 3dmux dsc, make sure is full ROI, since current driver doesn't |
| 918 | * support partial update for this configuration. |
| 919 | */ |
| 920 | if (!sde_kms_rect_is_null(crtc_roi) && |
| 921 | _sde_crtc_setup_is_3dmux_dsc(state)) { |
| 922 | struct drm_display_mode *adj_mode = &state->adjusted_mode; |
| 923 | |
| 924 | if (crtc_roi->w != adj_mode->hdisplay || |
| 925 | crtc_roi->h != adj_mode->vdisplay) { |
| 926 | SDE_ERROR("%s: unsupported top roi[%d %d] wxh[%d %d]\n", |
| 927 | sde_crtc->name, crtc_roi->w, crtc_roi->h, |
| 928 | adj_mode->hdisplay, adj_mode->vdisplay); |
| 929 | return -EINVAL; |
| 930 | } |
| 931 | } |
| 932 | |
Lloyd Atkinson | 8ba4703 | 2017-03-22 17:13:32 -0400 | [diff] [blame] | 933 | SDE_DEBUG("%s: crtc roi (%d,%d,%d,%d)\n", sde_crtc->name, |
| 934 | crtc_roi->x, crtc_roi->y, crtc_roi->w, crtc_roi->h); |
| 935 | |
| 936 | return 0; |
| 937 | } |
| 938 | |
Lloyd Atkinson | 7738220 | 2017-02-01 14:59:43 -0500 | [diff] [blame] | 939 | static int _sde_crtc_check_autorefresh(struct drm_crtc *crtc, |
| 940 | struct drm_crtc_state *state) |
| 941 | { |
| 942 | struct sde_crtc *sde_crtc; |
| 943 | struct sde_crtc_state *crtc_state; |
| 944 | struct drm_connector *conn; |
| 945 | struct drm_connector_state *conn_state; |
| 946 | int i; |
| 947 | |
| 948 | if (!crtc || !state) |
| 949 | return -EINVAL; |
| 950 | |
| 951 | sde_crtc = to_sde_crtc(crtc); |
| 952 | crtc_state = to_sde_crtc_state(state); |
| 953 | |
| 954 | if (sde_kms_rect_is_null(&crtc_state->crtc_roi)) |
| 955 | return 0; |
| 956 | |
| 957 | /* partial update active, check if autorefresh is also requested */ |
| 958 | for_each_connector_in_state(state->state, conn, conn_state, i) { |
| 959 | uint64_t autorefresh; |
| 960 | |
| 961 | if (!conn_state || conn_state->crtc != crtc) |
| 962 | continue; |
| 963 | |
| 964 | autorefresh = sde_connector_get_property(conn_state, |
| 965 | CONNECTOR_PROP_AUTOREFRESH); |
| 966 | if (autorefresh) { |
| 967 | SDE_ERROR( |
| 968 | "%s: autorefresh & partial crtc roi incompatible %llu\n", |
| 969 | sde_crtc->name, autorefresh); |
| 970 | return -EINVAL; |
| 971 | } |
| 972 | } |
| 973 | |
| 974 | return 0; |
| 975 | } |
| 976 | |
Lloyd Atkinson | 8ba4703 | 2017-03-22 17:13:32 -0400 | [diff] [blame] | 977 | static int _sde_crtc_set_lm_roi(struct drm_crtc *crtc, |
| 978 | struct drm_crtc_state *state, int lm_idx) |
| 979 | { |
| 980 | struct sde_crtc *sde_crtc; |
| 981 | struct sde_crtc_state *crtc_state; |
| 982 | const struct sde_rect *crtc_roi; |
| 983 | const struct sde_rect *lm_bounds; |
| 984 | struct sde_rect *lm_roi; |
| 985 | |
| 986 | if (!crtc || !state || lm_idx >= ARRAY_SIZE(crtc_state->lm_bounds)) |
| 987 | return -EINVAL; |
| 988 | |
| 989 | sde_crtc = to_sde_crtc(crtc); |
| 990 | crtc_state = to_sde_crtc_state(state); |
| 991 | crtc_roi = &crtc_state->crtc_roi; |
| 992 | lm_bounds = &crtc_state->lm_bounds[lm_idx]; |
| 993 | lm_roi = &crtc_state->lm_roi[lm_idx]; |
| 994 | |
Lloyd Atkinson | 73fb809 | 2017-02-08 16:02:55 -0500 | [diff] [blame] | 995 | if (sde_kms_rect_is_null(crtc_roi)) |
Lloyd Atkinson | 8ba4703 | 2017-03-22 17:13:32 -0400 | [diff] [blame] | 996 | memcpy(lm_roi, lm_bounds, sizeof(*lm_roi)); |
Lloyd Atkinson | 73fb809 | 2017-02-08 16:02:55 -0500 | [diff] [blame] | 997 | else |
| 998 | sde_kms_rect_intersect(crtc_roi, lm_bounds, lm_roi); |
Lloyd Atkinson | 8ba4703 | 2017-03-22 17:13:32 -0400 | [diff] [blame] | 999 | |
| 1000 | SDE_DEBUG("%s: lm%d roi (%d,%d,%d,%d)\n", sde_crtc->name, lm_idx, |
| 1001 | lm_roi->x, lm_roi->y, lm_roi->w, lm_roi->h); |
| 1002 | |
Lloyd Atkinson | 73fb809 | 2017-02-08 16:02:55 -0500 | [diff] [blame] | 1003 | /* if any dimension is zero, clear all dimensions for clarity */ |
| 1004 | if (sde_kms_rect_is_null(lm_roi)) |
| 1005 | memset(lm_roi, 0, sizeof(*lm_roi)); |
| 1006 | |
Lloyd Atkinson | 8ba4703 | 2017-03-22 17:13:32 -0400 | [diff] [blame] | 1007 | return 0; |
| 1008 | } |
| 1009 | |
Lloyd Atkinson | 73fb809 | 2017-02-08 16:02:55 -0500 | [diff] [blame] | 1010 | static u32 _sde_crtc_get_displays_affected(struct drm_crtc *crtc, |
| 1011 | struct drm_crtc_state *state) |
| 1012 | { |
| 1013 | struct sde_crtc *sde_crtc; |
| 1014 | struct sde_crtc_state *crtc_state; |
| 1015 | u32 disp_bitmask = 0; |
| 1016 | int i; |
| 1017 | |
| 1018 | sde_crtc = to_sde_crtc(crtc); |
| 1019 | crtc_state = to_sde_crtc_state(state); |
| 1020 | |
Lloyd Atkinson | 66e7dde | 2017-02-08 15:52:53 -0500 | [diff] [blame] | 1021 | /* pingpong split: one ROI, one LM, two physical displays */ |
| 1022 | if (crtc_state->is_ppsplit) { |
| 1023 | u32 lm_split_width = crtc_state->lm_bounds[0].w / 2; |
| 1024 | struct sde_rect *roi = &crtc_state->lm_roi[0]; |
| 1025 | |
| 1026 | if (sde_kms_rect_is_null(roi)) |
| 1027 | disp_bitmask = 0; |
| 1028 | else if ((u32)roi->x + (u32)roi->w <= lm_split_width) |
| 1029 | disp_bitmask = BIT(0); /* left only */ |
| 1030 | else if (roi->x >= lm_split_width) |
| 1031 | disp_bitmask = BIT(1); /* right only */ |
| 1032 | else |
| 1033 | disp_bitmask = BIT(0) | BIT(1); /* left and right */ |
| 1034 | } else { |
| 1035 | for (i = 0; i < sde_crtc->num_mixers; i++) { |
| 1036 | if (!sde_kms_rect_is_null(&crtc_state->lm_roi[i])) |
| 1037 | disp_bitmask |= BIT(i); |
| 1038 | } |
Lloyd Atkinson | 73fb809 | 2017-02-08 16:02:55 -0500 | [diff] [blame] | 1039 | } |
| 1040 | |
| 1041 | SDE_DEBUG("affected displays 0x%x\n", disp_bitmask); |
| 1042 | |
| 1043 | return disp_bitmask; |
| 1044 | } |
| 1045 | |
Lloyd Atkinson | 8ba4703 | 2017-03-22 17:13:32 -0400 | [diff] [blame] | 1046 | static int _sde_crtc_check_rois_centered_and_symmetric(struct drm_crtc *crtc, |
| 1047 | struct drm_crtc_state *state) |
| 1048 | { |
| 1049 | struct sde_crtc *sde_crtc; |
| 1050 | struct sde_crtc_state *crtc_state; |
Lloyd Atkinson | 73fb809 | 2017-02-08 16:02:55 -0500 | [diff] [blame] | 1051 | const struct sde_rect *roi[CRTC_DUAL_MIXERS]; |
Lloyd Atkinson | 8ba4703 | 2017-03-22 17:13:32 -0400 | [diff] [blame] | 1052 | |
| 1053 | if (!crtc || !state) |
| 1054 | return -EINVAL; |
| 1055 | |
Lloyd Atkinson | 73fb809 | 2017-02-08 16:02:55 -0500 | [diff] [blame] | 1056 | sde_crtc = to_sde_crtc(crtc); |
| 1057 | crtc_state = to_sde_crtc_state(state); |
| 1058 | |
Lloyd Atkinson | 73fb809 | 2017-02-08 16:02:55 -0500 | [diff] [blame] | 1059 | if (sde_crtc->num_mixers > CRTC_DUAL_MIXERS) { |
| 1060 | SDE_ERROR("%s: unsupported number of mixers: %d\n", |
| 1061 | sde_crtc->name, sde_crtc->num_mixers); |
| 1062 | return -EINVAL; |
| 1063 | } |
| 1064 | |
Lloyd Atkinson | 8ba4703 | 2017-03-22 17:13:32 -0400 | [diff] [blame] | 1065 | /* |
Lloyd Atkinson | 66e7dde | 2017-02-08 15:52:53 -0500 | [diff] [blame] | 1066 | * If using pingpong split: one ROI, one LM, two physical displays |
| 1067 | * then the ROI must be centered on the panel split boundary and |
| 1068 | * be of equal width across the split. |
Lloyd Atkinson | 8ba4703 | 2017-03-22 17:13:32 -0400 | [diff] [blame] | 1069 | */ |
Lloyd Atkinson | 66e7dde | 2017-02-08 15:52:53 -0500 | [diff] [blame] | 1070 | if (crtc_state->is_ppsplit) { |
| 1071 | u16 panel_split_width; |
| 1072 | u32 display_mask; |
| 1073 | |
| 1074 | roi[0] = &crtc_state->lm_roi[0]; |
| 1075 | |
| 1076 | if (sde_kms_rect_is_null(roi[0])) |
| 1077 | return 0; |
| 1078 | |
| 1079 | display_mask = _sde_crtc_get_displays_affected(crtc, state); |
| 1080 | if (display_mask != (BIT(0) | BIT(1))) |
| 1081 | return 0; |
| 1082 | |
| 1083 | panel_split_width = crtc_state->lm_bounds[0].w / 2; |
| 1084 | if (roi[0]->x + roi[0]->w / 2 != panel_split_width) { |
| 1085 | SDE_ERROR("%s: roi x %d w %d split %d\n", |
| 1086 | sde_crtc->name, roi[0]->x, roi[0]->w, |
| 1087 | panel_split_width); |
| 1088 | return -EINVAL; |
| 1089 | } |
| 1090 | |
| 1091 | return 0; |
| 1092 | } |
| 1093 | |
| 1094 | /* |
| 1095 | * On certain HW, if using 2 LM, ROIs must be split evenly between the |
| 1096 | * LMs and be of equal width. |
| 1097 | */ |
Clarence Ip | ffb8742 | 2017-06-30 13:37:48 -0400 | [diff] [blame] | 1098 | if (sde_crtc->num_mixers < 2) |
Lloyd Atkinson | 66e7dde | 2017-02-08 15:52:53 -0500 | [diff] [blame] | 1099 | return 0; |
| 1100 | |
Lloyd Atkinson | 73fb809 | 2017-02-08 16:02:55 -0500 | [diff] [blame] | 1101 | roi[0] = &crtc_state->lm_roi[0]; |
| 1102 | roi[1] = &crtc_state->lm_roi[1]; |
Lloyd Atkinson | 8ba4703 | 2017-03-22 17:13:32 -0400 | [diff] [blame] | 1103 | |
Lloyd Atkinson | 73fb809 | 2017-02-08 16:02:55 -0500 | [diff] [blame] | 1104 | /* if one of the roi is null it's a left/right-only update */ |
| 1105 | if (sde_kms_rect_is_null(roi[0]) || sde_kms_rect_is_null(roi[1])) |
| 1106 | return 0; |
Lloyd Atkinson | 8ba4703 | 2017-03-22 17:13:32 -0400 | [diff] [blame] | 1107 | |
Lloyd Atkinson | 73fb809 | 2017-02-08 16:02:55 -0500 | [diff] [blame] | 1108 | /* check lm rois are equal width & first roi ends at 2nd roi */ |
| 1109 | if (roi[0]->x + roi[0]->w != roi[1]->x || roi[0]->w != roi[1]->w) { |
| 1110 | SDE_ERROR( |
| 1111 | "%s: rois not centered and symmetric: roi0 x %d w %d roi1 x %d w %d\n", |
| 1112 | sde_crtc->name, roi[0]->x, roi[0]->w, |
| 1113 | roi[1]->x, roi[1]->w); |
| 1114 | return -EINVAL; |
Lloyd Atkinson | 8ba4703 | 2017-03-22 17:13:32 -0400 | [diff] [blame] | 1115 | } |
| 1116 | |
| 1117 | return 0; |
| 1118 | } |
| 1119 | |
| 1120 | static int _sde_crtc_check_planes_within_crtc_roi(struct drm_crtc *crtc, |
| 1121 | struct drm_crtc_state *state) |
| 1122 | { |
| 1123 | struct sde_crtc *sde_crtc; |
| 1124 | struct sde_crtc_state *crtc_state; |
| 1125 | const struct sde_rect *crtc_roi; |
| 1126 | struct drm_plane_state *pstate; |
| 1127 | struct drm_plane *plane; |
| 1128 | |
| 1129 | if (!crtc || !state) |
| 1130 | return -EINVAL; |
| 1131 | |
| 1132 | /* |
| 1133 | * Reject commit if a Plane CRTC destination coordinates fall outside |
| 1134 | * the partial CRTC ROI. LM output is determined via connector ROIs, |
| 1135 | * if they are specified, not Plane CRTC ROIs. |
| 1136 | */ |
| 1137 | |
| 1138 | sde_crtc = to_sde_crtc(crtc); |
| 1139 | crtc_state = to_sde_crtc_state(state); |
| 1140 | crtc_roi = &crtc_state->crtc_roi; |
| 1141 | |
| 1142 | if (sde_kms_rect_is_null(crtc_roi)) |
| 1143 | return 0; |
| 1144 | |
| 1145 | drm_atomic_crtc_state_for_each_plane(plane, state) { |
| 1146 | struct sde_rect plane_roi, intersection; |
| 1147 | |
| 1148 | pstate = drm_atomic_get_plane_state(state->state, plane); |
| 1149 | if (IS_ERR_OR_NULL(pstate)) { |
| 1150 | int rc = PTR_ERR(pstate); |
| 1151 | |
| 1152 | SDE_ERROR("%s: failed to get plane%d state, %d\n", |
| 1153 | sde_crtc->name, plane->base.id, rc); |
| 1154 | return rc; |
| 1155 | } |
| 1156 | |
| 1157 | plane_roi.x = pstate->crtc_x; |
| 1158 | plane_roi.y = pstate->crtc_y; |
| 1159 | plane_roi.w = pstate->crtc_w; |
| 1160 | plane_roi.h = pstate->crtc_h; |
| 1161 | sde_kms_rect_intersect(crtc_roi, &plane_roi, &intersection); |
| 1162 | if (!sde_kms_rect_is_equal(&plane_roi, &intersection)) { |
| 1163 | SDE_ERROR( |
| 1164 | "%s: plane%d crtc roi (%d,%d,%d,%d) outside crtc roi (%d,%d,%d,%d)\n", |
| 1165 | sde_crtc->name, plane->base.id, |
| 1166 | plane_roi.x, plane_roi.y, |
| 1167 | plane_roi.w, plane_roi.h, |
| 1168 | crtc_roi->x, crtc_roi->y, |
| 1169 | crtc_roi->w, crtc_roi->h); |
| 1170 | return -E2BIG; |
| 1171 | } |
| 1172 | } |
| 1173 | |
| 1174 | return 0; |
| 1175 | } |
| 1176 | |
| 1177 | static int _sde_crtc_check_rois(struct drm_crtc *crtc, |
| 1178 | struct drm_crtc_state *state) |
| 1179 | { |
| 1180 | struct sde_crtc *sde_crtc; |
| 1181 | int lm_idx; |
| 1182 | int rc; |
| 1183 | |
| 1184 | if (!crtc || !state) |
| 1185 | return -EINVAL; |
| 1186 | |
| 1187 | sde_crtc = to_sde_crtc(crtc); |
| 1188 | |
| 1189 | rc = _sde_crtc_set_crtc_roi(crtc, state); |
| 1190 | if (rc) |
| 1191 | return rc; |
| 1192 | |
Lloyd Atkinson | 7738220 | 2017-02-01 14:59:43 -0500 | [diff] [blame] | 1193 | rc = _sde_crtc_check_autorefresh(crtc, state); |
| 1194 | if (rc) |
| 1195 | return rc; |
| 1196 | |
Lloyd Atkinson | 8ba4703 | 2017-03-22 17:13:32 -0400 | [diff] [blame] | 1197 | for (lm_idx = 0; lm_idx < sde_crtc->num_mixers; lm_idx++) { |
| 1198 | rc = _sde_crtc_set_lm_roi(crtc, state, lm_idx); |
| 1199 | if (rc) |
| 1200 | return rc; |
| 1201 | } |
| 1202 | |
| 1203 | rc = _sde_crtc_check_rois_centered_and_symmetric(crtc, state); |
| 1204 | if (rc) |
| 1205 | return rc; |
| 1206 | |
| 1207 | rc = _sde_crtc_check_planes_within_crtc_roi(crtc, state); |
| 1208 | if (rc) |
| 1209 | return rc; |
| 1210 | |
| 1211 | return 0; |
| 1212 | } |
| 1213 | |
Lloyd Atkinson | a9d7e75 | 2017-01-17 16:31:43 -0500 | [diff] [blame] | 1214 | static void _sde_crtc_program_lm_output_roi(struct drm_crtc *crtc) |
| 1215 | { |
| 1216 | struct sde_crtc *sde_crtc; |
| 1217 | struct sde_crtc_state *crtc_state; |
Lloyd Atkinson | 8ba4703 | 2017-03-22 17:13:32 -0400 | [diff] [blame] | 1218 | const struct sde_rect *lm_roi; |
| 1219 | struct sde_hw_mixer *hw_lm; |
Lloyd Atkinson | a9d7e75 | 2017-01-17 16:31:43 -0500 | [diff] [blame] | 1220 | int lm_idx, lm_horiz_position; |
| 1221 | |
Lloyd Atkinson | 8ba4703 | 2017-03-22 17:13:32 -0400 | [diff] [blame] | 1222 | if (!crtc) |
| 1223 | return; |
| 1224 | |
Lloyd Atkinson | a9d7e75 | 2017-01-17 16:31:43 -0500 | [diff] [blame] | 1225 | sde_crtc = to_sde_crtc(crtc); |
| 1226 | crtc_state = to_sde_crtc_state(crtc->state); |
| 1227 | |
| 1228 | lm_horiz_position = 0; |
| 1229 | for (lm_idx = 0; lm_idx < sde_crtc->num_mixers; lm_idx++) { |
Lloyd Atkinson | a9d7e75 | 2017-01-17 16:31:43 -0500 | [diff] [blame] | 1230 | struct sde_hw_mixer_cfg cfg; |
| 1231 | |
Lloyd Atkinson | 8ba4703 | 2017-03-22 17:13:32 -0400 | [diff] [blame] | 1232 | lm_roi = &crtc_state->lm_roi[lm_idx]; |
| 1233 | hw_lm = sde_crtc->mixers[lm_idx].hw_lm; |
| 1234 | |
| 1235 | SDE_EVT32(DRMID(crtc_state->base.crtc), lm_idx, |
| 1236 | lm_roi->x, lm_roi->y, lm_roi->w, lm_roi->h); |
| 1237 | |
Lloyd Atkinson | a9d7e75 | 2017-01-17 16:31:43 -0500 | [diff] [blame] | 1238 | if (sde_kms_rect_is_null(lm_roi)) |
| 1239 | continue; |
| 1240 | |
Ping Li | f41c2ef | 2017-05-04 14:40:45 -0700 | [diff] [blame] | 1241 | hw_lm->cfg.out_width = lm_roi->w; |
| 1242 | hw_lm->cfg.out_height = lm_roi->h; |
| 1243 | hw_lm->cfg.right_mixer = lm_horiz_position; |
| 1244 | |
Lloyd Atkinson | a9d7e75 | 2017-01-17 16:31:43 -0500 | [diff] [blame] | 1245 | cfg.out_width = lm_roi->w; |
| 1246 | cfg.out_height = lm_roi->h; |
| 1247 | cfg.right_mixer = lm_horiz_position++; |
| 1248 | cfg.flags = 0; |
| 1249 | hw_lm->ops.setup_mixer_out(hw_lm, &cfg); |
| 1250 | } |
| 1251 | } |
| 1252 | |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 1253 | static void _sde_crtc_blend_setup_mixer(struct drm_crtc *crtc, |
| 1254 | struct sde_crtc *sde_crtc, struct sde_crtc_mixer *mixer) |
| 1255 | { |
| 1256 | struct drm_plane *plane; |
Dhaval Patel | 6c66662 | 2017-03-21 23:02:59 -0700 | [diff] [blame] | 1257 | struct drm_framebuffer *fb; |
| 1258 | struct drm_plane_state *state; |
Veera Sundaram Sankaran | 3171ff8 | 2017-01-04 14:34:47 -0800 | [diff] [blame] | 1259 | struct sde_crtc_state *cstate; |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 1260 | struct sde_plane_state *pstate = NULL; |
| 1261 | struct sde_format *format; |
Veera Sundaram Sankaran | 3171ff8 | 2017-01-04 14:34:47 -0800 | [diff] [blame] | 1262 | struct sde_hw_ctl *ctl; |
| 1263 | struct sde_hw_mixer *lm; |
| 1264 | struct sde_hw_stage_cfg *stage_cfg; |
Lloyd Atkinson | a9d7e75 | 2017-01-17 16:31:43 -0500 | [diff] [blame] | 1265 | struct sde_rect plane_crtc_roi; |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 1266 | |
Clarence Ip | 7e5f000 | 2017-05-29 18:46:56 -0400 | [diff] [blame] | 1267 | u32 flush_mask, flush_sbuf, flush_tmp; |
Dhaval Patel | 572cfd2 | 2017-06-12 19:33:39 -0700 | [diff] [blame] | 1268 | uint32_t stage_idx, lm_idx; |
| 1269 | int zpos_cnt[SDE_STAGE_MAX + 1] = { 0 }; |
Veera Sundaram Sankaran | 3171ff8 | 2017-01-04 14:34:47 -0800 | [diff] [blame] | 1270 | int i; |
Dhaval Patel | 572cfd2 | 2017-06-12 19:33:39 -0700 | [diff] [blame] | 1271 | bool bg_alpha_enable = false; |
Alan Kwong | 4dd64c8 | 2017-02-04 18:41:51 -0800 | [diff] [blame] | 1272 | u32 prefill = 0; |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 1273 | |
Veera Sundaram Sankaran | 3171ff8 | 2017-01-04 14:34:47 -0800 | [diff] [blame] | 1274 | if (!sde_crtc || !mixer) { |
| 1275 | SDE_ERROR("invalid sde_crtc or mixer\n"); |
| 1276 | return; |
| 1277 | } |
| 1278 | |
| 1279 | ctl = mixer->hw_ctl; |
| 1280 | lm = mixer->hw_lm; |
| 1281 | stage_cfg = &sde_crtc->stage_cfg; |
Lloyd Atkinson | a9d7e75 | 2017-01-17 16:31:43 -0500 | [diff] [blame] | 1282 | cstate = to_sde_crtc_state(crtc->state); |
Clarence Ip | 7e5f000 | 2017-05-29 18:46:56 -0400 | [diff] [blame] | 1283 | flush_sbuf = 0x0; |
Dhaval Patel | 44f1247 | 2016-08-29 12:19:47 -0700 | [diff] [blame] | 1284 | |
Clarence Ip | 7eb9045 | 2017-05-23 11:41:19 -0400 | [diff] [blame] | 1285 | cstate->sbuf_cfg.rot_op_mode = SDE_CTL_ROT_OP_MODE_OFFLINE; |
| 1286 | cstate->sbuf_prefill_line = 0; |
| 1287 | |
Dhaval Patel | 44f1247 | 2016-08-29 12:19:47 -0700 | [diff] [blame] | 1288 | drm_atomic_crtc_for_each_plane(plane, crtc) { |
Dhaval Patel | 6c66662 | 2017-03-21 23:02:59 -0700 | [diff] [blame] | 1289 | state = plane->state; |
| 1290 | if (!state) |
| 1291 | continue; |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 1292 | |
Lloyd Atkinson | a9d7e75 | 2017-01-17 16:31:43 -0500 | [diff] [blame] | 1293 | plane_crtc_roi.x = state->crtc_x; |
| 1294 | plane_crtc_roi.y = state->crtc_y; |
| 1295 | plane_crtc_roi.w = state->crtc_w; |
| 1296 | plane_crtc_roi.h = state->crtc_h; |
| 1297 | |
Dhaval Patel | 6c66662 | 2017-03-21 23:02:59 -0700 | [diff] [blame] | 1298 | pstate = to_sde_plane_state(state); |
| 1299 | fb = state->fb; |
Dhaval Patel | 44f1247 | 2016-08-29 12:19:47 -0700 | [diff] [blame] | 1300 | |
Alan Kwong | 4dd64c8 | 2017-02-04 18:41:51 -0800 | [diff] [blame] | 1301 | if (sde_plane_is_sbuf_mode(plane, &prefill)) |
Clarence Ip | 7eb9045 | 2017-05-23 11:41:19 -0400 | [diff] [blame] | 1302 | cstate->sbuf_cfg.rot_op_mode = |
| 1303 | SDE_CTL_ROT_OP_MODE_INLINE_SYNC; |
| 1304 | if (prefill > cstate->sbuf_prefill_line) |
| 1305 | cstate->sbuf_prefill_line = prefill; |
Alan Kwong | 4dd64c8 | 2017-02-04 18:41:51 -0800 | [diff] [blame] | 1306 | |
Clarence Ip | 7e5f000 | 2017-05-29 18:46:56 -0400 | [diff] [blame] | 1307 | sde_plane_get_ctl_flush(plane, ctl, &flush_mask, &flush_tmp); |
Dhaval Patel | 44f1247 | 2016-08-29 12:19:47 -0700 | [diff] [blame] | 1308 | |
Clarence Ip | 7e5f000 | 2017-05-29 18:46:56 -0400 | [diff] [blame] | 1309 | /* persist rotator flush bit(s) for one more commit */ |
| 1310 | flush_mask |= cstate->sbuf_flush_mask | flush_tmp; |
| 1311 | flush_sbuf |= flush_tmp; |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 1312 | |
| 1313 | SDE_DEBUG("crtc %d stage:%d - plane %d sspp %d fb %d\n", |
Clarence Ip | d9f9fa6 | 2016-09-09 13:42:32 -0400 | [diff] [blame] | 1314 | crtc->base.id, |
Clarence Ip | d9f9fa6 | 2016-09-09 13:42:32 -0400 | [diff] [blame] | 1315 | pstate->stage, |
| 1316 | plane->base.id, |
| 1317 | sde_plane_pipe(plane) - SSPP_VIG0, |
Dhaval Patel | 6c66662 | 2017-03-21 23:02:59 -0700 | [diff] [blame] | 1318 | state->fb ? state->fb->base.id : -1); |
Dhaval Patel | 44f1247 | 2016-08-29 12:19:47 -0700 | [diff] [blame] | 1319 | |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 1320 | format = to_sde_format(msm_framebuffer_format(pstate->base.fb)); |
Narendra Muppalla | ec11a0a | 2017-06-15 15:35:17 -0700 | [diff] [blame] | 1321 | if (!format) { |
| 1322 | SDE_ERROR("invalid format\n"); |
| 1323 | return; |
| 1324 | } |
| 1325 | |
Dhaval Patel | 572cfd2 | 2017-06-12 19:33:39 -0700 | [diff] [blame] | 1326 | if (pstate->stage == SDE_STAGE_BASE && format->alpha_enable) |
| 1327 | bg_alpha_enable = true; |
Dhaval Patel | 44f1247 | 2016-08-29 12:19:47 -0700 | [diff] [blame] | 1328 | |
Lloyd Atkinson | 8ba4703 | 2017-03-22 17:13:32 -0400 | [diff] [blame] | 1329 | SDE_EVT32(DRMID(crtc), DRMID(plane), |
| 1330 | state->fb ? state->fb->base.id : -1, |
| 1331 | state->src_x >> 16, state->src_y >> 16, |
| 1332 | state->src_w >> 16, state->src_h >> 16, |
| 1333 | state->crtc_x, state->crtc_y, |
Clarence Ip | 7eb9045 | 2017-05-23 11:41:19 -0400 | [diff] [blame] | 1334 | state->crtc_w, state->crtc_h, |
Clarence Ip | eb39cce | 2017-07-19 14:12:43 -0400 | [diff] [blame] | 1335 | flush_tmp ? cstate->sbuf_cfg.rot_op_mode : |
| 1336 | SDE_CTL_ROT_OP_MODE_OFFLINE); |
Dhaval Patel | 6c66662 | 2017-03-21 23:02:59 -0700 | [diff] [blame] | 1337 | |
Dhaval Patel | 572cfd2 | 2017-06-12 19:33:39 -0700 | [diff] [blame] | 1338 | stage_idx = zpos_cnt[pstate->stage]++; |
| 1339 | stage_cfg->stage[pstate->stage][stage_idx] = |
Lloyd Atkinson | a9d7e75 | 2017-01-17 16:31:43 -0500 | [diff] [blame] | 1340 | sde_plane_pipe(plane); |
Dhaval Patel | 572cfd2 | 2017-06-12 19:33:39 -0700 | [diff] [blame] | 1341 | stage_cfg->multirect_index[pstate->stage][stage_idx] = |
Lloyd Atkinson | a9d7e75 | 2017-01-17 16:31:43 -0500 | [diff] [blame] | 1342 | pstate->multirect_index; |
| 1343 | |
Dhaval Patel | 572cfd2 | 2017-06-12 19:33:39 -0700 | [diff] [blame] | 1344 | SDE_EVT32(DRMID(crtc), DRMID(plane), stage_idx, |
| 1345 | sde_plane_pipe(plane) - SSPP_VIG0, pstate->stage, |
| 1346 | pstate->multirect_index, pstate->multirect_mode, |
| 1347 | format->base.pixel_format, fb ? fb->modifier[0] : 0); |
| 1348 | |
| 1349 | /* blend config update */ |
| 1350 | for (lm_idx = 0; lm_idx < sde_crtc->num_mixers; lm_idx++) { |
| 1351 | _sde_crtc_setup_blend_cfg(mixer + lm_idx, pstate, |
| 1352 | format); |
Lloyd Atkinson | a9d7e75 | 2017-01-17 16:31:43 -0500 | [diff] [blame] | 1353 | mixer[lm_idx].flush_mask |= flush_mask; |
| 1354 | |
Dhaval Patel | 572cfd2 | 2017-06-12 19:33:39 -0700 | [diff] [blame] | 1355 | if (bg_alpha_enable && !format->alpha_enable) |
| 1356 | mixer[lm_idx].mixer_op_mode = 0; |
| 1357 | else |
| 1358 | mixer[lm_idx].mixer_op_mode |= |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 1359 | 1 << pstate->stage; |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 1360 | } |
Dhaval Patel | 44f1247 | 2016-08-29 12:19:47 -0700 | [diff] [blame] | 1361 | } |
Veera Sundaram Sankaran | 3171ff8 | 2017-01-04 14:34:47 -0800 | [diff] [blame] | 1362 | |
Clarence Ip | 7e5f000 | 2017-05-29 18:46:56 -0400 | [diff] [blame] | 1363 | cstate->sbuf_flush_mask = flush_sbuf; |
| 1364 | |
Veera Sundaram Sankaran | 3171ff8 | 2017-01-04 14:34:47 -0800 | [diff] [blame] | 1365 | if (lm && lm->ops.setup_dim_layer) { |
| 1366 | cstate = to_sde_crtc_state(crtc->state); |
| 1367 | for (i = 0; i < cstate->num_dim_layers; i++) |
| 1368 | _sde_crtc_setup_dim_layer_cfg(crtc, sde_crtc, |
| 1369 | mixer, &cstate->dim_layer[i]); |
| 1370 | } |
Alan Kwong | 4dd64c8 | 2017-02-04 18:41:51 -0800 | [diff] [blame] | 1371 | |
Clarence Ip | 7eb9045 | 2017-05-23 11:41:19 -0400 | [diff] [blame] | 1372 | if (ctl->ops.setup_sbuf_cfg) |
Alan Kwong | 4dd64c8 | 2017-02-04 18:41:51 -0800 | [diff] [blame] | 1373 | ctl->ops.setup_sbuf_cfg(ctl, &cstate->sbuf_cfg); |
Lloyd Atkinson | a9d7e75 | 2017-01-17 16:31:43 -0500 | [diff] [blame] | 1374 | |
| 1375 | _sde_crtc_program_lm_output_roi(crtc); |
Dhaval Patel | 44f1247 | 2016-08-29 12:19:47 -0700 | [diff] [blame] | 1376 | } |
| 1377 | |
Lloyd Atkinson | 094780d | 2017-04-24 17:25:08 -0400 | [diff] [blame] | 1378 | static void _sde_crtc_swap_mixers_for_right_partial_update( |
| 1379 | struct drm_crtc *crtc) |
| 1380 | { |
| 1381 | struct sde_crtc *sde_crtc; |
| 1382 | struct sde_crtc_state *cstate; |
| 1383 | struct drm_encoder *drm_enc; |
| 1384 | bool is_right_only; |
| 1385 | bool encoder_in_dsc_merge = false; |
| 1386 | |
| 1387 | if (!crtc || !crtc->state) |
| 1388 | return; |
| 1389 | |
| 1390 | sde_crtc = to_sde_crtc(crtc); |
| 1391 | cstate = to_sde_crtc_state(crtc->state); |
| 1392 | |
| 1393 | if (sde_crtc->num_mixers != CRTC_DUAL_MIXERS) |
| 1394 | return; |
| 1395 | |
| 1396 | drm_for_each_encoder(drm_enc, crtc->dev) { |
| 1397 | if (drm_enc->crtc == crtc && |
| 1398 | sde_encoder_is_dsc_merge(drm_enc)) { |
| 1399 | encoder_in_dsc_merge = true; |
| 1400 | break; |
| 1401 | } |
| 1402 | } |
| 1403 | |
| 1404 | /** |
| 1405 | * For right-only partial update with DSC merge, we swap LM0 & LM1. |
| 1406 | * This is due to two reasons: |
| 1407 | * - On 8996, there is a DSC HW requirement that in DSC Merge Mode, |
| 1408 | * the left DSC must be used, right DSC cannot be used alone. |
| 1409 | * For right-only partial update, this means swap layer mixers to map |
| 1410 | * Left LM to Right INTF. On later HW this was relaxed. |
| 1411 | * - In DSC Merge mode, the physical encoder has already registered |
| 1412 | * PP0 as the master, to switch to right-only we would have to |
| 1413 | * reprogram to be driven by PP1 instead. |
| 1414 | * To support both cases, we prefer to support the mixer swap solution. |
| 1415 | */ |
| 1416 | if (!encoder_in_dsc_merge) |
| 1417 | return; |
| 1418 | |
| 1419 | is_right_only = sde_kms_rect_is_null(&cstate->lm_roi[0]) && |
| 1420 | !sde_kms_rect_is_null(&cstate->lm_roi[1]); |
| 1421 | |
| 1422 | if (is_right_only && !sde_crtc->mixers_swapped) { |
| 1423 | /* right-only update swap mixers */ |
| 1424 | swap(sde_crtc->mixers[0], sde_crtc->mixers[1]); |
| 1425 | sde_crtc->mixers_swapped = true; |
| 1426 | } else if (!is_right_only && sde_crtc->mixers_swapped) { |
| 1427 | /* left-only or full update, swap back */ |
| 1428 | swap(sde_crtc->mixers[0], sde_crtc->mixers[1]); |
| 1429 | sde_crtc->mixers_swapped = false; |
| 1430 | } |
| 1431 | |
| 1432 | SDE_DEBUG("%s: right_only %d swapped %d, mix0->lm%d, mix1->lm%d\n", |
| 1433 | sde_crtc->name, is_right_only, sde_crtc->mixers_swapped, |
| 1434 | sde_crtc->mixers[0].hw_lm->idx - LM_0, |
| 1435 | sde_crtc->mixers[1].hw_lm->idx - LM_0); |
| 1436 | SDE_EVT32(DRMID(crtc), is_right_only, sde_crtc->mixers_swapped, |
| 1437 | sde_crtc->mixers[0].hw_lm->idx - LM_0, |
| 1438 | sde_crtc->mixers[1].hw_lm->idx - LM_0); |
| 1439 | } |
| 1440 | |
Clarence Ip | d9f9fa6 | 2016-09-09 13:42:32 -0400 | [diff] [blame] | 1441 | /** |
| 1442 | * _sde_crtc_blend_setup - configure crtc mixers |
| 1443 | * @crtc: Pointer to drm crtc structure |
| 1444 | */ |
| 1445 | static void _sde_crtc_blend_setup(struct drm_crtc *crtc) |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1446 | { |
Lloyd Atkinson | 73fb809 | 2017-02-08 16:02:55 -0500 | [diff] [blame] | 1447 | struct sde_crtc *sde_crtc; |
| 1448 | struct sde_crtc_state *sde_crtc_state; |
| 1449 | struct sde_crtc_mixer *mixer; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1450 | struct sde_hw_ctl *ctl; |
| 1451 | struct sde_hw_mixer *lm; |
Dhaval Patel | 44f1247 | 2016-08-29 12:19:47 -0700 | [diff] [blame] | 1452 | |
| 1453 | int i; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1454 | |
Lloyd Atkinson | 73fb809 | 2017-02-08 16:02:55 -0500 | [diff] [blame] | 1455 | if (!crtc) |
| 1456 | return; |
| 1457 | |
| 1458 | sde_crtc = to_sde_crtc(crtc); |
| 1459 | sde_crtc_state = to_sde_crtc_state(crtc->state); |
| 1460 | mixer = sde_crtc->mixers; |
| 1461 | |
Lloyd Atkinson | c44a52e | 2016-08-16 16:40:17 -0400 | [diff] [blame] | 1462 | SDE_DEBUG("%s\n", sde_crtc->name); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1463 | |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 1464 | if (sde_crtc->num_mixers > CRTC_DUAL_MIXERS) { |
| 1465 | SDE_ERROR("invalid number mixers: %d\n", sde_crtc->num_mixers); |
| 1466 | return; |
| 1467 | } |
| 1468 | |
| 1469 | for (i = 0; i < sde_crtc->num_mixers; i++) { |
| 1470 | if (!mixer[i].hw_lm || !mixer[i].hw_ctl) { |
| 1471 | SDE_ERROR("invalid lm or ctl assigned to mixer\n"); |
| 1472 | return; |
| 1473 | } |
| 1474 | mixer[i].mixer_op_mode = 0; |
| 1475 | mixer[i].flush_mask = 0; |
Lloyd Atkinson | e5ec30d | 2016-08-23 14:32:32 -0400 | [diff] [blame] | 1476 | if (mixer[i].hw_ctl->ops.clear_all_blendstages) |
| 1477 | mixer[i].hw_ctl->ops.clear_all_blendstages( |
| 1478 | mixer[i].hw_ctl); |
Veera Sundaram Sankaran | 3171ff8 | 2017-01-04 14:34:47 -0800 | [diff] [blame] | 1479 | |
| 1480 | /* clear dim_layer settings */ |
| 1481 | lm = mixer[i].hw_lm; |
| 1482 | if (lm->ops.clear_dim_layer) |
| 1483 | lm->ops.clear_dim_layer(lm); |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 1484 | } |
| 1485 | |
Lloyd Atkinson | 094780d | 2017-04-24 17:25:08 -0400 | [diff] [blame] | 1486 | _sde_crtc_swap_mixers_for_right_partial_update(crtc); |
| 1487 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1488 | /* initialize stage cfg */ |
Clarence Ip | 8f7366c | 2016-07-05 12:15:26 -0400 | [diff] [blame] | 1489 | memset(&sde_crtc->stage_cfg, 0, sizeof(struct sde_hw_stage_cfg)); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1490 | |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 1491 | _sde_crtc_blend_setup_mixer(crtc, sde_crtc, mixer); |
| 1492 | |
Abhijit Kulkarni | 71002ba | 2016-06-24 18:36:28 -0400 | [diff] [blame] | 1493 | for (i = 0; i < sde_crtc->num_mixers; i++) { |
Lloyd Atkinson | 73fb809 | 2017-02-08 16:02:55 -0500 | [diff] [blame] | 1494 | const struct sde_rect *lm_roi = &sde_crtc_state->lm_roi[i]; |
| 1495 | |
Abhijit Kulkarni | 71002ba | 2016-06-24 18:36:28 -0400 | [diff] [blame] | 1496 | ctl = mixer[i].hw_ctl; |
| 1497 | lm = mixer[i].hw_lm; |
Abhijit Kulkarni | 71002ba | 2016-06-24 18:36:28 -0400 | [diff] [blame] | 1498 | |
Lloyd Atkinson | 73fb809 | 2017-02-08 16:02:55 -0500 | [diff] [blame] | 1499 | if (sde_kms_rect_is_null(lm_roi)) { |
| 1500 | SDE_DEBUG( |
| 1501 | "%s: lm%d leave ctl%d mask 0 since null roi\n", |
| 1502 | sde_crtc->name, lm->idx - LM_0, |
| 1503 | ctl->idx - CTL_0); |
| 1504 | continue; |
| 1505 | } |
| 1506 | |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 1507 | lm->ops.setup_alpha_out(lm, mixer[i].mixer_op_mode); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1508 | |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 1509 | mixer[i].flush_mask |= ctl->ops.get_bitmask_mixer(ctl, |
Abhijit Kulkarni | 71002ba | 2016-06-24 18:36:28 -0400 | [diff] [blame] | 1510 | mixer[i].hw_lm->idx); |
Lloyd Atkinson | c44a52e | 2016-08-16 16:40:17 -0400 | [diff] [blame] | 1511 | |
| 1512 | /* stage config flush mask */ |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 1513 | ctl->ops.update_pending_flush(ctl, mixer[i].flush_mask); |
| 1514 | |
Clarence Ip | 8e69ad0 | 2016-12-09 09:43:57 -0500 | [diff] [blame] | 1515 | SDE_DEBUG("lm %d, op_mode 0x%X, ctl %d, flush mask 0x%x\n", |
| 1516 | mixer[i].hw_lm->idx - LM_0, |
| 1517 | mixer[i].mixer_op_mode, |
| 1518 | ctl->idx - CTL_0, |
| 1519 | mixer[i].flush_mask); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1520 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1521 | ctl->ops.setup_blendstage(ctl, mixer[i].hw_lm->idx, |
Dhaval Patel | 572cfd2 | 2017-06-12 19:33:39 -0700 | [diff] [blame] | 1522 | &sde_crtc->stage_cfg); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1523 | } |
Lloyd Atkinson | 8ba4703 | 2017-03-22 17:13:32 -0400 | [diff] [blame] | 1524 | |
| 1525 | _sde_crtc_program_lm_output_roi(crtc); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1526 | } |
| 1527 | |
Abhijit Kulkarni | 1b3340c | 2017-06-22 12:39:37 -0700 | [diff] [blame] | 1528 | static int _sde_crtc_find_plane_fb_modes(struct drm_crtc_state *state, |
| 1529 | uint32_t *fb_ns, |
| 1530 | uint32_t *fb_sec, |
| 1531 | uint32_t *fb_ns_dir, |
| 1532 | uint32_t *fb_sec_dir) |
| 1533 | { |
| 1534 | struct drm_plane *plane; |
| 1535 | const struct drm_plane_state *pstate; |
| 1536 | struct sde_plane_state *sde_pstate; |
| 1537 | uint32_t mode = 0; |
| 1538 | int rc; |
| 1539 | |
| 1540 | if (!state) { |
| 1541 | SDE_ERROR("invalid state\n"); |
| 1542 | return -EINVAL; |
| 1543 | } |
| 1544 | |
| 1545 | *fb_ns = 0; |
| 1546 | *fb_sec = 0; |
| 1547 | *fb_ns_dir = 0; |
| 1548 | *fb_sec_dir = 0; |
| 1549 | drm_atomic_crtc_state_for_each_plane_state(plane, pstate, state) { |
| 1550 | if (IS_ERR_OR_NULL(pstate)) { |
| 1551 | rc = PTR_ERR(pstate); |
| 1552 | SDE_ERROR("crtc%d failed to get plane%d state%d\n", |
| 1553 | state->crtc->base.id, |
| 1554 | plane->base.id, rc); |
| 1555 | return rc; |
| 1556 | } |
| 1557 | sde_pstate = to_sde_plane_state(pstate); |
| 1558 | mode = sde_plane_get_property(sde_pstate, |
| 1559 | PLANE_PROP_FB_TRANSLATION_MODE); |
| 1560 | switch (mode) { |
| 1561 | case SDE_DRM_FB_NON_SEC: |
| 1562 | (*fb_ns)++; |
| 1563 | break; |
| 1564 | case SDE_DRM_FB_SEC: |
| 1565 | (*fb_sec)++; |
| 1566 | break; |
| 1567 | case SDE_DRM_FB_NON_SEC_DIR_TRANS: |
| 1568 | (*fb_ns_dir)++; |
| 1569 | break; |
| 1570 | case SDE_DRM_FB_SEC_DIR_TRANS: |
| 1571 | (*fb_sec_dir)++; |
| 1572 | break; |
| 1573 | default: |
| 1574 | SDE_ERROR("Error: Plane[%d], fb_trans_mode:%d", |
| 1575 | plane->base.id, |
| 1576 | mode); |
| 1577 | return -EINVAL; |
| 1578 | } |
| 1579 | } |
| 1580 | return 0; |
| 1581 | } |
| 1582 | |
| 1583 | /** |
| 1584 | * sde_crtc_get_secure_transition_ops - determines the operations that |
| 1585 | * need to be performed before transitioning to secure state |
| 1586 | * This function should be called after swapping the new state |
| 1587 | * @crtc: Pointer to drm crtc structure |
| 1588 | * Returns the bitmask of operations need to be performed, -Error in |
| 1589 | * case of error cases |
| 1590 | */ |
| 1591 | int sde_crtc_get_secure_transition_ops(struct drm_crtc *crtc, |
| 1592 | struct drm_crtc_state *old_crtc_state, |
| 1593 | bool old_valid_fb) |
| 1594 | { |
| 1595 | struct drm_plane *plane; |
| 1596 | struct drm_encoder *encoder; |
| 1597 | struct sde_crtc *sde_crtc; |
| 1598 | struct sde_crtc_state *cstate; |
| 1599 | struct sde_crtc_smmu_state_data *smmu_state; |
| 1600 | uint32_t translation_mode = 0; |
| 1601 | int ops = 0; |
| 1602 | bool post_commit = false; |
| 1603 | |
| 1604 | if (!crtc || !crtc->state) { |
| 1605 | SDE_ERROR("invalid crtc\n"); |
| 1606 | return -EINVAL; |
| 1607 | } |
| 1608 | |
| 1609 | sde_crtc = to_sde_crtc(crtc); |
| 1610 | cstate = to_sde_crtc_state(crtc->state); |
| 1611 | smmu_state = &sde_crtc->smmu_state; |
| 1612 | |
| 1613 | SDE_DEBUG("crtc%d, secure_level%d\n", |
| 1614 | crtc->base.id, |
| 1615 | sde_crtc_get_secure_level(crtc, crtc->state)); |
| 1616 | |
| 1617 | /** |
| 1618 | * SMMU operations need to be delayed in case of |
| 1619 | * video mode panels when switching back to non_secure |
| 1620 | * mode |
| 1621 | */ |
| 1622 | drm_for_each_encoder(encoder, crtc->dev) { |
| 1623 | if (encoder->crtc != crtc) |
| 1624 | continue; |
| 1625 | |
| 1626 | post_commit &= !sde_encoder_is_cmd_mode(encoder); |
| 1627 | } |
| 1628 | |
| 1629 | drm_atomic_crtc_for_each_plane(plane, crtc) { |
| 1630 | if (!plane->state) |
| 1631 | continue; |
| 1632 | |
| 1633 | translation_mode = sde_plane_get_property( |
| 1634 | to_sde_plane_state(plane->state), |
| 1635 | PLANE_PROP_FB_TRANSLATION_MODE); |
| 1636 | if (translation_mode > SDE_DRM_FB_SEC_DIR_TRANS) { |
| 1637 | SDE_ERROR("crtc%d, invalid translation_mode%d\n", |
| 1638 | crtc->base.id, |
| 1639 | translation_mode); |
| 1640 | return -EINVAL; |
| 1641 | } |
| 1642 | |
| 1643 | /** |
| 1644 | * we can break if we find sec_fir or non_sec_dir |
| 1645 | * plane |
| 1646 | */ |
| 1647 | if ((translation_mode == SDE_DRM_FB_NON_SEC_DIR_TRANS) || |
| 1648 | (translation_mode == SDE_DRM_FB_SEC_DIR_TRANS)) |
| 1649 | break; |
| 1650 | } |
| 1651 | |
| 1652 | switch (translation_mode) { |
| 1653 | case SDE_DRM_FB_NON_SEC_DIR_TRANS: |
| 1654 | if (smmu_state->state == ATTACHED) { |
| 1655 | smmu_state->state = DETACH_ALL_REQ; |
| 1656 | smmu_state->transition_type = PRE_COMMIT; |
| 1657 | ops |= SDE_KMS_OPS_CRTC_SECURE_STATE_CHANGE; |
| 1658 | if (old_valid_fb) { |
| 1659 | ops |= (SDE_KMS_OPS_WAIT_FOR_TX_DONE | |
| 1660 | SDE_KMS_OPS_CLEANUP_PLANE_FB); |
| 1661 | } |
| 1662 | } |
| 1663 | break; |
| 1664 | case SDE_DRM_FB_SEC_DIR_TRANS: |
| 1665 | if (smmu_state->state == ATTACHED) { |
| 1666 | smmu_state->state = DETACH_SEC_REQ; |
| 1667 | smmu_state->transition_type = PRE_COMMIT; |
| 1668 | ops |= SDE_KMS_OPS_CRTC_SECURE_STATE_CHANGE; |
| 1669 | } |
| 1670 | break; |
| 1671 | case SDE_DRM_FB_SEC: |
| 1672 | case SDE_DRM_FB_NON_SEC: |
| 1673 | if (smmu_state->state == DETACHED_SEC) { |
| 1674 | smmu_state->state = ATTACH_SEC_REQ; |
| 1675 | smmu_state->transition_type = post_commit ? |
| 1676 | POST_COMMIT : PRE_COMMIT; |
| 1677 | ops |= SDE_KMS_OPS_CRTC_SECURE_STATE_CHANGE; |
| 1678 | if (translation_mode == SDE_DRM_FB_SEC) |
| 1679 | ops |= SDE_KMS_OPS_PREPARE_PLANE_FB; |
| 1680 | } else if (smmu_state->state == DETACHED) { |
| 1681 | smmu_state->state = ATTACH_ALL_REQ; |
| 1682 | smmu_state->transition_type = post_commit ? |
| 1683 | POST_COMMIT : PRE_COMMIT; |
| 1684 | ops |= SDE_KMS_OPS_CRTC_SECURE_STATE_CHANGE | |
| 1685 | SDE_KMS_OPS_PREPARE_PLANE_FB; |
| 1686 | if (old_valid_fb) |
| 1687 | ops |= (SDE_KMS_OPS_WAIT_FOR_TX_DONE | |
| 1688 | SDE_KMS_OPS_CLEANUP_PLANE_FB); |
| 1689 | } |
| 1690 | break; |
| 1691 | default: |
| 1692 | SDE_ERROR("invalid plane fb_mode:%d\n", |
| 1693 | translation_mode); |
| 1694 | ops = 0; |
| 1695 | return -EINVAL; |
| 1696 | } |
| 1697 | |
| 1698 | SDE_DEBUG("SMMU State:%d, type:%d ops:%x\n", smmu_state->state, |
| 1699 | smmu_state->transition_type, |
| 1700 | ops); |
| 1701 | return ops; |
| 1702 | } |
| 1703 | |
| 1704 | /** |
| 1705 | * _sde_crtc_scm_call - makes secure channel call to switch the VMIDs |
| 1706 | * @vimd: switch the stage 2 translation to this VMID. |
| 1707 | */ |
| 1708 | static int _sde_crtc_scm_call(int vmid) |
| 1709 | { |
| 1710 | struct scm_desc desc = {0}; |
| 1711 | uint32_t num_sids; |
| 1712 | uint32_t *sec_sid; |
| 1713 | uint32_t mem_protect_sd_ctrl_id = MEM_PROTECT_SD_CTRL_SWITCH; |
| 1714 | int ret = 0; |
| 1715 | |
| 1716 | /* This info should be queried from catalog */ |
| 1717 | num_sids = SEC_SID_CNT; |
| 1718 | sec_sid = kcalloc(num_sids, sizeof(uint32_t), GFP_KERNEL); |
| 1719 | if (!sec_sid) |
| 1720 | return -ENOMEM; |
| 1721 | |
| 1722 | /** |
| 1723 | * derive this info from device tree/catalog, this is combination of |
| 1724 | * smr mask and SID for secure |
| 1725 | */ |
| 1726 | sec_sid[0] = SEC_SID_MASK_0; |
| 1727 | sec_sid[1] = SEC_SID_MASK_1; |
| 1728 | dmac_flush_range(&sec_sid, &sec_sid + num_sids); |
| 1729 | |
| 1730 | SDE_DEBUG("calling scm_call for vmid %d", vmid); |
| 1731 | |
| 1732 | desc.arginfo = SCM_ARGS(4, SCM_VAL, SCM_RW, SCM_VAL, SCM_VAL); |
| 1733 | desc.args[0] = MDP_DEVICE_ID; |
| 1734 | desc.args[1] = SCM_BUFFER_PHYS(&sec_sid); |
| 1735 | desc.args[2] = sizeof(uint32_t) * num_sids; |
| 1736 | desc.args[3] = vmid; |
| 1737 | |
| 1738 | ret = scm_call2(SCM_SIP_FNID(SCM_SVC_MP, |
| 1739 | mem_protect_sd_ctrl_id), &desc); |
| 1740 | if (ret) { |
| 1741 | SDE_ERROR("Error:scm_call2, vmid (%lld): ret%d\n", |
| 1742 | desc.args[3], |
| 1743 | ret); |
| 1744 | } |
| 1745 | |
| 1746 | kfree(sec_sid); |
| 1747 | return ret; |
| 1748 | } |
| 1749 | |
| 1750 | /** |
| 1751 | * sde_crtc_secure_ctrl - Initiates the operations to swtich between secure |
| 1752 | * and non-secure mode |
| 1753 | * @crtc: Pointer to crtc |
| 1754 | * @post_commit: if this operation is triggered after commit |
| 1755 | */ |
| 1756 | int sde_crtc_secure_ctrl(struct drm_crtc *crtc, bool post_commit) |
| 1757 | { |
| 1758 | struct sde_crtc *sde_crtc; |
| 1759 | struct sde_crtc_state *cstate; |
| 1760 | struct sde_kms *sde_kms; |
| 1761 | struct sde_crtc_smmu_state_data *smmu_state; |
| 1762 | int ret = 0; |
| 1763 | int old_smmu_state; |
| 1764 | |
| 1765 | if (!crtc || !crtc->state) { |
| 1766 | SDE_ERROR("invalid crtc\n"); |
| 1767 | return -EINVAL; |
| 1768 | } |
| 1769 | |
| 1770 | sde_kms = _sde_crtc_get_kms(crtc); |
| 1771 | if (!sde_kms) { |
| 1772 | SDE_ERROR("invalid kms\n"); |
| 1773 | return -EINVAL; |
| 1774 | } |
| 1775 | |
| 1776 | sde_crtc = to_sde_crtc(crtc); |
| 1777 | cstate = to_sde_crtc_state(crtc->state); |
| 1778 | smmu_state = &sde_crtc->smmu_state; |
| 1779 | old_smmu_state = smmu_state->state; |
| 1780 | |
| 1781 | if ((!smmu_state->transition_type) || |
| 1782 | ((smmu_state->transition_type == POST_COMMIT) && !post_commit)) |
| 1783 | /* Bail out */ |
| 1784 | return 0; |
| 1785 | |
| 1786 | |
| 1787 | /* Secure UI use case enable */ |
| 1788 | switch (smmu_state->state) { |
| 1789 | case DETACH_ALL_REQ: |
| 1790 | /* detach_all_contexts */ |
| 1791 | ret = sde_kms_mmu_detach(sde_kms, false); |
| 1792 | if (ret) { |
| 1793 | SDE_ERROR("crtc: %d, failed to detach %d\n", |
| 1794 | crtc->base.id, ret); |
| 1795 | goto error; |
| 1796 | } |
| 1797 | |
| 1798 | ret = _sde_crtc_scm_call(VMID_CP_SEC_DISPLAY); |
| 1799 | if (ret) |
| 1800 | goto error; |
| 1801 | |
| 1802 | smmu_state->state = DETACHED; |
| 1803 | break; |
| 1804 | /* Secure UI use case disable */ |
| 1805 | case ATTACH_ALL_REQ: |
| 1806 | ret = _sde_crtc_scm_call(VMID_CP_PIXEL); |
| 1807 | if (ret) |
| 1808 | goto error; |
| 1809 | |
| 1810 | /* attach_all_contexts */ |
| 1811 | ret = sde_kms_mmu_attach(sde_kms, false); |
| 1812 | if (ret) { |
| 1813 | SDE_ERROR("crtc: %d, failed to attach %d\n", |
| 1814 | crtc->base.id, |
| 1815 | ret); |
| 1816 | goto error; |
| 1817 | } |
| 1818 | |
| 1819 | smmu_state->state = ATTACHED; |
| 1820 | |
| 1821 | break; |
| 1822 | /* Secure preview enable */ |
| 1823 | case DETACH_SEC_REQ: |
| 1824 | /* detach secure_context */ |
| 1825 | ret = sde_kms_mmu_detach(sde_kms, true); |
| 1826 | if (ret) { |
| 1827 | SDE_ERROR("crtc: %d, failed to detach %d\n", |
| 1828 | crtc->base.id, |
| 1829 | ret); |
| 1830 | goto error; |
| 1831 | } |
| 1832 | |
| 1833 | smmu_state->state = DETACHED_SEC; |
| 1834 | ret = _sde_crtc_scm_call(VMID_CP_CAMERA_PREVIEW); |
| 1835 | if (ret) |
| 1836 | goto error; |
| 1837 | |
| 1838 | break; |
| 1839 | |
| 1840 | /* Secure preview disable */ |
| 1841 | case ATTACH_SEC_REQ: |
| 1842 | ret = _sde_crtc_scm_call(VMID_CP_PIXEL); |
| 1843 | if (ret) |
| 1844 | goto error; |
| 1845 | |
| 1846 | ret = sde_kms_mmu_attach(sde_kms, true); |
| 1847 | if (ret) { |
| 1848 | SDE_ERROR("crtc: %d, failed to attach %d\n", |
| 1849 | crtc->base.id, |
| 1850 | ret); |
| 1851 | goto error; |
| 1852 | } |
| 1853 | smmu_state->state = ATTACHED; |
| 1854 | break; |
| 1855 | default: |
| 1856 | break; |
| 1857 | } |
| 1858 | |
| 1859 | SDE_DEBUG("crtc: %d, old_state %d new_state %d\n", crtc->base.id, |
| 1860 | old_smmu_state, |
| 1861 | smmu_state->state); |
| 1862 | smmu_state->transition_error = false; |
| 1863 | smmu_state->transition_type = NONE; |
| 1864 | |
| 1865 | error: |
| 1866 | smmu_state->transition_error = true; |
| 1867 | return ret; |
| 1868 | } |
| 1869 | |
Clarence Ip | 0d0e96d | 2016-10-24 18:13:13 -0400 | [diff] [blame] | 1870 | void sde_crtc_prepare_commit(struct drm_crtc *crtc, |
| 1871 | struct drm_crtc_state *old_state) |
Clarence Ip | 24f8066 | 2016-06-13 19:05:32 -0400 | [diff] [blame] | 1872 | { |
| 1873 | struct sde_crtc *sde_crtc; |
Clarence Ip | 0d0e96d | 2016-10-24 18:13:13 -0400 | [diff] [blame] | 1874 | struct sde_crtc_state *cstate; |
| 1875 | struct drm_connector *conn; |
Dhaval Patel | 5023c3c | 2017-08-22 12:40:11 -0700 | [diff] [blame^] | 1876 | struct sde_crtc_retire_event *retire_event = NULL; |
| 1877 | unsigned long flags; |
| 1878 | int i; |
Clarence Ip | 24f8066 | 2016-06-13 19:05:32 -0400 | [diff] [blame] | 1879 | |
Clarence Ip | 0d0e96d | 2016-10-24 18:13:13 -0400 | [diff] [blame] | 1880 | if (!crtc || !crtc->state) { |
Clarence Ip | 24f8066 | 2016-06-13 19:05:32 -0400 | [diff] [blame] | 1881 | SDE_ERROR("invalid crtc\n"); |
| 1882 | return; |
| 1883 | } |
| 1884 | |
| 1885 | sde_crtc = to_sde_crtc(crtc); |
Clarence Ip | 0d0e96d | 2016-10-24 18:13:13 -0400 | [diff] [blame] | 1886 | cstate = to_sde_crtc_state(crtc->state); |
Dhaval Patel | 6c66662 | 2017-03-21 23:02:59 -0700 | [diff] [blame] | 1887 | SDE_EVT32_VERBOSE(DRMID(crtc)); |
Clarence Ip | 24f8066 | 2016-06-13 19:05:32 -0400 | [diff] [blame] | 1888 | |
Clarence Ip | 0d0e96d | 2016-10-24 18:13:13 -0400 | [diff] [blame] | 1889 | /* identify connectors attached to this crtc */ |
Clarence Ip | 0d0e96d | 2016-10-24 18:13:13 -0400 | [diff] [blame] | 1890 | cstate->num_connectors = 0; |
| 1891 | |
| 1892 | drm_for_each_connector(conn, crtc->dev) |
| 1893 | if (conn->state && conn->state->crtc == crtc && |
| 1894 | cstate->num_connectors < MAX_CONNECTORS) { |
| 1895 | cstate->connectors[cstate->num_connectors++] = conn; |
| 1896 | sde_connector_prepare_fence(conn); |
Clarence Ip | 0d0e96d | 2016-10-24 18:13:13 -0400 | [diff] [blame] | 1897 | } |
| 1898 | |
Dhaval Patel | 5023c3c | 2017-08-22 12:40:11 -0700 | [diff] [blame^] | 1899 | for (i = 0; i < SDE_CRTC_FRAME_EVENT_SIZE; i++) { |
| 1900 | retire_event = &sde_crtc->retire_events[i]; |
| 1901 | if (list_empty(&retire_event->list)) |
| 1902 | break; |
| 1903 | retire_event = NULL; |
| 1904 | } |
| 1905 | |
| 1906 | if (retire_event) { |
| 1907 | retire_event->num_connectors = cstate->num_connectors; |
| 1908 | for (i = 0; i < cstate->num_connectors; i++) |
| 1909 | retire_event->connectors[i] = cstate->connectors[i]; |
| 1910 | |
| 1911 | spin_lock_irqsave(&sde_crtc->spin_lock, flags); |
| 1912 | list_add_tail(&retire_event->list, |
| 1913 | &sde_crtc->retire_event_list); |
| 1914 | spin_unlock_irqrestore(&sde_crtc->spin_lock, flags); |
| 1915 | } else { |
| 1916 | SDE_ERROR("crtc%d retire event overflow\n", crtc->base.id); |
| 1917 | SDE_EVT32(DRMID(crtc), SDE_EVTLOG_ERROR); |
| 1918 | } |
| 1919 | |
Clarence Ip | 0d0e96d | 2016-10-24 18:13:13 -0400 | [diff] [blame] | 1920 | /* prepare main output fence */ |
Clarence Ip | 24f8066 | 2016-06-13 19:05:32 -0400 | [diff] [blame] | 1921 | sde_fence_prepare(&sde_crtc->output_fence); |
| 1922 | } |
| 1923 | |
Abhinav Kumar | f2e94b5 | 2017-02-09 20:27:24 -0800 | [diff] [blame] | 1924 | /** |
| 1925 | * _sde_crtc_complete_flip - signal pending page_flip events |
| 1926 | * Any pending vblank events are added to the vblank_event_list |
| 1927 | * so that the next vblank interrupt shall signal them. |
| 1928 | * However PAGE_FLIP events are not handled through the vblank_event_list. |
| 1929 | * This API signals any pending PAGE_FLIP events requested through |
| 1930 | * DRM_IOCTL_MODE_PAGE_FLIP and are cached in the sde_crtc->event. |
| 1931 | * if file!=NULL, this is preclose potential cancel-flip path |
| 1932 | * @crtc: Pointer to drm crtc structure |
| 1933 | * @file: Pointer to drm file |
| 1934 | */ |
Lloyd Atkinson | 4f1c869 | 2016-09-14 14:04:25 -0400 | [diff] [blame] | 1935 | static void _sde_crtc_complete_flip(struct drm_crtc *crtc, |
| 1936 | struct drm_file *file) |
Abhijit Kulkarni | 40e3816 | 2016-06-26 22:12:09 -0400 | [diff] [blame] | 1937 | { |
| 1938 | struct sde_crtc *sde_crtc = to_sde_crtc(crtc); |
| 1939 | struct drm_device *dev = crtc->dev; |
| 1940 | struct drm_pending_vblank_event *event; |
| 1941 | unsigned long flags; |
| 1942 | |
| 1943 | spin_lock_irqsave(&dev->event_lock, flags); |
| 1944 | event = sde_crtc->event; |
| 1945 | if (event) { |
| 1946 | /* if regular vblank case (!file) or if cancel-flip from |
| 1947 | * preclose on file that requested flip, then send the |
| 1948 | * event: |
| 1949 | */ |
| 1950 | if (!file || (event->base.file_priv == file)) { |
| 1951 | sde_crtc->event = NULL; |
Lloyd Atkinson | 4f1c869 | 2016-09-14 14:04:25 -0400 | [diff] [blame] | 1952 | DRM_DEBUG_VBL("%s: send event: %pK\n", |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 1953 | sde_crtc->name, event); |
Dhaval Patel | a5f7595 | 2017-07-25 11:17:41 -0700 | [diff] [blame] | 1954 | SDE_EVT32_VERBOSE(DRMID(crtc)); |
Lloyd Atkinson | ac93364 | 2016-09-14 11:52:00 -0400 | [diff] [blame] | 1955 | drm_crtc_send_vblank_event(crtc, event); |
Abhijit Kulkarni | 40e3816 | 2016-06-26 22:12:09 -0400 | [diff] [blame] | 1956 | } |
| 1957 | } |
| 1958 | spin_unlock_irqrestore(&dev->event_lock, flags); |
| 1959 | } |
| 1960 | |
Alan Kwong | 3e985f0 | 2017-02-12 15:08:44 -0800 | [diff] [blame] | 1961 | enum sde_intf_mode sde_crtc_get_intf_mode(struct drm_crtc *crtc) |
| 1962 | { |
| 1963 | struct drm_encoder *encoder; |
| 1964 | |
| 1965 | if (!crtc || !crtc->dev) { |
| 1966 | SDE_ERROR("invalid crtc\n"); |
| 1967 | return INTF_MODE_NONE; |
| 1968 | } |
| 1969 | |
| 1970 | drm_for_each_encoder(encoder, crtc->dev) |
| 1971 | if (encoder->crtc == crtc) |
| 1972 | return sde_encoder_get_intf_mode(encoder); |
| 1973 | |
| 1974 | return INTF_MODE_NONE; |
| 1975 | } |
| 1976 | |
Abhijit Kulkarni | 40e3816 | 2016-06-26 22:12:09 -0400 | [diff] [blame] | 1977 | static void sde_crtc_vblank_cb(void *data) |
| 1978 | { |
| 1979 | struct drm_crtc *crtc = (struct drm_crtc *)data; |
Alan Kwong | 07da098 | 2016-11-04 12:57:45 -0400 | [diff] [blame] | 1980 | struct sde_crtc *sde_crtc = to_sde_crtc(crtc); |
| 1981 | |
| 1982 | /* keep statistics on vblank callback - with auto reset via debugfs */ |
| 1983 | if (ktime_equal(sde_crtc->vblank_cb_time, ktime_set(0, 0))) |
| 1984 | sde_crtc->vblank_cb_time = ktime_get(); |
| 1985 | else |
| 1986 | sde_crtc->vblank_cb_count++; |
Abhinav Kumar | f2e94b5 | 2017-02-09 20:27:24 -0800 | [diff] [blame] | 1987 | _sde_crtc_complete_flip(crtc, NULL); |
Lloyd Atkinson | ac93364 | 2016-09-14 11:52:00 -0400 | [diff] [blame] | 1988 | drm_crtc_handle_vblank(crtc); |
Lloyd Atkinson | 9eabe7a | 2016-09-14 13:39:15 -0400 | [diff] [blame] | 1989 | DRM_DEBUG_VBL("crtc%d\n", crtc->base.id); |
Dhaval Patel | 6c66662 | 2017-03-21 23:02:59 -0700 | [diff] [blame] | 1990 | SDE_EVT32_VERBOSE(DRMID(crtc)); |
Abhijit Kulkarni | 40e3816 | 2016-06-26 22:12:09 -0400 | [diff] [blame] | 1991 | } |
| 1992 | |
Dhaval Patel | 5023c3c | 2017-08-22 12:40:11 -0700 | [diff] [blame^] | 1993 | static void _sde_crtc_retire_event(struct drm_crtc *crtc, ktime_t ts) |
| 1994 | { |
| 1995 | struct sde_crtc_retire_event *retire_event; |
| 1996 | struct sde_crtc *sde_crtc; |
| 1997 | unsigned long flags; |
| 1998 | int i; |
| 1999 | |
| 2000 | if (!crtc) { |
| 2001 | SDE_ERROR("invalid param\n"); |
| 2002 | return; |
| 2003 | } |
| 2004 | |
| 2005 | sde_crtc = to_sde_crtc(crtc); |
| 2006 | spin_lock_irqsave(&sde_crtc->spin_lock, flags); |
| 2007 | retire_event = list_first_entry_or_null(&sde_crtc->retire_event_list, |
| 2008 | struct sde_crtc_retire_event, list); |
| 2009 | if (retire_event) |
| 2010 | list_del_init(&retire_event->list); |
| 2011 | spin_unlock_irqrestore(&sde_crtc->spin_lock, flags); |
| 2012 | |
| 2013 | if (!retire_event) { |
| 2014 | SDE_ERROR("crtc%d retire event without kickoff\n", |
| 2015 | crtc->base.id); |
| 2016 | SDE_EVT32(DRMID(crtc), SDE_EVTLOG_ERROR); |
| 2017 | return; |
| 2018 | } |
| 2019 | |
| 2020 | SDE_ATRACE_BEGIN("signal_retire_fence"); |
| 2021 | for (i = 0; (i < retire_event->num_connectors) && |
| 2022 | retire_event->connectors[i]; ++i) |
| 2023 | sde_connector_complete_commit( |
| 2024 | retire_event->connectors[i], ts); |
| 2025 | SDE_ATRACE_END("signal_retire_fence"); |
| 2026 | } |
| 2027 | |
Alan Kwong | 628d19e | 2016-10-31 13:50:13 -0400 | [diff] [blame] | 2028 | static void sde_crtc_frame_event_work(struct kthread_work *work) |
| 2029 | { |
Alan Kwong | 67a3f79 | 2016-11-01 23:16:53 -0400 | [diff] [blame] | 2030 | struct msm_drm_private *priv; |
Alan Kwong | 628d19e | 2016-10-31 13:50:13 -0400 | [diff] [blame] | 2031 | struct sde_crtc_frame_event *fevent; |
| 2032 | struct drm_crtc *crtc; |
| 2033 | struct sde_crtc *sde_crtc; |
| 2034 | struct sde_kms *sde_kms; |
| 2035 | unsigned long flags; |
Veera Sundaram Sankaran | 675ff62 | 2017-06-21 21:44:46 -0700 | [diff] [blame] | 2036 | bool frame_done = false; |
Alan Kwong | 628d19e | 2016-10-31 13:50:13 -0400 | [diff] [blame] | 2037 | |
| 2038 | if (!work) { |
| 2039 | SDE_ERROR("invalid work handle\n"); |
| 2040 | return; |
| 2041 | } |
| 2042 | |
| 2043 | fevent = container_of(work, struct sde_crtc_frame_event, work); |
Alan Kwong | a193968 | 2017-05-05 11:30:08 -0700 | [diff] [blame] | 2044 | if (!fevent->crtc || !fevent->crtc->state) { |
Alan Kwong | 628d19e | 2016-10-31 13:50:13 -0400 | [diff] [blame] | 2045 | SDE_ERROR("invalid crtc\n"); |
| 2046 | return; |
| 2047 | } |
| 2048 | |
| 2049 | crtc = fevent->crtc; |
| 2050 | sde_crtc = to_sde_crtc(crtc); |
| 2051 | |
| 2052 | sde_kms = _sde_crtc_get_kms(crtc); |
| 2053 | if (!sde_kms) { |
| 2054 | SDE_ERROR("invalid kms handle\n"); |
| 2055 | return; |
| 2056 | } |
Alan Kwong | 67a3f79 | 2016-11-01 23:16:53 -0400 | [diff] [blame] | 2057 | priv = sde_kms->dev->dev_private; |
Veera Sundaram Sankaran | a90e139 | 2017-07-06 15:00:09 -0700 | [diff] [blame] | 2058 | SDE_ATRACE_BEGIN("crtc_frame_event"); |
Alan Kwong | 628d19e | 2016-10-31 13:50:13 -0400 | [diff] [blame] | 2059 | |
| 2060 | SDE_DEBUG("crtc%d event:%u ts:%lld\n", crtc->base.id, fevent->event, |
| 2061 | ktime_to_ns(fevent->ts)); |
| 2062 | |
Veera Sundaram Sankaran | 675ff62 | 2017-06-21 21:44:46 -0700 | [diff] [blame] | 2063 | SDE_EVT32_VERBOSE(DRMID(crtc), fevent->event, SDE_EVTLOG_FUNC_ENTRY); |
| 2064 | |
| 2065 | if (fevent->event & (SDE_ENCODER_FRAME_EVENT_DONE |
| 2066 | | SDE_ENCODER_FRAME_EVENT_ERROR |
| 2067 | | SDE_ENCODER_FRAME_EVENT_PANEL_DEAD)) { |
Alan Kwong | 628d19e | 2016-10-31 13:50:13 -0400 | [diff] [blame] | 2068 | |
| 2069 | if (atomic_read(&sde_crtc->frame_pending) < 1) { |
| 2070 | /* this should not happen */ |
| 2071 | SDE_ERROR("crtc%d ts:%lld invalid frame_pending:%d\n", |
| 2072 | crtc->base.id, |
| 2073 | ktime_to_ns(fevent->ts), |
| 2074 | atomic_read(&sde_crtc->frame_pending)); |
Dhaval Patel | 6c66662 | 2017-03-21 23:02:59 -0700 | [diff] [blame] | 2075 | SDE_EVT32(DRMID(crtc), fevent->event, |
| 2076 | SDE_EVTLOG_FUNC_CASE1); |
Alan Kwong | 628d19e | 2016-10-31 13:50:13 -0400 | [diff] [blame] | 2077 | } else if (atomic_dec_return(&sde_crtc->frame_pending) == 0) { |
| 2078 | /* release bandwidth and other resources */ |
| 2079 | SDE_DEBUG("crtc%d ts:%lld last pending\n", |
| 2080 | crtc->base.id, |
| 2081 | ktime_to_ns(fevent->ts)); |
Dhaval Patel | 6c66662 | 2017-03-21 23:02:59 -0700 | [diff] [blame] | 2082 | SDE_EVT32(DRMID(crtc), fevent->event, |
| 2083 | SDE_EVTLOG_FUNC_CASE2); |
Veera Sundaram Sankaran | 7ee9909 | 2017-06-13 11:19:36 -0700 | [diff] [blame] | 2084 | sde_core_perf_crtc_release_bw(crtc); |
Alan Kwong | 628d19e | 2016-10-31 13:50:13 -0400 | [diff] [blame] | 2085 | } else { |
Dhaval Patel | 6c66662 | 2017-03-21 23:02:59 -0700 | [diff] [blame] | 2086 | SDE_EVT32_VERBOSE(DRMID(crtc), fevent->event, |
| 2087 | SDE_EVTLOG_FUNC_CASE3); |
Alan Kwong | 628d19e | 2016-10-31 13:50:13 -0400 | [diff] [blame] | 2088 | } |
Alan Kwong | a193968 | 2017-05-05 11:30:08 -0700 | [diff] [blame] | 2089 | |
Veera Sundaram Sankaran | 675ff62 | 2017-06-21 21:44:46 -0700 | [diff] [blame] | 2090 | if (fevent->event & SDE_ENCODER_FRAME_EVENT_DONE) |
Alan Kwong | a193968 | 2017-05-05 11:30:08 -0700 | [diff] [blame] | 2091 | sde_core_perf_crtc_update(crtc, 0, false); |
Veera Sundaram Sankaran | 675ff62 | 2017-06-21 21:44:46 -0700 | [diff] [blame] | 2092 | |
| 2093 | if (fevent->event & (SDE_ENCODER_FRAME_EVENT_DONE |
| 2094 | | SDE_ENCODER_FRAME_EVENT_ERROR)) |
| 2095 | frame_done = true; |
| 2096 | } |
| 2097 | |
Veera Sundaram Sankaran | a90e139 | 2017-07-06 15:00:09 -0700 | [diff] [blame] | 2098 | if (fevent->event & SDE_ENCODER_FRAME_EVENT_SIGNAL_RELEASE_FENCE) { |
| 2099 | SDE_ATRACE_BEGIN("signal_release_fence"); |
Dhaval Patel | fd8f774 | 2017-08-10 13:11:22 -0700 | [diff] [blame] | 2100 | sde_fence_signal(&sde_crtc->output_fence, fevent->ts, false); |
Veera Sundaram Sankaran | a90e139 | 2017-07-06 15:00:09 -0700 | [diff] [blame] | 2101 | SDE_ATRACE_END("signal_release_fence"); |
| 2102 | } |
Veera Sundaram Sankaran | 675ff62 | 2017-06-21 21:44:46 -0700 | [diff] [blame] | 2103 | |
Dhaval Patel | 5023c3c | 2017-08-22 12:40:11 -0700 | [diff] [blame^] | 2104 | if (fevent->event & SDE_ENCODER_FRAME_EVENT_SIGNAL_RETIRE_FENCE) |
| 2105 | /* this api should be called without spin_lock */ |
| 2106 | _sde_crtc_retire_event(crtc, fevent->ts); |
Alan Kwong | 628d19e | 2016-10-31 13:50:13 -0400 | [diff] [blame] | 2107 | |
Lloyd Atkinson | 8c49c58 | 2016-11-18 14:23:54 -0500 | [diff] [blame] | 2108 | if (fevent->event & SDE_ENCODER_FRAME_EVENT_PANEL_DEAD) |
| 2109 | SDE_ERROR("crtc%d ts:%lld received panel dead event\n", |
| 2110 | crtc->base.id, ktime_to_ns(fevent->ts)); |
| 2111 | |
Veera Sundaram Sankaran | 675ff62 | 2017-06-21 21:44:46 -0700 | [diff] [blame] | 2112 | if (frame_done) |
| 2113 | complete_all(&sde_crtc->frame_done_comp); |
| 2114 | |
Alan Kwong | 628d19e | 2016-10-31 13:50:13 -0400 | [diff] [blame] | 2115 | spin_lock_irqsave(&sde_crtc->spin_lock, flags); |
| 2116 | list_add_tail(&fevent->list, &sde_crtc->frame_event_list); |
| 2117 | spin_unlock_irqrestore(&sde_crtc->spin_lock, flags); |
Veera Sundaram Sankaran | a90e139 | 2017-07-06 15:00:09 -0700 | [diff] [blame] | 2118 | SDE_ATRACE_END("crtc_frame_event"); |
Alan Kwong | 628d19e | 2016-10-31 13:50:13 -0400 | [diff] [blame] | 2119 | } |
| 2120 | |
| 2121 | static void sde_crtc_frame_event_cb(void *data, u32 event) |
| 2122 | { |
| 2123 | struct drm_crtc *crtc = (struct drm_crtc *)data; |
| 2124 | struct sde_crtc *sde_crtc; |
| 2125 | struct msm_drm_private *priv; |
Alan Kwong | 628d19e | 2016-10-31 13:50:13 -0400 | [diff] [blame] | 2126 | struct sde_crtc_frame_event *fevent; |
| 2127 | unsigned long flags; |
Veera Sundaram Sankaran | 10ea2bd | 2017-06-14 14:10:57 -0700 | [diff] [blame] | 2128 | u32 crtc_id; |
Alan Kwong | 628d19e | 2016-10-31 13:50:13 -0400 | [diff] [blame] | 2129 | |
| 2130 | if (!crtc || !crtc->dev || !crtc->dev->dev_private) { |
| 2131 | SDE_ERROR("invalid parameters\n"); |
| 2132 | return; |
| 2133 | } |
| 2134 | sde_crtc = to_sde_crtc(crtc); |
| 2135 | priv = crtc->dev->dev_private; |
Veera Sundaram Sankaran | 10ea2bd | 2017-06-14 14:10:57 -0700 | [diff] [blame] | 2136 | crtc_id = drm_crtc_index(crtc); |
Alan Kwong | 628d19e | 2016-10-31 13:50:13 -0400 | [diff] [blame] | 2137 | |
| 2138 | SDE_DEBUG("crtc%d\n", crtc->base.id); |
Ingrid Gallardo | 79b4439 | 2017-05-30 16:30:52 -0700 | [diff] [blame] | 2139 | SDE_EVT32_VERBOSE(DRMID(crtc), event); |
Alan Kwong | 628d19e | 2016-10-31 13:50:13 -0400 | [diff] [blame] | 2140 | |
| 2141 | spin_lock_irqsave(&sde_crtc->spin_lock, flags); |
Lloyd Atkinson | 78831f8 | 2016-12-09 11:24:56 -0500 | [diff] [blame] | 2142 | fevent = list_first_entry_or_null(&sde_crtc->frame_event_list, |
| 2143 | struct sde_crtc_frame_event, list); |
| 2144 | if (fevent) |
| 2145 | list_del_init(&fevent->list); |
Alan Kwong | 628d19e | 2016-10-31 13:50:13 -0400 | [diff] [blame] | 2146 | spin_unlock_irqrestore(&sde_crtc->spin_lock, flags); |
| 2147 | |
Lloyd Atkinson | 78831f8 | 2016-12-09 11:24:56 -0500 | [diff] [blame] | 2148 | if (!fevent) { |
Alan Kwong | 628d19e | 2016-10-31 13:50:13 -0400 | [diff] [blame] | 2149 | SDE_ERROR("crtc%d event %d overflow\n", |
| 2150 | crtc->base.id, event); |
| 2151 | SDE_EVT32(DRMID(crtc), event); |
| 2152 | return; |
| 2153 | } |
| 2154 | |
Alan Kwong | 628d19e | 2016-10-31 13:50:13 -0400 | [diff] [blame] | 2155 | fevent->event = event; |
| 2156 | fevent->crtc = crtc; |
| 2157 | fevent->ts = ktime_get(); |
Veera Sundaram Sankaran | 10ea2bd | 2017-06-14 14:10:57 -0700 | [diff] [blame] | 2158 | kthread_queue_work(&priv->event_thread[crtc_id].worker, &fevent->work); |
Alan Kwong | 628d19e | 2016-10-31 13:50:13 -0400 | [diff] [blame] | 2159 | } |
| 2160 | |
Abhijit Kulkarni | 1b3340c | 2017-06-22 12:39:37 -0700 | [diff] [blame] | 2161 | void sde_crtc_complete_commit(struct drm_crtc *crtc, |
| 2162 | struct drm_crtc_state *old_state) |
| 2163 | { |
| 2164 | struct sde_crtc *sde_crtc; |
| 2165 | struct sde_crtc_smmu_state_data *smmu_state; |
| 2166 | |
| 2167 | if (!crtc || !crtc->state) { |
| 2168 | SDE_ERROR("invalid crtc\n"); |
| 2169 | return; |
| 2170 | } |
| 2171 | |
| 2172 | sde_crtc = to_sde_crtc(crtc); |
| 2173 | SDE_EVT32_VERBOSE(DRMID(crtc)); |
| 2174 | smmu_state = &sde_crtc->smmu_state; |
| 2175 | |
| 2176 | /* complete secure transitions if any */ |
| 2177 | if (smmu_state->transition_type == POST_COMMIT) |
| 2178 | sde_crtc_secure_ctrl(crtc, true); |
| 2179 | } |
| 2180 | |
Lloyd Atkinson | 5d72278 | 2016-05-30 14:09:41 -0400 | [diff] [blame] | 2181 | /** |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 2182 | * _sde_crtc_set_input_fence_timeout - update ns version of in fence timeout |
| 2183 | * @cstate: Pointer to sde crtc state |
| 2184 | */ |
| 2185 | static void _sde_crtc_set_input_fence_timeout(struct sde_crtc_state *cstate) |
| 2186 | { |
| 2187 | if (!cstate) { |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 2188 | SDE_ERROR("invalid cstate\n"); |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 2189 | return; |
| 2190 | } |
| 2191 | cstate->input_fence_timeout_ns = |
| 2192 | sde_crtc_get_property(cstate, CRTC_PROP_INPUT_FENCE_TIMEOUT); |
| 2193 | cstate->input_fence_timeout_ns *= NSEC_PER_MSEC; |
| 2194 | } |
| 2195 | |
| 2196 | /** |
Veera Sundaram Sankaran | 3171ff8 | 2017-01-04 14:34:47 -0800 | [diff] [blame] | 2197 | * _sde_crtc_set_dim_layer_v1 - copy dim layer settings from userspace |
| 2198 | * @cstate: Pointer to sde crtc state |
| 2199 | * @user_ptr: User ptr for sde_drm_dim_layer_v1 struct |
| 2200 | */ |
| 2201 | static void _sde_crtc_set_dim_layer_v1(struct sde_crtc_state *cstate, |
| 2202 | void *usr_ptr) |
| 2203 | { |
| 2204 | struct sde_drm_dim_layer_v1 dim_layer_v1; |
| 2205 | struct sde_drm_dim_layer_cfg *user_cfg; |
Veera Sundaram Sankaran | 2cb064f | 2017-05-05 14:12:17 -0700 | [diff] [blame] | 2206 | struct sde_hw_dim_layer *dim_layer; |
Veera Sundaram Sankaran | 3171ff8 | 2017-01-04 14:34:47 -0800 | [diff] [blame] | 2207 | u32 count, i; |
| 2208 | |
| 2209 | if (!cstate) { |
| 2210 | SDE_ERROR("invalid cstate\n"); |
| 2211 | return; |
| 2212 | } |
Veera Sundaram Sankaran | 2cb064f | 2017-05-05 14:12:17 -0700 | [diff] [blame] | 2213 | dim_layer = cstate->dim_layer; |
Veera Sundaram Sankaran | 3171ff8 | 2017-01-04 14:34:47 -0800 | [diff] [blame] | 2214 | |
| 2215 | if (!usr_ptr) { |
Veera Sundaram Sankaran | 2cb064f | 2017-05-05 14:12:17 -0700 | [diff] [blame] | 2216 | SDE_DEBUG("dim_layer data removed\n"); |
Veera Sundaram Sankaran | 3171ff8 | 2017-01-04 14:34:47 -0800 | [diff] [blame] | 2217 | return; |
| 2218 | } |
| 2219 | |
| 2220 | if (copy_from_user(&dim_layer_v1, usr_ptr, sizeof(dim_layer_v1))) { |
Veera Sundaram Sankaran | 2cb064f | 2017-05-05 14:12:17 -0700 | [diff] [blame] | 2221 | SDE_ERROR("failed to copy dim_layer data\n"); |
Veera Sundaram Sankaran | 3171ff8 | 2017-01-04 14:34:47 -0800 | [diff] [blame] | 2222 | return; |
| 2223 | } |
| 2224 | |
| 2225 | count = dim_layer_v1.num_layers; |
Veera Sundaram Sankaran | 2cb064f | 2017-05-05 14:12:17 -0700 | [diff] [blame] | 2226 | if (count > SDE_MAX_DIM_LAYERS) { |
| 2227 | SDE_ERROR("invalid number of dim_layers:%d", count); |
Veera Sundaram Sankaran | 3171ff8 | 2017-01-04 14:34:47 -0800 | [diff] [blame] | 2228 | return; |
| 2229 | } |
| 2230 | |
| 2231 | /* populate from user space */ |
| 2232 | cstate->num_dim_layers = count; |
| 2233 | for (i = 0; i < count; i++) { |
| 2234 | user_cfg = &dim_layer_v1.layer_cfg[i]; |
Veera Sundaram Sankaran | 3171ff8 | 2017-01-04 14:34:47 -0800 | [diff] [blame] | 2235 | |
Veera Sundaram Sankaran | 2cb064f | 2017-05-05 14:12:17 -0700 | [diff] [blame] | 2236 | dim_layer[i].flags = user_cfg->flags; |
| 2237 | dim_layer[i].stage = user_cfg->stage + SDE_STAGE_0; |
Veera Sundaram Sankaran | 3171ff8 | 2017-01-04 14:34:47 -0800 | [diff] [blame] | 2238 | |
Veera Sundaram Sankaran | 2cb064f | 2017-05-05 14:12:17 -0700 | [diff] [blame] | 2239 | dim_layer[i].rect.x = user_cfg->rect.x1; |
| 2240 | dim_layer[i].rect.y = user_cfg->rect.y1; |
| 2241 | dim_layer[i].rect.w = user_cfg->rect.x2 - user_cfg->rect.x1; |
| 2242 | dim_layer[i].rect.h = user_cfg->rect.y2 - user_cfg->rect.y1; |
| 2243 | |
| 2244 | dim_layer[i].color_fill = (struct sde_mdss_color) { |
Veera Sundaram Sankaran | 3171ff8 | 2017-01-04 14:34:47 -0800 | [diff] [blame] | 2245 | user_cfg->color_fill.color_0, |
| 2246 | user_cfg->color_fill.color_1, |
| 2247 | user_cfg->color_fill.color_2, |
| 2248 | user_cfg->color_fill.color_3, |
| 2249 | }; |
Veera Sundaram Sankaran | 2cb064f | 2017-05-05 14:12:17 -0700 | [diff] [blame] | 2250 | |
| 2251 | SDE_DEBUG("dim_layer[%d] - flags:%d, stage:%d\n", |
| 2252 | i, dim_layer[i].flags, dim_layer[i].stage); |
| 2253 | SDE_DEBUG(" rect:{%d,%d,%d,%d}, color:{%d,%d,%d,%d}\n", |
| 2254 | dim_layer[i].rect.x, dim_layer[i].rect.y, |
| 2255 | dim_layer[i].rect.w, dim_layer[i].rect.h, |
| 2256 | dim_layer[i].color_fill.color_0, |
| 2257 | dim_layer[i].color_fill.color_1, |
| 2258 | dim_layer[i].color_fill.color_2, |
| 2259 | dim_layer[i].color_fill.color_3); |
Veera Sundaram Sankaran | 3171ff8 | 2017-01-04 14:34:47 -0800 | [diff] [blame] | 2260 | } |
| 2261 | } |
| 2262 | |
| 2263 | /** |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 2264 | * _sde_crtc_wait_for_fences - wait for incoming framebuffer sync fences |
| 2265 | * @crtc: Pointer to CRTC object |
| 2266 | */ |
| 2267 | static void _sde_crtc_wait_for_fences(struct drm_crtc *crtc) |
| 2268 | { |
| 2269 | struct drm_plane *plane = NULL; |
| 2270 | uint32_t wait_ms = 1; |
Clarence Ip | 8dedc23 | 2016-09-09 16:41:00 -0400 | [diff] [blame] | 2271 | ktime_t kt_end, kt_wait; |
Dhaval Patel | 39323d4 | 2017-03-01 23:48:24 -0800 | [diff] [blame] | 2272 | int rc = 0; |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 2273 | |
Lloyd Atkinson | 4f1c869 | 2016-09-14 14:04:25 -0400 | [diff] [blame] | 2274 | SDE_DEBUG("\n"); |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 2275 | |
| 2276 | if (!crtc || !crtc->state) { |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 2277 | SDE_ERROR("invalid crtc/state %pK\n", crtc); |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 2278 | return; |
| 2279 | } |
| 2280 | |
| 2281 | /* use monotonic timer to limit total fence wait time */ |
Clarence Ip | 8dedc23 | 2016-09-09 16:41:00 -0400 | [diff] [blame] | 2282 | kt_end = ktime_add_ns(ktime_get(), |
| 2283 | to_sde_crtc_state(crtc->state)->input_fence_timeout_ns); |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 2284 | |
| 2285 | /* |
| 2286 | * Wait for fences sequentially, as all of them need to be signalled |
| 2287 | * before we can proceed. |
| 2288 | * |
| 2289 | * Limit total wait time to INPUT_FENCE_TIMEOUT, but still call |
| 2290 | * sde_plane_wait_input_fence with wait_ms == 0 after the timeout so |
| 2291 | * that each plane can check its fence status and react appropriately |
Dhaval Patel | 39323d4 | 2017-03-01 23:48:24 -0800 | [diff] [blame] | 2292 | * if its fence has timed out. Call input fence wait multiple times if |
| 2293 | * fence wait is interrupted due to interrupt call. |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 2294 | */ |
Narendra Muppalla | 77b3293 | 2017-05-10 13:53:11 -0700 | [diff] [blame] | 2295 | SDE_ATRACE_BEGIN("plane_wait_input_fence"); |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 2296 | drm_atomic_crtc_for_each_plane(plane, crtc) { |
Dhaval Patel | 39323d4 | 2017-03-01 23:48:24 -0800 | [diff] [blame] | 2297 | do { |
Clarence Ip | 8dedc23 | 2016-09-09 16:41:00 -0400 | [diff] [blame] | 2298 | kt_wait = ktime_sub(kt_end, ktime_get()); |
| 2299 | if (ktime_compare(kt_wait, ktime_set(0, 0)) >= 0) |
| 2300 | wait_ms = ktime_to_ms(kt_wait); |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 2301 | else |
| 2302 | wait_ms = 0; |
Dhaval Patel | 39323d4 | 2017-03-01 23:48:24 -0800 | [diff] [blame] | 2303 | |
| 2304 | rc = sde_plane_wait_input_fence(plane, wait_ms); |
| 2305 | } while (wait_ms && rc == -ERESTARTSYS); |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 2306 | } |
Narendra Muppalla | 77b3293 | 2017-05-10 13:53:11 -0700 | [diff] [blame] | 2307 | SDE_ATRACE_END("plane_wait_input_fence"); |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 2308 | } |
| 2309 | |
Lloyd Atkinson | 11f3444 | 2016-08-11 11:19:52 -0400 | [diff] [blame] | 2310 | static void _sde_crtc_setup_mixer_for_encoder( |
| 2311 | struct drm_crtc *crtc, |
| 2312 | struct drm_encoder *enc) |
| 2313 | { |
| 2314 | struct sde_crtc *sde_crtc = to_sde_crtc(crtc); |
Lloyd Atkinson | 4f1c869 | 2016-09-14 14:04:25 -0400 | [diff] [blame] | 2315 | struct sde_kms *sde_kms = _sde_crtc_get_kms(crtc); |
Lloyd Atkinson | 11f3444 | 2016-08-11 11:19:52 -0400 | [diff] [blame] | 2316 | struct sde_rm *rm = &sde_kms->rm; |
| 2317 | struct sde_crtc_mixer *mixer; |
Lloyd Atkinson | c44a52e | 2016-08-16 16:40:17 -0400 | [diff] [blame] | 2318 | struct sde_hw_ctl *last_valid_ctl = NULL; |
Lloyd Atkinson | 11f3444 | 2016-08-11 11:19:52 -0400 | [diff] [blame] | 2319 | int i; |
Gopikrishnaiah Anandan | e0e5e0c | 2016-05-25 11:05:33 -0700 | [diff] [blame] | 2320 | struct sde_rm_hw_iter lm_iter, ctl_iter, dspp_iter; |
Lloyd Atkinson | 11f3444 | 2016-08-11 11:19:52 -0400 | [diff] [blame] | 2321 | |
| 2322 | sde_rm_init_hw_iter(&lm_iter, enc->base.id, SDE_HW_BLK_LM); |
| 2323 | sde_rm_init_hw_iter(&ctl_iter, enc->base.id, SDE_HW_BLK_CTL); |
Gopikrishnaiah Anandan | e0e5e0c | 2016-05-25 11:05:33 -0700 | [diff] [blame] | 2324 | sde_rm_init_hw_iter(&dspp_iter, enc->base.id, SDE_HW_BLK_DSPP); |
Lloyd Atkinson | 11f3444 | 2016-08-11 11:19:52 -0400 | [diff] [blame] | 2325 | |
Lloyd Atkinson | c44a52e | 2016-08-16 16:40:17 -0400 | [diff] [blame] | 2326 | /* Set up all the mixers and ctls reserved by this encoder */ |
Lloyd Atkinson | 11f3444 | 2016-08-11 11:19:52 -0400 | [diff] [blame] | 2327 | for (i = sde_crtc->num_mixers; i < ARRAY_SIZE(sde_crtc->mixers); i++) { |
| 2328 | mixer = &sde_crtc->mixers[i]; |
| 2329 | |
Lloyd Atkinson | 11f3444 | 2016-08-11 11:19:52 -0400 | [diff] [blame] | 2330 | if (!sde_rm_get_hw(rm, &lm_iter)) |
| 2331 | break; |
| 2332 | mixer->hw_lm = (struct sde_hw_mixer *)lm_iter.hw; |
| 2333 | |
Lloyd Atkinson | c44a52e | 2016-08-16 16:40:17 -0400 | [diff] [blame] | 2334 | /* CTL may be <= LMs, if <, multiple LMs controlled by 1 CTL */ |
| 2335 | if (!sde_rm_get_hw(rm, &ctl_iter)) { |
| 2336 | SDE_DEBUG("no ctl assigned to lm %d, using previous\n", |
Clarence Ip | 8e69ad0 | 2016-12-09 09:43:57 -0500 | [diff] [blame] | 2337 | mixer->hw_lm->idx - LM_0); |
Lloyd Atkinson | c44a52e | 2016-08-16 16:40:17 -0400 | [diff] [blame] | 2338 | mixer->hw_ctl = last_valid_ctl; |
| 2339 | } else { |
| 2340 | mixer->hw_ctl = (struct sde_hw_ctl *)ctl_iter.hw; |
| 2341 | last_valid_ctl = mixer->hw_ctl; |
| 2342 | } |
Lloyd Atkinson | 11f3444 | 2016-08-11 11:19:52 -0400 | [diff] [blame] | 2343 | |
Lloyd Atkinson | c44a52e | 2016-08-16 16:40:17 -0400 | [diff] [blame] | 2344 | /* Shouldn't happen, mixers are always >= ctls */ |
| 2345 | if (!mixer->hw_ctl) { |
| 2346 | SDE_ERROR("no valid ctls found for lm %d\n", |
Clarence Ip | 8e69ad0 | 2016-12-09 09:43:57 -0500 | [diff] [blame] | 2347 | mixer->hw_lm->idx - LM_0); |
Lloyd Atkinson | c44a52e | 2016-08-16 16:40:17 -0400 | [diff] [blame] | 2348 | return; |
| 2349 | } |
| 2350 | |
Gopikrishnaiah Anandan | e0e5e0c | 2016-05-25 11:05:33 -0700 | [diff] [blame] | 2351 | /* Dspp may be null */ |
| 2352 | (void) sde_rm_get_hw(rm, &dspp_iter); |
| 2353 | mixer->hw_dspp = (struct sde_hw_dspp *)dspp_iter.hw; |
| 2354 | |
Lloyd Atkinson | 11f3444 | 2016-08-11 11:19:52 -0400 | [diff] [blame] | 2355 | mixer->encoder = enc; |
| 2356 | |
| 2357 | sde_crtc->num_mixers++; |
Clarence Ip | d9f9fa6 | 2016-09-09 13:42:32 -0400 | [diff] [blame] | 2358 | SDE_DEBUG("setup mixer %d: lm %d\n", |
| 2359 | i, mixer->hw_lm->idx - LM_0); |
| 2360 | SDE_DEBUG("setup mixer %d: ctl %d\n", |
| 2361 | i, mixer->hw_ctl->idx - CTL_0); |
Lloyd Atkinson | 11f3444 | 2016-08-11 11:19:52 -0400 | [diff] [blame] | 2362 | } |
| 2363 | } |
| 2364 | |
| 2365 | static void _sde_crtc_setup_mixers(struct drm_crtc *crtc) |
| 2366 | { |
| 2367 | struct sde_crtc *sde_crtc = to_sde_crtc(crtc); |
| 2368 | struct drm_encoder *enc; |
| 2369 | |
Lloyd Atkinson | 11f3444 | 2016-08-11 11:19:52 -0400 | [diff] [blame] | 2370 | sde_crtc->num_mixers = 0; |
| 2371 | memset(sde_crtc->mixers, 0, sizeof(sde_crtc->mixers)); |
| 2372 | |
Dhaval Patel | 3fbe6bf | 2016-10-20 20:00:41 -0700 | [diff] [blame] | 2373 | mutex_lock(&sde_crtc->crtc_lock); |
Lloyd Atkinson | 11f3444 | 2016-08-11 11:19:52 -0400 | [diff] [blame] | 2374 | /* Check for mixers on all encoders attached to this crtc */ |
| 2375 | list_for_each_entry(enc, &crtc->dev->mode_config.encoder_list, head) { |
| 2376 | if (enc->crtc != crtc) |
| 2377 | continue; |
| 2378 | |
| 2379 | _sde_crtc_setup_mixer_for_encoder(crtc, enc); |
| 2380 | } |
Lloyd Atkinson | a9d7e75 | 2017-01-17 16:31:43 -0500 | [diff] [blame] | 2381 | |
Dhaval Patel | 3fbe6bf | 2016-10-20 20:00:41 -0700 | [diff] [blame] | 2382 | mutex_unlock(&sde_crtc->crtc_lock); |
Lloyd Atkinson | 11f3444 | 2016-08-11 11:19:52 -0400 | [diff] [blame] | 2383 | } |
| 2384 | |
Lloyd Atkinson | 66e7dde | 2017-02-08 15:52:53 -0500 | [diff] [blame] | 2385 | static void _sde_crtc_setup_is_ppsplit(struct drm_crtc_state *state) |
| 2386 | { |
| 2387 | int i; |
| 2388 | struct sde_crtc_state *cstate; |
| 2389 | |
| 2390 | cstate = to_sde_crtc_state(state); |
| 2391 | |
| 2392 | cstate->is_ppsplit = false; |
| 2393 | for (i = 0; i < cstate->num_connectors; i++) { |
| 2394 | struct drm_connector *conn = cstate->connectors[i]; |
| 2395 | |
| 2396 | if (sde_connector_get_topology_name(conn) == |
| 2397 | SDE_RM_TOPOLOGY_PPSPLIT) |
| 2398 | cstate->is_ppsplit = true; |
| 2399 | } |
| 2400 | } |
| 2401 | |
Lloyd Atkinson | a9d7e75 | 2017-01-17 16:31:43 -0500 | [diff] [blame] | 2402 | static void _sde_crtc_setup_lm_bounds(struct drm_crtc *crtc, |
| 2403 | struct drm_crtc_state *state) |
| 2404 | { |
| 2405 | struct sde_crtc *sde_crtc; |
| 2406 | struct sde_crtc_state *cstate; |
| 2407 | struct drm_display_mode *adj_mode; |
| 2408 | u32 crtc_split_width; |
| 2409 | int i; |
| 2410 | |
| 2411 | if (!crtc || !state) { |
| 2412 | SDE_ERROR("invalid args\n"); |
| 2413 | return; |
| 2414 | } |
| 2415 | |
| 2416 | sde_crtc = to_sde_crtc(crtc); |
| 2417 | cstate = to_sde_crtc_state(state); |
| 2418 | |
| 2419 | adj_mode = &state->adjusted_mode; |
| 2420 | crtc_split_width = sde_crtc_mixer_width(sde_crtc, adj_mode); |
| 2421 | |
| 2422 | for (i = 0; i < sde_crtc->num_mixers; i++) { |
Lloyd Atkinson | 8ba4703 | 2017-03-22 17:13:32 -0400 | [diff] [blame] | 2423 | cstate->lm_bounds[i].x = crtc_split_width * i; |
| 2424 | cstate->lm_bounds[i].y = 0; |
| 2425 | cstate->lm_bounds[i].w = crtc_split_width; |
| 2426 | cstate->lm_bounds[i].h = adj_mode->vdisplay; |
| 2427 | memcpy(&cstate->lm_roi[i], &cstate->lm_bounds[i], |
| 2428 | sizeof(cstate->lm_roi[i])); |
Dhaval Patel | a5f7595 | 2017-07-25 11:17:41 -0700 | [diff] [blame] | 2429 | SDE_EVT32_VERBOSE(DRMID(crtc), i, |
Lloyd Atkinson | 8ba4703 | 2017-03-22 17:13:32 -0400 | [diff] [blame] | 2430 | cstate->lm_bounds[i].x, cstate->lm_bounds[i].y, |
| 2431 | cstate->lm_bounds[i].w, cstate->lm_bounds[i].h); |
| 2432 | SDE_DEBUG("%s: lm%d bnd&roi (%d,%d,%d,%d)\n", sde_crtc->name, i, |
| 2433 | cstate->lm_roi[i].x, cstate->lm_roi[i].y, |
| 2434 | cstate->lm_roi[i].w, cstate->lm_roi[i].h); |
Lloyd Atkinson | a9d7e75 | 2017-01-17 16:31:43 -0500 | [diff] [blame] | 2435 | } |
| 2436 | |
| 2437 | drm_mode_debug_printmodeline(adj_mode); |
| 2438 | } |
| 2439 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 2440 | static void sde_crtc_atomic_begin(struct drm_crtc *crtc, |
Clarence Ip | 0d0e96d | 2016-10-24 18:13:13 -0400 | [diff] [blame] | 2441 | struct drm_crtc_state *old_state) |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 2442 | { |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 2443 | struct sde_crtc *sde_crtc; |
Dhaval Patel | 0e558f4 | 2017-04-30 00:51:40 -0700 | [diff] [blame] | 2444 | struct drm_encoder *encoder; |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 2445 | struct drm_device *dev; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 2446 | unsigned long flags; |
Abhijit Kulkarni | 12cef9c | 2017-07-13 11:19:03 -0700 | [diff] [blame] | 2447 | struct sde_crtc_smmu_state_data *smmu_state; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 2448 | |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 2449 | if (!crtc) { |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 2450 | SDE_ERROR("invalid crtc\n"); |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 2451 | return; |
| 2452 | } |
| 2453 | |
Alan Kwong | 163d261 | 2016-11-03 00:56:56 -0400 | [diff] [blame] | 2454 | if (!crtc->state->enable) { |
| 2455 | SDE_DEBUG("crtc%d -> enable %d, skip atomic_begin\n", |
| 2456 | crtc->base.id, crtc->state->enable); |
| 2457 | return; |
| 2458 | } |
| 2459 | |
| 2460 | SDE_DEBUG("crtc%d\n", crtc->base.id); |
| 2461 | |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 2462 | sde_crtc = to_sde_crtc(crtc); |
| 2463 | dev = crtc->dev; |
Abhijit Kulkarni | 12cef9c | 2017-07-13 11:19:03 -0700 | [diff] [blame] | 2464 | smmu_state = &sde_crtc->smmu_state; |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 2465 | |
Lloyd Atkinson | 8ba4703 | 2017-03-22 17:13:32 -0400 | [diff] [blame] | 2466 | if (!sde_crtc->num_mixers) { |
Lloyd Atkinson | c44a52e | 2016-08-16 16:40:17 -0400 | [diff] [blame] | 2467 | _sde_crtc_setup_mixers(crtc); |
Lloyd Atkinson | 66e7dde | 2017-02-08 15:52:53 -0500 | [diff] [blame] | 2468 | _sde_crtc_setup_is_ppsplit(crtc->state); |
Lloyd Atkinson | 8ba4703 | 2017-03-22 17:13:32 -0400 | [diff] [blame] | 2469 | _sde_crtc_setup_lm_bounds(crtc, crtc->state); |
| 2470 | } |
Lloyd Atkinson | a9d7e75 | 2017-01-17 16:31:43 -0500 | [diff] [blame] | 2471 | |
Lloyd Atkinson | 265d221 | 2016-05-30 13:12:01 -0400 | [diff] [blame] | 2472 | if (sde_crtc->event) { |
| 2473 | WARN_ON(sde_crtc->event); |
| 2474 | } else { |
| 2475 | spin_lock_irqsave(&dev->event_lock, flags); |
| 2476 | sde_crtc->event = crtc->state->event; |
| 2477 | spin_unlock_irqrestore(&dev->event_lock, flags); |
| 2478 | } |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 2479 | |
Dhaval Patel | 0e558f4 | 2017-04-30 00:51:40 -0700 | [diff] [blame] | 2480 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
| 2481 | if (encoder->crtc != crtc) |
| 2482 | continue; |
Lloyd Atkinson | 5d72278 | 2016-05-30 14:09:41 -0400 | [diff] [blame] | 2483 | |
Dhaval Patel | 0e558f4 | 2017-04-30 00:51:40 -0700 | [diff] [blame] | 2484 | /* encoder will trigger pending mask now */ |
| 2485 | sde_encoder_trigger_kickoff_pending(encoder); |
Lloyd Atkinson | 5d72278 | 2016-05-30 14:09:41 -0400 | [diff] [blame] | 2486 | } |
| 2487 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 2488 | /* |
Lloyd Atkinson | c44a52e | 2016-08-16 16:40:17 -0400 | [diff] [blame] | 2489 | * If no mixers have been allocated in sde_crtc_atomic_check(), |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 2490 | * it means we are trying to flush a CRTC whose state is disabled: |
| 2491 | * nothing else needs to be done. |
| 2492 | */ |
Lloyd Atkinson | c44a52e | 2016-08-16 16:40:17 -0400 | [diff] [blame] | 2493 | if (unlikely(!sde_crtc->num_mixers)) |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 2494 | return; |
| 2495 | |
Clarence Ip | d9f9fa6 | 2016-09-09 13:42:32 -0400 | [diff] [blame] | 2496 | _sde_crtc_blend_setup(crtc); |
Abhijit Kulkarni | 12cef9c | 2017-07-13 11:19:03 -0700 | [diff] [blame] | 2497 | |
| 2498 | /* |
| 2499 | * Since CP properties use AXI buffer to program the |
| 2500 | * HW, check if context bank is in attached |
| 2501 | * state, |
| 2502 | * apply color processing properties only if |
| 2503 | * smmu state is attached, |
| 2504 | */ |
| 2505 | if ((smmu_state->state != DETACHED) || |
| 2506 | (smmu_state->state != DETACH_ALL_REQ)) |
| 2507 | sde_cp_crtc_apply_properties(crtc); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 2508 | |
| 2509 | /* |
| 2510 | * PP_DONE irq is only used by command mode for now. |
| 2511 | * It is better to request pending before FLUSH and START trigger |
| 2512 | * to make sure no pp_done irq missed. |
| 2513 | * This is safe because no pp_done will happen before SW trigger |
| 2514 | * in command mode. |
| 2515 | */ |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 2516 | } |
| 2517 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 2518 | static void sde_crtc_atomic_flush(struct drm_crtc *crtc, |
| 2519 | struct drm_crtc_state *old_crtc_state) |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 2520 | { |
Dhaval Patel | 82c8dbc | 2017-02-18 23:15:10 -0800 | [diff] [blame] | 2521 | struct drm_encoder *encoder; |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 2522 | struct sde_crtc *sde_crtc; |
| 2523 | struct drm_device *dev; |
Lloyd Atkinson | 265d221 | 2016-05-30 13:12:01 -0400 | [diff] [blame] | 2524 | struct drm_plane *plane; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 2525 | unsigned long flags; |
Dhaval Patel | 82c8dbc | 2017-02-18 23:15:10 -0800 | [diff] [blame] | 2526 | struct sde_crtc_state *cstate; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 2527 | |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 2528 | if (!crtc) { |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 2529 | SDE_ERROR("invalid crtc\n"); |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 2530 | return; |
| 2531 | } |
| 2532 | |
Alan Kwong | 163d261 | 2016-11-03 00:56:56 -0400 | [diff] [blame] | 2533 | if (!crtc->state->enable) { |
| 2534 | SDE_DEBUG("crtc%d -> enable %d, skip atomic_flush\n", |
| 2535 | crtc->base.id, crtc->state->enable); |
| 2536 | return; |
| 2537 | } |
| 2538 | |
| 2539 | SDE_DEBUG("crtc%d\n", crtc->base.id); |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 2540 | |
| 2541 | sde_crtc = to_sde_crtc(crtc); |
Dhaval Patel | 82c8dbc | 2017-02-18 23:15:10 -0800 | [diff] [blame] | 2542 | cstate = to_sde_crtc_state(crtc->state); |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 2543 | dev = crtc->dev; |
| 2544 | |
Lloyd Atkinson | 265d221 | 2016-05-30 13:12:01 -0400 | [diff] [blame] | 2545 | if (sde_crtc->event) { |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 2546 | SDE_DEBUG("already received sde_crtc->event\n"); |
Lloyd Atkinson | 265d221 | 2016-05-30 13:12:01 -0400 | [diff] [blame] | 2547 | } else { |
Lloyd Atkinson | 265d221 | 2016-05-30 13:12:01 -0400 | [diff] [blame] | 2548 | spin_lock_irqsave(&dev->event_lock, flags); |
| 2549 | sde_crtc->event = crtc->state->event; |
| 2550 | spin_unlock_irqrestore(&dev->event_lock, flags); |
| 2551 | } |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 2552 | |
| 2553 | /* |
Lloyd Atkinson | c44a52e | 2016-08-16 16:40:17 -0400 | [diff] [blame] | 2554 | * If no mixers has been allocated in sde_crtc_atomic_check(), |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 2555 | * it means we are trying to flush a CRTC whose state is disabled: |
| 2556 | * nothing else needs to be done. |
| 2557 | */ |
Lloyd Atkinson | c44a52e | 2016-08-16 16:40:17 -0400 | [diff] [blame] | 2558 | if (unlikely(!sde_crtc->num_mixers)) |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 2559 | return; |
| 2560 | |
Alan Kwong | 346223e | 2017-06-30 15:29:22 -0400 | [diff] [blame] | 2561 | /* |
| 2562 | * For planes without commit update, drm framework will not add |
| 2563 | * those planes to current state since hardware update is not |
| 2564 | * required. However, if those planes were power collapsed since |
| 2565 | * last commit cycle, driver has to restore the hardware state |
| 2566 | * of those planes explicitly here prior to plane flush. |
| 2567 | */ |
| 2568 | drm_atomic_crtc_for_each_plane(plane, crtc) |
| 2569 | sde_plane_restore(plane); |
| 2570 | |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 2571 | /* wait for acquire fences before anything else is done */ |
| 2572 | _sde_crtc_wait_for_fences(crtc); |
| 2573 | |
Dhaval Patel | 82c8dbc | 2017-02-18 23:15:10 -0800 | [diff] [blame] | 2574 | if (!cstate->rsc_update) { |
| 2575 | drm_for_each_encoder(encoder, dev) { |
| 2576 | if (encoder->crtc != crtc) |
| 2577 | continue; |
| 2578 | |
| 2579 | cstate->rsc_client = |
Dhaval Patel | 30fae8a | 2017-04-21 18:42:41 -0700 | [diff] [blame] | 2580 | sde_encoder_get_rsc_client(encoder); |
Dhaval Patel | 82c8dbc | 2017-02-18 23:15:10 -0800 | [diff] [blame] | 2581 | } |
| 2582 | cstate->rsc_update = true; |
| 2583 | } |
| 2584 | |
Alan Kwong | 9aa061c | 2016-11-06 21:17:12 -0500 | [diff] [blame] | 2585 | /* update performance setting before crtc kickoff */ |
| 2586 | sde_core_perf_crtc_update(crtc, 1, false); |
| 2587 | |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 2588 | /* |
| 2589 | * Final plane updates: Give each plane a chance to complete all |
| 2590 | * required writes/flushing before crtc's "flush |
| 2591 | * everything" call below. |
| 2592 | */ |
Abhijit Kulkarni | 1b3340c | 2017-06-22 12:39:37 -0700 | [diff] [blame] | 2593 | drm_atomic_crtc_for_each_plane(plane, crtc) { |
| 2594 | if (sde_crtc->smmu_state.transition_error) |
| 2595 | sde_plane_set_error(plane, true); |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 2596 | sde_plane_flush(plane); |
Abhijit Kulkarni | 1b3340c | 2017-06-22 12:39:37 -0700 | [diff] [blame] | 2597 | } |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 2598 | |
Lloyd Atkinson | 5d72278 | 2016-05-30 14:09:41 -0400 | [diff] [blame] | 2599 | /* Kickoff will be scheduled by outer layer */ |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 2600 | } |
| 2601 | |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 2602 | /** |
| 2603 | * sde_crtc_destroy_state - state destroy hook |
| 2604 | * @crtc: drm CRTC |
| 2605 | * @state: CRTC state object to release |
| 2606 | */ |
| 2607 | static void sde_crtc_destroy_state(struct drm_crtc *crtc, |
| 2608 | struct drm_crtc_state *state) |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 2609 | { |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 2610 | struct sde_crtc *sde_crtc; |
| 2611 | struct sde_crtc_state *cstate; |
| 2612 | |
| 2613 | if (!crtc || !state) { |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 2614 | SDE_ERROR("invalid argument(s)\n"); |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 2615 | return; |
| 2616 | } |
| 2617 | |
| 2618 | sde_crtc = to_sde_crtc(crtc); |
| 2619 | cstate = to_sde_crtc_state(state); |
| 2620 | |
Alan Kwong | 163d261 | 2016-11-03 00:56:56 -0400 | [diff] [blame] | 2621 | SDE_DEBUG("crtc%d\n", crtc->base.id); |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 2622 | |
Alan Kwong | cdb2f28 | 2017-03-18 13:42:06 -0700 | [diff] [blame] | 2623 | _sde_crtc_rp_destroy(&cstate->rp); |
| 2624 | |
Dhaval Patel | 04c7e8e | 2016-09-26 20:14:31 -0700 | [diff] [blame] | 2625 | __drm_atomic_helper_crtc_destroy_state(state); |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 2626 | |
| 2627 | /* destroy value helper */ |
| 2628 | msm_property_destroy_state(&sde_crtc->property_info, cstate, |
Clarence Ip | 4a2955d | 2017-07-04 18:04:33 -0400 | [diff] [blame] | 2629 | &cstate->property_state); |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 2630 | } |
| 2631 | |
Veera Sundaram Sankaran | 7ee9909 | 2017-06-13 11:19:36 -0700 | [diff] [blame] | 2632 | static int _sde_crtc_wait_for_frame_done(struct drm_crtc *crtc) |
| 2633 | { |
| 2634 | struct sde_crtc *sde_crtc; |
| 2635 | int ret, rc = 0; |
| 2636 | |
| 2637 | if (!crtc) { |
| 2638 | SDE_ERROR("invalid argument\n"); |
| 2639 | return -EINVAL; |
| 2640 | } |
| 2641 | sde_crtc = to_sde_crtc(crtc); |
| 2642 | |
| 2643 | if (!atomic_read(&sde_crtc->frame_pending)) { |
| 2644 | SDE_DEBUG("no frames pending\n"); |
| 2645 | return 0; |
| 2646 | } |
| 2647 | |
Dhaval Patel | a5f7595 | 2017-07-25 11:17:41 -0700 | [diff] [blame] | 2648 | SDE_EVT32_VERBOSE(DRMID(crtc), SDE_EVTLOG_FUNC_ENTRY); |
Veera Sundaram Sankaran | 7ee9909 | 2017-06-13 11:19:36 -0700 | [diff] [blame] | 2649 | ret = wait_for_completion_timeout(&sde_crtc->frame_done_comp, |
| 2650 | msecs_to_jiffies(SDE_FRAME_DONE_TIMEOUT)); |
| 2651 | if (!ret) { |
| 2652 | SDE_ERROR("frame done completion wait timed out, ret:%d\n", |
| 2653 | ret); |
| 2654 | SDE_EVT32(DRMID(crtc), SDE_EVTLOG_FATAL); |
| 2655 | rc = -ETIMEDOUT; |
| 2656 | } |
Dhaval Patel | a5f7595 | 2017-07-25 11:17:41 -0700 | [diff] [blame] | 2657 | SDE_EVT32_VERBOSE(DRMID(crtc), SDE_EVTLOG_FUNC_EXIT); |
Veera Sundaram Sankaran | 7ee9909 | 2017-06-13 11:19:36 -0700 | [diff] [blame] | 2658 | |
| 2659 | return rc; |
| 2660 | } |
| 2661 | |
Lloyd Atkinson | 5d72278 | 2016-05-30 14:09:41 -0400 | [diff] [blame] | 2662 | void sde_crtc_commit_kickoff(struct drm_crtc *crtc) |
| 2663 | { |
Clarence Ip | eb39cce | 2017-07-19 14:12:43 -0400 | [diff] [blame] | 2664 | struct drm_plane *plane; |
Lloyd Atkinson | e7bcdd2 | 2016-08-11 10:53:37 -0400 | [diff] [blame] | 2665 | struct drm_encoder *encoder; |
| 2666 | struct drm_device *dev; |
Alan Kwong | 628d19e | 2016-10-31 13:50:13 -0400 | [diff] [blame] | 2667 | struct sde_crtc *sde_crtc; |
Alan Kwong | 67a3f79 | 2016-11-01 23:16:53 -0400 | [diff] [blame] | 2668 | struct msm_drm_private *priv; |
| 2669 | struct sde_kms *sde_kms; |
Alan Kwong | 4aacd53 | 2017-02-04 18:51:33 -0800 | [diff] [blame] | 2670 | struct sde_crtc_state *cstate; |
Veera Sundaram Sankaran | a90e139 | 2017-07-06 15:00:09 -0700 | [diff] [blame] | 2671 | int ret; |
Lloyd Atkinson | 5d72278 | 2016-05-30 14:09:41 -0400 | [diff] [blame] | 2672 | |
| 2673 | if (!crtc) { |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 2674 | SDE_ERROR("invalid argument\n"); |
Lloyd Atkinson | 5d72278 | 2016-05-30 14:09:41 -0400 | [diff] [blame] | 2675 | return; |
| 2676 | } |
Lloyd Atkinson | e7bcdd2 | 2016-08-11 10:53:37 -0400 | [diff] [blame] | 2677 | dev = crtc->dev; |
Alan Kwong | 628d19e | 2016-10-31 13:50:13 -0400 | [diff] [blame] | 2678 | sde_crtc = to_sde_crtc(crtc); |
Alan Kwong | 67a3f79 | 2016-11-01 23:16:53 -0400 | [diff] [blame] | 2679 | sde_kms = _sde_crtc_get_kms(crtc); |
Narendra Muppalla | ec11a0a | 2017-06-15 15:35:17 -0700 | [diff] [blame] | 2680 | |
| 2681 | if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev_private) { |
| 2682 | SDE_ERROR("invalid argument\n"); |
| 2683 | return; |
| 2684 | } |
| 2685 | |
Alan Kwong | 67a3f79 | 2016-11-01 23:16:53 -0400 | [diff] [blame] | 2686 | priv = sde_kms->dev->dev_private; |
Alan Kwong | 4aacd53 | 2017-02-04 18:51:33 -0800 | [diff] [blame] | 2687 | cstate = to_sde_crtc_state(crtc->state); |
Lloyd Atkinson | 5d72278 | 2016-05-30 14:09:41 -0400 | [diff] [blame] | 2688 | |
Clarence Ip | 90b282d | 2017-05-04 10:00:32 -0700 | [diff] [blame] | 2689 | /* |
| 2690 | * If no mixers has been allocated in sde_crtc_atomic_check(), |
| 2691 | * it means we are trying to start a CRTC whose state is disabled: |
| 2692 | * nothing else needs to be done. |
| 2693 | */ |
| 2694 | if (unlikely(!sde_crtc->num_mixers)) |
| 2695 | return; |
| 2696 | |
Narendra Muppalla | 77b3293 | 2017-05-10 13:53:11 -0700 | [diff] [blame] | 2697 | SDE_ATRACE_BEGIN("crtc_commit"); |
Lloyd Atkinson | e7bcdd2 | 2016-08-11 10:53:37 -0400 | [diff] [blame] | 2698 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
Alan Kwong | 4aacd53 | 2017-02-04 18:51:33 -0800 | [diff] [blame] | 2699 | struct sde_encoder_kickoff_params params = { 0 }; |
| 2700 | |
Lloyd Atkinson | e7bcdd2 | 2016-08-11 10:53:37 -0400 | [diff] [blame] | 2701 | if (encoder->crtc != crtc) |
| 2702 | continue; |
| 2703 | |
| 2704 | /* |
| 2705 | * Encoder will flush/start now, unless it has a tx pending. |
| 2706 | * If so, it may delay and flush at an irq event (e.g. ppdone) |
| 2707 | */ |
Alan Kwong | 4aacd53 | 2017-02-04 18:51:33 -0800 | [diff] [blame] | 2708 | params.inline_rotate_prefill = cstate->sbuf_prefill_line; |
Lloyd Atkinson | 73fb809 | 2017-02-08 16:02:55 -0500 | [diff] [blame] | 2709 | params.affected_displays = _sde_crtc_get_displays_affected(crtc, |
| 2710 | crtc->state); |
Alan Kwong | 4aacd53 | 2017-02-04 18:51:33 -0800 | [diff] [blame] | 2711 | sde_encoder_prepare_for_kickoff(encoder, ¶ms); |
Alan Kwong | 628d19e | 2016-10-31 13:50:13 -0400 | [diff] [blame] | 2712 | } |
| 2713 | |
Veera Sundaram Sankaran | 7ee9909 | 2017-06-13 11:19:36 -0700 | [diff] [blame] | 2714 | /* wait for frame_event_done completion */ |
Veera Sundaram Sankaran | a90e139 | 2017-07-06 15:00:09 -0700 | [diff] [blame] | 2715 | SDE_ATRACE_BEGIN("wait_for_frame_done_event"); |
| 2716 | ret = _sde_crtc_wait_for_frame_done(crtc); |
| 2717 | SDE_ATRACE_END("wait_for_frame_done_event"); |
| 2718 | if (ret) { |
Veera Sundaram Sankaran | 7ee9909 | 2017-06-13 11:19:36 -0700 | [diff] [blame] | 2719 | SDE_ERROR("crtc%d wait for frame done failed;frame_pending%d\n", |
| 2720 | crtc->base.id, |
| 2721 | atomic_read(&sde_crtc->frame_pending)); |
Narendra Muppalla | 77b3293 | 2017-05-10 13:53:11 -0700 | [diff] [blame] | 2722 | goto end; |
Veera Sundaram Sankaran | 7ee9909 | 2017-06-13 11:19:36 -0700 | [diff] [blame] | 2723 | } |
| 2724 | |
| 2725 | if (atomic_inc_return(&sde_crtc->frame_pending) == 1) { |
Alan Kwong | 628d19e | 2016-10-31 13:50:13 -0400 | [diff] [blame] | 2726 | /* acquire bandwidth and other resources */ |
| 2727 | SDE_DEBUG("crtc%d first commit\n", crtc->base.id); |
Veera Sundaram Sankaran | 7ee9909 | 2017-06-13 11:19:36 -0700 | [diff] [blame] | 2728 | SDE_EVT32(DRMID(crtc), SDE_EVTLOG_FUNC_CASE1); |
Alan Kwong | 628d19e | 2016-10-31 13:50:13 -0400 | [diff] [blame] | 2729 | } else { |
| 2730 | SDE_DEBUG("crtc%d commit\n", crtc->base.id); |
Veera Sundaram Sankaran | 7ee9909 | 2017-06-13 11:19:36 -0700 | [diff] [blame] | 2731 | SDE_EVT32(DRMID(crtc), SDE_EVTLOG_FUNC_CASE2); |
Alan Kwong | 628d19e | 2016-10-31 13:50:13 -0400 | [diff] [blame] | 2732 | } |
Dhaval Patel | d67cf4a | 2017-06-14 18:08:32 -0700 | [diff] [blame] | 2733 | sde_crtc->play_count++; |
Alan Kwong | 628d19e | 2016-10-31 13:50:13 -0400 | [diff] [blame] | 2734 | |
Clarence Ip | eb39cce | 2017-07-19 14:12:43 -0400 | [diff] [blame] | 2735 | if (cstate->sbuf_cfg.rot_op_mode != SDE_CTL_ROT_OP_MODE_OFFLINE) |
| 2736 | drm_atomic_crtc_for_each_plane(plane, crtc) |
| 2737 | sde_plane_kickoff(plane); |
| 2738 | |
Clarence Ip | 980405d | 2017-08-08 18:33:44 -0400 | [diff] [blame] | 2739 | sde_vbif_clear_errors(sde_kms); |
| 2740 | |
Alan Kwong | 628d19e | 2016-10-31 13:50:13 -0400 | [diff] [blame] | 2741 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
| 2742 | if (encoder->crtc != crtc) |
| 2743 | continue; |
| 2744 | |
| 2745 | sde_encoder_kickoff(encoder); |
Lloyd Atkinson | e7bcdd2 | 2016-08-11 10:53:37 -0400 | [diff] [blame] | 2746 | } |
Veera Sundaram Sankaran | 7ee9909 | 2017-06-13 11:19:36 -0700 | [diff] [blame] | 2747 | |
Narendra Muppalla | 77b3293 | 2017-05-10 13:53:11 -0700 | [diff] [blame] | 2748 | end: |
Dhaval Patel | b9850c0 | 2017-08-07 22:55:47 -0700 | [diff] [blame] | 2749 | reinit_completion(&sde_crtc->frame_done_comp); |
Narendra Muppalla | 77b3293 | 2017-05-10 13:53:11 -0700 | [diff] [blame] | 2750 | SDE_ATRACE_END("crtc_commit"); |
| 2751 | return; |
Lloyd Atkinson | 5d72278 | 2016-05-30 14:09:41 -0400 | [diff] [blame] | 2752 | } |
| 2753 | |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 2754 | /** |
Lloyd Atkinson | dcb1c4a | 2017-07-27 10:52:09 -0400 | [diff] [blame] | 2755 | * _sde_crtc_vblank_enable_no_lock - update power resource and vblank request |
Clarence Ip | 7f70ce4 | 2017-03-20 06:53:46 -0700 | [diff] [blame] | 2756 | * @sde_crtc: Pointer to sde crtc structure |
| 2757 | * @enable: Whether to enable/disable vblanks |
Lloyd Atkinson | dcb1c4a | 2017-07-27 10:52:09 -0400 | [diff] [blame] | 2758 | * |
| 2759 | * @Return: error code |
Clarence Ip | 7f70ce4 | 2017-03-20 06:53:46 -0700 | [diff] [blame] | 2760 | */ |
Lloyd Atkinson | dcb1c4a | 2017-07-27 10:52:09 -0400 | [diff] [blame] | 2761 | static int _sde_crtc_vblank_enable_no_lock( |
Clarence Ip | 7f70ce4 | 2017-03-20 06:53:46 -0700 | [diff] [blame] | 2762 | struct sde_crtc *sde_crtc, bool enable) |
| 2763 | { |
| 2764 | struct drm_device *dev; |
| 2765 | struct drm_crtc *crtc; |
| 2766 | struct drm_encoder *enc; |
Clarence Ip | 7f70ce4 | 2017-03-20 06:53:46 -0700 | [diff] [blame] | 2767 | |
| 2768 | if (!sde_crtc) { |
| 2769 | SDE_ERROR("invalid crtc\n"); |
Lloyd Atkinson | dcb1c4a | 2017-07-27 10:52:09 -0400 | [diff] [blame] | 2770 | return -EINVAL; |
Clarence Ip | 7f70ce4 | 2017-03-20 06:53:46 -0700 | [diff] [blame] | 2771 | } |
| 2772 | |
| 2773 | crtc = &sde_crtc->base; |
| 2774 | dev = crtc->dev; |
Clarence Ip | 7f70ce4 | 2017-03-20 06:53:46 -0700 | [diff] [blame] | 2775 | |
| 2776 | if (enable) { |
Lloyd Atkinson | 2c554eb | 2017-05-24 16:22:39 -0400 | [diff] [blame] | 2777 | int ret; |
| 2778 | |
| 2779 | /* drop lock since power crtc cb may try to re-acquire lock */ |
| 2780 | mutex_unlock(&sde_crtc->crtc_lock); |
| 2781 | ret = _sde_crtc_power_enable(sde_crtc, true); |
| 2782 | mutex_lock(&sde_crtc->crtc_lock); |
| 2783 | if (ret) |
Lloyd Atkinson | dcb1c4a | 2017-07-27 10:52:09 -0400 | [diff] [blame] | 2784 | return ret; |
Dhaval Patel | f9245d6 | 2017-03-28 16:24:00 -0700 | [diff] [blame] | 2785 | |
Clarence Ip | 7f70ce4 | 2017-03-20 06:53:46 -0700 | [diff] [blame] | 2786 | list_for_each_entry(enc, &dev->mode_config.encoder_list, head) { |
| 2787 | if (enc->crtc != crtc) |
| 2788 | continue; |
| 2789 | |
Lloyd Atkinson | dcb1c4a | 2017-07-27 10:52:09 -0400 | [diff] [blame] | 2790 | SDE_EVT32(DRMID(&sde_crtc->base), DRMID(enc), enable, |
| 2791 | sde_crtc->enabled, |
| 2792 | sde_crtc->suspend, |
| 2793 | sde_crtc->vblank_requested); |
Clarence Ip | 7f70ce4 | 2017-03-20 06:53:46 -0700 | [diff] [blame] | 2794 | |
| 2795 | sde_encoder_register_vblank_callback(enc, |
| 2796 | sde_crtc_vblank_cb, (void *)crtc); |
| 2797 | } |
| 2798 | } else { |
| 2799 | list_for_each_entry(enc, &dev->mode_config.encoder_list, head) { |
| 2800 | if (enc->crtc != crtc) |
| 2801 | continue; |
| 2802 | |
Lloyd Atkinson | dcb1c4a | 2017-07-27 10:52:09 -0400 | [diff] [blame] | 2803 | SDE_EVT32(DRMID(&sde_crtc->base), DRMID(enc), enable, |
| 2804 | sde_crtc->enabled, |
| 2805 | sde_crtc->suspend, |
| 2806 | sde_crtc->vblank_requested); |
Clarence Ip | 7f70ce4 | 2017-03-20 06:53:46 -0700 | [diff] [blame] | 2807 | |
| 2808 | sde_encoder_register_vblank_callback(enc, NULL, NULL); |
| 2809 | } |
Lloyd Atkinson | 2c554eb | 2017-05-24 16:22:39 -0400 | [diff] [blame] | 2810 | |
| 2811 | /* drop lock since power crtc cb may try to re-acquire lock */ |
| 2812 | mutex_unlock(&sde_crtc->crtc_lock); |
Dhaval Patel | f9245d6 | 2017-03-28 16:24:00 -0700 | [diff] [blame] | 2813 | _sde_crtc_power_enable(sde_crtc, false); |
Lloyd Atkinson | 2c554eb | 2017-05-24 16:22:39 -0400 | [diff] [blame] | 2814 | mutex_lock(&sde_crtc->crtc_lock); |
Clarence Ip | 7f70ce4 | 2017-03-20 06:53:46 -0700 | [diff] [blame] | 2815 | } |
Lloyd Atkinson | dcb1c4a | 2017-07-27 10:52:09 -0400 | [diff] [blame] | 2816 | |
| 2817 | return 0; |
Clarence Ip | 7f70ce4 | 2017-03-20 06:53:46 -0700 | [diff] [blame] | 2818 | } |
| 2819 | |
| 2820 | /** |
| 2821 | * _sde_crtc_set_suspend - notify crtc of suspend enable/disable |
| 2822 | * @crtc: Pointer to drm crtc object |
| 2823 | * @enable: true to enable suspend, false to indicate resume |
| 2824 | */ |
| 2825 | static void _sde_crtc_set_suspend(struct drm_crtc *crtc, bool enable) |
| 2826 | { |
| 2827 | struct sde_crtc *sde_crtc; |
| 2828 | struct msm_drm_private *priv; |
| 2829 | struct sde_kms *sde_kms; |
Lloyd Atkinson | dcb1c4a | 2017-07-27 10:52:09 -0400 | [diff] [blame] | 2830 | int ret = 0; |
Clarence Ip | 7f70ce4 | 2017-03-20 06:53:46 -0700 | [diff] [blame] | 2831 | |
| 2832 | if (!crtc || !crtc->dev || !crtc->dev->dev_private) { |
| 2833 | SDE_ERROR("invalid crtc\n"); |
| 2834 | return; |
| 2835 | } |
| 2836 | sde_crtc = to_sde_crtc(crtc); |
| 2837 | priv = crtc->dev->dev_private; |
| 2838 | |
| 2839 | if (!priv->kms) { |
| 2840 | SDE_ERROR("invalid crtc kms\n"); |
| 2841 | return; |
| 2842 | } |
| 2843 | sde_kms = to_sde_kms(priv->kms); |
| 2844 | |
| 2845 | SDE_DEBUG("crtc%d suspend = %d\n", crtc->base.id, enable); |
Lloyd Atkinson | dcb1c4a | 2017-07-27 10:52:09 -0400 | [diff] [blame] | 2846 | SDE_EVT32_VERBOSE(DRMID(crtc), enable); |
Clarence Ip | 7f70ce4 | 2017-03-20 06:53:46 -0700 | [diff] [blame] | 2847 | |
| 2848 | mutex_lock(&sde_crtc->crtc_lock); |
| 2849 | |
Clarence Ip | 2f9beeb | 2017-03-16 11:04:53 -0400 | [diff] [blame] | 2850 | /* |
Lloyd Atkinson | b2be0c4 | 2017-07-17 16:41:00 -0400 | [diff] [blame] | 2851 | * If the vblank is enabled, release a power reference on suspend |
| 2852 | * and take it back during resume (if it is still enabled). |
Clarence Ip | 7f70ce4 | 2017-03-20 06:53:46 -0700 | [diff] [blame] | 2853 | */ |
Lloyd Atkinson | dcb1c4a | 2017-07-27 10:52:09 -0400 | [diff] [blame] | 2854 | SDE_EVT32(DRMID(&sde_crtc->base), enable, sde_crtc->enabled, |
| 2855 | sde_crtc->suspend, sde_crtc->vblank_requested); |
Clarence Ip | 7f70ce4 | 2017-03-20 06:53:46 -0700 | [diff] [blame] | 2856 | if (sde_crtc->suspend == enable) |
| 2857 | SDE_DEBUG("crtc%d suspend already set to %d, ignoring update\n", |
| 2858 | crtc->base.id, enable); |
Lloyd Atkinson | dcb1c4a | 2017-07-27 10:52:09 -0400 | [diff] [blame] | 2859 | else if (sde_crtc->enabled && sde_crtc->vblank_requested) { |
| 2860 | ret = _sde_crtc_vblank_enable_no_lock(sde_crtc, !enable); |
| 2861 | if (ret) |
| 2862 | SDE_ERROR("%s vblank enable failed: %d\n", |
| 2863 | sde_crtc->name, ret); |
| 2864 | } |
Clarence Ip | 7f70ce4 | 2017-03-20 06:53:46 -0700 | [diff] [blame] | 2865 | |
| 2866 | sde_crtc->suspend = enable; |
Clarence Ip | 7f70ce4 | 2017-03-20 06:53:46 -0700 | [diff] [blame] | 2867 | mutex_unlock(&sde_crtc->crtc_lock); |
| 2868 | } |
| 2869 | |
| 2870 | /** |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 2871 | * sde_crtc_duplicate_state - state duplicate hook |
| 2872 | * @crtc: Pointer to drm crtc structure |
| 2873 | * @Returns: Pointer to new drm_crtc_state structure |
| 2874 | */ |
| 2875 | static struct drm_crtc_state *sde_crtc_duplicate_state(struct drm_crtc *crtc) |
| 2876 | { |
| 2877 | struct sde_crtc *sde_crtc; |
| 2878 | struct sde_crtc_state *cstate, *old_cstate; |
| 2879 | |
| 2880 | if (!crtc || !crtc->state) { |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 2881 | SDE_ERROR("invalid argument(s)\n"); |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 2882 | return NULL; |
| 2883 | } |
| 2884 | |
| 2885 | sde_crtc = to_sde_crtc(crtc); |
| 2886 | old_cstate = to_sde_crtc_state(crtc->state); |
| 2887 | cstate = msm_property_alloc_state(&sde_crtc->property_info); |
| 2888 | if (!cstate) { |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 2889 | SDE_ERROR("failed to allocate state\n"); |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 2890 | return NULL; |
| 2891 | } |
| 2892 | |
| 2893 | /* duplicate value helper */ |
| 2894 | msm_property_duplicate_state(&sde_crtc->property_info, |
| 2895 | old_cstate, cstate, |
Clarence Ip | 4a2955d | 2017-07-04 18:04:33 -0400 | [diff] [blame] | 2896 | &cstate->property_state, cstate->property_values); |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 2897 | |
| 2898 | /* duplicate base helper */ |
| 2899 | __drm_atomic_helper_crtc_duplicate_state(crtc, &cstate->base); |
| 2900 | |
Alan Kwong | cdb2f28 | 2017-03-18 13:42:06 -0700 | [diff] [blame] | 2901 | _sde_crtc_rp_duplicate(&old_cstate->rp, &cstate->rp); |
| 2902 | |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 2903 | return &cstate->base; |
| 2904 | } |
| 2905 | |
| 2906 | /** |
| 2907 | * sde_crtc_reset - reset hook for CRTCs |
| 2908 | * Resets the atomic state for @crtc by freeing the state pointer (which might |
| 2909 | * be NULL, e.g. at driver load time) and allocating a new empty state object. |
| 2910 | * @crtc: Pointer to drm crtc structure |
| 2911 | */ |
| 2912 | static void sde_crtc_reset(struct drm_crtc *crtc) |
| 2913 | { |
| 2914 | struct sde_crtc *sde_crtc; |
| 2915 | struct sde_crtc_state *cstate; |
| 2916 | |
| 2917 | if (!crtc) { |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 2918 | SDE_ERROR("invalid crtc\n"); |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 2919 | return; |
| 2920 | } |
| 2921 | |
Clarence Ip | 7f70ce4 | 2017-03-20 06:53:46 -0700 | [diff] [blame] | 2922 | /* revert suspend actions, if necessary */ |
Clarence Ip | d86f6e4 | 2017-08-08 18:31:00 -0400 | [diff] [blame] | 2923 | if (sde_kms_is_suspend_state(crtc->dev)) |
Clarence Ip | 7f70ce4 | 2017-03-20 06:53:46 -0700 | [diff] [blame] | 2924 | _sde_crtc_set_suspend(crtc, false); |
| 2925 | |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 2926 | /* remove previous state, if present */ |
| 2927 | if (crtc->state) { |
| 2928 | sde_crtc_destroy_state(crtc, crtc->state); |
| 2929 | crtc->state = 0; |
| 2930 | } |
| 2931 | |
| 2932 | sde_crtc = to_sde_crtc(crtc); |
| 2933 | cstate = msm_property_alloc_state(&sde_crtc->property_info); |
| 2934 | if (!cstate) { |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 2935 | SDE_ERROR("failed to allocate state\n"); |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 2936 | return; |
| 2937 | } |
| 2938 | |
| 2939 | /* reset value helper */ |
| 2940 | msm_property_reset_state(&sde_crtc->property_info, cstate, |
Clarence Ip | 4a2955d | 2017-07-04 18:04:33 -0400 | [diff] [blame] | 2941 | &cstate->property_state, |
| 2942 | cstate->property_values); |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 2943 | |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 2944 | _sde_crtc_set_input_fence_timeout(cstate); |
| 2945 | |
Alan Kwong | 310e9b0 | 2017-08-03 02:04:07 -0400 | [diff] [blame] | 2946 | _sde_crtc_rp_reset(&cstate->rp, &sde_crtc->rp_lock, |
| 2947 | &sde_crtc->rp_head); |
Alan Kwong | cdb2f28 | 2017-03-18 13:42:06 -0700 | [diff] [blame] | 2948 | |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 2949 | cstate->base.crtc = crtc; |
| 2950 | crtc->state = &cstate->base; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 2951 | } |
| 2952 | |
Veera Sundaram Sankaran | 82916e0 | 2017-03-29 18:44:22 -0700 | [diff] [blame] | 2953 | static void sde_crtc_handle_power_event(u32 event_type, void *arg) |
| 2954 | { |
| 2955 | struct drm_crtc *crtc = arg; |
| 2956 | struct sde_crtc *sde_crtc; |
Dhaval Patel | 010f517 | 2017-08-01 22:40:09 -0700 | [diff] [blame] | 2957 | struct drm_plane *plane; |
Veera Sundaram Sankaran | 82916e0 | 2017-03-29 18:44:22 -0700 | [diff] [blame] | 2958 | struct drm_encoder *encoder; |
Dhaval Patel | 010f517 | 2017-08-01 22:40:09 -0700 | [diff] [blame] | 2959 | struct sde_crtc_mixer *m; |
Benjamin Chan | 9013910 | 2017-06-21 16:00:39 -0400 | [diff] [blame] | 2960 | struct drm_event event; |
Dhaval Patel | 010f517 | 2017-08-01 22:40:09 -0700 | [diff] [blame] | 2961 | u32 power_on = 0, i, misr_status; |
Veera Sundaram Sankaran | 82916e0 | 2017-03-29 18:44:22 -0700 | [diff] [blame] | 2962 | |
| 2963 | if (!crtc) { |
| 2964 | SDE_ERROR("invalid crtc\n"); |
| 2965 | return; |
| 2966 | } |
| 2967 | sde_crtc = to_sde_crtc(crtc); |
| 2968 | |
| 2969 | mutex_lock(&sde_crtc->crtc_lock); |
| 2970 | |
| 2971 | SDE_EVT32(DRMID(crtc), event_type); |
| 2972 | |
Dhaval Patel | 010f517 | 2017-08-01 22:40:09 -0700 | [diff] [blame] | 2973 | switch (event_type) { |
| 2974 | case SDE_POWER_EVENT_POST_ENABLE: |
Veera Sundaram Sankaran | 82916e0 | 2017-03-29 18:44:22 -0700 | [diff] [blame] | 2975 | /* restore encoder; crtc will be programmed during commit */ |
| 2976 | drm_for_each_encoder(encoder, crtc->dev) { |
| 2977 | if (encoder->crtc != crtc) |
| 2978 | continue; |
| 2979 | |
| 2980 | sde_encoder_virt_restore(encoder); |
| 2981 | } |
Ping Li | e505f3b | 2017-06-19 14:19:08 -0700 | [diff] [blame] | 2982 | sde_cp_crtc_post_ipc(crtc); |
Veera Sundaram Sankaran | 82916e0 | 2017-03-29 18:44:22 -0700 | [diff] [blame] | 2983 | |
Benjamin Chan | 9013910 | 2017-06-21 16:00:39 -0400 | [diff] [blame] | 2984 | event.type = DRM_EVENT_SDE_POWER; |
| 2985 | event.length = sizeof(power_on); |
| 2986 | power_on = 1; |
| 2987 | msm_mode_object_event_notify(&crtc->base, crtc->dev, &event, |
| 2988 | (u8 *)&power_on); |
Veera Sundaram Sankaran | 82916e0 | 2017-03-29 18:44:22 -0700 | [diff] [blame] | 2989 | |
Dhaval Patel | 010f517 | 2017-08-01 22:40:09 -0700 | [diff] [blame] | 2990 | for (i = 0; i < sde_crtc->num_mixers; ++i) { |
| 2991 | m = &sde_crtc->mixers[i]; |
| 2992 | if (!m->hw_lm || !m->hw_lm->ops.setup_misr || |
| 2993 | !sde_crtc->misr_enable) |
| 2994 | continue; |
| 2995 | |
| 2996 | m->hw_lm->ops.setup_misr(m->hw_lm, true, |
| 2997 | sde_crtc->misr_frame_count); |
| 2998 | } |
| 2999 | break; |
| 3000 | case SDE_POWER_EVENT_PRE_DISABLE: |
| 3001 | for (i = 0; i < sde_crtc->num_mixers; ++i) { |
| 3002 | m = &sde_crtc->mixers[i]; |
| 3003 | if (!m->hw_lm || !m->hw_lm->ops.collect_misr || |
| 3004 | !sde_crtc->misr_enable) |
| 3005 | continue; |
| 3006 | |
| 3007 | misr_status = m->hw_lm->ops.collect_misr(m->hw_lm); |
| 3008 | sde_crtc->misr_data[i] = misr_status ? misr_status : |
| 3009 | sde_crtc->misr_data[i]; |
| 3010 | } |
| 3011 | sde_cp_crtc_pre_ipc(crtc); |
| 3012 | break; |
| 3013 | case SDE_POWER_EVENT_POST_DISABLE: |
Veera Sundaram Sankaran | 82916e0 | 2017-03-29 18:44:22 -0700 | [diff] [blame] | 3014 | /* |
| 3015 | * set revalidate flag in planes, so it will be re-programmed |
| 3016 | * in the next frame update |
| 3017 | */ |
| 3018 | drm_atomic_crtc_for_each_plane(plane, crtc) |
| 3019 | sde_plane_set_revalidate(plane, true); |
Alan Kwong | 8a9b38a | 2017-06-22 11:30:52 -0400 | [diff] [blame] | 3020 | |
Gopikrishnaiah Anandan | db90fa1 | 2017-05-09 17:56:08 -0700 | [diff] [blame] | 3021 | sde_cp_crtc_suspend(crtc); |
Benjamin Chan | 9013910 | 2017-06-21 16:00:39 -0400 | [diff] [blame] | 3022 | |
| 3023 | event.type = DRM_EVENT_SDE_POWER; |
| 3024 | event.length = sizeof(power_on); |
| 3025 | power_on = 0; |
| 3026 | msm_mode_object_event_notify(&crtc->base, crtc->dev, &event, |
| 3027 | (u8 *)&power_on); |
Dhaval Patel | 010f517 | 2017-08-01 22:40:09 -0700 | [diff] [blame] | 3028 | break; |
| 3029 | default: |
| 3030 | SDE_DEBUG("event:%d not handled\n", event_type); |
| 3031 | break; |
Veera Sundaram Sankaran | 82916e0 | 2017-03-29 18:44:22 -0700 | [diff] [blame] | 3032 | } |
| 3033 | |
| 3034 | mutex_unlock(&sde_crtc->crtc_lock); |
| 3035 | } |
| 3036 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 3037 | static void sde_crtc_disable(struct drm_crtc *crtc) |
| 3038 | { |
Lloyd Atkinson | c44a52e | 2016-08-16 16:40:17 -0400 | [diff] [blame] | 3039 | struct sde_crtc *sde_crtc; |
Dhaval Patel | 82c8dbc | 2017-02-18 23:15:10 -0800 | [diff] [blame] | 3040 | struct sde_crtc_state *cstate; |
Alan Kwong | 07da098 | 2016-11-04 12:57:45 -0400 | [diff] [blame] | 3041 | struct drm_encoder *encoder; |
Veera Sundaram Sankaran | 82916e0 | 2017-03-29 18:44:22 -0700 | [diff] [blame] | 3042 | struct msm_drm_private *priv; |
Gopikrishnaiah Anandan | de2c81b | 2017-03-15 12:41:29 -0700 | [diff] [blame] | 3043 | unsigned long flags; |
| 3044 | struct sde_crtc_irq_info *node = NULL; |
Ping Li | c5c2e0b | 2017-08-02 15:17:59 -0700 | [diff] [blame] | 3045 | struct drm_event event; |
| 3046 | u32 power_on; |
Dhaval Patel | fd8f774 | 2017-08-10 13:11:22 -0700 | [diff] [blame] | 3047 | int ret, i; |
Lloyd Atkinson | c44a52e | 2016-08-16 16:40:17 -0400 | [diff] [blame] | 3048 | |
Veera Sundaram Sankaran | 82916e0 | 2017-03-29 18:44:22 -0700 | [diff] [blame] | 3049 | if (!crtc || !crtc->dev || !crtc->dev->dev_private || !crtc->state) { |
Lloyd Atkinson | 4f1c869 | 2016-09-14 14:04:25 -0400 | [diff] [blame] | 3050 | SDE_ERROR("invalid crtc\n"); |
Lloyd Atkinson | c44a52e | 2016-08-16 16:40:17 -0400 | [diff] [blame] | 3051 | return; |
| 3052 | } |
| 3053 | sde_crtc = to_sde_crtc(crtc); |
Dhaval Patel | 82c8dbc | 2017-02-18 23:15:10 -0800 | [diff] [blame] | 3054 | cstate = to_sde_crtc_state(crtc->state); |
Veera Sundaram Sankaran | 82916e0 | 2017-03-29 18:44:22 -0700 | [diff] [blame] | 3055 | priv = crtc->dev->dev_private; |
Lloyd Atkinson | c44a52e | 2016-08-16 16:40:17 -0400 | [diff] [blame] | 3056 | |
Alan Kwong | 163d261 | 2016-11-03 00:56:56 -0400 | [diff] [blame] | 3057 | SDE_DEBUG("crtc%d\n", crtc->base.id); |
Lloyd Atkinson | c44a52e | 2016-08-16 16:40:17 -0400 | [diff] [blame] | 3058 | |
Clarence Ip | d86f6e4 | 2017-08-08 18:31:00 -0400 | [diff] [blame] | 3059 | if (sde_kms_is_suspend_state(crtc->dev)) |
Clarence Ip | 7f70ce4 | 2017-03-20 06:53:46 -0700 | [diff] [blame] | 3060 | _sde_crtc_set_suspend(crtc, true); |
| 3061 | |
Dhaval Patel | 3fbe6bf | 2016-10-20 20:00:41 -0700 | [diff] [blame] | 3062 | mutex_lock(&sde_crtc->crtc_lock); |
Lloyd Atkinson | dcb1c4a | 2017-07-27 10:52:09 -0400 | [diff] [blame] | 3063 | SDE_EVT32_VERBOSE(DRMID(crtc)); |
Alan Kwong | 628d19e | 2016-10-31 13:50:13 -0400 | [diff] [blame] | 3064 | |
Ping Li | c5c2e0b | 2017-08-02 15:17:59 -0700 | [diff] [blame] | 3065 | /* update color processing on suspend */ |
| 3066 | event.type = DRM_EVENT_CRTC_POWER; |
| 3067 | event.length = sizeof(u32); |
| 3068 | sde_cp_crtc_suspend(crtc); |
| 3069 | power_on = 0; |
| 3070 | msm_mode_object_event_notify(&crtc->base, crtc->dev, &event, |
| 3071 | (u8 *)&power_on); |
| 3072 | |
Veera Sundaram Sankaran | 7ee9909 | 2017-06-13 11:19:36 -0700 | [diff] [blame] | 3073 | /* wait for frame_event_done completion */ |
| 3074 | if (_sde_crtc_wait_for_frame_done(crtc)) |
| 3075 | SDE_ERROR("crtc%d wait for frame done failed;frame_pending%d\n", |
| 3076 | crtc->base.id, |
| 3077 | atomic_read(&sde_crtc->frame_pending)); |
| 3078 | |
Lloyd Atkinson | dcb1c4a | 2017-07-27 10:52:09 -0400 | [diff] [blame] | 3079 | SDE_EVT32(DRMID(crtc), sde_crtc->enabled, sde_crtc->suspend, |
| 3080 | sde_crtc->vblank_requested); |
| 3081 | if (sde_crtc->enabled && !sde_crtc->suspend && |
| 3082 | sde_crtc->vblank_requested) { |
| 3083 | ret = _sde_crtc_vblank_enable_no_lock(sde_crtc, false); |
| 3084 | if (ret) |
| 3085 | SDE_ERROR("%s vblank enable failed: %d\n", |
| 3086 | sde_crtc->name, ret); |
Alan Kwong | 07da098 | 2016-11-04 12:57:45 -0400 | [diff] [blame] | 3087 | } |
Lloyd Atkinson | dcb1c4a | 2017-07-27 10:52:09 -0400 | [diff] [blame] | 3088 | sde_crtc->enabled = false; |
Alan Kwong | 07da098 | 2016-11-04 12:57:45 -0400 | [diff] [blame] | 3089 | |
Alan Kwong | 628d19e | 2016-10-31 13:50:13 -0400 | [diff] [blame] | 3090 | if (atomic_read(&sde_crtc->frame_pending)) { |
Dhaval Patel | 6c66662 | 2017-03-21 23:02:59 -0700 | [diff] [blame] | 3091 | SDE_EVT32(DRMID(crtc), atomic_read(&sde_crtc->frame_pending), |
| 3092 | SDE_EVTLOG_FUNC_CASE2); |
Alan Kwong | 9aa061c | 2016-11-06 21:17:12 -0500 | [diff] [blame] | 3093 | sde_core_perf_crtc_release_bw(crtc); |
Alan Kwong | 628d19e | 2016-10-31 13:50:13 -0400 | [diff] [blame] | 3094 | atomic_set(&sde_crtc->frame_pending, 0); |
| 3095 | } |
| 3096 | |
Ping Li | 6d5bf54 | 2017-06-27 11:40:28 -0700 | [diff] [blame] | 3097 | spin_lock_irqsave(&sde_crtc->spin_lock, flags); |
| 3098 | list_for_each_entry(node, &sde_crtc->user_event_list, list) { |
| 3099 | ret = 0; |
| 3100 | if (node->func) |
| 3101 | ret = node->func(crtc, false, &node->irq); |
| 3102 | if (ret) |
| 3103 | SDE_ERROR("%s failed to disable event %x\n", |
| 3104 | sde_crtc->name, node->event); |
| 3105 | } |
| 3106 | spin_unlock_irqrestore(&sde_crtc->spin_lock, flags); |
| 3107 | |
Alan Kwong | 9aa061c | 2016-11-06 21:17:12 -0500 | [diff] [blame] | 3108 | sde_core_perf_crtc_update(crtc, 0, true); |
| 3109 | |
Alan Kwong | 628d19e | 2016-10-31 13:50:13 -0400 | [diff] [blame] | 3110 | drm_for_each_encoder(encoder, crtc->dev) { |
| 3111 | if (encoder->crtc != crtc) |
| 3112 | continue; |
| 3113 | sde_encoder_register_frame_event_callback(encoder, NULL, NULL); |
Dhaval Patel | 82c8dbc | 2017-02-18 23:15:10 -0800 | [diff] [blame] | 3114 | cstate->rsc_client = NULL; |
| 3115 | cstate->rsc_update = false; |
Alan Kwong | 628d19e | 2016-10-31 13:50:13 -0400 | [diff] [blame] | 3116 | } |
| 3117 | |
Veera Sundaram Sankaran | 82916e0 | 2017-03-29 18:44:22 -0700 | [diff] [blame] | 3118 | if (sde_crtc->power_event) |
| 3119 | sde_power_handle_unregister_event(&priv->phandle, |
| 3120 | sde_crtc->power_event); |
| 3121 | |
Dhaval Patel | fd8f774 | 2017-08-10 13:11:22 -0700 | [diff] [blame] | 3122 | /** |
| 3123 | * All callbacks are unregistered and frame done waits are complete |
| 3124 | * at this point. No buffers are accessed by hardware. |
| 3125 | * reset the fence timeline if there is any issue. |
| 3126 | */ |
| 3127 | sde_fence_signal(&sde_crtc->output_fence, ktime_get(), true); |
| 3128 | for (i = 0; i < cstate->num_connectors; ++i) |
| 3129 | sde_connector_commit_reset(cstate->connectors[i], ktime_get()); |
| 3130 | |
Lloyd Atkinson | c44a52e | 2016-08-16 16:40:17 -0400 | [diff] [blame] | 3131 | memset(sde_crtc->mixers, 0, sizeof(sde_crtc->mixers)); |
| 3132 | sde_crtc->num_mixers = 0; |
Gopikrishnaiah Anandan | de2c81b | 2017-03-15 12:41:29 -0700 | [diff] [blame] | 3133 | |
Alan Kwong | 8411a911 | 2017-06-06 19:29:01 -0400 | [diff] [blame] | 3134 | /* disable clk & bw control until clk & bw properties are set */ |
| 3135 | cstate->bw_control = false; |
Alan Kwong | 0230a10 | 2017-05-16 11:36:44 -0700 | [diff] [blame] | 3136 | cstate->bw_split_vote = false; |
Alan Kwong | 8411a911 | 2017-06-06 19:29:01 -0400 | [diff] [blame] | 3137 | |
Dhaval Patel | 3fbe6bf | 2016-10-20 20:00:41 -0700 | [diff] [blame] | 3138 | mutex_unlock(&sde_crtc->crtc_lock); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 3139 | } |
| 3140 | |
| 3141 | static void sde_crtc_enable(struct drm_crtc *crtc) |
| 3142 | { |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 3143 | struct sde_crtc *sde_crtc; |
Alan Kwong | 628d19e | 2016-10-31 13:50:13 -0400 | [diff] [blame] | 3144 | struct drm_encoder *encoder; |
Veera Sundaram Sankaran | 82916e0 | 2017-03-29 18:44:22 -0700 | [diff] [blame] | 3145 | struct msm_drm_private *priv; |
Gopikrishnaiah Anandan | de2c81b | 2017-03-15 12:41:29 -0700 | [diff] [blame] | 3146 | unsigned long flags; |
| 3147 | struct sde_crtc_irq_info *node = NULL; |
Ping Li | c5c2e0b | 2017-08-02 15:17:59 -0700 | [diff] [blame] | 3148 | struct drm_event event; |
| 3149 | u32 power_on; |
Lloyd Atkinson | a9d7e75 | 2017-01-17 16:31:43 -0500 | [diff] [blame] | 3150 | int ret; |
Lloyd Atkinson | af7952d | 2016-06-26 22:41:26 -0400 | [diff] [blame] | 3151 | |
Veera Sundaram Sankaran | 82916e0 | 2017-03-29 18:44:22 -0700 | [diff] [blame] | 3152 | if (!crtc || !crtc->dev || !crtc->dev->dev_private) { |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 3153 | SDE_ERROR("invalid crtc\n"); |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 3154 | return; |
| 3155 | } |
Veera Sundaram Sankaran | 82916e0 | 2017-03-29 18:44:22 -0700 | [diff] [blame] | 3156 | priv = crtc->dev->dev_private; |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 3157 | |
Alan Kwong | 163d261 | 2016-11-03 00:56:56 -0400 | [diff] [blame] | 3158 | SDE_DEBUG("crtc%d\n", crtc->base.id); |
Lloyd Atkinson | dcb1c4a | 2017-07-27 10:52:09 -0400 | [diff] [blame] | 3159 | SDE_EVT32_VERBOSE(DRMID(crtc)); |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 3160 | sde_crtc = to_sde_crtc(crtc); |
Lloyd Atkinson | af7952d | 2016-06-26 22:41:26 -0400 | [diff] [blame] | 3161 | |
Alan Kwong | 628d19e | 2016-10-31 13:50:13 -0400 | [diff] [blame] | 3162 | drm_for_each_encoder(encoder, crtc->dev) { |
| 3163 | if (encoder->crtc != crtc) |
| 3164 | continue; |
| 3165 | sde_encoder_register_frame_event_callback(encoder, |
| 3166 | sde_crtc_frame_event_cb, (void *)crtc); |
| 3167 | } |
| 3168 | |
Lloyd Atkinson | b2be0c4 | 2017-07-17 16:41:00 -0400 | [diff] [blame] | 3169 | mutex_lock(&sde_crtc->crtc_lock); |
Lloyd Atkinson | dcb1c4a | 2017-07-27 10:52:09 -0400 | [diff] [blame] | 3170 | SDE_EVT32(DRMID(crtc), sde_crtc->enabled, sde_crtc->suspend, |
| 3171 | sde_crtc->vblank_requested); |
| 3172 | if (!sde_crtc->enabled && !sde_crtc->suspend && |
| 3173 | sde_crtc->vblank_requested) { |
| 3174 | ret = _sde_crtc_vblank_enable_no_lock(sde_crtc, true); |
| 3175 | if (ret) |
| 3176 | SDE_ERROR("%s vblank enable failed: %d\n", |
| 3177 | sde_crtc->name, ret); |
Lloyd Atkinson | b2be0c4 | 2017-07-17 16:41:00 -0400 | [diff] [blame] | 3178 | } |
Lloyd Atkinson | dcb1c4a | 2017-07-27 10:52:09 -0400 | [diff] [blame] | 3179 | sde_crtc->enabled = true; |
Ping Li | c5c2e0b | 2017-08-02 15:17:59 -0700 | [diff] [blame] | 3180 | |
| 3181 | /* update color processing on resume */ |
| 3182 | event.type = DRM_EVENT_CRTC_POWER; |
| 3183 | event.length = sizeof(u32); |
| 3184 | sde_cp_crtc_resume(crtc); |
| 3185 | power_on = 1; |
| 3186 | msm_mode_object_event_notify(&crtc->base, crtc->dev, &event, |
| 3187 | (u8 *)&power_on); |
| 3188 | |
Lloyd Atkinson | b2be0c4 | 2017-07-17 16:41:00 -0400 | [diff] [blame] | 3189 | mutex_unlock(&sde_crtc->crtc_lock); |
| 3190 | |
Gopikrishnaiah Anandan | de2c81b | 2017-03-15 12:41:29 -0700 | [diff] [blame] | 3191 | spin_lock_irqsave(&sde_crtc->spin_lock, flags); |
| 3192 | list_for_each_entry(node, &sde_crtc->user_event_list, list) { |
| 3193 | ret = 0; |
| 3194 | if (node->func) |
| 3195 | ret = node->func(crtc, true, &node->irq); |
| 3196 | if (ret) |
| 3197 | SDE_ERROR("%s failed to enable event %x\n", |
| 3198 | sde_crtc->name, node->event); |
| 3199 | } |
| 3200 | spin_unlock_irqrestore(&sde_crtc->spin_lock, flags); |
Veera Sundaram Sankaran | 82916e0 | 2017-03-29 18:44:22 -0700 | [diff] [blame] | 3201 | |
| 3202 | sde_crtc->power_event = sde_power_handle_register_event( |
| 3203 | &priv->phandle, |
Ping Li | e505f3b | 2017-06-19 14:19:08 -0700 | [diff] [blame] | 3204 | SDE_POWER_EVENT_POST_ENABLE | SDE_POWER_EVENT_POST_DISABLE | |
| 3205 | SDE_POWER_EVENT_PRE_DISABLE, |
Veera Sundaram Sankaran | 82916e0 | 2017-03-29 18:44:22 -0700 | [diff] [blame] | 3206 | sde_crtc_handle_power_event, crtc, sde_crtc->name); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 3207 | } |
| 3208 | |
| 3209 | struct plane_state { |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 3210 | struct sde_plane_state *sde_pstate; |
Dhaval Patel | 04c7e8e | 2016-09-26 20:14:31 -0700 | [diff] [blame] | 3211 | const struct drm_plane_state *drm_pstate; |
Clarence Ip | c47a069 | 2016-10-11 10:54:17 -0400 | [diff] [blame] | 3212 | int stage; |
Jeykumar Sankaran | 2e65503 | 2017-02-04 14:05:45 -0800 | [diff] [blame] | 3213 | u32 pipe_id; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 3214 | }; |
| 3215 | |
Clarence Ip | c47a069 | 2016-10-11 10:54:17 -0400 | [diff] [blame] | 3216 | static int pstate_cmp(const void *a, const void *b) |
| 3217 | { |
| 3218 | struct plane_state *pa = (struct plane_state *)a; |
| 3219 | struct plane_state *pb = (struct plane_state *)b; |
| 3220 | int rc = 0; |
| 3221 | int pa_zpos, pb_zpos; |
| 3222 | |
| 3223 | pa_zpos = sde_plane_get_property(pa->sde_pstate, PLANE_PROP_ZPOS); |
| 3224 | pb_zpos = sde_plane_get_property(pb->sde_pstate, PLANE_PROP_ZPOS); |
| 3225 | |
| 3226 | if (pa_zpos != pb_zpos) |
| 3227 | rc = pa_zpos - pb_zpos; |
| 3228 | else |
| 3229 | rc = pa->drm_pstate->crtc_x - pb->drm_pstate->crtc_x; |
| 3230 | |
| 3231 | return rc; |
| 3232 | } |
| 3233 | |
Dhaval Patel | a8d6bc6 | 2017-05-10 17:40:18 -0700 | [diff] [blame] | 3234 | static int _sde_crtc_excl_rect_overlap_check(struct plane_state pstates[], |
| 3235 | int cnt, int curr_cnt, struct sde_rect *excl_rect, int z_pos) |
| 3236 | { |
| 3237 | struct sde_rect dst_rect, intersect; |
| 3238 | int i, rc = -EINVAL; |
| 3239 | const struct drm_plane_state *pstate; |
| 3240 | |
| 3241 | /* start checking from next plane */ |
| 3242 | for (i = curr_cnt; i < cnt; i++) { |
| 3243 | pstate = pstates[i].drm_pstate; |
| 3244 | POPULATE_RECT(&dst_rect, pstate->crtc_x, pstate->crtc_y, |
Veera Sundaram Sankaran | 9d9ff91 | 2017-06-20 10:41:21 -0700 | [diff] [blame] | 3245 | pstate->crtc_w, pstate->crtc_h, false); |
Dhaval Patel | a8d6bc6 | 2017-05-10 17:40:18 -0700 | [diff] [blame] | 3246 | sde_kms_rect_intersect(&dst_rect, excl_rect, &intersect); |
| 3247 | |
| 3248 | if (intersect.w == excl_rect->w && intersect.h == excl_rect->h |
| 3249 | /* next plane may be on same z-order */ |
| 3250 | && z_pos != pstates[i].stage) { |
| 3251 | rc = 0; |
| 3252 | goto end; |
| 3253 | } |
| 3254 | } |
| 3255 | |
| 3256 | SDE_ERROR("excl rect does not find top overlapping rect\n"); |
| 3257 | end: |
| 3258 | return rc; |
| 3259 | } |
| 3260 | |
| 3261 | /* no input validation - caller API has all the checks */ |
| 3262 | static int _sde_crtc_excl_dim_layer_check(struct drm_crtc_state *state, |
| 3263 | struct plane_state pstates[], int cnt) |
| 3264 | { |
| 3265 | struct sde_crtc_state *cstate = to_sde_crtc_state(state); |
| 3266 | struct drm_display_mode *mode = &state->adjusted_mode; |
| 3267 | const struct drm_plane_state *pstate; |
| 3268 | struct sde_plane_state *sde_pstate; |
| 3269 | int rc = 0, i; |
| 3270 | |
| 3271 | /* Check dim layer rect bounds and stage */ |
| 3272 | for (i = 0; i < cstate->num_dim_layers; i++) { |
| 3273 | if ((CHECK_LAYER_BOUNDS(cstate->dim_layer[i].rect.y, |
| 3274 | cstate->dim_layer[i].rect.h, mode->vdisplay)) || |
| 3275 | (CHECK_LAYER_BOUNDS(cstate->dim_layer[i].rect.x, |
| 3276 | cstate->dim_layer[i].rect.w, mode->hdisplay)) || |
| 3277 | (cstate->dim_layer[i].stage >= SDE_STAGE_MAX) || |
| 3278 | (!cstate->dim_layer[i].rect.w) || |
| 3279 | (!cstate->dim_layer[i].rect.h)) { |
| 3280 | SDE_ERROR("invalid dim_layer:{%d,%d,%d,%d}, stage:%d\n", |
| 3281 | cstate->dim_layer[i].rect.x, |
| 3282 | cstate->dim_layer[i].rect.y, |
| 3283 | cstate->dim_layer[i].rect.w, |
| 3284 | cstate->dim_layer[i].rect.h, |
| 3285 | cstate->dim_layer[i].stage); |
| 3286 | SDE_ERROR("display: %dx%d\n", mode->hdisplay, |
| 3287 | mode->vdisplay); |
| 3288 | rc = -E2BIG; |
| 3289 | goto end; |
| 3290 | } |
| 3291 | } |
| 3292 | |
| 3293 | /* this is traversing on sorted z-order pstates */ |
| 3294 | for (i = 0; i < cnt; i++) { |
| 3295 | pstate = pstates[i].drm_pstate; |
| 3296 | sde_pstate = to_sde_plane_state(pstate); |
| 3297 | if (sde_pstate->excl_rect.w && sde_pstate->excl_rect.h) { |
| 3298 | /* check overlap on all top z-order */ |
| 3299 | rc = _sde_crtc_excl_rect_overlap_check(pstates, cnt, |
| 3300 | i + 1, &sde_pstate->excl_rect, pstates[i].stage); |
| 3301 | if (rc) |
| 3302 | goto end; |
| 3303 | } |
| 3304 | } |
| 3305 | |
| 3306 | end: |
| 3307 | return rc; |
| 3308 | } |
| 3309 | |
Abhijit Kulkarni | 7444a7d | 2017-06-21 18:53:36 -0700 | [diff] [blame] | 3310 | static int _sde_crtc_check_secure_state(struct drm_crtc *crtc, |
| 3311 | struct drm_crtc_state *state) |
| 3312 | { |
| 3313 | struct drm_encoder *encoder; |
| 3314 | struct sde_crtc_state *cstate; |
| 3315 | uint32_t secure; |
| 3316 | uint32_t fb_ns = 0, fb_sec = 0, fb_ns_dir = 0, fb_sec_dir = 0; |
| 3317 | int encoder_cnt = 0; |
| 3318 | int rc; |
| 3319 | |
| 3320 | if (!crtc || !state) { |
| 3321 | SDE_ERROR("invalid arguments\n"); |
| 3322 | return -EINVAL; |
| 3323 | } |
| 3324 | |
| 3325 | cstate = to_sde_crtc_state(state); |
| 3326 | |
| 3327 | secure = sde_crtc_get_property(cstate, |
| 3328 | CRTC_PROP_SECURITY_LEVEL); |
| 3329 | |
| 3330 | rc = _sde_crtc_find_plane_fb_modes(state, |
| 3331 | &fb_ns, |
| 3332 | &fb_sec, |
| 3333 | &fb_ns_dir, |
| 3334 | &fb_sec_dir); |
| 3335 | if (rc) |
| 3336 | return rc; |
| 3337 | |
| 3338 | /** |
| 3339 | * validate planes |
| 3340 | * fb_ns_dir is for secure display use case, |
| 3341 | * fb_sec_dir is for secure camera preview use case, |
| 3342 | * fb_sec is for secure video playback, |
| 3343 | * fb_ns is for normal non secure use cases. |
| 3344 | */ |
| 3345 | if (((secure == SDE_DRM_SEC_ONLY) && |
| 3346 | (fb_ns || fb_sec || fb_sec_dir)) || |
Veera Sundaram Sankaran | 91714e4 | 2017-08-14 22:35:28 -0700 | [diff] [blame] | 3347 | (fb_sec && fb_sec_dir)) { |
Abhijit Kulkarni | 7444a7d | 2017-06-21 18:53:36 -0700 | [diff] [blame] | 3348 | SDE_ERROR( |
| 3349 | "crtc%d: invalid planes fb_modes Sec:%d, NS:%d, Sec_Dir:%d, NS_Dir%d\n", |
| 3350 | crtc->base.id, |
| 3351 | fb_sec, fb_ns, fb_sec_dir, |
| 3352 | fb_ns_dir); |
| 3353 | return -EINVAL; |
| 3354 | } |
| 3355 | |
| 3356 | /** |
| 3357 | * secure_crtc is not allowed in a shared toppolgy |
| 3358 | * across different encoders. |
| 3359 | */ |
| 3360 | if (fb_ns_dir || fb_sec_dir) { |
| 3361 | drm_for_each_encoder(encoder, crtc->dev) |
| 3362 | if (encoder->crtc == crtc) |
| 3363 | encoder_cnt++; |
| 3364 | |
| 3365 | if (encoder_cnt > |
| 3366 | MAX_ALLOWED_ENCODER_CNT_PER_SECURE_CRTC) { |
| 3367 | SDE_ERROR( |
| 3368 | "crtc%d, invalid virtual encoder crtc%d\n", |
| 3369 | crtc->base.id, |
| 3370 | encoder_cnt); |
| 3371 | return -EINVAL; |
| 3372 | |
| 3373 | } |
| 3374 | } |
| 3375 | SDE_DEBUG("crtc:%d Secure validation successful\n", crtc->base.id); |
| 3376 | return 0; |
| 3377 | } |
| 3378 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 3379 | static int sde_crtc_atomic_check(struct drm_crtc *crtc, |
| 3380 | struct drm_crtc_state *state) |
| 3381 | { |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 3382 | struct sde_crtc *sde_crtc; |
Jeykumar Sankaran | 2e65503 | 2017-02-04 14:05:45 -0800 | [diff] [blame] | 3383 | struct plane_state pstates[SDE_STAGE_MAX * 4]; |
Veera Sundaram Sankaran | 3171ff8 | 2017-01-04 14:34:47 -0800 | [diff] [blame] | 3384 | struct sde_crtc_state *cstate; |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 3385 | |
Dhaval Patel | 04c7e8e | 2016-09-26 20:14:31 -0700 | [diff] [blame] | 3386 | const struct drm_plane_state *pstate; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 3387 | struct drm_plane *plane; |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 3388 | struct drm_display_mode *mode; |
| 3389 | |
| 3390 | int cnt = 0, rc = 0, mixer_width, i, z_pos; |
Jeykumar Sankaran | 2e65503 | 2017-02-04 14:05:45 -0800 | [diff] [blame] | 3391 | |
Jeykumar Sankaran | 2e65503 | 2017-02-04 14:05:45 -0800 | [diff] [blame] | 3392 | struct sde_multirect_plane_states multirect_plane[SDE_STAGE_MAX * 2]; |
| 3393 | int multirect_count = 0; |
| 3394 | const struct drm_plane_state *pipe_staged[SSPP_MAX]; |
Lloyd Atkinson | 629ce1f | 2016-10-27 16:50:26 -0400 | [diff] [blame] | 3395 | int left_zpos_cnt = 0, right_zpos_cnt = 0; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 3396 | |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 3397 | if (!crtc) { |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 3398 | SDE_ERROR("invalid crtc\n"); |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 3399 | return -EINVAL; |
| 3400 | } |
| 3401 | |
Alan Kwong | cdb2f28 | 2017-03-18 13:42:06 -0700 | [diff] [blame] | 3402 | sde_crtc = to_sde_crtc(crtc); |
| 3403 | cstate = to_sde_crtc_state(state); |
| 3404 | |
Lloyd Atkinson | 5217336c | 2016-09-15 18:21:18 -0400 | [diff] [blame] | 3405 | if (!state->enable || !state->active) { |
| 3406 | SDE_DEBUG("crtc%d -> enable %d, active %d, skip atomic_check\n", |
| 3407 | crtc->base.id, state->enable, state->active); |
Alan Kwong | cdb2f28 | 2017-03-18 13:42:06 -0700 | [diff] [blame] | 3408 | goto end; |
Lloyd Atkinson | 5217336c | 2016-09-15 18:21:18 -0400 | [diff] [blame] | 3409 | } |
| 3410 | |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 3411 | mode = &state->adjusted_mode; |
| 3412 | SDE_DEBUG("%s: check", sde_crtc->name); |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 3413 | |
Clarence Ip | 90b282d | 2017-05-04 10:00:32 -0700 | [diff] [blame] | 3414 | /* force a full mode set if active state changed */ |
| 3415 | if (state->active_changed) |
| 3416 | state->mode_changed = true; |
| 3417 | |
Jeykumar Sankaran | 2e65503 | 2017-02-04 14:05:45 -0800 | [diff] [blame] | 3418 | memset(pipe_staged, 0, sizeof(pipe_staged)); |
| 3419 | |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 3420 | mixer_width = sde_crtc_mixer_width(sde_crtc, mode); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 3421 | |
Lloyd Atkinson | 66e7dde | 2017-02-08 15:52:53 -0500 | [diff] [blame] | 3422 | _sde_crtc_setup_is_ppsplit(state); |
Lloyd Atkinson | a9d7e75 | 2017-01-17 16:31:43 -0500 | [diff] [blame] | 3423 | _sde_crtc_setup_lm_bounds(crtc, state); |
| 3424 | |
Abhijit Kulkarni | 7444a7d | 2017-06-21 18:53:36 -0700 | [diff] [blame] | 3425 | rc = _sde_crtc_check_secure_state(crtc, state); |
| 3426 | if (rc) |
| 3427 | return rc; |
| 3428 | |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 3429 | /* get plane state for all drm planes associated with crtc state */ |
Dhaval Patel | 04c7e8e | 2016-09-26 20:14:31 -0700 | [diff] [blame] | 3430 | drm_atomic_crtc_state_for_each_plane_state(plane, pstate, state) { |
Clarence Ip | c47a069 | 2016-10-11 10:54:17 -0400 | [diff] [blame] | 3431 | if (IS_ERR_OR_NULL(pstate)) { |
| 3432 | rc = PTR_ERR(pstate); |
| 3433 | SDE_ERROR("%s: failed to get plane%d state, %d\n", |
| 3434 | sde_crtc->name, plane->base.id, rc); |
Alan Kwong | 8576728 | 2016-10-03 18:03:37 -0400 | [diff] [blame] | 3435 | goto end; |
| 3436 | } |
Clarence Ip | c47a069 | 2016-10-11 10:54:17 -0400 | [diff] [blame] | 3437 | if (cnt >= ARRAY_SIZE(pstates)) |
| 3438 | continue; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 3439 | |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 3440 | pstates[cnt].sde_pstate = to_sde_plane_state(pstate); |
| 3441 | pstates[cnt].drm_pstate = pstate; |
Clarence Ip | c47a069 | 2016-10-11 10:54:17 -0400 | [diff] [blame] | 3442 | pstates[cnt].stage = sde_plane_get_property( |
| 3443 | pstates[cnt].sde_pstate, PLANE_PROP_ZPOS); |
Jeykumar Sankaran | 2e65503 | 2017-02-04 14:05:45 -0800 | [diff] [blame] | 3444 | pstates[cnt].pipe_id = sde_plane_pipe(plane); |
Veera Sundaram Sankaran | 3171ff8 | 2017-01-04 14:34:47 -0800 | [diff] [blame] | 3445 | |
| 3446 | /* check dim layer stage with every plane */ |
| 3447 | for (i = 0; i < cstate->num_dim_layers; i++) { |
Veera Sundaram Sankaran | b9ed6bd | 2017-07-11 19:18:03 -0700 | [diff] [blame] | 3448 | if (cstate->dim_layer[i].stage |
| 3449 | == (pstates[cnt].stage + SDE_STAGE_0)) { |
Veera Sundaram Sankaran | 2cb064f | 2017-05-05 14:12:17 -0700 | [diff] [blame] | 3450 | SDE_ERROR( |
| 3451 | "plane:%d/dim_layer:%i-same stage:%d\n", |
| 3452 | plane->base.id, i, |
| 3453 | cstate->dim_layer[i].stage); |
Veera Sundaram Sankaran | 3171ff8 | 2017-01-04 14:34:47 -0800 | [diff] [blame] | 3454 | rc = -EINVAL; |
| 3455 | goto end; |
| 3456 | } |
| 3457 | } |
| 3458 | |
Jeykumar Sankaran | 2e65503 | 2017-02-04 14:05:45 -0800 | [diff] [blame] | 3459 | if (pipe_staged[pstates[cnt].pipe_id]) { |
| 3460 | multirect_plane[multirect_count].r0 = |
| 3461 | pipe_staged[pstates[cnt].pipe_id]; |
| 3462 | multirect_plane[multirect_count].r1 = pstate; |
| 3463 | multirect_count++; |
| 3464 | |
| 3465 | pipe_staged[pstates[cnt].pipe_id] = NULL; |
| 3466 | } else { |
| 3467 | pipe_staged[pstates[cnt].pipe_id] = pstate; |
| 3468 | } |
| 3469 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 3470 | cnt++; |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 3471 | |
| 3472 | if (CHECK_LAYER_BOUNDS(pstate->crtc_y, pstate->crtc_h, |
| 3473 | mode->vdisplay) || |
| 3474 | CHECK_LAYER_BOUNDS(pstate->crtc_x, pstate->crtc_w, |
| 3475 | mode->hdisplay)) { |
| 3476 | SDE_ERROR("invalid vertical/horizontal destination\n"); |
| 3477 | SDE_ERROR("y:%d h:%d vdisp:%d x:%d w:%d hdisp:%d\n", |
| 3478 | pstate->crtc_y, pstate->crtc_h, mode->vdisplay, |
| 3479 | pstate->crtc_x, pstate->crtc_w, mode->hdisplay); |
| 3480 | rc = -E2BIG; |
| 3481 | goto end; |
| 3482 | } |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 3483 | } |
| 3484 | |
Jeykumar Sankaran | 2e65503 | 2017-02-04 14:05:45 -0800 | [diff] [blame] | 3485 | for (i = 1; i < SSPP_MAX; i++) { |
Jeykumar Sankaran | e964dc7 | 2017-05-10 19:26:43 -0700 | [diff] [blame] | 3486 | if (pipe_staged[i]) { |
| 3487 | sde_plane_clear_multirect(pipe_staged[i]); |
| 3488 | |
| 3489 | if (is_sde_plane_virtual(pipe_staged[i]->plane)) { |
Veera Sundaram Sankaran | 372596d | 2017-06-21 17:57:25 -0700 | [diff] [blame] | 3490 | SDE_ERROR( |
| 3491 | "r1 only virt plane:%d not supported\n", |
Jeykumar Sankaran | 2e65503 | 2017-02-04 14:05:45 -0800 | [diff] [blame] | 3492 | pipe_staged[i]->plane->base.id); |
Veera Sundaram Sankaran | 372596d | 2017-06-21 17:57:25 -0700 | [diff] [blame] | 3493 | rc = -EINVAL; |
Jeykumar Sankaran | e964dc7 | 2017-05-10 19:26:43 -0700 | [diff] [blame] | 3494 | goto end; |
| 3495 | } |
Jeykumar Sankaran | 2e65503 | 2017-02-04 14:05:45 -0800 | [diff] [blame] | 3496 | } |
| 3497 | } |
| 3498 | |
Lloyd Atkinson | 629ce1f | 2016-10-27 16:50:26 -0400 | [diff] [blame] | 3499 | /* assign mixer stages based on sorted zpos property */ |
| 3500 | sort(pstates, cnt, sizeof(pstates[0]), pstate_cmp, NULL); |
| 3501 | |
Dhaval Patel | a8d6bc6 | 2017-05-10 17:40:18 -0700 | [diff] [blame] | 3502 | rc = _sde_crtc_excl_dim_layer_check(state, pstates, cnt); |
| 3503 | if (rc) |
| 3504 | goto end; |
| 3505 | |
Clarence Ip | c47a069 | 2016-10-11 10:54:17 -0400 | [diff] [blame] | 3506 | if (!sde_is_custom_client()) { |
| 3507 | int stage_old = pstates[0].stage; |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 3508 | |
Clarence Ip | c47a069 | 2016-10-11 10:54:17 -0400 | [diff] [blame] | 3509 | z_pos = 0; |
| 3510 | for (i = 0; i < cnt; i++) { |
| 3511 | if (stage_old != pstates[i].stage) |
| 3512 | ++z_pos; |
| 3513 | stage_old = pstates[i].stage; |
| 3514 | pstates[i].stage = z_pos; |
| 3515 | } |
| 3516 | } |
| 3517 | |
Lloyd Atkinson | 629ce1f | 2016-10-27 16:50:26 -0400 | [diff] [blame] | 3518 | z_pos = -1; |
Clarence Ip | c47a069 | 2016-10-11 10:54:17 -0400 | [diff] [blame] | 3519 | for (i = 0; i < cnt; i++) { |
Lloyd Atkinson | 629ce1f | 2016-10-27 16:50:26 -0400 | [diff] [blame] | 3520 | /* reset counts at every new blend stage */ |
| 3521 | if (pstates[i].stage != z_pos) { |
| 3522 | left_zpos_cnt = 0; |
| 3523 | right_zpos_cnt = 0; |
| 3524 | z_pos = pstates[i].stage; |
| 3525 | } |
Clarence Ip | c47a069 | 2016-10-11 10:54:17 -0400 | [diff] [blame] | 3526 | |
| 3527 | /* verify z_pos setting before using it */ |
Clarence Ip | 649989a | 2016-10-21 14:28:34 -0400 | [diff] [blame] | 3528 | if (z_pos >= SDE_STAGE_MAX - SDE_STAGE_0) { |
Clarence Ip | c47a069 | 2016-10-11 10:54:17 -0400 | [diff] [blame] | 3529 | SDE_ERROR("> %d plane stages assigned\n", |
| 3530 | SDE_STAGE_MAX - SDE_STAGE_0); |
| 3531 | rc = -EINVAL; |
| 3532 | goto end; |
| 3533 | } else if (pstates[i].drm_pstate->crtc_x < mixer_width) { |
Lloyd Atkinson | 629ce1f | 2016-10-27 16:50:26 -0400 | [diff] [blame] | 3534 | if (left_zpos_cnt == 2) { |
Jeykumar Sankaran | 2e65503 | 2017-02-04 14:05:45 -0800 | [diff] [blame] | 3535 | SDE_ERROR("> 2 planes @ stage %d on left\n", |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 3536 | z_pos); |
| 3537 | rc = -EINVAL; |
| 3538 | goto end; |
| 3539 | } |
Lloyd Atkinson | 629ce1f | 2016-10-27 16:50:26 -0400 | [diff] [blame] | 3540 | left_zpos_cnt++; |
| 3541 | |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 3542 | } else { |
Lloyd Atkinson | 629ce1f | 2016-10-27 16:50:26 -0400 | [diff] [blame] | 3543 | if (right_zpos_cnt == 2) { |
Jeykumar Sankaran | 2e65503 | 2017-02-04 14:05:45 -0800 | [diff] [blame] | 3544 | SDE_ERROR("> 2 planes @ stage %d on right\n", |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 3545 | z_pos); |
| 3546 | rc = -EINVAL; |
| 3547 | goto end; |
| 3548 | } |
Lloyd Atkinson | 629ce1f | 2016-10-27 16:50:26 -0400 | [diff] [blame] | 3549 | right_zpos_cnt++; |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 3550 | } |
Lloyd Atkinson | 629ce1f | 2016-10-27 16:50:26 -0400 | [diff] [blame] | 3551 | |
Clarence Ip | c47a069 | 2016-10-11 10:54:17 -0400 | [diff] [blame] | 3552 | pstates[i].sde_pstate->stage = z_pos + SDE_STAGE_0; |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 3553 | SDE_DEBUG("%s: zpos %d", sde_crtc->name, z_pos); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 3554 | } |
| 3555 | |
Jeykumar Sankaran | 2e65503 | 2017-02-04 14:05:45 -0800 | [diff] [blame] | 3556 | for (i = 0; i < multirect_count; i++) { |
| 3557 | if (sde_plane_validate_multirect_v2(&multirect_plane[i])) { |
| 3558 | SDE_ERROR( |
| 3559 | "multirect validation failed for planes (%d - %d)\n", |
| 3560 | multirect_plane[i].r0->plane->base.id, |
| 3561 | multirect_plane[i].r1->plane->base.id); |
| 3562 | rc = -EINVAL; |
Alan Kwong | 9aa061c | 2016-11-06 21:17:12 -0500 | [diff] [blame] | 3563 | goto end; |
Jeykumar Sankaran | 2e65503 | 2017-02-04 14:05:45 -0800 | [diff] [blame] | 3564 | } |
| 3565 | } |
| 3566 | |
Alan Kwong | 9aa061c | 2016-11-06 21:17:12 -0500 | [diff] [blame] | 3567 | rc = sde_core_perf_crtc_check(crtc, state); |
| 3568 | if (rc) { |
| 3569 | SDE_ERROR("crtc%d failed performance check %d\n", |
| 3570 | crtc->base.id, rc); |
| 3571 | goto end; |
| 3572 | } |
| 3573 | |
Jeykumar Sankaran | aaaa071 | 2017-06-12 17:59:16 -0700 | [diff] [blame] | 3574 | /* validate source split: |
Lloyd Atkinson | 629ce1f | 2016-10-27 16:50:26 -0400 | [diff] [blame] | 3575 | * use pstates sorted by stage to check planes on same stage |
| 3576 | * we assume that all pipes are in source split so its valid to compare |
| 3577 | * without taking into account left/right mixer placement |
| 3578 | */ |
| 3579 | for (i = 1; i < cnt; i++) { |
| 3580 | struct plane_state *prv_pstate, *cur_pstate; |
Jeykumar Sankaran | aaaa071 | 2017-06-12 17:59:16 -0700 | [diff] [blame] | 3581 | struct sde_rect left_rect, right_rect; |
| 3582 | int32_t left_pid, right_pid; |
| 3583 | int32_t stage; |
Lloyd Atkinson | 629ce1f | 2016-10-27 16:50:26 -0400 | [diff] [blame] | 3584 | |
| 3585 | prv_pstate = &pstates[i - 1]; |
| 3586 | cur_pstate = &pstates[i]; |
| 3587 | if (prv_pstate->stage != cur_pstate->stage) |
| 3588 | continue; |
| 3589 | |
Jeykumar Sankaran | aaaa071 | 2017-06-12 17:59:16 -0700 | [diff] [blame] | 3590 | stage = cur_pstate->stage; |
Lloyd Atkinson | 629ce1f | 2016-10-27 16:50:26 -0400 | [diff] [blame] | 3591 | |
Jeykumar Sankaran | aaaa071 | 2017-06-12 17:59:16 -0700 | [diff] [blame] | 3592 | left_pid = prv_pstate->sde_pstate->base.plane->base.id; |
| 3593 | POPULATE_RECT(&left_rect, prv_pstate->drm_pstate->crtc_x, |
| 3594 | prv_pstate->drm_pstate->crtc_y, |
| 3595 | prv_pstate->drm_pstate->crtc_w, |
| 3596 | prv_pstate->drm_pstate->crtc_h, false); |
| 3597 | |
| 3598 | right_pid = cur_pstate->sde_pstate->base.plane->base.id; |
| 3599 | POPULATE_RECT(&right_rect, cur_pstate->drm_pstate->crtc_x, |
| 3600 | cur_pstate->drm_pstate->crtc_y, |
| 3601 | cur_pstate->drm_pstate->crtc_w, |
| 3602 | cur_pstate->drm_pstate->crtc_h, false); |
| 3603 | |
| 3604 | if (right_rect.x < left_rect.x) { |
| 3605 | swap(left_pid, right_pid); |
| 3606 | swap(left_rect, right_rect); |
| 3607 | } |
| 3608 | |
| 3609 | /** |
| 3610 | * - planes are enumerated in pipe-priority order such that |
| 3611 | * planes with lower drm_id must be left-most in a shared |
| 3612 | * blend-stage when using source split. |
| 3613 | * - planes in source split must be contiguous in width |
| 3614 | * - planes in source split must have same dest yoff and height |
Lloyd Atkinson | 629ce1f | 2016-10-27 16:50:26 -0400 | [diff] [blame] | 3615 | */ |
Jeykumar Sankaran | aaaa071 | 2017-06-12 17:59:16 -0700 | [diff] [blame] | 3616 | if (right_pid < left_pid) { |
Lloyd Atkinson | 629ce1f | 2016-10-27 16:50:26 -0400 | [diff] [blame] | 3617 | SDE_ERROR( |
Jeykumar Sankaran | aaaa071 | 2017-06-12 17:59:16 -0700 | [diff] [blame] | 3618 | "invalid src split cfg. priority mismatch. stage: %d left: %d right: %d\n", |
| 3619 | stage, left_pid, right_pid); |
Lloyd Atkinson | 629ce1f | 2016-10-27 16:50:26 -0400 | [diff] [blame] | 3620 | rc = -EINVAL; |
| 3621 | goto end; |
Jeykumar Sankaran | aaaa071 | 2017-06-12 17:59:16 -0700 | [diff] [blame] | 3622 | } else if (right_rect.x != (left_rect.x + left_rect.w)) { |
Lloyd Atkinson | 629ce1f | 2016-10-27 16:50:26 -0400 | [diff] [blame] | 3623 | SDE_ERROR( |
Jeykumar Sankaran | aaaa071 | 2017-06-12 17:59:16 -0700 | [diff] [blame] | 3624 | "non-contiguous coordinates for src split. stage: %d left: %d - %d right: %d - %d\n", |
| 3625 | stage, left_rect.x, left_rect.w, |
| 3626 | right_rect.x, right_rect.w); |
| 3627 | rc = -EINVAL; |
| 3628 | goto end; |
| 3629 | } else if ((left_rect.y != right_rect.y) || |
| 3630 | (left_rect.h != right_rect.h)) { |
| 3631 | SDE_ERROR( |
| 3632 | "source split at stage: %d. invalid yoff/height: l_y: %d r_y: %d l_h: %d r_h: %d\n", |
| 3633 | stage, left_rect.y, right_rect.y, |
| 3634 | left_rect.h, right_rect.h); |
Lloyd Atkinson | 629ce1f | 2016-10-27 16:50:26 -0400 | [diff] [blame] | 3635 | rc = -EINVAL; |
| 3636 | goto end; |
| 3637 | } |
| 3638 | } |
| 3639 | |
Lloyd Atkinson | 8ba4703 | 2017-03-22 17:13:32 -0400 | [diff] [blame] | 3640 | rc = _sde_crtc_check_rois(crtc, state); |
| 3641 | if (rc) { |
| 3642 | SDE_ERROR("crtc%d failed roi check %d\n", crtc->base.id, rc); |
| 3643 | goto end; |
| 3644 | } |
Lloyd Atkinson | 629ce1f | 2016-10-27 16:50:26 -0400 | [diff] [blame] | 3645 | |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 3646 | end: |
Alan Kwong | cdb2f28 | 2017-03-18 13:42:06 -0700 | [diff] [blame] | 3647 | _sde_crtc_rp_free_unused(&cstate->rp); |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 3648 | return rc; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 3649 | } |
| 3650 | |
Abhijit Kulkarni | 7acb326 | 2016-07-05 15:27:25 -0400 | [diff] [blame] | 3651 | int sde_crtc_vblank(struct drm_crtc *crtc, bool en) |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 3652 | { |
Clarence Ip | 7f70ce4 | 2017-03-20 06:53:46 -0700 | [diff] [blame] | 3653 | struct sde_crtc *sde_crtc; |
Lloyd Atkinson | dcb1c4a | 2017-07-27 10:52:09 -0400 | [diff] [blame] | 3654 | int ret; |
Abhijit Kulkarni | 7acb326 | 2016-07-05 15:27:25 -0400 | [diff] [blame] | 3655 | |
Clarence Ip | 7f70ce4 | 2017-03-20 06:53:46 -0700 | [diff] [blame] | 3656 | if (!crtc) { |
| 3657 | SDE_ERROR("invalid crtc\n"); |
| 3658 | return -EINVAL; |
| 3659 | } |
| 3660 | sde_crtc = to_sde_crtc(crtc); |
| 3661 | |
| 3662 | mutex_lock(&sde_crtc->crtc_lock); |
Lloyd Atkinson | dcb1c4a | 2017-07-27 10:52:09 -0400 | [diff] [blame] | 3663 | SDE_EVT32(DRMID(&sde_crtc->base), en, sde_crtc->enabled, |
| 3664 | sde_crtc->suspend, sde_crtc->vblank_requested); |
| 3665 | if (sde_crtc->enabled && !sde_crtc->suspend) { |
| 3666 | ret = _sde_crtc_vblank_enable_no_lock(sde_crtc, en); |
| 3667 | if (ret) |
| 3668 | SDE_ERROR("%s vblank enable failed: %d\n", |
| 3669 | sde_crtc->name, ret); |
| 3670 | } |
| 3671 | sde_crtc->vblank_requested = en; |
Clarence Ip | 7f70ce4 | 2017-03-20 06:53:46 -0700 | [diff] [blame] | 3672 | mutex_unlock(&sde_crtc->crtc_lock); |
Clarence Ip | 9728a1d | 2017-04-18 22:22:13 -0400 | [diff] [blame] | 3673 | |
Lloyd Atkinson | dcb1c4a | 2017-07-27 10:52:09 -0400 | [diff] [blame] | 3674 | return 0; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 3675 | } |
| 3676 | |
Lloyd Atkinson | 5217336c | 2016-09-15 18:21:18 -0400 | [diff] [blame] | 3677 | void sde_crtc_cancel_pending_flip(struct drm_crtc *crtc, struct drm_file *file) |
| 3678 | { |
| 3679 | struct sde_crtc *sde_crtc = to_sde_crtc(crtc); |
| 3680 | |
Alan Kwong | 163d261 | 2016-11-03 00:56:56 -0400 | [diff] [blame] | 3681 | SDE_DEBUG("%s: cancel: %p\n", sde_crtc->name, file); |
Lloyd Atkinson | 4f1c869 | 2016-09-14 14:04:25 -0400 | [diff] [blame] | 3682 | _sde_crtc_complete_flip(crtc, file); |
Lloyd Atkinson | 5217336c | 2016-09-15 18:21:18 -0400 | [diff] [blame] | 3683 | } |
| 3684 | |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 3685 | /** |
| 3686 | * sde_crtc_install_properties - install all drm properties for crtc |
| 3687 | * @crtc: Pointer to drm crtc structure |
| 3688 | */ |
Dhaval Patel | e4a5dda | 2016-10-13 19:29:30 -0700 | [diff] [blame] | 3689 | static void sde_crtc_install_properties(struct drm_crtc *crtc, |
| 3690 | struct sde_mdss_cfg *catalog) |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 3691 | { |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 3692 | struct sde_crtc *sde_crtc; |
| 3693 | struct drm_device *dev; |
Dhaval Patel | e4a5dda | 2016-10-13 19:29:30 -0700 | [diff] [blame] | 3694 | struct sde_kms_info *info; |
Alan Kwong | 9aa061c | 2016-11-06 21:17:12 -0500 | [diff] [blame] | 3695 | struct sde_kms *sde_kms; |
Abhijit Kulkarni | 50d6944 | 2017-04-11 19:50:47 -0700 | [diff] [blame] | 3696 | static const struct drm_prop_enum_list e_secure_level[] = { |
| 3697 | {SDE_DRM_SEC_NON_SEC, "sec_and_non_sec"}, |
| 3698 | {SDE_DRM_SEC_ONLY, "sec_only"}, |
| 3699 | }; |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 3700 | |
Lloyd Atkinson | 4f1c869 | 2016-09-14 14:04:25 -0400 | [diff] [blame] | 3701 | SDE_DEBUG("\n"); |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 3702 | |
Dhaval Patel | e4a5dda | 2016-10-13 19:29:30 -0700 | [diff] [blame] | 3703 | if (!crtc || !catalog) { |
| 3704 | SDE_ERROR("invalid crtc or catalog\n"); |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 3705 | return; |
| 3706 | } |
| 3707 | |
| 3708 | sde_crtc = to_sde_crtc(crtc); |
| 3709 | dev = crtc->dev; |
Alan Kwong | 9aa061c | 2016-11-06 21:17:12 -0500 | [diff] [blame] | 3710 | sde_kms = _sde_crtc_get_kms(crtc); |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 3711 | |
Narendra Muppalla | ec11a0a | 2017-06-15 15:35:17 -0700 | [diff] [blame] | 3712 | if (!sde_kms) { |
| 3713 | SDE_ERROR("invalid argument\n"); |
| 3714 | return; |
| 3715 | } |
| 3716 | |
Dhaval Patel | e4a5dda | 2016-10-13 19:29:30 -0700 | [diff] [blame] | 3717 | info = kzalloc(sizeof(struct sde_kms_info), GFP_KERNEL); |
| 3718 | if (!info) { |
| 3719 | SDE_ERROR("failed to allocate info memory\n"); |
| 3720 | return; |
| 3721 | } |
| 3722 | |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 3723 | /* range properties */ |
| 3724 | msm_property_install_range(&sde_crtc->property_info, |
Dhaval Patel | 4e57484 | 2016-08-23 15:11:37 -0700 | [diff] [blame] | 3725 | "input_fence_timeout", 0x0, 0, SDE_CRTC_MAX_INPUT_FENCE_TIMEOUT, |
| 3726 | SDE_CRTC_INPUT_FENCE_TIMEOUT, CRTC_PROP_INPUT_FENCE_TIMEOUT); |
| 3727 | |
| 3728 | msm_property_install_range(&sde_crtc->property_info, "output_fence", |
| 3729 | 0x0, 0, INR_OPEN_MAX, 0x0, CRTC_PROP_OUTPUT_FENCE); |
Clarence Ip | 1d9728b | 2016-09-01 11:10:54 -0400 | [diff] [blame] | 3730 | |
| 3731 | msm_property_install_range(&sde_crtc->property_info, |
| 3732 | "output_fence_offset", 0x0, 0, 1, 0, |
| 3733 | CRTC_PROP_OUTPUT_FENCE_OFFSET); |
Dhaval Patel | e4a5dda | 2016-10-13 19:29:30 -0700 | [diff] [blame] | 3734 | |
Alan Kwong | 9aa061c | 2016-11-06 21:17:12 -0500 | [diff] [blame] | 3735 | msm_property_install_range(&sde_crtc->property_info, |
| 3736 | "core_clk", 0x0, 0, U64_MAX, |
| 3737 | sde_kms->perf.max_core_clk_rate, |
| 3738 | CRTC_PROP_CORE_CLK); |
| 3739 | msm_property_install_range(&sde_crtc->property_info, |
| 3740 | "core_ab", 0x0, 0, U64_MAX, |
Alan Kwong | ff30f4a | 2017-05-23 12:02:00 -0700 | [diff] [blame] | 3741 | catalog->perf.max_bw_high * 1000ULL, |
Alan Kwong | 9aa061c | 2016-11-06 21:17:12 -0500 | [diff] [blame] | 3742 | CRTC_PROP_CORE_AB); |
| 3743 | msm_property_install_range(&sde_crtc->property_info, |
| 3744 | "core_ib", 0x0, 0, U64_MAX, |
Alan Kwong | ff30f4a | 2017-05-23 12:02:00 -0700 | [diff] [blame] | 3745 | catalog->perf.max_bw_high * 1000ULL, |
Alan Kwong | 9aa061c | 2016-11-06 21:17:12 -0500 | [diff] [blame] | 3746 | CRTC_PROP_CORE_IB); |
Alan Kwong | 4aacd53 | 2017-02-04 18:51:33 -0800 | [diff] [blame] | 3747 | msm_property_install_range(&sde_crtc->property_info, |
Alan Kwong | 0230a10 | 2017-05-16 11:36:44 -0700 | [diff] [blame] | 3748 | "llcc_ab", 0x0, 0, U64_MAX, |
Alan Kwong | ff30f4a | 2017-05-23 12:02:00 -0700 | [diff] [blame] | 3749 | catalog->perf.max_bw_high * 1000ULL, |
Alan Kwong | 0230a10 | 2017-05-16 11:36:44 -0700 | [diff] [blame] | 3750 | CRTC_PROP_LLCC_AB); |
Alan Kwong | 8c176bf | 2017-02-09 19:34:32 -0800 | [diff] [blame] | 3751 | msm_property_install_range(&sde_crtc->property_info, |
Alan Kwong | 0230a10 | 2017-05-16 11:36:44 -0700 | [diff] [blame] | 3752 | "llcc_ib", 0x0, 0, U64_MAX, |
Alan Kwong | ff30f4a | 2017-05-23 12:02:00 -0700 | [diff] [blame] | 3753 | catalog->perf.max_bw_high * 1000ULL, |
Alan Kwong | 0230a10 | 2017-05-16 11:36:44 -0700 | [diff] [blame] | 3754 | CRTC_PROP_LLCC_IB); |
| 3755 | msm_property_install_range(&sde_crtc->property_info, |
| 3756 | "dram_ab", 0x0, 0, U64_MAX, |
| 3757 | catalog->perf.max_bw_high * 1000ULL, |
| 3758 | CRTC_PROP_DRAM_AB); |
| 3759 | msm_property_install_range(&sde_crtc->property_info, |
| 3760 | "dram_ib", 0x0, 0, U64_MAX, |
| 3761 | catalog->perf.max_bw_high * 1000ULL, |
| 3762 | CRTC_PROP_DRAM_IB); |
Alan Kwong | 8c176bf | 2017-02-09 19:34:32 -0800 | [diff] [blame] | 3763 | msm_property_install_range(&sde_crtc->property_info, |
Alan Kwong | 4aacd53 | 2017-02-04 18:51:33 -0800 | [diff] [blame] | 3764 | "rot_prefill_bw", 0, 0, U64_MAX, |
| 3765 | catalog->perf.max_bw_high * 1000ULL, |
| 3766 | CRTC_PROP_ROT_PREFILL_BW); |
Alan Kwong | 8c176bf | 2017-02-09 19:34:32 -0800 | [diff] [blame] | 3767 | msm_property_install_range(&sde_crtc->property_info, |
| 3768 | "rot_clk", 0, 0, U64_MAX, |
| 3769 | sde_kms->perf.max_core_clk_rate, |
| 3770 | CRTC_PROP_ROT_CLK); |
Alan Kwong | 9aa061c | 2016-11-06 21:17:12 -0500 | [diff] [blame] | 3771 | |
Dhaval Patel | e4a5dda | 2016-10-13 19:29:30 -0700 | [diff] [blame] | 3772 | msm_property_install_blob(&sde_crtc->property_info, "capabilities", |
| 3773 | DRM_MODE_PROP_IMMUTABLE, CRTC_PROP_INFO); |
Veera Sundaram Sankaran | 3171ff8 | 2017-01-04 14:34:47 -0800 | [diff] [blame] | 3774 | |
Lloyd Atkinson | 8ba4703 | 2017-03-22 17:13:32 -0400 | [diff] [blame] | 3775 | msm_property_install_volatile_range(&sde_crtc->property_info, |
| 3776 | "sde_drm_roi_v1", 0x0, 0, ~0, 0, CRTC_PROP_ROI_V1); |
| 3777 | |
Abhijit Kulkarni | 50d6944 | 2017-04-11 19:50:47 -0700 | [diff] [blame] | 3778 | msm_property_install_enum(&sde_crtc->property_info, "security_level", |
| 3779 | 0x0, 0, e_secure_level, |
| 3780 | ARRAY_SIZE(e_secure_level), |
| 3781 | CRTC_PROP_SECURITY_LEVEL); |
| 3782 | |
Dhaval Patel | e4a5dda | 2016-10-13 19:29:30 -0700 | [diff] [blame] | 3783 | sde_kms_info_reset(info); |
| 3784 | |
Veera Sundaram Sankaran | 2cb064f | 2017-05-05 14:12:17 -0700 | [diff] [blame] | 3785 | if (catalog->has_dim_layer) { |
| 3786 | msm_property_install_volatile_range(&sde_crtc->property_info, |
| 3787 | "dim_layer_v1", 0x0, 0, ~0, 0, CRTC_PROP_DIM_LAYER_V1); |
| 3788 | sde_kms_info_add_keyint(info, "dim_layer_v1_max_layers", |
| 3789 | SDE_MAX_DIM_LAYERS); |
| 3790 | } |
| 3791 | |
Dhaval Patel | e4a5dda | 2016-10-13 19:29:30 -0700 | [diff] [blame] | 3792 | sde_kms_info_add_keyint(info, "hw_version", catalog->hwversion); |
| 3793 | sde_kms_info_add_keyint(info, "max_linewidth", |
| 3794 | catalog->max_mixer_width); |
| 3795 | sde_kms_info_add_keyint(info, "max_blendstages", |
| 3796 | catalog->max_mixer_blendstages); |
| 3797 | if (catalog->qseed_type == SDE_SSPP_SCALER_QSEED2) |
| 3798 | sde_kms_info_add_keystr(info, "qseed_type", "qseed2"); |
| 3799 | if (catalog->qseed_type == SDE_SSPP_SCALER_QSEED3) |
| 3800 | sde_kms_info_add_keystr(info, "qseed_type", "qseed3"); |
Jeykumar Sankaran | 2e65503 | 2017-02-04 14:05:45 -0800 | [diff] [blame] | 3801 | |
| 3802 | if (sde_is_custom_client()) { |
| 3803 | if (catalog->smart_dma_rev == SDE_SSPP_SMART_DMA_V1) |
| 3804 | sde_kms_info_add_keystr(info, |
| 3805 | "smart_dma_rev", "smart_dma_v1"); |
| 3806 | if (catalog->smart_dma_rev == SDE_SSPP_SMART_DMA_V2) |
| 3807 | sde_kms_info_add_keystr(info, |
| 3808 | "smart_dma_rev", "smart_dma_v2"); |
| 3809 | } |
| 3810 | |
Dhaval Patel | e4a5dda | 2016-10-13 19:29:30 -0700 | [diff] [blame] | 3811 | sde_kms_info_add_keyint(info, "has_src_split", catalog->has_src_split); |
Alan Kwong | 2f84f8a | 2016-12-29 13:07:47 -0500 | [diff] [blame] | 3812 | if (catalog->perf.max_bw_low) |
| 3813 | sde_kms_info_add_keyint(info, "max_bandwidth_low", |
Alan Kwong | 6259a38 | 2017-04-04 06:18:02 -0700 | [diff] [blame] | 3814 | catalog->perf.max_bw_low * 1000LL); |
Alan Kwong | 2f84f8a | 2016-12-29 13:07:47 -0500 | [diff] [blame] | 3815 | if (catalog->perf.max_bw_high) |
| 3816 | sde_kms_info_add_keyint(info, "max_bandwidth_high", |
Alan Kwong | 6259a38 | 2017-04-04 06:18:02 -0700 | [diff] [blame] | 3817 | catalog->perf.max_bw_high * 1000LL); |
Alan Kwong | 2f84f8a | 2016-12-29 13:07:47 -0500 | [diff] [blame] | 3818 | if (sde_kms->perf.max_core_clk_rate) |
| 3819 | sde_kms_info_add_keyint(info, "max_mdp_clk", |
| 3820 | sde_kms->perf.max_core_clk_rate); |
Alan Kwong | 6259a38 | 2017-04-04 06:18:02 -0700 | [diff] [blame] | 3821 | sde_kms_info_add_keystr(info, "core_ib_ff", |
| 3822 | catalog->perf.core_ib_ff); |
| 3823 | sde_kms_info_add_keystr(info, "core_clk_ff", |
| 3824 | catalog->perf.core_clk_ff); |
| 3825 | sde_kms_info_add_keystr(info, "comp_ratio_rt", |
| 3826 | catalog->perf.comp_ratio_rt); |
| 3827 | sde_kms_info_add_keystr(info, "comp_ratio_nrt", |
| 3828 | catalog->perf.comp_ratio_nrt); |
| 3829 | sde_kms_info_add_keyint(info, "dest_scale_prefill_lines", |
| 3830 | catalog->perf.dest_scale_prefill_lines); |
| 3831 | sde_kms_info_add_keyint(info, "undersized_prefill_lines", |
| 3832 | catalog->perf.undersized_prefill_lines); |
| 3833 | sde_kms_info_add_keyint(info, "macrotile_prefill_lines", |
| 3834 | catalog->perf.macrotile_prefill_lines); |
| 3835 | sde_kms_info_add_keyint(info, "yuv_nv12_prefill_lines", |
| 3836 | catalog->perf.yuv_nv12_prefill_lines); |
| 3837 | sde_kms_info_add_keyint(info, "linear_prefill_lines", |
| 3838 | catalog->perf.linear_prefill_lines); |
| 3839 | sde_kms_info_add_keyint(info, "downscaling_prefill_lines", |
| 3840 | catalog->perf.downscaling_prefill_lines); |
| 3841 | sde_kms_info_add_keyint(info, "xtra_prefill_lines", |
| 3842 | catalog->perf.xtra_prefill_lines); |
| 3843 | sde_kms_info_add_keyint(info, "amortizable_threshold", |
| 3844 | catalog->perf.amortizable_threshold); |
| 3845 | sde_kms_info_add_keyint(info, "min_prefill_lines", |
| 3846 | catalog->perf.min_prefill_lines); |
| 3847 | |
Dhaval Patel | e4a5dda | 2016-10-13 19:29:30 -0700 | [diff] [blame] | 3848 | msm_property_set_blob(&sde_crtc->property_info, &sde_crtc->blob_info, |
Narendra Muppalla | 22d1725 | 2017-05-31 15:13:39 -0700 | [diff] [blame] | 3849 | info->data, SDE_KMS_INFO_DATALEN(info), CRTC_PROP_INFO); |
Dhaval Patel | e4a5dda | 2016-10-13 19:29:30 -0700 | [diff] [blame] | 3850 | |
| 3851 | kfree(info); |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 3852 | } |
| 3853 | |
| 3854 | /** |
| 3855 | * sde_crtc_atomic_set_property - atomically set a crtc drm property |
| 3856 | * @crtc: Pointer to drm crtc structure |
| 3857 | * @state: Pointer to drm crtc state structure |
| 3858 | * @property: Pointer to targeted drm property |
| 3859 | * @val: Updated property value |
| 3860 | * @Returns: Zero on success |
| 3861 | */ |
| 3862 | static int sde_crtc_atomic_set_property(struct drm_crtc *crtc, |
| 3863 | struct drm_crtc_state *state, |
| 3864 | struct drm_property *property, |
| 3865 | uint64_t val) |
| 3866 | { |
| 3867 | struct sde_crtc *sde_crtc; |
| 3868 | struct sde_crtc_state *cstate; |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 3869 | int idx, ret = -EINVAL; |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 3870 | |
| 3871 | if (!crtc || !state || !property) { |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 3872 | SDE_ERROR("invalid argument(s)\n"); |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 3873 | } else { |
| 3874 | sde_crtc = to_sde_crtc(crtc); |
| 3875 | cstate = to_sde_crtc_state(state); |
| 3876 | ret = msm_property_atomic_set(&sde_crtc->property_info, |
Clarence Ip | 4a2955d | 2017-07-04 18:04:33 -0400 | [diff] [blame] | 3877 | &cstate->property_state, property, val); |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 3878 | if (!ret) { |
| 3879 | idx = msm_property_index(&sde_crtc->property_info, |
| 3880 | property); |
Veera Sundaram Sankaran | 3171ff8 | 2017-01-04 14:34:47 -0800 | [diff] [blame] | 3881 | switch (idx) { |
| 3882 | case CRTC_PROP_INPUT_FENCE_TIMEOUT: |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 3883 | _sde_crtc_set_input_fence_timeout(cstate); |
Veera Sundaram Sankaran | 3171ff8 | 2017-01-04 14:34:47 -0800 | [diff] [blame] | 3884 | break; |
| 3885 | case CRTC_PROP_DIM_LAYER_V1: |
| 3886 | _sde_crtc_set_dim_layer_v1(cstate, (void *)val); |
| 3887 | break; |
Lloyd Atkinson | 8ba4703 | 2017-03-22 17:13:32 -0400 | [diff] [blame] | 3888 | case CRTC_PROP_ROI_V1: |
| 3889 | ret = _sde_crtc_set_roi_v1(state, (void *)val); |
| 3890 | break; |
Alan Kwong | 8411a911 | 2017-06-06 19:29:01 -0400 | [diff] [blame] | 3891 | case CRTC_PROP_CORE_CLK: |
Alan Kwong | ff30f4a | 2017-05-23 12:02:00 -0700 | [diff] [blame] | 3892 | case CRTC_PROP_CORE_AB: |
| 3893 | case CRTC_PROP_CORE_IB: |
Alan Kwong | ff30f4a | 2017-05-23 12:02:00 -0700 | [diff] [blame] | 3894 | cstate->bw_control = true; |
| 3895 | break; |
Alan Kwong | 0230a10 | 2017-05-16 11:36:44 -0700 | [diff] [blame] | 3896 | case CRTC_PROP_LLCC_AB: |
| 3897 | case CRTC_PROP_LLCC_IB: |
| 3898 | case CRTC_PROP_DRAM_AB: |
| 3899 | case CRTC_PROP_DRAM_IB: |
| 3900 | cstate->bw_control = true; |
| 3901 | cstate->bw_split_vote = true; |
| 3902 | break; |
Veera Sundaram Sankaran | 3171ff8 | 2017-01-04 14:34:47 -0800 | [diff] [blame] | 3903 | default: |
| 3904 | /* nothing to do */ |
| 3905 | break; |
| 3906 | } |
Gopikrishnaiah Anandan | e0e5e0c | 2016-05-25 11:05:33 -0700 | [diff] [blame] | 3907 | } else { |
| 3908 | ret = sde_cp_crtc_set_property(crtc, |
| 3909 | property, val); |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 3910 | } |
Gopikrishnaiah Anandan | e0e5e0c | 2016-05-25 11:05:33 -0700 | [diff] [blame] | 3911 | if (ret) |
| 3912 | DRM_ERROR("failed to set the property\n"); |
Alan Kwong | cdb2f28 | 2017-03-18 13:42:06 -0700 | [diff] [blame] | 3913 | |
| 3914 | SDE_DEBUG("crtc%d %s[%d] <= 0x%llx ret=%d\n", crtc->base.id, |
| 3915 | property->name, property->base.id, val, ret); |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 3916 | } |
| 3917 | |
| 3918 | return ret; |
| 3919 | } |
| 3920 | |
| 3921 | /** |
| 3922 | * sde_crtc_set_property - set a crtc drm property |
| 3923 | * @crtc: Pointer to drm crtc structure |
| 3924 | * @property: Pointer to targeted drm property |
| 3925 | * @val: Updated property value |
| 3926 | * @Returns: Zero on success |
| 3927 | */ |
| 3928 | static int sde_crtc_set_property(struct drm_crtc *crtc, |
| 3929 | struct drm_property *property, uint64_t val) |
| 3930 | { |
Lloyd Atkinson | 4f1c869 | 2016-09-14 14:04:25 -0400 | [diff] [blame] | 3931 | SDE_DEBUG("\n"); |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 3932 | |
| 3933 | return sde_crtc_atomic_set_property(crtc, crtc->state, property, val); |
| 3934 | } |
| 3935 | |
| 3936 | /** |
| 3937 | * sde_crtc_atomic_get_property - retrieve a crtc drm property |
| 3938 | * @crtc: Pointer to drm crtc structure |
| 3939 | * @state: Pointer to drm crtc state structure |
| 3940 | * @property: Pointer to targeted drm property |
| 3941 | * @val: Pointer to variable for receiving property value |
| 3942 | * @Returns: Zero on success |
| 3943 | */ |
| 3944 | static int sde_crtc_atomic_get_property(struct drm_crtc *crtc, |
| 3945 | const struct drm_crtc_state *state, |
| 3946 | struct drm_property *property, |
| 3947 | uint64_t *val) |
| 3948 | { |
| 3949 | struct sde_crtc *sde_crtc; |
| 3950 | struct sde_crtc_state *cstate; |
Veera Sundaram Sankaran | 675ff62 | 2017-06-21 21:44:46 -0700 | [diff] [blame] | 3951 | struct drm_encoder *encoder; |
Clarence Ip | 24f8066 | 2016-06-13 19:05:32 -0400 | [diff] [blame] | 3952 | int i, ret = -EINVAL; |
Dhaval Patel | 5cb59be | 2017-04-20 20:00:56 -0700 | [diff] [blame] | 3953 | bool conn_offset = 0; |
Veera Sundaram Sankaran | 675ff62 | 2017-06-21 21:44:46 -0700 | [diff] [blame] | 3954 | bool is_cmd = true; |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 3955 | |
| 3956 | if (!crtc || !state) { |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 3957 | SDE_ERROR("invalid argument(s)\n"); |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 3958 | } else { |
| 3959 | sde_crtc = to_sde_crtc(crtc); |
| 3960 | cstate = to_sde_crtc_state(state); |
Dhaval Patel | 5cb59be | 2017-04-20 20:00:56 -0700 | [diff] [blame] | 3961 | |
| 3962 | for (i = 0; i < cstate->num_connectors; ++i) { |
| 3963 | conn_offset = sde_connector_needs_offset( |
| 3964 | cstate->connectors[i]); |
| 3965 | if (conn_offset) |
| 3966 | break; |
| 3967 | } |
| 3968 | |
Veera Sundaram Sankaran | 675ff62 | 2017-06-21 21:44:46 -0700 | [diff] [blame] | 3969 | /** |
| 3970 | * set the cmd flag only when all the encoders attached |
| 3971 | * to the crtc are in cmd mode. Consider all other cases |
| 3972 | * as video mode. |
| 3973 | */ |
| 3974 | drm_for_each_encoder(encoder, crtc->dev) { |
| 3975 | if (encoder->crtc == crtc) |
| 3976 | is_cmd &= sde_encoder_is_cmd_mode(encoder); |
| 3977 | } |
| 3978 | |
Clarence Ip | 24f8066 | 2016-06-13 19:05:32 -0400 | [diff] [blame] | 3979 | i = msm_property_index(&sde_crtc->property_info, property); |
| 3980 | if (i == CRTC_PROP_OUTPUT_FENCE) { |
Dhaval Patel | 39323d4 | 2017-03-01 23:48:24 -0800 | [diff] [blame] | 3981 | uint32_t offset = sde_crtc_get_property(cstate, |
Clarence Ip | 1d9728b | 2016-09-01 11:10:54 -0400 | [diff] [blame] | 3982 | CRTC_PROP_OUTPUT_FENCE_OFFSET); |
| 3983 | |
Veera Sundaram Sankaran | 675ff62 | 2017-06-21 21:44:46 -0700 | [diff] [blame] | 3984 | /** |
| 3985 | * set the offset to 0 only for cmd mode panels, so |
| 3986 | * the release fence for the current frame can be |
| 3987 | * triggered right after PP_DONE interrupt. |
| 3988 | */ |
| 3989 | offset = is_cmd ? 0 : (offset + conn_offset); |
| 3990 | |
Dhaval Patel | 5cb59be | 2017-04-20 20:00:56 -0700 | [diff] [blame] | 3991 | ret = sde_fence_create(&sde_crtc->output_fence, val, |
Veera Sundaram Sankaran | 675ff62 | 2017-06-21 21:44:46 -0700 | [diff] [blame] | 3992 | offset); |
Clarence Ip | 1d9728b | 2016-09-01 11:10:54 -0400 | [diff] [blame] | 3993 | if (ret) |
| 3994 | SDE_ERROR("fence create failed\n"); |
Clarence Ip | 24f8066 | 2016-06-13 19:05:32 -0400 | [diff] [blame] | 3995 | } else { |
| 3996 | ret = msm_property_atomic_get(&sde_crtc->property_info, |
Clarence Ip | 4a2955d | 2017-07-04 18:04:33 -0400 | [diff] [blame] | 3997 | &cstate->property_state, |
| 3998 | property, val); |
Gopikrishnaiah Anandan | e0e5e0c | 2016-05-25 11:05:33 -0700 | [diff] [blame] | 3999 | if (ret) |
| 4000 | ret = sde_cp_crtc_get_property(crtc, |
| 4001 | property, val); |
Clarence Ip | 24f8066 | 2016-06-13 19:05:32 -0400 | [diff] [blame] | 4002 | } |
Gopikrishnaiah Anandan | e0e5e0c | 2016-05-25 11:05:33 -0700 | [diff] [blame] | 4003 | if (ret) |
| 4004 | DRM_ERROR("get property failed\n"); |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 4005 | } |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 4006 | return ret; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 4007 | } |
| 4008 | |
Alan Kwong | 67a3f79 | 2016-11-01 23:16:53 -0400 | [diff] [blame] | 4009 | #ifdef CONFIG_DEBUG_FS |
Dhaval Patel | 3fbe6bf | 2016-10-20 20:00:41 -0700 | [diff] [blame] | 4010 | static int _sde_debugfs_status_show(struct seq_file *s, void *data) |
Clarence Ip | 8f7366c | 2016-07-05 12:15:26 -0400 | [diff] [blame] | 4011 | { |
| 4012 | struct sde_crtc *sde_crtc; |
Dhaval Patel | 3fbe6bf | 2016-10-20 20:00:41 -0700 | [diff] [blame] | 4013 | struct sde_plane_state *pstate = NULL; |
Clarence Ip | 8f7366c | 2016-07-05 12:15:26 -0400 | [diff] [blame] | 4014 | struct sde_crtc_mixer *m; |
Dhaval Patel | 3fbe6bf | 2016-10-20 20:00:41 -0700 | [diff] [blame] | 4015 | |
| 4016 | struct drm_crtc *crtc; |
| 4017 | struct drm_plane *plane; |
| 4018 | struct drm_display_mode *mode; |
| 4019 | struct drm_framebuffer *fb; |
| 4020 | struct drm_plane_state *state; |
Veera Sundaram Sankaran | 2cb064f | 2017-05-05 14:12:17 -0700 | [diff] [blame] | 4021 | struct sde_crtc_state *cstate; |
Dhaval Patel | 3fbe6bf | 2016-10-20 20:00:41 -0700 | [diff] [blame] | 4022 | |
| 4023 | int i, out_width; |
Clarence Ip | 8f7366c | 2016-07-05 12:15:26 -0400 | [diff] [blame] | 4024 | |
| 4025 | if (!s || !s->private) |
| 4026 | return -EINVAL; |
| 4027 | |
| 4028 | sde_crtc = s->private; |
Dhaval Patel | 3fbe6bf | 2016-10-20 20:00:41 -0700 | [diff] [blame] | 4029 | crtc = &sde_crtc->base; |
Veera Sundaram Sankaran | 2cb064f | 2017-05-05 14:12:17 -0700 | [diff] [blame] | 4030 | cstate = to_sde_crtc_state(crtc->state); |
Dhaval Patel | 3fbe6bf | 2016-10-20 20:00:41 -0700 | [diff] [blame] | 4031 | |
| 4032 | mutex_lock(&sde_crtc->crtc_lock); |
| 4033 | mode = &crtc->state->adjusted_mode; |
| 4034 | out_width = sde_crtc_mixer_width(sde_crtc, mode); |
| 4035 | |
| 4036 | seq_printf(s, "crtc:%d width:%d height:%d\n", crtc->base.id, |
| 4037 | mode->hdisplay, mode->vdisplay); |
| 4038 | |
| 4039 | seq_puts(s, "\n"); |
| 4040 | |
Clarence Ip | 8f7366c | 2016-07-05 12:15:26 -0400 | [diff] [blame] | 4041 | for (i = 0; i < sde_crtc->num_mixers; ++i) { |
Lloyd Atkinson | e7bcdd2 | 2016-08-11 10:53:37 -0400 | [diff] [blame] | 4042 | m = &sde_crtc->mixers[i]; |
Dhaval Patel | 3fbe6bf | 2016-10-20 20:00:41 -0700 | [diff] [blame] | 4043 | if (!m->hw_lm) |
| 4044 | seq_printf(s, "\tmixer[%d] has no lm\n", i); |
| 4045 | else if (!m->hw_ctl) |
| 4046 | seq_printf(s, "\tmixer[%d] has no ctl\n", i); |
| 4047 | else |
| 4048 | seq_printf(s, "\tmixer:%d ctl:%d width:%d height:%d\n", |
| 4049 | m->hw_lm->idx - LM_0, m->hw_ctl->idx - CTL_0, |
| 4050 | out_width, mode->vdisplay); |
Clarence Ip | 8f7366c | 2016-07-05 12:15:26 -0400 | [diff] [blame] | 4051 | } |
Dhaval Patel | 44f1247 | 2016-08-29 12:19:47 -0700 | [diff] [blame] | 4052 | |
Dhaval Patel | 3fbe6bf | 2016-10-20 20:00:41 -0700 | [diff] [blame] | 4053 | seq_puts(s, "\n"); |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 4054 | |
Veera Sundaram Sankaran | 2cb064f | 2017-05-05 14:12:17 -0700 | [diff] [blame] | 4055 | for (i = 0; i < cstate->num_dim_layers; i++) { |
| 4056 | struct sde_hw_dim_layer *dim_layer = &cstate->dim_layer[i]; |
| 4057 | |
| 4058 | seq_printf(s, "\tdim_layer:%d] stage:%d flags:%d\n", |
| 4059 | i, dim_layer->stage, dim_layer->flags); |
| 4060 | seq_printf(s, "\tdst_x:%d dst_y:%d dst_w:%d dst_h:%d\n", |
| 4061 | dim_layer->rect.x, dim_layer->rect.y, |
| 4062 | dim_layer->rect.w, dim_layer->rect.h); |
| 4063 | seq_printf(s, |
| 4064 | "\tcolor_0:%d color_1:%d color_2:%d color_3:%d\n", |
| 4065 | dim_layer->color_fill.color_0, |
| 4066 | dim_layer->color_fill.color_1, |
| 4067 | dim_layer->color_fill.color_2, |
| 4068 | dim_layer->color_fill.color_3); |
| 4069 | seq_puts(s, "\n"); |
| 4070 | } |
| 4071 | |
Dhaval Patel | 3fbe6bf | 2016-10-20 20:00:41 -0700 | [diff] [blame] | 4072 | drm_atomic_crtc_for_each_plane(plane, crtc) { |
| 4073 | pstate = to_sde_plane_state(plane->state); |
| 4074 | state = plane->state; |
| 4075 | |
| 4076 | if (!pstate || !state) |
| 4077 | continue; |
| 4078 | |
| 4079 | seq_printf(s, "\tplane:%u stage:%d\n", plane->base.id, |
| 4080 | pstate->stage); |
| 4081 | |
| 4082 | if (plane->state->fb) { |
| 4083 | fb = plane->state->fb; |
| 4084 | |
| 4085 | seq_printf(s, "\tfb:%d image format:%4.4s wxh:%ux%u bpp:%d\n", |
| 4086 | fb->base.id, (char *) &fb->pixel_format, |
| 4087 | fb->width, fb->height, fb->bits_per_pixel); |
| 4088 | |
| 4089 | seq_puts(s, "\t"); |
| 4090 | for (i = 0; i < ARRAY_SIZE(fb->modifier); i++) |
| 4091 | seq_printf(s, "modifier[%d]:%8llu ", i, |
| 4092 | fb->modifier[i]); |
| 4093 | seq_puts(s, "\n"); |
| 4094 | |
| 4095 | seq_puts(s, "\t"); |
| 4096 | for (i = 0; i < ARRAY_SIZE(fb->pitches); i++) |
| 4097 | seq_printf(s, "pitches[%d]:%8u ", i, |
| 4098 | fb->pitches[i]); |
| 4099 | seq_puts(s, "\n"); |
| 4100 | |
| 4101 | seq_puts(s, "\t"); |
| 4102 | for (i = 0; i < ARRAY_SIZE(fb->offsets); i++) |
| 4103 | seq_printf(s, "offsets[%d]:%8u ", i, |
| 4104 | fb->offsets[i]); |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 4105 | seq_puts(s, "\n"); |
| 4106 | } |
Dhaval Patel | 3fbe6bf | 2016-10-20 20:00:41 -0700 | [diff] [blame] | 4107 | |
| 4108 | seq_printf(s, "\tsrc_x:%4d src_y:%4d src_w:%4d src_h:%4d\n", |
| 4109 | state->src_x, state->src_y, state->src_w, state->src_h); |
| 4110 | |
| 4111 | seq_printf(s, "\tdst x:%4d dst_y:%4d dst_w:%4d dst_h:%4d\n", |
| 4112 | state->crtc_x, state->crtc_y, state->crtc_w, |
| 4113 | state->crtc_h); |
Jeykumar Sankaran | e964dc7 | 2017-05-10 19:26:43 -0700 | [diff] [blame] | 4114 | seq_printf(s, "\tmultirect: mode: %d index: %d\n", |
| 4115 | pstate->multirect_mode, pstate->multirect_index); |
Veera Sundaram Sankaran | 58e1281 | 2017-05-05 11:51:09 -0700 | [diff] [blame] | 4116 | |
| 4117 | seq_printf(s, "\texcl_rect: x:%4d y:%4d w:%4d h:%4d\n", |
| 4118 | pstate->excl_rect.x, pstate->excl_rect.y, |
| 4119 | pstate->excl_rect.w, pstate->excl_rect.h); |
| 4120 | |
Dhaval Patel | 3fbe6bf | 2016-10-20 20:00:41 -0700 | [diff] [blame] | 4121 | seq_puts(s, "\n"); |
Clarence Ip | 8f7366c | 2016-07-05 12:15:26 -0400 | [diff] [blame] | 4122 | } |
Alan Kwong | 07da098 | 2016-11-04 12:57:45 -0400 | [diff] [blame] | 4123 | |
| 4124 | if (sde_crtc->vblank_cb_count) { |
| 4125 | ktime_t diff = ktime_sub(ktime_get(), sde_crtc->vblank_cb_time); |
| 4126 | s64 diff_ms = ktime_to_ms(diff); |
| 4127 | s64 fps = diff_ms ? DIV_ROUND_CLOSEST( |
| 4128 | sde_crtc->vblank_cb_count * 1000, diff_ms) : 0; |
| 4129 | |
| 4130 | seq_printf(s, |
Dhaval Patel | d67cf4a | 2017-06-14 18:08:32 -0700 | [diff] [blame] | 4131 | "vblank fps:%lld count:%u total:%llums total_framecount:%llu\n", |
| 4132 | fps, sde_crtc->vblank_cb_count, |
| 4133 | ktime_to_ms(diff), sde_crtc->play_count); |
Alan Kwong | 07da098 | 2016-11-04 12:57:45 -0400 | [diff] [blame] | 4134 | |
| 4135 | /* reset time & count for next measurement */ |
| 4136 | sde_crtc->vblank_cb_count = 0; |
| 4137 | sde_crtc->vblank_cb_time = ktime_set(0, 0); |
| 4138 | } |
| 4139 | |
Lloyd Atkinson | dcb1c4a | 2017-07-27 10:52:09 -0400 | [diff] [blame] | 4140 | seq_printf(s, "vblank_enable:%d\n", sde_crtc->vblank_requested); |
Alan Kwong | 07da098 | 2016-11-04 12:57:45 -0400 | [diff] [blame] | 4141 | |
Dhaval Patel | 3fbe6bf | 2016-10-20 20:00:41 -0700 | [diff] [blame] | 4142 | mutex_unlock(&sde_crtc->crtc_lock); |
| 4143 | |
Clarence Ip | 8f7366c | 2016-07-05 12:15:26 -0400 | [diff] [blame] | 4144 | return 0; |
| 4145 | } |
| 4146 | |
Dhaval Patel | 3fbe6bf | 2016-10-20 20:00:41 -0700 | [diff] [blame] | 4147 | static int _sde_debugfs_status_open(struct inode *inode, struct file *file) |
Clarence Ip | 8f7366c | 2016-07-05 12:15:26 -0400 | [diff] [blame] | 4148 | { |
Dhaval Patel | 3fbe6bf | 2016-10-20 20:00:41 -0700 | [diff] [blame] | 4149 | return single_open(file, _sde_debugfs_status_show, inode->i_private); |
Clarence Ip | 8f7366c | 2016-07-05 12:15:26 -0400 | [diff] [blame] | 4150 | } |
| 4151 | |
Dhaval Patel | f9245d6 | 2017-03-28 16:24:00 -0700 | [diff] [blame] | 4152 | static ssize_t _sde_crtc_misr_setup(struct file *file, |
| 4153 | const char __user *user_buf, size_t count, loff_t *ppos) |
| 4154 | { |
| 4155 | struct sde_crtc *sde_crtc; |
| 4156 | struct sde_crtc_mixer *m; |
| 4157 | int i = 0, rc; |
| 4158 | char buf[MISR_BUFF_SIZE + 1]; |
| 4159 | u32 frame_count, enable; |
| 4160 | size_t buff_copy; |
| 4161 | |
| 4162 | if (!file || !file->private_data) |
| 4163 | return -EINVAL; |
| 4164 | |
| 4165 | sde_crtc = file->private_data; |
| 4166 | buff_copy = min_t(size_t, count, MISR_BUFF_SIZE); |
| 4167 | if (copy_from_user(buf, user_buf, buff_copy)) { |
| 4168 | SDE_ERROR("buffer copy failed\n"); |
| 4169 | return -EINVAL; |
| 4170 | } |
| 4171 | |
| 4172 | buf[buff_copy] = 0; /* end of string */ |
| 4173 | |
| 4174 | if (sscanf(buf, "%u %u", &enable, &frame_count) != 2) |
| 4175 | return -EINVAL; |
| 4176 | |
| 4177 | rc = _sde_crtc_power_enable(sde_crtc, true); |
| 4178 | if (rc) |
| 4179 | return rc; |
| 4180 | |
| 4181 | mutex_lock(&sde_crtc->crtc_lock); |
| 4182 | sde_crtc->misr_enable = enable; |
Dhaval Patel | 010f517 | 2017-08-01 22:40:09 -0700 | [diff] [blame] | 4183 | sde_crtc->misr_frame_count = frame_count; |
Dhaval Patel | f9245d6 | 2017-03-28 16:24:00 -0700 | [diff] [blame] | 4184 | for (i = 0; i < sde_crtc->num_mixers; ++i) { |
Dhaval Patel | 010f517 | 2017-08-01 22:40:09 -0700 | [diff] [blame] | 4185 | sde_crtc->misr_data[i] = 0; |
Dhaval Patel | f9245d6 | 2017-03-28 16:24:00 -0700 | [diff] [blame] | 4186 | m = &sde_crtc->mixers[i]; |
Dhaval Patel | 010f517 | 2017-08-01 22:40:09 -0700 | [diff] [blame] | 4187 | if (!m->hw_lm || !m->hw_lm->ops.setup_misr) |
Dhaval Patel | f9245d6 | 2017-03-28 16:24:00 -0700 | [diff] [blame] | 4188 | continue; |
| 4189 | |
| 4190 | m->hw_lm->ops.setup_misr(m->hw_lm, enable, frame_count); |
| 4191 | } |
| 4192 | mutex_unlock(&sde_crtc->crtc_lock); |
| 4193 | _sde_crtc_power_enable(sde_crtc, false); |
| 4194 | |
| 4195 | return count; |
| 4196 | } |
| 4197 | |
| 4198 | static ssize_t _sde_crtc_misr_read(struct file *file, |
| 4199 | char __user *user_buff, size_t count, loff_t *ppos) |
| 4200 | { |
| 4201 | struct sde_crtc *sde_crtc; |
| 4202 | struct sde_crtc_mixer *m; |
| 4203 | int i = 0, rc; |
Dhaval Patel | 010f517 | 2017-08-01 22:40:09 -0700 | [diff] [blame] | 4204 | u32 misr_status; |
Dhaval Patel | f9245d6 | 2017-03-28 16:24:00 -0700 | [diff] [blame] | 4205 | ssize_t len = 0; |
| 4206 | char buf[MISR_BUFF_SIZE + 1] = {'\0'}; |
| 4207 | |
| 4208 | if (*ppos) |
| 4209 | return 0; |
| 4210 | |
| 4211 | if (!file || !file->private_data) |
| 4212 | return -EINVAL; |
| 4213 | |
| 4214 | sde_crtc = file->private_data; |
| 4215 | rc = _sde_crtc_power_enable(sde_crtc, true); |
| 4216 | if (rc) |
| 4217 | return rc; |
| 4218 | |
| 4219 | mutex_lock(&sde_crtc->crtc_lock); |
| 4220 | if (!sde_crtc->misr_enable) { |
| 4221 | len += snprintf(buf + len, MISR_BUFF_SIZE - len, |
| 4222 | "disabled\n"); |
| 4223 | goto buff_check; |
| 4224 | } |
| 4225 | |
| 4226 | for (i = 0; i < sde_crtc->num_mixers; ++i) { |
| 4227 | m = &sde_crtc->mixers[i]; |
Dhaval Patel | 010f517 | 2017-08-01 22:40:09 -0700 | [diff] [blame] | 4228 | if (!m->hw_lm || !m->hw_lm->ops.collect_misr) |
Dhaval Patel | f9245d6 | 2017-03-28 16:24:00 -0700 | [diff] [blame] | 4229 | continue; |
| 4230 | |
Dhaval Patel | 010f517 | 2017-08-01 22:40:09 -0700 | [diff] [blame] | 4231 | misr_status = m->hw_lm->ops.collect_misr(m->hw_lm); |
| 4232 | sde_crtc->misr_data[i] = misr_status ? misr_status : |
| 4233 | sde_crtc->misr_data[i]; |
Dhaval Patel | f9245d6 | 2017-03-28 16:24:00 -0700 | [diff] [blame] | 4234 | len += snprintf(buf + len, MISR_BUFF_SIZE - len, "lm idx:%d\n", |
| 4235 | m->hw_lm->idx - LM_0); |
| 4236 | len += snprintf(buf + len, MISR_BUFF_SIZE - len, "0x%x\n", |
Dhaval Patel | 010f517 | 2017-08-01 22:40:09 -0700 | [diff] [blame] | 4237 | sde_crtc->misr_data[i]); |
Dhaval Patel | f9245d6 | 2017-03-28 16:24:00 -0700 | [diff] [blame] | 4238 | } |
| 4239 | |
| 4240 | buff_check: |
| 4241 | if (count <= len) { |
| 4242 | len = 0; |
| 4243 | goto end; |
| 4244 | } |
| 4245 | |
| 4246 | if (copy_to_user(user_buff, buf, len)) { |
| 4247 | len = -EFAULT; |
| 4248 | goto end; |
| 4249 | } |
| 4250 | |
| 4251 | *ppos += len; /* increase offset */ |
| 4252 | |
| 4253 | end: |
| 4254 | mutex_unlock(&sde_crtc->crtc_lock); |
| 4255 | _sde_crtc_power_enable(sde_crtc, false); |
| 4256 | return len; |
| 4257 | } |
| 4258 | |
| 4259 | #define DEFINE_SDE_DEBUGFS_SEQ_FOPS(__prefix) \ |
Alan Kwong | 67a3f79 | 2016-11-01 23:16:53 -0400 | [diff] [blame] | 4260 | static int __prefix ## _open(struct inode *inode, struct file *file) \ |
| 4261 | { \ |
| 4262 | return single_open(file, __prefix ## _show, inode->i_private); \ |
| 4263 | } \ |
| 4264 | static const struct file_operations __prefix ## _fops = { \ |
| 4265 | .owner = THIS_MODULE, \ |
| 4266 | .open = __prefix ## _open, \ |
| 4267 | .release = single_release, \ |
| 4268 | .read = seq_read, \ |
| 4269 | .llseek = seq_lseek, \ |
| 4270 | } |
| 4271 | |
| 4272 | static int sde_crtc_debugfs_state_show(struct seq_file *s, void *v) |
| 4273 | { |
| 4274 | struct drm_crtc *crtc = (struct drm_crtc *) s->private; |
Alan Kwong | 751cf46 | 2017-06-08 10:26:46 -0400 | [diff] [blame] | 4275 | struct sde_crtc *sde_crtc = to_sde_crtc(crtc); |
Alan Kwong | 67a3f79 | 2016-11-01 23:16:53 -0400 | [diff] [blame] | 4276 | struct sde_crtc_state *cstate = to_sde_crtc_state(crtc->state); |
Alan Kwong | cdb2f28 | 2017-03-18 13:42:06 -0700 | [diff] [blame] | 4277 | struct sde_crtc_res *res; |
Alan Kwong | 310e9b0 | 2017-08-03 02:04:07 -0400 | [diff] [blame] | 4278 | struct sde_crtc_respool *rp; |
Alan Kwong | 0230a10 | 2017-05-16 11:36:44 -0700 | [diff] [blame] | 4279 | int i; |
Alan Kwong | 67a3f79 | 2016-11-01 23:16:53 -0400 | [diff] [blame] | 4280 | |
| 4281 | seq_printf(s, "num_connectors: %d\n", cstate->num_connectors); |
Dhaval Patel | 4d42460 | 2017-02-18 19:40:14 -0800 | [diff] [blame] | 4282 | seq_printf(s, "client type: %d\n", sde_crtc_get_client_type(crtc)); |
Alan Kwong | 3e985f0 | 2017-02-12 15:08:44 -0800 | [diff] [blame] | 4283 | seq_printf(s, "intf_mode: %d\n", sde_crtc_get_intf_mode(crtc)); |
Alan Kwong | 751cf46 | 2017-06-08 10:26:46 -0400 | [diff] [blame] | 4284 | seq_printf(s, "core_clk_rate: %llu\n", |
| 4285 | sde_crtc->cur_perf.core_clk_rate); |
Alan Kwong | 0230a10 | 2017-05-16 11:36:44 -0700 | [diff] [blame] | 4286 | for (i = SDE_POWER_HANDLE_DBUS_ID_MNOC; |
| 4287 | i < SDE_POWER_HANDLE_DBUS_ID_MAX; i++) { |
| 4288 | seq_printf(s, "bw_ctl[%s]: %llu\n", |
| 4289 | sde_power_handle_get_dbus_name(i), |
| 4290 | sde_crtc->cur_perf.bw_ctl[i]); |
| 4291 | seq_printf(s, "max_per_pipe_ib[%s]: %llu\n", |
| 4292 | sde_power_handle_get_dbus_name(i), |
| 4293 | sde_crtc->cur_perf.max_per_pipe_ib[i]); |
| 4294 | } |
Alan Kwong | 67a3f79 | 2016-11-01 23:16:53 -0400 | [diff] [blame] | 4295 | |
Alan Kwong | 310e9b0 | 2017-08-03 02:04:07 -0400 | [diff] [blame] | 4296 | mutex_lock(&sde_crtc->rp_lock); |
| 4297 | list_for_each_entry(rp, &sde_crtc->rp_head, rp_list) { |
| 4298 | seq_printf(s, "rp.%d: ", rp->sequence_id); |
| 4299 | list_for_each_entry(res, &rp->res_list, list) |
| 4300 | seq_printf(s, "0x%x/0x%llx/%pK/%d ", |
| 4301 | res->type, res->tag, res->val, |
| 4302 | atomic_read(&res->refcount)); |
| 4303 | seq_puts(s, "\n"); |
| 4304 | } |
| 4305 | mutex_unlock(&sde_crtc->rp_lock); |
Alan Kwong | cdb2f28 | 2017-03-18 13:42:06 -0700 | [diff] [blame] | 4306 | |
Alan Kwong | 67a3f79 | 2016-11-01 23:16:53 -0400 | [diff] [blame] | 4307 | return 0; |
| 4308 | } |
| 4309 | DEFINE_SDE_DEBUGFS_SEQ_FOPS(sde_crtc_debugfs_state); |
| 4310 | |
Lloyd Atkinson | b020e0f | 2017-03-14 08:05:18 -0700 | [diff] [blame] | 4311 | static int _sde_crtc_init_debugfs(struct drm_crtc *crtc) |
Clarence Ip | 8f7366c | 2016-07-05 12:15:26 -0400 | [diff] [blame] | 4312 | { |
Lloyd Atkinson | b020e0f | 2017-03-14 08:05:18 -0700 | [diff] [blame] | 4313 | struct sde_crtc *sde_crtc; |
| 4314 | struct sde_kms *sde_kms; |
| 4315 | |
Dhaval Patel | 3fbe6bf | 2016-10-20 20:00:41 -0700 | [diff] [blame] | 4316 | static const struct file_operations debugfs_status_fops = { |
| 4317 | .open = _sde_debugfs_status_open, |
Clarence Ip | 8f7366c | 2016-07-05 12:15:26 -0400 | [diff] [blame] | 4318 | .read = seq_read, |
| 4319 | .llseek = seq_lseek, |
| 4320 | .release = single_release, |
| 4321 | }; |
Dhaval Patel | f9245d6 | 2017-03-28 16:24:00 -0700 | [diff] [blame] | 4322 | static const struct file_operations debugfs_misr_fops = { |
| 4323 | .open = simple_open, |
| 4324 | .read = _sde_crtc_misr_read, |
| 4325 | .write = _sde_crtc_misr_setup, |
| 4326 | }; |
Alan Kwong | 67a3f79 | 2016-11-01 23:16:53 -0400 | [diff] [blame] | 4327 | |
Lloyd Atkinson | b020e0f | 2017-03-14 08:05:18 -0700 | [diff] [blame] | 4328 | if (!crtc) |
| 4329 | return -EINVAL; |
| 4330 | sde_crtc = to_sde_crtc(crtc); |
| 4331 | |
| 4332 | sde_kms = _sde_crtc_get_kms(crtc); |
| 4333 | if (!sde_kms) |
| 4334 | return -EINVAL; |
| 4335 | |
| 4336 | sde_crtc->debugfs_root = debugfs_create_dir(sde_crtc->name, |
Lloyd Atkinson | 09e64bf | 2017-04-13 14:09:59 -0700 | [diff] [blame] | 4337 | crtc->dev->primary->debugfs_root); |
Lloyd Atkinson | b020e0f | 2017-03-14 08:05:18 -0700 | [diff] [blame] | 4338 | if (!sde_crtc->debugfs_root) |
| 4339 | return -ENOMEM; |
| 4340 | |
| 4341 | /* don't error check these */ |
Lloyd Atkinson | 8de415a | 2017-05-23 11:31:16 -0400 | [diff] [blame] | 4342 | debugfs_create_file("status", 0400, |
Lloyd Atkinson | b020e0f | 2017-03-14 08:05:18 -0700 | [diff] [blame] | 4343 | sde_crtc->debugfs_root, |
| 4344 | sde_crtc, &debugfs_status_fops); |
Lloyd Atkinson | 8de415a | 2017-05-23 11:31:16 -0400 | [diff] [blame] | 4345 | debugfs_create_file("state", 0600, |
Lloyd Atkinson | b020e0f | 2017-03-14 08:05:18 -0700 | [diff] [blame] | 4346 | sde_crtc->debugfs_root, |
| 4347 | &sde_crtc->base, |
| 4348 | &sde_crtc_debugfs_state_fops); |
Lloyd Atkinson | 8de415a | 2017-05-23 11:31:16 -0400 | [diff] [blame] | 4349 | debugfs_create_file("misr_data", 0600, sde_crtc->debugfs_root, |
Dhaval Patel | f9245d6 | 2017-03-28 16:24:00 -0700 | [diff] [blame] | 4350 | sde_crtc, &debugfs_misr_fops); |
Lloyd Atkinson | b020e0f | 2017-03-14 08:05:18 -0700 | [diff] [blame] | 4351 | |
| 4352 | return 0; |
| 4353 | } |
| 4354 | |
| 4355 | static void _sde_crtc_destroy_debugfs(struct drm_crtc *crtc) |
| 4356 | { |
| 4357 | struct sde_crtc *sde_crtc; |
| 4358 | |
| 4359 | if (!crtc) |
| 4360 | return; |
| 4361 | sde_crtc = to_sde_crtc(crtc); |
| 4362 | debugfs_remove_recursive(sde_crtc->debugfs_root); |
Clarence Ip | 8f7366c | 2016-07-05 12:15:26 -0400 | [diff] [blame] | 4363 | } |
Alan Kwong | 67a3f79 | 2016-11-01 23:16:53 -0400 | [diff] [blame] | 4364 | #else |
Lloyd Atkinson | b020e0f | 2017-03-14 08:05:18 -0700 | [diff] [blame] | 4365 | static int _sde_crtc_init_debugfs(struct drm_crtc *crtc) |
Alan Kwong | 67a3f79 | 2016-11-01 23:16:53 -0400 | [diff] [blame] | 4366 | { |
Lloyd Atkinson | b020e0f | 2017-03-14 08:05:18 -0700 | [diff] [blame] | 4367 | return 0; |
Alan Kwong | 67a3f79 | 2016-11-01 23:16:53 -0400 | [diff] [blame] | 4368 | } |
Lloyd Atkinson | b020e0f | 2017-03-14 08:05:18 -0700 | [diff] [blame] | 4369 | |
| 4370 | static void _sde_crtc_destroy_debugfs(struct drm_crtc *crtc) |
| 4371 | { |
Lloyd Atkinson | b020e0f | 2017-03-14 08:05:18 -0700 | [diff] [blame] | 4372 | } |
| 4373 | #endif /* CONFIG_DEBUG_FS */ |
| 4374 | |
| 4375 | static int sde_crtc_late_register(struct drm_crtc *crtc) |
| 4376 | { |
| 4377 | return _sde_crtc_init_debugfs(crtc); |
| 4378 | } |
| 4379 | |
| 4380 | static void sde_crtc_early_unregister(struct drm_crtc *crtc) |
| 4381 | { |
| 4382 | _sde_crtc_destroy_debugfs(crtc); |
| 4383 | } |
| 4384 | |
| 4385 | static const struct drm_crtc_funcs sde_crtc_funcs = { |
| 4386 | .set_config = drm_atomic_helper_set_config, |
| 4387 | .destroy = sde_crtc_destroy, |
| 4388 | .page_flip = drm_atomic_helper_page_flip, |
| 4389 | .set_property = sde_crtc_set_property, |
| 4390 | .atomic_set_property = sde_crtc_atomic_set_property, |
| 4391 | .atomic_get_property = sde_crtc_atomic_get_property, |
| 4392 | .reset = sde_crtc_reset, |
| 4393 | .atomic_duplicate_state = sde_crtc_duplicate_state, |
| 4394 | .atomic_destroy_state = sde_crtc_destroy_state, |
| 4395 | .late_register = sde_crtc_late_register, |
| 4396 | .early_unregister = sde_crtc_early_unregister, |
| 4397 | }; |
| 4398 | |
| 4399 | static const struct drm_crtc_helper_funcs sde_crtc_helper_funcs = { |
| 4400 | .mode_fixup = sde_crtc_mode_fixup, |
| 4401 | .disable = sde_crtc_disable, |
| 4402 | .enable = sde_crtc_enable, |
| 4403 | .atomic_check = sde_crtc_atomic_check, |
| 4404 | .atomic_begin = sde_crtc_atomic_begin, |
| 4405 | .atomic_flush = sde_crtc_atomic_flush, |
| 4406 | }; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 4407 | |
Clarence Ip | a18d483 | 2017-03-13 12:35:44 -0700 | [diff] [blame] | 4408 | static void _sde_crtc_event_cb(struct kthread_work *work) |
| 4409 | { |
| 4410 | struct sde_crtc_event *event; |
| 4411 | struct sde_crtc *sde_crtc; |
| 4412 | unsigned long irq_flags; |
| 4413 | |
| 4414 | if (!work) { |
| 4415 | SDE_ERROR("invalid work item\n"); |
| 4416 | return; |
| 4417 | } |
| 4418 | |
| 4419 | event = container_of(work, struct sde_crtc_event, kt_work); |
Clarence Ip | a18d483 | 2017-03-13 12:35:44 -0700 | [diff] [blame] | 4420 | |
| 4421 | /* set sde_crtc to NULL for static work structures */ |
| 4422 | sde_crtc = event->sde_crtc; |
| 4423 | if (!sde_crtc) |
| 4424 | return; |
| 4425 | |
Gopikrishnaiah Anandan | b6b401f | 2017-03-14 16:39:49 -0700 | [diff] [blame] | 4426 | if (event->cb_func) |
| 4427 | event->cb_func(&sde_crtc->base, event->usr); |
| 4428 | |
Clarence Ip | a18d483 | 2017-03-13 12:35:44 -0700 | [diff] [blame] | 4429 | spin_lock_irqsave(&sde_crtc->event_lock, irq_flags); |
| 4430 | list_add_tail(&event->list, &sde_crtc->event_free_list); |
| 4431 | spin_unlock_irqrestore(&sde_crtc->event_lock, irq_flags); |
| 4432 | } |
| 4433 | |
| 4434 | int sde_crtc_event_queue(struct drm_crtc *crtc, |
Gopikrishnaiah Anandan | b6b401f | 2017-03-14 16:39:49 -0700 | [diff] [blame] | 4435 | void (*func)(struct drm_crtc *crtc, void *usr), void *usr) |
Clarence Ip | a18d483 | 2017-03-13 12:35:44 -0700 | [diff] [blame] | 4436 | { |
| 4437 | unsigned long irq_flags; |
| 4438 | struct sde_crtc *sde_crtc; |
Veera Sundaram Sankaran | 10ea2bd | 2017-06-14 14:10:57 -0700 | [diff] [blame] | 4439 | struct msm_drm_private *priv; |
Clarence Ip | a18d483 | 2017-03-13 12:35:44 -0700 | [diff] [blame] | 4440 | struct sde_crtc_event *event = NULL; |
Veera Sundaram Sankaran | 10ea2bd | 2017-06-14 14:10:57 -0700 | [diff] [blame] | 4441 | u32 crtc_id; |
Clarence Ip | a18d483 | 2017-03-13 12:35:44 -0700 | [diff] [blame] | 4442 | |
Veera Sundaram Sankaran | 10ea2bd | 2017-06-14 14:10:57 -0700 | [diff] [blame] | 4443 | if (!crtc || !crtc->dev || !crtc->dev->dev_private || !func) { |
| 4444 | SDE_ERROR("invalid parameters\n"); |
Clarence Ip | a18d483 | 2017-03-13 12:35:44 -0700 | [diff] [blame] | 4445 | return -EINVAL; |
Veera Sundaram Sankaran | 10ea2bd | 2017-06-14 14:10:57 -0700 | [diff] [blame] | 4446 | } |
Clarence Ip | a18d483 | 2017-03-13 12:35:44 -0700 | [diff] [blame] | 4447 | sde_crtc = to_sde_crtc(crtc); |
Veera Sundaram Sankaran | 10ea2bd | 2017-06-14 14:10:57 -0700 | [diff] [blame] | 4448 | priv = crtc->dev->dev_private; |
| 4449 | crtc_id = drm_crtc_index(crtc); |
Clarence Ip | a18d483 | 2017-03-13 12:35:44 -0700 | [diff] [blame] | 4450 | |
| 4451 | /* |
| 4452 | * Obtain an event struct from the private cache. This event |
| 4453 | * queue may be called from ISR contexts, so use a private |
| 4454 | * cache to avoid calling any memory allocation functions. |
| 4455 | */ |
| 4456 | spin_lock_irqsave(&sde_crtc->event_lock, irq_flags); |
| 4457 | if (!list_empty(&sde_crtc->event_free_list)) { |
| 4458 | event = list_first_entry(&sde_crtc->event_free_list, |
| 4459 | struct sde_crtc_event, list); |
| 4460 | list_del_init(&event->list); |
| 4461 | } |
| 4462 | spin_unlock_irqrestore(&sde_crtc->event_lock, irq_flags); |
| 4463 | |
| 4464 | if (!event) |
| 4465 | return -ENOMEM; |
| 4466 | |
| 4467 | /* populate event node */ |
| 4468 | event->sde_crtc = sde_crtc; |
| 4469 | event->cb_func = func; |
| 4470 | event->usr = usr; |
| 4471 | |
| 4472 | /* queue new event request */ |
| 4473 | kthread_init_work(&event->kt_work, _sde_crtc_event_cb); |
Veera Sundaram Sankaran | 10ea2bd | 2017-06-14 14:10:57 -0700 | [diff] [blame] | 4474 | kthread_queue_work(&priv->event_thread[crtc_id].worker, |
| 4475 | &event->kt_work); |
Clarence Ip | a18d483 | 2017-03-13 12:35:44 -0700 | [diff] [blame] | 4476 | |
| 4477 | return 0; |
| 4478 | } |
| 4479 | |
| 4480 | static int _sde_crtc_init_events(struct sde_crtc *sde_crtc) |
| 4481 | { |
| 4482 | int i, rc = 0; |
| 4483 | |
| 4484 | if (!sde_crtc) { |
| 4485 | SDE_ERROR("invalid crtc\n"); |
| 4486 | return -EINVAL; |
| 4487 | } |
| 4488 | |
| 4489 | spin_lock_init(&sde_crtc->event_lock); |
| 4490 | |
| 4491 | INIT_LIST_HEAD(&sde_crtc->event_free_list); |
| 4492 | for (i = 0; i < SDE_CRTC_MAX_EVENT_COUNT; ++i) |
| 4493 | list_add_tail(&sde_crtc->event_cache[i].list, |
| 4494 | &sde_crtc->event_free_list); |
| 4495 | |
Dhaval Patel | 5023c3c | 2017-08-22 12:40:11 -0700 | [diff] [blame^] | 4496 | INIT_LIST_HEAD(&sde_crtc->retire_event_list); |
| 4497 | for (i = 0; i < ARRAY_SIZE(sde_crtc->retire_events); i++) |
| 4498 | INIT_LIST_HEAD(&sde_crtc->retire_events[i].list); |
| 4499 | |
Clarence Ip | a18d483 | 2017-03-13 12:35:44 -0700 | [diff] [blame] | 4500 | return rc; |
| 4501 | } |
| 4502 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 4503 | /* initialize crtc */ |
Lloyd Atkinson | ac93364 | 2016-09-14 11:52:00 -0400 | [diff] [blame] | 4504 | struct drm_crtc *sde_crtc_init(struct drm_device *dev, struct drm_plane *plane) |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 4505 | { |
| 4506 | struct drm_crtc *crtc = NULL; |
Clarence Ip | 8f7366c | 2016-07-05 12:15:26 -0400 | [diff] [blame] | 4507 | struct sde_crtc *sde_crtc = NULL; |
| 4508 | struct msm_drm_private *priv = NULL; |
| 4509 | struct sde_kms *kms = NULL; |
Clarence Ip | a18d483 | 2017-03-13 12:35:44 -0700 | [diff] [blame] | 4510 | int i, rc; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 4511 | |
Clarence Ip | 8f7366c | 2016-07-05 12:15:26 -0400 | [diff] [blame] | 4512 | priv = dev->dev_private; |
| 4513 | kms = to_sde_kms(priv->kms); |
| 4514 | |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 4515 | sde_crtc = kzalloc(sizeof(*sde_crtc), GFP_KERNEL); |
| 4516 | if (!sde_crtc) |
| 4517 | return ERR_PTR(-ENOMEM); |
| 4518 | |
| 4519 | crtc = &sde_crtc->base; |
Gopikrishnaiah Anandan | e0e5e0c | 2016-05-25 11:05:33 -0700 | [diff] [blame] | 4520 | crtc->dev = dev; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 4521 | |
Clarence Ip | 7f70ce4 | 2017-03-20 06:53:46 -0700 | [diff] [blame] | 4522 | mutex_init(&sde_crtc->crtc_lock); |
Alan Kwong | 628d19e | 2016-10-31 13:50:13 -0400 | [diff] [blame] | 4523 | spin_lock_init(&sde_crtc->spin_lock); |
| 4524 | atomic_set(&sde_crtc->frame_pending, 0); |
| 4525 | |
Alan Kwong | 310e9b0 | 2017-08-03 02:04:07 -0400 | [diff] [blame] | 4526 | mutex_init(&sde_crtc->rp_lock); |
| 4527 | INIT_LIST_HEAD(&sde_crtc->rp_head); |
| 4528 | |
Veera Sundaram Sankaran | 7ee9909 | 2017-06-13 11:19:36 -0700 | [diff] [blame] | 4529 | init_completion(&sde_crtc->frame_done_comp); |
| 4530 | |
Alan Kwong | 628d19e | 2016-10-31 13:50:13 -0400 | [diff] [blame] | 4531 | INIT_LIST_HEAD(&sde_crtc->frame_event_list); |
Gopikrishnaiah Anandan | de2c81b | 2017-03-15 12:41:29 -0700 | [diff] [blame] | 4532 | INIT_LIST_HEAD(&sde_crtc->user_event_list); |
Alan Kwong | 628d19e | 2016-10-31 13:50:13 -0400 | [diff] [blame] | 4533 | for (i = 0; i < ARRAY_SIZE(sde_crtc->frame_events); i++) { |
| 4534 | INIT_LIST_HEAD(&sde_crtc->frame_events[i].list); |
| 4535 | list_add(&sde_crtc->frame_events[i].list, |
| 4536 | &sde_crtc->frame_event_list); |
| 4537 | kthread_init_work(&sde_crtc->frame_events[i].work, |
| 4538 | sde_crtc_frame_event_work); |
| 4539 | } |
| 4540 | |
Dhaval Patel | 04c7e8e | 2016-09-26 20:14:31 -0700 | [diff] [blame] | 4541 | drm_crtc_init_with_planes(dev, crtc, plane, NULL, &sde_crtc_funcs, |
| 4542 | NULL); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 4543 | |
| 4544 | drm_crtc_helper_add(crtc, &sde_crtc_helper_funcs); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 4545 | plane->crtc = crtc; |
| 4546 | |
Clarence Ip | 8f7366c | 2016-07-05 12:15:26 -0400 | [diff] [blame] | 4547 | /* save user friendly CRTC name for later */ |
| 4548 | snprintf(sde_crtc->name, SDE_CRTC_NAME_SIZE, "crtc%u", crtc->base.id); |
| 4549 | |
Clarence Ip | a18d483 | 2017-03-13 12:35:44 -0700 | [diff] [blame] | 4550 | /* initialize event handling */ |
| 4551 | rc = _sde_crtc_init_events(sde_crtc); |
| 4552 | if (rc) { |
| 4553 | drm_crtc_cleanup(crtc); |
| 4554 | kfree(sde_crtc); |
| 4555 | return ERR_PTR(rc); |
| 4556 | } |
| 4557 | |
Clarence Ip | 9a74a44 | 2016-08-25 18:29:03 -0400 | [diff] [blame] | 4558 | /* initialize output fence support */ |
Lloyd Atkinson | 5d40d31 | 2016-09-06 08:34:13 -0400 | [diff] [blame] | 4559 | sde_fence_init(&sde_crtc->output_fence, sde_crtc->name, crtc->base.id); |
Clarence Ip | 24f8066 | 2016-06-13 19:05:32 -0400 | [diff] [blame] | 4560 | |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 4561 | /* create CRTC properties */ |
| 4562 | msm_property_init(&sde_crtc->property_info, &crtc->base, dev, |
| 4563 | priv->crtc_property, sde_crtc->property_data, |
| 4564 | CRTC_PROP_COUNT, CRTC_PROP_BLOBCOUNT, |
| 4565 | sizeof(struct sde_crtc_state)); |
| 4566 | |
Dhaval Patel | e4a5dda | 2016-10-13 19:29:30 -0700 | [diff] [blame] | 4567 | sde_crtc_install_properties(crtc, kms->catalog); |
Gopikrishnaiah Anandan | 703eb90 | 2016-10-06 18:43:57 -0700 | [diff] [blame] | 4568 | |
| 4569 | /* Install color processing properties */ |
Gopikrishnaiah Anandan | e0e5e0c | 2016-05-25 11:05:33 -0700 | [diff] [blame] | 4570 | sde_cp_crtc_init(crtc); |
Gopikrishnaiah Anandan | 703eb90 | 2016-10-06 18:43:57 -0700 | [diff] [blame] | 4571 | sde_cp_crtc_install_properties(crtc); |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 4572 | |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 4573 | SDE_DEBUG("%s: successfully initialized crtc\n", sde_crtc->name); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 4574 | return crtc; |
| 4575 | } |
Gopikrishnaiah Anandan | de2c81b | 2017-03-15 12:41:29 -0700 | [diff] [blame] | 4576 | |
Gopikrishnaiah Anandan | 5154c71 | 2017-02-27 17:48:24 -0800 | [diff] [blame] | 4577 | static int _sde_crtc_event_enable(struct sde_kms *kms, |
| 4578 | struct drm_crtc *crtc_drm, u32 event) |
Gopikrishnaiah Anandan | de2c81b | 2017-03-15 12:41:29 -0700 | [diff] [blame] | 4579 | { |
Gopikrishnaiah Anandan | 5154c71 | 2017-02-27 17:48:24 -0800 | [diff] [blame] | 4580 | struct sde_crtc *crtc = NULL; |
| 4581 | struct sde_crtc_irq_info *node; |
| 4582 | struct msm_drm_private *priv; |
| 4583 | unsigned long flags; |
| 4584 | bool found = false; |
Gopikrishnaiah Anandan | b6b401f | 2017-03-14 16:39:49 -0700 | [diff] [blame] | 4585 | int ret, i = 0; |
Gopikrishnaiah Anandan | 5154c71 | 2017-02-27 17:48:24 -0800 | [diff] [blame] | 4586 | |
| 4587 | crtc = to_sde_crtc(crtc_drm); |
| 4588 | spin_lock_irqsave(&crtc->spin_lock, flags); |
| 4589 | list_for_each_entry(node, &crtc->user_event_list, list) { |
| 4590 | if (node->event == event) { |
| 4591 | found = true; |
| 4592 | break; |
| 4593 | } |
| 4594 | } |
| 4595 | spin_unlock_irqrestore(&crtc->spin_lock, flags); |
| 4596 | |
| 4597 | /* event already enabled */ |
| 4598 | if (found) |
| 4599 | return 0; |
| 4600 | |
Gopikrishnaiah Anandan | b6b401f | 2017-03-14 16:39:49 -0700 | [diff] [blame] | 4601 | node = NULL; |
| 4602 | for (i = 0; i < ARRAY_SIZE(custom_events); i++) { |
| 4603 | if (custom_events[i].event == event && |
| 4604 | custom_events[i].func) { |
| 4605 | node = kzalloc(sizeof(*node), GFP_KERNEL); |
| 4606 | if (!node) |
| 4607 | return -ENOMEM; |
| 4608 | node->event = event; |
| 4609 | INIT_LIST_HEAD(&node->list); |
| 4610 | node->func = custom_events[i].func; |
| 4611 | node->event = event; |
| 4612 | break; |
| 4613 | } |
| 4614 | } |
Gopikrishnaiah Anandan | 5154c71 | 2017-02-27 17:48:24 -0800 | [diff] [blame] | 4615 | |
Gopikrishnaiah Anandan | b6b401f | 2017-03-14 16:39:49 -0700 | [diff] [blame] | 4616 | if (!node) { |
Gopikrishnaiah Anandan | 5154c71 | 2017-02-27 17:48:24 -0800 | [diff] [blame] | 4617 | SDE_ERROR("unsupported event %x\n", event); |
Gopikrishnaiah Anandan | 5154c71 | 2017-02-27 17:48:24 -0800 | [diff] [blame] | 4618 | return -EINVAL; |
| 4619 | } |
| 4620 | |
| 4621 | priv = kms->dev->dev_private; |
| 4622 | ret = 0; |
| 4623 | if (crtc_drm->enabled) { |
| 4624 | sde_power_resource_enable(&priv->phandle, kms->core_client, |
| 4625 | true); |
| 4626 | ret = node->func(crtc_drm, true, &node->irq); |
| 4627 | sde_power_resource_enable(&priv->phandle, kms->core_client, |
| 4628 | false); |
| 4629 | } |
| 4630 | |
| 4631 | if (!ret) { |
| 4632 | spin_lock_irqsave(&crtc->spin_lock, flags); |
| 4633 | list_add_tail(&node->list, &crtc->user_event_list); |
| 4634 | spin_unlock_irqrestore(&crtc->spin_lock, flags); |
| 4635 | } else { |
| 4636 | kfree(node); |
| 4637 | } |
| 4638 | |
| 4639 | return ret; |
| 4640 | } |
| 4641 | |
| 4642 | static int _sde_crtc_event_disable(struct sde_kms *kms, |
| 4643 | struct drm_crtc *crtc_drm, u32 event) |
| 4644 | { |
| 4645 | struct sde_crtc *crtc = NULL; |
| 4646 | struct sde_crtc_irq_info *node = NULL; |
| 4647 | struct msm_drm_private *priv; |
| 4648 | unsigned long flags; |
| 4649 | bool found = false; |
| 4650 | int ret; |
| 4651 | |
| 4652 | crtc = to_sde_crtc(crtc_drm); |
| 4653 | spin_lock_irqsave(&crtc->spin_lock, flags); |
| 4654 | list_for_each_entry(node, &crtc->user_event_list, list) { |
| 4655 | if (node->event == event) { |
| 4656 | list_del(&node->list); |
| 4657 | found = true; |
| 4658 | break; |
| 4659 | } |
| 4660 | } |
| 4661 | spin_unlock_irqrestore(&crtc->spin_lock, flags); |
| 4662 | |
| 4663 | /* event already disabled */ |
| 4664 | if (!found) |
| 4665 | return 0; |
| 4666 | |
| 4667 | /** |
| 4668 | * crtc is disabled interrupts are cleared remove from the list, |
| 4669 | * no need to disable/de-register. |
| 4670 | */ |
| 4671 | if (!crtc_drm->enabled) { |
| 4672 | kfree(node); |
| 4673 | return 0; |
| 4674 | } |
| 4675 | priv = kms->dev->dev_private; |
| 4676 | sde_power_resource_enable(&priv->phandle, kms->core_client, true); |
| 4677 | ret = node->func(crtc_drm, false, &node->irq); |
| 4678 | sde_power_resource_enable(&priv->phandle, kms->core_client, false); |
| 4679 | return ret; |
| 4680 | } |
| 4681 | |
| 4682 | int sde_crtc_register_custom_event(struct sde_kms *kms, |
| 4683 | struct drm_crtc *crtc_drm, u32 event, bool en) |
| 4684 | { |
| 4685 | struct sde_crtc *crtc = NULL; |
| 4686 | int ret; |
| 4687 | |
| 4688 | crtc = to_sde_crtc(crtc_drm); |
| 4689 | if (!crtc || !kms || !kms->dev) { |
| 4690 | DRM_ERROR("invalid sde_crtc %pK kms %pK dev %pK\n", crtc, |
| 4691 | kms, ((kms) ? (kms->dev) : NULL)); |
| 4692 | return -EINVAL; |
| 4693 | } |
| 4694 | |
| 4695 | if (en) |
| 4696 | ret = _sde_crtc_event_enable(kms, crtc_drm, event); |
| 4697 | else |
| 4698 | ret = _sde_crtc_event_disable(kms, crtc_drm, event); |
| 4699 | |
| 4700 | return ret; |
Gopikrishnaiah Anandan | de2c81b | 2017-03-15 12:41:29 -0700 | [diff] [blame] | 4701 | } |
Gopikrishnaiah Anandan | 84b4f67 | 2017-04-26 10:28:51 -0700 | [diff] [blame] | 4702 | |
| 4703 | static int sde_crtc_power_interrupt_handler(struct drm_crtc *crtc_drm, |
| 4704 | bool en, struct sde_irq_callback *irq) |
| 4705 | { |
| 4706 | return 0; |
| 4707 | } |
Benjamin Chan | 9013910 | 2017-06-21 16:00:39 -0400 | [diff] [blame] | 4708 | |
| 4709 | static int sde_crtc_pm_event_handler(struct drm_crtc *crtc, bool en, |
| 4710 | struct sde_irq_callback *noirq) |
| 4711 | { |
| 4712 | /* |
| 4713 | * IRQ object noirq is not being used here since there is |
| 4714 | * no crtc irq from pm event. |
| 4715 | */ |
| 4716 | return 0; |
| 4717 | } |