Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2013 Red Hat |
| 3 | * Author: Rob Clark <robdclark@gmail.com> |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify it |
| 6 | * under the terms of the GNU General Public License version 2 as published by |
| 7 | * the Free Software Foundation. |
| 8 | * |
| 9 | * This program is distributed in the hope that it will be useful, but WITHOUT |
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 12 | * more details. |
| 13 | * |
| 14 | * You should have received a copy of the GNU General Public License along with |
| 15 | * this program. If not, see <http://www.gnu.org/licenses/>. |
| 16 | */ |
| 17 | |
| 18 | #ifndef __MSM_DRV_H__ |
| 19 | #define __MSM_DRV_H__ |
| 20 | |
| 21 | #include <linux/kernel.h> |
| 22 | #include <linux/clk.h> |
| 23 | #include <linux/cpufreq.h> |
| 24 | #include <linux/module.h> |
Rob Clark | 060530f | 2014-03-03 14:19:12 -0500 | [diff] [blame] | 25 | #include <linux/component.h> |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 26 | #include <linux/platform_device.h> |
| 27 | #include <linux/pm.h> |
| 28 | #include <linux/pm_runtime.h> |
| 29 | #include <linux/slab.h> |
| 30 | #include <linux/list.h> |
| 31 | #include <linux/iommu.h> |
| 32 | #include <linux/types.h> |
Archit Taneja | 3d6df06 | 2015-06-09 14:17:22 +0530 | [diff] [blame] | 33 | #include <linux/of_graph.h> |
Archit Taneja | e9fbdaf | 2015-11-18 12:15:14 +0530 | [diff] [blame] | 34 | #include <linux/of_device.h> |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 35 | #include <asm/sizes.h> |
| 36 | |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 37 | #include <drm/drmP.h> |
Rob Clark | cf3a7e4 | 2014-11-08 13:21:06 -0500 | [diff] [blame] | 38 | #include <drm/drm_atomic.h> |
| 39 | #include <drm/drm_atomic_helper.h> |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 40 | #include <drm/drm_crtc_helper.h> |
Rob Clark | cf3a7e4 | 2014-11-08 13:21:06 -0500 | [diff] [blame] | 41 | #include <drm/drm_plane_helper.h> |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 42 | #include <drm/drm_fb_helper.h> |
Rob Clark | 7198e6b | 2013-07-19 12:59:32 -0400 | [diff] [blame] | 43 | #include <drm/msm_drm.h> |
Daniel Vetter | d9fc941 | 2014-09-23 15:46:53 +0200 | [diff] [blame] | 44 | #include <drm/drm_gem.h> |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 45 | |
| 46 | struct msm_kms; |
Rob Clark | 7198e6b | 2013-07-19 12:59:32 -0400 | [diff] [blame] | 47 | struct msm_gpu; |
Rob Clark | 871d812 | 2013-11-16 12:56:06 -0500 | [diff] [blame] | 48 | struct msm_mmu; |
Rob Clark | a7d3c95 | 2014-05-30 14:47:38 -0400 | [diff] [blame] | 49 | struct msm_rd_state; |
Rob Clark | 70c70f0 | 2014-05-30 14:49:43 -0400 | [diff] [blame] | 50 | struct msm_perf_state; |
Rob Clark | a7d3c95 | 2014-05-30 14:47:38 -0400 | [diff] [blame] | 51 | struct msm_gem_submit; |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 52 | |
Rob Clark | 7198e6b | 2013-07-19 12:59:32 -0400 | [diff] [blame] | 53 | #define NUM_DOMAINS 2 /* one for KMS, then one per gpu core (?) */ |
| 54 | |
| 55 | struct msm_file_private { |
| 56 | /* currently we don't do anything useful with this.. but when |
| 57 | * per-context address spaces are supported we'd keep track of |
| 58 | * the context's page-tables here. |
| 59 | */ |
| 60 | int dummy; |
| 61 | }; |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 62 | |
jilai wang | 1298778 | 2015-06-25 17:37:42 -0400 | [diff] [blame] | 63 | enum msm_mdp_plane_property { |
| 64 | PLANE_PROP_ZPOS, |
| 65 | PLANE_PROP_ALPHA, |
| 66 | PLANE_PROP_PREMULTIPLIED, |
| 67 | PLANE_PROP_MAX_NUM |
| 68 | }; |
| 69 | |
Hai Li | 78b1d47 | 2015-07-27 13:49:45 -0400 | [diff] [blame] | 70 | struct msm_vblank_ctrl { |
| 71 | struct work_struct work; |
| 72 | struct list_head event_list; |
| 73 | spinlock_t lock; |
| 74 | }; |
| 75 | |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 76 | struct msm_drm_private { |
| 77 | |
| 78 | struct msm_kms *kms; |
| 79 | |
Rob Clark | 060530f | 2014-03-03 14:19:12 -0500 | [diff] [blame] | 80 | /* subordinate devices, if present: */ |
Rob Clark | 067fef3 | 2014-11-04 13:33:14 -0500 | [diff] [blame] | 81 | struct platform_device *gpu_pdev; |
| 82 | |
| 83 | /* possibly this should be in the kms component, but it is |
| 84 | * shared by both mdp4 and mdp5.. |
| 85 | */ |
| 86 | struct hdmi *hdmi; |
Rob Clark | 060530f | 2014-03-03 14:19:12 -0500 | [diff] [blame] | 87 | |
Hai Li | ab5b010 | 2015-01-07 18:47:44 -0500 | [diff] [blame] | 88 | /* eDP is for mdp5 only, but kms has not been created |
| 89 | * when edp_bind() and edp_init() are called. Here is the only |
| 90 | * place to keep the edp instance. |
| 91 | */ |
| 92 | struct msm_edp *edp; |
| 93 | |
Hai Li | a689554 | 2015-03-31 14:36:33 -0400 | [diff] [blame] | 94 | /* DSI is shared by mdp4 and mdp5 */ |
| 95 | struct msm_dsi *dsi[2]; |
| 96 | |
Rob Clark | 7198e6b | 2013-07-19 12:59:32 -0400 | [diff] [blame] | 97 | /* when we have more than one 'msm_gpu' these need to be an array: */ |
| 98 | struct msm_gpu *gpu; |
| 99 | struct msm_file_private *lastctx; |
| 100 | |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 101 | struct drm_fb_helper *fbdev; |
| 102 | |
Rob Clark | 7198e6b | 2013-07-19 12:59:32 -0400 | [diff] [blame] | 103 | uint32_t next_fence, completed_fence; |
| 104 | wait_queue_head_t fence_event; |
| 105 | |
Rob Clark | a7d3c95 | 2014-05-30 14:47:38 -0400 | [diff] [blame] | 106 | struct msm_rd_state *rd; |
Rob Clark | 70c70f0 | 2014-05-30 14:49:43 -0400 | [diff] [blame] | 107 | struct msm_perf_state *perf; |
Rob Clark | a7d3c95 | 2014-05-30 14:47:38 -0400 | [diff] [blame] | 108 | |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 109 | /* list of GEM objects: */ |
| 110 | struct list_head inactive_list; |
| 111 | |
| 112 | struct workqueue_struct *wq; |
| 113 | |
Rob Clark | edd4fc6 | 2013-09-14 14:01:55 -0400 | [diff] [blame] | 114 | /* callbacks deferred until bo is inactive: */ |
| 115 | struct list_head fence_cbs; |
| 116 | |
Rob Clark | f86afec | 2014-11-25 12:41:18 -0500 | [diff] [blame] | 117 | /* crtcs pending async atomic updates: */ |
| 118 | uint32_t pending_crtcs; |
| 119 | wait_queue_head_t pending_crtcs_event; |
| 120 | |
Rob Clark | 871d812 | 2013-11-16 12:56:06 -0500 | [diff] [blame] | 121 | /* registered MMUs: */ |
| 122 | unsigned int num_mmus; |
| 123 | struct msm_mmu *mmus[NUM_DOMAINS]; |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 124 | |
Rob Clark | a862391 | 2013-10-08 12:57:48 -0400 | [diff] [blame] | 125 | unsigned int num_planes; |
| 126 | struct drm_plane *planes[8]; |
| 127 | |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 128 | unsigned int num_crtcs; |
| 129 | struct drm_crtc *crtcs[8]; |
| 130 | |
| 131 | unsigned int num_encoders; |
| 132 | struct drm_encoder *encoders[8]; |
| 133 | |
Rob Clark | a3376e3 | 2013-08-30 13:02:15 -0400 | [diff] [blame] | 134 | unsigned int num_bridges; |
| 135 | struct drm_bridge *bridges[8]; |
| 136 | |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 137 | unsigned int num_connectors; |
| 138 | struct drm_connector *connectors[8]; |
Rob Clark | 871d812 | 2013-11-16 12:56:06 -0500 | [diff] [blame] | 139 | |
jilai wang | 1298778 | 2015-06-25 17:37:42 -0400 | [diff] [blame] | 140 | /* Properties */ |
| 141 | struct drm_property *plane_property[PLANE_PROP_MAX_NUM]; |
| 142 | |
Rob Clark | 871d812 | 2013-11-16 12:56:06 -0500 | [diff] [blame] | 143 | /* VRAM carveout, used when no IOMMU: */ |
| 144 | struct { |
| 145 | unsigned long size; |
| 146 | dma_addr_t paddr; |
| 147 | /* NOTE: mm managed at the page level, size is in # of pages |
| 148 | * and position mm_node->start is in # of pages: |
| 149 | */ |
| 150 | struct drm_mm mm; |
| 151 | } vram; |
Hai Li | 78b1d47 | 2015-07-27 13:49:45 -0400 | [diff] [blame] | 152 | |
| 153 | struct msm_vblank_ctrl vblank_ctrl; |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 154 | }; |
| 155 | |
| 156 | struct msm_format { |
| 157 | uint32_t pixel_format; |
| 158 | }; |
| 159 | |
Rob Clark | edd4fc6 | 2013-09-14 14:01:55 -0400 | [diff] [blame] | 160 | /* callback from wq once fence has passed: */ |
| 161 | struct msm_fence_cb { |
| 162 | struct work_struct work; |
| 163 | uint32_t fence; |
| 164 | void (*func)(struct msm_fence_cb *cb); |
| 165 | }; |
| 166 | |
| 167 | void __msm_fence_worker(struct work_struct *work); |
| 168 | |
| 169 | #define INIT_FENCE_CB(_cb, _func) do { \ |
| 170 | INIT_WORK(&(_cb)->work, __msm_fence_worker); \ |
| 171 | (_cb)->func = _func; \ |
| 172 | } while (0) |
| 173 | |
Daniel Vetter | b4274fb | 2014-11-26 17:02:18 +0100 | [diff] [blame] | 174 | int msm_atomic_check(struct drm_device *dev, |
| 175 | struct drm_atomic_state *state); |
Rob Clark | cf3a7e4 | 2014-11-08 13:21:06 -0500 | [diff] [blame] | 176 | int msm_atomic_commit(struct drm_device *dev, |
| 177 | struct drm_atomic_state *state, bool async); |
| 178 | |
Rob Clark | 871d812 | 2013-11-16 12:56:06 -0500 | [diff] [blame] | 179 | int msm_register_mmu(struct drm_device *dev, struct msm_mmu *mmu); |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 180 | |
Wentao Xu | a9702ca | 2015-06-22 11:53:42 -0400 | [diff] [blame] | 181 | int msm_wait_fence(struct drm_device *dev, uint32_t fence, |
| 182 | ktime_t *timeout, bool interruptible); |
Rob Clark | 69193e5 | 2014-11-07 18:10:04 -0500 | [diff] [blame] | 183 | int msm_queue_fence_cb(struct drm_device *dev, |
| 184 | struct msm_fence_cb *cb, uint32_t fence); |
Rob Clark | 7198e6b | 2013-07-19 12:59:32 -0400 | [diff] [blame] | 185 | void msm_update_fence(struct drm_device *dev, uint32_t fence); |
| 186 | |
| 187 | int msm_ioctl_gem_submit(struct drm_device *dev, void *data, |
| 188 | struct drm_file *file); |
| 189 | |
Daniel Thompson | 77a147e | 2014-11-12 11:38:14 +0000 | [diff] [blame] | 190 | int msm_gem_mmap_obj(struct drm_gem_object *obj, |
| 191 | struct vm_area_struct *vma); |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 192 | int msm_gem_mmap(struct file *filp, struct vm_area_struct *vma); |
| 193 | int msm_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf); |
| 194 | uint64_t msm_gem_mmap_offset(struct drm_gem_object *obj); |
| 195 | int msm_gem_get_iova_locked(struct drm_gem_object *obj, int id, |
| 196 | uint32_t *iova); |
| 197 | int msm_gem_get_iova(struct drm_gem_object *obj, int id, uint32_t *iova); |
Rob Clark | 2638d90 | 2014-11-08 09:13:37 -0500 | [diff] [blame] | 198 | uint32_t msm_gem_iova(struct drm_gem_object *obj, int id); |
Rob Clark | 05b8491 | 2013-09-28 11:28:35 -0400 | [diff] [blame] | 199 | struct page **msm_gem_get_pages(struct drm_gem_object *obj); |
| 200 | void msm_gem_put_pages(struct drm_gem_object *obj); |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 201 | void msm_gem_put_iova(struct drm_gem_object *obj, int id); |
| 202 | int msm_gem_dumb_create(struct drm_file *file, struct drm_device *dev, |
| 203 | struct drm_mode_create_dumb *args); |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 204 | int msm_gem_dumb_map_offset(struct drm_file *file, struct drm_device *dev, |
| 205 | uint32_t handle, uint64_t *offset); |
Rob Clark | 05b8491 | 2013-09-28 11:28:35 -0400 | [diff] [blame] | 206 | struct sg_table *msm_gem_prime_get_sg_table(struct drm_gem_object *obj); |
| 207 | void *msm_gem_prime_vmap(struct drm_gem_object *obj); |
| 208 | void msm_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr); |
Daniel Thompson | 77a147e | 2014-11-12 11:38:14 +0000 | [diff] [blame] | 209 | int msm_gem_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma); |
Rob Clark | 05b8491 | 2013-09-28 11:28:35 -0400 | [diff] [blame] | 210 | struct drm_gem_object *msm_gem_prime_import_sg_table(struct drm_device *dev, |
Maarten Lankhorst | b5e9c1a | 2014-01-09 11:03:14 +0100 | [diff] [blame] | 211 | struct dma_buf_attachment *attach, struct sg_table *sg); |
Rob Clark | 05b8491 | 2013-09-28 11:28:35 -0400 | [diff] [blame] | 212 | int msm_gem_prime_pin(struct drm_gem_object *obj); |
| 213 | void msm_gem_prime_unpin(struct drm_gem_object *obj); |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 214 | void *msm_gem_vaddr_locked(struct drm_gem_object *obj); |
| 215 | void *msm_gem_vaddr(struct drm_gem_object *obj); |
Rob Clark | edd4fc6 | 2013-09-14 14:01:55 -0400 | [diff] [blame] | 216 | int msm_gem_queue_inactive_cb(struct drm_gem_object *obj, |
| 217 | struct msm_fence_cb *cb); |
Rob Clark | 7198e6b | 2013-07-19 12:59:32 -0400 | [diff] [blame] | 218 | void msm_gem_move_to_active(struct drm_gem_object *obj, |
Rob Clark | bf6811f | 2013-09-01 13:25:09 -0400 | [diff] [blame] | 219 | struct msm_gpu *gpu, bool write, uint32_t fence); |
Rob Clark | 7198e6b | 2013-07-19 12:59:32 -0400 | [diff] [blame] | 220 | void msm_gem_move_to_inactive(struct drm_gem_object *obj); |
| 221 | int msm_gem_cpu_prep(struct drm_gem_object *obj, uint32_t op, |
Rob Clark | 56c2da8 | 2015-05-11 11:50:03 -0400 | [diff] [blame] | 222 | ktime_t *timeout); |
Rob Clark | 7198e6b | 2013-07-19 12:59:32 -0400 | [diff] [blame] | 223 | int msm_gem_cpu_fini(struct drm_gem_object *obj); |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 224 | void msm_gem_free_object(struct drm_gem_object *obj); |
| 225 | int msm_gem_new_handle(struct drm_device *dev, struct drm_file *file, |
| 226 | uint32_t size, uint32_t flags, uint32_t *handle); |
| 227 | struct drm_gem_object *msm_gem_new(struct drm_device *dev, |
| 228 | uint32_t size, uint32_t flags); |
Rob Clark | 05b8491 | 2013-09-28 11:28:35 -0400 | [diff] [blame] | 229 | struct drm_gem_object *msm_gem_import(struct drm_device *dev, |
| 230 | uint32_t size, struct sg_table *sgt); |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 231 | |
Rob Clark | 2638d90 | 2014-11-08 09:13:37 -0500 | [diff] [blame] | 232 | int msm_framebuffer_prepare(struct drm_framebuffer *fb, int id); |
| 233 | void msm_framebuffer_cleanup(struct drm_framebuffer *fb, int id); |
| 234 | uint32_t msm_framebuffer_iova(struct drm_framebuffer *fb, int id, int plane); |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 235 | struct drm_gem_object *msm_framebuffer_bo(struct drm_framebuffer *fb, int plane); |
| 236 | const struct msm_format *msm_framebuffer_format(struct drm_framebuffer *fb); |
| 237 | struct drm_framebuffer *msm_framebuffer_init(struct drm_device *dev, |
Ville Syrjälä | 1eb8345 | 2015-11-11 19:11:29 +0200 | [diff] [blame] | 238 | const struct drm_mode_fb_cmd2 *mode_cmd, struct drm_gem_object **bos); |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 239 | struct drm_framebuffer *msm_framebuffer_create(struct drm_device *dev, |
Ville Syrjälä | 1eb8345 | 2015-11-11 19:11:29 +0200 | [diff] [blame] | 240 | struct drm_file *file, const struct drm_mode_fb_cmd2 *mode_cmd); |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 241 | |
| 242 | struct drm_fb_helper *msm_fbdev_init(struct drm_device *dev); |
| 243 | |
Rob Clark | dada25b | 2013-12-01 12:12:54 -0500 | [diff] [blame] | 244 | struct hdmi; |
Rob Clark | 067fef3 | 2014-11-04 13:33:14 -0500 | [diff] [blame] | 245 | int hdmi_modeset_init(struct hdmi *hdmi, struct drm_device *dev, |
| 246 | struct drm_encoder *encoder); |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 247 | void __init hdmi_register(void); |
| 248 | void __exit hdmi_unregister(void); |
| 249 | |
Hai Li | 0045398 | 2014-12-12 14:41:17 -0500 | [diff] [blame] | 250 | struct msm_edp; |
| 251 | void __init msm_edp_register(void); |
| 252 | void __exit msm_edp_unregister(void); |
| 253 | int msm_edp_modeset_init(struct msm_edp *edp, struct drm_device *dev, |
| 254 | struct drm_encoder *encoder); |
| 255 | |
Hai Li | a689554 | 2015-03-31 14:36:33 -0400 | [diff] [blame] | 256 | struct msm_dsi; |
| 257 | enum msm_dsi_encoder_id { |
| 258 | MSM_DSI_VIDEO_ENCODER_ID = 0, |
| 259 | MSM_DSI_CMD_ENCODER_ID = 1, |
| 260 | MSM_DSI_ENCODER_NUM = 2 |
| 261 | }; |
| 262 | #ifdef CONFIG_DRM_MSM_DSI |
| 263 | void __init msm_dsi_register(void); |
| 264 | void __exit msm_dsi_unregister(void); |
| 265 | int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, struct drm_device *dev, |
| 266 | struct drm_encoder *encoders[MSM_DSI_ENCODER_NUM]); |
| 267 | #else |
| 268 | static inline void __init msm_dsi_register(void) |
| 269 | { |
| 270 | } |
| 271 | static inline void __exit msm_dsi_unregister(void) |
| 272 | { |
| 273 | } |
| 274 | static inline int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, |
| 275 | struct drm_device *dev, |
| 276 | struct drm_encoder *encoders[MSM_DSI_ENCODER_NUM]) |
| 277 | { |
| 278 | return -EINVAL; |
| 279 | } |
| 280 | #endif |
| 281 | |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 282 | #ifdef CONFIG_DEBUG_FS |
| 283 | void msm_gem_describe(struct drm_gem_object *obj, struct seq_file *m); |
| 284 | void msm_gem_describe_objects(struct list_head *list, struct seq_file *m); |
| 285 | void msm_framebuffer_describe(struct drm_framebuffer *fb, struct seq_file *m); |
Rob Clark | a7d3c95 | 2014-05-30 14:47:38 -0400 | [diff] [blame] | 286 | int msm_debugfs_late_init(struct drm_device *dev); |
| 287 | int msm_rd_debugfs_init(struct drm_minor *minor); |
| 288 | void msm_rd_debugfs_cleanup(struct drm_minor *minor); |
| 289 | void msm_rd_dump_submit(struct msm_gem_submit *submit); |
Rob Clark | 70c70f0 | 2014-05-30 14:49:43 -0400 | [diff] [blame] | 290 | int msm_perf_debugfs_init(struct drm_minor *minor); |
| 291 | void msm_perf_debugfs_cleanup(struct drm_minor *minor); |
Rob Clark | a7d3c95 | 2014-05-30 14:47:38 -0400 | [diff] [blame] | 292 | #else |
| 293 | static inline int msm_debugfs_late_init(struct drm_device *dev) { return 0; } |
| 294 | static inline void msm_rd_dump_submit(struct msm_gem_submit *submit) {} |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 295 | #endif |
| 296 | |
| 297 | void __iomem *msm_ioremap(struct platform_device *pdev, const char *name, |
| 298 | const char *dbgname); |
| 299 | void msm_writel(u32 data, void __iomem *addr); |
| 300 | u32 msm_readl(const void __iomem *addr); |
| 301 | |
| 302 | #define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__) |
| 303 | #define VERB(fmt, ...) if (0) DRM_DEBUG(fmt"\n", ##__VA_ARGS__) |
| 304 | |
Rob Clark | f816f27 | 2013-09-11 17:34:07 -0400 | [diff] [blame] | 305 | static inline bool fence_completed(struct drm_device *dev, uint32_t fence) |
| 306 | { |
| 307 | struct msm_drm_private *priv = dev->dev_private; |
| 308 | return priv->completed_fence >= fence; |
| 309 | } |
| 310 | |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 311 | static inline int align_pitch(int width, int bpp) |
| 312 | { |
| 313 | int bytespp = (bpp + 7) / 8; |
| 314 | /* adreno needs pitch aligned to 32 pixels: */ |
| 315 | return bytespp * ALIGN(width, 32); |
| 316 | } |
| 317 | |
| 318 | /* for the generated headers: */ |
| 319 | #define INVALID_IDX(idx) ({BUG(); 0;}) |
Rob Clark | 7198e6b | 2013-07-19 12:59:32 -0400 | [diff] [blame] | 320 | #define fui(x) ({BUG(); 0;}) |
| 321 | #define util_float_to_half(x) ({BUG(); 0;}) |
| 322 | |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 323 | |
| 324 | #define FIELD(val, name) (((val) & name ## __MASK) >> name ## __SHIFT) |
| 325 | |
| 326 | /* for conditionally setting boolean flag(s): */ |
| 327 | #define COND(bool, val) ((bool) ? (val) : 0) |
| 328 | |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 329 | |
| 330 | #endif /* __MSM_DRV_H__ */ |