Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2013 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | */ |
| 23 | |
| 24 | #include "i915_drv.h" |
| 25 | #include "intel_drv.h" |
| 26 | |
Chris Wilson | 6daccb0 | 2015-01-16 11:34:35 +0200 | [diff] [blame] | 27 | #include <linux/pm_runtime.h> |
| 28 | |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 29 | #define FORCEWAKE_ACK_TIMEOUT_MS 2 |
| 30 | |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 31 | #define __raw_i915_read8(dev_priv__, reg__) readb((dev_priv__)->regs + (reg__)) |
| 32 | #define __raw_i915_write8(dev_priv__, reg__, val__) writeb(val__, (dev_priv__)->regs + (reg__)) |
| 33 | |
| 34 | #define __raw_i915_read16(dev_priv__, reg__) readw((dev_priv__)->regs + (reg__)) |
| 35 | #define __raw_i915_write16(dev_priv__, reg__, val__) writew(val__, (dev_priv__)->regs + (reg__)) |
| 36 | |
| 37 | #define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__)) |
| 38 | #define __raw_i915_write32(dev_priv__, reg__, val__) writel(val__, (dev_priv__)->regs + (reg__)) |
| 39 | |
| 40 | #define __raw_i915_read64(dev_priv__, reg__) readq((dev_priv__)->regs + (reg__)) |
| 41 | #define __raw_i915_write64(dev_priv__, reg__, val__) writeq(val__, (dev_priv__)->regs + (reg__)) |
| 42 | |
| 43 | #define __raw_posting_read(dev_priv__, reg__) (void)__raw_i915_read32(dev_priv__, reg__) |
| 44 | |
Paulo Zanoni | b2ec142 | 2014-02-21 13:52:25 -0300 | [diff] [blame] | 45 | static void |
| 46 | assert_device_not_suspended(struct drm_i915_private *dev_priv) |
| 47 | { |
Chris Wilson | 2b38705 | 2014-11-24 08:03:12 +0000 | [diff] [blame] | 48 | WARN_ONCE(HAS_RUNTIME_PM(dev_priv->dev) && dev_priv->pm.suspended, |
| 49 | "Device suspended\n"); |
Paulo Zanoni | b2ec142 | 2014-02-21 13:52:25 -0300 | [diff] [blame] | 50 | } |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 51 | |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 52 | static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv) |
| 53 | { |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 54 | /* w/a for a sporadic read returning 0 by waiting for the GT |
| 55 | * thread to wake up. |
| 56 | */ |
Ville Syrjälä | eb88bd1 | 2014-11-13 22:12:52 +0200 | [diff] [blame] | 57 | if (wait_for_atomic_us((__raw_i915_read32(dev_priv, GEN6_GT_THREAD_STATUS_REG) & |
| 58 | GEN6_GT_THREAD_STATUS_CORE_MASK) == 0, 500)) |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 59 | DRM_ERROR("GT thread status wait timed out\n"); |
| 60 | } |
| 61 | |
| 62 | static void __gen6_gt_force_wake_reset(struct drm_i915_private *dev_priv) |
| 63 | { |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 64 | __raw_i915_write32(dev_priv, FORCEWAKE, 0); |
| 65 | /* something from same cacheline, but !FORCEWAKE */ |
| 66 | __raw_posting_read(dev_priv, ECOBUS); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 67 | } |
| 68 | |
Deepak S | c8d9a59 | 2013-11-23 14:55:42 +0530 | [diff] [blame] | 69 | static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv, |
| 70 | int fw_engine) |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 71 | { |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 72 | if (wait_for_atomic((__raw_i915_read32(dev_priv, FORCEWAKE_ACK) & 1) == 0, |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 73 | FORCEWAKE_ACK_TIMEOUT_MS)) |
| 74 | DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n"); |
| 75 | |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 76 | __raw_i915_write32(dev_priv, FORCEWAKE, 1); |
| 77 | /* something from same cacheline, but !FORCEWAKE */ |
| 78 | __raw_posting_read(dev_priv, ECOBUS); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 79 | |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 80 | if (wait_for_atomic((__raw_i915_read32(dev_priv, FORCEWAKE_ACK) & 1), |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 81 | FORCEWAKE_ACK_TIMEOUT_MS)) |
| 82 | DRM_ERROR("Timed out waiting for forcewake to ack request.\n"); |
| 83 | |
| 84 | /* WaRsForcewakeWaitTC0:snb */ |
| 85 | __gen6_gt_wait_for_thread_c0(dev_priv); |
| 86 | } |
| 87 | |
Mika Kuoppala | 6a68735 | 2014-02-21 18:47:36 +0200 | [diff] [blame] | 88 | static void __gen7_gt_force_wake_mt_reset(struct drm_i915_private *dev_priv) |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 89 | { |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 90 | __raw_i915_write32(dev_priv, FORCEWAKE_MT, _MASKED_BIT_DISABLE(0xffff)); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 91 | /* something from same cacheline, but !FORCEWAKE_MT */ |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 92 | __raw_posting_read(dev_priv, ECOBUS); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 93 | } |
| 94 | |
Mika Kuoppala | 6a68735 | 2014-02-21 18:47:36 +0200 | [diff] [blame] | 95 | static void __gen7_gt_force_wake_mt_get(struct drm_i915_private *dev_priv, |
Deepak S | c8d9a59 | 2013-11-23 14:55:42 +0530 | [diff] [blame] | 96 | int fw_engine) |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 97 | { |
| 98 | u32 forcewake_ack; |
| 99 | |
Ville Syrjälä | f98cd09 | 2014-09-03 14:09:51 +0300 | [diff] [blame] | 100 | if (IS_HASWELL(dev_priv->dev) || IS_BROADWELL(dev_priv->dev)) |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 101 | forcewake_ack = FORCEWAKE_ACK_HSW; |
| 102 | else |
| 103 | forcewake_ack = FORCEWAKE_MT_ACK; |
| 104 | |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 105 | if (wait_for_atomic((__raw_i915_read32(dev_priv, forcewake_ack) & FORCEWAKE_KERNEL) == 0, |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 106 | FORCEWAKE_ACK_TIMEOUT_MS)) |
| 107 | DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n"); |
| 108 | |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 109 | __raw_i915_write32(dev_priv, FORCEWAKE_MT, |
| 110 | _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL)); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 111 | /* something from same cacheline, but !FORCEWAKE_MT */ |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 112 | __raw_posting_read(dev_priv, ECOBUS); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 113 | |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 114 | if (wait_for_atomic((__raw_i915_read32(dev_priv, forcewake_ack) & FORCEWAKE_KERNEL), |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 115 | FORCEWAKE_ACK_TIMEOUT_MS)) |
| 116 | DRM_ERROR("Timed out waiting for forcewake to ack request.\n"); |
| 117 | |
| 118 | /* WaRsForcewakeWaitTC0:ivb,hsw */ |
Mika Kuoppala | c549f73 | 2014-11-10 04:52:50 -0800 | [diff] [blame] | 119 | __gen6_gt_wait_for_thread_c0(dev_priv); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 120 | } |
| 121 | |
| 122 | static void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv) |
| 123 | { |
| 124 | u32 gtfifodbg; |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 125 | |
| 126 | gtfifodbg = __raw_i915_read32(dev_priv, GTFIFODBG); |
Ville Syrjälä | 90f256b | 2013-11-14 01:59:59 +0200 | [diff] [blame] | 127 | if (WARN(gtfifodbg, "GT wake FIFO error 0x%x\n", gtfifodbg)) |
| 128 | __raw_i915_write32(dev_priv, GTFIFODBG, gtfifodbg); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 129 | } |
| 130 | |
Deepak S | c8d9a59 | 2013-11-23 14:55:42 +0530 | [diff] [blame] | 131 | static void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv, |
| 132 | int fw_engine) |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 133 | { |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 134 | __raw_i915_write32(dev_priv, FORCEWAKE, 0); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 135 | /* something from same cacheline, but !FORCEWAKE */ |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 136 | __raw_posting_read(dev_priv, ECOBUS); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 137 | gen6_gt_check_fifodbg(dev_priv); |
| 138 | } |
| 139 | |
Mika Kuoppala | 6a68735 | 2014-02-21 18:47:36 +0200 | [diff] [blame] | 140 | static void __gen7_gt_force_wake_mt_put(struct drm_i915_private *dev_priv, |
Deepak S | c8d9a59 | 2013-11-23 14:55:42 +0530 | [diff] [blame] | 141 | int fw_engine) |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 142 | { |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 143 | __raw_i915_write32(dev_priv, FORCEWAKE_MT, |
| 144 | _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL)); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 145 | /* something from same cacheline, but !FORCEWAKE_MT */ |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 146 | __raw_posting_read(dev_priv, ECOBUS); |
Mika Kuoppala | 6a68735 | 2014-02-21 18:47:36 +0200 | [diff] [blame] | 147 | |
| 148 | if (IS_GEN7(dev_priv->dev)) |
| 149 | gen6_gt_check_fifodbg(dev_priv); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 150 | } |
| 151 | |
| 152 | static int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv) |
| 153 | { |
| 154 | int ret = 0; |
| 155 | |
Deepak S | 5135d64 | 2013-11-29 15:56:30 +0530 | [diff] [blame] | 156 | /* On VLV, FIFO will be shared by both SW and HW. |
| 157 | * So, we need to read the FREE_ENTRIES everytime */ |
| 158 | if (IS_VALLEYVIEW(dev_priv->dev)) |
| 159 | dev_priv->uncore.fifo_count = |
| 160 | __raw_i915_read32(dev_priv, GTFIFOCTL) & |
| 161 | GT_FIFO_FREE_ENTRIES_MASK; |
| 162 | |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 163 | if (dev_priv->uncore.fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) { |
| 164 | int loop = 500; |
Ville Syrjälä | 46520e2 | 2013-11-14 02:00:00 +0200 | [diff] [blame] | 165 | u32 fifo = __raw_i915_read32(dev_priv, GTFIFOCTL) & GT_FIFO_FREE_ENTRIES_MASK; |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 166 | while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) { |
| 167 | udelay(10); |
Ville Syrjälä | 46520e2 | 2013-11-14 02:00:00 +0200 | [diff] [blame] | 168 | fifo = __raw_i915_read32(dev_priv, GTFIFOCTL) & GT_FIFO_FREE_ENTRIES_MASK; |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 169 | } |
| 170 | if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES)) |
| 171 | ++ret; |
| 172 | dev_priv->uncore.fifo_count = fifo; |
| 173 | } |
| 174 | dev_priv->uncore.fifo_count--; |
| 175 | |
| 176 | return ret; |
| 177 | } |
| 178 | |
| 179 | static void vlv_force_wake_reset(struct drm_i915_private *dev_priv) |
| 180 | { |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 181 | __raw_i915_write32(dev_priv, FORCEWAKE_VLV, |
| 182 | _MASKED_BIT_DISABLE(0xffff)); |
Jani Nikula | 05adaf1 | 2014-05-09 14:52:34 +0300 | [diff] [blame] | 183 | __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_VLV, |
| 184 | _MASKED_BIT_DISABLE(0xffff)); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 185 | /* something from same cacheline, but !FORCEWAKE_VLV */ |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 186 | __raw_posting_read(dev_priv, FORCEWAKE_ACK_VLV); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 187 | } |
| 188 | |
Deepak S | 940aece | 2013-11-23 14:55:43 +0530 | [diff] [blame] | 189 | static void __vlv_force_wake_get(struct drm_i915_private *dev_priv, |
| 190 | int fw_engine) |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 191 | { |
Deepak S | 940aece | 2013-11-23 14:55:43 +0530 | [diff] [blame] | 192 | /* Check for Render Engine */ |
| 193 | if (FORCEWAKE_RENDER & fw_engine) { |
Mika Kuoppala | 9500986 | 2014-11-05 17:30:52 +0200 | [diff] [blame] | 194 | if (wait_for_atomic((__raw_i915_read32(dev_priv, |
| 195 | FORCEWAKE_ACK_VLV) & |
| 196 | FORCEWAKE_KERNEL) == 0, |
| 197 | FORCEWAKE_ACK_TIMEOUT_MS)) |
| 198 | DRM_ERROR("Timed out: Render forcewake old ack to clear.\n"); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 199 | |
Deepak S | 940aece | 2013-11-23 14:55:43 +0530 | [diff] [blame] | 200 | __raw_i915_write32(dev_priv, FORCEWAKE_VLV, |
| 201 | _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL)); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 202 | |
Deepak S | 940aece | 2013-11-23 14:55:43 +0530 | [diff] [blame] | 203 | if (wait_for_atomic((__raw_i915_read32(dev_priv, |
| 204 | FORCEWAKE_ACK_VLV) & |
| 205 | FORCEWAKE_KERNEL), |
| 206 | FORCEWAKE_ACK_TIMEOUT_MS)) |
| 207 | DRM_ERROR("Timed out: waiting for Render to ack.\n"); |
| 208 | } |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 209 | |
Deepak S | 940aece | 2013-11-23 14:55:43 +0530 | [diff] [blame] | 210 | /* Check for Media Engine */ |
| 211 | if (FORCEWAKE_MEDIA & fw_engine) { |
Mika Kuoppala | 9500986 | 2014-11-05 17:30:52 +0200 | [diff] [blame] | 212 | if (wait_for_atomic((__raw_i915_read32(dev_priv, |
| 213 | FORCEWAKE_ACK_MEDIA_VLV) & |
| 214 | FORCEWAKE_KERNEL) == 0, |
| 215 | FORCEWAKE_ACK_TIMEOUT_MS)) |
| 216 | DRM_ERROR("Timed out: Media forcewake old ack to clear.\n"); |
Deepak S | 940aece | 2013-11-23 14:55:43 +0530 | [diff] [blame] | 217 | |
| 218 | __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_VLV, |
| 219 | _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL)); |
| 220 | |
| 221 | if (wait_for_atomic((__raw_i915_read32(dev_priv, |
| 222 | FORCEWAKE_ACK_MEDIA_VLV) & |
| 223 | FORCEWAKE_KERNEL), |
| 224 | FORCEWAKE_ACK_TIMEOUT_MS)) |
| 225 | DRM_ERROR("Timed out: waiting for media to ack.\n"); |
| 226 | } |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 227 | } |
| 228 | |
Deepak S | 940aece | 2013-11-23 14:55:43 +0530 | [diff] [blame] | 229 | static void __vlv_force_wake_put(struct drm_i915_private *dev_priv, |
| 230 | int fw_engine) |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 231 | { |
Deepak S | 940aece | 2013-11-23 14:55:43 +0530 | [diff] [blame] | 232 | |
| 233 | /* Check for Render Engine */ |
| 234 | if (FORCEWAKE_RENDER & fw_engine) |
| 235 | __raw_i915_write32(dev_priv, FORCEWAKE_VLV, |
| 236 | _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL)); |
| 237 | |
| 238 | |
| 239 | /* Check for Media Engine */ |
| 240 | if (FORCEWAKE_MEDIA & fw_engine) |
| 241 | __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_VLV, |
| 242 | _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL)); |
| 243 | |
Ville Syrjälä | ab53c26 | 2014-05-23 21:00:19 +0530 | [diff] [blame] | 244 | /* something from same cacheline, but !FORCEWAKE_VLV */ |
| 245 | __raw_posting_read(dev_priv, FORCEWAKE_ACK_VLV); |
| 246 | if (!IS_CHERRYVIEW(dev_priv->dev)) |
| 247 | gen6_gt_check_fifodbg(dev_priv); |
Deepak S | 940aece | 2013-11-23 14:55:43 +0530 | [diff] [blame] | 248 | } |
| 249 | |
Damien Lespiau | b88b23d | 2014-03-28 16:54:25 +0000 | [diff] [blame] | 250 | static void vlv_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine) |
Deepak S | 940aece | 2013-11-23 14:55:43 +0530 | [diff] [blame] | 251 | { |
Ville Syrjälä | 6fe7286 | 2014-02-27 22:07:21 +0200 | [diff] [blame] | 252 | if (fw_engine & FORCEWAKE_RENDER && |
| 253 | dev_priv->uncore.fw_rendercount++ != 0) |
| 254 | fw_engine &= ~FORCEWAKE_RENDER; |
| 255 | if (fw_engine & FORCEWAKE_MEDIA && |
| 256 | dev_priv->uncore.fw_mediacount++ != 0) |
| 257 | fw_engine &= ~FORCEWAKE_MEDIA; |
| 258 | |
| 259 | if (fw_engine) |
| 260 | dev_priv->uncore.funcs.force_wake_get(dev_priv, fw_engine); |
Deepak S | 940aece | 2013-11-23 14:55:43 +0530 | [diff] [blame] | 261 | } |
| 262 | |
Damien Lespiau | b88b23d | 2014-03-28 16:54:25 +0000 | [diff] [blame] | 263 | static void vlv_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine) |
Deepak S | 940aece | 2013-11-23 14:55:43 +0530 | [diff] [blame] | 264 | { |
Daniel Vetter | 3123fca | 2014-03-15 20:20:29 +0100 | [diff] [blame] | 265 | if (fw_engine & FORCEWAKE_RENDER) { |
| 266 | WARN_ON(!dev_priv->uncore.fw_rendercount); |
| 267 | if (--dev_priv->uncore.fw_rendercount != 0) |
| 268 | fw_engine &= ~FORCEWAKE_RENDER; |
| 269 | } |
| 270 | |
| 271 | if (fw_engine & FORCEWAKE_MEDIA) { |
| 272 | WARN_ON(!dev_priv->uncore.fw_mediacount); |
| 273 | if (--dev_priv->uncore.fw_mediacount != 0) |
| 274 | fw_engine &= ~FORCEWAKE_MEDIA; |
| 275 | } |
Deepak S | 940aece | 2013-11-23 14:55:43 +0530 | [diff] [blame] | 276 | |
Ville Syrjälä | 6fe7286 | 2014-02-27 22:07:21 +0200 | [diff] [blame] | 277 | if (fw_engine) |
| 278 | dev_priv->uncore.funcs.force_wake_put(dev_priv, fw_engine); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 279 | } |
| 280 | |
Zhe Wang | 38cff0b | 2014-11-04 17:07:04 +0000 | [diff] [blame] | 281 | static void __gen9_gt_force_wake_mt_reset(struct drm_i915_private *dev_priv) |
| 282 | { |
| 283 | __raw_i915_write32(dev_priv, FORCEWAKE_RENDER_GEN9, |
| 284 | _MASKED_BIT_DISABLE(0xffff)); |
| 285 | |
| 286 | __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_GEN9, |
| 287 | _MASKED_BIT_DISABLE(0xffff)); |
| 288 | |
| 289 | __raw_i915_write32(dev_priv, FORCEWAKE_BLITTER_GEN9, |
| 290 | _MASKED_BIT_DISABLE(0xffff)); |
| 291 | } |
| 292 | |
| 293 | static void |
| 294 | __gen9_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine) |
| 295 | { |
| 296 | /* Check for Render Engine */ |
| 297 | if (FORCEWAKE_RENDER & fw_engine) { |
| 298 | if (wait_for_atomic((__raw_i915_read32(dev_priv, |
| 299 | FORCEWAKE_ACK_RENDER_GEN9) & |
| 300 | FORCEWAKE_KERNEL) == 0, |
| 301 | FORCEWAKE_ACK_TIMEOUT_MS)) |
| 302 | DRM_ERROR("Timed out: Render forcewake old ack to clear.\n"); |
| 303 | |
| 304 | __raw_i915_write32(dev_priv, FORCEWAKE_RENDER_GEN9, |
| 305 | _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL)); |
| 306 | |
| 307 | if (wait_for_atomic((__raw_i915_read32(dev_priv, |
| 308 | FORCEWAKE_ACK_RENDER_GEN9) & |
| 309 | FORCEWAKE_KERNEL), |
| 310 | FORCEWAKE_ACK_TIMEOUT_MS)) |
| 311 | DRM_ERROR("Timed out: waiting for Render to ack.\n"); |
| 312 | } |
| 313 | |
| 314 | /* Check for Media Engine */ |
| 315 | if (FORCEWAKE_MEDIA & fw_engine) { |
| 316 | if (wait_for_atomic((__raw_i915_read32(dev_priv, |
| 317 | FORCEWAKE_ACK_MEDIA_GEN9) & |
| 318 | FORCEWAKE_KERNEL) == 0, |
| 319 | FORCEWAKE_ACK_TIMEOUT_MS)) |
| 320 | DRM_ERROR("Timed out: Media forcewake old ack to clear.\n"); |
| 321 | |
| 322 | __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_GEN9, |
| 323 | _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL)); |
| 324 | |
| 325 | if (wait_for_atomic((__raw_i915_read32(dev_priv, |
| 326 | FORCEWAKE_ACK_MEDIA_GEN9) & |
| 327 | FORCEWAKE_KERNEL), |
| 328 | FORCEWAKE_ACK_TIMEOUT_MS)) |
| 329 | DRM_ERROR("Timed out: waiting for Media to ack.\n"); |
| 330 | } |
| 331 | |
| 332 | /* Check for Blitter Engine */ |
| 333 | if (FORCEWAKE_BLITTER & fw_engine) { |
| 334 | if (wait_for_atomic((__raw_i915_read32(dev_priv, |
| 335 | FORCEWAKE_ACK_BLITTER_GEN9) & |
| 336 | FORCEWAKE_KERNEL) == 0, |
| 337 | FORCEWAKE_ACK_TIMEOUT_MS)) |
| 338 | DRM_ERROR("Timed out: Blitter forcewake old ack to clear.\n"); |
| 339 | |
| 340 | __raw_i915_write32(dev_priv, FORCEWAKE_BLITTER_GEN9, |
| 341 | _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL)); |
| 342 | |
| 343 | if (wait_for_atomic((__raw_i915_read32(dev_priv, |
| 344 | FORCEWAKE_ACK_BLITTER_GEN9) & |
| 345 | FORCEWAKE_KERNEL), |
| 346 | FORCEWAKE_ACK_TIMEOUT_MS)) |
| 347 | DRM_ERROR("Timed out: waiting for Blitter to ack.\n"); |
| 348 | } |
| 349 | } |
| 350 | |
| 351 | static void |
| 352 | __gen9_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine) |
| 353 | { |
| 354 | /* Check for Render Engine */ |
| 355 | if (FORCEWAKE_RENDER & fw_engine) |
| 356 | __raw_i915_write32(dev_priv, FORCEWAKE_RENDER_GEN9, |
| 357 | _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL)); |
| 358 | |
| 359 | /* Check for Media Engine */ |
| 360 | if (FORCEWAKE_MEDIA & fw_engine) |
| 361 | __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_GEN9, |
| 362 | _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL)); |
| 363 | |
| 364 | /* Check for Blitter Engine */ |
| 365 | if (FORCEWAKE_BLITTER & fw_engine) |
| 366 | __raw_i915_write32(dev_priv, FORCEWAKE_BLITTER_GEN9, |
| 367 | _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL)); |
| 368 | } |
| 369 | |
| 370 | static void |
| 371 | gen9_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine) |
| 372 | { |
Zhe Wang | 38cff0b | 2014-11-04 17:07:04 +0000 | [diff] [blame] | 373 | if (FORCEWAKE_RENDER & fw_engine) { |
| 374 | if (dev_priv->uncore.fw_rendercount++ == 0) |
| 375 | dev_priv->uncore.funcs.force_wake_get(dev_priv, |
| 376 | FORCEWAKE_RENDER); |
| 377 | } |
| 378 | |
| 379 | if (FORCEWAKE_MEDIA & fw_engine) { |
| 380 | if (dev_priv->uncore.fw_mediacount++ == 0) |
| 381 | dev_priv->uncore.funcs.force_wake_get(dev_priv, |
| 382 | FORCEWAKE_MEDIA); |
| 383 | } |
| 384 | |
| 385 | if (FORCEWAKE_BLITTER & fw_engine) { |
| 386 | if (dev_priv->uncore.fw_blittercount++ == 0) |
| 387 | dev_priv->uncore.funcs.force_wake_get(dev_priv, |
| 388 | FORCEWAKE_BLITTER); |
| 389 | } |
Zhe Wang | 38cff0b | 2014-11-04 17:07:04 +0000 | [diff] [blame] | 390 | } |
| 391 | |
| 392 | static void |
| 393 | gen9_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine) |
| 394 | { |
Zhe Wang | 38cff0b | 2014-11-04 17:07:04 +0000 | [diff] [blame] | 395 | if (FORCEWAKE_RENDER & fw_engine) { |
| 396 | WARN_ON(dev_priv->uncore.fw_rendercount == 0); |
| 397 | if (--dev_priv->uncore.fw_rendercount == 0) |
| 398 | dev_priv->uncore.funcs.force_wake_put(dev_priv, |
| 399 | FORCEWAKE_RENDER); |
| 400 | } |
| 401 | |
| 402 | if (FORCEWAKE_MEDIA & fw_engine) { |
| 403 | WARN_ON(dev_priv->uncore.fw_mediacount == 0); |
| 404 | if (--dev_priv->uncore.fw_mediacount == 0) |
| 405 | dev_priv->uncore.funcs.force_wake_put(dev_priv, |
| 406 | FORCEWAKE_MEDIA); |
| 407 | } |
| 408 | |
| 409 | if (FORCEWAKE_BLITTER & fw_engine) { |
| 410 | WARN_ON(dev_priv->uncore.fw_blittercount == 0); |
| 411 | if (--dev_priv->uncore.fw_blittercount == 0) |
| 412 | dev_priv->uncore.funcs.force_wake_put(dev_priv, |
| 413 | FORCEWAKE_BLITTER); |
| 414 | } |
Zhe Wang | 38cff0b | 2014-11-04 17:07:04 +0000 | [diff] [blame] | 415 | } |
| 416 | |
Chris Wilson | 8232644 | 2014-03-05 12:00:39 +0000 | [diff] [blame] | 417 | static void gen6_force_wake_timer(unsigned long arg) |
Chris Wilson | aec347a | 2013-08-26 13:46:09 +0100 | [diff] [blame] | 418 | { |
Chris Wilson | 8232644 | 2014-03-05 12:00:39 +0000 | [diff] [blame] | 419 | struct drm_i915_private *dev_priv = (void *)arg; |
Chris Wilson | aec347a | 2013-08-26 13:46:09 +0100 | [diff] [blame] | 420 | unsigned long irqflags; |
| 421 | |
Paulo Zanoni | b2ec142 | 2014-02-21 13:52:25 -0300 | [diff] [blame] | 422 | assert_device_not_suspended(dev_priv); |
| 423 | |
Chris Wilson | aec347a | 2013-08-26 13:46:09 +0100 | [diff] [blame] | 424 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); |
Daniel Vetter | 3123fca | 2014-03-15 20:20:29 +0100 | [diff] [blame] | 425 | WARN_ON(!dev_priv->uncore.forcewake_count); |
| 426 | |
Chris Wilson | aec347a | 2013-08-26 13:46:09 +0100 | [diff] [blame] | 427 | if (--dev_priv->uncore.forcewake_count == 0) |
Deepak S | c8d9a59 | 2013-11-23 14:55:42 +0530 | [diff] [blame] | 428 | dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL); |
Chris Wilson | aec347a | 2013-08-26 13:46:09 +0100 | [diff] [blame] | 429 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
| 430 | } |
| 431 | |
Jesse Barnes | 156c7ca | 2014-06-12 08:35:45 -0700 | [diff] [blame] | 432 | void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore) |
Daniel Vetter | ef46e0d | 2013-11-16 16:00:09 +0100 | [diff] [blame] | 433 | { |
| 434 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 0294ae7 | 2014-03-13 12:00:29 +0000 | [diff] [blame] | 435 | unsigned long irqflags; |
| 436 | |
Imre Deak | 9e31c2a5 | 2014-06-06 14:04:37 +0300 | [diff] [blame] | 437 | if (del_timer_sync(&dev_priv->uncore.force_wake_timer)) |
| 438 | gen6_force_wake_timer((unsigned long)dev_priv); |
Chris Wilson | 0294ae7 | 2014-03-13 12:00:29 +0000 | [diff] [blame] | 439 | |
| 440 | /* Hold uncore.lock across reset to prevent any register access |
| 441 | * with forcewake not set correctly |
| 442 | */ |
| 443 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); |
Daniel Vetter | ef46e0d | 2013-11-16 16:00:09 +0100 | [diff] [blame] | 444 | |
Mika Kuoppala | 0a089e3 | 2014-02-21 17:32:00 +0200 | [diff] [blame] | 445 | if (IS_VALLEYVIEW(dev)) |
Daniel Vetter | ef46e0d | 2013-11-16 16:00:09 +0100 | [diff] [blame] | 446 | vlv_force_wake_reset(dev_priv); |
Mika Kuoppala | 0a089e3 | 2014-02-21 17:32:00 +0200 | [diff] [blame] | 447 | else if (IS_GEN6(dev) || IS_GEN7(dev)) |
Daniel Vetter | ef46e0d | 2013-11-16 16:00:09 +0100 | [diff] [blame] | 448 | __gen6_gt_force_wake_reset(dev_priv); |
Mika Kuoppala | 0a089e3 | 2014-02-21 17:32:00 +0200 | [diff] [blame] | 449 | |
Ville Syrjälä | f98cd09 | 2014-09-03 14:09:51 +0300 | [diff] [blame] | 450 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev)) |
Mika Kuoppala | 6a68735 | 2014-02-21 18:47:36 +0200 | [diff] [blame] | 451 | __gen7_gt_force_wake_mt_reset(dev_priv); |
Chris Wilson | 0294ae7 | 2014-03-13 12:00:29 +0000 | [diff] [blame] | 452 | |
Zhe Wang | 38cff0b | 2014-11-04 17:07:04 +0000 | [diff] [blame] | 453 | if (IS_GEN9(dev)) |
| 454 | __gen9_gt_force_wake_mt_reset(dev_priv); |
| 455 | |
Chris Wilson | 0294ae7 | 2014-03-13 12:00:29 +0000 | [diff] [blame] | 456 | if (restore) { /* If reset with a user forcewake, try to restore */ |
| 457 | unsigned fw = 0; |
| 458 | |
| 459 | if (IS_VALLEYVIEW(dev)) { |
| 460 | if (dev_priv->uncore.fw_rendercount) |
| 461 | fw |= FORCEWAKE_RENDER; |
| 462 | |
| 463 | if (dev_priv->uncore.fw_mediacount) |
| 464 | fw |= FORCEWAKE_MEDIA; |
Zhe Wang | 38cff0b | 2014-11-04 17:07:04 +0000 | [diff] [blame] | 465 | } else if (IS_GEN9(dev)) { |
| 466 | if (dev_priv->uncore.fw_rendercount) |
| 467 | fw |= FORCEWAKE_RENDER; |
| 468 | |
| 469 | if (dev_priv->uncore.fw_mediacount) |
| 470 | fw |= FORCEWAKE_MEDIA; |
| 471 | |
| 472 | if (dev_priv->uncore.fw_blittercount) |
| 473 | fw |= FORCEWAKE_BLITTER; |
Chris Wilson | 0294ae7 | 2014-03-13 12:00:29 +0000 | [diff] [blame] | 474 | } else { |
| 475 | if (dev_priv->uncore.forcewake_count) |
| 476 | fw = FORCEWAKE_ALL; |
| 477 | } |
| 478 | |
| 479 | if (fw) |
| 480 | dev_priv->uncore.funcs.force_wake_get(dev_priv, fw); |
| 481 | |
| 482 | if (IS_GEN6(dev) || IS_GEN7(dev)) |
| 483 | dev_priv->uncore.fifo_count = |
| 484 | __raw_i915_read32(dev_priv, GTFIFOCTL) & |
| 485 | GT_FIFO_FREE_ENTRIES_MASK; |
Chris Wilson | 0294ae7 | 2014-03-13 12:00:29 +0000 | [diff] [blame] | 486 | } |
| 487 | |
| 488 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
Daniel Vetter | ef46e0d | 2013-11-16 16:00:09 +0100 | [diff] [blame] | 489 | } |
| 490 | |
Imre Deak | ed49388 | 2014-10-23 19:23:21 +0300 | [diff] [blame] | 491 | static void __intel_uncore_early_sanitize(struct drm_device *dev, |
| 492 | bool restore_forcewake) |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 493 | { |
| 494 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 495 | |
| 496 | if (HAS_FPGA_DBG_UNCLAIMED(dev)) |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 497 | __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM); |
Ben Widawsky | 18ce399 | 2013-10-04 21:22:50 -0700 | [diff] [blame] | 498 | |
Ben Widawsky | 1d2866b | 2014-04-18 18:04:28 -0300 | [diff] [blame] | 499 | if ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && |
Ben Widawsky | 18ce399 | 2013-10-04 21:22:50 -0700 | [diff] [blame] | 500 | (__raw_i915_read32(dev_priv, HSW_EDRAM_PRESENT) == 1)) { |
| 501 | /* The docs do not explain exactly how the calculation can be |
| 502 | * made. It is somewhat guessable, but for now, it's always |
| 503 | * 128MB. |
| 504 | * NB: We can't write IDICR yet because we do not have gt funcs |
| 505 | * set up */ |
| 506 | dev_priv->ellc_size = 128; |
| 507 | DRM_INFO("Found %zuMB of eLLC\n", dev_priv->ellc_size); |
| 508 | } |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 509 | |
Ville Syrjälä | 9705887 | 2013-12-03 11:30:09 +0200 | [diff] [blame] | 510 | /* clear out old GT FIFO errors */ |
| 511 | if (IS_GEN6(dev) || IS_GEN7(dev)) |
| 512 | __raw_i915_write32(dev_priv, GTFIFODBG, |
| 513 | __raw_i915_read32(dev_priv, GTFIFODBG)); |
| 514 | |
Imre Deak | 1001860 | 2014-06-06 12:59:39 +0300 | [diff] [blame] | 515 | intel_uncore_forcewake_reset(dev, restore_forcewake); |
Mika Kuoppala | 521198a | 2013-08-23 16:52:30 +0300 | [diff] [blame] | 516 | } |
| 517 | |
Imre Deak | ed49388 | 2014-10-23 19:23:21 +0300 | [diff] [blame] | 518 | void intel_uncore_early_sanitize(struct drm_device *dev, bool restore_forcewake) |
| 519 | { |
| 520 | __intel_uncore_early_sanitize(dev, restore_forcewake); |
| 521 | i915_check_and_clear_faults(dev); |
| 522 | } |
| 523 | |
Mika Kuoppala | 521198a | 2013-08-23 16:52:30 +0300 | [diff] [blame] | 524 | void intel_uncore_sanitize(struct drm_device *dev) |
| 525 | { |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 526 | /* BIOS often leaves RC6 enabled, but disable it for hw init */ |
| 527 | intel_disable_gt_powersave(dev); |
| 528 | } |
| 529 | |
| 530 | /* |
| 531 | * Generally this is called implicitly by the register read function. However, |
| 532 | * if some sequence requires the GT to not power down then this function should |
| 533 | * be called at the beginning of the sequence followed by a call to |
| 534 | * gen6_gt_force_wake_put() at the end of the sequence. |
| 535 | */ |
Deepak S | c8d9a59 | 2013-11-23 14:55:42 +0530 | [diff] [blame] | 536 | void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine) |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 537 | { |
| 538 | unsigned long irqflags; |
| 539 | |
Ben Widawsky | ab484f8 | 2013-10-05 17:57:11 -0700 | [diff] [blame] | 540 | if (!dev_priv->uncore.funcs.force_wake_get) |
| 541 | return; |
| 542 | |
Chris Wilson | 6daccb0 | 2015-01-16 11:34:35 +0200 | [diff] [blame] | 543 | WARN_ON(dev_priv->pm.suspended); |
Deepak S | 940aece | 2013-11-23 14:55:43 +0530 | [diff] [blame] | 544 | |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 545 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); |
Chris Wilson | 6daccb0 | 2015-01-16 11:34:35 +0200 | [diff] [blame] | 546 | |
| 547 | if (IS_GEN9(dev_priv->dev)) { |
| 548 | gen9_force_wake_get(dev_priv, fw_engine); |
| 549 | } else if (IS_VALLEYVIEW(dev_priv->dev)) { |
| 550 | vlv_force_wake_get(dev_priv, fw_engine); |
| 551 | } else { |
| 552 | if (dev_priv->uncore.forcewake_count++ == 0) |
| 553 | dev_priv->uncore.funcs.force_wake_get(dev_priv, |
| 554 | FORCEWAKE_ALL); |
| 555 | } |
| 556 | |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 557 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
| 558 | } |
| 559 | |
| 560 | /* |
| 561 | * see gen6_gt_force_wake_get() |
| 562 | */ |
Deepak S | c8d9a59 | 2013-11-23 14:55:42 +0530 | [diff] [blame] | 563 | void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine) |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 564 | { |
| 565 | unsigned long irqflags; |
| 566 | |
Ben Widawsky | ab484f8 | 2013-10-05 17:57:11 -0700 | [diff] [blame] | 567 | if (!dev_priv->uncore.funcs.force_wake_put) |
| 568 | return; |
| 569 | |
Chris Wilson | 6daccb0 | 2015-01-16 11:34:35 +0200 | [diff] [blame] | 570 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); |
| 571 | |
Zhe Wang | 38cff0b | 2014-11-04 17:07:04 +0000 | [diff] [blame] | 572 | if (IS_GEN9(dev_priv->dev)) { |
| 573 | gen9_force_wake_put(dev_priv, fw_engine); |
Chris Wilson | 6daccb0 | 2015-01-16 11:34:35 +0200 | [diff] [blame] | 574 | } else if (IS_VALLEYVIEW(dev_priv->dev)) { |
Paulo Zanoni | 6d88064 | 2014-02-21 17:58:29 -0300 | [diff] [blame] | 575 | vlv_force_wake_put(dev_priv, fw_engine); |
Chris Wilson | 6daccb0 | 2015-01-16 11:34:35 +0200 | [diff] [blame] | 576 | } else { |
| 577 | WARN_ON(!dev_priv->uncore.forcewake_count); |
| 578 | if (--dev_priv->uncore.forcewake_count == 0) { |
| 579 | dev_priv->uncore.forcewake_count++; |
| 580 | mod_timer_pinned(&dev_priv->uncore.force_wake_timer, |
| 581 | jiffies + 1); |
| 582 | } |
Chris Wilson | aec347a | 2013-08-26 13:46:09 +0100 | [diff] [blame] | 583 | } |
Chris Wilson | dc9fb09 | 2015-01-16 11:34:34 +0200 | [diff] [blame] | 584 | |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 585 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
| 586 | } |
| 587 | |
Paulo Zanoni | e998c40 | 2014-02-21 13:52:26 -0300 | [diff] [blame] | 588 | void assert_force_wake_inactive(struct drm_i915_private *dev_priv) |
| 589 | { |
| 590 | if (!dev_priv->uncore.funcs.force_wake_get) |
| 591 | return; |
| 592 | |
| 593 | WARN_ON(dev_priv->uncore.forcewake_count > 0); |
| 594 | } |
| 595 | |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 596 | /* We give fast paths for the really cool registers */ |
| 597 | #define NEEDS_FORCE_WAKE(dev_priv, reg) \ |
Ben Widawsky | ab484f8 | 2013-10-05 17:57:11 -0700 | [diff] [blame] | 598 | ((reg) < 0x40000 && (reg) != FORCEWAKE) |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 599 | |
Deepak S | 1938e59 | 2014-05-23 21:00:16 +0530 | [diff] [blame] | 600 | #define REG_RANGE(reg, start, end) ((reg) >= (start) && (reg) < (end)) |
Damien Lespiau | 38fb6a4 | 2014-03-28 16:54:26 +0000 | [diff] [blame] | 601 | |
Deepak S | 1938e59 | 2014-05-23 21:00:16 +0530 | [diff] [blame] | 602 | #define FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg) \ |
| 603 | (REG_RANGE((reg), 0x2000, 0x4000) || \ |
| 604 | REG_RANGE((reg), 0x5000, 0x8000) || \ |
| 605 | REG_RANGE((reg), 0xB000, 0x12000) || \ |
| 606 | REG_RANGE((reg), 0x2E000, 0x30000)) |
| 607 | |
| 608 | #define FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg) \ |
| 609 | (REG_RANGE((reg), 0x12000, 0x14000) || \ |
| 610 | REG_RANGE((reg), 0x22000, 0x24000) || \ |
| 611 | REG_RANGE((reg), 0x30000, 0x40000)) |
| 612 | |
| 613 | #define FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg) \ |
| 614 | (REG_RANGE((reg), 0x2000, 0x4000) || \ |
Deepak S | db5ff4a | 2014-12-11 21:42:49 +0530 | [diff] [blame] | 615 | REG_RANGE((reg), 0x5200, 0x8000) || \ |
Deepak S | 1938e59 | 2014-05-23 21:00:16 +0530 | [diff] [blame] | 616 | REG_RANGE((reg), 0x8300, 0x8500) || \ |
Deepak S | db5ff4a | 2014-12-11 21:42:49 +0530 | [diff] [blame] | 617 | REG_RANGE((reg), 0xB000, 0xB480) || \ |
Deepak S | 1938e59 | 2014-05-23 21:00:16 +0530 | [diff] [blame] | 618 | REG_RANGE((reg), 0xE000, 0xE800)) |
| 619 | |
| 620 | #define FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg) \ |
| 621 | (REG_RANGE((reg), 0x8800, 0x8900) || \ |
| 622 | REG_RANGE((reg), 0xD000, 0xD800) || \ |
| 623 | REG_RANGE((reg), 0x12000, 0x14000) || \ |
| 624 | REG_RANGE((reg), 0x1A000, 0x1C000) || \ |
| 625 | REG_RANGE((reg), 0x1E800, 0x1EA00) || \ |
Deepak S | db5ff4a | 2014-12-11 21:42:49 +0530 | [diff] [blame] | 626 | REG_RANGE((reg), 0x30000, 0x38000)) |
Deepak S | 1938e59 | 2014-05-23 21:00:16 +0530 | [diff] [blame] | 627 | |
| 628 | #define FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg) \ |
| 629 | (REG_RANGE((reg), 0x4000, 0x5000) || \ |
| 630 | REG_RANGE((reg), 0x8000, 0x8300) || \ |
| 631 | REG_RANGE((reg), 0x8500, 0x8600) || \ |
| 632 | REG_RANGE((reg), 0x9000, 0xB000) || \ |
Deepak S | db5ff4a | 2014-12-11 21:42:49 +0530 | [diff] [blame] | 633 | REG_RANGE((reg), 0xF000, 0x10000)) |
Damien Lespiau | 38fb6a4 | 2014-03-28 16:54:26 +0000 | [diff] [blame] | 634 | |
Zhe Wang | 4597a88 | 2014-11-20 13:42:55 +0000 | [diff] [blame] | 635 | #define FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg) \ |
Akash Goel | 8ee558d | 2014-11-25 12:29:00 +0530 | [diff] [blame] | 636 | REG_RANGE((reg), 0xB00, 0x2000) |
Zhe Wang | 4597a88 | 2014-11-20 13:42:55 +0000 | [diff] [blame] | 637 | |
| 638 | #define FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg) \ |
Akash Goel | 8ee558d | 2014-11-25 12:29:00 +0530 | [diff] [blame] | 639 | (REG_RANGE((reg), 0x2000, 0x2700) || \ |
| 640 | REG_RANGE((reg), 0x3000, 0x4000) || \ |
Zhe Wang | 4597a88 | 2014-11-20 13:42:55 +0000 | [diff] [blame] | 641 | REG_RANGE((reg), 0x5200, 0x8000) || \ |
Akash Goel | 8ee558d | 2014-11-25 12:29:00 +0530 | [diff] [blame] | 642 | REG_RANGE((reg), 0x8140, 0x8160) || \ |
Zhe Wang | 4597a88 | 2014-11-20 13:42:55 +0000 | [diff] [blame] | 643 | REG_RANGE((reg), 0x8300, 0x8500) || \ |
| 644 | REG_RANGE((reg), 0x8C00, 0x8D00) || \ |
| 645 | REG_RANGE((reg), 0xB000, 0xB480) || \ |
Akash Goel | 8ee558d | 2014-11-25 12:29:00 +0530 | [diff] [blame] | 646 | REG_RANGE((reg), 0xE000, 0xE900) || \ |
| 647 | REG_RANGE((reg), 0x24400, 0x24800)) |
Zhe Wang | 4597a88 | 2014-11-20 13:42:55 +0000 | [diff] [blame] | 648 | |
| 649 | #define FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg) \ |
Akash Goel | 8ee558d | 2014-11-25 12:29:00 +0530 | [diff] [blame] | 650 | (REG_RANGE((reg), 0x8130, 0x8140) || \ |
| 651 | REG_RANGE((reg), 0x8800, 0x8A00) || \ |
Zhe Wang | 4597a88 | 2014-11-20 13:42:55 +0000 | [diff] [blame] | 652 | REG_RANGE((reg), 0xD000, 0xD800) || \ |
| 653 | REG_RANGE((reg), 0x12000, 0x14000) || \ |
| 654 | REG_RANGE((reg), 0x1A000, 0x1EA00) || \ |
| 655 | REG_RANGE((reg), 0x30000, 0x40000)) |
| 656 | |
| 657 | #define FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg) \ |
| 658 | REG_RANGE((reg), 0x9400, 0x9800) |
| 659 | |
| 660 | #define FORCEWAKE_GEN9_BLITTER_RANGE_OFFSET(reg) \ |
| 661 | ((reg) < 0x40000 &&\ |
| 662 | !FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg) && \ |
| 663 | !FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg) && \ |
| 664 | !FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg) && \ |
| 665 | !FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg)) |
| 666 | |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 667 | static void |
| 668 | ilk_dummy_write(struct drm_i915_private *dev_priv) |
| 669 | { |
| 670 | /* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up |
| 671 | * the chip from rc6 before touching it for real. MI_MODE is masked, |
| 672 | * hence harmless to write 0 into. */ |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 673 | __raw_i915_write32(dev_priv, MI_MODE, 0); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 674 | } |
| 675 | |
| 676 | static void |
Paulo Zanoni | 5978118 | 2014-07-16 17:49:29 -0300 | [diff] [blame] | 677 | hsw_unclaimed_reg_debug(struct drm_i915_private *dev_priv, u32 reg, bool read, |
| 678 | bool before) |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 679 | { |
Paulo Zanoni | 5978118 | 2014-07-16 17:49:29 -0300 | [diff] [blame] | 680 | const char *op = read ? "reading" : "writing to"; |
| 681 | const char *when = before ? "before" : "after"; |
| 682 | |
| 683 | if (!i915.mmio_debug) |
| 684 | return; |
| 685 | |
Ben Widawsky | ab484f8 | 2013-10-05 17:57:11 -0700 | [diff] [blame] | 686 | if (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM) { |
Paulo Zanoni | 5978118 | 2014-07-16 17:49:29 -0300 | [diff] [blame] | 687 | WARN(1, "Unclaimed register detected %s %s register 0x%x\n", |
| 688 | when, op, reg); |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 689 | __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 690 | } |
| 691 | } |
| 692 | |
| 693 | static void |
Paulo Zanoni | 5978118 | 2014-07-16 17:49:29 -0300 | [diff] [blame] | 694 | hsw_unclaimed_reg_detect(struct drm_i915_private *dev_priv) |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 695 | { |
Paulo Zanoni | 5978118 | 2014-07-16 17:49:29 -0300 | [diff] [blame] | 696 | if (i915.mmio_debug) |
| 697 | return; |
| 698 | |
Ben Widawsky | ab484f8 | 2013-10-05 17:57:11 -0700 | [diff] [blame] | 699 | if (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM) { |
Paulo Zanoni | 5978118 | 2014-07-16 17:49:29 -0300 | [diff] [blame] | 700 | DRM_ERROR("Unclaimed register detected. Please use the i915.mmio_debug=1 to debug this problem."); |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 701 | __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 702 | } |
| 703 | } |
| 704 | |
Chris Wilson | 51f6788 | 2015-01-16 11:34:36 +0200 | [diff] [blame^] | 705 | #define GEN2_READ_HEADER(x) \ |
Ben Widawsky | 5d73879 | 2013-10-04 21:24:53 -0700 | [diff] [blame] | 706 | u##x val = 0; \ |
Chris Wilson | 51f6788 | 2015-01-16 11:34:36 +0200 | [diff] [blame^] | 707 | assert_device_not_suspended(dev_priv); |
Ben Widawsky | 5d73879 | 2013-10-04 21:24:53 -0700 | [diff] [blame] | 708 | |
Chris Wilson | 51f6788 | 2015-01-16 11:34:36 +0200 | [diff] [blame^] | 709 | #define GEN2_READ_FOOTER \ |
Ben Widawsky | 5d73879 | 2013-10-04 21:24:53 -0700 | [diff] [blame] | 710 | trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \ |
| 711 | return val |
| 712 | |
Chris Wilson | 51f6788 | 2015-01-16 11:34:36 +0200 | [diff] [blame^] | 713 | #define __gen2_read(x) \ |
Ben Widawsky | 0b27448 | 2013-10-04 21:22:51 -0700 | [diff] [blame] | 714 | static u##x \ |
Chris Wilson | 51f6788 | 2015-01-16 11:34:36 +0200 | [diff] [blame^] | 715 | gen2_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \ |
| 716 | GEN2_READ_HEADER(x); \ |
Ben Widawsky | 3967018 | 2013-10-04 21:22:53 -0700 | [diff] [blame] | 717 | val = __raw_i915_read##x(dev_priv, reg); \ |
Chris Wilson | 51f6788 | 2015-01-16 11:34:36 +0200 | [diff] [blame^] | 718 | GEN2_READ_FOOTER; \ |
Ben Widawsky | 3967018 | 2013-10-04 21:22:53 -0700 | [diff] [blame] | 719 | } |
| 720 | |
| 721 | #define __gen5_read(x) \ |
| 722 | static u##x \ |
| 723 | gen5_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \ |
Chris Wilson | 51f6788 | 2015-01-16 11:34:36 +0200 | [diff] [blame^] | 724 | GEN2_READ_HEADER(x); \ |
Ben Widawsky | 3967018 | 2013-10-04 21:22:53 -0700 | [diff] [blame] | 725 | ilk_dummy_write(dev_priv); \ |
| 726 | val = __raw_i915_read##x(dev_priv, reg); \ |
Chris Wilson | 51f6788 | 2015-01-16 11:34:36 +0200 | [diff] [blame^] | 727 | GEN2_READ_FOOTER; \ |
Ben Widawsky | 3967018 | 2013-10-04 21:22:53 -0700 | [diff] [blame] | 728 | } |
| 729 | |
Chris Wilson | 51f6788 | 2015-01-16 11:34:36 +0200 | [diff] [blame^] | 730 | __gen5_read(8) |
| 731 | __gen5_read(16) |
| 732 | __gen5_read(32) |
| 733 | __gen5_read(64) |
| 734 | __gen2_read(8) |
| 735 | __gen2_read(16) |
| 736 | __gen2_read(32) |
| 737 | __gen2_read(64) |
| 738 | |
| 739 | #undef __gen5_read |
| 740 | #undef __gen2_read |
| 741 | |
| 742 | #undef GEN2_READ_FOOTER |
| 743 | #undef GEN2_READ_HEADER |
| 744 | |
| 745 | #define GEN6_READ_HEADER(x) \ |
| 746 | unsigned long irqflags; \ |
| 747 | u##x val = 0; \ |
| 748 | assert_device_not_suspended(dev_priv); \ |
| 749 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags) |
| 750 | |
| 751 | #define GEN6_READ_FOOTER \ |
| 752 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \ |
| 753 | trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \ |
| 754 | return val |
| 755 | |
Ben Widawsky | 3967018 | 2013-10-04 21:22:53 -0700 | [diff] [blame] | 756 | #define __gen6_read(x) \ |
| 757 | static u##x \ |
| 758 | gen6_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \ |
Chris Wilson | 51f6788 | 2015-01-16 11:34:36 +0200 | [diff] [blame^] | 759 | GEN6_READ_HEADER(x); \ |
Paulo Zanoni | 5978118 | 2014-07-16 17:49:29 -0300 | [diff] [blame] | 760 | hsw_unclaimed_reg_debug(dev_priv, reg, true, true); \ |
Chris Wilson | 8232644 | 2014-03-05 12:00:39 +0000 | [diff] [blame] | 761 | if (dev_priv->uncore.forcewake_count == 0 && \ |
| 762 | NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ |
| 763 | dev_priv->uncore.funcs.force_wake_get(dev_priv, \ |
| 764 | FORCEWAKE_ALL); \ |
Chris Wilson | dc9fb09 | 2015-01-16 11:34:34 +0200 | [diff] [blame] | 765 | dev_priv->uncore.forcewake_count++; \ |
| 766 | mod_timer_pinned(&dev_priv->uncore.force_wake_timer, \ |
| 767 | jiffies + 1); \ |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 768 | } \ |
Chris Wilson | dc9fb09 | 2015-01-16 11:34:34 +0200 | [diff] [blame] | 769 | val = __raw_i915_read##x(dev_priv, reg); \ |
Paulo Zanoni | 5978118 | 2014-07-16 17:49:29 -0300 | [diff] [blame] | 770 | hsw_unclaimed_reg_debug(dev_priv, reg, true, false); \ |
Chris Wilson | 51f6788 | 2015-01-16 11:34:36 +0200 | [diff] [blame^] | 771 | GEN6_READ_FOOTER; \ |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 772 | } |
| 773 | |
Deepak S | 940aece | 2013-11-23 14:55:43 +0530 | [diff] [blame] | 774 | #define __vlv_read(x) \ |
| 775 | static u##x \ |
| 776 | vlv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \ |
| 777 | unsigned fwengine = 0; \ |
Chris Wilson | 51f6788 | 2015-01-16 11:34:36 +0200 | [diff] [blame^] | 778 | GEN6_READ_HEADER(x); \ |
Ville Syrjälä | 6fe7286 | 2014-02-27 22:07:21 +0200 | [diff] [blame] | 779 | if (FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg)) { \ |
| 780 | if (dev_priv->uncore.fw_rendercount == 0) \ |
| 781 | fwengine = FORCEWAKE_RENDER; \ |
| 782 | } else if (FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg)) { \ |
| 783 | if (dev_priv->uncore.fw_mediacount == 0) \ |
| 784 | fwengine = FORCEWAKE_MEDIA; \ |
Deepak S | 940aece | 2013-11-23 14:55:43 +0530 | [diff] [blame] | 785 | } \ |
Ville Syrjälä | 6fe7286 | 2014-02-27 22:07:21 +0200 | [diff] [blame] | 786 | if (fwengine) \ |
| 787 | dev_priv->uncore.funcs.force_wake_get(dev_priv, fwengine); \ |
| 788 | val = __raw_i915_read##x(dev_priv, reg); \ |
| 789 | if (fwengine) \ |
| 790 | dev_priv->uncore.funcs.force_wake_put(dev_priv, fwengine); \ |
Chris Wilson | 51f6788 | 2015-01-16 11:34:36 +0200 | [diff] [blame^] | 791 | GEN6_READ_FOOTER; \ |
Deepak S | 940aece | 2013-11-23 14:55:43 +0530 | [diff] [blame] | 792 | } |
| 793 | |
Deepak S | 1938e59 | 2014-05-23 21:00:16 +0530 | [diff] [blame] | 794 | #define __chv_read(x) \ |
| 795 | static u##x \ |
| 796 | chv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \ |
| 797 | unsigned fwengine = 0; \ |
Chris Wilson | 51f6788 | 2015-01-16 11:34:36 +0200 | [diff] [blame^] | 798 | GEN6_READ_HEADER(x); \ |
Deepak S | 1938e59 | 2014-05-23 21:00:16 +0530 | [diff] [blame] | 799 | if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) { \ |
| 800 | if (dev_priv->uncore.fw_rendercount == 0) \ |
| 801 | fwengine = FORCEWAKE_RENDER; \ |
| 802 | } else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) { \ |
| 803 | if (dev_priv->uncore.fw_mediacount == 0) \ |
| 804 | fwengine = FORCEWAKE_MEDIA; \ |
| 805 | } else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) { \ |
| 806 | if (dev_priv->uncore.fw_rendercount == 0) \ |
| 807 | fwengine |= FORCEWAKE_RENDER; \ |
| 808 | if (dev_priv->uncore.fw_mediacount == 0) \ |
| 809 | fwengine |= FORCEWAKE_MEDIA; \ |
| 810 | } \ |
| 811 | if (fwengine) \ |
| 812 | dev_priv->uncore.funcs.force_wake_get(dev_priv, fwengine); \ |
| 813 | val = __raw_i915_read##x(dev_priv, reg); \ |
| 814 | if (fwengine) \ |
| 815 | dev_priv->uncore.funcs.force_wake_put(dev_priv, fwengine); \ |
Chris Wilson | 51f6788 | 2015-01-16 11:34:36 +0200 | [diff] [blame^] | 816 | GEN6_READ_FOOTER; \ |
Deepak S | 1938e59 | 2014-05-23 21:00:16 +0530 | [diff] [blame] | 817 | } |
Deepak S | 940aece | 2013-11-23 14:55:43 +0530 | [diff] [blame] | 818 | |
Zhe Wang | 4597a88 | 2014-11-20 13:42:55 +0000 | [diff] [blame] | 819 | #define SKL_NEEDS_FORCE_WAKE(dev_priv, reg) \ |
| 820 | ((reg) < 0x40000 && !FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg)) |
| 821 | |
| 822 | #define __gen9_read(x) \ |
| 823 | static u##x \ |
| 824 | gen9_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \ |
Chris Wilson | 51f6788 | 2015-01-16 11:34:36 +0200 | [diff] [blame^] | 825 | GEN6_READ_HEADER(x); \ |
Zhe Wang | 4597a88 | 2014-11-20 13:42:55 +0000 | [diff] [blame] | 826 | if (!SKL_NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ |
| 827 | val = __raw_i915_read##x(dev_priv, reg); \ |
| 828 | } else { \ |
| 829 | unsigned fwengine = 0; \ |
| 830 | if (FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg)) { \ |
| 831 | if (dev_priv->uncore.fw_rendercount == 0) \ |
| 832 | fwengine = FORCEWAKE_RENDER; \ |
| 833 | } else if (FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg)) { \ |
| 834 | if (dev_priv->uncore.fw_mediacount == 0) \ |
| 835 | fwengine = FORCEWAKE_MEDIA; \ |
| 836 | } else if (FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg)) { \ |
| 837 | if (dev_priv->uncore.fw_rendercount == 0) \ |
| 838 | fwengine |= FORCEWAKE_RENDER; \ |
| 839 | if (dev_priv->uncore.fw_mediacount == 0) \ |
| 840 | fwengine |= FORCEWAKE_MEDIA; \ |
| 841 | } else { \ |
| 842 | if (dev_priv->uncore.fw_blittercount == 0) \ |
| 843 | fwengine = FORCEWAKE_BLITTER; \ |
| 844 | } \ |
| 845 | if (fwengine) \ |
| 846 | dev_priv->uncore.funcs.force_wake_get(dev_priv, fwengine); \ |
| 847 | val = __raw_i915_read##x(dev_priv, reg); \ |
| 848 | if (fwengine) \ |
| 849 | dev_priv->uncore.funcs.force_wake_put(dev_priv, fwengine); \ |
| 850 | } \ |
Chris Wilson | 51f6788 | 2015-01-16 11:34:36 +0200 | [diff] [blame^] | 851 | GEN6_READ_FOOTER; \ |
Zhe Wang | 4597a88 | 2014-11-20 13:42:55 +0000 | [diff] [blame] | 852 | } |
| 853 | |
| 854 | __gen9_read(8) |
| 855 | __gen9_read(16) |
| 856 | __gen9_read(32) |
| 857 | __gen9_read(64) |
Deepak S | 1938e59 | 2014-05-23 21:00:16 +0530 | [diff] [blame] | 858 | __chv_read(8) |
| 859 | __chv_read(16) |
| 860 | __chv_read(32) |
| 861 | __chv_read(64) |
Deepak S | 940aece | 2013-11-23 14:55:43 +0530 | [diff] [blame] | 862 | __vlv_read(8) |
| 863 | __vlv_read(16) |
| 864 | __vlv_read(32) |
| 865 | __vlv_read(64) |
Ben Widawsky | 3967018 | 2013-10-04 21:22:53 -0700 | [diff] [blame] | 866 | __gen6_read(8) |
| 867 | __gen6_read(16) |
| 868 | __gen6_read(32) |
| 869 | __gen6_read(64) |
Ben Widawsky | 3967018 | 2013-10-04 21:22:53 -0700 | [diff] [blame] | 870 | |
Zhe Wang | 4597a88 | 2014-11-20 13:42:55 +0000 | [diff] [blame] | 871 | #undef __gen9_read |
Deepak S | 1938e59 | 2014-05-23 21:00:16 +0530 | [diff] [blame] | 872 | #undef __chv_read |
Deepak S | 940aece | 2013-11-23 14:55:43 +0530 | [diff] [blame] | 873 | #undef __vlv_read |
Ben Widawsky | 3967018 | 2013-10-04 21:22:53 -0700 | [diff] [blame] | 874 | #undef __gen6_read |
Chris Wilson | 51f6788 | 2015-01-16 11:34:36 +0200 | [diff] [blame^] | 875 | #undef GEN6_READ_FOOTER |
| 876 | #undef GEN6_READ_HEADER |
Ben Widawsky | 5d73879 | 2013-10-04 21:24:53 -0700 | [diff] [blame] | 877 | |
Chris Wilson | 51f6788 | 2015-01-16 11:34:36 +0200 | [diff] [blame^] | 878 | #define GEN2_WRITE_HEADER \ |
Ben Widawsky | 5d73879 | 2013-10-04 21:24:53 -0700 | [diff] [blame] | 879 | trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \ |
Paulo Zanoni | 6f0ea9e | 2014-02-21 13:52:28 -0300 | [diff] [blame] | 880 | assert_device_not_suspended(dev_priv); \ |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 881 | |
Chris Wilson | 51f6788 | 2015-01-16 11:34:36 +0200 | [diff] [blame^] | 882 | #define GEN2_WRITE_FOOTER |
Ville Syrjälä | 0d96530 | 2013-12-02 14:23:02 +0200 | [diff] [blame] | 883 | |
Chris Wilson | 51f6788 | 2015-01-16 11:34:36 +0200 | [diff] [blame^] | 884 | #define __gen2_write(x) \ |
Ben Widawsky | 0b27448 | 2013-10-04 21:22:51 -0700 | [diff] [blame] | 885 | static void \ |
Chris Wilson | 51f6788 | 2015-01-16 11:34:36 +0200 | [diff] [blame^] | 886 | gen2_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \ |
| 887 | GEN2_WRITE_HEADER; \ |
Ben Widawsky | 4032ef4 | 2013-10-04 21:22:54 -0700 | [diff] [blame] | 888 | __raw_i915_write##x(dev_priv, reg, val); \ |
Chris Wilson | 51f6788 | 2015-01-16 11:34:36 +0200 | [diff] [blame^] | 889 | GEN2_WRITE_FOOTER; \ |
Ben Widawsky | 4032ef4 | 2013-10-04 21:22:54 -0700 | [diff] [blame] | 890 | } |
| 891 | |
| 892 | #define __gen5_write(x) \ |
| 893 | static void \ |
| 894 | gen5_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \ |
Chris Wilson | 51f6788 | 2015-01-16 11:34:36 +0200 | [diff] [blame^] | 895 | GEN2_WRITE_HEADER; \ |
Ben Widawsky | 4032ef4 | 2013-10-04 21:22:54 -0700 | [diff] [blame] | 896 | ilk_dummy_write(dev_priv); \ |
| 897 | __raw_i915_write##x(dev_priv, reg, val); \ |
Chris Wilson | 51f6788 | 2015-01-16 11:34:36 +0200 | [diff] [blame^] | 898 | GEN2_WRITE_FOOTER; \ |
Ben Widawsky | 4032ef4 | 2013-10-04 21:22:54 -0700 | [diff] [blame] | 899 | } |
| 900 | |
Chris Wilson | 51f6788 | 2015-01-16 11:34:36 +0200 | [diff] [blame^] | 901 | __gen5_write(8) |
| 902 | __gen5_write(16) |
| 903 | __gen5_write(32) |
| 904 | __gen5_write(64) |
| 905 | __gen2_write(8) |
| 906 | __gen2_write(16) |
| 907 | __gen2_write(32) |
| 908 | __gen2_write(64) |
| 909 | |
| 910 | #undef __gen5_write |
| 911 | #undef __gen2_write |
| 912 | |
| 913 | #undef GEN2_WRITE_FOOTER |
| 914 | #undef GEN2_WRITE_HEADER |
| 915 | |
| 916 | #define GEN6_WRITE_HEADER \ |
| 917 | unsigned long irqflags; \ |
| 918 | trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \ |
| 919 | assert_device_not_suspended(dev_priv); \ |
| 920 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags) |
| 921 | |
| 922 | #define GEN6_WRITE_FOOTER \ |
| 923 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags) |
| 924 | |
Ben Widawsky | 4032ef4 | 2013-10-04 21:22:54 -0700 | [diff] [blame] | 925 | #define __gen6_write(x) \ |
| 926 | static void \ |
| 927 | gen6_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \ |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 928 | u32 __fifo_ret = 0; \ |
Chris Wilson | 51f6788 | 2015-01-16 11:34:36 +0200 | [diff] [blame^] | 929 | GEN6_WRITE_HEADER; \ |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 930 | if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ |
| 931 | __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \ |
| 932 | } \ |
Ben Widawsky | 4032ef4 | 2013-10-04 21:22:54 -0700 | [diff] [blame] | 933 | __raw_i915_write##x(dev_priv, reg, val); \ |
| 934 | if (unlikely(__fifo_ret)) { \ |
| 935 | gen6_gt_check_fifodbg(dev_priv); \ |
| 936 | } \ |
Chris Wilson | 51f6788 | 2015-01-16 11:34:36 +0200 | [diff] [blame^] | 937 | GEN6_WRITE_FOOTER; \ |
Ben Widawsky | 4032ef4 | 2013-10-04 21:22:54 -0700 | [diff] [blame] | 938 | } |
| 939 | |
| 940 | #define __hsw_write(x) \ |
| 941 | static void \ |
| 942 | hsw_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \ |
| 943 | u32 __fifo_ret = 0; \ |
Chris Wilson | 51f6788 | 2015-01-16 11:34:36 +0200 | [diff] [blame^] | 944 | GEN6_WRITE_HEADER; \ |
Ben Widawsky | 4032ef4 | 2013-10-04 21:22:54 -0700 | [diff] [blame] | 945 | if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ |
| 946 | __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \ |
| 947 | } \ |
Paulo Zanoni | 5978118 | 2014-07-16 17:49:29 -0300 | [diff] [blame] | 948 | hsw_unclaimed_reg_debug(dev_priv, reg, false, true); \ |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 949 | __raw_i915_write##x(dev_priv, reg, val); \ |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 950 | if (unlikely(__fifo_ret)) { \ |
| 951 | gen6_gt_check_fifodbg(dev_priv); \ |
| 952 | } \ |
Paulo Zanoni | 5978118 | 2014-07-16 17:49:29 -0300 | [diff] [blame] | 953 | hsw_unclaimed_reg_debug(dev_priv, reg, false, false); \ |
| 954 | hsw_unclaimed_reg_detect(dev_priv); \ |
Chris Wilson | 51f6788 | 2015-01-16 11:34:36 +0200 | [diff] [blame^] | 955 | GEN6_WRITE_FOOTER; \ |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 956 | } |
Ben Widawsky | 3967018 | 2013-10-04 21:22:53 -0700 | [diff] [blame] | 957 | |
Ben Widawsky | ab2aa47 | 2013-11-02 21:07:00 -0700 | [diff] [blame] | 958 | static const u32 gen8_shadowed_regs[] = { |
| 959 | FORCEWAKE_MT, |
| 960 | GEN6_RPNSWREQ, |
| 961 | GEN6_RC_VIDEO_FREQ, |
| 962 | RING_TAIL(RENDER_RING_BASE), |
| 963 | RING_TAIL(GEN6_BSD_RING_BASE), |
| 964 | RING_TAIL(VEBOX_RING_BASE), |
| 965 | RING_TAIL(BLT_RING_BASE), |
| 966 | /* TODO: Other registers are not yet used */ |
| 967 | }; |
| 968 | |
| 969 | static bool is_gen8_shadowed(struct drm_i915_private *dev_priv, u32 reg) |
| 970 | { |
| 971 | int i; |
| 972 | for (i = 0; i < ARRAY_SIZE(gen8_shadowed_regs); i++) |
| 973 | if (reg == gen8_shadowed_regs[i]) |
| 974 | return true; |
| 975 | |
| 976 | return false; |
| 977 | } |
| 978 | |
| 979 | #define __gen8_write(x) \ |
| 980 | static void \ |
| 981 | gen8_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \ |
Chris Wilson | 51f6788 | 2015-01-16 11:34:36 +0200 | [diff] [blame^] | 982 | GEN6_WRITE_HEADER; \ |
Paulo Zanoni | 66bc2ca | 2014-07-16 17:49:30 -0300 | [diff] [blame] | 983 | hsw_unclaimed_reg_debug(dev_priv, reg, false, true); \ |
Mika Kuoppala | e9dbd2b | 2014-02-18 19:10:24 +0200 | [diff] [blame] | 984 | if (reg < 0x40000 && !is_gen8_shadowed(dev_priv, reg)) { \ |
| 985 | if (dev_priv->uncore.forcewake_count == 0) \ |
| 986 | dev_priv->uncore.funcs.force_wake_get(dev_priv, \ |
| 987 | FORCEWAKE_ALL); \ |
| 988 | __raw_i915_write##x(dev_priv, reg, val); \ |
| 989 | if (dev_priv->uncore.forcewake_count == 0) \ |
| 990 | dev_priv->uncore.funcs.force_wake_put(dev_priv, \ |
| 991 | FORCEWAKE_ALL); \ |
| 992 | } else { \ |
| 993 | __raw_i915_write##x(dev_priv, reg, val); \ |
Ben Widawsky | ab2aa47 | 2013-11-02 21:07:00 -0700 | [diff] [blame] | 994 | } \ |
Paulo Zanoni | 66bc2ca | 2014-07-16 17:49:30 -0300 | [diff] [blame] | 995 | hsw_unclaimed_reg_debug(dev_priv, reg, false, false); \ |
| 996 | hsw_unclaimed_reg_detect(dev_priv); \ |
Chris Wilson | 51f6788 | 2015-01-16 11:34:36 +0200 | [diff] [blame^] | 997 | GEN6_WRITE_FOOTER; \ |
Ben Widawsky | ab2aa47 | 2013-11-02 21:07:00 -0700 | [diff] [blame] | 998 | } |
| 999 | |
Deepak S | 1938e59 | 2014-05-23 21:00:16 +0530 | [diff] [blame] | 1000 | #define __chv_write(x) \ |
| 1001 | static void \ |
| 1002 | chv_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \ |
| 1003 | unsigned fwengine = 0; \ |
| 1004 | bool shadowed = is_gen8_shadowed(dev_priv, reg); \ |
Chris Wilson | 51f6788 | 2015-01-16 11:34:36 +0200 | [diff] [blame^] | 1005 | GEN6_WRITE_HEADER; \ |
Deepak S | 1938e59 | 2014-05-23 21:00:16 +0530 | [diff] [blame] | 1006 | if (!shadowed) { \ |
| 1007 | if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) { \ |
| 1008 | if (dev_priv->uncore.fw_rendercount == 0) \ |
| 1009 | fwengine = FORCEWAKE_RENDER; \ |
| 1010 | } else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) { \ |
| 1011 | if (dev_priv->uncore.fw_mediacount == 0) \ |
| 1012 | fwengine = FORCEWAKE_MEDIA; \ |
| 1013 | } else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) { \ |
| 1014 | if (dev_priv->uncore.fw_rendercount == 0) \ |
| 1015 | fwengine |= FORCEWAKE_RENDER; \ |
| 1016 | if (dev_priv->uncore.fw_mediacount == 0) \ |
| 1017 | fwengine |= FORCEWAKE_MEDIA; \ |
| 1018 | } \ |
| 1019 | } \ |
| 1020 | if (fwengine) \ |
| 1021 | dev_priv->uncore.funcs.force_wake_get(dev_priv, fwengine); \ |
| 1022 | __raw_i915_write##x(dev_priv, reg, val); \ |
| 1023 | if (fwengine) \ |
| 1024 | dev_priv->uncore.funcs.force_wake_put(dev_priv, fwengine); \ |
Chris Wilson | 51f6788 | 2015-01-16 11:34:36 +0200 | [diff] [blame^] | 1025 | GEN6_WRITE_FOOTER; \ |
Deepak S | 1938e59 | 2014-05-23 21:00:16 +0530 | [diff] [blame] | 1026 | } |
| 1027 | |
Zhe Wang | 7c85900 | 2014-11-20 13:42:56 +0000 | [diff] [blame] | 1028 | static const u32 gen9_shadowed_regs[] = { |
| 1029 | RING_TAIL(RENDER_RING_BASE), |
| 1030 | RING_TAIL(GEN6_BSD_RING_BASE), |
| 1031 | RING_TAIL(VEBOX_RING_BASE), |
| 1032 | RING_TAIL(BLT_RING_BASE), |
| 1033 | FORCEWAKE_BLITTER_GEN9, |
| 1034 | FORCEWAKE_RENDER_GEN9, |
| 1035 | FORCEWAKE_MEDIA_GEN9, |
| 1036 | GEN6_RPNSWREQ, |
| 1037 | GEN6_RC_VIDEO_FREQ, |
| 1038 | /* TODO: Other registers are not yet used */ |
| 1039 | }; |
| 1040 | |
| 1041 | static bool is_gen9_shadowed(struct drm_i915_private *dev_priv, u32 reg) |
| 1042 | { |
| 1043 | int i; |
| 1044 | for (i = 0; i < ARRAY_SIZE(gen9_shadowed_regs); i++) |
| 1045 | if (reg == gen9_shadowed_regs[i]) |
| 1046 | return true; |
| 1047 | |
| 1048 | return false; |
| 1049 | } |
| 1050 | |
Zhe Wang | 4597a88 | 2014-11-20 13:42:55 +0000 | [diff] [blame] | 1051 | #define __gen9_write(x) \ |
| 1052 | static void \ |
| 1053 | gen9_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, \ |
| 1054 | bool trace) { \ |
Chris Wilson | 51f6788 | 2015-01-16 11:34:36 +0200 | [diff] [blame^] | 1055 | GEN6_WRITE_HEADER; \ |
Zhe Wang | 7c85900 | 2014-11-20 13:42:56 +0000 | [diff] [blame] | 1056 | if (!SKL_NEEDS_FORCE_WAKE((dev_priv), (reg)) || \ |
| 1057 | is_gen9_shadowed(dev_priv, reg)) { \ |
Zhe Wang | 4597a88 | 2014-11-20 13:42:55 +0000 | [diff] [blame] | 1058 | __raw_i915_write##x(dev_priv, reg, val); \ |
| 1059 | } else { \ |
| 1060 | unsigned fwengine = 0; \ |
| 1061 | if (FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg)) { \ |
| 1062 | if (dev_priv->uncore.fw_rendercount == 0) \ |
| 1063 | fwengine = FORCEWAKE_RENDER; \ |
| 1064 | } else if (FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg)) { \ |
| 1065 | if (dev_priv->uncore.fw_mediacount == 0) \ |
| 1066 | fwengine = FORCEWAKE_MEDIA; \ |
| 1067 | } else if (FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg)) { \ |
| 1068 | if (dev_priv->uncore.fw_rendercount == 0) \ |
| 1069 | fwengine |= FORCEWAKE_RENDER; \ |
| 1070 | if (dev_priv->uncore.fw_mediacount == 0) \ |
| 1071 | fwengine |= FORCEWAKE_MEDIA; \ |
| 1072 | } else { \ |
| 1073 | if (dev_priv->uncore.fw_blittercount == 0) \ |
| 1074 | fwengine = FORCEWAKE_BLITTER; \ |
| 1075 | } \ |
| 1076 | if (fwengine) \ |
| 1077 | dev_priv->uncore.funcs.force_wake_get(dev_priv, \ |
| 1078 | fwengine); \ |
| 1079 | __raw_i915_write##x(dev_priv, reg, val); \ |
| 1080 | if (fwengine) \ |
| 1081 | dev_priv->uncore.funcs.force_wake_put(dev_priv, \ |
| 1082 | fwengine); \ |
| 1083 | } \ |
Chris Wilson | 51f6788 | 2015-01-16 11:34:36 +0200 | [diff] [blame^] | 1084 | GEN6_WRITE_FOOTER; \ |
Zhe Wang | 4597a88 | 2014-11-20 13:42:55 +0000 | [diff] [blame] | 1085 | } |
| 1086 | |
| 1087 | __gen9_write(8) |
| 1088 | __gen9_write(16) |
| 1089 | __gen9_write(32) |
| 1090 | __gen9_write(64) |
Deepak S | 1938e59 | 2014-05-23 21:00:16 +0530 | [diff] [blame] | 1091 | __chv_write(8) |
| 1092 | __chv_write(16) |
| 1093 | __chv_write(32) |
| 1094 | __chv_write(64) |
Ben Widawsky | ab2aa47 | 2013-11-02 21:07:00 -0700 | [diff] [blame] | 1095 | __gen8_write(8) |
| 1096 | __gen8_write(16) |
| 1097 | __gen8_write(32) |
| 1098 | __gen8_write(64) |
Ben Widawsky | 4032ef4 | 2013-10-04 21:22:54 -0700 | [diff] [blame] | 1099 | __hsw_write(8) |
| 1100 | __hsw_write(16) |
| 1101 | __hsw_write(32) |
| 1102 | __hsw_write(64) |
| 1103 | __gen6_write(8) |
| 1104 | __gen6_write(16) |
| 1105 | __gen6_write(32) |
| 1106 | __gen6_write(64) |
Ben Widawsky | 4032ef4 | 2013-10-04 21:22:54 -0700 | [diff] [blame] | 1107 | |
Zhe Wang | 4597a88 | 2014-11-20 13:42:55 +0000 | [diff] [blame] | 1108 | #undef __gen9_write |
Deepak S | 1938e59 | 2014-05-23 21:00:16 +0530 | [diff] [blame] | 1109 | #undef __chv_write |
Ben Widawsky | ab2aa47 | 2013-11-02 21:07:00 -0700 | [diff] [blame] | 1110 | #undef __gen8_write |
Ben Widawsky | 4032ef4 | 2013-10-04 21:22:54 -0700 | [diff] [blame] | 1111 | #undef __hsw_write |
| 1112 | #undef __gen6_write |
Chris Wilson | 51f6788 | 2015-01-16 11:34:36 +0200 | [diff] [blame^] | 1113 | #undef GEN6_WRITE_FOOTER |
| 1114 | #undef GEN6_WRITE_HEADER |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 1115 | |
Yu Zhang | 43d942a | 2014-10-23 15:28:24 +0800 | [diff] [blame] | 1116 | #define ASSIGN_WRITE_MMIO_VFUNCS(x) \ |
| 1117 | do { \ |
| 1118 | dev_priv->uncore.funcs.mmio_writeb = x##_write8; \ |
| 1119 | dev_priv->uncore.funcs.mmio_writew = x##_write16; \ |
| 1120 | dev_priv->uncore.funcs.mmio_writel = x##_write32; \ |
| 1121 | dev_priv->uncore.funcs.mmio_writeq = x##_write64; \ |
| 1122 | } while (0) |
| 1123 | |
| 1124 | #define ASSIGN_READ_MMIO_VFUNCS(x) \ |
| 1125 | do { \ |
| 1126 | dev_priv->uncore.funcs.mmio_readb = x##_read8; \ |
| 1127 | dev_priv->uncore.funcs.mmio_readw = x##_read16; \ |
| 1128 | dev_priv->uncore.funcs.mmio_readl = x##_read32; \ |
| 1129 | dev_priv->uncore.funcs.mmio_readq = x##_read64; \ |
| 1130 | } while (0) |
| 1131 | |
Ben Widawsky | 0b27448 | 2013-10-04 21:22:51 -0700 | [diff] [blame] | 1132 | void intel_uncore_init(struct drm_device *dev) |
| 1133 | { |
| 1134 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1135 | |
Chris Wilson | 8232644 | 2014-03-05 12:00:39 +0000 | [diff] [blame] | 1136 | setup_timer(&dev_priv->uncore.force_wake_timer, |
| 1137 | gen6_force_wake_timer, (unsigned long)dev_priv); |
Ben Widawsky | 0b27448 | 2013-10-04 21:22:51 -0700 | [diff] [blame] | 1138 | |
Imre Deak | ed49388 | 2014-10-23 19:23:21 +0300 | [diff] [blame] | 1139 | __intel_uncore_early_sanitize(dev, false); |
Daniel Vetter | 05efeebd | 2014-03-18 16:26:25 +0100 | [diff] [blame] | 1140 | |
Zhe Wang | 38cff0b | 2014-11-04 17:07:04 +0000 | [diff] [blame] | 1141 | if (IS_GEN9(dev)) { |
| 1142 | dev_priv->uncore.funcs.force_wake_get = __gen9_force_wake_get; |
| 1143 | dev_priv->uncore.funcs.force_wake_put = __gen9_force_wake_put; |
| 1144 | } else if (IS_VALLEYVIEW(dev)) { |
Deepak S | 940aece | 2013-11-23 14:55:43 +0530 | [diff] [blame] | 1145 | dev_priv->uncore.funcs.force_wake_get = __vlv_force_wake_get; |
| 1146 | dev_priv->uncore.funcs.force_wake_put = __vlv_force_wake_put; |
Ville Syrjälä | f98cd09 | 2014-09-03 14:09:51 +0300 | [diff] [blame] | 1147 | } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
Mika Kuoppala | 6a68735 | 2014-02-21 18:47:36 +0200 | [diff] [blame] | 1148 | dev_priv->uncore.funcs.force_wake_get = __gen7_gt_force_wake_mt_get; |
| 1149 | dev_priv->uncore.funcs.force_wake_put = __gen7_gt_force_wake_mt_put; |
Ben Widawsky | 0b27448 | 2013-10-04 21:22:51 -0700 | [diff] [blame] | 1150 | } else if (IS_IVYBRIDGE(dev)) { |
| 1151 | u32 ecobus; |
| 1152 | |
| 1153 | /* IVB configs may use multi-threaded forcewake */ |
| 1154 | |
| 1155 | /* A small trick here - if the bios hasn't configured |
| 1156 | * MT forcewake, and if the device is in RC6, then |
| 1157 | * force_wake_mt_get will not wake the device and the |
| 1158 | * ECOBUS read will return zero. Which will be |
| 1159 | * (correctly) interpreted by the test below as MT |
| 1160 | * forcewake being disabled. |
| 1161 | */ |
| 1162 | mutex_lock(&dev->struct_mutex); |
Mika Kuoppala | 6a68735 | 2014-02-21 18:47:36 +0200 | [diff] [blame] | 1163 | __gen7_gt_force_wake_mt_get(dev_priv, FORCEWAKE_ALL); |
Ben Widawsky | 0b27448 | 2013-10-04 21:22:51 -0700 | [diff] [blame] | 1164 | ecobus = __raw_i915_read32(dev_priv, ECOBUS); |
Mika Kuoppala | 6a68735 | 2014-02-21 18:47:36 +0200 | [diff] [blame] | 1165 | __gen7_gt_force_wake_mt_put(dev_priv, FORCEWAKE_ALL); |
Ben Widawsky | 0b27448 | 2013-10-04 21:22:51 -0700 | [diff] [blame] | 1166 | mutex_unlock(&dev->struct_mutex); |
| 1167 | |
| 1168 | if (ecobus & FORCEWAKE_MT_ENABLE) { |
| 1169 | dev_priv->uncore.funcs.force_wake_get = |
Mika Kuoppala | 6a68735 | 2014-02-21 18:47:36 +0200 | [diff] [blame] | 1170 | __gen7_gt_force_wake_mt_get; |
Ben Widawsky | 0b27448 | 2013-10-04 21:22:51 -0700 | [diff] [blame] | 1171 | dev_priv->uncore.funcs.force_wake_put = |
Mika Kuoppala | 6a68735 | 2014-02-21 18:47:36 +0200 | [diff] [blame] | 1172 | __gen7_gt_force_wake_mt_put; |
Ben Widawsky | 0b27448 | 2013-10-04 21:22:51 -0700 | [diff] [blame] | 1173 | } else { |
| 1174 | DRM_INFO("No MT forcewake available on Ivybridge, this can result in issues\n"); |
| 1175 | DRM_INFO("when using vblank-synced partial screen updates.\n"); |
| 1176 | dev_priv->uncore.funcs.force_wake_get = |
| 1177 | __gen6_gt_force_wake_get; |
| 1178 | dev_priv->uncore.funcs.force_wake_put = |
| 1179 | __gen6_gt_force_wake_put; |
| 1180 | } |
| 1181 | } else if (IS_GEN6(dev)) { |
| 1182 | dev_priv->uncore.funcs.force_wake_get = |
| 1183 | __gen6_gt_force_wake_get; |
| 1184 | dev_priv->uncore.funcs.force_wake_put = |
| 1185 | __gen6_gt_force_wake_put; |
| 1186 | } |
| 1187 | |
Ben Widawsky | 3967018 | 2013-10-04 21:22:53 -0700 | [diff] [blame] | 1188 | switch (INTEL_INFO(dev)->gen) { |
Ben Widawsky | ab2aa47 | 2013-11-02 21:07:00 -0700 | [diff] [blame] | 1189 | default: |
Daniel Vetter | 5f77eeb | 2014-12-08 16:40:10 +0100 | [diff] [blame] | 1190 | MISSING_CASE(INTEL_INFO(dev)->gen); |
Zhe Wang | 4597a88 | 2014-11-20 13:42:55 +0000 | [diff] [blame] | 1191 | return; |
| 1192 | case 9: |
| 1193 | ASSIGN_WRITE_MMIO_VFUNCS(gen9); |
| 1194 | ASSIGN_READ_MMIO_VFUNCS(gen9); |
| 1195 | break; |
| 1196 | case 8: |
Deepak S | 1938e59 | 2014-05-23 21:00:16 +0530 | [diff] [blame] | 1197 | if (IS_CHERRYVIEW(dev)) { |
Yu Zhang | 43d942a | 2014-10-23 15:28:24 +0800 | [diff] [blame] | 1198 | ASSIGN_WRITE_MMIO_VFUNCS(chv); |
| 1199 | ASSIGN_READ_MMIO_VFUNCS(chv); |
Deepak S | 1938e59 | 2014-05-23 21:00:16 +0530 | [diff] [blame] | 1200 | |
| 1201 | } else { |
Yu Zhang | 43d942a | 2014-10-23 15:28:24 +0800 | [diff] [blame] | 1202 | ASSIGN_WRITE_MMIO_VFUNCS(gen8); |
| 1203 | ASSIGN_READ_MMIO_VFUNCS(gen6); |
Deepak S | 1938e59 | 2014-05-23 21:00:16 +0530 | [diff] [blame] | 1204 | } |
Ben Widawsky | ab2aa47 | 2013-11-02 21:07:00 -0700 | [diff] [blame] | 1205 | break; |
Ben Widawsky | 3967018 | 2013-10-04 21:22:53 -0700 | [diff] [blame] | 1206 | case 7: |
| 1207 | case 6: |
Ben Widawsky | 4032ef4 | 2013-10-04 21:22:54 -0700 | [diff] [blame] | 1208 | if (IS_HASWELL(dev)) { |
Yu Zhang | 43d942a | 2014-10-23 15:28:24 +0800 | [diff] [blame] | 1209 | ASSIGN_WRITE_MMIO_VFUNCS(hsw); |
Ben Widawsky | 4032ef4 | 2013-10-04 21:22:54 -0700 | [diff] [blame] | 1210 | } else { |
Yu Zhang | 43d942a | 2014-10-23 15:28:24 +0800 | [diff] [blame] | 1211 | ASSIGN_WRITE_MMIO_VFUNCS(gen6); |
Ben Widawsky | 4032ef4 | 2013-10-04 21:22:54 -0700 | [diff] [blame] | 1212 | } |
Deepak S | 940aece | 2013-11-23 14:55:43 +0530 | [diff] [blame] | 1213 | |
| 1214 | if (IS_VALLEYVIEW(dev)) { |
Yu Zhang | 43d942a | 2014-10-23 15:28:24 +0800 | [diff] [blame] | 1215 | ASSIGN_READ_MMIO_VFUNCS(vlv); |
Deepak S | 940aece | 2013-11-23 14:55:43 +0530 | [diff] [blame] | 1216 | } else { |
Yu Zhang | 43d942a | 2014-10-23 15:28:24 +0800 | [diff] [blame] | 1217 | ASSIGN_READ_MMIO_VFUNCS(gen6); |
Deepak S | 940aece | 2013-11-23 14:55:43 +0530 | [diff] [blame] | 1218 | } |
Ben Widawsky | 3967018 | 2013-10-04 21:22:53 -0700 | [diff] [blame] | 1219 | break; |
| 1220 | case 5: |
Yu Zhang | 43d942a | 2014-10-23 15:28:24 +0800 | [diff] [blame] | 1221 | ASSIGN_WRITE_MMIO_VFUNCS(gen5); |
| 1222 | ASSIGN_READ_MMIO_VFUNCS(gen5); |
Ben Widawsky | 3967018 | 2013-10-04 21:22:53 -0700 | [diff] [blame] | 1223 | break; |
| 1224 | case 4: |
| 1225 | case 3: |
| 1226 | case 2: |
Chris Wilson | 51f6788 | 2015-01-16 11:34:36 +0200 | [diff] [blame^] | 1227 | ASSIGN_WRITE_MMIO_VFUNCS(gen2); |
| 1228 | ASSIGN_READ_MMIO_VFUNCS(gen2); |
Ben Widawsky | 3967018 | 2013-10-04 21:22:53 -0700 | [diff] [blame] | 1229 | break; |
| 1230 | } |
Imre Deak | ed49388 | 2014-10-23 19:23:21 +0300 | [diff] [blame] | 1231 | |
| 1232 | i915_check_and_clear_faults(dev); |
Ben Widawsky | 0b27448 | 2013-10-04 21:22:51 -0700 | [diff] [blame] | 1233 | } |
Yu Zhang | 43d942a | 2014-10-23 15:28:24 +0800 | [diff] [blame] | 1234 | #undef ASSIGN_WRITE_MMIO_VFUNCS |
| 1235 | #undef ASSIGN_READ_MMIO_VFUNCS |
Ben Widawsky | 0b27448 | 2013-10-04 21:22:51 -0700 | [diff] [blame] | 1236 | |
| 1237 | void intel_uncore_fini(struct drm_device *dev) |
| 1238 | { |
Ben Widawsky | 0b27448 | 2013-10-04 21:22:51 -0700 | [diff] [blame] | 1239 | /* Paranoia: make sure we have disabled everything before we exit. */ |
| 1240 | intel_uncore_sanitize(dev); |
Chris Wilson | 0294ae7 | 2014-03-13 12:00:29 +0000 | [diff] [blame] | 1241 | intel_uncore_forcewake_reset(dev, false); |
Ben Widawsky | 0b27448 | 2013-10-04 21:22:51 -0700 | [diff] [blame] | 1242 | } |
| 1243 | |
Damien Lespiau | af76ae44 | 2014-03-31 11:24:08 +0100 | [diff] [blame] | 1244 | #define GEN_RANGE(l, h) GENMASK(h, l) |
| 1245 | |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 1246 | static const struct register_whitelist { |
| 1247 | uint64_t offset; |
| 1248 | uint32_t size; |
Damien Lespiau | af76ae44 | 2014-03-31 11:24:08 +0100 | [diff] [blame] | 1249 | /* supported gens, 0x10 for 4, 0x30 for 4 and 5, etc. */ |
| 1250 | uint32_t gen_bitmask; |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 1251 | } whitelist[] = { |
Damien Lespiau | c3f59a6 | 2014-03-30 16:28:23 +0100 | [diff] [blame] | 1252 | { RING_TIMESTAMP(RENDER_RING_BASE), 8, GEN_RANGE(4, 9) }, |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 1253 | }; |
| 1254 | |
| 1255 | int i915_reg_read_ioctl(struct drm_device *dev, |
| 1256 | void *data, struct drm_file *file) |
| 1257 | { |
| 1258 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1259 | struct drm_i915_reg_read *reg = data; |
| 1260 | struct register_whitelist const *entry = whitelist; |
Paulo Zanoni | cf67c70 | 2014-04-01 14:55:08 -0300 | [diff] [blame] | 1261 | int i, ret = 0; |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 1262 | |
| 1263 | for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) { |
| 1264 | if (entry->offset == reg->offset && |
| 1265 | (1 << INTEL_INFO(dev)->gen & entry->gen_bitmask)) |
| 1266 | break; |
| 1267 | } |
| 1268 | |
| 1269 | if (i == ARRAY_SIZE(whitelist)) |
| 1270 | return -EINVAL; |
| 1271 | |
Paulo Zanoni | cf67c70 | 2014-04-01 14:55:08 -0300 | [diff] [blame] | 1272 | intel_runtime_pm_get(dev_priv); |
| 1273 | |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 1274 | switch (entry->size) { |
| 1275 | case 8: |
| 1276 | reg->val = I915_READ64(reg->offset); |
| 1277 | break; |
| 1278 | case 4: |
| 1279 | reg->val = I915_READ(reg->offset); |
| 1280 | break; |
| 1281 | case 2: |
| 1282 | reg->val = I915_READ16(reg->offset); |
| 1283 | break; |
| 1284 | case 1: |
| 1285 | reg->val = I915_READ8(reg->offset); |
| 1286 | break; |
| 1287 | default: |
Daniel Vetter | 5f77eeb | 2014-12-08 16:40:10 +0100 | [diff] [blame] | 1288 | MISSING_CASE(entry->size); |
Paulo Zanoni | cf67c70 | 2014-04-01 14:55:08 -0300 | [diff] [blame] | 1289 | ret = -EINVAL; |
| 1290 | goto out; |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 1291 | } |
| 1292 | |
Paulo Zanoni | cf67c70 | 2014-04-01 14:55:08 -0300 | [diff] [blame] | 1293 | out: |
| 1294 | intel_runtime_pm_put(dev_priv); |
| 1295 | return ret; |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 1296 | } |
| 1297 | |
Mika Kuoppala | b635991 | 2013-10-30 15:44:16 +0200 | [diff] [blame] | 1298 | int i915_get_reset_stats_ioctl(struct drm_device *dev, |
| 1299 | void *data, struct drm_file *file) |
| 1300 | { |
| 1301 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1302 | struct drm_i915_reset_stats *args = data; |
| 1303 | struct i915_ctx_hang_stats *hs; |
Oscar Mateo | 273497e | 2014-05-22 14:13:37 +0100 | [diff] [blame] | 1304 | struct intel_context *ctx; |
Mika Kuoppala | b635991 | 2013-10-30 15:44:16 +0200 | [diff] [blame] | 1305 | int ret; |
| 1306 | |
Mika Kuoppala | 661df04 | 2013-11-12 19:49:35 +0200 | [diff] [blame] | 1307 | if (args->flags || args->pad) |
| 1308 | return -EINVAL; |
| 1309 | |
Oscar Mateo | 821d66d | 2014-07-03 16:28:00 +0100 | [diff] [blame] | 1310 | if (args->ctx_id == DEFAULT_CONTEXT_HANDLE && !capable(CAP_SYS_ADMIN)) |
Mika Kuoppala | b635991 | 2013-10-30 15:44:16 +0200 | [diff] [blame] | 1311 | return -EPERM; |
| 1312 | |
| 1313 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 1314 | if (ret) |
| 1315 | return ret; |
| 1316 | |
Ben Widawsky | 41bde55 | 2013-12-06 14:11:21 -0800 | [diff] [blame] | 1317 | ctx = i915_gem_context_get(file->driver_priv, args->ctx_id); |
| 1318 | if (IS_ERR(ctx)) { |
Mika Kuoppala | b635991 | 2013-10-30 15:44:16 +0200 | [diff] [blame] | 1319 | mutex_unlock(&dev->struct_mutex); |
Ben Widawsky | 41bde55 | 2013-12-06 14:11:21 -0800 | [diff] [blame] | 1320 | return PTR_ERR(ctx); |
Mika Kuoppala | b635991 | 2013-10-30 15:44:16 +0200 | [diff] [blame] | 1321 | } |
Ben Widawsky | 41bde55 | 2013-12-06 14:11:21 -0800 | [diff] [blame] | 1322 | hs = &ctx->hang_stats; |
Mika Kuoppala | b635991 | 2013-10-30 15:44:16 +0200 | [diff] [blame] | 1323 | |
| 1324 | if (capable(CAP_SYS_ADMIN)) |
| 1325 | args->reset_count = i915_reset_count(&dev_priv->gpu_error); |
| 1326 | else |
| 1327 | args->reset_count = 0; |
| 1328 | |
| 1329 | args->batch_active = hs->batch_active; |
| 1330 | args->batch_pending = hs->batch_pending; |
| 1331 | |
| 1332 | mutex_unlock(&dev->struct_mutex); |
| 1333 | |
| 1334 | return 0; |
| 1335 | } |
| 1336 | |
Ville Syrjälä | 59ea905 | 2014-11-21 21:54:27 +0200 | [diff] [blame] | 1337 | static int i915_reset_complete(struct drm_device *dev) |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 1338 | { |
| 1339 | u8 gdrst; |
Ville Syrjälä | 59ea905 | 2014-11-21 21:54:27 +0200 | [diff] [blame] | 1340 | pci_read_config_byte(dev->pdev, I915_GDRST, &gdrst); |
Ville Syrjälä | 73bbf6b | 2014-11-21 21:54:25 +0200 | [diff] [blame] | 1341 | return (gdrst & GRDOM_RESET_STATUS) == 0; |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 1342 | } |
| 1343 | |
Ville Syrjälä | 59ea905 | 2014-11-21 21:54:27 +0200 | [diff] [blame] | 1344 | static int i915_do_reset(struct drm_device *dev) |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 1345 | { |
Ville Syrjälä | 73bbf6b | 2014-11-21 21:54:25 +0200 | [diff] [blame] | 1346 | /* assert reset for at least 20 usec */ |
Ville Syrjälä | 59ea905 | 2014-11-21 21:54:27 +0200 | [diff] [blame] | 1347 | pci_write_config_byte(dev->pdev, I915_GDRST, GRDOM_RESET_ENABLE); |
Ville Syrjälä | 73bbf6b | 2014-11-21 21:54:25 +0200 | [diff] [blame] | 1348 | udelay(20); |
Ville Syrjälä | 59ea905 | 2014-11-21 21:54:27 +0200 | [diff] [blame] | 1349 | pci_write_config_byte(dev->pdev, I915_GDRST, 0); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 1350 | |
Ville Syrjälä | 59ea905 | 2014-11-21 21:54:27 +0200 | [diff] [blame] | 1351 | return wait_for(i915_reset_complete(dev), 500); |
Ville Syrjälä | 73bbf6b | 2014-11-21 21:54:25 +0200 | [diff] [blame] | 1352 | } |
| 1353 | |
| 1354 | static int g4x_reset_complete(struct drm_device *dev) |
| 1355 | { |
| 1356 | u8 gdrst; |
Ville Syrjälä | 59ea905 | 2014-11-21 21:54:27 +0200 | [diff] [blame] | 1357 | pci_read_config_byte(dev->pdev, I915_GDRST, &gdrst); |
Ville Syrjälä | 73bbf6b | 2014-11-21 21:54:25 +0200 | [diff] [blame] | 1358 | return (gdrst & GRDOM_RESET_ENABLE) == 0; |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 1359 | } |
| 1360 | |
Ville Syrjälä | 408d4b9 | 2014-11-21 21:54:28 +0200 | [diff] [blame] | 1361 | static int g33_do_reset(struct drm_device *dev) |
| 1362 | { |
Ville Syrjälä | 408d4b9 | 2014-11-21 21:54:28 +0200 | [diff] [blame] | 1363 | pci_write_config_byte(dev->pdev, I915_GDRST, GRDOM_RESET_ENABLE); |
| 1364 | return wait_for(g4x_reset_complete(dev), 500); |
| 1365 | } |
| 1366 | |
Ville Syrjälä | fa4f53c | 2014-05-19 19:23:27 +0300 | [diff] [blame] | 1367 | static int g4x_do_reset(struct drm_device *dev) |
| 1368 | { |
| 1369 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1370 | int ret; |
| 1371 | |
Ville Syrjälä | 59ea905 | 2014-11-21 21:54:27 +0200 | [diff] [blame] | 1372 | pci_write_config_byte(dev->pdev, I915_GDRST, |
Ville Syrjälä | fa4f53c | 2014-05-19 19:23:27 +0300 | [diff] [blame] | 1373 | GRDOM_RENDER | GRDOM_RESET_ENABLE); |
Ville Syrjälä | 73bbf6b | 2014-11-21 21:54:25 +0200 | [diff] [blame] | 1374 | ret = wait_for(g4x_reset_complete(dev), 500); |
Ville Syrjälä | fa4f53c | 2014-05-19 19:23:27 +0300 | [diff] [blame] | 1375 | if (ret) |
| 1376 | return ret; |
| 1377 | |
| 1378 | /* WaVcpClkGateDisableForMediaReset:ctg,elk */ |
| 1379 | I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) | VCP_UNIT_CLOCK_GATE_DISABLE); |
| 1380 | POSTING_READ(VDECCLK_GATE_D); |
| 1381 | |
Ville Syrjälä | 59ea905 | 2014-11-21 21:54:27 +0200 | [diff] [blame] | 1382 | pci_write_config_byte(dev->pdev, I915_GDRST, |
Ville Syrjälä | fa4f53c | 2014-05-19 19:23:27 +0300 | [diff] [blame] | 1383 | GRDOM_MEDIA | GRDOM_RESET_ENABLE); |
Ville Syrjälä | 73bbf6b | 2014-11-21 21:54:25 +0200 | [diff] [blame] | 1384 | ret = wait_for(g4x_reset_complete(dev), 500); |
Ville Syrjälä | fa4f53c | 2014-05-19 19:23:27 +0300 | [diff] [blame] | 1385 | if (ret) |
| 1386 | return ret; |
| 1387 | |
| 1388 | /* WaVcpClkGateDisableForMediaReset:ctg,elk */ |
| 1389 | I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) & ~VCP_UNIT_CLOCK_GATE_DISABLE); |
| 1390 | POSTING_READ(VDECCLK_GATE_D); |
| 1391 | |
Ville Syrjälä | 59ea905 | 2014-11-21 21:54:27 +0200 | [diff] [blame] | 1392 | pci_write_config_byte(dev->pdev, I915_GDRST, 0); |
Ville Syrjälä | fa4f53c | 2014-05-19 19:23:27 +0300 | [diff] [blame] | 1393 | |
| 1394 | return 0; |
| 1395 | } |
| 1396 | |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 1397 | static int ironlake_do_reset(struct drm_device *dev) |
| 1398 | { |
| 1399 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 1400 | int ret; |
| 1401 | |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 1402 | I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, |
Ville Syrjälä | 0f08ffd | 2014-05-19 19:23:25 +0300 | [diff] [blame] | 1403 | ILK_GRDOM_RENDER | ILK_GRDOM_RESET_ENABLE); |
Ville Syrjälä | f67deb7 | 2014-05-19 19:23:23 +0300 | [diff] [blame] | 1404 | ret = wait_for((I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & |
Ville Syrjälä | b3a3f03 | 2014-05-19 19:23:24 +0300 | [diff] [blame] | 1405 | ILK_GRDOM_RESET_ENABLE) == 0, 500); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 1406 | if (ret) |
| 1407 | return ret; |
| 1408 | |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 1409 | I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, |
Ville Syrjälä | 0f08ffd | 2014-05-19 19:23:25 +0300 | [diff] [blame] | 1410 | ILK_GRDOM_MEDIA | ILK_GRDOM_RESET_ENABLE); |
Ville Syrjälä | 9aa7250 | 2014-05-19 19:23:26 +0300 | [diff] [blame] | 1411 | ret = wait_for((I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & |
| 1412 | ILK_GRDOM_RESET_ENABLE) == 0, 500); |
| 1413 | if (ret) |
| 1414 | return ret; |
| 1415 | |
| 1416 | I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, 0); |
| 1417 | |
| 1418 | return 0; |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 1419 | } |
| 1420 | |
| 1421 | static int gen6_do_reset(struct drm_device *dev) |
| 1422 | { |
| 1423 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1424 | int ret; |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 1425 | |
| 1426 | /* Reset the chip */ |
| 1427 | |
| 1428 | /* GEN6_GDRST is not in the gt power well, no need to check |
| 1429 | * for fifo space for the write or forcewake the chip for |
| 1430 | * the read |
| 1431 | */ |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 1432 | __raw_i915_write32(dev_priv, GEN6_GDRST, GEN6_GRDOM_FULL); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 1433 | |
| 1434 | /* Spin waiting for the device to ack the reset request */ |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 1435 | ret = wait_for((__raw_i915_read32(dev_priv, GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 1436 | |
Chris Wilson | 0294ae7 | 2014-03-13 12:00:29 +0000 | [diff] [blame] | 1437 | intel_uncore_forcewake_reset(dev, true); |
Mika Kuoppala | 521198a | 2013-08-23 16:52:30 +0300 | [diff] [blame] | 1438 | |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 1439 | return ret; |
| 1440 | } |
| 1441 | |
| 1442 | int intel_gpu_reset(struct drm_device *dev) |
| 1443 | { |
Robert Beckett | 542c184 | 2014-06-03 10:08:26 +0200 | [diff] [blame] | 1444 | if (INTEL_INFO(dev)->gen >= 6) |
| 1445 | return gen6_do_reset(dev); |
| 1446 | else if (IS_GEN5(dev)) |
| 1447 | return ironlake_do_reset(dev); |
| 1448 | else if (IS_G4X(dev)) |
| 1449 | return g4x_do_reset(dev); |
Ville Syrjälä | 408d4b9 | 2014-11-21 21:54:28 +0200 | [diff] [blame] | 1450 | else if (IS_G33(dev)) |
| 1451 | return g33_do_reset(dev); |
| 1452 | else if (INTEL_INFO(dev)->gen >= 3) |
Ville Syrjälä | 59ea905 | 2014-11-21 21:54:27 +0200 | [diff] [blame] | 1453 | return i915_do_reset(dev); |
Robert Beckett | 542c184 | 2014-06-03 10:08:26 +0200 | [diff] [blame] | 1454 | else |
| 1455 | return -ENODEV; |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 1456 | } |
| 1457 | |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 1458 | void intel_uncore_check_errors(struct drm_device *dev) |
| 1459 | { |
| 1460 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1461 | |
| 1462 | if (HAS_FPGA_DBG_UNCLAIMED(dev) && |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 1463 | (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) { |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 1464 | DRM_ERROR("Unclaimed register before interrupt\n"); |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 1465 | __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 1466 | } |
| 1467 | } |