Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved. |
Jack Morgenstein | 51a379d | 2008-07-25 10:32:52 -0700 | [diff] [blame] | 3 | * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved. |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 4 | * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved. |
| 5 | * |
| 6 | * This software is available to you under a choice of one of two |
| 7 | * licenses. You may choose to be licensed under the terms of the GNU |
| 8 | * General Public License (GPL) Version 2, available from the file |
| 9 | * COPYING in the main directory of this source tree, or the |
| 10 | * OpenIB.org BSD license below: |
| 11 | * |
| 12 | * Redistribution and use in source and binary forms, with or |
| 13 | * without modification, are permitted provided that the following |
| 14 | * conditions are met: |
| 15 | * |
| 16 | * - Redistributions of source code must retain the above |
| 17 | * copyright notice, this list of conditions and the following |
| 18 | * disclaimer. |
| 19 | * |
| 20 | * - Redistributions in binary form must reproduce the above |
| 21 | * copyright notice, this list of conditions and the following |
| 22 | * disclaimer in the documentation and/or other materials |
| 23 | * provided with the distribution. |
| 24 | * |
| 25 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
| 26 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| 27 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
| 28 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS |
| 29 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN |
| 30 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN |
| 31 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
| 32 | * SOFTWARE. |
| 33 | */ |
| 34 | |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 35 | #include <linux/etherdevice.h> |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 36 | #include <linux/mlx4/cmd.h> |
Paul Gortmaker | 9d9779e | 2011-07-03 15:21:01 -0400 | [diff] [blame] | 37 | #include <linux/module.h> |
Eli Cohen | c57e20dcf | 2009-09-24 11:03:03 -0700 | [diff] [blame] | 38 | #include <linux/cache.h> |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 39 | |
| 40 | #include "fw.h" |
| 41 | #include "icm.h" |
| 42 | |
Roland Dreier | fe40900 | 2007-06-07 23:24:36 -0700 | [diff] [blame] | 43 | enum { |
Roland Dreier | 5ae2a7a | 2007-06-18 08:15:02 -0700 | [diff] [blame] | 44 | MLX4_COMMAND_INTERFACE_MIN_REV = 2, |
| 45 | MLX4_COMMAND_INTERFACE_MAX_REV = 3, |
| 46 | MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS = 3, |
Roland Dreier | fe40900 | 2007-06-07 23:24:36 -0700 | [diff] [blame] | 47 | }; |
| 48 | |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 49 | extern void __buggy_use_of_MLX4_GET(void); |
| 50 | extern void __buggy_use_of_MLX4_PUT(void); |
| 51 | |
Rusty Russell | eb93992 | 2011-12-19 14:08:01 +0000 | [diff] [blame] | 52 | static bool enable_qos; |
Jack Morgenstein | 51f5f0e | 2008-07-22 14:19:37 -0700 | [diff] [blame] | 53 | module_param(enable_qos, bool, 0444); |
| 54 | MODULE_PARM_DESC(enable_qos, "Enable Quality of Service support in the HCA (default: off)"); |
| 55 | |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 56 | #define MLX4_GET(dest, source, offset) \ |
| 57 | do { \ |
| 58 | void *__p = (char *) (source) + (offset); \ |
| 59 | switch (sizeof (dest)) { \ |
| 60 | case 1: (dest) = *(u8 *) __p; break; \ |
| 61 | case 2: (dest) = be16_to_cpup(__p); break; \ |
| 62 | case 4: (dest) = be32_to_cpup(__p); break; \ |
| 63 | case 8: (dest) = be64_to_cpup(__p); break; \ |
| 64 | default: __buggy_use_of_MLX4_GET(); \ |
| 65 | } \ |
| 66 | } while (0) |
| 67 | |
| 68 | #define MLX4_PUT(dest, source, offset) \ |
| 69 | do { \ |
| 70 | void *__d = ((char *) (dest) + (offset)); \ |
| 71 | switch (sizeof(source)) { \ |
| 72 | case 1: *(u8 *) __d = (source); break; \ |
| 73 | case 2: *(__be16 *) __d = cpu_to_be16(source); break; \ |
| 74 | case 4: *(__be32 *) __d = cpu_to_be32(source); break; \ |
| 75 | case 8: *(__be64 *) __d = cpu_to_be64(source); break; \ |
| 76 | default: __buggy_use_of_MLX4_PUT(); \ |
| 77 | } \ |
| 78 | } while (0) |
| 79 | |
Or Gerlitz | 52eafc6 | 2011-06-15 14:41:42 +0000 | [diff] [blame] | 80 | static void dump_dev_cap_flags(struct mlx4_dev *dev, u64 flags) |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 81 | { |
| 82 | static const char *fname[] = { |
| 83 | [ 0] = "RC transport", |
| 84 | [ 1] = "UC transport", |
| 85 | [ 2] = "UD transport", |
Roland Dreier | ea98054 | 2007-10-09 19:59:13 -0700 | [diff] [blame] | 86 | [ 3] = "XRC transport", |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 87 | [ 4] = "reliable multicast", |
| 88 | [ 5] = "FCoIB support", |
| 89 | [ 6] = "SRQ support", |
| 90 | [ 7] = "IPoIB checksum offload", |
| 91 | [ 8] = "P_Key violation counter", |
| 92 | [ 9] = "Q_Key violation counter", |
| 93 | [10] = "VMM", |
Or Gerlitz | 4d531aa | 2013-04-07 03:44:06 +0000 | [diff] [blame] | 94 | [12] = "Dual Port Different Protocol (DPDP) support", |
Eli Cohen | 417608c | 2009-11-12 11:19:44 -0800 | [diff] [blame] | 95 | [15] = "Big LSO headers", |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 96 | [16] = "MW support", |
| 97 | [17] = "APM support", |
| 98 | [18] = "Atomic ops support", |
| 99 | [19] = "Raw multicast support", |
| 100 | [20] = "Address vector port checking support", |
| 101 | [21] = "UD multicast support", |
| 102 | [24] = "Demand paging support", |
Eli Cohen | 96dfa68 | 2010-10-20 21:57:02 -0700 | [diff] [blame] | 103 | [25] = "Router support", |
Or Gerlitz | ccf8632 | 2011-07-07 19:19:29 +0000 | [diff] [blame] | 104 | [30] = "IBoE support", |
| 105 | [32] = "Unicast loopback support", |
Yevgeny Petrilin | f3a9d1f | 2011-10-18 01:50:42 +0000 | [diff] [blame] | 106 | [34] = "FCS header control", |
Or Gerlitz | ccf8632 | 2011-07-07 19:19:29 +0000 | [diff] [blame] | 107 | [38] = "Wake On LAN support", |
| 108 | [40] = "UDP RSS support", |
| 109 | [41] = "Unicast VEP steering support", |
Or Gerlitz | f2a3f6a | 2011-06-15 14:47:14 +0000 | [diff] [blame] | 110 | [42] = "Multicast VEP steering support", |
| 111 | [48] = "Counters support", |
Or Gerlitz | 540b3a3 | 2013-04-07 03:44:07 +0000 | [diff] [blame] | 112 | [53] = "Port ETS Scheduler support", |
Or Gerlitz | 4d531aa | 2013-04-07 03:44:06 +0000 | [diff] [blame] | 113 | [55] = "Port link type sensing support", |
Jack Morgenstein | 00f5ce9 | 2012-06-19 11:21:40 +0300 | [diff] [blame] | 114 | [59] = "Port management change event support", |
Or Gerlitz | 08ff323 | 2012-10-21 14:59:24 +0000 | [diff] [blame] | 115 | [61] = "64 byte EQE support", |
| 116 | [62] = "64 byte CQE support", |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 117 | }; |
| 118 | int i; |
| 119 | |
| 120 | mlx4_dbg(dev, "DEV_CAP flags:\n"); |
Roland Dreier | 23c15c2 | 2007-05-19 08:51:57 -0700 | [diff] [blame] | 121 | for (i = 0; i < ARRAY_SIZE(fname); ++i) |
Or Gerlitz | 52eafc6 | 2011-06-15 14:41:42 +0000 | [diff] [blame] | 122 | if (fname[i] && (flags & (1LL << i))) |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 123 | mlx4_dbg(dev, " %s\n", fname[i]); |
| 124 | } |
| 125 | |
Shlomo Pongratz | b3416f4 | 2012-04-29 17:04:25 +0300 | [diff] [blame] | 126 | static void dump_dev_cap_flags2(struct mlx4_dev *dev, u64 flags) |
| 127 | { |
| 128 | static const char * const fname[] = { |
| 129 | [0] = "RSS support", |
| 130 | [1] = "RSS Toeplitz Hash Function support", |
Hadar Hen Zion | 0ff1fb6 | 2012-07-05 04:03:46 +0000 | [diff] [blame] | 131 | [2] = "RSS XOR Hash Function support", |
Or Gerlitz | 56cb456 | 2014-03-12 17:16:30 +0200 | [diff] [blame] | 132 | [3] = "Device managed flow steering support", |
Eugenia Emantayev | d998735 | 2013-04-23 06:06:47 +0000 | [diff] [blame] | 133 | [4] = "Automatic MAC reassignment support", |
Or Gerlitz | 4e8cf5b | 2013-05-08 22:22:34 +0000 | [diff] [blame] | 134 | [5] = "Time stamping support", |
| 135 | [6] = "VST (control vlan insertion/stripping) support", |
Jack Morgenstein | b01978c | 2013-06-27 19:05:21 +0300 | [diff] [blame] | 136 | [7] = "FSM (MAC anti-spoofing) support", |
Or Gerlitz | 7ffdf72 | 2013-12-23 16:09:43 +0200 | [diff] [blame] | 137 | [8] = "Dynamic QP updates support", |
Or Gerlitz | 56cb456 | 2014-03-12 17:16:30 +0200 | [diff] [blame] | 138 | [9] = "Device managed flow steering IPoIB support", |
Jack Morgenstein | 114840c | 2014-06-01 11:53:50 +0300 | [diff] [blame] | 139 | [10] = "TCP/IP offloads/flow-steering for VXLAN support", |
| 140 | [11] = "MAD DEMUX (Secure-Host) support" |
Shlomo Pongratz | b3416f4 | 2012-04-29 17:04:25 +0300 | [diff] [blame] | 141 | }; |
| 142 | int i; |
| 143 | |
| 144 | for (i = 0; i < ARRAY_SIZE(fname); ++i) |
| 145 | if (fname[i] && (flags & (1LL << i))) |
| 146 | mlx4_dbg(dev, " %s\n", fname[i]); |
| 147 | } |
| 148 | |
Vladimir Sokolovsky | 2d92865 | 2008-07-14 23:48:53 -0700 | [diff] [blame] | 149 | int mlx4_MOD_STAT_CFG(struct mlx4_dev *dev, struct mlx4_mod_stat_cfg *cfg) |
| 150 | { |
| 151 | struct mlx4_cmd_mailbox *mailbox; |
| 152 | u32 *inbox; |
| 153 | int err = 0; |
| 154 | |
| 155 | #define MOD_STAT_CFG_IN_SIZE 0x100 |
| 156 | |
| 157 | #define MOD_STAT_CFG_PG_SZ_M_OFFSET 0x002 |
| 158 | #define MOD_STAT_CFG_PG_SZ_OFFSET 0x003 |
| 159 | |
| 160 | mailbox = mlx4_alloc_cmd_mailbox(dev); |
| 161 | if (IS_ERR(mailbox)) |
| 162 | return PTR_ERR(mailbox); |
| 163 | inbox = mailbox->buf; |
| 164 | |
Vladimir Sokolovsky | 2d92865 | 2008-07-14 23:48:53 -0700 | [diff] [blame] | 165 | MLX4_PUT(inbox, cfg->log_pg_sz, MOD_STAT_CFG_PG_SZ_OFFSET); |
| 166 | MLX4_PUT(inbox, cfg->log_pg_sz_m, MOD_STAT_CFG_PG_SZ_M_OFFSET); |
| 167 | |
| 168 | err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_MOD_STAT_CFG, |
Jack Morgenstein | f9baff5 | 2011-12-13 04:10:51 +0000 | [diff] [blame] | 169 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); |
Vladimir Sokolovsky | 2d92865 | 2008-07-14 23:48:53 -0700 | [diff] [blame] | 170 | |
| 171 | mlx4_free_cmd_mailbox(dev, mailbox); |
| 172 | return err; |
| 173 | } |
| 174 | |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 175 | int mlx4_QUERY_FUNC_CAP_wrapper(struct mlx4_dev *dev, int slave, |
| 176 | struct mlx4_vhcr *vhcr, |
| 177 | struct mlx4_cmd_mailbox *inbox, |
| 178 | struct mlx4_cmd_mailbox *outbox, |
| 179 | struct mlx4_cmd_info *cmd) |
| 180 | { |
Jack Morgenstein | 5a0d0a6 | 2013-11-03 10:03:23 +0200 | [diff] [blame] | 181 | struct mlx4_priv *priv = mlx4_priv(dev); |
Jack Morgenstein | 99ec41d | 2014-05-29 16:31:03 +0300 | [diff] [blame] | 182 | u8 field, port; |
| 183 | u32 size, proxy_qp, qkey; |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 184 | int err = 0; |
| 185 | |
| 186 | #define QUERY_FUNC_CAP_FLAGS_OFFSET 0x0 |
| 187 | #define QUERY_FUNC_CAP_NUM_PORTS_OFFSET 0x1 |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 188 | #define QUERY_FUNC_CAP_PF_BHVR_OFFSET 0x4 |
Jack Morgenstein | 105c320 | 2012-06-19 11:21:43 +0300 | [diff] [blame] | 189 | #define QUERY_FUNC_CAP_FMR_OFFSET 0x8 |
Jack Morgenstein | eb456a6 | 2013-11-03 10:03:24 +0200 | [diff] [blame] | 190 | #define QUERY_FUNC_CAP_QP_QUOTA_OFFSET_DEP 0x10 |
| 191 | #define QUERY_FUNC_CAP_CQ_QUOTA_OFFSET_DEP 0x14 |
| 192 | #define QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET_DEP 0x18 |
| 193 | #define QUERY_FUNC_CAP_MPT_QUOTA_OFFSET_DEP 0x20 |
| 194 | #define QUERY_FUNC_CAP_MTT_QUOTA_OFFSET_DEP 0x24 |
| 195 | #define QUERY_FUNC_CAP_MCG_QUOTA_OFFSET_DEP 0x28 |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 196 | #define QUERY_FUNC_CAP_MAX_EQ_OFFSET 0x2c |
Roland Dreier | 69612b9 | 2012-09-23 09:18:24 -0700 | [diff] [blame] | 197 | #define QUERY_FUNC_CAP_RESERVED_EQ_OFFSET 0x30 |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 198 | |
Jack Morgenstein | eb456a6 | 2013-11-03 10:03:24 +0200 | [diff] [blame] | 199 | #define QUERY_FUNC_CAP_QP_QUOTA_OFFSET 0x50 |
| 200 | #define QUERY_FUNC_CAP_CQ_QUOTA_OFFSET 0x54 |
| 201 | #define QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET 0x58 |
| 202 | #define QUERY_FUNC_CAP_MPT_QUOTA_OFFSET 0x60 |
| 203 | #define QUERY_FUNC_CAP_MTT_QUOTA_OFFSET 0x64 |
| 204 | #define QUERY_FUNC_CAP_MCG_QUOTA_OFFSET 0x68 |
| 205 | |
Jack Morgenstein | 105c320 | 2012-06-19 11:21:43 +0300 | [diff] [blame] | 206 | #define QUERY_FUNC_CAP_FMR_FLAG 0x80 |
| 207 | #define QUERY_FUNC_CAP_FLAG_RDMA 0x40 |
| 208 | #define QUERY_FUNC_CAP_FLAG_ETH 0x80 |
Jack Morgenstein | eb456a6 | 2013-11-03 10:03:24 +0200 | [diff] [blame] | 209 | #define QUERY_FUNC_CAP_FLAG_QUOTAS 0x10 |
Jack Morgenstein | 105c320 | 2012-06-19 11:21:43 +0300 | [diff] [blame] | 210 | |
| 211 | /* when opcode modifier = 1 */ |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 212 | #define QUERY_FUNC_CAP_PHYS_PORT_OFFSET 0x3 |
Jack Morgenstein | 99ec41d | 2014-05-29 16:31:03 +0300 | [diff] [blame] | 213 | #define QUERY_FUNC_CAP_PRIV_VF_QKEY_OFFSET 0x4 |
Hadar Hen Zion | 73e74ab | 2013-12-19 21:20:10 +0200 | [diff] [blame] | 214 | #define QUERY_FUNC_CAP_FLAGS0_OFFSET 0x8 |
| 215 | #define QUERY_FUNC_CAP_FLAGS1_OFFSET 0xc |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 216 | |
Jack Morgenstein | 47605df | 2012-08-03 08:40:57 +0000 | [diff] [blame] | 217 | #define QUERY_FUNC_CAP_QP0_TUNNEL 0x10 |
| 218 | #define QUERY_FUNC_CAP_QP0_PROXY 0x14 |
| 219 | #define QUERY_FUNC_CAP_QP1_TUNNEL 0x18 |
| 220 | #define QUERY_FUNC_CAP_QP1_PROXY 0x1c |
Hadar Hen Zion | 8e1a28e | 2013-12-19 21:20:12 +0200 | [diff] [blame] | 221 | #define QUERY_FUNC_CAP_PHYS_PORT_ID 0x28 |
Jack Morgenstein | 47605df | 2012-08-03 08:40:57 +0000 | [diff] [blame] | 222 | |
Hadar Hen Zion | 73e74ab | 2013-12-19 21:20:10 +0200 | [diff] [blame] | 223 | #define QUERY_FUNC_CAP_FLAGS1_FORCE_MAC 0x40 |
| 224 | #define QUERY_FUNC_CAP_FLAGS1_FORCE_VLAN 0x80 |
Hadar Hen Zion | eb17711 | 2013-12-19 21:20:11 +0200 | [diff] [blame] | 225 | #define QUERY_FUNC_CAP_FLAGS1_NIC_INFO 0x10 |
Jack Morgenstein | 99ec41d | 2014-05-29 16:31:03 +0300 | [diff] [blame] | 226 | #define QUERY_FUNC_CAP_VF_ENABLE_QP0 0x08 |
Jack Morgenstein | 105c320 | 2012-06-19 11:21:43 +0300 | [diff] [blame] | 227 | |
Hadar Hen Zion | 73e74ab | 2013-12-19 21:20:10 +0200 | [diff] [blame] | 228 | #define QUERY_FUNC_CAP_FLAGS0_FORCE_PHY_WQE_GID 0x80 |
Jack Morgenstein | 105c320 | 2012-06-19 11:21:43 +0300 | [diff] [blame] | 229 | |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 230 | if (vhcr->op_modifier == 1) { |
Matan Barak | 449fc48 | 2014-03-19 18:11:52 +0200 | [diff] [blame] | 231 | struct mlx4_active_ports actv_ports = |
| 232 | mlx4_get_active_ports(dev, slave); |
| 233 | int converted_port = mlx4_slave_convert_port( |
| 234 | dev, slave, vhcr->in_modifier); |
| 235 | |
| 236 | if (converted_port < 0) |
| 237 | return -EINVAL; |
| 238 | |
| 239 | vhcr->in_modifier = converted_port; |
Matan Barak | 449fc48 | 2014-03-19 18:11:52 +0200 | [diff] [blame] | 240 | /* phys-port = logical-port */ |
| 241 | field = vhcr->in_modifier - |
| 242 | find_first_bit(actv_ports.ports, dev->caps.num_ports); |
Jack Morgenstein | 47605df | 2012-08-03 08:40:57 +0000 | [diff] [blame] | 243 | MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_PHYS_PORT_OFFSET); |
| 244 | |
Jack Morgenstein | 99ec41d | 2014-05-29 16:31:03 +0300 | [diff] [blame] | 245 | port = vhcr->in_modifier; |
| 246 | proxy_qp = dev->phys_caps.base_proxy_sqpn + 8 * slave + port - 1; |
| 247 | |
| 248 | /* Set nic_info bit to mark new fields support */ |
| 249 | field = QUERY_FUNC_CAP_FLAGS1_NIC_INFO; |
| 250 | |
| 251 | if (mlx4_vf_smi_enabled(dev, slave, port) && |
| 252 | !mlx4_get_parav_qkey(dev, proxy_qp, &qkey)) { |
| 253 | field |= QUERY_FUNC_CAP_VF_ENABLE_QP0; |
| 254 | MLX4_PUT(outbox->buf, qkey, |
| 255 | QUERY_FUNC_CAP_PRIV_VF_QKEY_OFFSET); |
| 256 | } |
| 257 | MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FLAGS1_OFFSET); |
| 258 | |
Jack Morgenstein | 47605df | 2012-08-03 08:40:57 +0000 | [diff] [blame] | 259 | /* size is now the QP number */ |
Jack Morgenstein | 99ec41d | 2014-05-29 16:31:03 +0300 | [diff] [blame] | 260 | size = dev->phys_caps.base_tunnel_sqpn + 8 * slave + port - 1; |
Jack Morgenstein | 47605df | 2012-08-03 08:40:57 +0000 | [diff] [blame] | 261 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP0_TUNNEL); |
| 262 | |
| 263 | size += 2; |
| 264 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP1_TUNNEL); |
| 265 | |
Jack Morgenstein | 99ec41d | 2014-05-29 16:31:03 +0300 | [diff] [blame] | 266 | MLX4_PUT(outbox->buf, proxy_qp, QUERY_FUNC_CAP_QP0_PROXY); |
| 267 | proxy_qp += 2; |
| 268 | MLX4_PUT(outbox->buf, proxy_qp, QUERY_FUNC_CAP_QP1_PROXY); |
Jack Morgenstein | 47605df | 2012-08-03 08:40:57 +0000 | [diff] [blame] | 269 | |
Hadar Hen Zion | 8e1a28e | 2013-12-19 21:20:12 +0200 | [diff] [blame] | 270 | MLX4_PUT(outbox->buf, dev->caps.phys_port_id[vhcr->in_modifier], |
| 271 | QUERY_FUNC_CAP_PHYS_PORT_ID); |
| 272 | |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 273 | } else if (vhcr->op_modifier == 0) { |
Matan Barak | 449fc48 | 2014-03-19 18:11:52 +0200 | [diff] [blame] | 274 | struct mlx4_active_ports actv_ports = |
| 275 | mlx4_get_active_ports(dev, slave); |
Jack Morgenstein | eb456a6 | 2013-11-03 10:03:24 +0200 | [diff] [blame] | 276 | /* enable rdma and ethernet interfaces, and new quota locations */ |
| 277 | field = (QUERY_FUNC_CAP_FLAG_ETH | QUERY_FUNC_CAP_FLAG_RDMA | |
| 278 | QUERY_FUNC_CAP_FLAG_QUOTAS); |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 279 | MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FLAGS_OFFSET); |
| 280 | |
Matan Barak | 449fc48 | 2014-03-19 18:11:52 +0200 | [diff] [blame] | 281 | field = min( |
| 282 | bitmap_weight(actv_ports.ports, dev->caps.num_ports), |
| 283 | dev->caps.num_ports); |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 284 | MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_NUM_PORTS_OFFSET); |
| 285 | |
Or Gerlitz | 08ff323 | 2012-10-21 14:59:24 +0000 | [diff] [blame] | 286 | size = dev->caps.function_caps; /* set PF behaviours */ |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 287 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_PF_BHVR_OFFSET); |
| 288 | |
Jack Morgenstein | 105c320 | 2012-06-19 11:21:43 +0300 | [diff] [blame] | 289 | field = 0; /* protected FMR support not available as yet */ |
| 290 | MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FMR_OFFSET); |
| 291 | |
Jack Morgenstein | 5a0d0a6 | 2013-11-03 10:03:23 +0200 | [diff] [blame] | 292 | size = priv->mfunc.master.res_tracker.res_alloc[RES_QP].quota[slave]; |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 293 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP_QUOTA_OFFSET); |
Jack Morgenstein | eb456a6 | 2013-11-03 10:03:24 +0200 | [diff] [blame] | 294 | size = dev->caps.num_qps; |
| 295 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP_QUOTA_OFFSET_DEP); |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 296 | |
Jack Morgenstein | 5a0d0a6 | 2013-11-03 10:03:23 +0200 | [diff] [blame] | 297 | size = priv->mfunc.master.res_tracker.res_alloc[RES_SRQ].quota[slave]; |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 298 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET); |
Jack Morgenstein | eb456a6 | 2013-11-03 10:03:24 +0200 | [diff] [blame] | 299 | size = dev->caps.num_srqs; |
| 300 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET_DEP); |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 301 | |
Jack Morgenstein | 5a0d0a6 | 2013-11-03 10:03:23 +0200 | [diff] [blame] | 302 | size = priv->mfunc.master.res_tracker.res_alloc[RES_CQ].quota[slave]; |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 303 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET); |
Jack Morgenstein | eb456a6 | 2013-11-03 10:03:24 +0200 | [diff] [blame] | 304 | size = dev->caps.num_cqs; |
| 305 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET_DEP); |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 306 | |
| 307 | size = dev->caps.num_eqs; |
| 308 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MAX_EQ_OFFSET); |
| 309 | |
| 310 | size = dev->caps.reserved_eqs; |
| 311 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET); |
| 312 | |
Jack Morgenstein | 5a0d0a6 | 2013-11-03 10:03:23 +0200 | [diff] [blame] | 313 | size = priv->mfunc.master.res_tracker.res_alloc[RES_MPT].quota[slave]; |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 314 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET); |
Jack Morgenstein | eb456a6 | 2013-11-03 10:03:24 +0200 | [diff] [blame] | 315 | size = dev->caps.num_mpts; |
| 316 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET_DEP); |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 317 | |
Jack Morgenstein | 5a0d0a6 | 2013-11-03 10:03:23 +0200 | [diff] [blame] | 318 | size = priv->mfunc.master.res_tracker.res_alloc[RES_MTT].quota[slave]; |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 319 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET); |
Jack Morgenstein | eb456a6 | 2013-11-03 10:03:24 +0200 | [diff] [blame] | 320 | size = dev->caps.num_mtts; |
| 321 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET_DEP); |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 322 | |
| 323 | size = dev->caps.num_mgms + dev->caps.num_amgms; |
| 324 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET); |
Jack Morgenstein | eb456a6 | 2013-11-03 10:03:24 +0200 | [diff] [blame] | 325 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET_DEP); |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 326 | |
| 327 | } else |
| 328 | err = -EINVAL; |
| 329 | |
| 330 | return err; |
| 331 | } |
| 332 | |
Jack Morgenstein | 47605df | 2012-08-03 08:40:57 +0000 | [diff] [blame] | 333 | int mlx4_QUERY_FUNC_CAP(struct mlx4_dev *dev, u32 gen_or_port, |
| 334 | struct mlx4_func_cap *func_cap) |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 335 | { |
| 336 | struct mlx4_cmd_mailbox *mailbox; |
| 337 | u32 *outbox; |
Jack Morgenstein | 47605df | 2012-08-03 08:40:57 +0000 | [diff] [blame] | 338 | u8 field, op_modifier; |
Jack Morgenstein | 99ec41d | 2014-05-29 16:31:03 +0300 | [diff] [blame] | 339 | u32 size, qkey; |
Jack Morgenstein | eb456a6 | 2013-11-03 10:03:24 +0200 | [diff] [blame] | 340 | int err = 0, quotas = 0; |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 341 | |
Jack Morgenstein | 47605df | 2012-08-03 08:40:57 +0000 | [diff] [blame] | 342 | op_modifier = !!gen_or_port; /* 0 = general, 1 = logical port */ |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 343 | |
| 344 | mailbox = mlx4_alloc_cmd_mailbox(dev); |
| 345 | if (IS_ERR(mailbox)) |
| 346 | return PTR_ERR(mailbox); |
| 347 | |
Jack Morgenstein | 47605df | 2012-08-03 08:40:57 +0000 | [diff] [blame] | 348 | err = mlx4_cmd_box(dev, 0, mailbox->dma, gen_or_port, op_modifier, |
| 349 | MLX4_CMD_QUERY_FUNC_CAP, |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 350 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED); |
| 351 | if (err) |
| 352 | goto out; |
| 353 | |
| 354 | outbox = mailbox->buf; |
| 355 | |
Jack Morgenstein | 47605df | 2012-08-03 08:40:57 +0000 | [diff] [blame] | 356 | if (!op_modifier) { |
| 357 | MLX4_GET(field, outbox, QUERY_FUNC_CAP_FLAGS_OFFSET); |
| 358 | if (!(field & (QUERY_FUNC_CAP_FLAG_ETH | QUERY_FUNC_CAP_FLAG_RDMA))) { |
| 359 | mlx4_err(dev, "The host supports neither eth nor rdma interfaces\n"); |
| 360 | err = -EPROTONOSUPPORT; |
| 361 | goto out; |
| 362 | } |
| 363 | func_cap->flags = field; |
Jack Morgenstein | eb456a6 | 2013-11-03 10:03:24 +0200 | [diff] [blame] | 364 | quotas = !!(func_cap->flags & QUERY_FUNC_CAP_FLAG_QUOTAS); |
Jack Morgenstein | 47605df | 2012-08-03 08:40:57 +0000 | [diff] [blame] | 365 | |
| 366 | MLX4_GET(field, outbox, QUERY_FUNC_CAP_NUM_PORTS_OFFSET); |
| 367 | func_cap->num_ports = field; |
| 368 | |
| 369 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_PF_BHVR_OFFSET); |
| 370 | func_cap->pf_context_behaviour = size; |
| 371 | |
Jack Morgenstein | eb456a6 | 2013-11-03 10:03:24 +0200 | [diff] [blame] | 372 | if (quotas) { |
| 373 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP_QUOTA_OFFSET); |
| 374 | func_cap->qp_quota = size & 0xFFFFFF; |
Jack Morgenstein | 47605df | 2012-08-03 08:40:57 +0000 | [diff] [blame] | 375 | |
Jack Morgenstein | eb456a6 | 2013-11-03 10:03:24 +0200 | [diff] [blame] | 376 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET); |
| 377 | func_cap->srq_quota = size & 0xFFFFFF; |
Jack Morgenstein | 47605df | 2012-08-03 08:40:57 +0000 | [diff] [blame] | 378 | |
Jack Morgenstein | eb456a6 | 2013-11-03 10:03:24 +0200 | [diff] [blame] | 379 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET); |
| 380 | func_cap->cq_quota = size & 0xFFFFFF; |
Jack Morgenstein | 47605df | 2012-08-03 08:40:57 +0000 | [diff] [blame] | 381 | |
Jack Morgenstein | eb456a6 | 2013-11-03 10:03:24 +0200 | [diff] [blame] | 382 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET); |
| 383 | func_cap->mpt_quota = size & 0xFFFFFF; |
| 384 | |
| 385 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET); |
| 386 | func_cap->mtt_quota = size & 0xFFFFFF; |
| 387 | |
| 388 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET); |
| 389 | func_cap->mcg_quota = size & 0xFFFFFF; |
| 390 | |
| 391 | } else { |
| 392 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP_QUOTA_OFFSET_DEP); |
| 393 | func_cap->qp_quota = size & 0xFFFFFF; |
| 394 | |
| 395 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET_DEP); |
| 396 | func_cap->srq_quota = size & 0xFFFFFF; |
| 397 | |
| 398 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET_DEP); |
| 399 | func_cap->cq_quota = size & 0xFFFFFF; |
| 400 | |
| 401 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET_DEP); |
| 402 | func_cap->mpt_quota = size & 0xFFFFFF; |
| 403 | |
| 404 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET_DEP); |
| 405 | func_cap->mtt_quota = size & 0xFFFFFF; |
| 406 | |
| 407 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET_DEP); |
| 408 | func_cap->mcg_quota = size & 0xFFFFFF; |
| 409 | } |
Jack Morgenstein | 47605df | 2012-08-03 08:40:57 +0000 | [diff] [blame] | 410 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_MAX_EQ_OFFSET); |
| 411 | func_cap->max_eq = size & 0xFFFFFF; |
| 412 | |
| 413 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET); |
| 414 | func_cap->reserved_eq = size & 0xFFFFFF; |
| 415 | |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 416 | goto out; |
| 417 | } |
| 418 | |
Jack Morgenstein | 47605df | 2012-08-03 08:40:57 +0000 | [diff] [blame] | 419 | /* logical port query */ |
| 420 | if (gen_or_port > dev->caps.num_ports) { |
| 421 | err = -EINVAL; |
| 422 | goto out; |
| 423 | } |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 424 | |
Hadar Hen Zion | eb17711 | 2013-12-19 21:20:11 +0200 | [diff] [blame] | 425 | MLX4_GET(func_cap->flags1, outbox, QUERY_FUNC_CAP_FLAGS1_OFFSET); |
Jack Morgenstein | 47605df | 2012-08-03 08:40:57 +0000 | [diff] [blame] | 426 | if (dev->caps.port_type[gen_or_port] == MLX4_PORT_TYPE_ETH) { |
Jack Morgenstein | bc82878 | 2014-05-29 16:31:00 +0300 | [diff] [blame] | 427 | if (func_cap->flags1 & QUERY_FUNC_CAP_FLAGS1_FORCE_VLAN) { |
Jack Morgenstein | 47605df | 2012-08-03 08:40:57 +0000 | [diff] [blame] | 428 | mlx4_err(dev, "VLAN is enforced on this port\n"); |
| 429 | err = -EPROTONOSUPPORT; |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 430 | goto out; |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 431 | } |
| 432 | |
Hadar Hen Zion | eb17711 | 2013-12-19 21:20:11 +0200 | [diff] [blame] | 433 | if (func_cap->flags1 & QUERY_FUNC_CAP_FLAGS1_FORCE_MAC) { |
Jack Morgenstein | 47605df | 2012-08-03 08:40:57 +0000 | [diff] [blame] | 434 | mlx4_err(dev, "Force mac is enabled on this port\n"); |
| 435 | err = -EPROTONOSUPPORT; |
| 436 | goto out; |
| 437 | } |
| 438 | } else if (dev->caps.port_type[gen_or_port] == MLX4_PORT_TYPE_IB) { |
Hadar Hen Zion | 73e74ab | 2013-12-19 21:20:10 +0200 | [diff] [blame] | 439 | MLX4_GET(field, outbox, QUERY_FUNC_CAP_FLAGS0_OFFSET); |
| 440 | if (field & QUERY_FUNC_CAP_FLAGS0_FORCE_PHY_WQE_GID) { |
Joe Perches | 1a91de2 | 2014-05-07 12:52:57 -0700 | [diff] [blame] | 441 | mlx4_err(dev, "phy_wqe_gid is enforced on this ib port\n"); |
Jack Morgenstein | 47605df | 2012-08-03 08:40:57 +0000 | [diff] [blame] | 442 | err = -EPROTONOSUPPORT; |
| 443 | goto out; |
| 444 | } |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 445 | } |
| 446 | |
Jack Morgenstein | 47605df | 2012-08-03 08:40:57 +0000 | [diff] [blame] | 447 | MLX4_GET(field, outbox, QUERY_FUNC_CAP_PHYS_PORT_OFFSET); |
| 448 | func_cap->physical_port = field; |
| 449 | if (func_cap->physical_port != gen_or_port) { |
| 450 | err = -ENOSYS; |
| 451 | goto out; |
| 452 | } |
| 453 | |
Jack Morgenstein | 99ec41d | 2014-05-29 16:31:03 +0300 | [diff] [blame] | 454 | if (func_cap->flags1 & QUERY_FUNC_CAP_VF_ENABLE_QP0) { |
| 455 | MLX4_GET(qkey, outbox, QUERY_FUNC_CAP_PRIV_VF_QKEY_OFFSET); |
| 456 | func_cap->qp0_qkey = qkey; |
| 457 | } else { |
| 458 | func_cap->qp0_qkey = 0; |
| 459 | } |
| 460 | |
Jack Morgenstein | 47605df | 2012-08-03 08:40:57 +0000 | [diff] [blame] | 461 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP0_TUNNEL); |
| 462 | func_cap->qp0_tunnel_qpn = size & 0xFFFFFF; |
| 463 | |
| 464 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP0_PROXY); |
| 465 | func_cap->qp0_proxy_qpn = size & 0xFFFFFF; |
| 466 | |
| 467 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP1_TUNNEL); |
| 468 | func_cap->qp1_tunnel_qpn = size & 0xFFFFFF; |
| 469 | |
| 470 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP1_PROXY); |
| 471 | func_cap->qp1_proxy_qpn = size & 0xFFFFFF; |
| 472 | |
Hadar Hen Zion | 8e1a28e | 2013-12-19 21:20:12 +0200 | [diff] [blame] | 473 | if (func_cap->flags1 & QUERY_FUNC_CAP_FLAGS1_NIC_INFO) |
| 474 | MLX4_GET(func_cap->phys_port_id, outbox, |
| 475 | QUERY_FUNC_CAP_PHYS_PORT_ID); |
| 476 | |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 477 | /* All other resources are allocated by the master, but we still report |
| 478 | * 'num' and 'reserved' capabilities as follows: |
| 479 | * - num remains the maximum resource index |
| 480 | * - 'num - reserved' is the total available objects of a resource, but |
| 481 | * resource indices may be less than 'reserved' |
| 482 | * TODO: set per-resource quotas */ |
| 483 | |
| 484 | out: |
| 485 | mlx4_free_cmd_mailbox(dev, mailbox); |
| 486 | |
| 487 | return err; |
| 488 | } |
| 489 | |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 490 | int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap) |
| 491 | { |
| 492 | struct mlx4_cmd_mailbox *mailbox; |
| 493 | u32 *outbox; |
| 494 | u8 field; |
Or Gerlitz | ccf8632 | 2011-07-07 19:19:29 +0000 | [diff] [blame] | 495 | u32 field32, flags, ext_flags; |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 496 | u16 size; |
| 497 | u16 stat_rate; |
| 498 | int err; |
Roland Dreier | 5ae2a7a | 2007-06-18 08:15:02 -0700 | [diff] [blame] | 499 | int i; |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 500 | |
| 501 | #define QUERY_DEV_CAP_OUT_SIZE 0x100 |
| 502 | #define QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET 0x10 |
| 503 | #define QUERY_DEV_CAP_MAX_QP_SZ_OFFSET 0x11 |
| 504 | #define QUERY_DEV_CAP_RSVD_QP_OFFSET 0x12 |
| 505 | #define QUERY_DEV_CAP_MAX_QP_OFFSET 0x13 |
| 506 | #define QUERY_DEV_CAP_RSVD_SRQ_OFFSET 0x14 |
| 507 | #define QUERY_DEV_CAP_MAX_SRQ_OFFSET 0x15 |
| 508 | #define QUERY_DEV_CAP_RSVD_EEC_OFFSET 0x16 |
| 509 | #define QUERY_DEV_CAP_MAX_EEC_OFFSET 0x17 |
| 510 | #define QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET 0x19 |
| 511 | #define QUERY_DEV_CAP_RSVD_CQ_OFFSET 0x1a |
| 512 | #define QUERY_DEV_CAP_MAX_CQ_OFFSET 0x1b |
| 513 | #define QUERY_DEV_CAP_MAX_MPT_OFFSET 0x1d |
| 514 | #define QUERY_DEV_CAP_RSVD_EQ_OFFSET 0x1e |
| 515 | #define QUERY_DEV_CAP_MAX_EQ_OFFSET 0x1f |
| 516 | #define QUERY_DEV_CAP_RSVD_MTT_OFFSET 0x20 |
| 517 | #define QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET 0x21 |
| 518 | #define QUERY_DEV_CAP_RSVD_MRW_OFFSET 0x22 |
| 519 | #define QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET 0x23 |
| 520 | #define QUERY_DEV_CAP_MAX_AV_OFFSET 0x27 |
| 521 | #define QUERY_DEV_CAP_MAX_REQ_QP_OFFSET 0x29 |
| 522 | #define QUERY_DEV_CAP_MAX_RES_QP_OFFSET 0x2b |
Eli Cohen | b832be1 | 2008-04-16 21:09:27 -0700 | [diff] [blame] | 523 | #define QUERY_DEV_CAP_MAX_GSO_OFFSET 0x2d |
Shlomo Pongratz | b3416f4 | 2012-04-29 17:04:25 +0300 | [diff] [blame] | 524 | #define QUERY_DEV_CAP_RSS_OFFSET 0x2e |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 525 | #define QUERY_DEV_CAP_MAX_RDMA_OFFSET 0x2f |
| 526 | #define QUERY_DEV_CAP_RSZ_SRQ_OFFSET 0x33 |
| 527 | #define QUERY_DEV_CAP_ACK_DELAY_OFFSET 0x35 |
| 528 | #define QUERY_DEV_CAP_MTU_WIDTH_OFFSET 0x36 |
| 529 | #define QUERY_DEV_CAP_VL_PORT_OFFSET 0x37 |
Dotan Barak | 149983af | 2007-06-26 15:55:28 +0300 | [diff] [blame] | 530 | #define QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET 0x38 |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 531 | #define QUERY_DEV_CAP_MAX_GID_OFFSET 0x3b |
| 532 | #define QUERY_DEV_CAP_RATE_SUPPORT_OFFSET 0x3c |
Eugenia Emantayev | d998735 | 2013-04-23 06:06:47 +0000 | [diff] [blame] | 533 | #define QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET 0x3e |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 534 | #define QUERY_DEV_CAP_MAX_PKEY_OFFSET 0x3f |
Or Gerlitz | ccf8632 | 2011-07-07 19:19:29 +0000 | [diff] [blame] | 535 | #define QUERY_DEV_CAP_EXT_FLAGS_OFFSET 0x40 |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 536 | #define QUERY_DEV_CAP_FLAGS_OFFSET 0x44 |
| 537 | #define QUERY_DEV_CAP_RSVD_UAR_OFFSET 0x48 |
| 538 | #define QUERY_DEV_CAP_UAR_SZ_OFFSET 0x49 |
| 539 | #define QUERY_DEV_CAP_PAGE_SZ_OFFSET 0x4b |
| 540 | #define QUERY_DEV_CAP_BF_OFFSET 0x4c |
| 541 | #define QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET 0x4d |
| 542 | #define QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET 0x4e |
| 543 | #define QUERY_DEV_CAP_LOG_MAX_BF_PAGES_OFFSET 0x4f |
| 544 | #define QUERY_DEV_CAP_MAX_SG_SQ_OFFSET 0x51 |
| 545 | #define QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET 0x52 |
| 546 | #define QUERY_DEV_CAP_MAX_SG_RQ_OFFSET 0x55 |
| 547 | #define QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET 0x56 |
| 548 | #define QUERY_DEV_CAP_MAX_QP_MCG_OFFSET 0x61 |
| 549 | #define QUERY_DEV_CAP_RSVD_MCG_OFFSET 0x62 |
| 550 | #define QUERY_DEV_CAP_MAX_MCG_OFFSET 0x63 |
| 551 | #define QUERY_DEV_CAP_RSVD_PD_OFFSET 0x64 |
| 552 | #define QUERY_DEV_CAP_MAX_PD_OFFSET 0x65 |
Linus Torvalds | f470f8d | 2011-11-01 10:51:38 -0700 | [diff] [blame] | 553 | #define QUERY_DEV_CAP_RSVD_XRC_OFFSET 0x66 |
| 554 | #define QUERY_DEV_CAP_MAX_XRC_OFFSET 0x67 |
Or Gerlitz | f2a3f6a | 2011-06-15 14:47:14 +0000 | [diff] [blame] | 555 | #define QUERY_DEV_CAP_MAX_COUNTERS_OFFSET 0x68 |
Rony Efraim | 3f7fb02 | 2013-04-25 05:22:28 +0000 | [diff] [blame] | 556 | #define QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET 0x70 |
Matan Barak | 4de6580 | 2013-11-07 15:25:14 +0200 | [diff] [blame] | 557 | #define QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET 0x74 |
Hadar Hen Zion | 0ff1fb6 | 2012-07-05 04:03:46 +0000 | [diff] [blame] | 558 | #define QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET 0x76 |
| 559 | #define QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET 0x77 |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 560 | #define QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET 0x80 |
| 561 | #define QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET 0x82 |
| 562 | #define QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET 0x84 |
| 563 | #define QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET 0x86 |
| 564 | #define QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET 0x88 |
| 565 | #define QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET 0x8a |
| 566 | #define QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET 0x8c |
| 567 | #define QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET 0x8e |
| 568 | #define QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET 0x90 |
| 569 | #define QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET 0x92 |
Roland Dreier | 95d04f0 | 2008-07-23 08:12:26 -0700 | [diff] [blame] | 570 | #define QUERY_DEV_CAP_BMME_FLAGS_OFFSET 0x94 |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 571 | #define QUERY_DEV_CAP_RSVD_LKEY_OFFSET 0x98 |
| 572 | #define QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET 0xa0 |
Matan Barak | 955154f | 2013-01-30 23:07:10 +0000 | [diff] [blame] | 573 | #define QUERY_DEV_CAP_FW_REASSIGN_MAC 0x9d |
Or Gerlitz | 7ffdf72 | 2013-12-23 16:09:43 +0200 | [diff] [blame] | 574 | #define QUERY_DEV_CAP_VXLAN 0x9e |
Jack Morgenstein | 114840c | 2014-06-01 11:53:50 +0300 | [diff] [blame] | 575 | #define QUERY_DEV_CAP_MAD_DEMUX_OFFSET 0xb0 |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 576 | |
Shlomo Pongratz | b3416f4 | 2012-04-29 17:04:25 +0300 | [diff] [blame] | 577 | dev_cap->flags2 = 0; |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 578 | mailbox = mlx4_alloc_cmd_mailbox(dev); |
| 579 | if (IS_ERR(mailbox)) |
| 580 | return PTR_ERR(mailbox); |
| 581 | outbox = mailbox->buf; |
| 582 | |
| 583 | err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP, |
Jack Morgenstein | 401453a | 2012-05-30 09:14:55 +0000 | [diff] [blame] | 584 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 585 | if (err) |
| 586 | goto out; |
| 587 | |
| 588 | MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_QP_OFFSET); |
| 589 | dev_cap->reserved_qps = 1 << (field & 0xf); |
| 590 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_OFFSET); |
| 591 | dev_cap->max_qps = 1 << (field & 0x1f); |
| 592 | MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_SRQ_OFFSET); |
| 593 | dev_cap->reserved_srqs = 1 << (field >> 4); |
| 594 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_OFFSET); |
| 595 | dev_cap->max_srqs = 1 << (field & 0x1f); |
| 596 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET); |
| 597 | dev_cap->max_cq_sz = 1 << field; |
| 598 | MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_CQ_OFFSET); |
| 599 | dev_cap->reserved_cqs = 1 << (field & 0xf); |
| 600 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_OFFSET); |
| 601 | dev_cap->max_cqs = 1 << (field & 0x1f); |
| 602 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MPT_OFFSET); |
| 603 | dev_cap->max_mpts = 1 << (field & 0x3f); |
| 604 | MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_EQ_OFFSET); |
Yevgeny Petrilin | be504b0 | 2009-11-12 15:51:16 -0800 | [diff] [blame] | 605 | dev_cap->reserved_eqs = field & 0xf; |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 606 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_EQ_OFFSET); |
Jack Morgenstein | 5920869 | 2007-12-10 05:25:23 +0200 | [diff] [blame] | 607 | dev_cap->max_eqs = 1 << (field & 0xf); |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 608 | MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MTT_OFFSET); |
| 609 | dev_cap->reserved_mtts = 1 << (field >> 4); |
| 610 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET); |
| 611 | dev_cap->max_mrw_sz = 1 << field; |
| 612 | MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MRW_OFFSET); |
| 613 | dev_cap->reserved_mrws = 1 << (field & 0xf); |
| 614 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET); |
| 615 | dev_cap->max_mtt_seg = 1 << (field & 0x3f); |
| 616 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_REQ_QP_OFFSET); |
| 617 | dev_cap->max_requester_per_qp = 1 << (field & 0x3f); |
| 618 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RES_QP_OFFSET); |
| 619 | dev_cap->max_responder_per_qp = 1 << (field & 0x3f); |
Eli Cohen | b832be1 | 2008-04-16 21:09:27 -0700 | [diff] [blame] | 620 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GSO_OFFSET); |
| 621 | field &= 0x1f; |
| 622 | if (!field) |
| 623 | dev_cap->max_gso_sz = 0; |
| 624 | else |
| 625 | dev_cap->max_gso_sz = 1 << field; |
| 626 | |
Shlomo Pongratz | b3416f4 | 2012-04-29 17:04:25 +0300 | [diff] [blame] | 627 | MLX4_GET(field, outbox, QUERY_DEV_CAP_RSS_OFFSET); |
| 628 | if (field & 0x20) |
| 629 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS_XOR; |
| 630 | if (field & 0x10) |
| 631 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS_TOP; |
| 632 | field &= 0xf; |
| 633 | if (field) { |
| 634 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS; |
| 635 | dev_cap->max_rss_tbl_sz = 1 << field; |
| 636 | } else |
| 637 | dev_cap->max_rss_tbl_sz = 0; |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 638 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RDMA_OFFSET); |
| 639 | dev_cap->max_rdma_global = 1 << (field & 0x3f); |
| 640 | MLX4_GET(field, outbox, QUERY_DEV_CAP_ACK_DELAY_OFFSET); |
| 641 | dev_cap->local_ca_ack_delay = field & 0x1f; |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 642 | MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET); |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 643 | dev_cap->num_ports = field & 0xf; |
Dotan Barak | 149983af | 2007-06-26 15:55:28 +0300 | [diff] [blame] | 644 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET); |
| 645 | dev_cap->max_msg_sz = 1 << (field & 0x1f); |
Hadar Hen Zion | 0ff1fb6 | 2012-07-05 04:03:46 +0000 | [diff] [blame] | 646 | MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET); |
| 647 | if (field & 0x80) |
| 648 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FS_EN; |
| 649 | dev_cap->fs_log_max_ucast_qp_range_size = field & 0x1f; |
Matan Barak | 4de6580 | 2013-11-07 15:25:14 +0200 | [diff] [blame] | 650 | MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET); |
| 651 | if (field & 0x80) |
| 652 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_DMFS_IPOIB; |
Hadar Hen Zion | 0ff1fb6 | 2012-07-05 04:03:46 +0000 | [diff] [blame] | 653 | MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET); |
| 654 | dev_cap->fs_max_num_qp_per_entry = field; |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 655 | MLX4_GET(stat_rate, outbox, QUERY_DEV_CAP_RATE_SUPPORT_OFFSET); |
| 656 | dev_cap->stat_rate_support = stat_rate; |
Eugenia Emantayev | d998735 | 2013-04-23 06:06:47 +0000 | [diff] [blame] | 657 | MLX4_GET(field, outbox, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET); |
| 658 | if (field & 0x80) |
| 659 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_TS; |
Or Gerlitz | ccf8632 | 2011-07-07 19:19:29 +0000 | [diff] [blame] | 660 | MLX4_GET(ext_flags, outbox, QUERY_DEV_CAP_EXT_FLAGS_OFFSET); |
Or Gerlitz | 52eafc6 | 2011-06-15 14:41:42 +0000 | [diff] [blame] | 661 | MLX4_GET(flags, outbox, QUERY_DEV_CAP_FLAGS_OFFSET); |
Or Gerlitz | ccf8632 | 2011-07-07 19:19:29 +0000 | [diff] [blame] | 662 | dev_cap->flags = flags | (u64)ext_flags << 32; |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 663 | MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_UAR_OFFSET); |
| 664 | dev_cap->reserved_uars = field >> 4; |
| 665 | MLX4_GET(field, outbox, QUERY_DEV_CAP_UAR_SZ_OFFSET); |
| 666 | dev_cap->uar_size = 1 << ((field & 0x3f) + 20); |
| 667 | MLX4_GET(field, outbox, QUERY_DEV_CAP_PAGE_SZ_OFFSET); |
| 668 | dev_cap->min_page_sz = 1 << field; |
| 669 | |
| 670 | MLX4_GET(field, outbox, QUERY_DEV_CAP_BF_OFFSET); |
| 671 | if (field & 0x80) { |
| 672 | MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET); |
| 673 | dev_cap->bf_reg_size = 1 << (field & 0x1f); |
| 674 | MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET); |
Roland Dreier | f5a4953 | 2011-01-10 17:42:05 -0800 | [diff] [blame] | 675 | if ((1 << (field & 0x3f)) > (PAGE_SIZE / dev_cap->bf_reg_size)) |
Eli Cohen | 58d74bb | 2010-11-10 12:52:37 +0000 | [diff] [blame] | 676 | field = 3; |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 677 | dev_cap->bf_regs_per_page = 1 << (field & 0x3f); |
| 678 | mlx4_dbg(dev, "BlueFlame available (reg size %d, regs/page %d)\n", |
| 679 | dev_cap->bf_reg_size, dev_cap->bf_regs_per_page); |
| 680 | } else { |
| 681 | dev_cap->bf_reg_size = 0; |
| 682 | mlx4_dbg(dev, "BlueFlame not available\n"); |
| 683 | } |
| 684 | |
| 685 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_SQ_OFFSET); |
| 686 | dev_cap->max_sq_sg = field; |
| 687 | MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET); |
| 688 | dev_cap->max_sq_desc_sz = size; |
| 689 | |
| 690 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_MCG_OFFSET); |
| 691 | dev_cap->max_qp_per_mcg = 1 << field; |
| 692 | MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MCG_OFFSET); |
| 693 | dev_cap->reserved_mgms = field & 0xf; |
| 694 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MCG_OFFSET); |
| 695 | dev_cap->max_mcgs = 1 << field; |
| 696 | MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_PD_OFFSET); |
| 697 | dev_cap->reserved_pds = field >> 4; |
| 698 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PD_OFFSET); |
| 699 | dev_cap->max_pds = 1 << (field & 0x3f); |
Linus Torvalds | f470f8d | 2011-11-01 10:51:38 -0700 | [diff] [blame] | 700 | MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_XRC_OFFSET); |
| 701 | dev_cap->reserved_xrcds = field >> 4; |
Dotan Barak | 426dd00 | 2012-08-23 14:09:04 +0000 | [diff] [blame] | 702 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_XRC_OFFSET); |
Linus Torvalds | f470f8d | 2011-11-01 10:51:38 -0700 | [diff] [blame] | 703 | dev_cap->max_xrcds = 1 << (field & 0x1f); |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 704 | |
| 705 | MLX4_GET(size, outbox, QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET); |
| 706 | dev_cap->rdmarc_entry_sz = size; |
| 707 | MLX4_GET(size, outbox, QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET); |
| 708 | dev_cap->qpc_entry_sz = size; |
| 709 | MLX4_GET(size, outbox, QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET); |
| 710 | dev_cap->aux_entry_sz = size; |
| 711 | MLX4_GET(size, outbox, QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET); |
| 712 | dev_cap->altc_entry_sz = size; |
| 713 | MLX4_GET(size, outbox, QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET); |
| 714 | dev_cap->eqc_entry_sz = size; |
| 715 | MLX4_GET(size, outbox, QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET); |
| 716 | dev_cap->cqc_entry_sz = size; |
| 717 | MLX4_GET(size, outbox, QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET); |
| 718 | dev_cap->srq_entry_sz = size; |
| 719 | MLX4_GET(size, outbox, QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET); |
| 720 | dev_cap->cmpt_entry_sz = size; |
| 721 | MLX4_GET(size, outbox, QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET); |
| 722 | dev_cap->mtt_entry_sz = size; |
| 723 | MLX4_GET(size, outbox, QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET); |
| 724 | dev_cap->dmpt_entry_sz = size; |
| 725 | |
| 726 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET); |
| 727 | dev_cap->max_srq_sz = 1 << field; |
| 728 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_SZ_OFFSET); |
| 729 | dev_cap->max_qp_sz = 1 << field; |
| 730 | MLX4_GET(field, outbox, QUERY_DEV_CAP_RSZ_SRQ_OFFSET); |
| 731 | dev_cap->resize_srq = field & 1; |
| 732 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_RQ_OFFSET); |
| 733 | dev_cap->max_rq_sg = field; |
| 734 | MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET); |
| 735 | dev_cap->max_rq_desc_sz = size; |
| 736 | |
| 737 | MLX4_GET(dev_cap->bmme_flags, outbox, |
| 738 | QUERY_DEV_CAP_BMME_FLAGS_OFFSET); |
| 739 | MLX4_GET(dev_cap->reserved_lkey, outbox, |
| 740 | QUERY_DEV_CAP_RSVD_LKEY_OFFSET); |
Matan Barak | 955154f | 2013-01-30 23:07:10 +0000 | [diff] [blame] | 741 | MLX4_GET(field, outbox, QUERY_DEV_CAP_FW_REASSIGN_MAC); |
| 742 | if (field & 1<<6) |
Or Gerlitz | 5930e8d | 2013-10-15 16:55:22 +0200 | [diff] [blame] | 743 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN; |
Or Gerlitz | 7ffdf72 | 2013-12-23 16:09:43 +0200 | [diff] [blame] | 744 | MLX4_GET(field, outbox, QUERY_DEV_CAP_VXLAN); |
| 745 | if (field & 1<<3) |
| 746 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS; |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 747 | MLX4_GET(dev_cap->max_icm_sz, outbox, |
| 748 | QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET); |
Or Gerlitz | f2a3f6a | 2011-06-15 14:47:14 +0000 | [diff] [blame] | 749 | if (dev_cap->flags & MLX4_DEV_CAP_FLAG_COUNTERS) |
| 750 | MLX4_GET(dev_cap->max_counters, outbox, |
| 751 | QUERY_DEV_CAP_MAX_COUNTERS_OFFSET); |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 752 | |
Jack Morgenstein | 114840c | 2014-06-01 11:53:50 +0300 | [diff] [blame] | 753 | MLX4_GET(field32, outbox, |
| 754 | QUERY_DEV_CAP_MAD_DEMUX_OFFSET); |
| 755 | if (field32 & (1 << 0)) |
| 756 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_MAD_DEMUX; |
| 757 | |
Rony Efraim | 3f7fb02 | 2013-04-25 05:22:28 +0000 | [diff] [blame] | 758 | MLX4_GET(field32, outbox, QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET); |
Jack Morgenstein | b01978c | 2013-06-27 19:05:21 +0300 | [diff] [blame] | 759 | if (field32 & (1 << 16)) |
| 760 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_UPDATE_QP; |
Rony Efraim | 3f7fb02 | 2013-04-25 05:22:28 +0000 | [diff] [blame] | 761 | if (field32 & (1 << 26)) |
| 762 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_VLAN_CONTROL; |
Rony Efraim | e6b6a23 | 2013-04-25 05:22:29 +0000 | [diff] [blame] | 763 | if (field32 & (1 << 20)) |
| 764 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FSM; |
Rony Efraim | 3f7fb02 | 2013-04-25 05:22:28 +0000 | [diff] [blame] | 765 | |
Roland Dreier | 5ae2a7a | 2007-06-18 08:15:02 -0700 | [diff] [blame] | 766 | if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) { |
| 767 | for (i = 1; i <= dev_cap->num_ports; ++i) { |
| 768 | MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET); |
| 769 | dev_cap->max_vl[i] = field >> 4; |
| 770 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MTU_WIDTH_OFFSET); |
Yevgeny Petrilin | b79acb4 | 2008-10-22 10:56:48 -0700 | [diff] [blame] | 771 | dev_cap->ib_mtu[i] = field >> 4; |
Roland Dreier | 5ae2a7a | 2007-06-18 08:15:02 -0700 | [diff] [blame] | 772 | dev_cap->max_port_width[i] = field & 0xf; |
| 773 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GID_OFFSET); |
| 774 | dev_cap->max_gids[i] = 1 << (field & 0xf); |
| 775 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PKEY_OFFSET); |
| 776 | dev_cap->max_pkeys[i] = 1 << (field & 0xf); |
| 777 | } |
| 778 | } else { |
Yevgeny Petrilin | 7ff93f8 | 2008-10-22 15:38:42 -0700 | [diff] [blame] | 779 | #define QUERY_PORT_SUPPORTED_TYPE_OFFSET 0x00 |
Roland Dreier | 5ae2a7a | 2007-06-18 08:15:02 -0700 | [diff] [blame] | 780 | #define QUERY_PORT_MTU_OFFSET 0x01 |
Yevgeny Petrilin | b79acb4 | 2008-10-22 10:56:48 -0700 | [diff] [blame] | 781 | #define QUERY_PORT_ETH_MTU_OFFSET 0x02 |
Roland Dreier | 5ae2a7a | 2007-06-18 08:15:02 -0700 | [diff] [blame] | 782 | #define QUERY_PORT_WIDTH_OFFSET 0x06 |
| 783 | #define QUERY_PORT_MAX_GID_PKEY_OFFSET 0x07 |
Yevgeny Petrilin | 93fc9e1 | 2008-10-22 10:25:29 -0700 | [diff] [blame] | 784 | #define QUERY_PORT_MAX_MACVLAN_OFFSET 0x0a |
Roland Dreier | 5ae2a7a | 2007-06-18 08:15:02 -0700 | [diff] [blame] | 785 | #define QUERY_PORT_MAX_VL_OFFSET 0x0b |
Yevgeny Petrilin | e65b959 | 2008-10-26 17:13:24 +0200 | [diff] [blame] | 786 | #define QUERY_PORT_MAC_OFFSET 0x10 |
Yevgeny Petrilin | 7699517 | 2010-08-24 03:46:23 +0000 | [diff] [blame] | 787 | #define QUERY_PORT_TRANS_VENDOR_OFFSET 0x18 |
| 788 | #define QUERY_PORT_WAVELENGTH_OFFSET 0x1c |
| 789 | #define QUERY_PORT_TRANS_CODE_OFFSET 0x20 |
Roland Dreier | 5ae2a7a | 2007-06-18 08:15:02 -0700 | [diff] [blame] | 790 | |
| 791 | for (i = 1; i <= dev_cap->num_ports; ++i) { |
| 792 | err = mlx4_cmd_box(dev, 0, mailbox->dma, i, 0, MLX4_CMD_QUERY_PORT, |
Jack Morgenstein | 401453a | 2012-05-30 09:14:55 +0000 | [diff] [blame] | 793 | MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); |
Roland Dreier | 5ae2a7a | 2007-06-18 08:15:02 -0700 | [diff] [blame] | 794 | if (err) |
| 795 | goto out; |
| 796 | |
Yevgeny Petrilin | 7ff93f8 | 2008-10-22 15:38:42 -0700 | [diff] [blame] | 797 | MLX4_GET(field, outbox, QUERY_PORT_SUPPORTED_TYPE_OFFSET); |
| 798 | dev_cap->supported_port_types[i] = field & 3; |
Yevgeny Petrilin | 8d0fc7b | 2011-12-19 04:00:34 +0000 | [diff] [blame] | 799 | dev_cap->suggested_type[i] = (field >> 3) & 1; |
| 800 | dev_cap->default_sense[i] = (field >> 4) & 1; |
Roland Dreier | 5ae2a7a | 2007-06-18 08:15:02 -0700 | [diff] [blame] | 801 | MLX4_GET(field, outbox, QUERY_PORT_MTU_OFFSET); |
Yevgeny Petrilin | b79acb4 | 2008-10-22 10:56:48 -0700 | [diff] [blame] | 802 | dev_cap->ib_mtu[i] = field & 0xf; |
Roland Dreier | 5ae2a7a | 2007-06-18 08:15:02 -0700 | [diff] [blame] | 803 | MLX4_GET(field, outbox, QUERY_PORT_WIDTH_OFFSET); |
| 804 | dev_cap->max_port_width[i] = field & 0xf; |
| 805 | MLX4_GET(field, outbox, QUERY_PORT_MAX_GID_PKEY_OFFSET); |
| 806 | dev_cap->max_gids[i] = 1 << (field >> 4); |
| 807 | dev_cap->max_pkeys[i] = 1 << (field & 0xf); |
| 808 | MLX4_GET(field, outbox, QUERY_PORT_MAX_VL_OFFSET); |
| 809 | dev_cap->max_vl[i] = field & 0xf; |
Yevgeny Petrilin | 93fc9e1 | 2008-10-22 10:25:29 -0700 | [diff] [blame] | 810 | MLX4_GET(field, outbox, QUERY_PORT_MAX_MACVLAN_OFFSET); |
| 811 | dev_cap->log_max_macs[i] = field & 0xf; |
| 812 | dev_cap->log_max_vlans[i] = field >> 4; |
Yevgeny Petrilin | b79acb4 | 2008-10-22 10:56:48 -0700 | [diff] [blame] | 813 | MLX4_GET(dev_cap->eth_mtu[i], outbox, QUERY_PORT_ETH_MTU_OFFSET); |
| 814 | MLX4_GET(dev_cap->def_mac[i], outbox, QUERY_PORT_MAC_OFFSET); |
Yevgeny Petrilin | 7699517 | 2010-08-24 03:46:23 +0000 | [diff] [blame] | 815 | MLX4_GET(field32, outbox, QUERY_PORT_TRANS_VENDOR_OFFSET); |
| 816 | dev_cap->trans_type[i] = field32 >> 24; |
| 817 | dev_cap->vendor_oui[i] = field32 & 0xffffff; |
| 818 | MLX4_GET(dev_cap->wavelength[i], outbox, QUERY_PORT_WAVELENGTH_OFFSET); |
| 819 | MLX4_GET(dev_cap->trans_code[i], outbox, QUERY_PORT_TRANS_CODE_OFFSET); |
Roland Dreier | 5ae2a7a | 2007-06-18 08:15:02 -0700 | [diff] [blame] | 820 | } |
| 821 | } |
| 822 | |
Roland Dreier | 95d04f0 | 2008-07-23 08:12:26 -0700 | [diff] [blame] | 823 | mlx4_dbg(dev, "Base MM extensions: flags %08x, rsvd L_Key %08x\n", |
| 824 | dev_cap->bmme_flags, dev_cap->reserved_lkey); |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 825 | |
| 826 | /* |
| 827 | * Each UAR has 4 EQ doorbells; so if a UAR is reserved, then |
| 828 | * we can't use any EQs whose doorbell falls on that page, |
| 829 | * even if the EQ itself isn't reserved. |
| 830 | */ |
| 831 | dev_cap->reserved_eqs = max(dev_cap->reserved_uars * 4, |
| 832 | dev_cap->reserved_eqs); |
| 833 | |
| 834 | mlx4_dbg(dev, "Max ICM size %lld MB\n", |
| 835 | (unsigned long long) dev_cap->max_icm_sz >> 20); |
| 836 | mlx4_dbg(dev, "Max QPs: %d, reserved QPs: %d, entry size: %d\n", |
| 837 | dev_cap->max_qps, dev_cap->reserved_qps, dev_cap->qpc_entry_sz); |
| 838 | mlx4_dbg(dev, "Max SRQs: %d, reserved SRQs: %d, entry size: %d\n", |
| 839 | dev_cap->max_srqs, dev_cap->reserved_srqs, dev_cap->srq_entry_sz); |
| 840 | mlx4_dbg(dev, "Max CQs: %d, reserved CQs: %d, entry size: %d\n", |
| 841 | dev_cap->max_cqs, dev_cap->reserved_cqs, dev_cap->cqc_entry_sz); |
| 842 | mlx4_dbg(dev, "Max EQs: %d, reserved EQs: %d, entry size: %d\n", |
| 843 | dev_cap->max_eqs, dev_cap->reserved_eqs, dev_cap->eqc_entry_sz); |
| 844 | mlx4_dbg(dev, "reserved MPTs: %d, reserved MTTs: %d\n", |
| 845 | dev_cap->reserved_mrws, dev_cap->reserved_mtts); |
| 846 | mlx4_dbg(dev, "Max PDs: %d, reserved PDs: %d, reserved UARs: %d\n", |
| 847 | dev_cap->max_pds, dev_cap->reserved_pds, dev_cap->reserved_uars); |
| 848 | mlx4_dbg(dev, "Max QP/MCG: %d, reserved MGMs: %d\n", |
| 849 | dev_cap->max_pds, dev_cap->reserved_mgms); |
| 850 | mlx4_dbg(dev, "Max CQEs: %d, max WQEs: %d, max SRQ WQEs: %d\n", |
| 851 | dev_cap->max_cq_sz, dev_cap->max_qp_sz, dev_cap->max_srq_sz); |
| 852 | mlx4_dbg(dev, "Local CA ACK delay: %d, max MTU: %d, port width cap: %d\n", |
Yevgeny Petrilin | b79acb4 | 2008-10-22 10:56:48 -0700 | [diff] [blame] | 853 | dev_cap->local_ca_ack_delay, 128 << dev_cap->ib_mtu[1], |
Roland Dreier | 5ae2a7a | 2007-06-18 08:15:02 -0700 | [diff] [blame] | 854 | dev_cap->max_port_width[1]); |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 855 | mlx4_dbg(dev, "Max SQ desc size: %d, max SQ S/G: %d\n", |
| 856 | dev_cap->max_sq_desc_sz, dev_cap->max_sq_sg); |
| 857 | mlx4_dbg(dev, "Max RQ desc size: %d, max RQ S/G: %d\n", |
| 858 | dev_cap->max_rq_desc_sz, dev_cap->max_rq_sg); |
Eli Cohen | b832be1 | 2008-04-16 21:09:27 -0700 | [diff] [blame] | 859 | mlx4_dbg(dev, "Max GSO size: %d\n", dev_cap->max_gso_sz); |
Or Gerlitz | f2a3f6a | 2011-06-15 14:47:14 +0000 | [diff] [blame] | 860 | mlx4_dbg(dev, "Max counters: %d\n", dev_cap->max_counters); |
Shlomo Pongratz | b3416f4 | 2012-04-29 17:04:25 +0300 | [diff] [blame] | 861 | mlx4_dbg(dev, "Max RSS Table size: %d\n", dev_cap->max_rss_tbl_sz); |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 862 | |
| 863 | dump_dev_cap_flags(dev, dev_cap->flags); |
Shlomo Pongratz | b3416f4 | 2012-04-29 17:04:25 +0300 | [diff] [blame] | 864 | dump_dev_cap_flags2(dev, dev_cap->flags2); |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 865 | |
| 866 | out: |
| 867 | mlx4_free_cmd_mailbox(dev, mailbox); |
| 868 | return err; |
| 869 | } |
| 870 | |
Jack Morgenstein | b91cb3e | 2012-05-30 09:14:53 +0000 | [diff] [blame] | 871 | int mlx4_QUERY_DEV_CAP_wrapper(struct mlx4_dev *dev, int slave, |
| 872 | struct mlx4_vhcr *vhcr, |
| 873 | struct mlx4_cmd_mailbox *inbox, |
| 874 | struct mlx4_cmd_mailbox *outbox, |
| 875 | struct mlx4_cmd_info *cmd) |
| 876 | { |
Jack Morgenstein | 2a4fae1 | 2012-08-03 08:40:50 +0000 | [diff] [blame] | 877 | u64 flags; |
Jack Morgenstein | b91cb3e | 2012-05-30 09:14:53 +0000 | [diff] [blame] | 878 | int err = 0; |
| 879 | u8 field; |
Shani Michaeli | cc1ade9 | 2013-02-06 16:19:10 +0000 | [diff] [blame] | 880 | u32 bmme_flags; |
Matan Barak | 449fc48 | 2014-03-19 18:11:52 +0200 | [diff] [blame] | 881 | int real_port; |
| 882 | int slave_port; |
| 883 | int first_port; |
| 884 | struct mlx4_active_ports actv_ports; |
Jack Morgenstein | b91cb3e | 2012-05-30 09:14:53 +0000 | [diff] [blame] | 885 | |
| 886 | err = mlx4_cmd_box(dev, 0, outbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP, |
| 887 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); |
| 888 | if (err) |
| 889 | return err; |
| 890 | |
Shani Michaeli | cc1ade9 | 2013-02-06 16:19:10 +0000 | [diff] [blame] | 891 | /* add port mng change event capability and disable mw type 1 |
| 892 | * unconditionally to slaves |
| 893 | */ |
Jack Morgenstein | 2a4fae1 | 2012-08-03 08:40:50 +0000 | [diff] [blame] | 894 | MLX4_GET(flags, outbox->buf, QUERY_DEV_CAP_EXT_FLAGS_OFFSET); |
| 895 | flags |= MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV; |
Shani Michaeli | cc1ade9 | 2013-02-06 16:19:10 +0000 | [diff] [blame] | 896 | flags &= ~MLX4_DEV_CAP_FLAG_MEM_WINDOW; |
Matan Barak | 449fc48 | 2014-03-19 18:11:52 +0200 | [diff] [blame] | 897 | actv_ports = mlx4_get_active_ports(dev, slave); |
| 898 | first_port = find_first_bit(actv_ports.ports, dev->caps.num_ports); |
| 899 | for (slave_port = 0, real_port = first_port; |
| 900 | real_port < first_port + |
| 901 | bitmap_weight(actv_ports.ports, dev->caps.num_ports); |
| 902 | ++real_port, ++slave_port) { |
| 903 | if (flags & (MLX4_DEV_CAP_FLAG_WOL_PORT1 << real_port)) |
| 904 | flags |= MLX4_DEV_CAP_FLAG_WOL_PORT1 << slave_port; |
| 905 | else |
| 906 | flags &= ~(MLX4_DEV_CAP_FLAG_WOL_PORT1 << slave_port); |
| 907 | } |
| 908 | for (; slave_port < dev->caps.num_ports; ++slave_port) |
| 909 | flags &= ~(MLX4_DEV_CAP_FLAG_WOL_PORT1 << slave_port); |
Jack Morgenstein | 2a4fae1 | 2012-08-03 08:40:50 +0000 | [diff] [blame] | 910 | MLX4_PUT(outbox->buf, flags, QUERY_DEV_CAP_EXT_FLAGS_OFFSET); |
| 911 | |
Matan Barak | 449fc48 | 2014-03-19 18:11:52 +0200 | [diff] [blame] | 912 | MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_VL_PORT_OFFSET); |
| 913 | field &= ~0x0F; |
| 914 | field |= bitmap_weight(actv_ports.ports, dev->caps.num_ports) & 0x0F; |
| 915 | MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_VL_PORT_OFFSET); |
| 916 | |
Amir Vadai | 30b40c3 | 2013-04-25 05:22:23 +0000 | [diff] [blame] | 917 | /* For guests, disable timestamp */ |
| 918 | MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET); |
| 919 | field &= 0x7f; |
| 920 | MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET); |
| 921 | |
Or Gerlitz | 7ffdf72 | 2013-12-23 16:09:43 +0200 | [diff] [blame] | 922 | /* For guests, disable vxlan tunneling */ |
Amir Vadai | 57352ef | 2014-03-06 18:28:16 +0200 | [diff] [blame] | 923 | MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_VXLAN); |
Or Gerlitz | 7ffdf72 | 2013-12-23 16:09:43 +0200 | [diff] [blame] | 924 | field &= 0xf7; |
| 925 | MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_VXLAN); |
| 926 | |
Jack Morgenstein | b91cb3e | 2012-05-30 09:14:53 +0000 | [diff] [blame] | 927 | /* For guests, report Blueflame disabled */ |
| 928 | MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_BF_OFFSET); |
| 929 | field &= 0x7f; |
| 930 | MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_BF_OFFSET); |
| 931 | |
Shani Michaeli | cc1ade9 | 2013-02-06 16:19:10 +0000 | [diff] [blame] | 932 | /* For guests, disable mw type 2 */ |
Amir Vadai | 57352ef | 2014-03-06 18:28:16 +0200 | [diff] [blame] | 933 | MLX4_GET(bmme_flags, outbox->buf, QUERY_DEV_CAP_BMME_FLAGS_OFFSET); |
Shani Michaeli | cc1ade9 | 2013-02-06 16:19:10 +0000 | [diff] [blame] | 934 | bmme_flags &= ~MLX4_BMME_FLAG_TYPE_2_WIN; |
| 935 | MLX4_PUT(outbox->buf, bmme_flags, QUERY_DEV_CAP_BMME_FLAGS_OFFSET); |
| 936 | |
Jack Morgenstein | 0081c8f | 2013-03-07 03:46:53 +0000 | [diff] [blame] | 937 | /* turn off device-managed steering capability if not enabled */ |
| 938 | if (dev->caps.steering_mode != MLX4_STEERING_MODE_DEVICE_MANAGED) { |
| 939 | MLX4_GET(field, outbox->buf, |
| 940 | QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET); |
| 941 | field &= 0x7f; |
| 942 | MLX4_PUT(outbox->buf, field, |
| 943 | QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET); |
| 944 | } |
Matan Barak | 4de6580 | 2013-11-07 15:25:14 +0200 | [diff] [blame] | 945 | |
| 946 | /* turn off ipoib managed steering for guests */ |
Amir Vadai | 57352ef | 2014-03-06 18:28:16 +0200 | [diff] [blame] | 947 | MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET); |
Matan Barak | 4de6580 | 2013-11-07 15:25:14 +0200 | [diff] [blame] | 948 | field &= ~0x80; |
| 949 | MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET); |
| 950 | |
Jack Morgenstein | b91cb3e | 2012-05-30 09:14:53 +0000 | [diff] [blame] | 951 | return 0; |
| 952 | } |
| 953 | |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 954 | int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave, |
| 955 | struct mlx4_vhcr *vhcr, |
| 956 | struct mlx4_cmd_mailbox *inbox, |
| 957 | struct mlx4_cmd_mailbox *outbox, |
| 958 | struct mlx4_cmd_info *cmd) |
| 959 | { |
Rony Efraim | 0eb62b9 | 2013-04-25 05:22:26 +0000 | [diff] [blame] | 960 | struct mlx4_priv *priv = mlx4_priv(dev); |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 961 | u64 def_mac; |
| 962 | u8 port_type; |
Jack Morgenstein | 6634961 | 2012-06-19 11:21:44 +0300 | [diff] [blame] | 963 | u16 short_field; |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 964 | int err; |
Rony Efraim | 948e306 | 2013-06-13 13:19:11 +0300 | [diff] [blame] | 965 | int admin_link_state; |
Matan Barak | 449fc48 | 2014-03-19 18:11:52 +0200 | [diff] [blame] | 966 | int port = mlx4_slave_convert_port(dev, slave, |
| 967 | vhcr->in_modifier & 0xFF); |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 968 | |
Jack Morgenstein | 105c320 | 2012-06-19 11:21:43 +0300 | [diff] [blame] | 969 | #define MLX4_VF_PORT_NO_LINK_SENSE_MASK 0xE0 |
Rony Efraim | 948e306 | 2013-06-13 13:19:11 +0300 | [diff] [blame] | 970 | #define MLX4_PORT_LINK_UP_MASK 0x80 |
Jack Morgenstein | 6634961 | 2012-06-19 11:21:44 +0300 | [diff] [blame] | 971 | #define QUERY_PORT_CUR_MAX_PKEY_OFFSET 0x0c |
| 972 | #define QUERY_PORT_CUR_MAX_GID_OFFSET 0x0e |
Yevgeny Petrilin | 95f56e7 | 2011-12-29 07:42:39 +0000 | [diff] [blame] | 973 | |
Matan Barak | 449fc48 | 2014-03-19 18:11:52 +0200 | [diff] [blame] | 974 | if (port < 0) |
| 975 | return -EINVAL; |
| 976 | |
| 977 | vhcr->in_modifier = (vhcr->in_modifier & ~0xFF) | |
| 978 | (port & 0xFF); |
| 979 | |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 980 | err = mlx4_cmd_box(dev, 0, outbox->dma, vhcr->in_modifier, 0, |
| 981 | MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B, |
| 982 | MLX4_CMD_NATIVE); |
| 983 | |
| 984 | if (!err && dev->caps.function != slave) { |
Or Gerlitz | 0508ad6 | 2013-08-01 19:55:00 +0300 | [diff] [blame] | 985 | def_mac = priv->mfunc.master.vf_oper[slave].vport[vhcr->in_modifier].state.mac; |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 986 | MLX4_PUT(outbox->buf, def_mac, QUERY_PORT_MAC_OFFSET); |
| 987 | |
| 988 | /* get port type - currently only eth is enabled */ |
| 989 | MLX4_GET(port_type, outbox->buf, |
| 990 | QUERY_PORT_SUPPORTED_TYPE_OFFSET); |
| 991 | |
Jack Morgenstein | 105c320 | 2012-06-19 11:21:43 +0300 | [diff] [blame] | 992 | /* No link sensing allowed */ |
| 993 | port_type &= MLX4_VF_PORT_NO_LINK_SENSE_MASK; |
| 994 | /* set port type to currently operating port type */ |
| 995 | port_type |= (dev->caps.port_type[vhcr->in_modifier] & 0x3); |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 996 | |
Rony Efraim | 948e306 | 2013-06-13 13:19:11 +0300 | [diff] [blame] | 997 | admin_link_state = priv->mfunc.master.vf_oper[slave].vport[vhcr->in_modifier].state.link_state; |
| 998 | if (IFLA_VF_LINK_STATE_ENABLE == admin_link_state) |
| 999 | port_type |= MLX4_PORT_LINK_UP_MASK; |
| 1000 | else if (IFLA_VF_LINK_STATE_DISABLE == admin_link_state) |
| 1001 | port_type &= ~MLX4_PORT_LINK_UP_MASK; |
| 1002 | |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 1003 | MLX4_PUT(outbox->buf, port_type, |
| 1004 | QUERY_PORT_SUPPORTED_TYPE_OFFSET); |
Jack Morgenstein | 6634961 | 2012-06-19 11:21:44 +0300 | [diff] [blame] | 1005 | |
Jack Morgenstein | b6ffaef | 2014-03-12 12:00:39 +0200 | [diff] [blame] | 1006 | if (dev->caps.port_type[vhcr->in_modifier] == MLX4_PORT_TYPE_ETH) |
Matan Barak | 449fc48 | 2014-03-19 18:11:52 +0200 | [diff] [blame] | 1007 | short_field = mlx4_get_slave_num_gids(dev, slave, port); |
Jack Morgenstein | b6ffaef | 2014-03-12 12:00:39 +0200 | [diff] [blame] | 1008 | else |
| 1009 | short_field = 1; /* slave max gids */ |
Jack Morgenstein | 6634961 | 2012-06-19 11:21:44 +0300 | [diff] [blame] | 1010 | MLX4_PUT(outbox->buf, short_field, |
| 1011 | QUERY_PORT_CUR_MAX_GID_OFFSET); |
| 1012 | |
| 1013 | short_field = dev->caps.pkey_table_len[vhcr->in_modifier]; |
| 1014 | MLX4_PUT(outbox->buf, short_field, |
| 1015 | QUERY_PORT_CUR_MAX_PKEY_OFFSET); |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 1016 | } |
| 1017 | |
| 1018 | return err; |
| 1019 | } |
| 1020 | |
Jack Morgenstein | 6634961 | 2012-06-19 11:21:44 +0300 | [diff] [blame] | 1021 | int mlx4_get_slave_pkey_gid_tbl_len(struct mlx4_dev *dev, u8 port, |
| 1022 | int *gid_tbl_len, int *pkey_tbl_len) |
| 1023 | { |
| 1024 | struct mlx4_cmd_mailbox *mailbox; |
| 1025 | u32 *outbox; |
| 1026 | u16 field; |
| 1027 | int err; |
| 1028 | |
| 1029 | mailbox = mlx4_alloc_cmd_mailbox(dev); |
| 1030 | if (IS_ERR(mailbox)) |
| 1031 | return PTR_ERR(mailbox); |
| 1032 | |
| 1033 | err = mlx4_cmd_box(dev, 0, mailbox->dma, port, 0, |
| 1034 | MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B, |
| 1035 | MLX4_CMD_WRAPPED); |
| 1036 | if (err) |
| 1037 | goto out; |
| 1038 | |
| 1039 | outbox = mailbox->buf; |
| 1040 | |
| 1041 | MLX4_GET(field, outbox, QUERY_PORT_CUR_MAX_GID_OFFSET); |
| 1042 | *gid_tbl_len = field; |
| 1043 | |
| 1044 | MLX4_GET(field, outbox, QUERY_PORT_CUR_MAX_PKEY_OFFSET); |
| 1045 | *pkey_tbl_len = field; |
| 1046 | |
| 1047 | out: |
| 1048 | mlx4_free_cmd_mailbox(dev, mailbox); |
| 1049 | return err; |
| 1050 | } |
| 1051 | EXPORT_SYMBOL(mlx4_get_slave_pkey_gid_tbl_len); |
| 1052 | |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1053 | int mlx4_map_cmd(struct mlx4_dev *dev, u16 op, struct mlx4_icm *icm, u64 virt) |
| 1054 | { |
| 1055 | struct mlx4_cmd_mailbox *mailbox; |
| 1056 | struct mlx4_icm_iter iter; |
| 1057 | __be64 *pages; |
| 1058 | int lg; |
| 1059 | int nent = 0; |
| 1060 | int i; |
| 1061 | int err = 0; |
| 1062 | int ts = 0, tc = 0; |
| 1063 | |
| 1064 | mailbox = mlx4_alloc_cmd_mailbox(dev); |
| 1065 | if (IS_ERR(mailbox)) |
| 1066 | return PTR_ERR(mailbox); |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1067 | pages = mailbox->buf; |
| 1068 | |
| 1069 | for (mlx4_icm_first(icm, &iter); |
| 1070 | !mlx4_icm_last(&iter); |
| 1071 | mlx4_icm_next(&iter)) { |
| 1072 | /* |
| 1073 | * We have to pass pages that are aligned to their |
| 1074 | * size, so find the least significant 1 in the |
| 1075 | * address or size and use that as our log2 size. |
| 1076 | */ |
| 1077 | lg = ffs(mlx4_icm_addr(&iter) | mlx4_icm_size(&iter)) - 1; |
| 1078 | if (lg < MLX4_ICM_PAGE_SHIFT) { |
Joe Perches | 1a91de2 | 2014-05-07 12:52:57 -0700 | [diff] [blame] | 1079 | mlx4_warn(dev, "Got FW area not aligned to %d (%llx/%lx)\n", |
| 1080 | MLX4_ICM_PAGE_SIZE, |
| 1081 | (unsigned long long) mlx4_icm_addr(&iter), |
| 1082 | mlx4_icm_size(&iter)); |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1083 | err = -EINVAL; |
| 1084 | goto out; |
| 1085 | } |
| 1086 | |
| 1087 | for (i = 0; i < mlx4_icm_size(&iter) >> lg; ++i) { |
| 1088 | if (virt != -1) { |
| 1089 | pages[nent * 2] = cpu_to_be64(virt); |
| 1090 | virt += 1 << lg; |
| 1091 | } |
| 1092 | |
| 1093 | pages[nent * 2 + 1] = |
| 1094 | cpu_to_be64((mlx4_icm_addr(&iter) + (i << lg)) | |
| 1095 | (lg - MLX4_ICM_PAGE_SHIFT)); |
| 1096 | ts += 1 << (lg - 10); |
| 1097 | ++tc; |
| 1098 | |
| 1099 | if (++nent == MLX4_MAILBOX_SIZE / 16) { |
| 1100 | err = mlx4_cmd(dev, mailbox->dma, nent, 0, op, |
Jack Morgenstein | f9baff5 | 2011-12-13 04:10:51 +0000 | [diff] [blame] | 1101 | MLX4_CMD_TIME_CLASS_B, |
| 1102 | MLX4_CMD_NATIVE); |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1103 | if (err) |
| 1104 | goto out; |
| 1105 | nent = 0; |
| 1106 | } |
| 1107 | } |
| 1108 | } |
| 1109 | |
| 1110 | if (nent) |
Jack Morgenstein | f9baff5 | 2011-12-13 04:10:51 +0000 | [diff] [blame] | 1111 | err = mlx4_cmd(dev, mailbox->dma, nent, 0, op, |
| 1112 | MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1113 | if (err) |
| 1114 | goto out; |
| 1115 | |
| 1116 | switch (op) { |
| 1117 | case MLX4_CMD_MAP_FA: |
Joe Perches | 1a91de2 | 2014-05-07 12:52:57 -0700 | [diff] [blame] | 1118 | mlx4_dbg(dev, "Mapped %d chunks/%d KB for FW\n", tc, ts); |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1119 | break; |
| 1120 | case MLX4_CMD_MAP_ICM_AUX: |
Joe Perches | 1a91de2 | 2014-05-07 12:52:57 -0700 | [diff] [blame] | 1121 | mlx4_dbg(dev, "Mapped %d chunks/%d KB for ICM aux\n", tc, ts); |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1122 | break; |
| 1123 | case MLX4_CMD_MAP_ICM: |
Joe Perches | 1a91de2 | 2014-05-07 12:52:57 -0700 | [diff] [blame] | 1124 | mlx4_dbg(dev, "Mapped %d chunks/%d KB at %llx for ICM\n", |
| 1125 | tc, ts, (unsigned long long) virt - (ts << 10)); |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1126 | break; |
| 1127 | } |
| 1128 | |
| 1129 | out: |
| 1130 | mlx4_free_cmd_mailbox(dev, mailbox); |
| 1131 | return err; |
| 1132 | } |
| 1133 | |
| 1134 | int mlx4_MAP_FA(struct mlx4_dev *dev, struct mlx4_icm *icm) |
| 1135 | { |
| 1136 | return mlx4_map_cmd(dev, MLX4_CMD_MAP_FA, icm, -1); |
| 1137 | } |
| 1138 | |
| 1139 | int mlx4_UNMAP_FA(struct mlx4_dev *dev) |
| 1140 | { |
Jack Morgenstein | f9baff5 | 2011-12-13 04:10:51 +0000 | [diff] [blame] | 1141 | return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_UNMAP_FA, |
| 1142 | MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1143 | } |
| 1144 | |
| 1145 | |
| 1146 | int mlx4_RUN_FW(struct mlx4_dev *dev) |
| 1147 | { |
Jack Morgenstein | f9baff5 | 2011-12-13 04:10:51 +0000 | [diff] [blame] | 1148 | return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_RUN_FW, |
| 1149 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1150 | } |
| 1151 | |
| 1152 | int mlx4_QUERY_FW(struct mlx4_dev *dev) |
| 1153 | { |
| 1154 | struct mlx4_fw *fw = &mlx4_priv(dev)->fw; |
| 1155 | struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd; |
| 1156 | struct mlx4_cmd_mailbox *mailbox; |
| 1157 | u32 *outbox; |
| 1158 | int err = 0; |
| 1159 | u64 fw_ver; |
Roland Dreier | fe40900 | 2007-06-07 23:24:36 -0700 | [diff] [blame] | 1160 | u16 cmd_if_rev; |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1161 | u8 lg; |
| 1162 | |
| 1163 | #define QUERY_FW_OUT_SIZE 0x100 |
| 1164 | #define QUERY_FW_VER_OFFSET 0x00 |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 1165 | #define QUERY_FW_PPF_ID 0x09 |
Roland Dreier | fe40900 | 2007-06-07 23:24:36 -0700 | [diff] [blame] | 1166 | #define QUERY_FW_CMD_IF_REV_OFFSET 0x0a |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1167 | #define QUERY_FW_MAX_CMD_OFFSET 0x0f |
| 1168 | #define QUERY_FW_ERR_START_OFFSET 0x30 |
| 1169 | #define QUERY_FW_ERR_SIZE_OFFSET 0x38 |
| 1170 | #define QUERY_FW_ERR_BAR_OFFSET 0x3c |
| 1171 | |
| 1172 | #define QUERY_FW_SIZE_OFFSET 0x00 |
| 1173 | #define QUERY_FW_CLR_INT_BASE_OFFSET 0x20 |
| 1174 | #define QUERY_FW_CLR_INT_BAR_OFFSET 0x28 |
| 1175 | |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 1176 | #define QUERY_FW_COMM_BASE_OFFSET 0x40 |
| 1177 | #define QUERY_FW_COMM_BAR_OFFSET 0x48 |
| 1178 | |
Eugenia Emantayev | ddd8a6c | 2013-04-23 06:06:48 +0000 | [diff] [blame] | 1179 | #define QUERY_FW_CLOCK_OFFSET 0x50 |
| 1180 | #define QUERY_FW_CLOCK_BAR 0x58 |
| 1181 | |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1182 | mailbox = mlx4_alloc_cmd_mailbox(dev); |
| 1183 | if (IS_ERR(mailbox)) |
| 1184 | return PTR_ERR(mailbox); |
| 1185 | outbox = mailbox->buf; |
| 1186 | |
| 1187 | err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_FW, |
Jack Morgenstein | f9baff5 | 2011-12-13 04:10:51 +0000 | [diff] [blame] | 1188 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1189 | if (err) |
| 1190 | goto out; |
| 1191 | |
| 1192 | MLX4_GET(fw_ver, outbox, QUERY_FW_VER_OFFSET); |
| 1193 | /* |
Roland Dreier | 3e1db33 | 2007-06-03 19:47:10 -0700 | [diff] [blame] | 1194 | * FW subminor version is at more significant bits than minor |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1195 | * version, so swap here. |
| 1196 | */ |
| 1197 | dev->caps.fw_ver = (fw_ver & 0xffff00000000ull) | |
| 1198 | ((fw_ver & 0xffff0000ull) >> 16) | |
| 1199 | ((fw_ver & 0x0000ffffull) << 16); |
| 1200 | |
Jack Morgenstein | 752a50c | 2012-06-19 11:21:33 +0300 | [diff] [blame] | 1201 | MLX4_GET(lg, outbox, QUERY_FW_PPF_ID); |
| 1202 | dev->caps.function = lg; |
| 1203 | |
Jack Morgenstein | b91cb3e | 2012-05-30 09:14:53 +0000 | [diff] [blame] | 1204 | if (mlx4_is_slave(dev)) |
| 1205 | goto out; |
| 1206 | |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 1207 | |
Roland Dreier | fe40900 | 2007-06-07 23:24:36 -0700 | [diff] [blame] | 1208 | MLX4_GET(cmd_if_rev, outbox, QUERY_FW_CMD_IF_REV_OFFSET); |
Roland Dreier | 5ae2a7a | 2007-06-18 08:15:02 -0700 | [diff] [blame] | 1209 | if (cmd_if_rev < MLX4_COMMAND_INTERFACE_MIN_REV || |
| 1210 | cmd_if_rev > MLX4_COMMAND_INTERFACE_MAX_REV) { |
Joe Perches | 1a91de2 | 2014-05-07 12:52:57 -0700 | [diff] [blame] | 1211 | mlx4_err(dev, "Installed FW has unsupported command interface revision %d\n", |
Roland Dreier | fe40900 | 2007-06-07 23:24:36 -0700 | [diff] [blame] | 1212 | cmd_if_rev); |
| 1213 | mlx4_err(dev, "(Installed FW version is %d.%d.%03d)\n", |
| 1214 | (int) (dev->caps.fw_ver >> 32), |
| 1215 | (int) (dev->caps.fw_ver >> 16) & 0xffff, |
| 1216 | (int) dev->caps.fw_ver & 0xffff); |
Joe Perches | 1a91de2 | 2014-05-07 12:52:57 -0700 | [diff] [blame] | 1217 | mlx4_err(dev, "This driver version supports only revisions %d to %d\n", |
Roland Dreier | 5ae2a7a | 2007-06-18 08:15:02 -0700 | [diff] [blame] | 1218 | MLX4_COMMAND_INTERFACE_MIN_REV, MLX4_COMMAND_INTERFACE_MAX_REV); |
Roland Dreier | fe40900 | 2007-06-07 23:24:36 -0700 | [diff] [blame] | 1219 | err = -ENODEV; |
| 1220 | goto out; |
| 1221 | } |
| 1222 | |
Roland Dreier | 5ae2a7a | 2007-06-18 08:15:02 -0700 | [diff] [blame] | 1223 | if (cmd_if_rev < MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS) |
| 1224 | dev->flags |= MLX4_FLAG_OLD_PORT_CMDS; |
| 1225 | |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1226 | MLX4_GET(lg, outbox, QUERY_FW_MAX_CMD_OFFSET); |
| 1227 | cmd->max_cmds = 1 << lg; |
| 1228 | |
Roland Dreier | fe40900 | 2007-06-07 23:24:36 -0700 | [diff] [blame] | 1229 | mlx4_dbg(dev, "FW version %d.%d.%03d (cmd intf rev %d), max commands %d\n", |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1230 | (int) (dev->caps.fw_ver >> 32), |
| 1231 | (int) (dev->caps.fw_ver >> 16) & 0xffff, |
| 1232 | (int) dev->caps.fw_ver & 0xffff, |
Roland Dreier | fe40900 | 2007-06-07 23:24:36 -0700 | [diff] [blame] | 1233 | cmd_if_rev, cmd->max_cmds); |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1234 | |
| 1235 | MLX4_GET(fw->catas_offset, outbox, QUERY_FW_ERR_START_OFFSET); |
| 1236 | MLX4_GET(fw->catas_size, outbox, QUERY_FW_ERR_SIZE_OFFSET); |
| 1237 | MLX4_GET(fw->catas_bar, outbox, QUERY_FW_ERR_BAR_OFFSET); |
| 1238 | fw->catas_bar = (fw->catas_bar >> 6) * 2; |
| 1239 | |
| 1240 | mlx4_dbg(dev, "Catastrophic error buffer at 0x%llx, size 0x%x, BAR %d\n", |
| 1241 | (unsigned long long) fw->catas_offset, fw->catas_size, fw->catas_bar); |
| 1242 | |
| 1243 | MLX4_GET(fw->fw_pages, outbox, QUERY_FW_SIZE_OFFSET); |
| 1244 | MLX4_GET(fw->clr_int_base, outbox, QUERY_FW_CLR_INT_BASE_OFFSET); |
| 1245 | MLX4_GET(fw->clr_int_bar, outbox, QUERY_FW_CLR_INT_BAR_OFFSET); |
| 1246 | fw->clr_int_bar = (fw->clr_int_bar >> 6) * 2; |
| 1247 | |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 1248 | MLX4_GET(fw->comm_base, outbox, QUERY_FW_COMM_BASE_OFFSET); |
| 1249 | MLX4_GET(fw->comm_bar, outbox, QUERY_FW_COMM_BAR_OFFSET); |
| 1250 | fw->comm_bar = (fw->comm_bar >> 6) * 2; |
| 1251 | mlx4_dbg(dev, "Communication vector bar:%d offset:0x%llx\n", |
| 1252 | fw->comm_bar, fw->comm_base); |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1253 | mlx4_dbg(dev, "FW size %d KB\n", fw->fw_pages >> 2); |
| 1254 | |
Eugenia Emantayev | ddd8a6c | 2013-04-23 06:06:48 +0000 | [diff] [blame] | 1255 | MLX4_GET(fw->clock_offset, outbox, QUERY_FW_CLOCK_OFFSET); |
| 1256 | MLX4_GET(fw->clock_bar, outbox, QUERY_FW_CLOCK_BAR); |
| 1257 | fw->clock_bar = (fw->clock_bar >> 6) * 2; |
| 1258 | mlx4_dbg(dev, "Internal clock bar:%d offset:0x%llx\n", |
| 1259 | fw->clock_bar, fw->clock_offset); |
| 1260 | |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1261 | /* |
| 1262 | * Round up number of system pages needed in case |
| 1263 | * MLX4_ICM_PAGE_SIZE < PAGE_SIZE. |
| 1264 | */ |
| 1265 | fw->fw_pages = |
| 1266 | ALIGN(fw->fw_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >> |
| 1267 | (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT); |
| 1268 | |
| 1269 | mlx4_dbg(dev, "Clear int @ %llx, BAR %d\n", |
| 1270 | (unsigned long long) fw->clr_int_base, fw->clr_int_bar); |
| 1271 | |
| 1272 | out: |
| 1273 | mlx4_free_cmd_mailbox(dev, mailbox); |
| 1274 | return err; |
| 1275 | } |
| 1276 | |
Jack Morgenstein | b91cb3e | 2012-05-30 09:14:53 +0000 | [diff] [blame] | 1277 | int mlx4_QUERY_FW_wrapper(struct mlx4_dev *dev, int slave, |
| 1278 | struct mlx4_vhcr *vhcr, |
| 1279 | struct mlx4_cmd_mailbox *inbox, |
| 1280 | struct mlx4_cmd_mailbox *outbox, |
| 1281 | struct mlx4_cmd_info *cmd) |
| 1282 | { |
| 1283 | u8 *outbuf; |
| 1284 | int err; |
| 1285 | |
| 1286 | outbuf = outbox->buf; |
| 1287 | err = mlx4_cmd_box(dev, 0, outbox->dma, 0, 0, MLX4_CMD_QUERY_FW, |
| 1288 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); |
| 1289 | if (err) |
| 1290 | return err; |
| 1291 | |
Jack Morgenstein | 752a50c | 2012-06-19 11:21:33 +0300 | [diff] [blame] | 1292 | /* for slaves, set pci PPF ID to invalid and zero out everything |
| 1293 | * else except FW version */ |
Jack Morgenstein | b91cb3e | 2012-05-30 09:14:53 +0000 | [diff] [blame] | 1294 | outbuf[0] = outbuf[1] = 0; |
| 1295 | memset(&outbuf[8], 0, QUERY_FW_OUT_SIZE - 8); |
Jack Morgenstein | 752a50c | 2012-06-19 11:21:33 +0300 | [diff] [blame] | 1296 | outbuf[QUERY_FW_PPF_ID] = MLX4_INVALID_SLAVE_ID; |
| 1297 | |
Jack Morgenstein | b91cb3e | 2012-05-30 09:14:53 +0000 | [diff] [blame] | 1298 | return 0; |
| 1299 | } |
| 1300 | |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1301 | static void get_board_id(void *vsd, char *board_id) |
| 1302 | { |
| 1303 | int i; |
| 1304 | |
| 1305 | #define VSD_OFFSET_SIG1 0x00 |
| 1306 | #define VSD_OFFSET_SIG2 0xde |
| 1307 | #define VSD_OFFSET_MLX_BOARD_ID 0xd0 |
| 1308 | #define VSD_OFFSET_TS_BOARD_ID 0x20 |
| 1309 | |
| 1310 | #define VSD_SIGNATURE_TOPSPIN 0x5ad |
| 1311 | |
| 1312 | memset(board_id, 0, MLX4_BOARD_ID_LEN); |
| 1313 | |
| 1314 | if (be16_to_cpup(vsd + VSD_OFFSET_SIG1) == VSD_SIGNATURE_TOPSPIN && |
| 1315 | be16_to_cpup(vsd + VSD_OFFSET_SIG2) == VSD_SIGNATURE_TOPSPIN) { |
| 1316 | strlcpy(board_id, vsd + VSD_OFFSET_TS_BOARD_ID, MLX4_BOARD_ID_LEN); |
| 1317 | } else { |
| 1318 | /* |
| 1319 | * The board ID is a string but the firmware byte |
| 1320 | * swaps each 4-byte word before passing it back to |
| 1321 | * us. Therefore we need to swab it before printing. |
| 1322 | */ |
| 1323 | for (i = 0; i < 4; ++i) |
| 1324 | ((u32 *) board_id)[i] = |
| 1325 | swab32(*(u32 *) (vsd + VSD_OFFSET_MLX_BOARD_ID + i * 4)); |
| 1326 | } |
| 1327 | } |
| 1328 | |
| 1329 | int mlx4_QUERY_ADAPTER(struct mlx4_dev *dev, struct mlx4_adapter *adapter) |
| 1330 | { |
| 1331 | struct mlx4_cmd_mailbox *mailbox; |
| 1332 | u32 *outbox; |
| 1333 | int err; |
| 1334 | |
| 1335 | #define QUERY_ADAPTER_OUT_SIZE 0x100 |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1336 | #define QUERY_ADAPTER_INTA_PIN_OFFSET 0x10 |
| 1337 | #define QUERY_ADAPTER_VSD_OFFSET 0x20 |
| 1338 | |
| 1339 | mailbox = mlx4_alloc_cmd_mailbox(dev); |
| 1340 | if (IS_ERR(mailbox)) |
| 1341 | return PTR_ERR(mailbox); |
| 1342 | outbox = mailbox->buf; |
| 1343 | |
| 1344 | err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_ADAPTER, |
Jack Morgenstein | f9baff5 | 2011-12-13 04:10:51 +0000 | [diff] [blame] | 1345 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1346 | if (err) |
| 1347 | goto out; |
| 1348 | |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1349 | MLX4_GET(adapter->inta_pin, outbox, QUERY_ADAPTER_INTA_PIN_OFFSET); |
| 1350 | |
| 1351 | get_board_id(outbox + QUERY_ADAPTER_VSD_OFFSET / 4, |
| 1352 | adapter->board_id); |
| 1353 | |
| 1354 | out: |
| 1355 | mlx4_free_cmd_mailbox(dev, mailbox); |
| 1356 | return err; |
| 1357 | } |
| 1358 | |
| 1359 | int mlx4_INIT_HCA(struct mlx4_dev *dev, struct mlx4_init_hca_param *param) |
| 1360 | { |
| 1361 | struct mlx4_cmd_mailbox *mailbox; |
| 1362 | __be32 *inbox; |
| 1363 | int err; |
| 1364 | |
| 1365 | #define INIT_HCA_IN_SIZE 0x200 |
| 1366 | #define INIT_HCA_VERSION_OFFSET 0x000 |
| 1367 | #define INIT_HCA_VERSION 2 |
Or Gerlitz | 7ffdf72 | 2013-12-23 16:09:43 +0200 | [diff] [blame] | 1368 | #define INIT_HCA_VXLAN_OFFSET 0x0c |
Eli Cohen | c57e20dcf | 2009-09-24 11:03:03 -0700 | [diff] [blame] | 1369 | #define INIT_HCA_CACHELINE_SZ_OFFSET 0x0e |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1370 | #define INIT_HCA_FLAGS_OFFSET 0x014 |
| 1371 | #define INIT_HCA_QPC_OFFSET 0x020 |
| 1372 | #define INIT_HCA_QPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x10) |
| 1373 | #define INIT_HCA_LOG_QP_OFFSET (INIT_HCA_QPC_OFFSET + 0x17) |
| 1374 | #define INIT_HCA_SRQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x28) |
| 1375 | #define INIT_HCA_LOG_SRQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x2f) |
| 1376 | #define INIT_HCA_CQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x30) |
| 1377 | #define INIT_HCA_LOG_CQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x37) |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 1378 | #define INIT_HCA_EQE_CQE_OFFSETS (INIT_HCA_QPC_OFFSET + 0x38) |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1379 | #define INIT_HCA_ALTC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x40) |
| 1380 | #define INIT_HCA_AUXC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x50) |
| 1381 | #define INIT_HCA_EQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x60) |
| 1382 | #define INIT_HCA_LOG_EQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x67) |
| 1383 | #define INIT_HCA_RDMARC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x70) |
| 1384 | #define INIT_HCA_LOG_RD_OFFSET (INIT_HCA_QPC_OFFSET + 0x77) |
| 1385 | #define INIT_HCA_MCAST_OFFSET 0x0c0 |
| 1386 | #define INIT_HCA_MC_BASE_OFFSET (INIT_HCA_MCAST_OFFSET + 0x00) |
| 1387 | #define INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x12) |
| 1388 | #define INIT_HCA_LOG_MC_HASH_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x16) |
Yevgeny Petrilin | 1679200 | 2011-03-22 22:38:31 +0000 | [diff] [blame] | 1389 | #define INIT_HCA_UC_STEERING_OFFSET (INIT_HCA_MCAST_OFFSET + 0x18) |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1390 | #define INIT_HCA_LOG_MC_TABLE_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x1b) |
Hadar Hen Zion | 0ff1fb6 | 2012-07-05 04:03:46 +0000 | [diff] [blame] | 1391 | #define INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN 0x6 |
| 1392 | #define INIT_HCA_FS_PARAM_OFFSET 0x1d0 |
| 1393 | #define INIT_HCA_FS_BASE_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x00) |
| 1394 | #define INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x12) |
| 1395 | #define INIT_HCA_FS_LOG_TABLE_SZ_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x1b) |
| 1396 | #define INIT_HCA_FS_ETH_BITS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x21) |
| 1397 | #define INIT_HCA_FS_ETH_NUM_ADDRS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x22) |
| 1398 | #define INIT_HCA_FS_IB_BITS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x25) |
| 1399 | #define INIT_HCA_FS_IB_NUM_ADDRS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x26) |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1400 | #define INIT_HCA_TPT_OFFSET 0x0f0 |
| 1401 | #define INIT_HCA_DMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x00) |
Shani Michaeli | e448834 | 2013-02-06 16:19:11 +0000 | [diff] [blame] | 1402 | #define INIT_HCA_TPT_MW_OFFSET (INIT_HCA_TPT_OFFSET + 0x08) |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1403 | #define INIT_HCA_LOG_MPT_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x0b) |
| 1404 | #define INIT_HCA_MTT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x10) |
| 1405 | #define INIT_HCA_CMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x18) |
| 1406 | #define INIT_HCA_UAR_OFFSET 0x120 |
| 1407 | #define INIT_HCA_LOG_UAR_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0a) |
| 1408 | #define INIT_HCA_UAR_PAGE_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0b) |
| 1409 | |
| 1410 | mailbox = mlx4_alloc_cmd_mailbox(dev); |
| 1411 | if (IS_ERR(mailbox)) |
| 1412 | return PTR_ERR(mailbox); |
| 1413 | inbox = mailbox->buf; |
| 1414 | |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1415 | *((u8 *) mailbox->buf + INIT_HCA_VERSION_OFFSET) = INIT_HCA_VERSION; |
| 1416 | |
Eli Cohen | c57e20dcf | 2009-09-24 11:03:03 -0700 | [diff] [blame] | 1417 | *((u8 *) mailbox->buf + INIT_HCA_CACHELINE_SZ_OFFSET) = |
| 1418 | (ilog2(cache_line_size()) - 4) << 5; |
| 1419 | |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1420 | #if defined(__LITTLE_ENDIAN) |
| 1421 | *(inbox + INIT_HCA_FLAGS_OFFSET / 4) &= ~cpu_to_be32(1 << 1); |
| 1422 | #elif defined(__BIG_ENDIAN) |
| 1423 | *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 1); |
| 1424 | #else |
| 1425 | #error Host endianness not defined |
| 1426 | #endif |
| 1427 | /* Check port for UD address vector: */ |
| 1428 | *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1); |
| 1429 | |
Eli Cohen | 8ff095e | 2008-04-16 21:01:10 -0700 | [diff] [blame] | 1430 | /* Enable IPoIB checksumming if we can: */ |
| 1431 | if (dev->caps.flags & MLX4_DEV_CAP_FLAG_IPOIB_CSUM) |
| 1432 | *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 3); |
| 1433 | |
Jack Morgenstein | 51f5f0e | 2008-07-22 14:19:37 -0700 | [diff] [blame] | 1434 | /* Enable QoS support if module parameter set */ |
| 1435 | if (enable_qos) |
| 1436 | *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 2); |
| 1437 | |
Or Gerlitz | f2a3f6a | 2011-06-15 14:47:14 +0000 | [diff] [blame] | 1438 | /* enable counters */ |
| 1439 | if (dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS) |
| 1440 | *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 4); |
| 1441 | |
Or Gerlitz | 08ff323 | 2012-10-21 14:59:24 +0000 | [diff] [blame] | 1442 | /* CX3 is capable of extending CQEs/EQEs from 32 to 64 bytes */ |
| 1443 | if (dev->caps.flags & MLX4_DEV_CAP_FLAG_64B_EQE) { |
| 1444 | *(inbox + INIT_HCA_EQE_CQE_OFFSETS / 4) |= cpu_to_be32(1 << 29); |
| 1445 | dev->caps.eqe_size = 64; |
| 1446 | dev->caps.eqe_factor = 1; |
| 1447 | } else { |
| 1448 | dev->caps.eqe_size = 32; |
| 1449 | dev->caps.eqe_factor = 0; |
| 1450 | } |
| 1451 | |
| 1452 | if (dev->caps.flags & MLX4_DEV_CAP_FLAG_64B_CQE) { |
| 1453 | *(inbox + INIT_HCA_EQE_CQE_OFFSETS / 4) |= cpu_to_be32(1 << 30); |
| 1454 | dev->caps.cqe_size = 64; |
| 1455 | dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_64B_CQE; |
| 1456 | } else { |
| 1457 | dev->caps.cqe_size = 32; |
| 1458 | } |
| 1459 | |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1460 | /* QPC/EEC/CQC/EQC/RDMARC attributes */ |
| 1461 | |
| 1462 | MLX4_PUT(inbox, param->qpc_base, INIT_HCA_QPC_BASE_OFFSET); |
| 1463 | MLX4_PUT(inbox, param->log_num_qps, INIT_HCA_LOG_QP_OFFSET); |
| 1464 | MLX4_PUT(inbox, param->srqc_base, INIT_HCA_SRQC_BASE_OFFSET); |
| 1465 | MLX4_PUT(inbox, param->log_num_srqs, INIT_HCA_LOG_SRQ_OFFSET); |
| 1466 | MLX4_PUT(inbox, param->cqc_base, INIT_HCA_CQC_BASE_OFFSET); |
| 1467 | MLX4_PUT(inbox, param->log_num_cqs, INIT_HCA_LOG_CQ_OFFSET); |
| 1468 | MLX4_PUT(inbox, param->altc_base, INIT_HCA_ALTC_BASE_OFFSET); |
| 1469 | MLX4_PUT(inbox, param->auxc_base, INIT_HCA_AUXC_BASE_OFFSET); |
| 1470 | MLX4_PUT(inbox, param->eqc_base, INIT_HCA_EQC_BASE_OFFSET); |
| 1471 | MLX4_PUT(inbox, param->log_num_eqs, INIT_HCA_LOG_EQ_OFFSET); |
| 1472 | MLX4_PUT(inbox, param->rdmarc_base, INIT_HCA_RDMARC_BASE_OFFSET); |
| 1473 | MLX4_PUT(inbox, param->log_rd_per_qp, INIT_HCA_LOG_RD_OFFSET); |
| 1474 | |
Hadar Hen Zion | 0ff1fb6 | 2012-07-05 04:03:46 +0000 | [diff] [blame] | 1475 | /* steering attributes */ |
| 1476 | if (dev->caps.steering_mode == |
| 1477 | MLX4_STEERING_MODE_DEVICE_MANAGED) { |
| 1478 | *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= |
| 1479 | cpu_to_be32(1 << |
| 1480 | INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN); |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1481 | |
Hadar Hen Zion | 0ff1fb6 | 2012-07-05 04:03:46 +0000 | [diff] [blame] | 1482 | MLX4_PUT(inbox, param->mc_base, INIT_HCA_FS_BASE_OFFSET); |
| 1483 | MLX4_PUT(inbox, param->log_mc_entry_sz, |
| 1484 | INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET); |
| 1485 | MLX4_PUT(inbox, param->log_mc_table_sz, |
| 1486 | INIT_HCA_FS_LOG_TABLE_SZ_OFFSET); |
| 1487 | /* Enable Ethernet flow steering |
| 1488 | * with udp unicast and tcp unicast |
| 1489 | */ |
Hadar Hen Zion | 23537b7 | 2013-01-30 23:07:09 +0000 | [diff] [blame] | 1490 | MLX4_PUT(inbox, (u8) (MLX4_FS_UDP_UC_EN | MLX4_FS_TCP_UC_EN), |
Hadar Hen Zion | 0ff1fb6 | 2012-07-05 04:03:46 +0000 | [diff] [blame] | 1491 | INIT_HCA_FS_ETH_BITS_OFFSET); |
| 1492 | MLX4_PUT(inbox, (u16) MLX4_FS_NUM_OF_L2_ADDR, |
| 1493 | INIT_HCA_FS_ETH_NUM_ADDRS_OFFSET); |
| 1494 | /* Enable IPoIB flow steering |
| 1495 | * with udp unicast and tcp unicast |
| 1496 | */ |
Hadar Hen Zion | 23537b7 | 2013-01-30 23:07:09 +0000 | [diff] [blame] | 1497 | MLX4_PUT(inbox, (u8) (MLX4_FS_UDP_UC_EN | MLX4_FS_TCP_UC_EN), |
Hadar Hen Zion | 0ff1fb6 | 2012-07-05 04:03:46 +0000 | [diff] [blame] | 1498 | INIT_HCA_FS_IB_BITS_OFFSET); |
| 1499 | MLX4_PUT(inbox, (u16) MLX4_FS_NUM_OF_L2_ADDR, |
| 1500 | INIT_HCA_FS_IB_NUM_ADDRS_OFFSET); |
| 1501 | } else { |
| 1502 | MLX4_PUT(inbox, param->mc_base, INIT_HCA_MC_BASE_OFFSET); |
| 1503 | MLX4_PUT(inbox, param->log_mc_entry_sz, |
| 1504 | INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET); |
| 1505 | MLX4_PUT(inbox, param->log_mc_hash_sz, |
| 1506 | INIT_HCA_LOG_MC_HASH_SZ_OFFSET); |
| 1507 | MLX4_PUT(inbox, param->log_mc_table_sz, |
| 1508 | INIT_HCA_LOG_MC_TABLE_SZ_OFFSET); |
| 1509 | if (dev->caps.steering_mode == MLX4_STEERING_MODE_B0) |
| 1510 | MLX4_PUT(inbox, (u8) (1 << 3), |
| 1511 | INIT_HCA_UC_STEERING_OFFSET); |
| 1512 | } |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1513 | |
| 1514 | /* TPT attributes */ |
| 1515 | |
| 1516 | MLX4_PUT(inbox, param->dmpt_base, INIT_HCA_DMPT_BASE_OFFSET); |
Shani Michaeli | e448834 | 2013-02-06 16:19:11 +0000 | [diff] [blame] | 1517 | MLX4_PUT(inbox, param->mw_enabled, INIT_HCA_TPT_MW_OFFSET); |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1518 | MLX4_PUT(inbox, param->log_mpt_sz, INIT_HCA_LOG_MPT_SZ_OFFSET); |
| 1519 | MLX4_PUT(inbox, param->mtt_base, INIT_HCA_MTT_BASE_OFFSET); |
| 1520 | MLX4_PUT(inbox, param->cmpt_base, INIT_HCA_CMPT_BASE_OFFSET); |
| 1521 | |
| 1522 | /* UAR attributes */ |
| 1523 | |
Jack Morgenstein | ab9c17a | 2011-12-13 04:18:30 +0000 | [diff] [blame] | 1524 | MLX4_PUT(inbox, param->uar_page_sz, INIT_HCA_UAR_PAGE_SZ_OFFSET); |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1525 | MLX4_PUT(inbox, param->log_uar_sz, INIT_HCA_LOG_UAR_SZ_OFFSET); |
| 1526 | |
Or Gerlitz | 7ffdf72 | 2013-12-23 16:09:43 +0200 | [diff] [blame] | 1527 | /* set parser VXLAN attributes */ |
| 1528 | if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS) { |
| 1529 | u8 parser_params = 0; |
| 1530 | MLX4_PUT(inbox, parser_params, INIT_HCA_VXLAN_OFFSET); |
| 1531 | } |
| 1532 | |
Jack Morgenstein | f9baff5 | 2011-12-13 04:10:51 +0000 | [diff] [blame] | 1533 | err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_INIT_HCA, 10000, |
| 1534 | MLX4_CMD_NATIVE); |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1535 | |
| 1536 | if (err) |
| 1537 | mlx4_err(dev, "INIT_HCA returns %d\n", err); |
| 1538 | |
| 1539 | mlx4_free_cmd_mailbox(dev, mailbox); |
| 1540 | return err; |
| 1541 | } |
| 1542 | |
Jack Morgenstein | ab9c17a | 2011-12-13 04:18:30 +0000 | [diff] [blame] | 1543 | int mlx4_QUERY_HCA(struct mlx4_dev *dev, |
| 1544 | struct mlx4_init_hca_param *param) |
| 1545 | { |
| 1546 | struct mlx4_cmd_mailbox *mailbox; |
| 1547 | __be32 *outbox; |
Jack Morgenstein | 7b8157b | 2012-12-06 17:11:59 +0000 | [diff] [blame] | 1548 | u32 dword_field; |
Jack Morgenstein | ab9c17a | 2011-12-13 04:18:30 +0000 | [diff] [blame] | 1549 | int err; |
Or Gerlitz | 08ff323 | 2012-10-21 14:59:24 +0000 | [diff] [blame] | 1550 | u8 byte_field; |
Jack Morgenstein | ab9c17a | 2011-12-13 04:18:30 +0000 | [diff] [blame] | 1551 | |
| 1552 | #define QUERY_HCA_GLOBAL_CAPS_OFFSET 0x04 |
Eugenia Emantayev | ddd8a6c | 2013-04-23 06:06:48 +0000 | [diff] [blame] | 1553 | #define QUERY_HCA_CORE_CLOCK_OFFSET 0x0c |
Jack Morgenstein | ab9c17a | 2011-12-13 04:18:30 +0000 | [diff] [blame] | 1554 | |
| 1555 | mailbox = mlx4_alloc_cmd_mailbox(dev); |
| 1556 | if (IS_ERR(mailbox)) |
| 1557 | return PTR_ERR(mailbox); |
| 1558 | outbox = mailbox->buf; |
| 1559 | |
| 1560 | err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, |
| 1561 | MLX4_CMD_QUERY_HCA, |
| 1562 | MLX4_CMD_TIME_CLASS_B, |
| 1563 | !mlx4_is_slave(dev)); |
| 1564 | if (err) |
| 1565 | goto out; |
| 1566 | |
| 1567 | MLX4_GET(param->global_caps, outbox, QUERY_HCA_GLOBAL_CAPS_OFFSET); |
Eugenia Emantayev | ddd8a6c | 2013-04-23 06:06:48 +0000 | [diff] [blame] | 1568 | MLX4_GET(param->hca_core_clock, outbox, QUERY_HCA_CORE_CLOCK_OFFSET); |
Jack Morgenstein | ab9c17a | 2011-12-13 04:18:30 +0000 | [diff] [blame] | 1569 | |
| 1570 | /* QPC/EEC/CQC/EQC/RDMARC attributes */ |
| 1571 | |
| 1572 | MLX4_GET(param->qpc_base, outbox, INIT_HCA_QPC_BASE_OFFSET); |
| 1573 | MLX4_GET(param->log_num_qps, outbox, INIT_HCA_LOG_QP_OFFSET); |
| 1574 | MLX4_GET(param->srqc_base, outbox, INIT_HCA_SRQC_BASE_OFFSET); |
| 1575 | MLX4_GET(param->log_num_srqs, outbox, INIT_HCA_LOG_SRQ_OFFSET); |
| 1576 | MLX4_GET(param->cqc_base, outbox, INIT_HCA_CQC_BASE_OFFSET); |
| 1577 | MLX4_GET(param->log_num_cqs, outbox, INIT_HCA_LOG_CQ_OFFSET); |
| 1578 | MLX4_GET(param->altc_base, outbox, INIT_HCA_ALTC_BASE_OFFSET); |
| 1579 | MLX4_GET(param->auxc_base, outbox, INIT_HCA_AUXC_BASE_OFFSET); |
| 1580 | MLX4_GET(param->eqc_base, outbox, INIT_HCA_EQC_BASE_OFFSET); |
| 1581 | MLX4_GET(param->log_num_eqs, outbox, INIT_HCA_LOG_EQ_OFFSET); |
| 1582 | MLX4_GET(param->rdmarc_base, outbox, INIT_HCA_RDMARC_BASE_OFFSET); |
| 1583 | MLX4_GET(param->log_rd_per_qp, outbox, INIT_HCA_LOG_RD_OFFSET); |
| 1584 | |
Jack Morgenstein | 7b8157b | 2012-12-06 17:11:59 +0000 | [diff] [blame] | 1585 | MLX4_GET(dword_field, outbox, INIT_HCA_FLAGS_OFFSET); |
| 1586 | if (dword_field & (1 << INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN)) { |
| 1587 | param->steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED; |
| 1588 | } else { |
| 1589 | MLX4_GET(byte_field, outbox, INIT_HCA_UC_STEERING_OFFSET); |
| 1590 | if (byte_field & 0x8) |
| 1591 | param->steering_mode = MLX4_STEERING_MODE_B0; |
| 1592 | else |
| 1593 | param->steering_mode = MLX4_STEERING_MODE_A0; |
| 1594 | } |
Hadar Hen Zion | 0ff1fb6 | 2012-07-05 04:03:46 +0000 | [diff] [blame] | 1595 | /* steering attributes */ |
Jack Morgenstein | 7b8157b | 2012-12-06 17:11:59 +0000 | [diff] [blame] | 1596 | if (param->steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) { |
Hadar Hen Zion | 0ff1fb6 | 2012-07-05 04:03:46 +0000 | [diff] [blame] | 1597 | MLX4_GET(param->mc_base, outbox, INIT_HCA_FS_BASE_OFFSET); |
| 1598 | MLX4_GET(param->log_mc_entry_sz, outbox, |
| 1599 | INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET); |
| 1600 | MLX4_GET(param->log_mc_table_sz, outbox, |
| 1601 | INIT_HCA_FS_LOG_TABLE_SZ_OFFSET); |
| 1602 | } else { |
| 1603 | MLX4_GET(param->mc_base, outbox, INIT_HCA_MC_BASE_OFFSET); |
| 1604 | MLX4_GET(param->log_mc_entry_sz, outbox, |
| 1605 | INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET); |
| 1606 | MLX4_GET(param->log_mc_hash_sz, outbox, |
| 1607 | INIT_HCA_LOG_MC_HASH_SZ_OFFSET); |
| 1608 | MLX4_GET(param->log_mc_table_sz, outbox, |
| 1609 | INIT_HCA_LOG_MC_TABLE_SZ_OFFSET); |
| 1610 | } |
Jack Morgenstein | ab9c17a | 2011-12-13 04:18:30 +0000 | [diff] [blame] | 1611 | |
Or Gerlitz | 08ff323 | 2012-10-21 14:59:24 +0000 | [diff] [blame] | 1612 | /* CX3 is capable of extending CQEs/EQEs from 32 to 64 bytes */ |
| 1613 | MLX4_GET(byte_field, outbox, INIT_HCA_EQE_CQE_OFFSETS); |
| 1614 | if (byte_field & 0x20) /* 64-bytes eqe enabled */ |
| 1615 | param->dev_cap_enabled |= MLX4_DEV_CAP_64B_EQE_ENABLED; |
| 1616 | if (byte_field & 0x40) /* 64-bytes cqe enabled */ |
| 1617 | param->dev_cap_enabled |= MLX4_DEV_CAP_64B_CQE_ENABLED; |
| 1618 | |
Jack Morgenstein | ab9c17a | 2011-12-13 04:18:30 +0000 | [diff] [blame] | 1619 | /* TPT attributes */ |
| 1620 | |
| 1621 | MLX4_GET(param->dmpt_base, outbox, INIT_HCA_DMPT_BASE_OFFSET); |
Shani Michaeli | e448834 | 2013-02-06 16:19:11 +0000 | [diff] [blame] | 1622 | MLX4_GET(param->mw_enabled, outbox, INIT_HCA_TPT_MW_OFFSET); |
Jack Morgenstein | ab9c17a | 2011-12-13 04:18:30 +0000 | [diff] [blame] | 1623 | MLX4_GET(param->log_mpt_sz, outbox, INIT_HCA_LOG_MPT_SZ_OFFSET); |
| 1624 | MLX4_GET(param->mtt_base, outbox, INIT_HCA_MTT_BASE_OFFSET); |
| 1625 | MLX4_GET(param->cmpt_base, outbox, INIT_HCA_CMPT_BASE_OFFSET); |
| 1626 | |
| 1627 | /* UAR attributes */ |
| 1628 | |
| 1629 | MLX4_GET(param->uar_page_sz, outbox, INIT_HCA_UAR_PAGE_SZ_OFFSET); |
| 1630 | MLX4_GET(param->log_uar_sz, outbox, INIT_HCA_LOG_UAR_SZ_OFFSET); |
| 1631 | |
| 1632 | out: |
| 1633 | mlx4_free_cmd_mailbox(dev, mailbox); |
| 1634 | |
| 1635 | return err; |
| 1636 | } |
| 1637 | |
Jack Morgenstein | 980e900 | 2012-08-03 08:40:53 +0000 | [diff] [blame] | 1638 | /* for IB-type ports only in SRIOV mode. Checks that both proxy QP0 |
| 1639 | * and real QP0 are active, so that the paravirtualized QP0 is ready |
| 1640 | * to operate */ |
| 1641 | static int check_qp0_state(struct mlx4_dev *dev, int function, int port) |
| 1642 | { |
| 1643 | struct mlx4_priv *priv = mlx4_priv(dev); |
| 1644 | /* irrelevant if not infiniband */ |
| 1645 | if (priv->mfunc.master.qp0_state[port].proxy_qp0_active && |
| 1646 | priv->mfunc.master.qp0_state[port].qp0_active) |
| 1647 | return 1; |
| 1648 | return 0; |
| 1649 | } |
| 1650 | |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 1651 | int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave, |
| 1652 | struct mlx4_vhcr *vhcr, |
| 1653 | struct mlx4_cmd_mailbox *inbox, |
| 1654 | struct mlx4_cmd_mailbox *outbox, |
| 1655 | struct mlx4_cmd_info *cmd) |
| 1656 | { |
| 1657 | struct mlx4_priv *priv = mlx4_priv(dev); |
Matan Barak | 449fc48 | 2014-03-19 18:11:52 +0200 | [diff] [blame] | 1658 | int port = mlx4_slave_convert_port(dev, slave, vhcr->in_modifier); |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 1659 | int err; |
| 1660 | |
Matan Barak | 449fc48 | 2014-03-19 18:11:52 +0200 | [diff] [blame] | 1661 | if (port < 0) |
| 1662 | return -EINVAL; |
| 1663 | |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 1664 | if (priv->mfunc.master.slave_state[slave].init_port_mask & (1 << port)) |
| 1665 | return 0; |
| 1666 | |
Jack Morgenstein | 980e900 | 2012-08-03 08:40:53 +0000 | [diff] [blame] | 1667 | if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB) { |
| 1668 | /* Enable port only if it was previously disabled */ |
| 1669 | if (!priv->mfunc.master.init_port_ref[port]) { |
| 1670 | err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT, |
| 1671 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); |
| 1672 | if (err) |
| 1673 | return err; |
| 1674 | } |
| 1675 | priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port); |
| 1676 | } else { |
| 1677 | if (slave == mlx4_master_func_num(dev)) { |
| 1678 | if (check_qp0_state(dev, slave, port) && |
| 1679 | !priv->mfunc.master.qp0_state[port].port_active) { |
| 1680 | err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT, |
| 1681 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); |
| 1682 | if (err) |
| 1683 | return err; |
| 1684 | priv->mfunc.master.qp0_state[port].port_active = 1; |
| 1685 | priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port); |
| 1686 | } |
| 1687 | } else |
| 1688 | priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port); |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 1689 | } |
| 1690 | ++priv->mfunc.master.init_port_ref[port]; |
| 1691 | return 0; |
| 1692 | } |
| 1693 | |
Roland Dreier | 5ae2a7a | 2007-06-18 08:15:02 -0700 | [diff] [blame] | 1694 | int mlx4_INIT_PORT(struct mlx4_dev *dev, int port) |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1695 | { |
| 1696 | struct mlx4_cmd_mailbox *mailbox; |
| 1697 | u32 *inbox; |
| 1698 | int err; |
| 1699 | u32 flags; |
Roland Dreier | 5ae2a7a | 2007-06-18 08:15:02 -0700 | [diff] [blame] | 1700 | u16 field; |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1701 | |
Roland Dreier | 5ae2a7a | 2007-06-18 08:15:02 -0700 | [diff] [blame] | 1702 | if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) { |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1703 | #define INIT_PORT_IN_SIZE 256 |
| 1704 | #define INIT_PORT_FLAGS_OFFSET 0x00 |
| 1705 | #define INIT_PORT_FLAG_SIG (1 << 18) |
| 1706 | #define INIT_PORT_FLAG_NG (1 << 17) |
| 1707 | #define INIT_PORT_FLAG_G0 (1 << 16) |
| 1708 | #define INIT_PORT_VL_SHIFT 4 |
| 1709 | #define INIT_PORT_PORT_WIDTH_SHIFT 8 |
| 1710 | #define INIT_PORT_MTU_OFFSET 0x04 |
| 1711 | #define INIT_PORT_MAX_GID_OFFSET 0x06 |
| 1712 | #define INIT_PORT_MAX_PKEY_OFFSET 0x0a |
| 1713 | #define INIT_PORT_GUID0_OFFSET 0x10 |
| 1714 | #define INIT_PORT_NODE_GUID_OFFSET 0x18 |
| 1715 | #define INIT_PORT_SI_GUID_OFFSET 0x20 |
| 1716 | |
Roland Dreier | 5ae2a7a | 2007-06-18 08:15:02 -0700 | [diff] [blame] | 1717 | mailbox = mlx4_alloc_cmd_mailbox(dev); |
| 1718 | if (IS_ERR(mailbox)) |
| 1719 | return PTR_ERR(mailbox); |
| 1720 | inbox = mailbox->buf; |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1721 | |
Roland Dreier | 5ae2a7a | 2007-06-18 08:15:02 -0700 | [diff] [blame] | 1722 | flags = 0; |
| 1723 | flags |= (dev->caps.vl_cap[port] & 0xf) << INIT_PORT_VL_SHIFT; |
| 1724 | flags |= (dev->caps.port_width_cap[port] & 0xf) << INIT_PORT_PORT_WIDTH_SHIFT; |
| 1725 | MLX4_PUT(inbox, flags, INIT_PORT_FLAGS_OFFSET); |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1726 | |
Yevgeny Petrilin | b79acb4 | 2008-10-22 10:56:48 -0700 | [diff] [blame] | 1727 | field = 128 << dev->caps.ib_mtu_cap[port]; |
Roland Dreier | 5ae2a7a | 2007-06-18 08:15:02 -0700 | [diff] [blame] | 1728 | MLX4_PUT(inbox, field, INIT_PORT_MTU_OFFSET); |
| 1729 | field = dev->caps.gid_table_len[port]; |
| 1730 | MLX4_PUT(inbox, field, INIT_PORT_MAX_GID_OFFSET); |
| 1731 | field = dev->caps.pkey_table_len[port]; |
| 1732 | MLX4_PUT(inbox, field, INIT_PORT_MAX_PKEY_OFFSET); |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1733 | |
Roland Dreier | 5ae2a7a | 2007-06-18 08:15:02 -0700 | [diff] [blame] | 1734 | err = mlx4_cmd(dev, mailbox->dma, port, 0, MLX4_CMD_INIT_PORT, |
Jack Morgenstein | f9baff5 | 2011-12-13 04:10:51 +0000 | [diff] [blame] | 1735 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1736 | |
Roland Dreier | 5ae2a7a | 2007-06-18 08:15:02 -0700 | [diff] [blame] | 1737 | mlx4_free_cmd_mailbox(dev, mailbox); |
| 1738 | } else |
| 1739 | err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT, |
Jack Morgenstein | f9baff5 | 2011-12-13 04:10:51 +0000 | [diff] [blame] | 1740 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED); |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1741 | |
| 1742 | return err; |
| 1743 | } |
| 1744 | EXPORT_SYMBOL_GPL(mlx4_INIT_PORT); |
| 1745 | |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 1746 | int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave, |
| 1747 | struct mlx4_vhcr *vhcr, |
| 1748 | struct mlx4_cmd_mailbox *inbox, |
| 1749 | struct mlx4_cmd_mailbox *outbox, |
| 1750 | struct mlx4_cmd_info *cmd) |
| 1751 | { |
| 1752 | struct mlx4_priv *priv = mlx4_priv(dev); |
Matan Barak | 449fc48 | 2014-03-19 18:11:52 +0200 | [diff] [blame] | 1753 | int port = mlx4_slave_convert_port(dev, slave, vhcr->in_modifier); |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 1754 | int err; |
| 1755 | |
Matan Barak | 449fc48 | 2014-03-19 18:11:52 +0200 | [diff] [blame] | 1756 | if (port < 0) |
| 1757 | return -EINVAL; |
| 1758 | |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 1759 | if (!(priv->mfunc.master.slave_state[slave].init_port_mask & |
| 1760 | (1 << port))) |
| 1761 | return 0; |
| 1762 | |
Jack Morgenstein | 980e900 | 2012-08-03 08:40:53 +0000 | [diff] [blame] | 1763 | if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB) { |
| 1764 | if (priv->mfunc.master.init_port_ref[port] == 1) { |
| 1765 | err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, |
| 1766 | 1000, MLX4_CMD_NATIVE); |
| 1767 | if (err) |
| 1768 | return err; |
| 1769 | } |
| 1770 | priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port); |
| 1771 | } else { |
| 1772 | /* infiniband port */ |
| 1773 | if (slave == mlx4_master_func_num(dev)) { |
| 1774 | if (!priv->mfunc.master.qp0_state[port].qp0_active && |
| 1775 | priv->mfunc.master.qp0_state[port].port_active) { |
| 1776 | err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, |
| 1777 | 1000, MLX4_CMD_NATIVE); |
| 1778 | if (err) |
| 1779 | return err; |
| 1780 | priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port); |
| 1781 | priv->mfunc.master.qp0_state[port].port_active = 0; |
| 1782 | } |
| 1783 | } else |
| 1784 | priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port); |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 1785 | } |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 1786 | --priv->mfunc.master.init_port_ref[port]; |
| 1787 | return 0; |
| 1788 | } |
| 1789 | |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1790 | int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port) |
| 1791 | { |
Jack Morgenstein | f9baff5 | 2011-12-13 04:10:51 +0000 | [diff] [blame] | 1792 | return mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, 1000, |
| 1793 | MLX4_CMD_WRAPPED); |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1794 | } |
| 1795 | EXPORT_SYMBOL_GPL(mlx4_CLOSE_PORT); |
| 1796 | |
| 1797 | int mlx4_CLOSE_HCA(struct mlx4_dev *dev, int panic) |
| 1798 | { |
Jack Morgenstein | f9baff5 | 2011-12-13 04:10:51 +0000 | [diff] [blame] | 1799 | return mlx4_cmd(dev, 0, 0, panic, MLX4_CMD_CLOSE_HCA, 1000, |
| 1800 | MLX4_CMD_NATIVE); |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1801 | } |
| 1802 | |
Or Gerlitz | d18f141 | 2014-03-27 14:02:03 +0200 | [diff] [blame] | 1803 | struct mlx4_config_dev { |
| 1804 | __be32 update_flags; |
| 1805 | __be32 rsdv1[3]; |
| 1806 | __be16 vxlan_udp_dport; |
| 1807 | __be16 rsvd2; |
| 1808 | }; |
| 1809 | |
| 1810 | #define MLX4_VXLAN_UDP_DPORT (1 << 0) |
| 1811 | |
| 1812 | static int mlx4_CONFIG_DEV(struct mlx4_dev *dev, struct mlx4_config_dev *config_dev) |
| 1813 | { |
| 1814 | int err; |
| 1815 | struct mlx4_cmd_mailbox *mailbox; |
| 1816 | |
| 1817 | mailbox = mlx4_alloc_cmd_mailbox(dev); |
| 1818 | if (IS_ERR(mailbox)) |
| 1819 | return PTR_ERR(mailbox); |
| 1820 | |
| 1821 | memcpy(mailbox->buf, config_dev, sizeof(*config_dev)); |
| 1822 | |
| 1823 | err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_CONFIG_DEV, |
| 1824 | MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); |
| 1825 | |
| 1826 | mlx4_free_cmd_mailbox(dev, mailbox); |
| 1827 | return err; |
| 1828 | } |
| 1829 | |
| 1830 | int mlx4_config_vxlan_port(struct mlx4_dev *dev, __be16 udp_port) |
| 1831 | { |
| 1832 | struct mlx4_config_dev config_dev; |
| 1833 | |
| 1834 | memset(&config_dev, 0, sizeof(config_dev)); |
| 1835 | config_dev.update_flags = cpu_to_be32(MLX4_VXLAN_UDP_DPORT); |
| 1836 | config_dev.vxlan_udp_dport = udp_port; |
| 1837 | |
| 1838 | return mlx4_CONFIG_DEV(dev, &config_dev); |
| 1839 | } |
| 1840 | EXPORT_SYMBOL_GPL(mlx4_config_vxlan_port); |
| 1841 | |
| 1842 | |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1843 | int mlx4_SET_ICM_SIZE(struct mlx4_dev *dev, u64 icm_size, u64 *aux_pages) |
| 1844 | { |
| 1845 | int ret = mlx4_cmd_imm(dev, icm_size, aux_pages, 0, 0, |
| 1846 | MLX4_CMD_SET_ICM_SIZE, |
Jack Morgenstein | f9baff5 | 2011-12-13 04:10:51 +0000 | [diff] [blame] | 1847 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1848 | if (ret) |
| 1849 | return ret; |
| 1850 | |
| 1851 | /* |
| 1852 | * Round up number of system pages needed in case |
| 1853 | * MLX4_ICM_PAGE_SIZE < PAGE_SIZE. |
| 1854 | */ |
| 1855 | *aux_pages = ALIGN(*aux_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >> |
| 1856 | (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT); |
| 1857 | |
| 1858 | return 0; |
| 1859 | } |
| 1860 | |
| 1861 | int mlx4_NOP(struct mlx4_dev *dev) |
| 1862 | { |
| 1863 | /* Input modifier of 0x1f means "finish as soon as possible." */ |
Jack Morgenstein | f9baff5 | 2011-12-13 04:10:51 +0000 | [diff] [blame] | 1864 | return mlx4_cmd(dev, 0, 0x1f, 0, MLX4_CMD_NOP, 100, MLX4_CMD_NATIVE); |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1865 | } |
Yevgeny Petrilin | 14c07b1 | 2011-03-22 22:37:59 +0000 | [diff] [blame] | 1866 | |
Hadar Hen Zion | 8e1a28e | 2013-12-19 21:20:12 +0200 | [diff] [blame] | 1867 | int mlx4_get_phys_port_id(struct mlx4_dev *dev) |
| 1868 | { |
| 1869 | u8 port; |
| 1870 | u32 *outbox; |
| 1871 | struct mlx4_cmd_mailbox *mailbox; |
| 1872 | u32 in_mod; |
| 1873 | u32 guid_hi, guid_lo; |
| 1874 | int err, ret = 0; |
| 1875 | #define MOD_STAT_CFG_PORT_OFFSET 8 |
| 1876 | #define MOD_STAT_CFG_GUID_H 0X14 |
| 1877 | #define MOD_STAT_CFG_GUID_L 0X1c |
| 1878 | |
| 1879 | mailbox = mlx4_alloc_cmd_mailbox(dev); |
| 1880 | if (IS_ERR(mailbox)) |
| 1881 | return PTR_ERR(mailbox); |
| 1882 | outbox = mailbox->buf; |
| 1883 | |
| 1884 | for (port = 1; port <= dev->caps.num_ports; port++) { |
| 1885 | in_mod = port << MOD_STAT_CFG_PORT_OFFSET; |
| 1886 | err = mlx4_cmd_box(dev, 0, mailbox->dma, in_mod, 0x2, |
| 1887 | MLX4_CMD_MOD_STAT_CFG, MLX4_CMD_TIME_CLASS_A, |
| 1888 | MLX4_CMD_NATIVE); |
| 1889 | if (err) { |
| 1890 | mlx4_err(dev, "Fail to get port %d uplink guid\n", |
| 1891 | port); |
| 1892 | ret = err; |
| 1893 | } else { |
| 1894 | MLX4_GET(guid_hi, outbox, MOD_STAT_CFG_GUID_H); |
| 1895 | MLX4_GET(guid_lo, outbox, MOD_STAT_CFG_GUID_L); |
| 1896 | dev->caps.phys_port_id[port] = (u64)guid_lo | |
| 1897 | (u64)guid_hi << 32; |
| 1898 | } |
| 1899 | } |
| 1900 | mlx4_free_cmd_mailbox(dev, mailbox); |
| 1901 | return ret; |
| 1902 | } |
| 1903 | |
Yevgeny Petrilin | 14c07b1 | 2011-03-22 22:37:59 +0000 | [diff] [blame] | 1904 | #define MLX4_WOL_SETUP_MODE (5 << 28) |
| 1905 | int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port) |
| 1906 | { |
| 1907 | u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8; |
| 1908 | |
| 1909 | return mlx4_cmd_imm(dev, 0, config, in_mod, 0x3, |
Jack Morgenstein | f9baff5 | 2011-12-13 04:10:51 +0000 | [diff] [blame] | 1910 | MLX4_CMD_MOD_STAT_CFG, MLX4_CMD_TIME_CLASS_A, |
| 1911 | MLX4_CMD_NATIVE); |
Yevgeny Petrilin | 14c07b1 | 2011-03-22 22:37:59 +0000 | [diff] [blame] | 1912 | } |
| 1913 | EXPORT_SYMBOL_GPL(mlx4_wol_read); |
| 1914 | |
| 1915 | int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port) |
| 1916 | { |
| 1917 | u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8; |
| 1918 | |
| 1919 | return mlx4_cmd(dev, config, in_mod, 0x1, MLX4_CMD_MOD_STAT_CFG, |
Jack Morgenstein | f9baff5 | 2011-12-13 04:10:51 +0000 | [diff] [blame] | 1920 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); |
Yevgeny Petrilin | 14c07b1 | 2011-03-22 22:37:59 +0000 | [diff] [blame] | 1921 | } |
| 1922 | EXPORT_SYMBOL_GPL(mlx4_wol_write); |
Yevgeny Petrilin | fe6f700 | 2013-07-28 18:54:21 +0300 | [diff] [blame] | 1923 | |
| 1924 | enum { |
| 1925 | ADD_TO_MCG = 0x26, |
| 1926 | }; |
| 1927 | |
| 1928 | |
| 1929 | void mlx4_opreq_action(struct work_struct *work) |
| 1930 | { |
| 1931 | struct mlx4_priv *priv = container_of(work, struct mlx4_priv, |
| 1932 | opreq_task); |
| 1933 | struct mlx4_dev *dev = &priv->dev; |
| 1934 | int num_tasks = atomic_read(&priv->opreq_count); |
| 1935 | struct mlx4_cmd_mailbox *mailbox; |
| 1936 | struct mlx4_mgm *mgm; |
| 1937 | u32 *outbox; |
| 1938 | u32 modifier; |
| 1939 | u16 token; |
Yevgeny Petrilin | fe6f700 | 2013-07-28 18:54:21 +0300 | [diff] [blame] | 1940 | u16 type; |
| 1941 | int err; |
| 1942 | u32 num_qps; |
| 1943 | struct mlx4_qp qp; |
| 1944 | int i; |
| 1945 | u8 rem_mcg; |
| 1946 | u8 prot; |
| 1947 | |
| 1948 | #define GET_OP_REQ_MODIFIER_OFFSET 0x08 |
| 1949 | #define GET_OP_REQ_TOKEN_OFFSET 0x14 |
| 1950 | #define GET_OP_REQ_TYPE_OFFSET 0x1a |
| 1951 | #define GET_OP_REQ_DATA_OFFSET 0x20 |
| 1952 | |
| 1953 | mailbox = mlx4_alloc_cmd_mailbox(dev); |
| 1954 | if (IS_ERR(mailbox)) { |
| 1955 | mlx4_err(dev, "Failed to allocate mailbox for GET_OP_REQ\n"); |
| 1956 | return; |
| 1957 | } |
| 1958 | outbox = mailbox->buf; |
| 1959 | |
| 1960 | while (num_tasks) { |
| 1961 | err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, |
| 1962 | MLX4_CMD_GET_OP_REQ, MLX4_CMD_TIME_CLASS_A, |
| 1963 | MLX4_CMD_NATIVE); |
| 1964 | if (err) { |
Masanari Iida | 6d3be30 | 2013-09-30 23:19:09 +0900 | [diff] [blame] | 1965 | mlx4_err(dev, "Failed to retrieve required operation: %d\n", |
Yevgeny Petrilin | fe6f700 | 2013-07-28 18:54:21 +0300 | [diff] [blame] | 1966 | err); |
| 1967 | return; |
| 1968 | } |
| 1969 | MLX4_GET(modifier, outbox, GET_OP_REQ_MODIFIER_OFFSET); |
| 1970 | MLX4_GET(token, outbox, GET_OP_REQ_TOKEN_OFFSET); |
| 1971 | MLX4_GET(type, outbox, GET_OP_REQ_TYPE_OFFSET); |
Yevgeny Petrilin | fe6f700 | 2013-07-28 18:54:21 +0300 | [diff] [blame] | 1972 | type &= 0xfff; |
| 1973 | |
| 1974 | switch (type) { |
| 1975 | case ADD_TO_MCG: |
| 1976 | if (dev->caps.steering_mode == |
| 1977 | MLX4_STEERING_MODE_DEVICE_MANAGED) { |
| 1978 | mlx4_warn(dev, "ADD MCG operation is not supported in DEVICE_MANAGED steering mode\n"); |
| 1979 | err = EPERM; |
| 1980 | break; |
| 1981 | } |
| 1982 | mgm = (struct mlx4_mgm *)((u8 *)(outbox) + |
| 1983 | GET_OP_REQ_DATA_OFFSET); |
| 1984 | num_qps = be32_to_cpu(mgm->members_count) & |
| 1985 | MGM_QPN_MASK; |
| 1986 | rem_mcg = ((u8 *)(&mgm->members_count))[0] & 1; |
| 1987 | prot = ((u8 *)(&mgm->members_count))[0] >> 6; |
| 1988 | |
| 1989 | for (i = 0; i < num_qps; i++) { |
| 1990 | qp.qpn = be32_to_cpu(mgm->qp[i]); |
| 1991 | if (rem_mcg) |
| 1992 | err = mlx4_multicast_detach(dev, &qp, |
| 1993 | mgm->gid, |
| 1994 | prot, 0); |
| 1995 | else |
| 1996 | err = mlx4_multicast_attach(dev, &qp, |
| 1997 | mgm->gid, |
| 1998 | mgm->gid[5] |
| 1999 | , 0, prot, |
| 2000 | NULL); |
| 2001 | if (err) |
| 2002 | break; |
| 2003 | } |
| 2004 | break; |
| 2005 | default: |
| 2006 | mlx4_warn(dev, "Bad type for required operation\n"); |
| 2007 | err = EINVAL; |
| 2008 | break; |
| 2009 | } |
Eyal Perry | 28d222b | 2014-03-02 10:25:03 +0200 | [diff] [blame] | 2010 | err = mlx4_cmd(dev, 0, ((u32) err | |
| 2011 | (__force u32)cpu_to_be32(token) << 16), |
Yevgeny Petrilin | fe6f700 | 2013-07-28 18:54:21 +0300 | [diff] [blame] | 2012 | 1, MLX4_CMD_GET_OP_REQ, MLX4_CMD_TIME_CLASS_A, |
| 2013 | MLX4_CMD_NATIVE); |
| 2014 | if (err) { |
| 2015 | mlx4_err(dev, "Failed to acknowledge required request: %d\n", |
| 2016 | err); |
| 2017 | goto out; |
| 2018 | } |
| 2019 | memset(outbox, 0, 0xffc); |
| 2020 | num_tasks = atomic_dec_return(&priv->opreq_count); |
| 2021 | } |
| 2022 | |
| 2023 | out: |
| 2024 | mlx4_free_cmd_mailbox(dev, mailbox); |
| 2025 | } |
Jack Morgenstein | 114840c | 2014-06-01 11:53:50 +0300 | [diff] [blame] | 2026 | |
| 2027 | static int mlx4_check_smp_firewall_active(struct mlx4_dev *dev, |
| 2028 | struct mlx4_cmd_mailbox *mailbox) |
| 2029 | { |
| 2030 | #define MLX4_CMD_MAD_DEMUX_SET_ATTR_OFFSET 0x10 |
| 2031 | #define MLX4_CMD_MAD_DEMUX_GETRESP_ATTR_OFFSET 0x20 |
| 2032 | #define MLX4_CMD_MAD_DEMUX_TRAP_ATTR_OFFSET 0x40 |
| 2033 | #define MLX4_CMD_MAD_DEMUX_TRAP_REPRESS_ATTR_OFFSET 0x70 |
| 2034 | |
| 2035 | u32 set_attr_mask, getresp_attr_mask; |
| 2036 | u32 trap_attr_mask, traprepress_attr_mask; |
| 2037 | |
| 2038 | MLX4_GET(set_attr_mask, mailbox->buf, |
| 2039 | MLX4_CMD_MAD_DEMUX_SET_ATTR_OFFSET); |
| 2040 | mlx4_dbg(dev, "SMP firewall set_attribute_mask = 0x%x\n", |
| 2041 | set_attr_mask); |
| 2042 | |
| 2043 | MLX4_GET(getresp_attr_mask, mailbox->buf, |
| 2044 | MLX4_CMD_MAD_DEMUX_GETRESP_ATTR_OFFSET); |
| 2045 | mlx4_dbg(dev, "SMP firewall getresp_attribute_mask = 0x%x\n", |
| 2046 | getresp_attr_mask); |
| 2047 | |
| 2048 | MLX4_GET(trap_attr_mask, mailbox->buf, |
| 2049 | MLX4_CMD_MAD_DEMUX_TRAP_ATTR_OFFSET); |
| 2050 | mlx4_dbg(dev, "SMP firewall trap_attribute_mask = 0x%x\n", |
| 2051 | trap_attr_mask); |
| 2052 | |
| 2053 | MLX4_GET(traprepress_attr_mask, mailbox->buf, |
| 2054 | MLX4_CMD_MAD_DEMUX_TRAP_REPRESS_ATTR_OFFSET); |
| 2055 | mlx4_dbg(dev, "SMP firewall traprepress_attribute_mask = 0x%x\n", |
| 2056 | traprepress_attr_mask); |
| 2057 | |
| 2058 | if (set_attr_mask && getresp_attr_mask && trap_attr_mask && |
| 2059 | traprepress_attr_mask) |
| 2060 | return 1; |
| 2061 | |
| 2062 | return 0; |
| 2063 | } |
| 2064 | |
| 2065 | int mlx4_config_mad_demux(struct mlx4_dev *dev) |
| 2066 | { |
| 2067 | struct mlx4_cmd_mailbox *mailbox; |
| 2068 | int secure_host_active; |
| 2069 | int err; |
| 2070 | |
| 2071 | /* Check if mad_demux is supported */ |
| 2072 | if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_MAD_DEMUX)) |
| 2073 | return 0; |
| 2074 | |
| 2075 | mailbox = mlx4_alloc_cmd_mailbox(dev); |
| 2076 | if (IS_ERR(mailbox)) { |
| 2077 | mlx4_warn(dev, "Failed to allocate mailbox for cmd MAD_DEMUX"); |
| 2078 | return -ENOMEM; |
| 2079 | } |
| 2080 | |
| 2081 | /* Query mad_demux to find out which MADs are handled by internal sma */ |
| 2082 | err = mlx4_cmd_box(dev, 0, mailbox->dma, 0x01 /* subn mgmt class */, |
| 2083 | MLX4_CMD_MAD_DEMUX_QUERY_RESTR, MLX4_CMD_MAD_DEMUX, |
| 2084 | MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); |
| 2085 | if (err) { |
| 2086 | mlx4_warn(dev, "MLX4_CMD_MAD_DEMUX: query restrictions failed (%d)\n", |
| 2087 | err); |
| 2088 | goto out; |
| 2089 | } |
| 2090 | |
| 2091 | secure_host_active = mlx4_check_smp_firewall_active(dev, mailbox); |
| 2092 | |
| 2093 | /* Config mad_demux to handle all MADs returned by the query above */ |
| 2094 | err = mlx4_cmd(dev, mailbox->dma, 0x01 /* subn mgmt class */, |
| 2095 | MLX4_CMD_MAD_DEMUX_CONFIG, MLX4_CMD_MAD_DEMUX, |
| 2096 | MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); |
| 2097 | if (err) { |
| 2098 | mlx4_warn(dev, "MLX4_CMD_MAD_DEMUX: configure failed (%d)\n", err); |
| 2099 | goto out; |
| 2100 | } |
| 2101 | |
| 2102 | if (secure_host_active) |
| 2103 | mlx4_warn(dev, "HCA operating in secure-host mode. SMP firewall activated.\n"); |
| 2104 | out: |
| 2105 | mlx4_free_cmd_mailbox(dev, mailbox); |
| 2106 | return err; |
| 2107 | } |