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Aneesh V7ec94452012-04-27 17:54:05 +05301#
2# Memory devices
3#
4
5menuconfig MEMORY
6 bool "Memory Controller drivers"
7
8if MEMORY
9
Ivan Khoronzhuk5a7c8152014-02-24 19:26:11 +020010config TI_AEMIF
11 tristate "Texas Instruments AEMIF driver"
12 depends on (ARCH_DAVINCI || ARCH_KEYSTONE) && OF
13 help
14 This driver is for the AEMIF module available in Texas Instruments
15 SoCs. AEMIF stands for Asynchronous External Memory Interface and
16 is intended to provide a glue-less interface to a variety of
17 asynchronuous memory devices like ASRAM, NOR and NAND memory. A total
18 of 256M bytes of any of these memories can be accessed at a given
19 time via four chip selects with 64M byte access per chip select.
20
Aneesh V7ec94452012-04-27 17:54:05 +053021config TI_EMIF
22 tristate "Texas Instruments EMIF driver"
Santosh Shilimkar18e9a972012-05-04 11:38:11 +053023 depends on ARCH_OMAP2PLUS
Aneesh V7ec94452012-04-27 17:54:05 +053024 select DDR
25 help
26 This driver is for the EMIF module available in Texas Instruments
27 SoCs. EMIF is an SDRAM controller that, based on its revision,
28 supports one or more of DDR2, DDR3, and LPDDR2 SDRAM protocols.
29 This driver takes care of only LPDDR2 memories presently. The
30 functions of the driver includes re-configuring AC timing
31 parameters and other settings during frequency, voltage and
32 temperature changes
33
Ezequiel Garcia3edad322013-04-23 16:21:26 -030034config MVEBU_DEVBUS
35 bool "Marvell EBU Device Bus Controller"
36 default y
37 depends on PLAT_ORION && OF
38 help
39 This driver is for the Device Bus controller available in some
40 Marvell EBU SoCs such as Discovery (mv78xx0), Orion (88f5xxx) and
41 Armada 370 and Armada XP. This controller allows to handle flash
42 devices such as NOR, NAND, SRAM, and FPGA.
43
Hiroshi DOYUc542fb72012-05-10 10:42:30 +030044config TEGRA20_MC
Hiroshi DOYUf0e33f92012-05-11 09:56:24 +030045 bool "Tegra20 Memory Controller(MC) driver"
46 default y
Hiroshi DOYUc542fb72012-05-10 10:42:30 +030047 depends on ARCH_TEGRA_2x_SOC
Hiroshi DOYUf0e33f92012-05-11 09:56:24 +030048 help
49 This driver is for the Memory Controller(MC) module available
50 in Tegra20 SoCs, mainly for a address translation fault
51 analysis, especially for IOMMU/GART(Graphics Address
52 Relocation Table) module.
Hiroshi DOYUc542fb72012-05-10 10:42:30 +030053
Hiroshi DOYUaf468102012-05-10 10:42:32 +030054config TEGRA30_MC
Hiroshi DOYU42d11492012-05-11 09:56:25 +030055 bool "Tegra30 Memory Controller(MC) driver"
56 default y
Hiroshi DOYUaf468102012-05-10 10:42:32 +030057 depends on ARCH_TEGRA_3x_SOC
Hiroshi DOYU42d11492012-05-11 09:56:25 +030058 help
59 This driver is for the Memory Controller(MC) module available
60 in Tegra30 SoCs, mainly for a address translation fault
61 analysis, especially for IOMMU/SMMU(System Memory Management
62 Unit) module.
Hiroshi DOYUaf468102012-05-10 10:42:32 +030063
Scott Wood54afbec2014-07-02 18:52:11 -050064config FSL_CORENET_CF
65 tristate "Freescale CoreNet Error Reporting"
66 depends on FSL_SOC_BOOKE
67 help
68 Say Y for reporting of errors from the Freescale CoreNet
69 Coherency Fabric. Errors reported include accesses to
70 physical addresses that mapped by no local access window
71 (LAW) or an invalid LAW, as well as bad cache state that
72 represents a coherency violation.
73
Paul Gortmaker42d87b12014-02-19 17:46:40 -050074config FSL_IFC
75 bool
76 depends on FSL_SOC
77
Aneesh V7ec94452012-04-27 17:54:05 +053078endif