blob: 366b19d33f77f7c826f5f935c4bb6a39760d84af [file] [log] [blame]
Ralf Baechle38b18f722005-02-03 14:28:23 +00001config SIBYTE_SB1250
2 bool
Ralf Baechle217dd112007-11-01 01:57:55 +00003 select CEVT_SB1250
4 select CSRC_SB1250
Ralf Baechle38b18f722005-02-03 14:28:23 +00005 select HW_HAS_PCI
Ralf Baechle7bcf7712007-10-11 23:46:09 +01006 select IRQ_CPU
Ralf Baechleca6f5492007-03-09 12:17:32 +00007 select SIBYTE_ENABLE_LDT_IF_PCI
Mark Masond619f382007-03-29 11:39:56 -07008 select SIBYTE_HAS_ZBUS_PROFILING
Ralf Baechle38b18f722005-02-03 14:28:23 +00009 select SIBYTE_SB1xxx_SOC
Ralf Baechlee73ea272006-06-04 11:51:46 +010010 select SYS_SUPPORTS_SMP
Ralf Baechle38b18f722005-02-03 14:28:23 +000011
12config SIBYTE_BCM1120
13 bool
Ralf Baechle217dd112007-11-01 01:57:55 +000014 select CEVT_SB1250
15 select CSRC_SB1250
Ralf Baechle7bcf7712007-10-11 23:46:09 +010016 select IRQ_CPU
Ralf Baechle38b18f722005-02-03 14:28:23 +000017 select SIBYTE_BCM112X
Ralf Baechlebb9b8132007-03-09 15:59:56 +000018 select SIBYTE_HAS_ZBUS_PROFILING
Ralf Baechle38b18f722005-02-03 14:28:23 +000019 select SIBYTE_SB1xxx_SOC
20
21config SIBYTE_BCM1125
22 bool
Ralf Baechle217dd112007-11-01 01:57:55 +000023 select CEVT_SB1250
24 select CSRC_SB1250
Ralf Baechle38b18f722005-02-03 14:28:23 +000025 select HW_HAS_PCI
Ralf Baechle7bcf7712007-10-11 23:46:09 +010026 select IRQ_CPU
Ralf Baechle38b18f722005-02-03 14:28:23 +000027 select SIBYTE_BCM112X
Ralf Baechlebb9b8132007-03-09 15:59:56 +000028 select SIBYTE_HAS_ZBUS_PROFILING
Ralf Baechle38b18f722005-02-03 14:28:23 +000029 select SIBYTE_SB1xxx_SOC
30
31config SIBYTE_BCM1125H
32 bool
Ralf Baechle217dd112007-11-01 01:57:55 +000033 select CEVT_SB1250
34 select CSRC_SB1250
Ralf Baechle38b18f722005-02-03 14:28:23 +000035 select HW_HAS_PCI
Ralf Baechle7bcf7712007-10-11 23:46:09 +010036 select IRQ_CPU
Ralf Baechle38b18f722005-02-03 14:28:23 +000037 select SIBYTE_BCM112X
Ralf Baechleca6f5492007-03-09 12:17:32 +000038 select SIBYTE_ENABLE_LDT_IF_PCI
Ralf Baechlebb9b8132007-03-09 15:59:56 +000039 select SIBYTE_HAS_ZBUS_PROFILING
Ralf Baechle38b18f722005-02-03 14:28:23 +000040 select SIBYTE_SB1xxx_SOC
41
42config SIBYTE_BCM112X
43 bool
Ralf Baechle217dd112007-11-01 01:57:55 +000044 select CEVT_SB1250
45 select CSRC_SB1250
Ralf Baechle7bcf7712007-10-11 23:46:09 +010046 select IRQ_CPU
Ralf Baechle38b18f722005-02-03 14:28:23 +000047 select SIBYTE_SB1xxx_SOC
Ralf Baechlebb9b8132007-03-09 15:59:56 +000048 select SIBYTE_HAS_ZBUS_PROFILING
Ralf Baechle38b18f722005-02-03 14:28:23 +000049
Andrew Isaacsonf137e462005-10-19 23:56:38 -070050config SIBYTE_BCM1x80
51 bool
Ralf Baechle217dd112007-11-01 01:57:55 +000052 select CEVT_BCM1480
53 select CSRC_BCM1480
Andrew Isaacsonf137e462005-10-19 23:56:38 -070054 select HW_HAS_PCI
Ralf Baechle7bcf7712007-10-11 23:46:09 +010055 select IRQ_CPU
Mark Masond619f382007-03-29 11:39:56 -070056 select SIBYTE_HAS_ZBUS_PROFILING
Andrew Isaacsonf137e462005-10-19 23:56:38 -070057 select SIBYTE_SB1xxx_SOC
Ralf Baechlee73ea272006-06-04 11:51:46 +010058 select SYS_SUPPORTS_SMP
Andrew Isaacsonf137e462005-10-19 23:56:38 -070059
60config SIBYTE_BCM1x55
61 bool
Ralf Baechle217dd112007-11-01 01:57:55 +000062 select CEVT_BCM1480
63 select CSRC_BCM1480
Andrew Isaacsonf137e462005-10-19 23:56:38 -070064 select HW_HAS_PCI
Ralf Baechle7bcf7712007-10-11 23:46:09 +010065 select IRQ_CPU
Andrew Isaacsonf137e462005-10-19 23:56:38 -070066 select SIBYTE_SB1xxx_SOC
Ralf Baechlebb9b8132007-03-09 15:59:56 +000067 select SIBYTE_HAS_ZBUS_PROFILING
Ralf Baechlee73ea272006-06-04 11:51:46 +010068 select SYS_SUPPORTS_SMP
Andrew Isaacsonf137e462005-10-19 23:56:38 -070069
Ralf Baechle38b18f722005-02-03 14:28:23 +000070config SIBYTE_SB1xxx_SOC
71 bool
Ralf Baechle38b18f722005-02-03 14:28:23 +000072 select DMA_COHERENT
Ralf Baechle7bcf7712007-10-11 23:46:09 +010073 select IRQ_CPU
Ralf Baechle38b18f722005-02-03 14:28:23 +000074 select SIBYTE_CFE
75 select SWAP_IO_SPACE
76 select SYS_SUPPORTS_32BIT_KERNEL
77 select SYS_SUPPORTS_64BIT_KERNEL
78
79choice
80 prompt "SiByte SOC Stepping"
81 depends on SIBYTE_SB1xxx_SOC
82
83config CPU_SB1_PASS_1
84 bool "1250 Pass1"
85 depends on SIBYTE_SB1250
86 select CPU_HAS_PREFETCH
87
88config CPU_SB1_PASS_2_1250
89 bool "1250 An"
90 depends on SIBYTE_SB1250
91 select CPU_SB1_PASS_2
92 help
93 Also called BCM1250 Pass 2
94
95config CPU_SB1_PASS_2_2
96 bool "1250 Bn"
97 depends on SIBYTE_SB1250
98 select CPU_HAS_PREFETCH
99 help
100 Also called BCM1250 Pass 2.2
101
102config CPU_SB1_PASS_4
103 bool "1250 Cn"
104 depends on SIBYTE_SB1250
105 select CPU_HAS_PREFETCH
106 help
107 Also called BCM1250 Pass 3
108
109config CPU_SB1_PASS_2_112x
110 bool "112x Hybrid"
111 depends on SIBYTE_BCM112X
112 select CPU_SB1_PASS_2
113
114config CPU_SB1_PASS_3
115 bool "112x An"
116 depends on SIBYTE_BCM112X
117 select CPU_HAS_PREFETCH
118
119endchoice
120
121config CPU_SB1_PASS_2
122 bool
123
124config SIBYTE_HAS_LDT
125 bool
Ralf Baechleca6f5492007-03-09 12:17:32 +0000126
127config SIBYTE_ENABLE_LDT_IF_PCI
128 bool
129 select SIBYTE_HAS_LDT if PCI
Ralf Baechle38b18f722005-02-03 14:28:23 +0000130
131config SIMULATION
132 bool "Running under simulation"
133 depends on SIBYTE_SB1xxx_SOC
134 help
135 Build a kernel suitable for running under the GDB simulator.
136 Primarily adjusts the kernel's notion of time.
137
Ralf Baechle77607632005-11-10 16:32:14 +0000138config SB1_CEX_ALWAYS_FATAL
Andrew Isaacsona4b5bd92005-10-19 23:57:40 -0700139 bool "All cache exceptions considered fatal (no recovery attempted)"
140 depends on SIBYTE_SB1xxx_SOC
141
Ralf Baechle77607632005-11-10 16:32:14 +0000142config SB1_CERR_STALL
Andrew Isaacsona4b5bd92005-10-19 23:57:40 -0700143 bool "Stall (rather than panic) on fatal cache error"
144 depends on SIBYTE_SB1xxx_SOC
145
Ralf Baechle38b18f722005-02-03 14:28:23 +0000146config SIBYTE_CFE
147 bool "Booting from CFE"
148 depends on SIBYTE_SB1xxx_SOC
Aurelien Jarnodf78b5c2007-09-05 08:58:26 +0200149 select CFE
Ralf Baechle36a88532007-03-01 11:56:43 +0000150 select SYS_HAS_EARLY_PRINTK
Ralf Baechle38b18f722005-02-03 14:28:23 +0000151 help
152 Make use of the CFE API for enumerating available memory,
153 controlling secondary CPUs, and possibly console output.
154
155config SIBYTE_CFE_CONSOLE
156 bool "Use firmware console"
157 depends on SIBYTE_CFE
158 help
159 Use the CFE API's console write routines during boot. Other console
160 options (VT console, sb1250 duart console, etc.) should not be
161 configured.
162
163config SIBYTE_STANDALONE
164 bool
165 depends on SIBYTE_SB1xxx_SOC && !SIBYTE_CFE
Ralf Baechle36a88532007-03-01 11:56:43 +0000166 select SYS_HAS_EARLY_PRINTK
Ralf Baechle38b18f722005-02-03 14:28:23 +0000167 default y
168
169config SIBYTE_STANDALONE_RAM_SIZE
170 int "Memory size (in megabytes)"
171 depends on SIBYTE_STANDALONE
172 default "32"
173
174config SIBYTE_BUS_WATCHER
175 bool "Support for Bus Watcher statistics"
176 depends on SIBYTE_SB1xxx_SOC
177 help
178 Handle and keep statistics on the bus error interrupts (COR_ECC,
179 BAD_ECC, IO_BUS).
180
181config SIBYTE_BW_TRACE
182 bool "Capture bus trace before bus error"
183 depends on SIBYTE_BUS_WATCHER
184 help
185 Run a continuous bus trace, dumping the raw data as soon as
186 a ZBbus error is detected. Cannot work if ZBbus profiling
187 is turned on, and also will interfere with JTAG-based trace
188 buffer activity. Raw buffer data is dumped to console, and
189 must be processed off-line.
190
Ralf Baechle38b18f722005-02-03 14:28:23 +0000191config SIBYTE_TBPROF
Ralf Baechlebb9b8132007-03-09 15:59:56 +0000192 tristate "Support for ZBbus profiling"
193 depends on SIBYTE_HAS_ZBUS_PROFILING
194
195config SIBYTE_HAS_ZBUS_PROFILING
196 bool