Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 1 | /* |
| 2 | * linux/arch/arm/mach-omap2/cpuidle34xx.c |
| 3 | * |
| 4 | * OMAP3 CPU IDLE Routines |
| 5 | * |
| 6 | * Copyright (C) 2008 Texas Instruments, Inc. |
| 7 | * Rajendra Nayak <rnayak@ti.com> |
| 8 | * |
| 9 | * Copyright (C) 2007 Texas Instruments, Inc. |
| 10 | * Karthik Dasu <karthik-dp@ti.com> |
| 11 | * |
| 12 | * Copyright (C) 2006 Nokia Corporation |
| 13 | * Tony Lindgren <tony@atomide.com> |
| 14 | * |
| 15 | * Copyright (C) 2005 Texas Instruments, Inc. |
| 16 | * Richard Woodruff <r-woodruff2@ti.com> |
| 17 | * |
| 18 | * Based on pm.c for omap2 |
| 19 | * |
| 20 | * This program is free software; you can redistribute it and/or modify |
| 21 | * it under the terms of the GNU General Public License version 2 as |
| 22 | * published by the Free Software Foundation. |
| 23 | */ |
| 24 | |
Tero Kristo | cf22854 | 2009-03-20 15:21:02 +0200 | [diff] [blame] | 25 | #include <linux/sched.h> |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 26 | #include <linux/cpuidle.h> |
Kevin Hilman | 5698eb4 | 2011-11-07 15:58:40 -0800 | [diff] [blame^] | 27 | #include <linux/export.h> |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 28 | |
| 29 | #include <plat/prcm.h> |
Rajendra Nayak | 20b0166 | 2008-10-08 17:31:22 +0530 | [diff] [blame] | 30 | #include <plat/irqs.h> |
Paul Walmsley | 72e06d0 | 2010-12-21 21:05:16 -0700 | [diff] [blame] | 31 | #include "powerdomain.h" |
Paul Walmsley | 1540f214 | 2010-12-21 21:05:15 -0700 | [diff] [blame] | 32 | #include "clockdomain.h" |
Kevin Hilman | 0f724ed | 2008-10-28 17:32:11 -0700 | [diff] [blame] | 33 | #include <plat/serial.h> |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 34 | |
Kevin Hilman | c98e223 | 2008-10-28 17:30:07 -0700 | [diff] [blame] | 35 | #include "pm.h" |
Paul Walmsley | 4814ced | 2010-10-08 11:40:20 -0600 | [diff] [blame] | 36 | #include "control.h" |
Kevin Hilman | c98e223 | 2008-10-28 17:30:07 -0700 | [diff] [blame] | 37 | |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 38 | #ifdef CONFIG_CPU_IDLE |
| 39 | |
Kevin Hilman | bb4de3d | 2009-12-15 16:37:18 -0800 | [diff] [blame] | 40 | /* |
| 41 | * The latencies/thresholds for various C states have |
| 42 | * to be configured from the respective board files. |
| 43 | * These are some default values (which might not provide |
| 44 | * the best power savings) used on boards which do not |
| 45 | * pass these details from the board file. |
| 46 | */ |
| 47 | static struct cpuidle_params cpuidle_params_table[] = { |
| 48 | /* C1 */ |
Jean Pihet | 866ba0e | 2011-05-09 12:02:13 +0200 | [diff] [blame] | 49 | {2 + 2, 5, 1}, |
Kevin Hilman | bb4de3d | 2009-12-15 16:37:18 -0800 | [diff] [blame] | 50 | /* C2 */ |
Jean Pihet | 866ba0e | 2011-05-09 12:02:13 +0200 | [diff] [blame] | 51 | {10 + 10, 30, 1}, |
Kevin Hilman | bb4de3d | 2009-12-15 16:37:18 -0800 | [diff] [blame] | 52 | /* C3 */ |
Jean Pihet | 866ba0e | 2011-05-09 12:02:13 +0200 | [diff] [blame] | 53 | {50 + 50, 300, 1}, |
Kevin Hilman | bb4de3d | 2009-12-15 16:37:18 -0800 | [diff] [blame] | 54 | /* C4 */ |
Jean Pihet | 866ba0e | 2011-05-09 12:02:13 +0200 | [diff] [blame] | 55 | {1500 + 1800, 4000, 1}, |
Kevin Hilman | bb4de3d | 2009-12-15 16:37:18 -0800 | [diff] [blame] | 56 | /* C5 */ |
Jean Pihet | 866ba0e | 2011-05-09 12:02:13 +0200 | [diff] [blame] | 57 | {2500 + 7500, 12000, 1}, |
Kevin Hilman | bb4de3d | 2009-12-15 16:37:18 -0800 | [diff] [blame] | 58 | /* C6 */ |
Jean Pihet | 866ba0e | 2011-05-09 12:02:13 +0200 | [diff] [blame] | 59 | {3000 + 8500, 15000, 1}, |
Kevin Hilman | bb4de3d | 2009-12-15 16:37:18 -0800 | [diff] [blame] | 60 | /* C7 */ |
Jean Pihet | 866ba0e | 2011-05-09 12:02:13 +0200 | [diff] [blame] | 61 | {10000 + 30000, 300000, 1}, |
Kevin Hilman | bb4de3d | 2009-12-15 16:37:18 -0800 | [diff] [blame] | 62 | }; |
Jean Pihet | badc303 | 2011-05-09 12:02:14 +0200 | [diff] [blame] | 63 | #define OMAP3_NUM_STATES ARRAY_SIZE(cpuidle_params_table) |
| 64 | |
| 65 | /* Mach specific information to be recorded in the C-state driver_data */ |
| 66 | struct omap3_idle_statedata { |
| 67 | u32 mpu_state; |
| 68 | u32 core_state; |
| 69 | u8 valid; |
| 70 | }; |
| 71 | struct omap3_idle_statedata omap3_idle_data[OMAP3_NUM_STATES]; |
| 72 | |
| 73 | struct powerdomain *mpu_pd, *core_pd, *per_pd, *cam_pd; |
Kevin Hilman | bb4de3d | 2009-12-15 16:37:18 -0800 | [diff] [blame] | 74 | |
Peter 'p2' De Schrijver | 06d8f06 | 2009-03-13 18:19:16 +0200 | [diff] [blame] | 75 | static int _cpuidle_allow_idle(struct powerdomain *pwrdm, |
| 76 | struct clockdomain *clkdm) |
| 77 | { |
Rajendra Nayak | 5cd1937 | 2011-02-25 16:06:48 -0700 | [diff] [blame] | 78 | clkdm_allow_idle(clkdm); |
Peter 'p2' De Schrijver | 06d8f06 | 2009-03-13 18:19:16 +0200 | [diff] [blame] | 79 | return 0; |
| 80 | } |
| 81 | |
| 82 | static int _cpuidle_deny_idle(struct powerdomain *pwrdm, |
| 83 | struct clockdomain *clkdm) |
| 84 | { |
Rajendra Nayak | 5cd1937 | 2011-02-25 16:06:48 -0700 | [diff] [blame] | 85 | clkdm_deny_idle(clkdm); |
Peter 'p2' De Schrijver | 06d8f06 | 2009-03-13 18:19:16 +0200 | [diff] [blame] | 86 | return 0; |
| 87 | } |
| 88 | |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 89 | /** |
| 90 | * omap3_enter_idle - Programs OMAP3 to enter the specified state |
| 91 | * @dev: cpuidle device |
| 92 | * @state: The target state to be programmed |
| 93 | * |
| 94 | * Called from the CPUidle framework to program the device to the |
| 95 | * specified target state selected by the governor. |
| 96 | */ |
| 97 | static int omap3_enter_idle(struct cpuidle_device *dev, |
| 98 | struct cpuidle_state *state) |
| 99 | { |
Jean Pihet | badc303 | 2011-05-09 12:02:14 +0200 | [diff] [blame] | 100 | struct omap3_idle_statedata *cx = cpuidle_get_statedata(state); |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 101 | struct timespec ts_preidle, ts_postidle, ts_idle; |
Kevin Hilman | c98e223 | 2008-10-28 17:30:07 -0700 | [diff] [blame] | 102 | u32 mpu_state = cx->mpu_state, core_state = cx->core_state; |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 103 | |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 104 | /* Used to keep track of the total time in idle */ |
| 105 | getnstimeofday(&ts_preidle); |
| 106 | |
| 107 | local_irq_disable(); |
| 108 | local_fiq_disable(); |
| 109 | |
Jouni Hogander | 7139178 | 2008-10-28 10:59:05 +0200 | [diff] [blame] | 110 | pwrdm_set_next_pwrst(mpu_pd, mpu_state); |
| 111 | pwrdm_set_next_pwrst(core_pd, core_state); |
Rajendra Nayak | 20b0166 | 2008-10-08 17:31:22 +0530 | [diff] [blame] | 112 | |
Tero Kristo | cf22854 | 2009-03-20 15:21:02 +0200 | [diff] [blame] | 113 | if (omap_irq_pending() || need_resched()) |
Rajendra Nayak | 20b0166 | 2008-10-08 17:31:22 +0530 | [diff] [blame] | 114 | goto return_sleep_time; |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 115 | |
Jean Pihet | badc303 | 2011-05-09 12:02:14 +0200 | [diff] [blame] | 116 | /* Deny idle for C1 */ |
| 117 | if (state == &dev->states[0]) { |
Peter 'p2' De Schrijver | 06d8f06 | 2009-03-13 18:19:16 +0200 | [diff] [blame] | 118 | pwrdm_for_each_clkdm(mpu_pd, _cpuidle_deny_idle); |
| 119 | pwrdm_for_each_clkdm(core_pd, _cpuidle_deny_idle); |
| 120 | } |
| 121 | |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 122 | /* Execute ARM wfi */ |
| 123 | omap_sram_idle(); |
| 124 | |
Jean Pihet | badc303 | 2011-05-09 12:02:14 +0200 | [diff] [blame] | 125 | /* Re-allow idle for C1 */ |
| 126 | if (state == &dev->states[0]) { |
Peter 'p2' De Schrijver | 06d8f06 | 2009-03-13 18:19:16 +0200 | [diff] [blame] | 127 | pwrdm_for_each_clkdm(mpu_pd, _cpuidle_allow_idle); |
| 128 | pwrdm_for_each_clkdm(core_pd, _cpuidle_allow_idle); |
| 129 | } |
| 130 | |
Rajendra Nayak | 20b0166 | 2008-10-08 17:31:22 +0530 | [diff] [blame] | 131 | return_sleep_time: |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 132 | getnstimeofday(&ts_postidle); |
| 133 | ts_idle = timespec_sub(ts_postidle, ts_preidle); |
| 134 | |
| 135 | local_irq_enable(); |
| 136 | local_fiq_enable(); |
| 137 | |
Tero Kristo | afbcf61 | 2009-10-26 15:10:40 +0200 | [diff] [blame] | 138 | return ts_idle.tv_nsec / NSEC_PER_USEC + ts_idle.tv_sec * USEC_PER_SEC; |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 139 | } |
| 140 | |
| 141 | /** |
Jean Pihet | 0490891 | 2011-05-09 12:02:16 +0200 | [diff] [blame] | 142 | * next_valid_state - Find next valid C-state |
Sanjeev Premi | 6af83b3 | 2010-01-28 23:16:43 +0530 | [diff] [blame] | 143 | * @dev: cpuidle device |
Jean Pihet | 0490891 | 2011-05-09 12:02:16 +0200 | [diff] [blame] | 144 | * @state: Currently selected C-state |
Sanjeev Premi | 6af83b3 | 2010-01-28 23:16:43 +0530 | [diff] [blame] | 145 | * |
| 146 | * If the current state is valid, it is returned back to the caller. |
| 147 | * Else, this function searches for a lower c-state which is still |
Jean Pihet | badc303 | 2011-05-09 12:02:14 +0200 | [diff] [blame] | 148 | * valid. |
Jean Pihet | 0490891 | 2011-05-09 12:02:16 +0200 | [diff] [blame] | 149 | * |
| 150 | * A state is valid if the 'valid' field is enabled and |
| 151 | * if it satisfies the enable_off_mode condition. |
Sanjeev Premi | 6af83b3 | 2010-01-28 23:16:43 +0530 | [diff] [blame] | 152 | */ |
| 153 | static struct cpuidle_state *next_valid_state(struct cpuidle_device *dev, |
Jean Pihet | badc303 | 2011-05-09 12:02:14 +0200 | [diff] [blame] | 154 | struct cpuidle_state *curr) |
Sanjeev Premi | 6af83b3 | 2010-01-28 23:16:43 +0530 | [diff] [blame] | 155 | { |
| 156 | struct cpuidle_state *next = NULL; |
Jean Pihet | c6cd91d | 2011-05-09 12:02:15 +0200 | [diff] [blame] | 157 | struct omap3_idle_statedata *cx = cpuidle_get_statedata(curr); |
Jean Pihet | 0490891 | 2011-05-09 12:02:16 +0200 | [diff] [blame] | 158 | u32 mpu_deepest_state = PWRDM_POWER_RET; |
| 159 | u32 core_deepest_state = PWRDM_POWER_RET; |
| 160 | |
| 161 | if (enable_off_mode) { |
| 162 | mpu_deepest_state = PWRDM_POWER_OFF; |
| 163 | /* |
| 164 | * Erratum i583: valable for ES rev < Es1.2 on 3630. |
| 165 | * CORE OFF mode is not supported in a stable form, restrict |
| 166 | * instead the CORE state to RET. |
| 167 | */ |
| 168 | if (!IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583)) |
| 169 | core_deepest_state = PWRDM_POWER_OFF; |
| 170 | } |
Sanjeev Premi | 6af83b3 | 2010-01-28 23:16:43 +0530 | [diff] [blame] | 171 | |
| 172 | /* Check if current state is valid */ |
Jean Pihet | 0490891 | 2011-05-09 12:02:16 +0200 | [diff] [blame] | 173 | if ((cx->valid) && |
| 174 | (cx->mpu_state >= mpu_deepest_state) && |
| 175 | (cx->core_state >= core_deepest_state)) { |
Sanjeev Premi | 6af83b3 | 2010-01-28 23:16:43 +0530 | [diff] [blame] | 176 | return curr; |
| 177 | } else { |
Jean Pihet | badc303 | 2011-05-09 12:02:14 +0200 | [diff] [blame] | 178 | int idx = OMAP3_NUM_STATES - 1; |
Sanjeev Premi | 6af83b3 | 2010-01-28 23:16:43 +0530 | [diff] [blame] | 179 | |
Jean Pihet | c6cd91d | 2011-05-09 12:02:15 +0200 | [diff] [blame] | 180 | /* Reach the current state starting at highest C-state */ |
Jean Pihet | badc303 | 2011-05-09 12:02:14 +0200 | [diff] [blame] | 181 | for (; idx >= 0; idx--) { |
Sanjeev Premi | 6af83b3 | 2010-01-28 23:16:43 +0530 | [diff] [blame] | 182 | if (&dev->states[idx] == curr) { |
| 183 | next = &dev->states[idx]; |
| 184 | break; |
| 185 | } |
| 186 | } |
| 187 | |
Jean Pihet | c6cd91d | 2011-05-09 12:02:15 +0200 | [diff] [blame] | 188 | /* Should never hit this condition */ |
Sanjeev Premi | 6af83b3 | 2010-01-28 23:16:43 +0530 | [diff] [blame] | 189 | WARN_ON(next == NULL); |
| 190 | |
| 191 | /* |
| 192 | * Drop to next valid state. |
| 193 | * Start search from the next (lower) state. |
| 194 | */ |
| 195 | idx--; |
Jean Pihet | badc303 | 2011-05-09 12:02:14 +0200 | [diff] [blame] | 196 | for (; idx >= 0; idx--) { |
Sanjeev Premi | 6af83b3 | 2010-01-28 23:16:43 +0530 | [diff] [blame] | 197 | cx = cpuidle_get_statedata(&dev->states[idx]); |
Jean Pihet | 0490891 | 2011-05-09 12:02:16 +0200 | [diff] [blame] | 198 | if ((cx->valid) && |
| 199 | (cx->mpu_state >= mpu_deepest_state) && |
| 200 | (cx->core_state >= core_deepest_state)) { |
Sanjeev Premi | 6af83b3 | 2010-01-28 23:16:43 +0530 | [diff] [blame] | 201 | next = &dev->states[idx]; |
| 202 | break; |
| 203 | } |
| 204 | } |
| 205 | /* |
Jean Pihet | badc303 | 2011-05-09 12:02:14 +0200 | [diff] [blame] | 206 | * C1 is always valid. |
Sanjeev Premi | 6af83b3 | 2010-01-28 23:16:43 +0530 | [diff] [blame] | 207 | * So, no need to check for 'next==NULL' outside this loop. |
| 208 | */ |
| 209 | } |
| 210 | |
| 211 | return next; |
| 212 | } |
| 213 | |
| 214 | /** |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 215 | * omap3_enter_idle_bm - Checks for any bus activity |
| 216 | * @dev: cpuidle device |
| 217 | * @state: The target state to be programmed |
| 218 | * |
Jean Pihet | badc303 | 2011-05-09 12:02:14 +0200 | [diff] [blame] | 219 | * This function checks for any pending activity and then programs |
| 220 | * the device to the specified or a safer state. |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 221 | */ |
| 222 | static int omap3_enter_idle_bm(struct cpuidle_device *dev, |
| 223 | struct cpuidle_state *state) |
| 224 | { |
Jean Pihet | c6cd91d | 2011-05-09 12:02:15 +0200 | [diff] [blame] | 225 | struct cpuidle_state *new_state; |
| 226 | u32 core_next_state, per_next_state = 0, per_saved_state = 0, cam_state; |
Jean Pihet | badc303 | 2011-05-09 12:02:14 +0200 | [diff] [blame] | 227 | struct omap3_idle_statedata *cx; |
Kevin Hilman | e7410cf | 2010-09-08 16:37:42 -0700 | [diff] [blame] | 228 | int ret; |
Kevin Hilman | 0f724ed | 2008-10-28 17:32:11 -0700 | [diff] [blame] | 229 | |
Jean Pihet | c6cd91d | 2011-05-09 12:02:15 +0200 | [diff] [blame] | 230 | if (!omap3_can_sleep()) { |
Kevin Hilman | 0f724ed | 2008-10-28 17:32:11 -0700 | [diff] [blame] | 231 | new_state = dev->safe_state; |
Kevin Hilman | e7410cf | 2010-09-08 16:37:42 -0700 | [diff] [blame] | 232 | goto select_state; |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 233 | } |
Kevin Hilman | 0f724ed | 2008-10-28 17:32:11 -0700 | [diff] [blame] | 234 | |
Kevin Hilman | e7410cf | 2010-09-08 16:37:42 -0700 | [diff] [blame] | 235 | /* |
| 236 | * Prevent idle completely if CAM is active. |
| 237 | * CAM does not have wakeup capability in OMAP3. |
| 238 | */ |
| 239 | cam_state = pwrdm_read_pwrst(cam_pd); |
| 240 | if (cam_state == PWRDM_POWER_ON) { |
| 241 | new_state = dev->safe_state; |
| 242 | goto select_state; |
| 243 | } |
| 244 | |
| 245 | /* |
Jean Pihet | c6cd91d | 2011-05-09 12:02:15 +0200 | [diff] [blame] | 246 | * FIXME: we currently manage device-specific idle states |
| 247 | * for PER and CORE in combination with CPU-specific |
| 248 | * idle states. This is wrong, and device-specific |
| 249 | * idle management needs to be separated out into |
| 250 | * its own code. |
| 251 | */ |
| 252 | |
| 253 | /* |
Kevin Hilman | e7410cf | 2010-09-08 16:37:42 -0700 | [diff] [blame] | 254 | * Prevent PER off if CORE is not in retention or off as this |
| 255 | * would disable PER wakeups completely. |
| 256 | */ |
Jean Pihet | c6cd91d | 2011-05-09 12:02:15 +0200 | [diff] [blame] | 257 | cx = cpuidle_get_statedata(state); |
| 258 | core_next_state = cx->core_state; |
Kevin Hilman | e7410cf | 2010-09-08 16:37:42 -0700 | [diff] [blame] | 259 | per_next_state = per_saved_state = pwrdm_read_next_pwrst(per_pd); |
| 260 | if ((per_next_state == PWRDM_POWER_OFF) && |
Kevin Hilman | 65707fb | 2010-10-01 08:35:47 -0700 | [diff] [blame] | 261 | (core_next_state > PWRDM_POWER_RET)) |
Kevin Hilman | e7410cf | 2010-09-08 16:37:42 -0700 | [diff] [blame] | 262 | per_next_state = PWRDM_POWER_RET; |
Kevin Hilman | e7410cf | 2010-09-08 16:37:42 -0700 | [diff] [blame] | 263 | |
| 264 | /* Are we changing PER target state? */ |
| 265 | if (per_next_state != per_saved_state) |
| 266 | pwrdm_set_next_pwrst(per_pd, per_next_state); |
| 267 | |
Jean Pihet | c6cd91d | 2011-05-09 12:02:15 +0200 | [diff] [blame] | 268 | new_state = next_valid_state(dev, state); |
| 269 | |
Kevin Hilman | e7410cf | 2010-09-08 16:37:42 -0700 | [diff] [blame] | 270 | select_state: |
Kevin Hilman | 0f724ed | 2008-10-28 17:32:11 -0700 | [diff] [blame] | 271 | dev->last_state = new_state; |
Kevin Hilman | e7410cf | 2010-09-08 16:37:42 -0700 | [diff] [blame] | 272 | ret = omap3_enter_idle(dev, new_state); |
| 273 | |
| 274 | /* Restore original PER state if it was modified */ |
| 275 | if (per_next_state != per_saved_state) |
| 276 | pwrdm_set_next_pwrst(per_pd, per_saved_state); |
| 277 | |
| 278 | return ret; |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 279 | } |
| 280 | |
| 281 | DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev); |
| 282 | |
Kevin Hilman | bb4de3d | 2009-12-15 16:37:18 -0800 | [diff] [blame] | 283 | void omap3_pm_init_cpuidle(struct cpuidle_params *cpuidle_board_params) |
| 284 | { |
| 285 | int i; |
| 286 | |
| 287 | if (!cpuidle_board_params) |
| 288 | return; |
| 289 | |
Jean Pihet | badc303 | 2011-05-09 12:02:14 +0200 | [diff] [blame] | 290 | for (i = 0; i < OMAP3_NUM_STATES; i++) { |
| 291 | cpuidle_params_table[i].valid = cpuidle_board_params[i].valid; |
Jean Pihet | 866ba0e | 2011-05-09 12:02:13 +0200 | [diff] [blame] | 292 | cpuidle_params_table[i].exit_latency = |
| 293 | cpuidle_board_params[i].exit_latency; |
| 294 | cpuidle_params_table[i].target_residency = |
| 295 | cpuidle_board_params[i].target_residency; |
Kevin Hilman | bb4de3d | 2009-12-15 16:37:18 -0800 | [diff] [blame] | 296 | } |
| 297 | return; |
| 298 | } |
| 299 | |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 300 | struct cpuidle_driver omap3_idle_driver = { |
| 301 | .name = "omap3_idle", |
| 302 | .owner = THIS_MODULE, |
| 303 | }; |
| 304 | |
Jean Pihet | c6cd91d | 2011-05-09 12:02:15 +0200 | [diff] [blame] | 305 | /* Helper to fill the C-state common data and register the driver_data */ |
Jean Pihet | badc303 | 2011-05-09 12:02:14 +0200 | [diff] [blame] | 306 | static inline struct omap3_idle_statedata *_fill_cstate( |
| 307 | struct cpuidle_device *dev, |
| 308 | int idx, const char *descr) |
| 309 | { |
| 310 | struct omap3_idle_statedata *cx = &omap3_idle_data[idx]; |
| 311 | struct cpuidle_state *state = &dev->states[idx]; |
| 312 | |
| 313 | state->exit_latency = cpuidle_params_table[idx].exit_latency; |
| 314 | state->target_residency = cpuidle_params_table[idx].target_residency; |
| 315 | state->flags = CPUIDLE_FLAG_TIME_VALID; |
| 316 | state->enter = omap3_enter_idle_bm; |
| 317 | cx->valid = cpuidle_params_table[idx].valid; |
| 318 | sprintf(state->name, "C%d", idx + 1); |
| 319 | strncpy(state->desc, descr, CPUIDLE_DESC_LEN); |
| 320 | cpuidle_set_statedata(state, cx); |
| 321 | |
| 322 | return cx; |
| 323 | } |
| 324 | |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 325 | /** |
| 326 | * omap3_idle_init - Init routine for OMAP3 idle |
| 327 | * |
Jean Pihet | badc303 | 2011-05-09 12:02:14 +0200 | [diff] [blame] | 328 | * Registers the OMAP3 specific cpuidle driver to the cpuidle |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 329 | * framework with the valid set of states. |
| 330 | */ |
Kalle Jokiniemi | 0343371 | 2008-09-26 11:04:20 +0300 | [diff] [blame] | 331 | int __init omap3_idle_init(void) |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 332 | { |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 333 | struct cpuidle_device *dev; |
Jean Pihet | badc303 | 2011-05-09 12:02:14 +0200 | [diff] [blame] | 334 | struct omap3_idle_statedata *cx; |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 335 | |
| 336 | mpu_pd = pwrdm_lookup("mpu_pwrdm"); |
Rajendra Nayak | 20b0166 | 2008-10-08 17:31:22 +0530 | [diff] [blame] | 337 | core_pd = pwrdm_lookup("core_pwrdm"); |
Kevin Hilman | e7410cf | 2010-09-08 16:37:42 -0700 | [diff] [blame] | 338 | per_pd = pwrdm_lookup("per_pwrdm"); |
| 339 | cam_pd = pwrdm_lookup("cam_pwrdm"); |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 340 | |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 341 | cpuidle_register_driver(&omap3_idle_driver); |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 342 | dev = &per_cpu(omap3_idle_dev, smp_processor_id()); |
| 343 | |
Jean Pihet | badc303 | 2011-05-09 12:02:14 +0200 | [diff] [blame] | 344 | /* C1 . MPU WFI + Core active */ |
| 345 | cx = _fill_cstate(dev, 0, "MPU ON + CORE ON"); |
| 346 | (&dev->states[0])->enter = omap3_enter_idle; |
| 347 | dev->safe_state = &dev->states[0]; |
| 348 | cx->valid = 1; /* C1 is always valid */ |
| 349 | cx->mpu_state = PWRDM_POWER_ON; |
| 350 | cx->core_state = PWRDM_POWER_ON; |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 351 | |
Jean Pihet | badc303 | 2011-05-09 12:02:14 +0200 | [diff] [blame] | 352 | /* C2 . MPU WFI + Core inactive */ |
| 353 | cx = _fill_cstate(dev, 1, "MPU ON + CORE ON"); |
| 354 | cx->mpu_state = PWRDM_POWER_ON; |
| 355 | cx->core_state = PWRDM_POWER_ON; |
| 356 | |
| 357 | /* C3 . MPU CSWR + Core inactive */ |
| 358 | cx = _fill_cstate(dev, 2, "MPU RET + CORE ON"); |
| 359 | cx->mpu_state = PWRDM_POWER_RET; |
| 360 | cx->core_state = PWRDM_POWER_ON; |
| 361 | |
| 362 | /* C4 . MPU OFF + Core inactive */ |
| 363 | cx = _fill_cstate(dev, 3, "MPU OFF + CORE ON"); |
| 364 | cx->mpu_state = PWRDM_POWER_OFF; |
| 365 | cx->core_state = PWRDM_POWER_ON; |
| 366 | |
| 367 | /* C5 . MPU RET + Core RET */ |
| 368 | cx = _fill_cstate(dev, 4, "MPU RET + CORE RET"); |
| 369 | cx->mpu_state = PWRDM_POWER_RET; |
| 370 | cx->core_state = PWRDM_POWER_RET; |
| 371 | |
| 372 | /* C6 . MPU OFF + Core RET */ |
| 373 | cx = _fill_cstate(dev, 5, "MPU OFF + CORE RET"); |
| 374 | cx->mpu_state = PWRDM_POWER_OFF; |
| 375 | cx->core_state = PWRDM_POWER_RET; |
| 376 | |
| 377 | /* C7 . MPU OFF + Core OFF */ |
| 378 | cx = _fill_cstate(dev, 6, "MPU OFF + CORE OFF"); |
| 379 | /* |
| 380 | * Erratum i583: implementation for ES rev < Es1.2 on 3630. We cannot |
| 381 | * enable OFF mode in a stable form for previous revisions. |
| 382 | * We disable C7 state as a result. |
| 383 | */ |
| 384 | if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583)) { |
| 385 | cx->valid = 0; |
| 386 | pr_warn("%s: core off state C7 disabled due to i583\n", |
| 387 | __func__); |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 388 | } |
Jean Pihet | badc303 | 2011-05-09 12:02:14 +0200 | [diff] [blame] | 389 | cx->mpu_state = PWRDM_POWER_OFF; |
| 390 | cx->core_state = PWRDM_POWER_OFF; |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 391 | |
Jean Pihet | badc303 | 2011-05-09 12:02:14 +0200 | [diff] [blame] | 392 | dev->state_count = OMAP3_NUM_STATES; |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 393 | if (cpuidle_register_device(dev)) { |
| 394 | printk(KERN_ERR "%s: CPUidle register device failed\n", |
| 395 | __func__); |
| 396 | return -EIO; |
| 397 | } |
| 398 | |
| 399 | return 0; |
| 400 | } |
Kalle Jokiniemi | 0343371 | 2008-09-26 11:04:20 +0300 | [diff] [blame] | 401 | #else |
| 402 | int __init omap3_idle_init(void) |
| 403 | { |
| 404 | return 0; |
| 405 | } |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 406 | #endif /* CONFIG_CPU_IDLE */ |