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gerrit-public.fairphone.software / kernel / msm-4.9 / 5da4eb049de803c7e9b81afbadf9f2e70e34dcae / . / drivers / pinctrl / sh-pfc / pfc-sh73a0.c
blob: 78f7ae802b4805b6c5c3602497c57433bb5b5322 [file] [log] [blame]
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]1/*
2 * sh73a0 processor support - PFC hardware block
3 *
4 * Copyright (C) 2010 Renesas Solutions Corp.
5 * Copyright (C) 2010 NISHIMOTO Hiroki
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; version 2 of the
10 * License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 */
Laurent Pinchartb8238992013-03-13 01:31:23 +0100[diff] [blame]21#include <linux/io.h>
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]22#include <linux/kernel.h>
Laurent Pinchartea770ad2013-04-21 23:26:26 +0200[diff] [blame]23#include <linux/module.h>
Laurent Pinchartb8238992013-03-13 01:31:23 +0100[diff] [blame]24#include <linux/pinctrl/pinconf-generic.h>
Laurent Pinchartea770ad2013-04-21 23:26:26 +0200[diff] [blame]25#include <linux/regulator/driver.h>
26#include <linux/regulator/machine.h>
27#include <linux/slab.h>
Laurent Pinchartb8238992013-03-13 01:31:23 +0100[diff] [blame]28
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]29#include <mach/sh73a0.h>
30#include <mach/irqs.h>
31
Laurent Pinchartb8238992013-03-13 01:31:23 +0100[diff] [blame]32#include "core.h"
Laurent Pinchartc3323802012-12-15 23:51:55 +0100[diff] [blame]33#include "sh_pfc.h"
34
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]35#define CPU_ALL_PORT(fn, pfx, sfx) \
Guennadi Liakhovetski942785d2013-02-12 16:34:31 +0100[diff] [blame]36 PORT_10(fn, pfx, sfx), PORT_90(fn, pfx, sfx), \
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]37 PORT_10(fn, pfx##10, sfx), \
38 PORT_1(fn, pfx##110, sfx), PORT_1(fn, pfx##111, sfx), \
39 PORT_1(fn, pfx##112, sfx), PORT_1(fn, pfx##113, sfx), \
40 PORT_1(fn, pfx##114, sfx), PORT_1(fn, pfx##115, sfx), \
41 PORT_1(fn, pfx##116, sfx), PORT_1(fn, pfx##117, sfx), \
42 PORT_1(fn, pfx##118, sfx), \
43 PORT_1(fn, pfx##128, sfx), PORT_1(fn, pfx##129, sfx), \
44 PORT_10(fn, pfx##13, sfx), PORT_10(fn, pfx##14, sfx), \
45 PORT_10(fn, pfx##15, sfx), \
46 PORT_1(fn, pfx##160, sfx), PORT_1(fn, pfx##161, sfx), \
47 PORT_1(fn, pfx##162, sfx), PORT_1(fn, pfx##163, sfx), \
48 PORT_1(fn, pfx##164, sfx), \
49 PORT_1(fn, pfx##192, sfx), PORT_1(fn, pfx##193, sfx), \
50 PORT_1(fn, pfx##194, sfx), PORT_1(fn, pfx##195, sfx), \
51 PORT_1(fn, pfx##196, sfx), PORT_1(fn, pfx##197, sfx), \
52 PORT_1(fn, pfx##198, sfx), PORT_1(fn, pfx##199, sfx), \
53 PORT_10(fn, pfx##20, sfx), PORT_10(fn, pfx##21, sfx), \
54 PORT_10(fn, pfx##22, sfx), PORT_10(fn, pfx##23, sfx), \
55 PORT_10(fn, pfx##24, sfx), PORT_10(fn, pfx##25, sfx), \
56 PORT_10(fn, pfx##26, sfx), PORT_10(fn, pfx##27, sfx), \
57 PORT_1(fn, pfx##280, sfx), PORT_1(fn, pfx##281, sfx), \
58 PORT_1(fn, pfx##282, sfx), \
59 PORT_1(fn, pfx##288, sfx), PORT_1(fn, pfx##289, sfx), \
60 PORT_10(fn, pfx##29, sfx), PORT_10(fn, pfx##30, sfx)
61
62enum {
63 PINMUX_RESERVED = 0,
64
65 PINMUX_DATA_BEGIN,
66 PORT_ALL(DATA), /* PORT0_DATA -> PORT309_DATA */
67 PINMUX_DATA_END,
68
69 PINMUX_INPUT_BEGIN,
70 PORT_ALL(IN), /* PORT0_IN -> PORT309_IN */
71 PINMUX_INPUT_END,
72
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]73 PINMUX_OUTPUT_BEGIN,
74 PORT_ALL(OUT), /* PORT0_OUT -> PORT309_OUT */
75 PINMUX_OUTPUT_END,
76
77 PINMUX_FUNCTION_BEGIN,
78 PORT_ALL(FN_IN), /* PORT0_FN_IN -> PORT309_FN_IN */
79 PORT_ALL(FN_OUT), /* PORT0_FN_OUT -> PORT309_FN_OUT */
80 PORT_ALL(FN0), /* PORT0_FN0 -> PORT309_FN0 */
81 PORT_ALL(FN1), /* PORT0_FN1 -> PORT309_FN1 */
82 PORT_ALL(FN2), /* PORT0_FN2 -> PORT309_FN2 */
83 PORT_ALL(FN3), /* PORT0_FN3 -> PORT309_FN3 */
84 PORT_ALL(FN4), /* PORT0_FN4 -> PORT309_FN4 */
85 PORT_ALL(FN5), /* PORT0_FN5 -> PORT309_FN5 */
86 PORT_ALL(FN6), /* PORT0_FN6 -> PORT309_FN6 */
87 PORT_ALL(FN7), /* PORT0_FN7 -> PORT309_FN7 */
88
89 MSEL2CR_MSEL19_0, MSEL2CR_MSEL19_1,
90 MSEL2CR_MSEL18_0, MSEL2CR_MSEL18_1,
91 MSEL2CR_MSEL17_0, MSEL2CR_MSEL17_1,
92 MSEL2CR_MSEL16_0, MSEL2CR_MSEL16_1,
93 MSEL2CR_MSEL14_0, MSEL2CR_MSEL14_1,
94 MSEL2CR_MSEL13_0, MSEL2CR_MSEL13_1,
95 MSEL2CR_MSEL12_0, MSEL2CR_MSEL12_1,
96 MSEL2CR_MSEL11_0, MSEL2CR_MSEL11_1,
97 MSEL2CR_MSEL10_0, MSEL2CR_MSEL10_1,
98 MSEL2CR_MSEL9_0, MSEL2CR_MSEL9_1,
99 MSEL2CR_MSEL8_0, MSEL2CR_MSEL8_1,
100 MSEL2CR_MSEL7_0, MSEL2CR_MSEL7_1,
101 MSEL2CR_MSEL6_0, MSEL2CR_MSEL6_1,
102 MSEL2CR_MSEL4_0, MSEL2CR_MSEL4_1,
103 MSEL2CR_MSEL5_0, MSEL2CR_MSEL5_1,
104 MSEL2CR_MSEL3_0, MSEL2CR_MSEL3_1,
105 MSEL2CR_MSEL2_0, MSEL2CR_MSEL2_1,
106 MSEL2CR_MSEL1_0, MSEL2CR_MSEL1_1,
107 MSEL2CR_MSEL0_0, MSEL2CR_MSEL0_1,
108 MSEL3CR_MSEL28_0, MSEL3CR_MSEL28_1,
109 MSEL3CR_MSEL15_0, MSEL3CR_MSEL15_1,
110 MSEL3CR_MSEL11_0, MSEL3CR_MSEL11_1,
111 MSEL3CR_MSEL9_0, MSEL3CR_MSEL9_1,
112 MSEL3CR_MSEL6_0, MSEL3CR_MSEL6_1,
113 MSEL3CR_MSEL2_0, MSEL3CR_MSEL2_1,
114 MSEL4CR_MSEL29_0, MSEL4CR_MSEL29_1,
115 MSEL4CR_MSEL27_0, MSEL4CR_MSEL27_1,
116 MSEL4CR_MSEL26_0, MSEL4CR_MSEL26_1,
117 MSEL4CR_MSEL22_0, MSEL4CR_MSEL22_1,
118 MSEL4CR_MSEL21_0, MSEL4CR_MSEL21_1,
119 MSEL4CR_MSEL20_0, MSEL4CR_MSEL20_1,
120 MSEL4CR_MSEL19_0, MSEL4CR_MSEL19_1,
121 MSEL4CR_MSEL15_0, MSEL4CR_MSEL15_1,
122 MSEL4CR_MSEL13_0, MSEL4CR_MSEL13_1,
123 MSEL4CR_MSEL12_0, MSEL4CR_MSEL12_1,
124 MSEL4CR_MSEL11_0, MSEL4CR_MSEL11_1,
125 MSEL4CR_MSEL10_0, MSEL4CR_MSEL10_1,
126 MSEL4CR_MSEL9_0, MSEL4CR_MSEL9_1,
127 MSEL4CR_MSEL8_0, MSEL4CR_MSEL8_1,
128 MSEL4CR_MSEL7_0, MSEL4CR_MSEL7_1,
129 MSEL4CR_MSEL4_0, MSEL4CR_MSEL4_1,
130 MSEL4CR_MSEL1_0, MSEL4CR_MSEL1_1,
131 PINMUX_FUNCTION_END,
132
133 PINMUX_MARK_BEGIN,
134 /* Hardware manual Table 25-1 (Function 0-7) */
135 VBUS_0_MARK,
136 GPI0_MARK,
137 GPI1_MARK,
138 GPI2_MARK,
139 GPI3_MARK,
140 GPI4_MARK,
141 GPI5_MARK,
142 GPI6_MARK,
143 GPI7_MARK,
144 SCIFA7_RXD_MARK,
145 SCIFA7_CTS__MARK,
146 GPO7_MARK, MFG0_OUT2_MARK,
147 GPO6_MARK, MFG1_OUT2_MARK,
148 GPO5_MARK, SCIFA0_SCK_MARK, FSICOSLDT3_MARK, PORT16_VIO_CKOR_MARK,
149 SCIFA0_TXD_MARK,
150 SCIFA7_TXD_MARK,
151 SCIFA7_RTS__MARK, PORT19_VIO_CKO2_MARK,
152 GPO0_MARK,
153 GPO1_MARK,
154 GPO2_MARK, STATUS0_MARK,
155 GPO3_MARK, STATUS1_MARK,
156 GPO4_MARK, STATUS2_MARK,
157 VINT_MARK,
158 TCKON_MARK,
159 XDVFS1_MARK, PORT27_I2C_SCL2_MARK, PORT27_I2C_SCL3_MARK, \
160 MFG0_OUT1_MARK, PORT27_IROUT_MARK,
161 XDVFS2_MARK, PORT28_I2C_SDA2_MARK, PORT28_I2C_SDA3_MARK, \
162 PORT28_TPU1TO1_MARK,
163 SIM_RST_MARK, PORT29_TPU1TO1_MARK,
164 SIM_CLK_MARK, PORT30_VIO_CKOR_MARK,
165 SIM_D_MARK, PORT31_IROUT_MARK,
166 SCIFA4_TXD_MARK,
167 SCIFA4_RXD_MARK, XWUP_MARK,
168 SCIFA4_RTS__MARK,
169 SCIFA4_CTS__MARK,
170 FSIBOBT_MARK, FSIBIBT_MARK,
171 FSIBOLR_MARK, FSIBILR_MARK,
172 FSIBOSLD_MARK,
173 FSIBISLD_MARK,
174 VACK_MARK,
175 XTAL1L_MARK,
176 SCIFA0_RTS__MARK, FSICOSLDT2_MARK,
177 SCIFA0_RXD_MARK,
178 SCIFA0_CTS__MARK, FSICOSLDT1_MARK,
179 FSICOBT_MARK, FSICIBT_MARK, FSIDOBT_MARK, FSIDIBT_MARK,
180 FSICOLR_MARK, FSICILR_MARK, FSIDOLR_MARK, FSIDILR_MARK,
181 FSICOSLD_MARK, PORT47_FSICSPDIF_MARK,
182 FSICISLD_MARK, FSIDISLD_MARK,
183 FSIACK_MARK, PORT49_IRDA_OUT_MARK, PORT49_IROUT_MARK, FSIAOMC_MARK,
184 FSIAOLR_MARK, BBIF2_TSYNC2_MARK, TPU2TO2_MARK, FSIAILR_MARK,
185
186 FSIAOBT_MARK, BBIF2_TSCK2_MARK, TPU2TO3_MARK, FSIAIBT_MARK,
187 FSIAOSLD_MARK, BBIF2_TXD2_MARK,
188 FSIASPDIF_MARK, PORT53_IRDA_IN_MARK, TPU3TO3_MARK, FSIBSPDIF_MARK, \
189 PORT53_FSICSPDIF_MARK,
190 FSIBCK_MARK, PORT54_IRDA_FIRSEL_MARK, TPU3TO2_MARK, FSIBOMC_MARK, \
191 FSICCK_MARK, FSICOMC_MARK,
192 FSIAISLD_MARK, TPU0TO0_MARK,
193 A0_MARK, BS__MARK,
194 A12_MARK, PORT58_KEYOUT7_MARK, TPU4TO2_MARK,
195 A13_MARK, PORT59_KEYOUT6_MARK, TPU0TO1_MARK,
196 A14_MARK, KEYOUT5_MARK,
197 A15_MARK, KEYOUT4_MARK,
198 A16_MARK, KEYOUT3_MARK, MSIOF0_SS1_MARK,
199 A17_MARK, KEYOUT2_MARK, MSIOF0_TSYNC_MARK,
200 A18_MARK, KEYOUT1_MARK, MSIOF0_TSCK_MARK,
201 A19_MARK, KEYOUT0_MARK, MSIOF0_TXD_MARK,
202 A20_MARK, KEYIN0_MARK, MSIOF0_RSCK_MARK,
203 A21_MARK, KEYIN1_MARK, MSIOF0_RSYNC_MARK,
204 A22_MARK, KEYIN2_MARK, MSIOF0_MCK0_MARK,
205 A23_MARK, KEYIN3_MARK, MSIOF0_MCK1_MARK,
206 A24_MARK, KEYIN4_MARK, MSIOF0_RXD_MARK,
207 A25_MARK, KEYIN5_MARK, MSIOF0_SS2_MARK,
208 A26_MARK, KEYIN6_MARK,
209 KEYIN7_MARK,
210 D0_NAF0_MARK,
211 D1_NAF1_MARK,
212 D2_NAF2_MARK,
213 D3_NAF3_MARK,
214 D4_NAF4_MARK,
215 D5_NAF5_MARK,
216 D6_NAF6_MARK,
217 D7_NAF7_MARK,
218 D8_NAF8_MARK,
219 D9_NAF9_MARK,
220 D10_NAF10_MARK,
221 D11_NAF11_MARK,
222 D12_NAF12_MARK,
223 D13_NAF13_MARK,
224 D14_NAF14_MARK,
225 D15_NAF15_MARK,
226 CS4__MARK,
227 CS5A__MARK, PORT91_RDWR_MARK,
228 CS5B__MARK, FCE1__MARK,
229 CS6B__MARK, DACK0_MARK,
230 FCE0__MARK, CS6A__MARK,
231 WAIT__MARK, DREQ0_MARK,
232 RD__FSC_MARK,
233 WE0__FWE_MARK, RDWR_FWE_MARK,
234 WE1__MARK,
235 FRB_MARK,
236 CKO_MARK,
237 NBRSTOUT__MARK,
238 NBRST__MARK,
239 BBIF2_TXD_MARK,
240 BBIF2_RXD_MARK,
241 BBIF2_SYNC_MARK,
242 BBIF2_SCK_MARK,
243 SCIFA3_CTS__MARK, MFG3_IN2_MARK,
244 SCIFA3_RXD_MARK, MFG3_IN1_MARK,
245 BBIF1_SS2_MARK, SCIFA3_RTS__MARK, MFG3_OUT1_MARK,
246 SCIFA3_TXD_MARK,
247 HSI_RX_DATA_MARK, BBIF1_RXD_MARK,
248 HSI_TX_WAKE_MARK, BBIF1_TSCK_MARK,
249 HSI_TX_DATA_MARK, BBIF1_TSYNC_MARK,
250 HSI_TX_READY_MARK, BBIF1_TXD_MARK,
251 HSI_RX_READY_MARK, BBIF1_RSCK_MARK, PORT115_I2C_SCL2_MARK, \
252 PORT115_I2C_SCL3_MARK,
253 HSI_RX_WAKE_MARK, BBIF1_RSYNC_MARK, PORT116_I2C_SDA2_MARK, \
254 PORT116_I2C_SDA3_MARK,
255 HSI_RX_FLAG_MARK, BBIF1_SS1_MARK, BBIF1_FLOW_MARK,
256 HSI_TX_FLAG_MARK,
257 VIO_VD_MARK, PORT128_LCD2VSYN_MARK, VIO2_VD_MARK, LCD2D0_MARK,
258
259 VIO_HD_MARK, PORT129_LCD2HSYN_MARK, PORT129_LCD2CS__MARK, \
260 VIO2_HD_MARK, LCD2D1_MARK,
261 VIO_D0_MARK, PORT130_MSIOF2_RXD_MARK, LCD2D10_MARK,
262 VIO_D1_MARK, PORT131_KEYOUT6_MARK, PORT131_MSIOF2_SS1_MARK, \
263 PORT131_KEYOUT11_MARK, LCD2D11_MARK,
264 VIO_D2_MARK, PORT132_KEYOUT7_MARK, PORT132_MSIOF2_SS2_MARK, \
265 PORT132_KEYOUT10_MARK, LCD2D12_MARK,
266 VIO_D3_MARK, MSIOF2_TSYNC_MARK, LCD2D13_MARK,
267 VIO_D4_MARK, MSIOF2_TXD_MARK, LCD2D14_MARK,
268 VIO_D5_MARK, MSIOF2_TSCK_MARK, LCD2D15_MARK,
269 VIO_D6_MARK, PORT136_KEYOUT8_MARK, LCD2D16_MARK,
270 VIO_D7_MARK, PORT137_KEYOUT9_MARK, LCD2D17_MARK,
271 VIO_D8_MARK, PORT138_KEYOUT8_MARK, VIO2_D0_MARK, LCD2D6_MARK,
272 VIO_D9_MARK, PORT139_KEYOUT9_MARK, VIO2_D1_MARK, LCD2D7_MARK,
273 VIO_D10_MARK, TPU0TO2_MARK, VIO2_D2_MARK, LCD2D8_MARK,
274 VIO_D11_MARK, TPU0TO3_MARK, VIO2_D3_MARK, LCD2D9_MARK,
275 VIO_D12_MARK, PORT142_KEYOUT10_MARK, VIO2_D4_MARK, LCD2D2_MARK,
276 VIO_D13_MARK, PORT143_KEYOUT11_MARK, PORT143_KEYOUT6_MARK, \
277 VIO2_D5_MARK, LCD2D3_MARK,
278 VIO_D14_MARK, PORT144_KEYOUT7_MARK, VIO2_D6_MARK, LCD2D4_MARK,
279 VIO_D15_MARK, TPU1TO3_MARK, PORT145_LCD2DISP_MARK, \
280 PORT145_LCD2RS_MARK, VIO2_D7_MARK, LCD2D5_MARK,
281 VIO_CLK_MARK, LCD2DCK_MARK, PORT146_LCD2WR__MARK, VIO2_CLK_MARK, \
282 LCD2D18_MARK,
283 VIO_FIELD_MARK, LCD2RD__MARK, VIO2_FIELD_MARK, LCD2D19_MARK,
284 VIO_CKO_MARK,
285 A27_MARK, PORT149_RDWR_MARK, MFG0_IN1_MARK, PORT149_KEYOUT9_MARK,
286 MFG0_IN2_MARK,
287 TS_SPSYNC3_MARK, MSIOF2_RSCK_MARK,
288 TS_SDAT3_MARK, MSIOF2_RSYNC_MARK,
289 TPU1TO2_MARK, TS_SDEN3_MARK, PORT153_MSIOF2_SS1_MARK,
290 SCIFA2_TXD1_MARK, MSIOF2_MCK0_MARK,
291 SCIFA2_RXD1_MARK, MSIOF2_MCK1_MARK,
292 SCIFA2_RTS1__MARK, PORT156_MSIOF2_SS2_MARK,
293 SCIFA2_CTS1__MARK, PORT157_MSIOF2_RXD_MARK,
294 DINT__MARK, SCIFA2_SCK1_MARK, TS_SCK3_MARK,
295 PORT159_SCIFB_SCK_MARK, PORT159_SCIFA5_SCK_MARK, NMI_MARK,
296 PORT160_SCIFB_TXD_MARK, PORT160_SCIFA5_TXD_MARK,
297 PORT161_SCIFB_CTS__MARK, PORT161_SCIFA5_CTS__MARK,
298 PORT162_SCIFB_RXD_MARK, PORT162_SCIFA5_RXD_MARK,
299 PORT163_SCIFB_RTS__MARK, PORT163_SCIFA5_RTS__MARK, TPU3TO0_MARK,
300 LCDD0_MARK,
301 LCDD1_MARK, PORT193_SCIFA5_CTS__MARK, BBIF2_TSYNC1_MARK,
302 LCDD2_MARK, PORT194_SCIFA5_RTS__MARK, BBIF2_TSCK1_MARK,
303 LCDD3_MARK, PORT195_SCIFA5_RXD_MARK, BBIF2_TXD1_MARK,
304 LCDD4_MARK, PORT196_SCIFA5_TXD_MARK,
305 LCDD5_MARK, PORT197_SCIFA5_SCK_MARK, MFG2_OUT2_MARK, TPU2TO1_MARK,
306 LCDD6_MARK,
307 LCDD7_MARK, TPU4TO1_MARK, MFG4_OUT2_MARK,
308 LCDD8_MARK, D16_MARK,
309 LCDD9_MARK, D17_MARK,
310 LCDD10_MARK, D18_MARK,
311 LCDD11_MARK, D19_MARK,
312 LCDD12_MARK, D20_MARK,
313 LCDD13_MARK, D21_MARK,
314 LCDD14_MARK, D22_MARK,
315 LCDD15_MARK, PORT207_MSIOF0L_SS1_MARK, D23_MARK,
316 LCDD16_MARK, PORT208_MSIOF0L_SS2_MARK, D24_MARK,
317 LCDD17_MARK, D25_MARK,
318 LCDD18_MARK, DREQ2_MARK, PORT210_MSIOF0L_SS1_MARK, D26_MARK,
319 LCDD19_MARK, PORT211_MSIOF0L_SS2_MARK, D27_MARK,
320 LCDD20_MARK, TS_SPSYNC1_MARK, MSIOF0L_MCK0_MARK, D28_MARK,
321 LCDD21_MARK, TS_SDAT1_MARK, MSIOF0L_MCK1_MARK, D29_MARK,
322 LCDD22_MARK, TS_SDEN1_MARK, MSIOF0L_RSCK_MARK, D30_MARK,
323 LCDD23_MARK, TS_SCK1_MARK, MSIOF0L_RSYNC_MARK, D31_MARK,
324 LCDDCK_MARK, LCDWR__MARK,
325 LCDRD__MARK, DACK2_MARK, PORT217_LCD2RS_MARK, MSIOF0L_TSYNC_MARK, \
326 VIO2_FIELD3_MARK, PORT217_LCD2DISP_MARK,
327 LCDHSYN_MARK, LCDCS__MARK, LCDCS2__MARK, DACK3_MARK, \
328 PORT218_VIO_CKOR_MARK,
329 LCDDISP_MARK, LCDRS_MARK, PORT219_LCD2WR__MARK, DREQ3_MARK, \
330 MSIOF0L_TSCK_MARK, VIO2_CLK3_MARK, LCD2DCK_2_MARK,
331 LCDVSYN_MARK, LCDVSYN2_MARK,
332 LCDLCLK_MARK, DREQ1_MARK, PORT221_LCD2CS__MARK, PWEN_MARK, \
333 MSIOF0L_RXD_MARK, VIO2_HD3_MARK, PORT221_LCD2HSYN_MARK,
334 LCDDON_MARK, LCDDON2_MARK, DACK1_MARK, OVCN_MARK, MSIOF0L_TXD_MARK, \
335 VIO2_VD3_MARK, PORT222_LCD2VSYN_MARK,
336
337 SCIFA1_TXD_MARK, OVCN2_MARK,
338 EXTLP_MARK, SCIFA1_SCK_MARK, PORT226_VIO_CKO2_MARK,
339 SCIFA1_RTS__MARK, IDIN_MARK,
340 SCIFA1_RXD_MARK,
341 SCIFA1_CTS__MARK, MFG1_IN1_MARK,
342 MSIOF1_TXD_MARK, SCIFA2_TXD2_MARK,
343 MSIOF1_TSYNC_MARK, SCIFA2_CTS2__MARK,
344 MSIOF1_TSCK_MARK, SCIFA2_SCK2_MARK,
345 MSIOF1_RXD_MARK, SCIFA2_RXD2_MARK,
346 MSIOF1_RSCK_MARK, SCIFA2_RTS2__MARK, VIO2_CLK2_MARK, LCD2D20_MARK,
347 MSIOF1_RSYNC_MARK, MFG1_IN2_MARK, VIO2_VD2_MARK, LCD2D21_MARK,
348 MSIOF1_MCK0_MARK, PORT236_I2C_SDA2_MARK,
349 MSIOF1_MCK1_MARK, PORT237_I2C_SCL2_MARK,
350 MSIOF1_SS1_MARK, VIO2_FIELD2_MARK, LCD2D22_MARK,
351 MSIOF1_SS2_MARK, VIO2_HD2_MARK, LCD2D23_MARK,
352 SCIFA6_TXD_MARK,
353 PORT241_IRDA_OUT_MARK, PORT241_IROUT_MARK, MFG4_OUT1_MARK, TPU4TO0_MARK,
354 PORT242_IRDA_IN_MARK, MFG4_IN2_MARK,
355 PORT243_IRDA_FIRSEL_MARK, PORT243_VIO_CKO2_MARK,
356 PORT244_SCIFA5_CTS__MARK, MFG2_IN1_MARK, PORT244_SCIFB_CTS__MARK, \
357 MSIOF2R_RXD_MARK,
358 PORT245_SCIFA5_RTS__MARK, MFG2_IN2_MARK, PORT245_SCIFB_RTS__MARK, \
359 MSIOF2R_TXD_MARK,
360 PORT246_SCIFA5_RXD_MARK, MFG1_OUT1_MARK, PORT246_SCIFB_RXD_MARK, \
361 TPU1TO0_MARK,
362 PORT247_SCIFA5_TXD_MARK, MFG3_OUT2_MARK, PORT247_SCIFB_TXD_MARK, \
363 TPU3TO1_MARK,
364 PORT248_SCIFA5_SCK_MARK, MFG2_OUT1_MARK, PORT248_SCIFB_SCK_MARK, \
365 TPU2TO0_MARK, PORT248_I2C_SCL3_MARK, MSIOF2R_TSCK_MARK,
366 PORT249_IROUT_MARK, MFG4_IN1_MARK, PORT249_I2C_SDA3_MARK, \
367 MSIOF2R_TSYNC_MARK,
368 SDHICLK0_MARK,
369 SDHICD0_MARK,
370 SDHID0_0_MARK,
371 SDHID0_1_MARK,
372 SDHID0_2_MARK,
373 SDHID0_3_MARK,
374 SDHICMD0_MARK,
375 SDHIWP0_MARK,
376 SDHICLK1_MARK,
377 SDHID1_0_MARK, TS_SPSYNC2_MARK,
378 SDHID1_1_MARK, TS_SDAT2_MARK,
379 SDHID1_2_MARK, TS_SDEN2_MARK,
380 SDHID1_3_MARK, TS_SCK2_MARK,
381 SDHICMD1_MARK,
382 SDHICLK2_MARK,
383 SDHID2_0_MARK, TS_SPSYNC4_MARK,
384 SDHID2_1_MARK, TS_SDAT4_MARK,
385 SDHID2_2_MARK, TS_SDEN4_MARK,
386 SDHID2_3_MARK, TS_SCK4_MARK,
387 SDHICMD2_MARK,
388 MMCCLK0_MARK,
389 MMCD0_0_MARK,
390 MMCD0_1_MARK,
391 MMCD0_2_MARK,
392 MMCD0_3_MARK,
393 MMCD0_4_MARK, TS_SPSYNC5_MARK,
394 MMCD0_5_MARK, TS_SDAT5_MARK,
395 MMCD0_6_MARK, TS_SDEN5_MARK,
396 MMCD0_7_MARK, TS_SCK5_MARK,
397 MMCCMD0_MARK,
398 RESETOUTS__MARK, EXTAL2OUT_MARK,
399 MCP_WAIT__MCP_FRB_MARK,
400 MCP_CKO_MARK, MMCCLK1_MARK,
401 MCP_D15_MCP_NAF15_MARK,
402 MCP_D14_MCP_NAF14_MARK,
403 MCP_D13_MCP_NAF13_MARK,
404 MCP_D12_MCP_NAF12_MARK,
405 MCP_D11_MCP_NAF11_MARK,
406 MCP_D10_MCP_NAF10_MARK,
407 MCP_D9_MCP_NAF9_MARK,
408 MCP_D8_MCP_NAF8_MARK, MMCCMD1_MARK,
409 MCP_D7_MCP_NAF7_MARK, MMCD1_7_MARK,
410
411 MCP_D6_MCP_NAF6_MARK, MMCD1_6_MARK,
412 MCP_D5_MCP_NAF5_MARK, MMCD1_5_MARK,
413 MCP_D4_MCP_NAF4_MARK, MMCD1_4_MARK,
414 MCP_D3_MCP_NAF3_MARK, MMCD1_3_MARK,
415 MCP_D2_MCP_NAF2_MARK, MMCD1_2_MARK,
416 MCP_D1_MCP_NAF1_MARK, MMCD1_1_MARK,
417 MCP_D0_MCP_NAF0_MARK, MMCD1_0_MARK,
418 MCP_NBRSTOUT__MARK,
419 MCP_WE0__MCP_FWE_MARK, MCP_RDWR_MCP_FWE_MARK,
420
421 /* MSEL2 special cases */
422 TSIF2_TS_XX1_MARK,
423 TSIF2_TS_XX2_MARK,
424 TSIF2_TS_XX3_MARK,
425 TSIF2_TS_XX4_MARK,
426 TSIF2_TS_XX5_MARK,
427 TSIF1_TS_XX1_MARK,
428 TSIF1_TS_XX2_MARK,
429 TSIF1_TS_XX3_MARK,
430 TSIF1_TS_XX4_MARK,
431 TSIF1_TS_XX5_MARK,
432 TSIF0_TS_XX1_MARK,
433 TSIF0_TS_XX2_MARK,
434 TSIF0_TS_XX3_MARK,
435 TSIF0_TS_XX4_MARK,
436 TSIF0_TS_XX5_MARK,
437 MST1_TS_XX1_MARK,
438 MST1_TS_XX2_MARK,
439 MST1_TS_XX3_MARK,
440 MST1_TS_XX4_MARK,
441 MST1_TS_XX5_MARK,
442 MST0_TS_XX1_MARK,
443 MST0_TS_XX2_MARK,
444 MST0_TS_XX3_MARK,
445 MST0_TS_XX4_MARK,
446 MST0_TS_XX5_MARK,
447
448 /* MSEL3 special cases */
449 SDHI0_VCCQ_MC0_ON_MARK,
450 SDHI0_VCCQ_MC0_OFF_MARK,
451 DEBUG_MON_VIO_MARK,
452 DEBUG_MON_LCDD_MARK,
453 LCDC_LCDC0_MARK,
454 LCDC_LCDC1_MARK,
455
456 /* MSEL4 special cases */
457 IRQ9_MEM_INT_MARK,
458 IRQ9_MCP_INT_MARK,
459 A11_MARK,
460 KEYOUT8_MARK,
461 TPU4TO3_MARK,
462 RESETA_N_PU_ON_MARK,
463 RESETA_N_PU_OFF_MARK,
464 EDBGREQ_PD_MARK,
465 EDBGREQ_PU_MARK,
466
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]467 PINMUX_MARK_END,
468};
469
Laurent Pinchart19ac5552013-03-13 18:32:00 +0100[diff] [blame]470#define _PORT_DATA(pfx, sfx) PORT_DATA_IO(pfx)
471#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_PORT_DATA, , unused)
472
Laurent Pinchartcd3c1be2013-02-16 18:47:05 +0100[diff] [blame]473static const pinmux_enum_t pinmux_data[] = {
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]474 /* specify valid pin states for each pin in GPIO mode */
Laurent Pinchart19ac5552013-03-13 18:32:00 +0100[diff] [blame]475 PINMUX_DATA_GP_ALL(),
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]476
477 /* Table 25-1 (Function 0-7) */
478 PINMUX_DATA(VBUS_0_MARK, PORT0_FN1),
479 PINMUX_DATA(GPI0_MARK, PORT1_FN1),
480 PINMUX_DATA(GPI1_MARK, PORT2_FN1),
481 PINMUX_DATA(GPI2_MARK, PORT3_FN1),
482 PINMUX_DATA(GPI3_MARK, PORT4_FN1),
483 PINMUX_DATA(GPI4_MARK, PORT5_FN1),
484 PINMUX_DATA(GPI5_MARK, PORT6_FN1),
485 PINMUX_DATA(GPI6_MARK, PORT7_FN1),
486 PINMUX_DATA(GPI7_MARK, PORT8_FN1),
487 PINMUX_DATA(SCIFA7_RXD_MARK, PORT12_FN2),
488 PINMUX_DATA(SCIFA7_CTS__MARK, PORT13_FN2),
489 PINMUX_DATA(GPO7_MARK, PORT14_FN1), \
490 PINMUX_DATA(MFG0_OUT2_MARK, PORT14_FN4),
491 PINMUX_DATA(GPO6_MARK, PORT15_FN1), \
492 PINMUX_DATA(MFG1_OUT2_MARK, PORT15_FN4),
493 PINMUX_DATA(GPO5_MARK, PORT16_FN1), \
494 PINMUX_DATA(SCIFA0_SCK_MARK, PORT16_FN2), \
495 PINMUX_DATA(FSICOSLDT3_MARK, PORT16_FN3), \
496 PINMUX_DATA(PORT16_VIO_CKOR_MARK, PORT16_FN4),
497 PINMUX_DATA(SCIFA0_TXD_MARK, PORT17_FN2),
498 PINMUX_DATA(SCIFA7_TXD_MARK, PORT18_FN2),
499 PINMUX_DATA(SCIFA7_RTS__MARK, PORT19_FN2), \
500 PINMUX_DATA(PORT19_VIO_CKO2_MARK, PORT19_FN3),
501 PINMUX_DATA(GPO0_MARK, PORT20_FN1),
502 PINMUX_DATA(GPO1_MARK, PORT21_FN1),
503 PINMUX_DATA(GPO2_MARK, PORT22_FN1), \
504 PINMUX_DATA(STATUS0_MARK, PORT22_FN2),
505 PINMUX_DATA(GPO3_MARK, PORT23_FN1), \
506 PINMUX_DATA(STATUS1_MARK, PORT23_FN2),
507 PINMUX_DATA(GPO4_MARK, PORT24_FN1), \
508 PINMUX_DATA(STATUS2_MARK, PORT24_FN2),
509 PINMUX_DATA(VINT_MARK, PORT25_FN1),
510 PINMUX_DATA(TCKON_MARK, PORT26_FN1),
511 PINMUX_DATA(XDVFS1_MARK, PORT27_FN1), \
512 PINMUX_DATA(PORT27_I2C_SCL2_MARK, PORT27_FN2, MSEL2CR_MSEL17_0,
513 MSEL2CR_MSEL16_1), \
514 PINMUX_DATA(PORT27_I2C_SCL3_MARK, PORT27_FN3, MSEL2CR_MSEL19_0,
515 MSEL2CR_MSEL18_1), \
516 PINMUX_DATA(MFG0_OUT1_MARK, PORT27_FN4), \
517 PINMUX_DATA(PORT27_IROUT_MARK, PORT27_FN7),
518 PINMUX_DATA(XDVFS2_MARK, PORT28_FN1), \
519 PINMUX_DATA(PORT28_I2C_SDA2_MARK, PORT28_FN2, MSEL2CR_MSEL17_0,
520 MSEL2CR_MSEL16_1), \
521 PINMUX_DATA(PORT28_I2C_SDA3_MARK, PORT28_FN3, MSEL2CR_MSEL19_0,
522 MSEL2CR_MSEL18_1), \
523 PINMUX_DATA(PORT28_TPU1TO1_MARK, PORT28_FN7),
524 PINMUX_DATA(SIM_RST_MARK, PORT29_FN1), \
525 PINMUX_DATA(PORT29_TPU1TO1_MARK, PORT29_FN4),
526 PINMUX_DATA(SIM_CLK_MARK, PORT30_FN1), \
527 PINMUX_DATA(PORT30_VIO_CKOR_MARK, PORT30_FN4),
528 PINMUX_DATA(SIM_D_MARK, PORT31_FN1), \
529 PINMUX_DATA(PORT31_IROUT_MARK, PORT31_FN4),
530 PINMUX_DATA(SCIFA4_TXD_MARK, PORT32_FN2),
531 PINMUX_DATA(SCIFA4_RXD_MARK, PORT33_FN2), \
532 PINMUX_DATA(XWUP_MARK, PORT33_FN3),
533 PINMUX_DATA(SCIFA4_RTS__MARK, PORT34_FN2),
534 PINMUX_DATA(SCIFA4_CTS__MARK, PORT35_FN2),
535 PINMUX_DATA(FSIBOBT_MARK, PORT36_FN1), \
536 PINMUX_DATA(FSIBIBT_MARK, PORT36_FN2),
537 PINMUX_DATA(FSIBOLR_MARK, PORT37_FN1), \
538 PINMUX_DATA(FSIBILR_MARK, PORT37_FN2),
539 PINMUX_DATA(FSIBOSLD_MARK, PORT38_FN1),
540 PINMUX_DATA(FSIBISLD_MARK, PORT39_FN1),
541 PINMUX_DATA(VACK_MARK, PORT40_FN1),
542 PINMUX_DATA(XTAL1L_MARK, PORT41_FN1),
543 PINMUX_DATA(SCIFA0_RTS__MARK, PORT42_FN2), \
544 PINMUX_DATA(FSICOSLDT2_MARK, PORT42_FN3),
545 PINMUX_DATA(SCIFA0_RXD_MARK, PORT43_FN2),
546 PINMUX_DATA(SCIFA0_CTS__MARK, PORT44_FN2), \
547 PINMUX_DATA(FSICOSLDT1_MARK, PORT44_FN3),
548 PINMUX_DATA(FSICOBT_MARK, PORT45_FN1), \
549 PINMUX_DATA(FSICIBT_MARK, PORT45_FN2), \
550 PINMUX_DATA(FSIDOBT_MARK, PORT45_FN3), \
551 PINMUX_DATA(FSIDIBT_MARK, PORT45_FN4),
552 PINMUX_DATA(FSICOLR_MARK, PORT46_FN1), \
553 PINMUX_DATA(FSICILR_MARK, PORT46_FN2), \
554 PINMUX_DATA(FSIDOLR_MARK, PORT46_FN3), \
555 PINMUX_DATA(FSIDILR_MARK, PORT46_FN4),
556 PINMUX_DATA(FSICOSLD_MARK, PORT47_FN1), \
557 PINMUX_DATA(PORT47_FSICSPDIF_MARK, PORT47_FN2),
558 PINMUX_DATA(FSICISLD_MARK, PORT48_FN1), \
559 PINMUX_DATA(FSIDISLD_MARK, PORT48_FN3),
560 PINMUX_DATA(FSIACK_MARK, PORT49_FN1), \
561 PINMUX_DATA(PORT49_IRDA_OUT_MARK, PORT49_FN2, MSEL4CR_MSEL19_1), \
562 PINMUX_DATA(PORT49_IROUT_MARK, PORT49_FN4), \
563 PINMUX_DATA(FSIAOMC_MARK, PORT49_FN5),
564 PINMUX_DATA(FSIAOLR_MARK, PORT50_FN1), \
565 PINMUX_DATA(BBIF2_TSYNC2_MARK, PORT50_FN2), \
566 PINMUX_DATA(TPU2TO2_MARK, PORT50_FN3), \
567 PINMUX_DATA(FSIAILR_MARK, PORT50_FN5),
568
569 PINMUX_DATA(FSIAOBT_MARK, PORT51_FN1), \
570 PINMUX_DATA(BBIF2_TSCK2_MARK, PORT51_FN2), \
571 PINMUX_DATA(TPU2TO3_MARK, PORT51_FN3), \
572 PINMUX_DATA(FSIAIBT_MARK, PORT51_FN5),
573 PINMUX_DATA(FSIAOSLD_MARK, PORT52_FN1), \
574 PINMUX_DATA(BBIF2_TXD2_MARK, PORT52_FN2),
575 PINMUX_DATA(FSIASPDIF_MARK, PORT53_FN1), \
576 PINMUX_DATA(PORT53_IRDA_IN_MARK, PORT53_FN2, MSEL4CR_MSEL19_1), \
577 PINMUX_DATA(TPU3TO3_MARK, PORT53_FN3), \
578 PINMUX_DATA(FSIBSPDIF_MARK, PORT53_FN5), \
579 PINMUX_DATA(PORT53_FSICSPDIF_MARK, PORT53_FN6),
580 PINMUX_DATA(FSIBCK_MARK, PORT54_FN1), \
581 PINMUX_DATA(PORT54_IRDA_FIRSEL_MARK, PORT54_FN2, MSEL4CR_MSEL19_1), \
582 PINMUX_DATA(TPU3TO2_MARK, PORT54_FN3), \
583 PINMUX_DATA(FSIBOMC_MARK, PORT54_FN5), \
584 PINMUX_DATA(FSICCK_MARK, PORT54_FN6), \
585 PINMUX_DATA(FSICOMC_MARK, PORT54_FN7),
586 PINMUX_DATA(FSIAISLD_MARK, PORT55_FN1), \
587 PINMUX_DATA(TPU0TO0_MARK, PORT55_FN3),
588 PINMUX_DATA(A0_MARK, PORT57_FN1), \
589 PINMUX_DATA(BS__MARK, PORT57_FN2),
590 PINMUX_DATA(A12_MARK, PORT58_FN1), \
591 PINMUX_DATA(PORT58_KEYOUT7_MARK, PORT58_FN2), \
592 PINMUX_DATA(TPU4TO2_MARK, PORT58_FN4),
593 PINMUX_DATA(A13_MARK, PORT59_FN1), \
594 PINMUX_DATA(PORT59_KEYOUT6_MARK, PORT59_FN2), \
595 PINMUX_DATA(TPU0TO1_MARK, PORT59_FN4),
596 PINMUX_DATA(A14_MARK, PORT60_FN1), \
597 PINMUX_DATA(KEYOUT5_MARK, PORT60_FN2),
598 PINMUX_DATA(A15_MARK, PORT61_FN1), \
599 PINMUX_DATA(KEYOUT4_MARK, PORT61_FN2),
600 PINMUX_DATA(A16_MARK, PORT62_FN1), \
601 PINMUX_DATA(KEYOUT3_MARK, PORT62_FN2), \
602 PINMUX_DATA(MSIOF0_SS1_MARK, PORT62_FN4, MSEL3CR_MSEL11_0),
603 PINMUX_DATA(A17_MARK, PORT63_FN1), \
604 PINMUX_DATA(KEYOUT2_MARK, PORT63_FN2), \
605 PINMUX_DATA(MSIOF0_TSYNC_MARK, PORT63_FN4, MSEL3CR_MSEL11_0),
606 PINMUX_DATA(A18_MARK, PORT64_FN1), \
607 PINMUX_DATA(KEYOUT1_MARK, PORT64_FN2), \
608 PINMUX_DATA(MSIOF0_TSCK_MARK, PORT64_FN4, MSEL3CR_MSEL11_0),
609 PINMUX_DATA(A19_MARK, PORT65_FN1), \
610 PINMUX_DATA(KEYOUT0_MARK, PORT65_FN2), \
611 PINMUX_DATA(MSIOF0_TXD_MARK, PORT65_FN4, MSEL3CR_MSEL11_0),
612 PINMUX_DATA(A20_MARK, PORT66_FN1), \
613 PINMUX_DATA(KEYIN0_MARK, PORT66_FN2), \
614 PINMUX_DATA(MSIOF0_RSCK_MARK, PORT66_FN4, MSEL3CR_MSEL11_0),
615 PINMUX_DATA(A21_MARK, PORT67_FN1), \
616 PINMUX_DATA(KEYIN1_MARK, PORT67_FN2), \
617 PINMUX_DATA(MSIOF0_RSYNC_MARK, PORT67_FN4, MSEL3CR_MSEL11_0),
618 PINMUX_DATA(A22_MARK, PORT68_FN1), \
619 PINMUX_DATA(KEYIN2_MARK, PORT68_FN2), \
620 PINMUX_DATA(MSIOF0_MCK0_MARK, PORT68_FN4, MSEL3CR_MSEL11_0),
621 PINMUX_DATA(A23_MARK, PORT69_FN1), \
622 PINMUX_DATA(KEYIN3_MARK, PORT69_FN2), \
623 PINMUX_DATA(MSIOF0_MCK1_MARK, PORT69_FN4, MSEL3CR_MSEL11_0),
624 PINMUX_DATA(A24_MARK, PORT70_FN1), \
625 PINMUX_DATA(KEYIN4_MARK, PORT70_FN2), \
626 PINMUX_DATA(MSIOF0_RXD_MARK, PORT70_FN4, MSEL3CR_MSEL11_0),
627 PINMUX_DATA(A25_MARK, PORT71_FN1), \
628 PINMUX_DATA(KEYIN5_MARK, PORT71_FN2), \
629 PINMUX_DATA(MSIOF0_SS2_MARK, PORT71_FN4, MSEL3CR_MSEL11_0),
630 PINMUX_DATA(A26_MARK, PORT72_FN1), \
631 PINMUX_DATA(KEYIN6_MARK, PORT72_FN2),
632 PINMUX_DATA(KEYIN7_MARK, PORT73_FN2),
633 PINMUX_DATA(D0_NAF0_MARK, PORT74_FN1),
634 PINMUX_DATA(D1_NAF1_MARK, PORT75_FN1),
635 PINMUX_DATA(D2_NAF2_MARK, PORT76_FN1),
636 PINMUX_DATA(D3_NAF3_MARK, PORT77_FN1),
637 PINMUX_DATA(D4_NAF4_MARK, PORT78_FN1),
638 PINMUX_DATA(D5_NAF5_MARK, PORT79_FN1),
639 PINMUX_DATA(D6_NAF6_MARK, PORT80_FN1),
640 PINMUX_DATA(D7_NAF7_MARK, PORT81_FN1),
641 PINMUX_DATA(D8_NAF8_MARK, PORT82_FN1),
642 PINMUX_DATA(D9_NAF9_MARK, PORT83_FN1),
643 PINMUX_DATA(D10_NAF10_MARK, PORT84_FN1),
644 PINMUX_DATA(D11_NAF11_MARK, PORT85_FN1),
645 PINMUX_DATA(D12_NAF12_MARK, PORT86_FN1),
646 PINMUX_DATA(D13_NAF13_MARK, PORT87_FN1),
647 PINMUX_DATA(D14_NAF14_MARK, PORT88_FN1),
648 PINMUX_DATA(D15_NAF15_MARK, PORT89_FN1),
649 PINMUX_DATA(CS4__MARK, PORT90_FN1),
650 PINMUX_DATA(CS5A__MARK, PORT91_FN1), \
651 PINMUX_DATA(PORT91_RDWR_MARK, PORT91_FN2),
652 PINMUX_DATA(CS5B__MARK, PORT92_FN1), \
653 PINMUX_DATA(FCE1__MARK, PORT92_FN2),
654 PINMUX_DATA(CS6B__MARK, PORT93_FN1), \
655 PINMUX_DATA(DACK0_MARK, PORT93_FN4),
656 PINMUX_DATA(FCE0__MARK, PORT94_FN1), \
657 PINMUX_DATA(CS6A__MARK, PORT94_FN2),
658 PINMUX_DATA(WAIT__MARK, PORT95_FN1), \
659 PINMUX_DATA(DREQ0_MARK, PORT95_FN2),
660 PINMUX_DATA(RD__FSC_MARK, PORT96_FN1),
661 PINMUX_DATA(WE0__FWE_MARK, PORT97_FN1), \
662 PINMUX_DATA(RDWR_FWE_MARK, PORT97_FN2),
663 PINMUX_DATA(WE1__MARK, PORT98_FN1),
664 PINMUX_DATA(FRB_MARK, PORT99_FN1),
665 PINMUX_DATA(CKO_MARK, PORT100_FN1),
666 PINMUX_DATA(NBRSTOUT__MARK, PORT101_FN1),
667 PINMUX_DATA(NBRST__MARK, PORT102_FN1),
668 PINMUX_DATA(BBIF2_TXD_MARK, PORT103_FN3),
669 PINMUX_DATA(BBIF2_RXD_MARK, PORT104_FN3),
670 PINMUX_DATA(BBIF2_SYNC_MARK, PORT105_FN3),
671 PINMUX_DATA(BBIF2_SCK_MARK, PORT106_FN3),
672 PINMUX_DATA(SCIFA3_CTS__MARK, PORT107_FN3), \
673 PINMUX_DATA(MFG3_IN2_MARK, PORT107_FN4),
674 PINMUX_DATA(SCIFA3_RXD_MARK, PORT108_FN3), \
675 PINMUX_DATA(MFG3_IN1_MARK, PORT108_FN4),
676 PINMUX_DATA(BBIF1_SS2_MARK, PORT109_FN2), \
677 PINMUX_DATA(SCIFA3_RTS__MARK, PORT109_FN3), \
678 PINMUX_DATA(MFG3_OUT1_MARK, PORT109_FN4),
679 PINMUX_DATA(SCIFA3_TXD_MARK, PORT110_FN3),
680 PINMUX_DATA(HSI_RX_DATA_MARK, PORT111_FN1), \
681 PINMUX_DATA(BBIF1_RXD_MARK, PORT111_FN3),
682 PINMUX_DATA(HSI_TX_WAKE_MARK, PORT112_FN1), \
683 PINMUX_DATA(BBIF1_TSCK_MARK, PORT112_FN3),
684 PINMUX_DATA(HSI_TX_DATA_MARK, PORT113_FN1), \
685 PINMUX_DATA(BBIF1_TSYNC_MARK, PORT113_FN3),
686 PINMUX_DATA(HSI_TX_READY_MARK, PORT114_FN1), \
687 PINMUX_DATA(BBIF1_TXD_MARK, PORT114_FN3),
688 PINMUX_DATA(HSI_RX_READY_MARK, PORT115_FN1), \
689 PINMUX_DATA(BBIF1_RSCK_MARK, PORT115_FN3), \
690 PINMUX_DATA(PORT115_I2C_SCL2_MARK, PORT115_FN5, MSEL2CR_MSEL17_1), \
691 PINMUX_DATA(PORT115_I2C_SCL3_MARK, PORT115_FN6, MSEL2CR_MSEL19_1),
692 PINMUX_DATA(HSI_RX_WAKE_MARK, PORT116_FN1), \
693 PINMUX_DATA(BBIF1_RSYNC_MARK, PORT116_FN3), \
694 PINMUX_DATA(PORT116_I2C_SDA2_MARK, PORT116_FN5, MSEL2CR_MSEL17_1), \
695 PINMUX_DATA(PORT116_I2C_SDA3_MARK, PORT116_FN6, MSEL2CR_MSEL19_1),
696 PINMUX_DATA(HSI_RX_FLAG_MARK, PORT117_FN1), \
697 PINMUX_DATA(BBIF1_SS1_MARK, PORT117_FN2), \
698 PINMUX_DATA(BBIF1_FLOW_MARK, PORT117_FN3),
699 PINMUX_DATA(HSI_TX_FLAG_MARK, PORT118_FN1),
700 PINMUX_DATA(VIO_VD_MARK, PORT128_FN1), \
701 PINMUX_DATA(PORT128_LCD2VSYN_MARK, PORT128_FN4, MSEL3CR_MSEL2_0), \
702 PINMUX_DATA(VIO2_VD_MARK, PORT128_FN6, MSEL4CR_MSEL27_0), \
703 PINMUX_DATA(LCD2D0_MARK, PORT128_FN7),
704
705 PINMUX_DATA(VIO_HD_MARK, PORT129_FN1), \
706 PINMUX_DATA(PORT129_LCD2HSYN_MARK, PORT129_FN4), \
707 PINMUX_DATA(PORT129_LCD2CS__MARK, PORT129_FN5), \
708 PINMUX_DATA(VIO2_HD_MARK, PORT129_FN6, MSEL4CR_MSEL27_0), \
709 PINMUX_DATA(LCD2D1_MARK, PORT129_FN7),
710 PINMUX_DATA(VIO_D0_MARK, PORT130_FN1), \
711 PINMUX_DATA(PORT130_MSIOF2_RXD_MARK, PORT130_FN3, MSEL4CR_MSEL11_0,
712 MSEL4CR_MSEL10_1), \
713 PINMUX_DATA(LCD2D10_MARK, PORT130_FN7),
714 PINMUX_DATA(VIO_D1_MARK, PORT131_FN1), \
715 PINMUX_DATA(PORT131_KEYOUT6_MARK, PORT131_FN2), \
716 PINMUX_DATA(PORT131_MSIOF2_SS1_MARK, PORT131_FN3), \
717 PINMUX_DATA(PORT131_KEYOUT11_MARK, PORT131_FN4), \
718 PINMUX_DATA(LCD2D11_MARK, PORT131_FN7),
719 PINMUX_DATA(VIO_D2_MARK, PORT132_FN1), \
720 PINMUX_DATA(PORT132_KEYOUT7_MARK, PORT132_FN2), \
721 PINMUX_DATA(PORT132_MSIOF2_SS2_MARK, PORT132_FN3), \
722 PINMUX_DATA(PORT132_KEYOUT10_MARK, PORT132_FN4), \
723 PINMUX_DATA(LCD2D12_MARK, PORT132_FN7),
724 PINMUX_DATA(VIO_D3_MARK, PORT133_FN1), \
725 PINMUX_DATA(MSIOF2_TSYNC_MARK, PORT133_FN3, MSEL4CR_MSEL11_0), \
726 PINMUX_DATA(LCD2D13_MARK, PORT133_FN7),
727 PINMUX_DATA(VIO_D4_MARK, PORT134_FN1), \
728 PINMUX_DATA(MSIOF2_TXD_MARK, PORT134_FN3, MSEL4CR_MSEL11_0), \
729 PINMUX_DATA(LCD2D14_MARK, PORT134_FN7),
730 PINMUX_DATA(VIO_D5_MARK, PORT135_FN1), \
731 PINMUX_DATA(MSIOF2_TSCK_MARK, PORT135_FN3, MSEL4CR_MSEL11_0), \
732 PINMUX_DATA(LCD2D15_MARK, PORT135_FN7),
733 PINMUX_DATA(VIO_D6_MARK, PORT136_FN1), \
734 PINMUX_DATA(PORT136_KEYOUT8_MARK, PORT136_FN2), \
735 PINMUX_DATA(LCD2D16_MARK, PORT136_FN7),
736 PINMUX_DATA(VIO_D7_MARK, PORT137_FN1), \
737 PINMUX_DATA(PORT137_KEYOUT9_MARK, PORT137_FN2), \
738 PINMUX_DATA(LCD2D17_MARK, PORT137_FN7),
739 PINMUX_DATA(VIO_D8_MARK, PORT138_FN1), \
740 PINMUX_DATA(PORT138_KEYOUT8_MARK, PORT138_FN2), \
741 PINMUX_DATA(VIO2_D0_MARK, PORT138_FN6), \
742 PINMUX_DATA(LCD2D6_MARK, PORT138_FN7),
743 PINMUX_DATA(VIO_D9_MARK, PORT139_FN1), \
744 PINMUX_DATA(PORT139_KEYOUT9_MARK, PORT139_FN2), \
745 PINMUX_DATA(VIO2_D1_MARK, PORT139_FN6), \
746 PINMUX_DATA(LCD2D7_MARK, PORT139_FN7),
747 PINMUX_DATA(VIO_D10_MARK, PORT140_FN1), \
748 PINMUX_DATA(TPU0TO2_MARK, PORT140_FN4), \
749 PINMUX_DATA(VIO2_D2_MARK, PORT140_FN6), \
750 PINMUX_DATA(LCD2D8_MARK, PORT140_FN7),
751 PINMUX_DATA(VIO_D11_MARK, PORT141_FN1), \
752 PINMUX_DATA(TPU0TO3_MARK, PORT141_FN4), \
753 PINMUX_DATA(VIO2_D3_MARK, PORT141_FN6), \
754 PINMUX_DATA(LCD2D9_MARK, PORT141_FN7),
755 PINMUX_DATA(VIO_D12_MARK, PORT142_FN1), \
756 PINMUX_DATA(PORT142_KEYOUT10_MARK, PORT142_FN2), \
757 PINMUX_DATA(VIO2_D4_MARK, PORT142_FN6), \
758 PINMUX_DATA(LCD2D2_MARK, PORT142_FN7),
759 PINMUX_DATA(VIO_D13_MARK, PORT143_FN1), \
760 PINMUX_DATA(PORT143_KEYOUT11_MARK, PORT143_FN2), \
761 PINMUX_DATA(PORT143_KEYOUT6_MARK, PORT143_FN3), \
762 PINMUX_DATA(VIO2_D5_MARK, PORT143_FN6), \
763 PINMUX_DATA(LCD2D3_MARK, PORT143_FN7),
764 PINMUX_DATA(VIO_D14_MARK, PORT144_FN1), \
765 PINMUX_DATA(PORT144_KEYOUT7_MARK, PORT144_FN2), \
766 PINMUX_DATA(VIO2_D6_MARK, PORT144_FN6), \
767 PINMUX_DATA(LCD2D4_MARK, PORT144_FN7),
768 PINMUX_DATA(VIO_D15_MARK, PORT145_FN1), \
769 PINMUX_DATA(TPU1TO3_MARK, PORT145_FN3), \
770 PINMUX_DATA(PORT145_LCD2DISP_MARK, PORT145_FN4), \
771 PINMUX_DATA(PORT145_LCD2RS_MARK, PORT145_FN5), \
772 PINMUX_DATA(VIO2_D7_MARK, PORT145_FN6), \
773 PINMUX_DATA(LCD2D5_MARK, PORT145_FN7),
774 PINMUX_DATA(VIO_CLK_MARK, PORT146_FN1), \
775 PINMUX_DATA(LCD2DCK_MARK, PORT146_FN4), \
776 PINMUX_DATA(PORT146_LCD2WR__MARK, PORT146_FN5), \
777 PINMUX_DATA(VIO2_CLK_MARK, PORT146_FN6, MSEL4CR_MSEL27_0), \
778 PINMUX_DATA(LCD2D18_MARK, PORT146_FN7),
779 PINMUX_DATA(VIO_FIELD_MARK, PORT147_FN1), \
780 PINMUX_DATA(LCD2RD__MARK, PORT147_FN4), \
781 PINMUX_DATA(VIO2_FIELD_MARK, PORT147_FN6, MSEL4CR_MSEL27_0), \
782 PINMUX_DATA(LCD2D19_MARK, PORT147_FN7),
783 PINMUX_DATA(VIO_CKO_MARK, PORT148_FN1),
784 PINMUX_DATA(A27_MARK, PORT149_FN1), \
785 PINMUX_DATA(PORT149_RDWR_MARK, PORT149_FN2), \
786 PINMUX_DATA(MFG0_IN1_MARK, PORT149_FN3), \
787 PINMUX_DATA(PORT149_KEYOUT9_MARK, PORT149_FN4),
788 PINMUX_DATA(MFG0_IN2_MARK, PORT150_FN3),
789 PINMUX_DATA(TS_SPSYNC3_MARK, PORT151_FN4), \
790 PINMUX_DATA(MSIOF2_RSCK_MARK, PORT151_FN5),
791 PINMUX_DATA(TS_SDAT3_MARK, PORT152_FN4), \
792 PINMUX_DATA(MSIOF2_RSYNC_MARK, PORT152_FN5),
793 PINMUX_DATA(TPU1TO2_MARK, PORT153_FN3), \
794 PINMUX_DATA(TS_SDEN3_MARK, PORT153_FN4), \
795 PINMUX_DATA(PORT153_MSIOF2_SS1_MARK, PORT153_FN5),
796 PINMUX_DATA(SCIFA2_TXD1_MARK, PORT154_FN2, MSEL3CR_MSEL9_0), \
797 PINMUX_DATA(MSIOF2_MCK0_MARK, PORT154_FN5),
798 PINMUX_DATA(SCIFA2_RXD1_MARK, PORT155_FN2, MSEL3CR_MSEL9_0), \
799 PINMUX_DATA(MSIOF2_MCK1_MARK, PORT155_FN5),
800 PINMUX_DATA(SCIFA2_RTS1__MARK, PORT156_FN2, MSEL3CR_MSEL9_0), \
801 PINMUX_DATA(PORT156_MSIOF2_SS2_MARK, PORT156_FN5),
802 PINMUX_DATA(SCIFA2_CTS1__MARK, PORT157_FN2, MSEL3CR_MSEL9_0), \
803 PINMUX_DATA(PORT157_MSIOF2_RXD_MARK, PORT157_FN5, MSEL4CR_MSEL11_0,
804 MSEL4CR_MSEL10_0),
805 PINMUX_DATA(DINT__MARK, PORT158_FN1), \
806 PINMUX_DATA(SCIFA2_SCK1_MARK, PORT158_FN2, MSEL3CR_MSEL9_0), \
807 PINMUX_DATA(TS_SCK3_MARK, PORT158_FN4),
808 PINMUX_DATA(PORT159_SCIFB_SCK_MARK, PORT159_FN1, MSEL4CR_MSEL22_0), \
809 PINMUX_DATA(PORT159_SCIFA5_SCK_MARK, PORT159_FN2, MSEL4CR_MSEL21_1), \
810 PINMUX_DATA(NMI_MARK, PORT159_FN3),
811 PINMUX_DATA(PORT160_SCIFB_TXD_MARK, PORT160_FN1, MSEL4CR_MSEL22_0), \
812 PINMUX_DATA(PORT160_SCIFA5_TXD_MARK, PORT160_FN2, MSEL4CR_MSEL21_1),
813 PINMUX_DATA(PORT161_SCIFB_CTS__MARK, PORT161_FN1, MSEL4CR_MSEL22_0), \
814 PINMUX_DATA(PORT161_SCIFA5_CTS__MARK, PORT161_FN2, MSEL4CR_MSEL21_1),
815 PINMUX_DATA(PORT162_SCIFB_RXD_MARK, PORT162_FN1, MSEL4CR_MSEL22_0), \
816 PINMUX_DATA(PORT162_SCIFA5_RXD_MARK, PORT162_FN2, MSEL4CR_MSEL21_1),
817 PINMUX_DATA(PORT163_SCIFB_RTS__MARK, PORT163_FN1, MSEL4CR_MSEL22_0), \
818 PINMUX_DATA(PORT163_SCIFA5_RTS__MARK, PORT163_FN2, MSEL4CR_MSEL21_1), \
819 PINMUX_DATA(TPU3TO0_MARK, PORT163_FN5),
820 PINMUX_DATA(LCDD0_MARK, PORT192_FN1),
821 PINMUX_DATA(LCDD1_MARK, PORT193_FN1), \
822 PINMUX_DATA(PORT193_SCIFA5_CTS__MARK, PORT193_FN3, MSEL4CR_MSEL21_0,
823 MSEL4CR_MSEL20_1), \
824 PINMUX_DATA(BBIF2_TSYNC1_MARK, PORT193_FN5),
825 PINMUX_DATA(LCDD2_MARK, PORT194_FN1), \
826 PINMUX_DATA(PORT194_SCIFA5_RTS__MARK, PORT194_FN3, MSEL4CR_MSEL21_0,
827 MSEL4CR_MSEL20_1), \
828 PINMUX_DATA(BBIF2_TSCK1_MARK, PORT194_FN5),
829 PINMUX_DATA(LCDD3_MARK, PORT195_FN1), \
830 PINMUX_DATA(PORT195_SCIFA5_RXD_MARK, PORT195_FN3, MSEL4CR_MSEL21_0,
831 MSEL4CR_MSEL20_1), \
832 PINMUX_DATA(BBIF2_TXD1_MARK, PORT195_FN5),
833 PINMUX_DATA(LCDD4_MARK, PORT196_FN1), \
834 PINMUX_DATA(PORT196_SCIFA5_TXD_MARK, PORT196_FN3, MSEL4CR_MSEL21_0,
835 MSEL4CR_MSEL20_1),
836 PINMUX_DATA(LCDD5_MARK, PORT197_FN1), \
837 PINMUX_DATA(PORT197_SCIFA5_SCK_MARK, PORT197_FN3, MSEL4CR_MSEL21_0,
838 MSEL4CR_MSEL20_1), \
839 PINMUX_DATA(MFG2_OUT2_MARK, PORT197_FN5), \
840 PINMUX_DATA(TPU2TO1_MARK, PORT197_FN7),
841 PINMUX_DATA(LCDD6_MARK, PORT198_FN1),
842 PINMUX_DATA(LCDD7_MARK, PORT199_FN1), \
843 PINMUX_DATA(TPU4TO1_MARK, PORT199_FN2), \
844 PINMUX_DATA(MFG4_OUT2_MARK, PORT199_FN5),
845 PINMUX_DATA(LCDD8_MARK, PORT200_FN1), \
846 PINMUX_DATA(D16_MARK, PORT200_FN6),
847 PINMUX_DATA(LCDD9_MARK, PORT201_FN1), \
848 PINMUX_DATA(D17_MARK, PORT201_FN6),
849 PINMUX_DATA(LCDD10_MARK, PORT202_FN1), \
850 PINMUX_DATA(D18_MARK, PORT202_FN6),
851 PINMUX_DATA(LCDD11_MARK, PORT203_FN1), \
852 PINMUX_DATA(D19_MARK, PORT203_FN6),
853 PINMUX_DATA(LCDD12_MARK, PORT204_FN1), \
854 PINMUX_DATA(D20_MARK, PORT204_FN6),
855 PINMUX_DATA(LCDD13_MARK, PORT205_FN1), \
856 PINMUX_DATA(D21_MARK, PORT205_FN6),
857 PINMUX_DATA(LCDD14_MARK, PORT206_FN1), \
858 PINMUX_DATA(D22_MARK, PORT206_FN6),
859 PINMUX_DATA(LCDD15_MARK, PORT207_FN1), \
860 PINMUX_DATA(PORT207_MSIOF0L_SS1_MARK, PORT207_FN2, MSEL3CR_MSEL11_1), \
861 PINMUX_DATA(D23_MARK, PORT207_FN6),
862 PINMUX_DATA(LCDD16_MARK, PORT208_FN1), \
863 PINMUX_DATA(PORT208_MSIOF0L_SS2_MARK, PORT208_FN2, MSEL3CR_MSEL11_1), \
864 PINMUX_DATA(D24_MARK, PORT208_FN6),
865 PINMUX_DATA(LCDD17_MARK, PORT209_FN1), \
866 PINMUX_DATA(D25_MARK, PORT209_FN6),
867 PINMUX_DATA(LCDD18_MARK, PORT210_FN1), \
868 PINMUX_DATA(DREQ2_MARK, PORT210_FN2), \
869 PINMUX_DATA(PORT210_MSIOF0L_SS1_MARK, PORT210_FN5, MSEL3CR_MSEL11_1), \
870 PINMUX_DATA(D26_MARK, PORT210_FN6),
871 PINMUX_DATA(LCDD19_MARK, PORT211_FN1), \
872 PINMUX_DATA(PORT211_MSIOF0L_SS2_MARK, PORT211_FN5, MSEL3CR_MSEL11_1), \
873 PINMUX_DATA(D27_MARK, PORT211_FN6),
874 PINMUX_DATA(LCDD20_MARK, PORT212_FN1), \
875 PINMUX_DATA(TS_SPSYNC1_MARK, PORT212_FN2), \
876 PINMUX_DATA(MSIOF0L_MCK0_MARK, PORT212_FN5, MSEL3CR_MSEL11_1), \
877 PINMUX_DATA(D28_MARK, PORT212_FN6),
878 PINMUX_DATA(LCDD21_MARK, PORT213_FN1), \
879 PINMUX_DATA(TS_SDAT1_MARK, PORT213_FN2), \
880 PINMUX_DATA(MSIOF0L_MCK1_MARK, PORT213_FN5, MSEL3CR_MSEL11_1), \
881 PINMUX_DATA(D29_MARK, PORT213_FN6),
882 PINMUX_DATA(LCDD22_MARK, PORT214_FN1), \
883 PINMUX_DATA(TS_SDEN1_MARK, PORT214_FN2), \
884 PINMUX_DATA(MSIOF0L_RSCK_MARK, PORT214_FN5, MSEL3CR_MSEL11_1), \
885 PINMUX_DATA(D30_MARK, PORT214_FN6),
886 PINMUX_DATA(LCDD23_MARK, PORT215_FN1), \
887 PINMUX_DATA(TS_SCK1_MARK, PORT215_FN2), \
888 PINMUX_DATA(MSIOF0L_RSYNC_MARK, PORT215_FN5, MSEL3CR_MSEL11_1), \
889 PINMUX_DATA(D31_MARK, PORT215_FN6),
890 PINMUX_DATA(LCDDCK_MARK, PORT216_FN1), \
891 PINMUX_DATA(LCDWR__MARK, PORT216_FN2),
892 PINMUX_DATA(LCDRD__MARK, PORT217_FN1), \
893 PINMUX_DATA(DACK2_MARK, PORT217_FN2), \
894 PINMUX_DATA(PORT217_LCD2RS_MARK, PORT217_FN3), \
895 PINMUX_DATA(MSIOF0L_TSYNC_MARK, PORT217_FN5, MSEL3CR_MSEL11_1), \
896 PINMUX_DATA(VIO2_FIELD3_MARK, PORT217_FN6, MSEL4CR_MSEL27_1,
897 MSEL4CR_MSEL26_1), \
898 PINMUX_DATA(PORT217_LCD2DISP_MARK, PORT217_FN7),
899 PINMUX_DATA(LCDHSYN_MARK, PORT218_FN1), \
900 PINMUX_DATA(LCDCS__MARK, PORT218_FN2), \
901 PINMUX_DATA(LCDCS2__MARK, PORT218_FN3), \
902 PINMUX_DATA(DACK3_MARK, PORT218_FN4), \
903 PINMUX_DATA(PORT218_VIO_CKOR_MARK, PORT218_FN5),
904 PINMUX_DATA(LCDDISP_MARK, PORT219_FN1), \
905 PINMUX_DATA(LCDRS_MARK, PORT219_FN2), \
906 PINMUX_DATA(PORT219_LCD2WR__MARK, PORT219_FN3), \
907 PINMUX_DATA(DREQ3_MARK, PORT219_FN4), \
908 PINMUX_DATA(MSIOF0L_TSCK_MARK, PORT219_FN5, MSEL3CR_MSEL11_1), \
909 PINMUX_DATA(VIO2_CLK3_MARK, PORT219_FN6, MSEL4CR_MSEL27_1,
910 MSEL4CR_MSEL26_1), \
911 PINMUX_DATA(LCD2DCK_2_MARK, PORT219_FN7),
912 PINMUX_DATA(LCDVSYN_MARK, PORT220_FN1), \
913 PINMUX_DATA(LCDVSYN2_MARK, PORT220_FN2),
914 PINMUX_DATA(LCDLCLK_MARK, PORT221_FN1), \
915 PINMUX_DATA(DREQ1_MARK, PORT221_FN2), \
916 PINMUX_DATA(PORT221_LCD2CS__MARK, PORT221_FN3), \
917 PINMUX_DATA(PWEN_MARK, PORT221_FN4), \
918 PINMUX_DATA(MSIOF0L_RXD_MARK, PORT221_FN5, MSEL3CR_MSEL11_1), \
919 PINMUX_DATA(VIO2_HD3_MARK, PORT221_FN6, MSEL4CR_MSEL27_1,
920 MSEL4CR_MSEL26_1), \
921 PINMUX_DATA(PORT221_LCD2HSYN_MARK, PORT221_FN7),
922 PINMUX_DATA(LCDDON_MARK, PORT222_FN1), \
923 PINMUX_DATA(LCDDON2_MARK, PORT222_FN2), \
924 PINMUX_DATA(DACK1_MARK, PORT222_FN3), \
925 PINMUX_DATA(OVCN_MARK, PORT222_FN4), \
926 PINMUX_DATA(MSIOF0L_TXD_MARK, PORT222_FN5, MSEL3CR_MSEL11_1), \
927 PINMUX_DATA(VIO2_VD3_MARK, PORT222_FN6, MSEL4CR_MSEL27_1,
928 MSEL4CR_MSEL26_1), \
929 PINMUX_DATA(PORT222_LCD2VSYN_MARK, PORT222_FN7, MSEL3CR_MSEL2_1),
930
931 PINMUX_DATA(SCIFA1_TXD_MARK, PORT225_FN2), \
932 PINMUX_DATA(OVCN2_MARK, PORT225_FN4),
933 PINMUX_DATA(EXTLP_MARK, PORT226_FN1), \
934 PINMUX_DATA(SCIFA1_SCK_MARK, PORT226_FN2), \
935 PINMUX_DATA(PORT226_VIO_CKO2_MARK, PORT226_FN5),
936 PINMUX_DATA(SCIFA1_RTS__MARK, PORT227_FN2), \
937 PINMUX_DATA(IDIN_MARK, PORT227_FN4),
938 PINMUX_DATA(SCIFA1_RXD_MARK, PORT228_FN2),
939 PINMUX_DATA(SCIFA1_CTS__MARK, PORT229_FN2), \
940 PINMUX_DATA(MFG1_IN1_MARK, PORT229_FN3),
941 PINMUX_DATA(MSIOF1_TXD_MARK, PORT230_FN1), \
942 PINMUX_DATA(SCIFA2_TXD2_MARK, PORT230_FN2, MSEL3CR_MSEL9_1),
943 PINMUX_DATA(MSIOF1_TSYNC_MARK, PORT231_FN1), \
944 PINMUX_DATA(SCIFA2_CTS2__MARK, PORT231_FN2, MSEL3CR_MSEL9_1),
945 PINMUX_DATA(MSIOF1_TSCK_MARK, PORT232_FN1), \
946 PINMUX_DATA(SCIFA2_SCK2_MARK, PORT232_FN2, MSEL3CR_MSEL9_1),
947 PINMUX_DATA(MSIOF1_RXD_MARK, PORT233_FN1), \
948 PINMUX_DATA(SCIFA2_RXD2_MARK, PORT233_FN2, MSEL3CR_MSEL9_1),
949 PINMUX_DATA(MSIOF1_RSCK_MARK, PORT234_FN1), \
950 PINMUX_DATA(SCIFA2_RTS2__MARK, PORT234_FN2, MSEL3CR_MSEL9_1), \
951 PINMUX_DATA(VIO2_CLK2_MARK, PORT234_FN6, MSEL4CR_MSEL27_1,
952 MSEL4CR_MSEL26_0), \
953 PINMUX_DATA(LCD2D20_MARK, PORT234_FN7),
954 PINMUX_DATA(MSIOF1_RSYNC_MARK, PORT235_FN1), \
955 PINMUX_DATA(MFG1_IN2_MARK, PORT235_FN3), \
956 PINMUX_DATA(VIO2_VD2_MARK, PORT235_FN6, MSEL4CR_MSEL27_1,
957 MSEL4CR_MSEL26_0), \
958 PINMUX_DATA(LCD2D21_MARK, PORT235_FN7),
959 PINMUX_DATA(MSIOF1_MCK0_MARK, PORT236_FN1), \
960 PINMUX_DATA(PORT236_I2C_SDA2_MARK, PORT236_FN2, MSEL2CR_MSEL17_0,
961 MSEL2CR_MSEL16_0),
962 PINMUX_DATA(MSIOF1_MCK1_MARK, PORT237_FN1), \
963 PINMUX_DATA(PORT237_I2C_SCL2_MARK, PORT237_FN2, MSEL2CR_MSEL17_0,
964 MSEL2CR_MSEL16_0),
965 PINMUX_DATA(MSIOF1_SS1_MARK, PORT238_FN1), \
966 PINMUX_DATA(VIO2_FIELD2_MARK, PORT238_FN6, MSEL4CR_MSEL27_1,
967 MSEL4CR_MSEL26_0), \
968 PINMUX_DATA(LCD2D22_MARK, PORT238_FN7),
969 PINMUX_DATA(MSIOF1_SS2_MARK, PORT239_FN1), \
970 PINMUX_DATA(VIO2_HD2_MARK, PORT239_FN6, MSEL4CR_MSEL27_1,
971 MSEL4CR_MSEL26_0), \
972 PINMUX_DATA(LCD2D23_MARK, PORT239_FN7),
973 PINMUX_DATA(SCIFA6_TXD_MARK, PORT240_FN1),
974 PINMUX_DATA(PORT241_IRDA_OUT_MARK, PORT241_FN1, MSEL4CR_MSEL19_0), \
975 PINMUX_DATA(PORT241_IROUT_MARK, PORT241_FN2), \
976 PINMUX_DATA(MFG4_OUT1_MARK, PORT241_FN3), \
977 PINMUX_DATA(TPU4TO0_MARK, PORT241_FN4),
978 PINMUX_DATA(PORT242_IRDA_IN_MARK, PORT242_FN1, MSEL4CR_MSEL19_0), \
979 PINMUX_DATA(MFG4_IN2_MARK, PORT242_FN3),
980 PINMUX_DATA(PORT243_IRDA_FIRSEL_MARK, PORT243_FN1, MSEL4CR_MSEL19_0), \
981 PINMUX_DATA(PORT243_VIO_CKO2_MARK, PORT243_FN2),
982 PINMUX_DATA(PORT244_SCIFA5_CTS__MARK, PORT244_FN1, MSEL4CR_MSEL21_0,
983 MSEL4CR_MSEL20_0), \
984 PINMUX_DATA(MFG2_IN1_MARK, PORT244_FN2), \
985 PINMUX_DATA(PORT244_SCIFB_CTS__MARK, PORT244_FN3, MSEL4CR_MSEL22_1), \
986 PINMUX_DATA(MSIOF2R_RXD_MARK, PORT244_FN7, MSEL4CR_MSEL11_1),
987 PINMUX_DATA(PORT245_SCIFA5_RTS__MARK, PORT245_FN1, MSEL4CR_MSEL21_0,
988 MSEL4CR_MSEL20_0), \
989 PINMUX_DATA(MFG2_IN2_MARK, PORT245_FN2), \
990 PINMUX_DATA(PORT245_SCIFB_RTS__MARK, PORT245_FN3, MSEL4CR_MSEL22_1), \
991 PINMUX_DATA(MSIOF2R_TXD_MARK, PORT245_FN7, MSEL4CR_MSEL11_1),
992 PINMUX_DATA(PORT246_SCIFA5_RXD_MARK, PORT246_FN1, MSEL4CR_MSEL21_0,
993 MSEL4CR_MSEL20_0), \
994 PINMUX_DATA(MFG1_OUT1_MARK, PORT246_FN2), \
995 PINMUX_DATA(PORT246_SCIFB_RXD_MARK, PORT246_FN3, MSEL4CR_MSEL22_1), \
996 PINMUX_DATA(TPU1TO0_MARK, PORT246_FN4),
997 PINMUX_DATA(PORT247_SCIFA5_TXD_MARK, PORT247_FN1, MSEL4CR_MSEL21_0,
998 MSEL4CR_MSEL20_0), \
999 PINMUX_DATA(MFG3_OUT2_MARK, PORT247_FN2), \
1000 PINMUX_DATA(PORT247_SCIFB_TXD_MARK, PORT247_FN3, MSEL4CR_MSEL22_1), \
1001 PINMUX_DATA(TPU3TO1_MARK, PORT247_FN4),
1002 PINMUX_DATA(PORT248_SCIFA5_SCK_MARK, PORT248_FN1, MSEL4CR_MSEL21_0,
1003 MSEL4CR_MSEL20_0), \
1004 PINMUX_DATA(MFG2_OUT1_MARK, PORT248_FN2), \
1005 PINMUX_DATA(PORT248_SCIFB_SCK_MARK, PORT248_FN3, MSEL4CR_MSEL22_1), \
1006 PINMUX_DATA(TPU2TO0_MARK, PORT248_FN4), \
1007 PINMUX_DATA(PORT248_I2C_SCL3_MARK, PORT248_FN5, MSEL2CR_MSEL19_0,
1008 MSEL2CR_MSEL18_0), \
1009 PINMUX_DATA(MSIOF2R_TSCK_MARK, PORT248_FN7, MSEL4CR_MSEL11_1),
1010 PINMUX_DATA(PORT249_IROUT_MARK, PORT249_FN1), \
1011 PINMUX_DATA(MFG4_IN1_MARK, PORT249_FN2), \
1012 PINMUX_DATA(PORT249_I2C_SDA3_MARK, PORT249_FN5, MSEL2CR_MSEL19_0,
1013 MSEL2CR_MSEL18_0), \
1014 PINMUX_DATA(MSIOF2R_TSYNC_MARK, PORT249_FN7, MSEL4CR_MSEL11_1),
1015 PINMUX_DATA(SDHICLK0_MARK, PORT250_FN1),
1016 PINMUX_DATA(SDHICD0_MARK, PORT251_FN1),
1017 PINMUX_DATA(SDHID0_0_MARK, PORT252_FN1),
1018 PINMUX_DATA(SDHID0_1_MARK, PORT253_FN1),
1019 PINMUX_DATA(SDHID0_2_MARK, PORT254_FN1),
1020 PINMUX_DATA(SDHID0_3_MARK, PORT255_FN1),
1021 PINMUX_DATA(SDHICMD0_MARK, PORT256_FN1),
1022 PINMUX_DATA(SDHIWP0_MARK, PORT257_FN1),
1023 PINMUX_DATA(SDHICLK1_MARK, PORT258_FN1),
1024 PINMUX_DATA(SDHID1_0_MARK, PORT259_FN1), \
1025 PINMUX_DATA(TS_SPSYNC2_MARK, PORT259_FN3),
1026 PINMUX_DATA(SDHID1_1_MARK, PORT260_FN1), \
1027 PINMUX_DATA(TS_SDAT2_MARK, PORT260_FN3),
1028 PINMUX_DATA(SDHID1_2_MARK, PORT261_FN1), \
1029 PINMUX_DATA(TS_SDEN2_MARK, PORT261_FN3),
1030 PINMUX_DATA(SDHID1_3_MARK, PORT262_FN1), \
1031 PINMUX_DATA(TS_SCK2_MARK, PORT262_FN3),
1032 PINMUX_DATA(SDHICMD1_MARK, PORT263_FN1),
1033 PINMUX_DATA(SDHICLK2_MARK, PORT264_FN1),
1034 PINMUX_DATA(SDHID2_0_MARK, PORT265_FN1), \
1035 PINMUX_DATA(TS_SPSYNC4_MARK, PORT265_FN3),
1036 PINMUX_DATA(SDHID2_1_MARK, PORT266_FN1), \
1037 PINMUX_DATA(TS_SDAT4_MARK, PORT266_FN3),
1038 PINMUX_DATA(SDHID2_2_MARK, PORT267_FN1), \
1039 PINMUX_DATA(TS_SDEN4_MARK, PORT267_FN3),
1040 PINMUX_DATA(SDHID2_3_MARK, PORT268_FN1), \
1041 PINMUX_DATA(TS_SCK4_MARK, PORT268_FN3),
1042 PINMUX_DATA(SDHICMD2_MARK, PORT269_FN1),
1043 PINMUX_DATA(MMCCLK0_MARK, PORT270_FN1, MSEL4CR_MSEL15_0),
Laurent Pinchart19ac5552013-03-13 18:32:00 +0100[diff] [blame]1044 PINMUX_DATA(MMCD0_0_MARK, PORT271_FN1, MSEL4CR_MSEL15_0),
1045 PINMUX_DATA(MMCD0_1_MARK, PORT272_FN1, MSEL4CR_MSEL15_0),
1046 PINMUX_DATA(MMCD0_2_MARK, PORT273_FN1, MSEL4CR_MSEL15_0),
1047 PINMUX_DATA(MMCD0_3_MARK, PORT274_FN1, MSEL4CR_MSEL15_0),
1048 PINMUX_DATA(MMCD0_4_MARK, PORT275_FN1, MSEL4CR_MSEL15_0),
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]1049 PINMUX_DATA(TS_SPSYNC5_MARK, PORT275_FN3),
Laurent Pinchart19ac5552013-03-13 18:32:00 +0100[diff] [blame]1050 PINMUX_DATA(MMCD0_5_MARK, PORT276_FN1, MSEL4CR_MSEL15_0),
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]1051 PINMUX_DATA(TS_SDAT5_MARK, PORT276_FN3),
Laurent Pinchart19ac5552013-03-13 18:32:00 +0100[diff] [blame]1052 PINMUX_DATA(MMCD0_6_MARK, PORT277_FN1, MSEL4CR_MSEL15_0),
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]1053 PINMUX_DATA(TS_SDEN5_MARK, PORT277_FN3),
Laurent Pinchart19ac5552013-03-13 18:32:00 +0100[diff] [blame]1054 PINMUX_DATA(MMCD0_7_MARK, PORT278_FN1, MSEL4CR_MSEL15_0),
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]1055 PINMUX_DATA(TS_SCK5_MARK, PORT278_FN3),
Laurent Pinchart19ac5552013-03-13 18:32:00 +0100[diff] [blame]1056 PINMUX_DATA(MMCCMD0_MARK, PORT279_FN1, MSEL4CR_MSEL15_0),
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]1057 PINMUX_DATA(RESETOUTS__MARK, PORT281_FN1), \
1058 PINMUX_DATA(EXTAL2OUT_MARK, PORT281_FN2),
1059 PINMUX_DATA(MCP_WAIT__MCP_FRB_MARK, PORT288_FN1),
1060 PINMUX_DATA(MCP_CKO_MARK, PORT289_FN1), \
1061 PINMUX_DATA(MMCCLK1_MARK, PORT289_FN2, MSEL4CR_MSEL15_1),
1062 PINMUX_DATA(MCP_D15_MCP_NAF15_MARK, PORT290_FN1),
1063 PINMUX_DATA(MCP_D14_MCP_NAF14_MARK, PORT291_FN1),
1064 PINMUX_DATA(MCP_D13_MCP_NAF13_MARK, PORT292_FN1),
1065 PINMUX_DATA(MCP_D12_MCP_NAF12_MARK, PORT293_FN1),
1066 PINMUX_DATA(MCP_D11_MCP_NAF11_MARK, PORT294_FN1),
1067 PINMUX_DATA(MCP_D10_MCP_NAF10_MARK, PORT295_FN1),
1068 PINMUX_DATA(MCP_D9_MCP_NAF9_MARK, PORT296_FN1),
1069 PINMUX_DATA(MCP_D8_MCP_NAF8_MARK, PORT297_FN1), \
1070 PINMUX_DATA(MMCCMD1_MARK, PORT297_FN2, MSEL4CR_MSEL15_1),
1071 PINMUX_DATA(MCP_D7_MCP_NAF7_MARK, PORT298_FN1), \
1072 PINMUX_DATA(MMCD1_7_MARK, PORT298_FN2, MSEL4CR_MSEL15_1),
1073
1074 PINMUX_DATA(MCP_D6_MCP_NAF6_MARK, PORT299_FN1), \
1075 PINMUX_DATA(MMCD1_6_MARK, PORT299_FN2, MSEL4CR_MSEL15_1),
1076 PINMUX_DATA(MCP_D5_MCP_NAF5_MARK, PORT300_FN1), \
1077 PINMUX_DATA(MMCD1_5_MARK, PORT300_FN2, MSEL4CR_MSEL15_1),
1078 PINMUX_DATA(MCP_D4_MCP_NAF4_MARK, PORT301_FN1), \
1079 PINMUX_DATA(MMCD1_4_MARK, PORT301_FN2, MSEL4CR_MSEL15_1),
1080 PINMUX_DATA(MCP_D3_MCP_NAF3_MARK, PORT302_FN1), \
1081 PINMUX_DATA(MMCD1_3_MARK, PORT302_FN2, MSEL4CR_MSEL15_1),
1082 PINMUX_DATA(MCP_D2_MCP_NAF2_MARK, PORT303_FN1), \
1083 PINMUX_DATA(MMCD1_2_MARK, PORT303_FN2, MSEL4CR_MSEL15_1),
1084 PINMUX_DATA(MCP_D1_MCP_NAF1_MARK, PORT304_FN1), \
1085 PINMUX_DATA(MMCD1_1_MARK, PORT304_FN2, MSEL4CR_MSEL15_1),
1086 PINMUX_DATA(MCP_D0_MCP_NAF0_MARK, PORT305_FN1), \
1087 PINMUX_DATA(MMCD1_0_MARK, PORT305_FN2, MSEL4CR_MSEL15_1),
1088 PINMUX_DATA(MCP_NBRSTOUT__MARK, PORT306_FN1),
1089 PINMUX_DATA(MCP_WE0__MCP_FWE_MARK, PORT309_FN1), \
1090 PINMUX_DATA(MCP_RDWR_MCP_FWE_MARK, PORT309_FN2),
1091
1092 /* MSEL2 special cases */
1093 PINMUX_DATA(TSIF2_TS_XX1_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_0,
1094 MSEL2CR_MSEL12_0),
1095 PINMUX_DATA(TSIF2_TS_XX2_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_0,
1096 MSEL2CR_MSEL12_1),
1097 PINMUX_DATA(TSIF2_TS_XX3_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_1,
1098 MSEL2CR_MSEL12_0),
1099 PINMUX_DATA(TSIF2_TS_XX4_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_1,
1100 MSEL2CR_MSEL12_1),
1101 PINMUX_DATA(TSIF2_TS_XX5_MARK, MSEL2CR_MSEL14_1, MSEL2CR_MSEL13_0,
1102 MSEL2CR_MSEL12_0),
1103 PINMUX_DATA(TSIF1_TS_XX1_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_0,
1104 MSEL2CR_MSEL9_0),
1105 PINMUX_DATA(TSIF1_TS_XX2_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_0,
1106 MSEL2CR_MSEL9_1),
1107 PINMUX_DATA(TSIF1_TS_XX3_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_1,
1108 MSEL2CR_MSEL9_0),
1109 PINMUX_DATA(TSIF1_TS_XX4_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_1,
1110 MSEL2CR_MSEL9_1),
1111 PINMUX_DATA(TSIF1_TS_XX5_MARK, MSEL2CR_MSEL11_1, MSEL2CR_MSEL10_0,
1112 MSEL2CR_MSEL9_0),
1113 PINMUX_DATA(TSIF0_TS_XX1_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_0,
1114 MSEL2CR_MSEL6_0),
1115 PINMUX_DATA(TSIF0_TS_XX2_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_0,
1116 MSEL2CR_MSEL6_1),
1117 PINMUX_DATA(TSIF0_TS_XX3_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_1,
1118 MSEL2CR_MSEL6_0),
1119 PINMUX_DATA(TSIF0_TS_XX4_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_1,
1120 MSEL2CR_MSEL6_1),
1121 PINMUX_DATA(TSIF0_TS_XX5_MARK, MSEL2CR_MSEL8_1, MSEL2CR_MSEL7_0,
1122 MSEL2CR_MSEL6_0),
1123 PINMUX_DATA(MST1_TS_XX1_MARK, MSEL2CR_MSEL5_0, MSEL2CR_MSEL4_0,
1124 MSEL2CR_MSEL3_0),
1125 PINMUX_DATA(MST1_TS_XX2_MARK, MSEL2CR_MSEL5_0, MSEL2CR_MSEL4_0,
1126 MSEL2CR_MSEL3_1),
1127 PINMUX_DATA(MST1_TS_XX3_MARK, MSEL2CR_MSEL5_0, MSEL2CR_MSEL4_1,
1128 MSEL2CR_MSEL3_0),
1129 PINMUX_DATA(MST1_TS_XX4_MARK, MSEL2CR_MSEL5_0, MSEL2CR_MSEL4_1,
1130 MSEL2CR_MSEL3_1),
1131 PINMUX_DATA(MST1_TS_XX5_MARK, MSEL2CR_MSEL5_1, MSEL2CR_MSEL4_0,
1132 MSEL2CR_MSEL3_0),
1133 PINMUX_DATA(MST0_TS_XX1_MARK, MSEL2CR_MSEL2_0, MSEL2CR_MSEL1_0,
1134 MSEL2CR_MSEL0_0),
1135 PINMUX_DATA(MST0_TS_XX2_MARK, MSEL2CR_MSEL2_0, MSEL2CR_MSEL1_0,
1136 MSEL2CR_MSEL0_1),
1137 PINMUX_DATA(MST0_TS_XX3_MARK, MSEL2CR_MSEL2_0, MSEL2CR_MSEL1_1,
1138 MSEL2CR_MSEL0_0),
1139 PINMUX_DATA(MST0_TS_XX4_MARK, MSEL2CR_MSEL2_0, MSEL2CR_MSEL1_1,
1140 MSEL2CR_MSEL0_1),
1141 PINMUX_DATA(MST0_TS_XX5_MARK, MSEL2CR_MSEL2_1, MSEL2CR_MSEL1_0,
1142 MSEL2CR_MSEL0_0),
1143
1144 /* MSEL3 special cases */
1145 PINMUX_DATA(SDHI0_VCCQ_MC0_ON_MARK, MSEL3CR_MSEL28_1),
1146 PINMUX_DATA(SDHI0_VCCQ_MC0_OFF_MARK, MSEL3CR_MSEL28_0),
1147 PINMUX_DATA(DEBUG_MON_VIO_MARK, MSEL3CR_MSEL15_0),
1148 PINMUX_DATA(DEBUG_MON_LCDD_MARK, MSEL3CR_MSEL15_1),
1149 PINMUX_DATA(LCDC_LCDC0_MARK, MSEL3CR_MSEL6_0),
1150 PINMUX_DATA(LCDC_LCDC1_MARK, MSEL3CR_MSEL6_1),
1151
1152 /* MSEL4 special cases */
1153 PINMUX_DATA(IRQ9_MEM_INT_MARK, MSEL4CR_MSEL29_0),
1154 PINMUX_DATA(IRQ9_MCP_INT_MARK, MSEL4CR_MSEL29_1),
1155 PINMUX_DATA(A11_MARK, MSEL4CR_MSEL13_0, MSEL4CR_MSEL12_0),
1156 PINMUX_DATA(KEYOUT8_MARK, MSEL4CR_MSEL13_0, MSEL4CR_MSEL12_1),
1157 PINMUX_DATA(TPU4TO3_MARK, MSEL4CR_MSEL13_1, MSEL4CR_MSEL12_0),
1158 PINMUX_DATA(RESETA_N_PU_ON_MARK, MSEL4CR_MSEL4_0),
1159 PINMUX_DATA(RESETA_N_PU_OFF_MARK, MSEL4CR_MSEL4_1),
1160 PINMUX_DATA(EDBGREQ_PD_MARK, MSEL4CR_MSEL1_0),
1161 PINMUX_DATA(EDBGREQ_PU_MARK, MSEL4CR_MSEL1_1),
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]1162};
1163
Laurent Pinchartb8238992013-03-13 01:31:23 +0100[diff] [blame]1164#define SH73A0_PIN(pin, cfgs) \
1165 { \
1166 .name = __stringify(PORT##pin), \
1167 .enum_id = PORT##pin##_DATA, \
1168 .configs = cfgs, \
1169 }
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]1170
Laurent Pinchartb8238992013-03-13 01:31:23 +0100[diff] [blame]1171#define __I (SH_PFC_PIN_CFG_INPUT)
1172#define __O (SH_PFC_PIN_CFG_OUTPUT)
1173#define __IO (SH_PFC_PIN_CFG_INPUT | SH_PFC_PIN_CFG_OUTPUT)
1174#define __PD (SH_PFC_PIN_CFG_PULL_DOWN)
1175#define __PU (SH_PFC_PIN_CFG_PULL_UP)
1176#define __PUD (SH_PFC_PIN_CFG_PULL_DOWN | SH_PFC_PIN_CFG_PULL_UP)
1177
1178#define SH73A0_PIN_I_PD(pin) SH73A0_PIN(pin, __I | __PD)
1179#define SH73A0_PIN_I_PU(pin) SH73A0_PIN(pin, __I | __PU)
1180#define SH73A0_PIN_I_PU_PD(pin) SH73A0_PIN(pin, __I | __PUD)
1181#define SH73A0_PIN_IO(pin) SH73A0_PIN(pin, __IO)
1182#define SH73A0_PIN_IO_PD(pin) SH73A0_PIN(pin, __IO | __PD)
1183#define SH73A0_PIN_IO_PU(pin) SH73A0_PIN(pin, __IO | __PU)
1184#define SH73A0_PIN_IO_PU_PD(pin) SH73A0_PIN(pin, __IO | __PUD)
1185#define SH73A0_PIN_O(pin) SH73A0_PIN(pin, __O)
1186
Laurent Pincharta3db40a62013-01-02 14:53:37 +0100[diff] [blame]1187static struct sh_pfc_pin pinmux_pins[] = {
Laurent Pinchartb8238992013-03-13 01:31:23 +0100[diff] [blame]1188 /* Table 25-1 (I/O and Pull U/D) */
1189 SH73A0_PIN_I_PD(0),
1190 SH73A0_PIN_I_PU(1),
1191 SH73A0_PIN_I_PU(2),
1192 SH73A0_PIN_I_PU(3),
1193 SH73A0_PIN_I_PU(4),
1194 SH73A0_PIN_I_PU(5),
1195 SH73A0_PIN_I_PU(6),
1196 SH73A0_PIN_I_PU(7),
1197 SH73A0_PIN_I_PU(8),
1198 SH73A0_PIN_I_PD(9),
1199 SH73A0_PIN_I_PD(10),
1200 SH73A0_PIN_I_PU_PD(11),
1201 SH73A0_PIN_IO_PU_PD(12),
1202 SH73A0_PIN_IO_PU_PD(13),
1203 SH73A0_PIN_IO_PU_PD(14),
1204 SH73A0_PIN_IO_PU_PD(15),
1205 SH73A0_PIN_IO_PD(16),
1206 SH73A0_PIN_IO_PD(17),
1207 SH73A0_PIN_IO_PU(18),
1208 SH73A0_PIN_IO_PU(19),
1209 SH73A0_PIN_O(20),
1210 SH73A0_PIN_O(21),
1211 SH73A0_PIN_O(22),
1212 SH73A0_PIN_O(23),
1213 SH73A0_PIN_O(24),
1214 SH73A0_PIN_I_PD(25),
1215 SH73A0_PIN_I_PD(26),
1216 SH73A0_PIN_IO_PU(27),
1217 SH73A0_PIN_IO_PU(28),
1218 SH73A0_PIN_IO_PD(29),
1219 SH73A0_PIN_IO_PD(30),
1220 SH73A0_PIN_IO_PU(31),
1221 SH73A0_PIN_IO_PD(32),
1222 SH73A0_PIN_I_PU_PD(33),
1223 SH73A0_PIN_IO_PD(34),
1224 SH73A0_PIN_I_PU_PD(35),
1225 SH73A0_PIN_IO_PD(36),
1226 SH73A0_PIN_IO(37),
1227 SH73A0_PIN_O(38),
1228 SH73A0_PIN_I_PU(39),
1229 SH73A0_PIN_I_PU_PD(40),
1230 SH73A0_PIN_O(41),
1231 SH73A0_PIN_IO_PD(42),
1232 SH73A0_PIN_IO_PU_PD(43),
1233 SH73A0_PIN_IO_PU_PD(44),
1234 SH73A0_PIN_IO_PD(45),
1235 SH73A0_PIN_IO_PD(46),
1236 SH73A0_PIN_IO_PD(47),
1237 SH73A0_PIN_I_PD(48),
1238 SH73A0_PIN_IO_PU_PD(49),
1239 SH73A0_PIN_IO_PD(50),
1240 SH73A0_PIN_IO_PD(51),
1241 SH73A0_PIN_O(52),
1242 SH73A0_PIN_IO_PU_PD(53),
1243 SH73A0_PIN_IO_PU_PD(54),
1244 SH73A0_PIN_IO_PD(55),
1245 SH73A0_PIN_I_PU_PD(56),
1246 SH73A0_PIN_IO(57),
1247 SH73A0_PIN_IO(58),
1248 SH73A0_PIN_IO(59),
1249 SH73A0_PIN_IO(60),
1250 SH73A0_PIN_IO(61),
1251 SH73A0_PIN_IO_PD(62),
1252 SH73A0_PIN_IO_PD(63),
1253 SH73A0_PIN_IO_PU_PD(64),
1254 SH73A0_PIN_IO_PD(65),
1255 SH73A0_PIN_IO_PU_PD(66),
1256 SH73A0_PIN_IO_PU_PD(67),
1257 SH73A0_PIN_IO_PU_PD(68),
1258 SH73A0_PIN_IO_PU_PD(69),
1259 SH73A0_PIN_IO_PU_PD(70),
1260 SH73A0_PIN_IO_PU_PD(71),
1261 SH73A0_PIN_IO_PU_PD(72),
1262 SH73A0_PIN_I_PU_PD(73),
1263 SH73A0_PIN_IO_PU(74),
1264 SH73A0_PIN_IO_PU(75),
1265 SH73A0_PIN_IO_PU(76),
1266 SH73A0_PIN_IO_PU(77),
1267 SH73A0_PIN_IO_PU(78),
1268 SH73A0_PIN_IO_PU(79),
1269 SH73A0_PIN_IO_PU(80),
1270 SH73A0_PIN_IO_PU(81),
1271 SH73A0_PIN_IO_PU(82),
1272 SH73A0_PIN_IO_PU(83),
1273 SH73A0_PIN_IO_PU(84),
1274 SH73A0_PIN_IO_PU(85),
1275 SH73A0_PIN_IO_PU(86),
1276 SH73A0_PIN_IO_PU(87),
1277 SH73A0_PIN_IO_PU(88),
1278 SH73A0_PIN_IO_PU(89),
1279 SH73A0_PIN_O(90),
1280 SH73A0_PIN_IO_PU(91),
1281 SH73A0_PIN_O(92),
1282 SH73A0_PIN_IO_PU(93),
1283 SH73A0_PIN_O(94),
1284 SH73A0_PIN_I_PU_PD(95),
1285 SH73A0_PIN_IO(96),
1286 SH73A0_PIN_IO(97),
1287 SH73A0_PIN_IO(98),
1288 SH73A0_PIN_I_PU(99),
1289 SH73A0_PIN_O(100),
1290 SH73A0_PIN_O(101),
1291 SH73A0_PIN_I_PU(102),
1292 SH73A0_PIN_IO_PD(103),
1293 SH73A0_PIN_I_PU_PD(104),
1294 SH73A0_PIN_I_PD(105),
1295 SH73A0_PIN_I_PD(106),
1296 SH73A0_PIN_I_PU_PD(107),
1297 SH73A0_PIN_I_PU_PD(108),
1298 SH73A0_PIN_IO_PD(109),
1299 SH73A0_PIN_IO_PD(110),
1300 SH73A0_PIN_IO_PU_PD(111),
1301 SH73A0_PIN_IO_PU_PD(112),
1302 SH73A0_PIN_IO_PU_PD(113),
1303 SH73A0_PIN_IO_PD(114),
1304 SH73A0_PIN_IO_PU(115),
1305 SH73A0_PIN_IO_PU(116),
1306 SH73A0_PIN_IO_PU_PD(117),
1307 SH73A0_PIN_IO_PU_PD(118),
1308 SH73A0_PIN_IO_PD(128),
1309 SH73A0_PIN_IO_PD(129),
1310 SH73A0_PIN_IO_PU_PD(130),
1311 SH73A0_PIN_IO_PD(131),
1312 SH73A0_PIN_IO_PD(132),
1313 SH73A0_PIN_IO_PD(133),
1314 SH73A0_PIN_IO_PU_PD(134),
1315 SH73A0_PIN_IO_PU_PD(135),
1316 SH73A0_PIN_IO_PU_PD(136),
1317 SH73A0_PIN_IO_PU_PD(137),
1318 SH73A0_PIN_IO_PD(138),
1319 SH73A0_PIN_IO_PD(139),
1320 SH73A0_PIN_IO_PD(140),
1321 SH73A0_PIN_IO_PD(141),
1322 SH73A0_PIN_IO_PD(142),
1323 SH73A0_PIN_IO_PD(143),
1324 SH73A0_PIN_IO_PU_PD(144),
1325 SH73A0_PIN_IO_PD(145),
1326 SH73A0_PIN_IO_PU_PD(146),
1327 SH73A0_PIN_IO_PU_PD(147),
1328 SH73A0_PIN_IO_PU_PD(148),
1329 SH73A0_PIN_IO_PU_PD(149),
1330 SH73A0_PIN_I_PU_PD(150),
1331 SH73A0_PIN_IO_PU_PD(151),
1332 SH73A0_PIN_IO_PU_PD(152),
1333 SH73A0_PIN_IO_PD(153),
1334 SH73A0_PIN_IO_PD(154),
1335 SH73A0_PIN_I_PU_PD(155),
1336 SH73A0_PIN_IO_PU_PD(156),
1337 SH73A0_PIN_I_PD(157),
1338 SH73A0_PIN_IO_PD(158),
1339 SH73A0_PIN_IO_PU_PD(159),
1340 SH73A0_PIN_IO_PU_PD(160),
1341 SH73A0_PIN_I_PU_PD(161),
1342 SH73A0_PIN_I_PU_PD(162),
1343 SH73A0_PIN_IO_PU_PD(163),
1344 SH73A0_PIN_I_PU_PD(164),
1345 SH73A0_PIN_IO_PD(192),
1346 SH73A0_PIN_IO_PU_PD(193),
1347 SH73A0_PIN_IO_PD(194),
1348 SH73A0_PIN_IO_PU_PD(195),
1349 SH73A0_PIN_IO_PD(196),
1350 SH73A0_PIN_IO_PD(197),
1351 SH73A0_PIN_IO_PD(198),
1352 SH73A0_PIN_IO_PD(199),
1353 SH73A0_PIN_IO_PU_PD(200),
1354 SH73A0_PIN_IO_PU_PD(201),
1355 SH73A0_PIN_IO_PU_PD(202),
1356 SH73A0_PIN_IO_PU_PD(203),
1357 SH73A0_PIN_IO_PU_PD(204),
1358 SH73A0_PIN_IO_PU_PD(205),
1359 SH73A0_PIN_IO_PU_PD(206),
1360 SH73A0_PIN_IO_PD(207),
1361 SH73A0_PIN_IO_PD(208),
1362 SH73A0_PIN_IO_PD(209),
1363 SH73A0_PIN_IO_PD(210),
1364 SH73A0_PIN_IO_PD(211),
1365 SH73A0_PIN_IO_PD(212),
1366 SH73A0_PIN_IO_PD(213),
1367 SH73A0_PIN_IO_PU_PD(214),
1368 SH73A0_PIN_IO_PU_PD(215),
1369 SH73A0_PIN_IO_PD(216),
1370 SH73A0_PIN_IO_PD(217),
1371 SH73A0_PIN_O(218),
1372 SH73A0_PIN_IO_PD(219),
1373 SH73A0_PIN_IO_PD(220),
1374 SH73A0_PIN_IO_PU_PD(221),
1375 SH73A0_PIN_IO_PU_PD(222),
1376 SH73A0_PIN_I_PU_PD(223),
1377 SH73A0_PIN_I_PU_PD(224),
1378 SH73A0_PIN_IO_PU_PD(225),
1379 SH73A0_PIN_O(226),
1380 SH73A0_PIN_IO_PU_PD(227),
1381 SH73A0_PIN_I_PU_PD(228),
1382 SH73A0_PIN_I_PD(229),
1383 SH73A0_PIN_IO(230),
1384 SH73A0_PIN_IO_PU_PD(231),
1385 SH73A0_PIN_IO_PU_PD(232),
1386 SH73A0_PIN_I_PU_PD(233),
1387 SH73A0_PIN_IO_PU_PD(234),
1388 SH73A0_PIN_IO_PU_PD(235),
1389 SH73A0_PIN_IO_PU_PD(236),
1390 SH73A0_PIN_IO_PD(237),
1391 SH73A0_PIN_IO_PU_PD(238),
1392 SH73A0_PIN_IO_PU_PD(239),
1393 SH73A0_PIN_IO_PU_PD(240),
1394 SH73A0_PIN_O(241),
1395 SH73A0_PIN_I_PD(242),
1396 SH73A0_PIN_IO_PU_PD(243),
1397 SH73A0_PIN_IO_PU_PD(244),
1398 SH73A0_PIN_IO_PU_PD(245),
1399 SH73A0_PIN_IO_PU_PD(246),
1400 SH73A0_PIN_IO_PU_PD(247),
1401 SH73A0_PIN_IO_PU_PD(248),
1402 SH73A0_PIN_IO_PU_PD(249),
1403 SH73A0_PIN_IO_PU_PD(250),
1404 SH73A0_PIN_IO_PU_PD(251),
1405 SH73A0_PIN_IO_PU_PD(252),
1406 SH73A0_PIN_IO_PU_PD(253),
1407 SH73A0_PIN_IO_PU_PD(254),
1408 SH73A0_PIN_IO_PU_PD(255),
1409 SH73A0_PIN_IO_PU_PD(256),
1410 SH73A0_PIN_IO_PU_PD(257),
1411 SH73A0_PIN_IO_PU_PD(258),
1412 SH73A0_PIN_IO_PU_PD(259),
1413 SH73A0_PIN_IO_PU_PD(260),
1414 SH73A0_PIN_IO_PU_PD(261),
1415 SH73A0_PIN_IO_PU_PD(262),
1416 SH73A0_PIN_IO_PU_PD(263),
1417 SH73A0_PIN_IO_PU_PD(264),
1418 SH73A0_PIN_IO_PU_PD(265),
1419 SH73A0_PIN_IO_PU_PD(266),
1420 SH73A0_PIN_IO_PU_PD(267),
1421 SH73A0_PIN_IO_PU_PD(268),
1422 SH73A0_PIN_IO_PU_PD(269),
1423 SH73A0_PIN_IO_PU_PD(270),
1424 SH73A0_PIN_IO_PU_PD(271),
1425 SH73A0_PIN_IO_PU_PD(272),
1426 SH73A0_PIN_IO_PU_PD(273),
1427 SH73A0_PIN_IO_PU_PD(274),
1428 SH73A0_PIN_IO_PU_PD(275),
1429 SH73A0_PIN_IO_PU_PD(276),
1430 SH73A0_PIN_IO_PU_PD(277),
1431 SH73A0_PIN_IO_PU_PD(278),
1432 SH73A0_PIN_IO_PU_PD(279),
1433 SH73A0_PIN_IO_PU_PD(280),
1434 SH73A0_PIN_O(281),
1435 SH73A0_PIN_O(282),
1436 SH73A0_PIN_I_PU(288),
1437 SH73A0_PIN_IO_PU_PD(289),
1438 SH73A0_PIN_IO_PU_PD(290),
1439 SH73A0_PIN_IO_PU_PD(291),
1440 SH73A0_PIN_IO_PU_PD(292),
1441 SH73A0_PIN_IO_PU_PD(293),
1442 SH73A0_PIN_IO_PU_PD(294),
1443 SH73A0_PIN_IO_PU_PD(295),
1444 SH73A0_PIN_IO_PU_PD(296),
1445 SH73A0_PIN_IO_PU_PD(297),
1446 SH73A0_PIN_IO_PU_PD(298),
1447 SH73A0_PIN_IO_PU_PD(299),
1448 SH73A0_PIN_IO_PU_PD(300),
1449 SH73A0_PIN_IO_PU_PD(301),
1450 SH73A0_PIN_IO_PU_PD(302),
1451 SH73A0_PIN_IO_PU_PD(303),
1452 SH73A0_PIN_IO_PU_PD(304),
1453 SH73A0_PIN_IO_PU_PD(305),
1454 SH73A0_PIN_O(306),
1455 SH73A0_PIN_O(307),
1456 SH73A0_PIN_I_PU(308),
1457 SH73A0_PIN_O(309),
Laurent Pincharta373ed02012-11-29 13:24:07 +0100[diff] [blame]1458};
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]1459
Laurent Pinchartcd3c1be2013-02-16 18:47:05 +0100[diff] [blame]1460static const struct pinmux_range pinmux_ranges[] = {
Guennadi Liakhovetskib58e5fa2013-02-12 16:50:02 +0100[diff] [blame]1461 {.begin = 0, .end = 118,},
1462 {.begin = 128, .end = 164,},
1463 {.begin = 192, .end = 282,},
1464 {.begin = 288, .end = 309,},
1465};
1466
Laurent Pinchartd6bab7b2013-03-12 01:55:08 +0100[diff] [blame]1467/* Pin numbers for pins without a corresponding GPIO port number are computed
1468 * from the row and column numbers with a 1000 offset to avoid collisions with
1469 * GPIO port numbers.
1470 */
1471#define PIN_NUMBER(row, col) (1000+((row)-1)*34+(col)-1)
1472
Laurent Pincharte24c62a2013-03-12 01:55:08 +0100[diff] [blame]1473/* - BSC -------------------------------------------------------------------- */
1474static const unsigned int bsc_data_0_7_pins[] = {
1475 /* D[0:7] */
1476 74, 75, 76, 77, 78, 79, 80, 81,
1477};
1478static const unsigned int bsc_data_0_7_mux[] = {
1479 D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
1480 D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
1481};
1482static const unsigned int bsc_data_8_15_pins[] = {
1483 /* D[8:15] */
1484 82, 83, 84, 85, 86, 87, 88, 89,
1485};
1486static const unsigned int bsc_data_8_15_mux[] = {
1487 D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK,
1488 D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, D15_NAF15_MARK,
1489};
1490static const unsigned int bsc_cs4_pins[] = {
1491 /* CS */
1492 90,
1493};
1494static const unsigned int bsc_cs4_mux[] = {
1495 CS4__MARK,
1496};
1497static const unsigned int bsc_cs5_a_pins[] = {
1498 /* CS */
1499 91,
1500};
1501static const unsigned int bsc_cs5_a_mux[] = {
1502 CS5A__MARK,
1503};
1504static const unsigned int bsc_cs5_b_pins[] = {
1505 /* CS */
1506 92,
1507};
1508static const unsigned int bsc_cs5_b_mux[] = {
1509 CS5B__MARK,
1510};
1511static const unsigned int bsc_cs6_a_pins[] = {
1512 /* CS */
1513 94,
1514};
1515static const unsigned int bsc_cs6_a_mux[] = {
1516 CS6A__MARK,
1517};
1518static const unsigned int bsc_cs6_b_pins[] = {
1519 /* CS */
1520 93,
1521};
1522static const unsigned int bsc_cs6_b_mux[] = {
1523 CS6B__MARK,
1524};
1525static const unsigned int bsc_rd_pins[] = {
1526 /* RD */
1527 96,
1528};
1529static const unsigned int bsc_rd_mux[] = {
1530 RD__FSC_MARK,
1531};
1532static const unsigned int bsc_rdwr_0_pins[] = {
1533 /* RDWR */
1534 91,
1535};
1536static const unsigned int bsc_rdwr_0_mux[] = {
1537 PORT91_RDWR_MARK,
1538};
1539static const unsigned int bsc_rdwr_1_pins[] = {
1540 /* RDWR */
1541 97,
1542};
1543static const unsigned int bsc_rdwr_1_mux[] = {
1544 RDWR_FWE_MARK,
1545};
1546static const unsigned int bsc_rdwr_2_pins[] = {
1547 /* RDWR */
1548 149,
1549};
1550static const unsigned int bsc_rdwr_2_mux[] = {
1551 PORT149_RDWR_MARK,
1552};
1553static const unsigned int bsc_we0_pins[] = {
1554 /* WE0 */
1555 97,
1556};
1557static const unsigned int bsc_we0_mux[] = {
1558 WE0__FWE_MARK,
1559};
1560static const unsigned int bsc_we1_pins[] = {
1561 /* WE1 */
1562 98,
1563};
1564static const unsigned int bsc_we1_mux[] = {
1565 WE1__MARK,
1566};
Laurent Pinchart2ecd4152013-01-03 13:07:05 +0100[diff] [blame]1567/* - FSIA ------------------------------------------------------------------- */
1568static const unsigned int fsia_mclk_in_pins[] = {
1569 /* CK */
1570 49,
1571};
1572static const unsigned int fsia_mclk_in_mux[] = {
1573 FSIACK_MARK,
1574};
1575static const unsigned int fsia_mclk_out_pins[] = {
1576 /* OMC */
1577 49,
1578};
1579static const unsigned int fsia_mclk_out_mux[] = {
1580 FSIAOMC_MARK,
1581};
1582static const unsigned int fsia_sclk_in_pins[] = {
1583 /* ILR, IBT */
1584 50, 51,
1585};
1586static const unsigned int fsia_sclk_in_mux[] = {
1587 FSIAILR_MARK, FSIAIBT_MARK,
1588};
1589static const unsigned int fsia_sclk_out_pins[] = {
1590 /* OLR, OBT */
1591 50, 51,
1592};
1593static const unsigned int fsia_sclk_out_mux[] = {
1594 FSIAOLR_MARK, FSIAOBT_MARK,
1595};
1596static const unsigned int fsia_data_in_pins[] = {
1597 /* ISLD */
1598 55,
1599};
1600static const unsigned int fsia_data_in_mux[] = {
1601 FSIAISLD_MARK,
1602};
1603static const unsigned int fsia_data_out_pins[] = {
1604 /* OSLD */
1605 52,
1606};
1607static const unsigned int fsia_data_out_mux[] = {
1608 FSIAOSLD_MARK,
1609};
1610static const unsigned int fsia_spdif_pins[] = {
1611 /* SPDIF */
1612 53,
1613};
1614static const unsigned int fsia_spdif_mux[] = {
1615 FSIASPDIF_MARK,
1616};
1617/* - FSIB ------------------------------------------------------------------- */
1618static const unsigned int fsib_mclk_in_pins[] = {
1619 /* CK */
1620 54,
1621};
1622static const unsigned int fsib_mclk_in_mux[] = {
1623 FSIBCK_MARK,
1624};
1625static const unsigned int fsib_mclk_out_pins[] = {
1626 /* OMC */
1627 54,
1628};
1629static const unsigned int fsib_mclk_out_mux[] = {
1630 FSIBOMC_MARK,
1631};
1632static const unsigned int fsib_sclk_in_pins[] = {
1633 /* ILR, IBT */
1634 37, 36,
1635};
1636static const unsigned int fsib_sclk_in_mux[] = {
1637 FSIBILR_MARK, FSIBIBT_MARK,
1638};
1639static const unsigned int fsib_sclk_out_pins[] = {
1640 /* OLR, OBT */
1641 37, 36,
1642};
1643static const unsigned int fsib_sclk_out_mux[] = {
1644 FSIBOLR_MARK, FSIBOBT_MARK,
1645};
1646static const unsigned int fsib_data_in_pins[] = {
1647 /* ISLD */
1648 39,
1649};
1650static const unsigned int fsib_data_in_mux[] = {
1651 FSIBISLD_MARK,
1652};
1653static const unsigned int fsib_data_out_pins[] = {
1654 /* OSLD */
1655 38,
1656};
1657static const unsigned int fsib_data_out_mux[] = {
1658 FSIBOSLD_MARK,
1659};
1660static const unsigned int fsib_spdif_pins[] = {
1661 /* SPDIF */
1662 53,
1663};
1664static const unsigned int fsib_spdif_mux[] = {
1665 FSIBSPDIF_MARK,
1666};
1667/* - FSIC ------------------------------------------------------------------- */
1668static const unsigned int fsic_mclk_in_pins[] = {
1669 /* CK */
1670 54,
1671};
1672static const unsigned int fsic_mclk_in_mux[] = {
1673 FSICCK_MARK,
1674};
1675static const unsigned int fsic_mclk_out_pins[] = {
1676 /* OMC */
1677 54,
1678};
1679static const unsigned int fsic_mclk_out_mux[] = {
1680 FSICOMC_MARK,
1681};
1682static const unsigned int fsic_sclk_in_pins[] = {
1683 /* ILR, IBT */
1684 46, 45,
1685};
1686static const unsigned int fsic_sclk_in_mux[] = {
1687 FSICILR_MARK, FSICIBT_MARK,
1688};
1689static const unsigned int fsic_sclk_out_pins[] = {
1690 /* OLR, OBT */
1691 46, 45,
1692};
1693static const unsigned int fsic_sclk_out_mux[] = {
1694 FSICOLR_MARK, FSICOBT_MARK,
1695};
1696static const unsigned int fsic_data_in_pins[] = {
1697 /* ISLD */
1698 48,
1699};
1700static const unsigned int fsic_data_in_mux[] = {
1701 FSICISLD_MARK,
1702};
1703static const unsigned int fsic_data_out_pins[] = {
1704 /* OSLD, OSLDT1, OSLDT2, OSLDT3 */
1705 47, 44, 42, 16,
1706};
1707static const unsigned int fsic_data_out_mux[] = {
1708 FSICOSLD_MARK, FSICOSLDT1_MARK, FSICOSLDT2_MARK, FSICOSLDT3_MARK,
1709};
1710static const unsigned int fsic_spdif_0_pins[] = {
1711 /* SPDIF */
1712 53,
1713};
1714static const unsigned int fsic_spdif_0_mux[] = {
1715 PORT53_FSICSPDIF_MARK,
1716};
1717static const unsigned int fsic_spdif_1_pins[] = {
1718 /* SPDIF */
1719 47,
1720};
1721static const unsigned int fsic_spdif_1_mux[] = {
1722 PORT47_FSICSPDIF_MARK,
1723};
1724/* - FSID ------------------------------------------------------------------- */
1725static const unsigned int fsid_sclk_in_pins[] = {
1726 /* ILR, IBT */
1727 46, 45,
1728};
1729static const unsigned int fsid_sclk_in_mux[] = {
1730 FSIDILR_MARK, FSIDIBT_MARK,
1731};
1732static const unsigned int fsid_sclk_out_pins[] = {
1733 /* OLR, OBT */
1734 46, 45,
1735};
1736static const unsigned int fsid_sclk_out_mux[] = {
1737 FSIDOLR_MARK, FSIDOBT_MARK,
1738};
1739static const unsigned int fsid_data_in_pins[] = {
1740 /* ISLD */
1741 48,
1742};
1743static const unsigned int fsid_data_in_mux[] = {
1744 FSIDISLD_MARK,
1745};
Laurent Pinchartec3a57b2013-01-03 13:07:05 +0100[diff] [blame]1746/* - I2C2 ------------------------------------------------------------------- */
1747static const unsigned int i2c2_0_pins[] = {
1748 /* SCL, SDA */
1749 237, 236,
1750};
1751static const unsigned int i2c2_0_mux[] = {
1752 PORT237_I2C_SCL2_MARK, PORT236_I2C_SDA2_MARK,
1753};
1754static const unsigned int i2c2_1_pins[] = {
1755 /* SCL, SDA */
1756 27, 28,
1757};
1758static const unsigned int i2c2_1_mux[] = {
1759 PORT27_I2C_SCL2_MARK, PORT28_I2C_SDA2_MARK,
1760};
1761static const unsigned int i2c2_2_pins[] = {
1762 /* SCL, SDA */
1763 115, 116,
1764};
1765static const unsigned int i2c2_2_mux[] = {
1766 PORT115_I2C_SCL2_MARK, PORT116_I2C_SDA2_MARK,
1767};
1768/* - I2C3 ------------------------------------------------------------------- */
1769static const unsigned int i2c3_0_pins[] = {
1770 /* SCL, SDA */
1771 248, 249,
1772};
1773static const unsigned int i2c3_0_mux[] = {
1774 PORT248_I2C_SCL3_MARK, PORT249_I2C_SDA3_MARK,
1775};
1776static const unsigned int i2c3_1_pins[] = {
1777 /* SCL, SDA */
1778 27, 28,
1779};
1780static const unsigned int i2c3_1_mux[] = {
1781 PORT27_I2C_SCL3_MARK, PORT28_I2C_SDA3_MARK,
1782};
1783static const unsigned int i2c3_2_pins[] = {
1784 /* SCL, SDA */
1785 115, 116,
1786};
1787static const unsigned int i2c3_2_mux[] = {
1788 PORT115_I2C_SCL3_MARK, PORT116_I2C_SDA3_MARK,
1789};
Laurent Pinchart512b1562013-03-12 01:55:08 +0100[diff] [blame]1790/* - IrDA ------------------------------------------------------------------- */
1791static const unsigned int irda_0_pins[] = {
1792 /* OUT, IN, FIRSEL */
1793 241, 242, 243,
1794};
1795static const unsigned int irda_0_mux[] = {
1796 PORT241_IRDA_OUT_MARK, PORT242_IRDA_IN_MARK, PORT243_IRDA_FIRSEL_MARK,
1797};
1798static const unsigned int irda_1_pins[] = {
1799 /* OUT, IN, FIRSEL */
1800 49, 53, 54,
1801};
1802static const unsigned int irda_1_mux[] = {
1803 PORT49_IRDA_OUT_MARK, PORT53_IRDA_IN_MARK, PORT54_IRDA_FIRSEL_MARK,
1804};
Laurent Pinchartd6bab7b2013-03-12 01:55:08 +0100[diff] [blame]1805/* - KEYSC ------------------------------------------------------------------ */
1806static const unsigned int keysc_in5_pins[] = {
1807 /* KEYIN[0:4] */
1808 66, 67, 68, 69, 70,
1809};
1810static const unsigned int keysc_in5_mux[] = {
1811 KEYIN0_MARK, KEYIN1_MARK, KEYIN2_MARK, KEYIN3_MARK,
1812 KEYIN4_MARK,
1813};
1814static const unsigned int keysc_in6_pins[] = {
1815 /* KEYIN[0:5] */
1816 66, 67, 68, 69, 70, 71,
1817};
1818static const unsigned int keysc_in6_mux[] = {
1819 KEYIN0_MARK, KEYIN1_MARK, KEYIN2_MARK, KEYIN3_MARK,
1820 KEYIN4_MARK, KEYIN5_MARK,
1821};
1822static const unsigned int keysc_in7_pins[] = {
1823 /* KEYIN[0:6] */
1824 66, 67, 68, 69, 70, 71, 72,
1825};
1826static const unsigned int keysc_in7_mux[] = {
1827 KEYIN0_MARK, KEYIN1_MARK, KEYIN2_MARK, KEYIN3_MARK,
1828 KEYIN4_MARK, KEYIN5_MARK, KEYIN6_MARK,
1829};
1830static const unsigned int keysc_in8_pins[] = {
1831 /* KEYIN[0:7] */
1832 66, 67, 68, 69, 70, 71, 72, 73,
1833};
1834static const unsigned int keysc_in8_mux[] = {
1835 KEYIN0_MARK, KEYIN1_MARK, KEYIN2_MARK, KEYIN3_MARK,
1836 KEYIN4_MARK, KEYIN5_MARK, KEYIN6_MARK, KEYIN7_MARK,
1837};
1838static const unsigned int keysc_out04_pins[] = {
1839 /* KEYOUT[0:4] */
1840 65, 64, 63, 62, 61,
1841};
1842static const unsigned int keysc_out04_mux[] = {
1843 KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK, KEYOUT4_MARK,
1844};
1845static const unsigned int keysc_out5_pins[] = {
1846 /* KEYOUT5 */
1847 60,
1848};
1849static const unsigned int keysc_out5_mux[] = {
1850 KEYOUT5_MARK,
1851};
1852static const unsigned int keysc_out6_0_pins[] = {
1853 /* KEYOUT6 */
1854 59,
1855};
1856static const unsigned int keysc_out6_0_mux[] = {
1857 PORT59_KEYOUT6_MARK,
1858};
1859static const unsigned int keysc_out6_1_pins[] = {
1860 /* KEYOUT6 */
1861 131,
1862};
1863static const unsigned int keysc_out6_1_mux[] = {
1864 PORT131_KEYOUT6_MARK,
1865};
1866static const unsigned int keysc_out6_2_pins[] = {
1867 /* KEYOUT6 */
1868 143,
1869};
1870static const unsigned int keysc_out6_2_mux[] = {
1871 PORT143_KEYOUT6_MARK,
1872};
1873static const unsigned int keysc_out7_0_pins[] = {
1874 /* KEYOUT7 */
1875 58,
1876};
1877static const unsigned int keysc_out7_0_mux[] = {
1878 PORT58_KEYOUT7_MARK,
1879};
1880static const unsigned int keysc_out7_1_pins[] = {
1881 /* KEYOUT7 */
1882 132,
1883};
1884static const unsigned int keysc_out7_1_mux[] = {
1885 PORT132_KEYOUT7_MARK,
1886};
1887static const unsigned int keysc_out7_2_pins[] = {
1888 /* KEYOUT7 */
1889 144,
1890};
1891static const unsigned int keysc_out7_2_mux[] = {
1892 PORT144_KEYOUT7_MARK,
1893};
1894static const unsigned int keysc_out8_0_pins[] = {
1895 /* KEYOUT8 */
1896 PIN_NUMBER(6, 26),
1897};
1898static const unsigned int keysc_out8_0_mux[] = {
1899 KEYOUT8_MARK,
1900};
1901static const unsigned int keysc_out8_1_pins[] = {
1902 /* KEYOUT8 */
1903 136,
1904};
1905static const unsigned int keysc_out8_1_mux[] = {
1906 PORT136_KEYOUT8_MARK,
1907};
1908static const unsigned int keysc_out8_2_pins[] = {
1909 /* KEYOUT8 */
1910 138,
1911};
1912static const unsigned int keysc_out8_2_mux[] = {
1913 PORT138_KEYOUT8_MARK,
1914};
1915static const unsigned int keysc_out9_0_pins[] = {
1916 /* KEYOUT9 */
1917 137,
1918};
1919static const unsigned int keysc_out9_0_mux[] = {
1920 PORT137_KEYOUT9_MARK,
1921};
1922static const unsigned int keysc_out9_1_pins[] = {
1923 /* KEYOUT9 */
1924 139,
1925};
1926static const unsigned int keysc_out9_1_mux[] = {
1927 PORT139_KEYOUT9_MARK,
1928};
1929static const unsigned int keysc_out9_2_pins[] = {
1930 /* KEYOUT9 */
1931 149,
1932};
1933static const unsigned int keysc_out9_2_mux[] = {
1934 PORT149_KEYOUT9_MARK,
1935};
1936static const unsigned int keysc_out10_0_pins[] = {
1937 /* KEYOUT10 */
1938 132,
1939};
1940static const unsigned int keysc_out10_0_mux[] = {
1941 PORT132_KEYOUT10_MARK,
1942};
1943static const unsigned int keysc_out10_1_pins[] = {
1944 /* KEYOUT10 */
1945 142,
1946};
1947static const unsigned int keysc_out10_1_mux[] = {
1948 PORT142_KEYOUT10_MARK,
1949};
1950static const unsigned int keysc_out11_0_pins[] = {
1951 /* KEYOUT11 */
1952 131,
1953};
1954static const unsigned int keysc_out11_0_mux[] = {
1955 PORT131_KEYOUT11_MARK,
1956};
1957static const unsigned int keysc_out11_1_pins[] = {
1958 /* KEYOUT11 */
1959 143,
1960};
1961static const unsigned int keysc_out11_1_mux[] = {
1962 PORT143_KEYOUT11_MARK,
1963};
Laurent Pinchartdf68a282013-01-03 13:07:05 +0100[diff] [blame]1964/* - LCD -------------------------------------------------------------------- */
1965static const unsigned int lcd_data8_pins[] = {
1966 /* D[0:7] */
1967 192, 193, 194, 195, 196, 197, 198, 199,
1968};
1969static const unsigned int lcd_data8_mux[] = {
1970 LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
1971 LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
1972};
1973static const unsigned int lcd_data9_pins[] = {
1974 /* D[0:8] */
1975 192, 193, 194, 195, 196, 197, 198, 199,
1976 200,
1977};
1978static const unsigned int lcd_data9_mux[] = {
1979 LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
1980 LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
1981 LCDD8_MARK,
1982};
1983static const unsigned int lcd_data12_pins[] = {
1984 /* D[0:11] */
1985 192, 193, 194, 195, 196, 197, 198, 199,
1986 200, 201, 202, 203,
1987};
1988static const unsigned int lcd_data12_mux[] = {
1989 LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
1990 LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
1991 LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK,
1992};
1993static const unsigned int lcd_data16_pins[] = {
1994 /* D[0:15] */
1995 192, 193, 194, 195, 196, 197, 198, 199,
1996 200, 201, 202, 203, 204, 205, 206, 207,
1997};
1998static const unsigned int lcd_data16_mux[] = {
1999 LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
2000 LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
2001 LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK,
2002 LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK,
2003};
2004static const unsigned int lcd_data18_pins[] = {
2005 /* D[0:17] */
2006 192, 193, 194, 195, 196, 197, 198, 199,
2007 200, 201, 202, 203, 204, 205, 206, 207,
2008 208, 209,
2009};
2010static const unsigned int lcd_data18_mux[] = {
2011 LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
2012 LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
2013 LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK,
2014 LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK,
2015 LCDD16_MARK, LCDD17_MARK,
2016};
2017static const unsigned int lcd_data24_pins[] = {
2018 /* D[0:23] */
2019 192, 193, 194, 195, 196, 197, 198, 199,
2020 200, 201, 202, 203, 204, 205, 206, 207,
2021 208, 209, 210, 211, 212, 213, 214, 215
2022};
2023static const unsigned int lcd_data24_mux[] = {
2024 LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
2025 LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
2026 LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK,
2027 LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK,
2028 LCDD16_MARK, LCDD17_MARK, LCDD18_MARK, LCDD19_MARK,
2029 LCDD20_MARK, LCDD21_MARK, LCDD22_MARK, LCDD23_MARK,
2030};
2031static const unsigned int lcd_display_pins[] = {
2032 /* DON */
2033 222,
2034};
2035static const unsigned int lcd_display_mux[] = {
2036 LCDDON_MARK,
2037};
2038static const unsigned int lcd_lclk_pins[] = {
2039 /* LCLK */
2040 221,
2041};
2042static const unsigned int lcd_lclk_mux[] = {
2043 LCDLCLK_MARK,
2044};
2045static const unsigned int lcd_sync_pins[] = {
2046 /* VSYN, HSYN, DCK, DISP */
2047 220, 218, 216, 219,
2048};
2049static const unsigned int lcd_sync_mux[] = {
2050 LCDVSYN_MARK, LCDHSYN_MARK, LCDDCK_MARK, LCDDISP_MARK,
2051};
2052static const unsigned int lcd_sys_pins[] = {
2053 /* CS, WR, RD, RS */
2054 218, 216, 217, 219,
2055};
2056static const unsigned int lcd_sys_mux[] = {
2057 LCDCS__MARK, LCDWR__MARK, LCDRD__MARK, LCDRS_MARK,
2058};
2059/* - LCD2 ------------------------------------------------------------------- */
2060static const unsigned int lcd2_data8_pins[] = {
2061 /* D[0:7] */
2062 128, 129, 142, 143, 144, 145, 138, 139,
2063};
2064static const unsigned int lcd2_data8_mux[] = {
2065 LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK,
2066 LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK,
2067};
2068static const unsigned int lcd2_data9_pins[] = {
2069 /* D[0:8] */
2070 128, 129, 142, 143, 144, 145, 138, 139,
2071 140,
2072};
2073static const unsigned int lcd2_data9_mux[] = {
2074 LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK,
2075 LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK,
2076 LCD2D8_MARK,
2077};
2078static const unsigned int lcd2_data12_pins[] = {
2079 /* D[0:12] */
2080 128, 129, 142, 143, 144, 145, 138, 139,
2081 140, 141, 130, 131,
2082};
2083static const unsigned int lcd2_data12_mux[] = {
2084 LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK,
2085 LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK,
2086 LCD2D8_MARK, LCD2D9_MARK, LCD2D10_MARK, LCD2D11_MARK,
2087};
2088static const unsigned int lcd2_data16_pins[] = {
2089 /* D[0:15] */
2090 128, 129, 142, 143, 144, 145, 138, 139,
2091 140, 141, 130, 131, 132, 133, 134, 135,
2092};
2093static const unsigned int lcd2_data16_mux[] = {
2094 LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK,
2095 LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK,
2096 LCD2D8_MARK, LCD2D9_MARK, LCD2D10_MARK, LCD2D11_MARK,
2097 LCD2D12_MARK, LCD2D13_MARK, LCD2D14_MARK, LCD2D15_MARK,
2098};
2099static const unsigned int lcd2_data18_pins[] = {
2100 /* D[0:17] */
2101 128, 129, 142, 143, 144, 145, 138, 139,
2102 140, 141, 130, 131, 132, 133, 134, 135,
2103 136, 137,
2104};
2105static const unsigned int lcd2_data18_mux[] = {
2106 LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK,
2107 LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK,
2108 LCD2D8_MARK, LCD2D9_MARK, LCD2D10_MARK, LCD2D11_MARK,
2109 LCD2D12_MARK, LCD2D13_MARK, LCD2D14_MARK, LCD2D15_MARK,
2110 LCD2D16_MARK, LCD2D17_MARK,
2111};
2112static const unsigned int lcd2_data24_pins[] = {
2113 /* D[0:23] */
2114 128, 129, 142, 143, 144, 145, 138, 139,
2115 140, 141, 130, 131, 132, 133, 134, 135,
2116 136, 137, 146, 147, 234, 235, 238, 239
2117};
2118static const unsigned int lcd2_data24_mux[] = {
2119 LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK,
2120 LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK,
2121 LCD2D8_MARK, LCD2D9_MARK, LCD2D10_MARK, LCD2D11_MARK,
2122 LCD2D12_MARK, LCD2D13_MARK, LCD2D14_MARK, LCD2D15_MARK,
2123 LCD2D16_MARK, LCD2D17_MARK, LCD2D18_MARK, LCD2D19_MARK,
2124 LCD2D20_MARK, LCD2D21_MARK, LCD2D22_MARK, LCD2D23_MARK,
2125};
2126static const unsigned int lcd2_sync_0_pins[] = {
2127 /* VSYN, HSYN, DCK, DISP */
2128 128, 129, 146, 145,
2129};
2130static const unsigned int lcd2_sync_0_mux[] = {
2131 PORT128_LCD2VSYN_MARK, PORT129_LCD2HSYN_MARK,
2132 LCD2DCK_MARK, PORT145_LCD2DISP_MARK,
2133};
2134static const unsigned int lcd2_sync_1_pins[] = {
2135 /* VSYN, HSYN, DCK, DISP */
2136 222, 221, 219, 217,
2137};
2138static const unsigned int lcd2_sync_1_mux[] = {
2139 PORT222_LCD2VSYN_MARK, PORT221_LCD2HSYN_MARK,
2140 LCD2DCK_2_MARK, PORT217_LCD2DISP_MARK,
2141};
2142static const unsigned int lcd2_sys_0_pins[] = {
2143 /* CS, WR, RD, RS */
2144 129, 146, 147, 145,
2145};
2146static const unsigned int lcd2_sys_0_mux[] = {
2147 PORT129_LCD2CS__MARK, PORT146_LCD2WR__MARK,
2148 LCD2RD__MARK, PORT145_LCD2RS_MARK,
2149};
2150static const unsigned int lcd2_sys_1_pins[] = {
2151 /* CS, WR, RD, RS */
2152 221, 219, 147, 217,
2153};
2154static const unsigned int lcd2_sys_1_mux[] = {
2155 PORT221_LCD2CS__MARK, PORT219_LCD2WR__MARK,
2156 LCD2RD__MARK, PORT217_LCD2RS_MARK,
2157};
Guennadi Liakhovetski82f6b6d2013-02-12 16:50:03 +0100[diff] [blame]2158/* - MMCIF ------------------------------------------------------------------ */
2159static const unsigned int mmc0_data1_0_pins[] = {
2160 /* D[0] */
2161 271,
2162};
2163static const unsigned int mmc0_data1_0_mux[] = {
2164 MMCD0_0_MARK,
2165};
2166static const unsigned int mmc0_data4_0_pins[] = {
2167 /* D[0:3] */
2168 271, 272, 273, 274,
2169};
2170static const unsigned int mmc0_data4_0_mux[] = {
2171 MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK,
2172};
2173static const unsigned int mmc0_data8_0_pins[] = {
2174 /* D[0:7] */
2175 271, 272, 273, 274, 275, 276, 277, 278,
2176};
2177static const unsigned int mmc0_data8_0_mux[] = {
2178 MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK,
2179 MMCD0_4_MARK, MMCD0_5_MARK, MMCD0_6_MARK, MMCD0_7_MARK,
2180};
2181static const unsigned int mmc0_ctrl_0_pins[] = {
2182 /* CMD, CLK */
2183 279, 270,
2184};
2185static const unsigned int mmc0_ctrl_0_mux[] = {
2186 MMCCMD0_MARK, MMCCLK0_MARK,
2187};
2188
2189static const unsigned int mmc0_data1_1_pins[] = {
2190 /* D[0] */
2191 305,
2192};
2193static const unsigned int mmc0_data1_1_mux[] = {
2194 MMCD1_0_MARK,
2195};
2196static const unsigned int mmc0_data4_1_pins[] = {
2197 /* D[0:3] */
2198 305, 304, 303, 302,
2199};
2200static const unsigned int mmc0_data4_1_mux[] = {
2201 MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK,
2202};
2203static const unsigned int mmc0_data8_1_pins[] = {
2204 /* D[0:7] */
2205 305, 304, 303, 302, 301, 300, 299, 298,
2206};
2207static const unsigned int mmc0_data8_1_mux[] = {
2208 MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK,
2209 MMCD1_4_MARK, MMCD1_5_MARK, MMCD1_6_MARK, MMCD1_7_MARK,
2210};
2211static const unsigned int mmc0_ctrl_1_pins[] = {
2212 /* CMD, CLK */
2213 297, 289,
2214};
2215static const unsigned int mmc0_ctrl_1_mux[] = {
2216 MMCCMD1_MARK, MMCCLK1_MARK,
2217};
Laurent Pinchart64d87ac2013-01-03 13:07:05 +0100[diff] [blame]2218/* - SCIFA0 ----------------------------------------------------------------- */
2219static const unsigned int scifa0_data_pins[] = {
2220 /* RXD, TXD */
2221 43, 17,
2222};
2223static const unsigned int scifa0_data_mux[] = {
2224 SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
2225};
2226static const unsigned int scifa0_clk_pins[] = {
2227 /* SCK */
2228 16,
2229};
2230static const unsigned int scifa0_clk_mux[] = {
2231 SCIFA0_SCK_MARK,
2232};
2233static const unsigned int scifa0_ctrl_pins[] = {
2234 /* RTS, CTS */
2235 42, 44,
2236};
2237static const unsigned int scifa0_ctrl_mux[] = {
2238 SCIFA0_RTS__MARK, SCIFA0_CTS__MARK,
2239};
2240/* - SCIFA1 ----------------------------------------------------------------- */
2241static const unsigned int scifa1_data_pins[] = {
2242 /* RXD, TXD */
2243 228, 225,
2244};
2245static const unsigned int scifa1_data_mux[] = {
2246 SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
2247};
2248static const unsigned int scifa1_clk_pins[] = {
2249 /* SCK */
2250 226,
2251};
2252static const unsigned int scifa1_clk_mux[] = {
2253 SCIFA1_SCK_MARK,
2254};
2255static const unsigned int scifa1_ctrl_pins[] = {
2256 /* RTS, CTS */
2257 227, 229,
2258};
2259static const unsigned int scifa1_ctrl_mux[] = {
2260 SCIFA1_RTS__MARK, SCIFA1_CTS__MARK,
2261};
2262/* - SCIFA2 ----------------------------------------------------------------- */
2263static const unsigned int scifa2_data_0_pins[] = {
2264 /* RXD, TXD */
2265 155, 154,
2266};
2267static const unsigned int scifa2_data_0_mux[] = {
2268 SCIFA2_RXD1_MARK, SCIFA2_TXD1_MARK,
2269};
2270static const unsigned int scifa2_clk_0_pins[] = {
2271 /* SCK */
2272 158,
2273};
2274static const unsigned int scifa2_clk_0_mux[] = {
2275 SCIFA2_SCK1_MARK,
2276};
2277static const unsigned int scifa2_ctrl_0_pins[] = {
2278 /* RTS, CTS */
2279 156, 157,
2280};
2281static const unsigned int scifa2_ctrl_0_mux[] = {
2282 SCIFA2_RTS1__MARK, SCIFA2_CTS1__MARK,
2283};
2284static const unsigned int scifa2_data_1_pins[] = {
2285 /* RXD, TXD */
2286 233, 230,
2287};
2288static const unsigned int scifa2_data_1_mux[] = {
2289 SCIFA2_RXD2_MARK, SCIFA2_TXD2_MARK,
2290};
2291static const unsigned int scifa2_clk_1_pins[] = {
2292 /* SCK */
2293 232,
2294};
2295static const unsigned int scifa2_clk_1_mux[] = {
2296 SCIFA2_SCK2_MARK,
2297};
2298static const unsigned int scifa2_ctrl_1_pins[] = {
2299 /* RTS, CTS */
2300 234, 231,
2301};
2302static const unsigned int scifa2_ctrl_1_mux[] = {
2303 SCIFA2_RTS2__MARK, SCIFA2_CTS2__MARK,
2304};
2305/* - SCIFA3 ----------------------------------------------------------------- */
2306static const unsigned int scifa3_data_pins[] = {
2307 /* RXD, TXD */
2308 108, 110,
2309};
2310static const unsigned int scifa3_data_mux[] = {
2311 SCIFA3_RXD_MARK, SCIFA3_TXD_MARK,
2312};
2313static const unsigned int scifa3_ctrl_pins[] = {
2314 /* RTS, CTS */
2315 109, 107,
2316};
2317static const unsigned int scifa3_ctrl_mux[] = {
2318 SCIFA3_RTS__MARK, SCIFA3_CTS__MARK,
2319};
2320/* - SCIFA4 ----------------------------------------------------------------- */
2321static const unsigned int scifa4_data_pins[] = {
2322 /* RXD, TXD */
2323 33, 32,
2324};
2325static const unsigned int scifa4_data_mux[] = {
2326 SCIFA4_RXD_MARK, SCIFA4_TXD_MARK,
2327};
2328static const unsigned int scifa4_ctrl_pins[] = {
2329 /* RTS, CTS */
2330 34, 35,
2331};
2332static const unsigned int scifa4_ctrl_mux[] = {
2333 SCIFA4_RTS__MARK, SCIFA4_CTS__MARK,
2334};
2335/* - SCIFA5 ----------------------------------------------------------------- */
2336static const unsigned int scifa5_data_0_pins[] = {
2337 /* RXD, TXD */
2338 246, 247,
2339};
2340static const unsigned int scifa5_data_0_mux[] = {
2341 PORT246_SCIFA5_RXD_MARK, PORT247_SCIFA5_TXD_MARK,
2342};
2343static const unsigned int scifa5_clk_0_pins[] = {
2344 /* SCK */
2345 248,
2346};
2347static const unsigned int scifa5_clk_0_mux[] = {
2348 PORT248_SCIFA5_SCK_MARK,
2349};
2350static const unsigned int scifa5_ctrl_0_pins[] = {
2351 /* RTS, CTS */
2352 245, 244,
2353};
2354static const unsigned int scifa5_ctrl_0_mux[] = {
2355 PORT245_SCIFA5_RTS__MARK, PORT244_SCIFA5_CTS__MARK,
2356};
2357static const unsigned int scifa5_data_1_pins[] = {
2358 /* RXD, TXD */
2359 195, 196,
2360};
2361static const unsigned int scifa5_data_1_mux[] = {
2362 PORT195_SCIFA5_RXD_MARK, PORT196_SCIFA5_TXD_MARK,
2363};
2364static const unsigned int scifa5_clk_1_pins[] = {
2365 /* SCK */
2366 197,
2367};
2368static const unsigned int scifa5_clk_1_mux[] = {
2369 PORT197_SCIFA5_SCK_MARK,
2370};
2371static const unsigned int scifa5_ctrl_1_pins[] = {
2372 /* RTS, CTS */
2373 194, 193,
2374};
2375static const unsigned int scifa5_ctrl_1_mux[] = {
2376 PORT194_SCIFA5_RTS__MARK, PORT193_SCIFA5_CTS__MARK,
2377};
2378static const unsigned int scifa5_data_2_pins[] = {
2379 /* RXD, TXD */
2380 162, 160,
2381};
2382static const unsigned int scifa5_data_2_mux[] = {
2383 PORT162_SCIFA5_RXD_MARK, PORT160_SCIFA5_TXD_MARK,
2384};
2385static const unsigned int scifa5_clk_2_pins[] = {
2386 /* SCK */
2387 159,
2388};
2389static const unsigned int scifa5_clk_2_mux[] = {
2390 PORT159_SCIFA5_SCK_MARK,
2391};
2392static const unsigned int scifa5_ctrl_2_pins[] = {
2393 /* RTS, CTS */
2394 163, 161,
2395};
2396static const unsigned int scifa5_ctrl_2_mux[] = {
2397 PORT163_SCIFA5_RTS__MARK, PORT161_SCIFA5_CTS__MARK,
2398};
2399/* - SCIFA6 ----------------------------------------------------------------- */
2400static const unsigned int scifa6_pins[] = {
2401 /* TXD */
2402 240,
2403};
2404static const unsigned int scifa6_mux[] = {
2405 SCIFA6_TXD_MARK,
2406};
2407/* - SCIFA7 ----------------------------------------------------------------- */
2408static const unsigned int scifa7_data_pins[] = {
2409 /* RXD, TXD */
2410 12, 18,
2411};
2412static const unsigned int scifa7_data_mux[] = {
2413 SCIFA7_RXD_MARK, SCIFA7_TXD_MARK,
2414};
2415static const unsigned int scifa7_ctrl_pins[] = {
2416 /* RTS, CTS */
2417 19, 13,
2418};
2419static const unsigned int scifa7_ctrl_mux[] = {
2420 SCIFA7_RTS__MARK, SCIFA7_CTS__MARK,
2421};
2422/* - SCIFB ------------------------------------------------------------------ */
2423static const unsigned int scifb_data_0_pins[] = {
2424 /* RXD, TXD */
2425 162, 160,
2426};
2427static const unsigned int scifb_data_0_mux[] = {
2428 PORT162_SCIFB_RXD_MARK, PORT160_SCIFB_TXD_MARK,
2429};
2430static const unsigned int scifb_clk_0_pins[] = {
2431 /* SCK */
2432 159,
2433};
2434static const unsigned int scifb_clk_0_mux[] = {
2435 PORT159_SCIFB_SCK_MARK,
2436};
2437static const unsigned int scifb_ctrl_0_pins[] = {
2438 /* RTS, CTS */
2439 163, 161,
2440};
2441static const unsigned int scifb_ctrl_0_mux[] = {
2442 PORT163_SCIFB_RTS__MARK, PORT161_SCIFB_CTS__MARK,
2443};
2444static const unsigned int scifb_data_1_pins[] = {
2445 /* RXD, TXD */
2446 246, 247,
2447};
2448static const unsigned int scifb_data_1_mux[] = {
2449 PORT246_SCIFB_RXD_MARK, PORT247_SCIFB_TXD_MARK,
2450};
2451static const unsigned int scifb_clk_1_pins[] = {
2452 /* SCK */
2453 248,
2454};
2455static const unsigned int scifb_clk_1_mux[] = {
2456 PORT248_SCIFB_SCK_MARK,
2457};
2458static const unsigned int scifb_ctrl_1_pins[] = {
2459 /* RTS, CTS */
2460 245, 244,
2461};
2462static const unsigned int scifb_ctrl_1_mux[] = {
2463 PORT245_SCIFB_RTS__MARK, PORT244_SCIFB_CTS__MARK,
2464};
Guennadi Liakhovetski82f6b6d2013-02-12 16:50:03 +0100[diff] [blame]2465/* - SDHI0 ------------------------------------------------------------------ */
2466static const unsigned int sdhi0_data1_pins[] = {
2467 /* D0 */
2468 252,
2469};
2470static const unsigned int sdhi0_data1_mux[] = {
2471 SDHID0_0_MARK,
2472};
2473static const unsigned int sdhi0_data4_pins[] = {
2474 /* D[0:3] */
2475 252, 253, 254, 255,
2476};
2477static const unsigned int sdhi0_data4_mux[] = {
2478 SDHID0_0_MARK, SDHID0_1_MARK, SDHID0_2_MARK, SDHID0_3_MARK,
2479};
2480static const unsigned int sdhi0_ctrl_pins[] = {
2481 /* CMD, CLK */
2482 256, 250,
2483};
2484static const unsigned int sdhi0_ctrl_mux[] = {
2485 SDHICMD0_MARK, SDHICLK0_MARK,
2486};
2487static const unsigned int sdhi0_cd_pins[] = {
2488 /* CD */
2489 251,
2490};
2491static const unsigned int sdhi0_cd_mux[] = {
2492 SDHICD0_MARK,
2493};
2494static const unsigned int sdhi0_wp_pins[] = {
2495 /* WP */
2496 257,
2497};
2498static const unsigned int sdhi0_wp_mux[] = {
2499 SDHIWP0_MARK,
2500};
2501/* - SDHI1 ------------------------------------------------------------------ */
2502static const unsigned int sdhi1_data1_pins[] = {
2503 /* D0 */
2504 259,
2505};
2506static const unsigned int sdhi1_data1_mux[] = {
2507 SDHID1_0_MARK,
2508};
2509static const unsigned int sdhi1_data4_pins[] = {
2510 /* D[0:3] */
2511 259, 260, 261, 262,
2512};
2513static const unsigned int sdhi1_data4_mux[] = {
2514 SDHID1_0_MARK, SDHID1_1_MARK, SDHID1_2_MARK, SDHID1_3_MARK,
2515};
2516static const unsigned int sdhi1_ctrl_pins[] = {
2517 /* CMD, CLK */
2518 263, 258,
2519};
2520static const unsigned int sdhi1_ctrl_mux[] = {
2521 SDHICMD1_MARK, SDHICLK1_MARK,
2522};
2523/* - SDHI2 ------------------------------------------------------------------ */
2524static const unsigned int sdhi2_data1_pins[] = {
2525 /* D0 */
2526 265,
2527};
2528static const unsigned int sdhi2_data1_mux[] = {
2529 SDHID2_0_MARK,
2530};
2531static const unsigned int sdhi2_data4_pins[] = {
2532 /* D[0:3] */
2533 265, 266, 267, 268,
2534};
2535static const unsigned int sdhi2_data4_mux[] = {
2536 SDHID2_0_MARK, SDHID2_1_MARK, SDHID2_2_MARK, SDHID2_3_MARK,
2537};
2538static const unsigned int sdhi2_ctrl_pins[] = {
2539 /* CMD, CLK */
2540 269, 264,
2541};
2542static const unsigned int sdhi2_ctrl_mux[] = {
2543 SDHICMD2_MARK, SDHICLK2_MARK,
2544};
Laurent Pinchart5da4eb02013-04-24 01:07:16 +0200[diff] [blame^]2545/* - TPU0 ------------------------------------------------------------------- */
2546static const unsigned int tpu0_to0_pins[] = {
2547 /* TO */
2548 55,
2549};
2550static const unsigned int tpu0_to0_mux[] = {
2551 TPU0TO0_MARK,
2552};
2553static const unsigned int tpu0_to1_pins[] = {
2554 /* TO */
2555 59,
2556};
2557static const unsigned int tpu0_to1_mux[] = {
2558 TPU0TO1_MARK,
2559};
2560static const unsigned int tpu0_to2_pins[] = {
2561 /* TO */
2562 140,
2563};
2564static const unsigned int tpu0_to2_mux[] = {
2565 TPU0TO2_MARK,
2566};
2567static const unsigned int tpu0_to3_pins[] = {
2568 /* TO */
2569 141,
2570};
2571static const unsigned int tpu0_to3_mux[] = {
2572 TPU0TO3_MARK,
2573};
2574/* - TPU1 ------------------------------------------------------------------- */
2575static const unsigned int tpu1_to0_pins[] = {
2576 /* TO */
2577 246,
2578};
2579static const unsigned int tpu1_to0_mux[] = {
2580 TPU1TO0_MARK,
2581};
2582static const unsigned int tpu1_to1_0_pins[] = {
2583 /* TO */
2584 28,
2585};
2586static const unsigned int tpu1_to1_0_mux[] = {
2587 PORT28_TPU1TO1_MARK,
2588};
2589static const unsigned int tpu1_to1_1_pins[] = {
2590 /* TO */
2591 29,
2592};
2593static const unsigned int tpu1_to1_1_mux[] = {
2594 PORT29_TPU1TO1_MARK,
2595};
2596static const unsigned int tpu1_to2_pins[] = {
2597 /* TO */
2598 153,
2599};
2600static const unsigned int tpu1_to2_mux[] = {
2601 TPU1TO2_MARK,
2602};
2603static const unsigned int tpu1_to3_pins[] = {
2604 /* TO */
2605 145,
2606};
2607static const unsigned int tpu1_to3_mux[] = {
2608 TPU1TO3_MARK,
2609};
2610/* - TPU2 ------------------------------------------------------------------- */
2611static const unsigned int tpu2_to0_pins[] = {
2612 /* TO */
2613 248,
2614};
2615static const unsigned int tpu2_to0_mux[] = {
2616 TPU2TO0_MARK,
2617};
2618static const unsigned int tpu2_to1_pins[] = {
2619 /* TO */
2620 197,
2621};
2622static const unsigned int tpu2_to1_mux[] = {
2623 TPU2TO1_MARK,
2624};
2625static const unsigned int tpu2_to2_pins[] = {
2626 /* TO */
2627 50,
2628};
2629static const unsigned int tpu2_to2_mux[] = {
2630 TPU2TO2_MARK,
2631};
2632static const unsigned int tpu2_to3_pins[] = {
2633 /* TO */
2634 51,
2635};
2636static const unsigned int tpu2_to3_mux[] = {
2637 TPU2TO3_MARK,
2638};
2639/* - TPU3 ------------------------------------------------------------------- */
2640static const unsigned int tpu3_to0_pins[] = {
2641 /* TO */
2642 163,
2643};
2644static const unsigned int tpu3_to0_mux[] = {
2645 TPU3TO0_MARK,
2646};
2647static const unsigned int tpu3_to1_pins[] = {
2648 /* TO */
2649 247,
2650};
2651static const unsigned int tpu3_to1_mux[] = {
2652 TPU3TO1_MARK,
2653};
2654static const unsigned int tpu3_to2_pins[] = {
2655 /* TO */
2656 54,
2657};
2658static const unsigned int tpu3_to2_mux[] = {
2659 TPU3TO2_MARK,
2660};
2661static const unsigned int tpu3_to3_pins[] = {
2662 /* TO */
2663 53,
2664};
2665static const unsigned int tpu3_to3_mux[] = {
2666 TPU3TO3_MARK,
2667};
2668/* - TPU4 ------------------------------------------------------------------- */
2669static const unsigned int tpu4_to0_pins[] = {
2670 /* TO */
2671 241,
2672};
2673static const unsigned int tpu4_to0_mux[] = {
2674 TPU4TO0_MARK,
2675};
2676static const unsigned int tpu4_to1_pins[] = {
2677 /* TO */
2678 199,
2679};
2680static const unsigned int tpu4_to1_mux[] = {
2681 TPU4TO1_MARK,
2682};
2683static const unsigned int tpu4_to2_pins[] = {
2684 /* TO */
2685 58,
2686};
2687static const unsigned int tpu4_to2_mux[] = {
2688 TPU4TO2_MARK,
2689};
2690static const unsigned int tpu4_to3_pins[] = {
2691 /* TO */
2692};
2693static const unsigned int tpu4_to3_mux[] = {
2694 TPU4TO3_MARK,
2695};
Laurent Pincharta6aa1c72013-03-12 01:55:08 +0100[diff] [blame]2696/* - USB -------------------------------------------------------------------- */
2697static const unsigned int usb_vbus_pins[] = {
2698 /* VBUS */
2699 0,
2700};
2701static const unsigned int usb_vbus_mux[] = {
2702 VBUS_0_MARK,
2703};
Laurent Pinchartdf68a282013-01-03 13:07:05 +0100[diff] [blame]2704
2705static const struct sh_pfc_pin_group pinmux_groups[] = {
Laurent Pincharte24c62a2013-03-12 01:55:08 +0100[diff] [blame]2706 SH_PFC_PIN_GROUP(bsc_data_0_7),
2707 SH_PFC_PIN_GROUP(bsc_data_8_15),
2708 SH_PFC_PIN_GROUP(bsc_cs4),
2709 SH_PFC_PIN_GROUP(bsc_cs5_a),
2710 SH_PFC_PIN_GROUP(bsc_cs5_b),
2711 SH_PFC_PIN_GROUP(bsc_cs6_a),
2712 SH_PFC_PIN_GROUP(bsc_cs6_b),
2713 SH_PFC_PIN_GROUP(bsc_rd),
2714 SH_PFC_PIN_GROUP(bsc_rdwr_0),
2715 SH_PFC_PIN_GROUP(bsc_rdwr_1),
2716 SH_PFC_PIN_GROUP(bsc_rdwr_2),
2717 SH_PFC_PIN_GROUP(bsc_we0),
2718 SH_PFC_PIN_GROUP(bsc_we1),
Laurent Pinchart2ecd4152013-01-03 13:07:05 +0100[diff] [blame]2719 SH_PFC_PIN_GROUP(fsia_mclk_in),
2720 SH_PFC_PIN_GROUP(fsia_mclk_out),
2721 SH_PFC_PIN_GROUP(fsia_sclk_in),
2722 SH_PFC_PIN_GROUP(fsia_sclk_out),
2723 SH_PFC_PIN_GROUP(fsia_data_in),
2724 SH_PFC_PIN_GROUP(fsia_data_out),
2725 SH_PFC_PIN_GROUP(fsia_spdif),
2726 SH_PFC_PIN_GROUP(fsib_mclk_in),
2727 SH_PFC_PIN_GROUP(fsib_mclk_out),
2728 SH_PFC_PIN_GROUP(fsib_sclk_in),
2729 SH_PFC_PIN_GROUP(fsib_sclk_out),
2730 SH_PFC_PIN_GROUP(fsib_data_in),
2731 SH_PFC_PIN_GROUP(fsib_data_out),
2732 SH_PFC_PIN_GROUP(fsib_spdif),
2733 SH_PFC_PIN_GROUP(fsic_mclk_in),
2734 SH_PFC_PIN_GROUP(fsic_mclk_out),
2735 SH_PFC_PIN_GROUP(fsic_sclk_in),
2736 SH_PFC_PIN_GROUP(fsic_sclk_out),
2737 SH_PFC_PIN_GROUP(fsic_data_in),
2738 SH_PFC_PIN_GROUP(fsic_data_out),
2739 SH_PFC_PIN_GROUP(fsic_spdif_0),
2740 SH_PFC_PIN_GROUP(fsic_spdif_1),
2741 SH_PFC_PIN_GROUP(fsid_sclk_in),
2742 SH_PFC_PIN_GROUP(fsid_sclk_out),
2743 SH_PFC_PIN_GROUP(fsid_data_in),
Laurent Pinchartec3a57b2013-01-03 13:07:05 +0100[diff] [blame]2744 SH_PFC_PIN_GROUP(i2c2_0),
2745 SH_PFC_PIN_GROUP(i2c2_1),
2746 SH_PFC_PIN_GROUP(i2c2_2),
2747 SH_PFC_PIN_GROUP(i2c3_0),
2748 SH_PFC_PIN_GROUP(i2c3_1),
2749 SH_PFC_PIN_GROUP(i2c3_2),
Laurent Pinchart512b1562013-03-12 01:55:08 +0100[diff] [blame]2750 SH_PFC_PIN_GROUP(irda_0),
2751 SH_PFC_PIN_GROUP(irda_1),
Laurent Pinchartd6bab7b2013-03-12 01:55:08 +0100[diff] [blame]2752 SH_PFC_PIN_GROUP(keysc_in5),
2753 SH_PFC_PIN_GROUP(keysc_in6),
2754 SH_PFC_PIN_GROUP(keysc_in7),
2755 SH_PFC_PIN_GROUP(keysc_in8),
2756 SH_PFC_PIN_GROUP(keysc_out04),
2757 SH_PFC_PIN_GROUP(keysc_out5),
2758 SH_PFC_PIN_GROUP(keysc_out6_0),
2759 SH_PFC_PIN_GROUP(keysc_out6_1),
2760 SH_PFC_PIN_GROUP(keysc_out6_2),
2761 SH_PFC_PIN_GROUP(keysc_out7_0),
2762 SH_PFC_PIN_GROUP(keysc_out7_1),
2763 SH_PFC_PIN_GROUP(keysc_out7_2),
2764 SH_PFC_PIN_GROUP(keysc_out8_0),
2765 SH_PFC_PIN_GROUP(keysc_out8_1),
2766 SH_PFC_PIN_GROUP(keysc_out8_2),
2767 SH_PFC_PIN_GROUP(keysc_out9_0),
2768 SH_PFC_PIN_GROUP(keysc_out9_1),
2769 SH_PFC_PIN_GROUP(keysc_out9_2),
2770 SH_PFC_PIN_GROUP(keysc_out10_0),
2771 SH_PFC_PIN_GROUP(keysc_out10_1),
2772 SH_PFC_PIN_GROUP(keysc_out11_0),
2773 SH_PFC_PIN_GROUP(keysc_out11_1),
Laurent Pinchartdf68a282013-01-03 13:07:05 +0100[diff] [blame]2774 SH_PFC_PIN_GROUP(lcd_data8),
2775 SH_PFC_PIN_GROUP(lcd_data9),
2776 SH_PFC_PIN_GROUP(lcd_data12),
2777 SH_PFC_PIN_GROUP(lcd_data16),
2778 SH_PFC_PIN_GROUP(lcd_data18),
2779 SH_PFC_PIN_GROUP(lcd_data24),
2780 SH_PFC_PIN_GROUP(lcd_display),
2781 SH_PFC_PIN_GROUP(lcd_lclk),
2782 SH_PFC_PIN_GROUP(lcd_sync),
2783 SH_PFC_PIN_GROUP(lcd_sys),
2784 SH_PFC_PIN_GROUP(lcd2_data8),
2785 SH_PFC_PIN_GROUP(lcd2_data9),
2786 SH_PFC_PIN_GROUP(lcd2_data12),
2787 SH_PFC_PIN_GROUP(lcd2_data16),
2788 SH_PFC_PIN_GROUP(lcd2_data18),
2789 SH_PFC_PIN_GROUP(lcd2_data24),
2790 SH_PFC_PIN_GROUP(lcd2_sync_0),
2791 SH_PFC_PIN_GROUP(lcd2_sync_1),
2792 SH_PFC_PIN_GROUP(lcd2_sys_0),
2793 SH_PFC_PIN_GROUP(lcd2_sys_1),
Guennadi Liakhovetski82f6b6d2013-02-12 16:50:03 +0100[diff] [blame]2794 SH_PFC_PIN_GROUP(mmc0_data1_0),
2795 SH_PFC_PIN_GROUP(mmc0_data4_0),
2796 SH_PFC_PIN_GROUP(mmc0_data8_0),
2797 SH_PFC_PIN_GROUP(mmc0_ctrl_0),
2798 SH_PFC_PIN_GROUP(mmc0_data1_1),
2799 SH_PFC_PIN_GROUP(mmc0_data4_1),
2800 SH_PFC_PIN_GROUP(mmc0_data8_1),
2801 SH_PFC_PIN_GROUP(mmc0_ctrl_1),
Laurent Pinchart64d87ac2013-01-03 13:07:05 +0100[diff] [blame]2802 SH_PFC_PIN_GROUP(scifa0_data),
2803 SH_PFC_PIN_GROUP(scifa0_clk),
2804 SH_PFC_PIN_GROUP(scifa0_ctrl),
2805 SH_PFC_PIN_GROUP(scifa1_data),
2806 SH_PFC_PIN_GROUP(scifa1_clk),
2807 SH_PFC_PIN_GROUP(scifa1_ctrl),
2808 SH_PFC_PIN_GROUP(scifa2_data_0),
2809 SH_PFC_PIN_GROUP(scifa2_clk_0),
2810 SH_PFC_PIN_GROUP(scifa2_ctrl_0),
2811 SH_PFC_PIN_GROUP(scifa2_data_1),
2812 SH_PFC_PIN_GROUP(scifa2_clk_1),
2813 SH_PFC_PIN_GROUP(scifa2_ctrl_1),
2814 SH_PFC_PIN_GROUP(scifa3_data),
2815 SH_PFC_PIN_GROUP(scifa3_ctrl),
2816 SH_PFC_PIN_GROUP(scifa4_data),
2817 SH_PFC_PIN_GROUP(scifa4_ctrl),
2818 SH_PFC_PIN_GROUP(scifa5_data_0),
2819 SH_PFC_PIN_GROUP(scifa5_clk_0),
2820 SH_PFC_PIN_GROUP(scifa5_ctrl_0),
2821 SH_PFC_PIN_GROUP(scifa5_data_1),
2822 SH_PFC_PIN_GROUP(scifa5_clk_1),
2823 SH_PFC_PIN_GROUP(scifa5_ctrl_1),
2824 SH_PFC_PIN_GROUP(scifa5_data_2),
2825 SH_PFC_PIN_GROUP(scifa5_clk_2),
2826 SH_PFC_PIN_GROUP(scifa5_ctrl_2),
2827 SH_PFC_PIN_GROUP(scifa6),
2828 SH_PFC_PIN_GROUP(scifa7_data),
2829 SH_PFC_PIN_GROUP(scifa7_ctrl),
2830 SH_PFC_PIN_GROUP(scifb_data_0),
2831 SH_PFC_PIN_GROUP(scifb_clk_0),
2832 SH_PFC_PIN_GROUP(scifb_ctrl_0),
2833 SH_PFC_PIN_GROUP(scifb_data_1),
2834 SH_PFC_PIN_GROUP(scifb_clk_1),
2835 SH_PFC_PIN_GROUP(scifb_ctrl_1),
Guennadi Liakhovetski82f6b6d2013-02-12 16:50:03 +0100[diff] [blame]2836 SH_PFC_PIN_GROUP(sdhi0_data1),
2837 SH_PFC_PIN_GROUP(sdhi0_data4),
2838 SH_PFC_PIN_GROUP(sdhi0_ctrl),
2839 SH_PFC_PIN_GROUP(sdhi0_cd),
2840 SH_PFC_PIN_GROUP(sdhi0_wp),
2841 SH_PFC_PIN_GROUP(sdhi1_data1),
2842 SH_PFC_PIN_GROUP(sdhi1_data4),
2843 SH_PFC_PIN_GROUP(sdhi1_ctrl),
2844 SH_PFC_PIN_GROUP(sdhi2_data1),
2845 SH_PFC_PIN_GROUP(sdhi2_data4),
2846 SH_PFC_PIN_GROUP(sdhi2_ctrl),
Laurent Pinchart5da4eb02013-04-24 01:07:16 +0200[diff] [blame^]2847 SH_PFC_PIN_GROUP(tpu0_to0),
2848 SH_PFC_PIN_GROUP(tpu0_to1),
2849 SH_PFC_PIN_GROUP(tpu0_to2),
2850 SH_PFC_PIN_GROUP(tpu0_to3),
2851 SH_PFC_PIN_GROUP(tpu1_to0),
2852 SH_PFC_PIN_GROUP(tpu1_to1_0),
2853 SH_PFC_PIN_GROUP(tpu1_to1_1),
2854 SH_PFC_PIN_GROUP(tpu1_to2),
2855 SH_PFC_PIN_GROUP(tpu1_to3),
2856 SH_PFC_PIN_GROUP(tpu2_to0),
2857 SH_PFC_PIN_GROUP(tpu2_to1),
2858 SH_PFC_PIN_GROUP(tpu2_to2),
2859 SH_PFC_PIN_GROUP(tpu2_to3),
2860 SH_PFC_PIN_GROUP(tpu3_to0),
2861 SH_PFC_PIN_GROUP(tpu3_to1),
2862 SH_PFC_PIN_GROUP(tpu3_to2),
2863 SH_PFC_PIN_GROUP(tpu3_to3),
2864 SH_PFC_PIN_GROUP(tpu4_to0),
2865 SH_PFC_PIN_GROUP(tpu4_to1),
2866 SH_PFC_PIN_GROUP(tpu4_to2),
2867 SH_PFC_PIN_GROUP(tpu4_to3),
Laurent Pincharta6aa1c72013-03-12 01:55:08 +0100[diff] [blame]2868 SH_PFC_PIN_GROUP(usb_vbus),
Laurent Pinchartdf68a282013-01-03 13:07:05 +0100[diff] [blame]2869};
2870
Laurent Pincharte24c62a2013-03-12 01:55:08 +0100[diff] [blame]2871static const char * const bsc_groups[] = {
2872 "bsc_data_0_7",
2873 "bsc_data_8_15",
2874 "bsc_cs4",
2875 "bsc_cs5_a",
2876 "bsc_cs5_b",
2877 "bsc_cs6_a",
2878 "bsc_cs6_b",
2879 "bsc_rd",
2880 "bsc_rdwr_0",
2881 "bsc_rdwr_1",
2882 "bsc_rdwr_2",
2883 "bsc_we0",
2884 "bsc_we1",
2885};
2886
Laurent Pinchart2ecd4152013-01-03 13:07:05 +0100[diff] [blame]2887static const char * const fsia_groups[] = {
2888 "fsia_mclk_in",
2889 "fsia_mclk_out",
2890 "fsia_sclk_in",
2891 "fsia_sclk_out",
2892 "fsia_data_in",
2893 "fsia_data_out",
2894 "fsia_spdif",
2895};
2896
2897static const char * const fsib_groups[] = {
2898 "fsib_mclk_in",
2899 "fsib_mclk_out",
2900 "fsib_sclk_in",
2901 "fsib_sclk_out",
2902 "fsib_data_in",
2903 "fsib_data_out",
2904 "fsib_spdif",
2905};
2906
2907static const char * const fsic_groups[] = {
2908 "fsic_mclk_in",
2909 "fsic_mclk_out",
2910 "fsic_sclk_in",
2911 "fsic_sclk_out",
2912 "fsic_data_in",
2913 "fsic_data_out",
2914 "fsic_spdif",
2915};
2916
2917static const char * const fsid_groups[] = {
2918 "fsid_sclk_in",
2919 "fsid_sclk_out",
2920 "fsid_data_in",
2921};
2922
Laurent Pinchartec3a57b2013-01-03 13:07:05 +0100[diff] [blame]2923static const char * const i2c2_groups[] = {
2924 "i2c2_0",
2925 "i2c2_1",
2926 "i2c2_2",
2927};
2928
2929static const char * const i2c3_groups[] = {
2930 "i2c3_0",
2931 "i2c3_1",
2932 "i2c3_2",
2933};
2934
Laurent Pinchart512b1562013-03-12 01:55:08 +0100[diff] [blame]2935static const char * const irda_groups[] = {
2936 "irda_0",
2937 "irda_1",
2938};
2939
Laurent Pinchartd6bab7b2013-03-12 01:55:08 +0100[diff] [blame]2940static const char * const keysc_groups[] = {
2941 "keysc_in5",
2942 "keysc_in6",
2943 "keysc_in7",
2944 "keysc_in8",
2945 "keysc_out04",
2946 "keysc_out5",
2947 "keysc_out6_0",
2948 "keysc_out6_1",
2949 "keysc_out6_2",
2950 "keysc_out7_0",
2951 "keysc_out7_1",
2952 "keysc_out7_2",
2953 "keysc_out8_0",
2954 "keysc_out8_1",
2955 "keysc_out8_2",
2956 "keysc_out9_0",
2957 "keysc_out9_1",
2958 "keysc_out9_2",
2959 "keysc_out10_0",
2960 "keysc_out10_1",
2961 "keysc_out11_0",
2962 "keysc_out11_1",
2963};
2964
Laurent Pinchartdf68a282013-01-03 13:07:05 +0100[diff] [blame]2965static const char * const lcd_groups[] = {
2966 "lcd_data8",
2967 "lcd_data9",
2968 "lcd_data12",
2969 "lcd_data16",
2970 "lcd_data18",
2971 "lcd_data24",
2972 "lcd_display",
2973 "lcd_lclk",
2974 "lcd_sync",
2975 "lcd_sys",
2976};
2977
2978static const char * const lcd2_groups[] = {
2979 "lcd2_data8",
2980 "lcd2_data9",
2981 "lcd2_data12",
2982 "lcd2_data16",
2983 "lcd2_data18",
2984 "lcd2_data24",
2985 "lcd2_sync_0",
2986 "lcd2_sync_1",
2987 "lcd2_sys_0",
2988 "lcd2_sys_1",
2989};
2990
Guennadi Liakhovetski82f6b6d2013-02-12 16:50:03 +0100[diff] [blame]2991static const char * const mmc0_groups[] = {
2992 "mmc0_data1_0",
2993 "mmc0_data4_0",
2994 "mmc0_data8_0",
2995 "mmc0_ctrl_0",
2996 "mmc0_data1_1",
2997 "mmc0_data4_1",
2998 "mmc0_data8_1",
2999 "mmc0_ctrl_1",
3000};
3001
Laurent Pinchart64d87ac2013-01-03 13:07:05 +0100[diff] [blame]3002static const char * const scifa0_groups[] = {
3003 "scifa0_data",
3004 "scifa0_clk",
3005 "scifa0_ctrl",
3006};
3007
3008static const char * const scifa1_groups[] = {
3009 "scifa1_data",
3010 "scifa1_clk",
3011 "scifa1_ctrl",
3012};
3013
3014static const char * const scifa2_groups[] = {
3015 "scifa2_data_0",
3016 "scifa2_clk_0",
3017 "scifa2_ctrl_0",
3018 "scifa2_data_1",
3019 "scifa2_clk_1",
3020 "scifa2_ctrl_1",
3021};
3022
3023static const char * const scifa3_groups[] = {
3024 "scifa3_data",
3025 "scifa3_ctrl",
3026};
3027
3028static const char * const scifa4_groups[] = {
3029 "scifa4_data",
3030 "scifa4_ctrl",
3031};
3032
3033static const char * const scifa5_groups[] = {
3034 "scifa5_data_0",
3035 "scifa5_clk_0",
3036 "scifa5_ctrl_0",
3037 "scifa5_data_1",
3038 "scifa5_clk_1",
3039 "scifa5_ctrl_1",
3040 "scifa5_data_2",
3041 "scifa5_clk_2",
3042 "scifa5_ctrl_2",
3043};
3044
3045static const char * const scifa6_groups[] = {
3046 "scifa6",
3047};
3048
3049static const char * const scifa7_groups[] = {
3050 "scifa7_data",
3051 "scifa7_ctrl",
3052};
3053
3054static const char * const scifb_groups[] = {
3055 "scifb_data_0",
3056 "scifb_clk_0",
3057 "scifb_ctrl_0",
3058 "scifb_data_1",
3059 "scifb_clk_1",
3060 "scifb_ctrl_1",
3061};
3062
Guennadi Liakhovetski82f6b6d2013-02-12 16:50:03 +0100[diff] [blame]3063static const char * const sdhi0_groups[] = {
3064 "sdhi0_data1",
3065 "sdhi0_data4",
3066 "sdhi0_ctrl",
3067 "sdhi0_cd",
3068 "sdhi0_wp",
3069};
3070
3071static const char * const sdhi1_groups[] = {
3072 "sdhi1_data1",
3073 "sdhi1_data4",
3074 "sdhi1_ctrl",
3075};
3076
3077static const char * const sdhi2_groups[] = {
3078 "sdhi2_data1",
3079 "sdhi2_data4",
3080 "sdhi2_ctrl",
3081};
3082
Laurent Pincharta6aa1c72013-03-12 01:55:08 +0100[diff] [blame]3083static const char * const usb_groups[] = {
3084 "usb_vbus",
3085};
3086
Laurent Pinchart5da4eb02013-04-24 01:07:16 +0200[diff] [blame^]3087static const char * const tpu0_groups[] = {
3088 "tpu0_to0",
3089 "tpu0_to1",
3090 "tpu0_to2",
3091 "tpu0_to3",
3092};
3093
3094static const char * const tpu1_groups[] = {
3095 "tpu1_to0",
3096 "tpu1_to1_0",
3097 "tpu1_to1_1",
3098 "tpu1_to2",
3099 "tpu1_to3",
3100};
3101
3102static const char * const tpu2_groups[] = {
3103 "tpu2_to0",
3104 "tpu2_to1",
3105 "tpu2_to2",
3106 "tpu2_to3",
3107};
3108
3109static const char * const tpu3_groups[] = {
3110 "tpu3_to0",
3111 "tpu3_to1",
3112 "tpu3_to2",
3113 "tpu3_to3",
3114};
3115
3116static const char * const tpu4_groups[] = {
3117 "tpu4_to0",
3118 "tpu4_to1",
3119 "tpu4_to2",
3120 "tpu4_to3",
3121};
3122
Laurent Pinchartdf68a282013-01-03 13:07:05 +0100[diff] [blame]3123static const struct sh_pfc_function pinmux_functions[] = {
Laurent Pincharte24c62a2013-03-12 01:55:08 +0100[diff] [blame]3124 SH_PFC_FUNCTION(bsc),
Laurent Pinchart2ecd4152013-01-03 13:07:05 +0100[diff] [blame]3125 SH_PFC_FUNCTION(fsia),
3126 SH_PFC_FUNCTION(fsib),
3127 SH_PFC_FUNCTION(fsic),
3128 SH_PFC_FUNCTION(fsid),
Laurent Pinchartec3a57b2013-01-03 13:07:05 +0100[diff] [blame]3129 SH_PFC_FUNCTION(i2c2),
3130 SH_PFC_FUNCTION(i2c3),
Laurent Pinchart512b1562013-03-12 01:55:08 +0100[diff] [blame]3131 SH_PFC_FUNCTION(irda),
Laurent Pinchartd6bab7b2013-03-12 01:55:08 +0100[diff] [blame]3132 SH_PFC_FUNCTION(keysc),
Laurent Pinchartdf68a282013-01-03 13:07:05 +0100[diff] [blame]3133 SH_PFC_FUNCTION(lcd),
3134 SH_PFC_FUNCTION(lcd2),
Guennadi Liakhovetski82f6b6d2013-02-12 16:50:03 +0100[diff] [blame]3135 SH_PFC_FUNCTION(mmc0),
Laurent Pinchart64d87ac2013-01-03 13:07:05 +0100[diff] [blame]3136 SH_PFC_FUNCTION(scifa0),
3137 SH_PFC_FUNCTION(scifa1),
3138 SH_PFC_FUNCTION(scifa2),
3139 SH_PFC_FUNCTION(scifa3),
3140 SH_PFC_FUNCTION(scifa4),
3141 SH_PFC_FUNCTION(scifa5),
3142 SH_PFC_FUNCTION(scifa6),
3143 SH_PFC_FUNCTION(scifa7),
3144 SH_PFC_FUNCTION(scifb),
Guennadi Liakhovetski82f6b6d2013-02-12 16:50:03 +0100[diff] [blame]3145 SH_PFC_FUNCTION(sdhi0),
3146 SH_PFC_FUNCTION(sdhi1),
3147 SH_PFC_FUNCTION(sdhi2),
Laurent Pinchart5da4eb02013-04-24 01:07:16 +0200[diff] [blame^]3148 SH_PFC_FUNCTION(tpu0),
3149 SH_PFC_FUNCTION(tpu1),
3150 SH_PFC_FUNCTION(tpu2),
3151 SH_PFC_FUNCTION(tpu3),
3152 SH_PFC_FUNCTION(tpu4),
Laurent Pincharta6aa1c72013-03-12 01:55:08 +0100[diff] [blame]3153 SH_PFC_FUNCTION(usb),
Laurent Pinchartdf68a282013-01-03 13:07:05 +0100[diff] [blame]3154};
3155
Laurent Pinchartf03e4be2013-03-13 18:53:05 +0100[diff] [blame]3156#define PINMUX_FN_BASE GPIO_FN_GPI0
Laurent Pincharta373ed02012-11-29 13:24:07 +0100[diff] [blame]3157
Laurent Pinchartcd3c1be2013-02-16 18:47:05 +0100[diff] [blame]3158static const struct pinmux_func pinmux_func_gpios[] = {
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3159 /* Table 25-1 (Functions 0-7) */
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3160 GPIO_FN(GPI0),
3161 GPIO_FN(GPI1),
3162 GPIO_FN(GPI2),
3163 GPIO_FN(GPI3),
3164 GPIO_FN(GPI4),
3165 GPIO_FN(GPI5),
3166 GPIO_FN(GPI6),
3167 GPIO_FN(GPI7),
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3168 GPIO_FN(GPO7), \
3169 GPIO_FN(MFG0_OUT2),
3170 GPIO_FN(GPO6), \
3171 GPIO_FN(MFG1_OUT2),
3172 GPIO_FN(GPO5), \
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3173 GPIO_FN(PORT16_VIO_CKOR),
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3174 GPIO_FN(PORT19_VIO_CKO2),
3175 GPIO_FN(GPO0),
3176 GPIO_FN(GPO1),
3177 GPIO_FN(GPO2), \
3178 GPIO_FN(STATUS0),
3179 GPIO_FN(GPO3), \
3180 GPIO_FN(STATUS1),
3181 GPIO_FN(GPO4), \
3182 GPIO_FN(STATUS2),
3183 GPIO_FN(VINT),
3184 GPIO_FN(TCKON),
3185 GPIO_FN(XDVFS1), \
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3186 GPIO_FN(MFG0_OUT1), \
3187 GPIO_FN(PORT27_IROUT),
3188 GPIO_FN(XDVFS2), \
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3189 GPIO_FN(PORT28_TPU1TO1),
3190 GPIO_FN(SIM_RST), \
3191 GPIO_FN(PORT29_TPU1TO1),
3192 GPIO_FN(SIM_CLK), \
3193 GPIO_FN(PORT30_VIO_CKOR),
3194 GPIO_FN(SIM_D), \
3195 GPIO_FN(PORT31_IROUT),
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3196 GPIO_FN(XWUP),
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3197 GPIO_FN(VACK),
3198 GPIO_FN(XTAL1L),
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3199 GPIO_FN(PORT49_IROUT), \
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3200 GPIO_FN(BBIF2_TSYNC2), \
3201 GPIO_FN(TPU2TO2), \
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3202
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3203 GPIO_FN(BBIF2_TSCK2), \
3204 GPIO_FN(TPU2TO3), \
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3205 GPIO_FN(BBIF2_TXD2),
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3206 GPIO_FN(TPU3TO3), \
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3207 GPIO_FN(TPU3TO2), \
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3208 GPIO_FN(TPU0TO0),
3209 GPIO_FN(A0), \
3210 GPIO_FN(BS_),
3211 GPIO_FN(A12), \
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3212 GPIO_FN(TPU4TO2),
3213 GPIO_FN(A13), \
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3214 GPIO_FN(TPU0TO1),
3215 GPIO_FN(A14), \
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3216 GPIO_FN(A15), \
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3217 GPIO_FN(A16), \
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3218 GPIO_FN(MSIOF0_SS1),
3219 GPIO_FN(A17), \
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3220 GPIO_FN(MSIOF0_TSYNC),
3221 GPIO_FN(A18), \
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3222 GPIO_FN(MSIOF0_TSCK),
3223 GPIO_FN(A19), \
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3224 GPIO_FN(MSIOF0_TXD),
3225 GPIO_FN(A20), \
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3226 GPIO_FN(MSIOF0_RSCK),
3227 GPIO_FN(A21), \
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3228 GPIO_FN(MSIOF0_RSYNC),
3229 GPIO_FN(A22), \
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3230 GPIO_FN(MSIOF0_MCK0),
3231 GPIO_FN(A23), \
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3232 GPIO_FN(MSIOF0_MCK1),
3233 GPIO_FN(A24), \
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3234 GPIO_FN(MSIOF0_RXD),
3235 GPIO_FN(A25), \
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3236 GPIO_FN(MSIOF0_SS2),
3237 GPIO_FN(A26), \
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3238 GPIO_FN(FCE1_),
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3239 GPIO_FN(DACK0),
3240 GPIO_FN(FCE0_), \
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3241 GPIO_FN(WAIT_), \
3242 GPIO_FN(DREQ0),
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3243 GPIO_FN(FRB),
3244 GPIO_FN(CKO),
3245 GPIO_FN(NBRSTOUT_),
3246 GPIO_FN(NBRST_),
3247 GPIO_FN(BBIF2_TXD),
3248 GPIO_FN(BBIF2_RXD),
3249 GPIO_FN(BBIF2_SYNC),
3250 GPIO_FN(BBIF2_SCK),
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3251 GPIO_FN(MFG3_IN2),
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3252 GPIO_FN(MFG3_IN1),
3253 GPIO_FN(BBIF1_SS2), \
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3254 GPIO_FN(MFG3_OUT1),
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3255 GPIO_FN(HSI_RX_DATA), \
3256 GPIO_FN(BBIF1_RXD),
3257 GPIO_FN(HSI_TX_WAKE), \
3258 GPIO_FN(BBIF1_TSCK),
3259 GPIO_FN(HSI_TX_DATA), \
3260 GPIO_FN(BBIF1_TSYNC),
3261 GPIO_FN(HSI_TX_READY), \
3262 GPIO_FN(BBIF1_TXD),
3263 GPIO_FN(HSI_RX_READY), \
3264 GPIO_FN(BBIF1_RSCK), \
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3265 GPIO_FN(HSI_RX_WAKE), \
3266 GPIO_FN(BBIF1_RSYNC), \
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3267 GPIO_FN(HSI_RX_FLAG), \
3268 GPIO_FN(BBIF1_SS1), \
3269 GPIO_FN(BBIF1_FLOW),
3270 GPIO_FN(HSI_TX_FLAG),
3271 GPIO_FN(VIO_VD), \
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3272 GPIO_FN(VIO2_VD), \
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3273
3274 GPIO_FN(VIO_HD), \
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3275 GPIO_FN(VIO2_HD), \
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3276 GPIO_FN(VIO_D0), \
3277 GPIO_FN(PORT130_MSIOF2_RXD), \
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3278 GPIO_FN(VIO_D1), \
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3279 GPIO_FN(PORT131_MSIOF2_SS1), \
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3280 GPIO_FN(VIO_D2), \
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3281 GPIO_FN(PORT132_MSIOF2_SS2), \
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3282 GPIO_FN(VIO_D3), \
3283 GPIO_FN(MSIOF2_TSYNC), \
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3284 GPIO_FN(VIO_D4), \
3285 GPIO_FN(MSIOF2_TXD), \
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3286 GPIO_FN(VIO_D5), \
3287 GPIO_FN(MSIOF2_TSCK), \
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3288 GPIO_FN(VIO_D6), \
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3289 GPIO_FN(VIO_D7), \
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3290 GPIO_FN(VIO_D8), \
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3291 GPIO_FN(VIO2_D0), \
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3292 GPIO_FN(VIO_D9), \
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3293 GPIO_FN(VIO2_D1), \
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3294 GPIO_FN(VIO_D10), \
3295 GPIO_FN(TPU0TO2), \
3296 GPIO_FN(VIO2_D2), \
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3297 GPIO_FN(VIO_D11), \
3298 GPIO_FN(TPU0TO3), \
3299 GPIO_FN(VIO2_D3), \
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3300 GPIO_FN(VIO_D12), \
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3301 GPIO_FN(VIO2_D4), \
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3302 GPIO_FN(VIO_D13), \
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3303 GPIO_FN(VIO2_D5), \
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3304 GPIO_FN(VIO_D14), \
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3305 GPIO_FN(VIO2_D6), \
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3306 GPIO_FN(VIO_D15), \
3307 GPIO_FN(TPU1TO3), \
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3308 GPIO_FN(VIO2_D7), \
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3309 GPIO_FN(VIO_CLK), \
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3310 GPIO_FN(VIO2_CLK), \
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3311 GPIO_FN(VIO_FIELD), \
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3312 GPIO_FN(VIO2_FIELD), \
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3313 GPIO_FN(VIO_CKO),
3314 GPIO_FN(A27), \
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3315 GPIO_FN(MFG0_IN1), \
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3316 GPIO_FN(MFG0_IN2),
3317 GPIO_FN(TS_SPSYNC3), \
3318 GPIO_FN(MSIOF2_RSCK),
3319 GPIO_FN(TS_SDAT3), \
3320 GPIO_FN(MSIOF2_RSYNC),
3321 GPIO_FN(TPU1TO2), \
3322 GPIO_FN(TS_SDEN3), \
3323 GPIO_FN(PORT153_MSIOF2_SS1),
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3324 GPIO_FN(MSIOF2_MCK0),
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3325 GPIO_FN(MSIOF2_MCK1),
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3326 GPIO_FN(PORT156_MSIOF2_SS2),
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3327 GPIO_FN(PORT157_MSIOF2_RXD),
3328 GPIO_FN(DINT_), \
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3329 GPIO_FN(TS_SCK3),
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3330 GPIO_FN(NMI),
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3331 GPIO_FN(TPU3TO0),
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3332 GPIO_FN(BBIF2_TSYNC1),
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3333 GPIO_FN(BBIF2_TSCK1),
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3334 GPIO_FN(BBIF2_TXD1),
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3335 GPIO_FN(MFG2_OUT2), \
3336 GPIO_FN(TPU2TO1),
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3337 GPIO_FN(TPU4TO1), \
3338 GPIO_FN(MFG4_OUT2),
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3339 GPIO_FN(D16),
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3340 GPIO_FN(D17),
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3341 GPIO_FN(D18),
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3342 GPIO_FN(D19),
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3343 GPIO_FN(D20),
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3344 GPIO_FN(D21),
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3345 GPIO_FN(D22),
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3346 GPIO_FN(PORT207_MSIOF0L_SS1), \
3347 GPIO_FN(D23),
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3348 GPIO_FN(PORT208_MSIOF0L_SS2), \
3349 GPIO_FN(D24),
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3350 GPIO_FN(D25),
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3351 GPIO_FN(DREQ2), \
3352 GPIO_FN(PORT210_MSIOF0L_SS1), \
3353 GPIO_FN(D26),
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3354 GPIO_FN(PORT211_MSIOF0L_SS2), \
3355 GPIO_FN(D27),
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3356 GPIO_FN(TS_SPSYNC1), \
3357 GPIO_FN(MSIOF0L_MCK0), \
3358 GPIO_FN(D28),
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3359 GPIO_FN(TS_SDAT1), \
3360 GPIO_FN(MSIOF0L_MCK1), \
3361 GPIO_FN(D29),
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3362 GPIO_FN(TS_SDEN1), \
3363 GPIO_FN(MSIOF0L_RSCK), \
3364 GPIO_FN(D30),
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3365 GPIO_FN(TS_SCK1), \
3366 GPIO_FN(MSIOF0L_RSYNC), \
3367 GPIO_FN(D31),
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3368 GPIO_FN(DACK2), \
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3369 GPIO_FN(MSIOF0L_TSYNC), \
3370 GPIO_FN(VIO2_FIELD3), \
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3371 GPIO_FN(DACK3), \
3372 GPIO_FN(PORT218_VIO_CKOR),
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3373 GPIO_FN(DREQ3), \
3374 GPIO_FN(MSIOF0L_TSCK), \
3375 GPIO_FN(VIO2_CLK3), \
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3376 GPIO_FN(DREQ1), \
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3377 GPIO_FN(PWEN), \
3378 GPIO_FN(MSIOF0L_RXD), \
3379 GPIO_FN(VIO2_HD3), \
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3380 GPIO_FN(DACK1), \
3381 GPIO_FN(OVCN), \
3382 GPIO_FN(MSIOF0L_TXD), \
3383 GPIO_FN(VIO2_VD3), \
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3384
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3385 GPIO_FN(OVCN2),
3386 GPIO_FN(EXTLP), \
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3387 GPIO_FN(PORT226_VIO_CKO2),
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3388 GPIO_FN(IDIN),
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3389 GPIO_FN(MFG1_IN1),
3390 GPIO_FN(MSIOF1_TXD), \
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3391 GPIO_FN(MSIOF1_TSYNC), \
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3392 GPIO_FN(MSIOF1_TSCK), \
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3393 GPIO_FN(MSIOF1_RXD), \
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3394 GPIO_FN(MSIOF1_RSCK), \
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3395 GPIO_FN(VIO2_CLK2), \
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3396 GPIO_FN(MSIOF1_RSYNC), \
3397 GPIO_FN(MFG1_IN2), \
3398 GPIO_FN(VIO2_VD2), \
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3399 GPIO_FN(MSIOF1_MCK0), \
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3400 GPIO_FN(MSIOF1_MCK1), \
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3401 GPIO_FN(MSIOF1_SS1), \
3402 GPIO_FN(VIO2_FIELD2), \
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3403 GPIO_FN(MSIOF1_SS2), \
3404 GPIO_FN(VIO2_HD2), \
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3405 GPIO_FN(PORT241_IROUT), \
3406 GPIO_FN(MFG4_OUT1), \
3407 GPIO_FN(TPU4TO0),
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3408 GPIO_FN(MFG4_IN2),
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3409 GPIO_FN(PORT243_VIO_CKO2),
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3410 GPIO_FN(MFG2_IN1), \
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3411 GPIO_FN(MSIOF2R_RXD),
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3412 GPIO_FN(MFG2_IN2), \
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3413 GPIO_FN(MSIOF2R_TXD),
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3414 GPIO_FN(MFG1_OUT1), \
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3415 GPIO_FN(TPU1TO0),
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3416 GPIO_FN(MFG3_OUT2), \
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3417 GPIO_FN(TPU3TO1),
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3418 GPIO_FN(MFG2_OUT1), \
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3419 GPIO_FN(TPU2TO0), \
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3420 GPIO_FN(MSIOF2R_TSCK),
3421 GPIO_FN(PORT249_IROUT), \
3422 GPIO_FN(MFG4_IN1), \
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3423 GPIO_FN(MSIOF2R_TSYNC),
3424 GPIO_FN(SDHICLK0),
3425 GPIO_FN(SDHICD0),
3426 GPIO_FN(SDHID0_0),
3427 GPIO_FN(SDHID0_1),
3428 GPIO_FN(SDHID0_2),
3429 GPIO_FN(SDHID0_3),
3430 GPIO_FN(SDHICMD0),
3431 GPIO_FN(SDHIWP0),
3432 GPIO_FN(SDHICLK1),
3433 GPIO_FN(SDHID1_0), \
3434 GPIO_FN(TS_SPSYNC2),
3435 GPIO_FN(SDHID1_1), \
3436 GPIO_FN(TS_SDAT2),
3437 GPIO_FN(SDHID1_2), \
3438 GPIO_FN(TS_SDEN2),
3439 GPIO_FN(SDHID1_3), \
3440 GPIO_FN(TS_SCK2),
3441 GPIO_FN(SDHICMD1),
3442 GPIO_FN(SDHICLK2),
3443 GPIO_FN(SDHID2_0), \
3444 GPIO_FN(TS_SPSYNC4),
3445 GPIO_FN(SDHID2_1), \
3446 GPIO_FN(TS_SDAT4),
3447 GPIO_FN(SDHID2_2), \
3448 GPIO_FN(TS_SDEN4),
3449 GPIO_FN(SDHID2_3), \
3450 GPIO_FN(TS_SCK4),
3451 GPIO_FN(SDHICMD2),
3452 GPIO_FN(MMCCLK0),
3453 GPIO_FN(MMCD0_0),
3454 GPIO_FN(MMCD0_1),
3455 GPIO_FN(MMCD0_2),
3456 GPIO_FN(MMCD0_3),
3457 GPIO_FN(MMCD0_4), \
3458 GPIO_FN(TS_SPSYNC5),
3459 GPIO_FN(MMCD0_5), \
3460 GPIO_FN(TS_SDAT5),
3461 GPIO_FN(MMCD0_6), \
3462 GPIO_FN(TS_SDEN5),
3463 GPIO_FN(MMCD0_7), \
3464 GPIO_FN(TS_SCK5),
3465 GPIO_FN(MMCCMD0),
3466 GPIO_FN(RESETOUTS_), \
3467 GPIO_FN(EXTAL2OUT),
3468 GPIO_FN(MCP_WAIT__MCP_FRB),
3469 GPIO_FN(MCP_CKO), \
3470 GPIO_FN(MMCCLK1),
3471 GPIO_FN(MCP_D15_MCP_NAF15),
3472 GPIO_FN(MCP_D14_MCP_NAF14),
3473 GPIO_FN(MCP_D13_MCP_NAF13),
3474 GPIO_FN(MCP_D12_MCP_NAF12),
3475 GPIO_FN(MCP_D11_MCP_NAF11),
3476 GPIO_FN(MCP_D10_MCP_NAF10),
3477 GPIO_FN(MCP_D9_MCP_NAF9),
3478 GPIO_FN(MCP_D8_MCP_NAF8), \
3479 GPIO_FN(MMCCMD1),
3480 GPIO_FN(MCP_D7_MCP_NAF7), \
3481 GPIO_FN(MMCD1_7),
3482
3483 GPIO_FN(MCP_D6_MCP_NAF6), \
3484 GPIO_FN(MMCD1_6),
3485 GPIO_FN(MCP_D5_MCP_NAF5), \
3486 GPIO_FN(MMCD1_5),
3487 GPIO_FN(MCP_D4_MCP_NAF4), \
3488 GPIO_FN(MMCD1_4),
3489 GPIO_FN(MCP_D3_MCP_NAF3), \
3490 GPIO_FN(MMCD1_3),
3491 GPIO_FN(MCP_D2_MCP_NAF2), \
3492 GPIO_FN(MMCD1_2),
3493 GPIO_FN(MCP_D1_MCP_NAF1), \
3494 GPIO_FN(MMCD1_1),
3495 GPIO_FN(MCP_D0_MCP_NAF0), \
3496 GPIO_FN(MMCD1_0),
3497 GPIO_FN(MCP_NBRSTOUT_),
3498 GPIO_FN(MCP_WE0__MCP_FWE), \
3499 GPIO_FN(MCP_RDWR_MCP_FWE),
3500
3501 /* MSEL2 special cases */
3502 GPIO_FN(TSIF2_TS_XX1),
3503 GPIO_FN(TSIF2_TS_XX2),
3504 GPIO_FN(TSIF2_TS_XX3),
3505 GPIO_FN(TSIF2_TS_XX4),
3506 GPIO_FN(TSIF2_TS_XX5),
3507 GPIO_FN(TSIF1_TS_XX1),
3508 GPIO_FN(TSIF1_TS_XX2),
3509 GPIO_FN(TSIF1_TS_XX3),
3510 GPIO_FN(TSIF1_TS_XX4),
3511 GPIO_FN(TSIF1_TS_XX5),
3512 GPIO_FN(TSIF0_TS_XX1),
3513 GPIO_FN(TSIF0_TS_XX2),
3514 GPIO_FN(TSIF0_TS_XX3),
3515 GPIO_FN(TSIF0_TS_XX4),
3516 GPIO_FN(TSIF0_TS_XX5),
3517 GPIO_FN(MST1_TS_XX1),
3518 GPIO_FN(MST1_TS_XX2),
3519 GPIO_FN(MST1_TS_XX3),
3520 GPIO_FN(MST1_TS_XX4),
3521 GPIO_FN(MST1_TS_XX5),
3522 GPIO_FN(MST0_TS_XX1),
3523 GPIO_FN(MST0_TS_XX2),
3524 GPIO_FN(MST0_TS_XX3),
3525 GPIO_FN(MST0_TS_XX4),
3526 GPIO_FN(MST0_TS_XX5),
3527
3528 /* MSEL3 special cases */
3529 GPIO_FN(SDHI0_VCCQ_MC0_ON),
3530 GPIO_FN(SDHI0_VCCQ_MC0_OFF),
3531 GPIO_FN(DEBUG_MON_VIO),
3532 GPIO_FN(DEBUG_MON_LCDD),
3533 GPIO_FN(LCDC_LCDC0),
3534 GPIO_FN(LCDC_LCDC1),
3535
3536 /* MSEL4 special cases */
3537 GPIO_FN(IRQ9_MEM_INT),
3538 GPIO_FN(IRQ9_MCP_INT),
3539 GPIO_FN(A11),
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3540 GPIO_FN(TPU4TO3),
3541 GPIO_FN(RESETA_N_PU_ON),
3542 GPIO_FN(RESETA_N_PU_OFF),
3543 GPIO_FN(EDBGREQ_PD),
3544 GPIO_FN(EDBGREQ_PU),
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3545};
3546
Laurent Pinchart19ac5552013-03-13 18:32:00 +0100[diff] [blame]3547#undef PORTCR
3548#define PORTCR(nr, reg) \
3549 { \
3550 PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) { \
3551 _PCRH(PORT##nr##_IN, 0, 0, PORT##nr##_OUT), \
3552 PORT##nr##_FN0, PORT##nr##_FN1, \
3553 PORT##nr##_FN2, PORT##nr##_FN3, \
3554 PORT##nr##_FN4, PORT##nr##_FN5, \
3555 PORT##nr##_FN6, PORT##nr##_FN7 } \
3556 }
Laurent Pinchartcd3c1be2013-02-16 18:47:05 +0100[diff] [blame]3557static const struct pinmux_cfg_reg pinmux_config_regs[] = {
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3558 PORTCR(0, 0xe6050000), /* PORT0CR */
3559 PORTCR(1, 0xe6050001), /* PORT1CR */
3560 PORTCR(2, 0xe6050002), /* PORT2CR */
3561 PORTCR(3, 0xe6050003), /* PORT3CR */
3562 PORTCR(4, 0xe6050004), /* PORT4CR */
3563 PORTCR(5, 0xe6050005), /* PORT5CR */
3564 PORTCR(6, 0xe6050006), /* PORT6CR */
3565 PORTCR(7, 0xe6050007), /* PORT7CR */
3566 PORTCR(8, 0xe6050008), /* PORT8CR */
3567 PORTCR(9, 0xe6050009), /* PORT9CR */
3568
3569 PORTCR(10, 0xe605000a), /* PORT10CR */
3570 PORTCR(11, 0xe605000b), /* PORT11CR */
3571 PORTCR(12, 0xe605000c), /* PORT12CR */
3572 PORTCR(13, 0xe605000d), /* PORT13CR */
3573 PORTCR(14, 0xe605000e), /* PORT14CR */
3574 PORTCR(15, 0xe605000f), /* PORT15CR */
3575 PORTCR(16, 0xe6050010), /* PORT16CR */
3576 PORTCR(17, 0xe6050011), /* PORT17CR */
3577 PORTCR(18, 0xe6050012), /* PORT18CR */
3578 PORTCR(19, 0xe6050013), /* PORT19CR */
3579
3580 PORTCR(20, 0xe6050014), /* PORT20CR */
3581 PORTCR(21, 0xe6050015), /* PORT21CR */
3582 PORTCR(22, 0xe6050016), /* PORT22CR */
3583 PORTCR(23, 0xe6050017), /* PORT23CR */
3584 PORTCR(24, 0xe6050018), /* PORT24CR */
3585 PORTCR(25, 0xe6050019), /* PORT25CR */
3586 PORTCR(26, 0xe605001a), /* PORT26CR */
3587 PORTCR(27, 0xe605001b), /* PORT27CR */
3588 PORTCR(28, 0xe605001c), /* PORT28CR */
3589 PORTCR(29, 0xe605001d), /* PORT29CR */
3590
3591 PORTCR(30, 0xe605001e), /* PORT30CR */
3592 PORTCR(31, 0xe605001f), /* PORT31CR */
3593 PORTCR(32, 0xe6051020), /* PORT32CR */
3594 PORTCR(33, 0xe6051021), /* PORT33CR */
3595 PORTCR(34, 0xe6051022), /* PORT34CR */
3596 PORTCR(35, 0xe6051023), /* PORT35CR */
3597 PORTCR(36, 0xe6051024), /* PORT36CR */
3598 PORTCR(37, 0xe6051025), /* PORT37CR */
3599 PORTCR(38, 0xe6051026), /* PORT38CR */
3600 PORTCR(39, 0xe6051027), /* PORT39CR */
3601
3602 PORTCR(40, 0xe6051028), /* PORT40CR */
3603 PORTCR(41, 0xe6051029), /* PORT41CR */
3604 PORTCR(42, 0xe605102a), /* PORT42CR */
3605 PORTCR(43, 0xe605102b), /* PORT43CR */
3606 PORTCR(44, 0xe605102c), /* PORT44CR */
3607 PORTCR(45, 0xe605102d), /* PORT45CR */
3608 PORTCR(46, 0xe605102e), /* PORT46CR */
3609 PORTCR(47, 0xe605102f), /* PORT47CR */
3610 PORTCR(48, 0xe6051030), /* PORT48CR */
3611 PORTCR(49, 0xe6051031), /* PORT49CR */
3612
3613 PORTCR(50, 0xe6051032), /* PORT50CR */
3614 PORTCR(51, 0xe6051033), /* PORT51CR */
3615 PORTCR(52, 0xe6051034), /* PORT52CR */
3616 PORTCR(53, 0xe6051035), /* PORT53CR */
3617 PORTCR(54, 0xe6051036), /* PORT54CR */
3618 PORTCR(55, 0xe6051037), /* PORT55CR */
3619 PORTCR(56, 0xe6051038), /* PORT56CR */
3620 PORTCR(57, 0xe6051039), /* PORT57CR */
3621 PORTCR(58, 0xe605103a), /* PORT58CR */
3622 PORTCR(59, 0xe605103b), /* PORT59CR */
3623
3624 PORTCR(60, 0xe605103c), /* PORT60CR */
3625 PORTCR(61, 0xe605103d), /* PORT61CR */
3626 PORTCR(62, 0xe605103e), /* PORT62CR */
3627 PORTCR(63, 0xe605103f), /* PORT63CR */
3628 PORTCR(64, 0xe6051040), /* PORT64CR */
3629 PORTCR(65, 0xe6051041), /* PORT65CR */
3630 PORTCR(66, 0xe6051042), /* PORT66CR */
3631 PORTCR(67, 0xe6051043), /* PORT67CR */
3632 PORTCR(68, 0xe6051044), /* PORT68CR */
3633 PORTCR(69, 0xe6051045), /* PORT69CR */
3634
3635 PORTCR(70, 0xe6051046), /* PORT70CR */
3636 PORTCR(71, 0xe6051047), /* PORT71CR */
3637 PORTCR(72, 0xe6051048), /* PORT72CR */
3638 PORTCR(73, 0xe6051049), /* PORT73CR */
3639 PORTCR(74, 0xe605104a), /* PORT74CR */
3640 PORTCR(75, 0xe605104b), /* PORT75CR */
3641 PORTCR(76, 0xe605104c), /* PORT76CR */
3642 PORTCR(77, 0xe605104d), /* PORT77CR */
3643 PORTCR(78, 0xe605104e), /* PORT78CR */
3644 PORTCR(79, 0xe605104f), /* PORT79CR */
3645
3646 PORTCR(80, 0xe6051050), /* PORT80CR */
3647 PORTCR(81, 0xe6051051), /* PORT81CR */
3648 PORTCR(82, 0xe6051052), /* PORT82CR */
3649 PORTCR(83, 0xe6051053), /* PORT83CR */
3650 PORTCR(84, 0xe6051054), /* PORT84CR */
3651 PORTCR(85, 0xe6051055), /* PORT85CR */
3652 PORTCR(86, 0xe6051056), /* PORT86CR */
3653 PORTCR(87, 0xe6051057), /* PORT87CR */
3654 PORTCR(88, 0xe6051058), /* PORT88CR */
3655 PORTCR(89, 0xe6051059), /* PORT89CR */
3656
3657 PORTCR(90, 0xe605105a), /* PORT90CR */
3658 PORTCR(91, 0xe605105b), /* PORT91CR */
3659 PORTCR(92, 0xe605105c), /* PORT92CR */
3660 PORTCR(93, 0xe605105d), /* PORT93CR */
3661 PORTCR(94, 0xe605105e), /* PORT94CR */
3662 PORTCR(95, 0xe605105f), /* PORT95CR */
3663 PORTCR(96, 0xe6052060), /* PORT96CR */
3664 PORTCR(97, 0xe6052061), /* PORT97CR */
3665 PORTCR(98, 0xe6052062), /* PORT98CR */
3666 PORTCR(99, 0xe6052063), /* PORT99CR */
3667
3668 PORTCR(100, 0xe6052064), /* PORT100CR */
3669 PORTCR(101, 0xe6052065), /* PORT101CR */
3670 PORTCR(102, 0xe6052066), /* PORT102CR */
3671 PORTCR(103, 0xe6052067), /* PORT103CR */
3672 PORTCR(104, 0xe6052068), /* PORT104CR */
3673 PORTCR(105, 0xe6052069), /* PORT105CR */
3674 PORTCR(106, 0xe605206a), /* PORT106CR */
3675 PORTCR(107, 0xe605206b), /* PORT107CR */
3676 PORTCR(108, 0xe605206c), /* PORT108CR */
3677 PORTCR(109, 0xe605206d), /* PORT109CR */
3678
3679 PORTCR(110, 0xe605206e), /* PORT110CR */
3680 PORTCR(111, 0xe605206f), /* PORT111CR */
3681 PORTCR(112, 0xe6052070), /* PORT112CR */
3682 PORTCR(113, 0xe6052071), /* PORT113CR */
3683 PORTCR(114, 0xe6052072), /* PORT114CR */
3684 PORTCR(115, 0xe6052073), /* PORT115CR */
3685 PORTCR(116, 0xe6052074), /* PORT116CR */
3686 PORTCR(117, 0xe6052075), /* PORT117CR */
3687 PORTCR(118, 0xe6052076), /* PORT118CR */
3688
3689 PORTCR(128, 0xe6052080), /* PORT128CR */
3690 PORTCR(129, 0xe6052081), /* PORT129CR */
3691
3692 PORTCR(130, 0xe6052082), /* PORT130CR */
3693 PORTCR(131, 0xe6052083), /* PORT131CR */
3694 PORTCR(132, 0xe6052084), /* PORT132CR */
3695 PORTCR(133, 0xe6052085), /* PORT133CR */
3696 PORTCR(134, 0xe6052086), /* PORT134CR */
3697 PORTCR(135, 0xe6052087), /* PORT135CR */
3698 PORTCR(136, 0xe6052088), /* PORT136CR */
3699 PORTCR(137, 0xe6052089), /* PORT137CR */
3700 PORTCR(138, 0xe605208a), /* PORT138CR */
3701 PORTCR(139, 0xe605208b), /* PORT139CR */
3702
3703 PORTCR(140, 0xe605208c), /* PORT140CR */
3704 PORTCR(141, 0xe605208d), /* PORT141CR */
3705 PORTCR(142, 0xe605208e), /* PORT142CR */
3706 PORTCR(143, 0xe605208f), /* PORT143CR */
3707 PORTCR(144, 0xe6052090), /* PORT144CR */
3708 PORTCR(145, 0xe6052091), /* PORT145CR */
3709 PORTCR(146, 0xe6052092), /* PORT146CR */
3710 PORTCR(147, 0xe6052093), /* PORT147CR */
3711 PORTCR(148, 0xe6052094), /* PORT148CR */
3712 PORTCR(149, 0xe6052095), /* PORT149CR */
3713
3714 PORTCR(150, 0xe6052096), /* PORT150CR */
3715 PORTCR(151, 0xe6052097), /* PORT151CR */
3716 PORTCR(152, 0xe6052098), /* PORT152CR */
3717 PORTCR(153, 0xe6052099), /* PORT153CR */
3718 PORTCR(154, 0xe605209a), /* PORT154CR */
3719 PORTCR(155, 0xe605209b), /* PORT155CR */
3720 PORTCR(156, 0xe605209c), /* PORT156CR */
3721 PORTCR(157, 0xe605209d), /* PORT157CR */
3722 PORTCR(158, 0xe605209e), /* PORT158CR */
3723 PORTCR(159, 0xe605209f), /* PORT159CR */
3724
3725 PORTCR(160, 0xe60520a0), /* PORT160CR */
3726 PORTCR(161, 0xe60520a1), /* PORT161CR */
3727 PORTCR(162, 0xe60520a2), /* PORT162CR */
3728 PORTCR(163, 0xe60520a3), /* PORT163CR */
3729 PORTCR(164, 0xe60520a4), /* PORT164CR */
3730
3731 PORTCR(192, 0xe60520c0), /* PORT192CR */
3732 PORTCR(193, 0xe60520c1), /* PORT193CR */
3733 PORTCR(194, 0xe60520c2), /* PORT194CR */
3734 PORTCR(195, 0xe60520c3), /* PORT195CR */
3735 PORTCR(196, 0xe60520c4), /* PORT196CR */
3736 PORTCR(197, 0xe60520c5), /* PORT197CR */
3737 PORTCR(198, 0xe60520c6), /* PORT198CR */
3738 PORTCR(199, 0xe60520c7), /* PORT199CR */
3739
3740 PORTCR(200, 0xe60520c8), /* PORT200CR */
3741 PORTCR(201, 0xe60520c9), /* PORT201CR */
3742 PORTCR(202, 0xe60520ca), /* PORT202CR */
3743 PORTCR(203, 0xe60520cb), /* PORT203CR */
3744 PORTCR(204, 0xe60520cc), /* PORT204CR */
3745 PORTCR(205, 0xe60520cd), /* PORT205CR */
3746 PORTCR(206, 0xe60520ce), /* PORT206CR */
3747 PORTCR(207, 0xe60520cf), /* PORT207CR */
3748 PORTCR(208, 0xe60520d0), /* PORT208CR */
3749 PORTCR(209, 0xe60520d1), /* PORT209CR */
3750
3751 PORTCR(210, 0xe60520d2), /* PORT210CR */
3752 PORTCR(211, 0xe60520d3), /* PORT211CR */
3753 PORTCR(212, 0xe60520d4), /* PORT212CR */
3754 PORTCR(213, 0xe60520d5), /* PORT213CR */
3755 PORTCR(214, 0xe60520d6), /* PORT214CR */
3756 PORTCR(215, 0xe60520d7), /* PORT215CR */
3757 PORTCR(216, 0xe60520d8), /* PORT216CR */
3758 PORTCR(217, 0xe60520d9), /* PORT217CR */
3759 PORTCR(218, 0xe60520da), /* PORT218CR */
3760 PORTCR(219, 0xe60520db), /* PORT219CR */
3761
3762 PORTCR(220, 0xe60520dc), /* PORT220CR */
3763 PORTCR(221, 0xe60520dd), /* PORT221CR */
3764 PORTCR(222, 0xe60520de), /* PORT222CR */
3765 PORTCR(223, 0xe60520df), /* PORT223CR */
3766 PORTCR(224, 0xe60530e0), /* PORT224CR */
3767 PORTCR(225, 0xe60530e1), /* PORT225CR */
3768 PORTCR(226, 0xe60530e2), /* PORT226CR */
3769 PORTCR(227, 0xe60530e3), /* PORT227CR */
3770 PORTCR(228, 0xe60530e4), /* PORT228CR */
3771 PORTCR(229, 0xe60530e5), /* PORT229CR */
3772
3773 PORTCR(230, 0xe60530e6), /* PORT230CR */
3774 PORTCR(231, 0xe60530e7), /* PORT231CR */
3775 PORTCR(232, 0xe60530e8), /* PORT232CR */
3776 PORTCR(233, 0xe60530e9), /* PORT233CR */
3777 PORTCR(234, 0xe60530ea), /* PORT234CR */
3778 PORTCR(235, 0xe60530eb), /* PORT235CR */
3779 PORTCR(236, 0xe60530ec), /* PORT236CR */
3780 PORTCR(237, 0xe60530ed), /* PORT237CR */
3781 PORTCR(238, 0xe60530ee), /* PORT238CR */
3782 PORTCR(239, 0xe60530ef), /* PORT239CR */
3783
3784 PORTCR(240, 0xe60530f0), /* PORT240CR */
3785 PORTCR(241, 0xe60530f1), /* PORT241CR */
3786 PORTCR(242, 0xe60530f2), /* PORT242CR */
3787 PORTCR(243, 0xe60530f3), /* PORT243CR */
3788 PORTCR(244, 0xe60530f4), /* PORT244CR */
3789 PORTCR(245, 0xe60530f5), /* PORT245CR */
3790 PORTCR(246, 0xe60530f6), /* PORT246CR */
3791 PORTCR(247, 0xe60530f7), /* PORT247CR */
3792 PORTCR(248, 0xe60530f8), /* PORT248CR */
3793 PORTCR(249, 0xe60530f9), /* PORT249CR */
3794
3795 PORTCR(250, 0xe60530fa), /* PORT250CR */
3796 PORTCR(251, 0xe60530fb), /* PORT251CR */
3797 PORTCR(252, 0xe60530fc), /* PORT252CR */
3798 PORTCR(253, 0xe60530fd), /* PORT253CR */
3799 PORTCR(254, 0xe60530fe), /* PORT254CR */
3800 PORTCR(255, 0xe60530ff), /* PORT255CR */
3801 PORTCR(256, 0xe6053100), /* PORT256CR */
3802 PORTCR(257, 0xe6053101), /* PORT257CR */
3803 PORTCR(258, 0xe6053102), /* PORT258CR */
3804 PORTCR(259, 0xe6053103), /* PORT259CR */
3805
3806 PORTCR(260, 0xe6053104), /* PORT260CR */
3807 PORTCR(261, 0xe6053105), /* PORT261CR */
3808 PORTCR(262, 0xe6053106), /* PORT262CR */
3809 PORTCR(263, 0xe6053107), /* PORT263CR */
3810 PORTCR(264, 0xe6053108), /* PORT264CR */
3811 PORTCR(265, 0xe6053109), /* PORT265CR */
3812 PORTCR(266, 0xe605310a), /* PORT266CR */
3813 PORTCR(267, 0xe605310b), /* PORT267CR */
3814 PORTCR(268, 0xe605310c), /* PORT268CR */
3815 PORTCR(269, 0xe605310d), /* PORT269CR */
3816
3817 PORTCR(270, 0xe605310e), /* PORT270CR */
3818 PORTCR(271, 0xe605310f), /* PORT271CR */
3819 PORTCR(272, 0xe6053110), /* PORT272CR */
3820 PORTCR(273, 0xe6053111), /* PORT273CR */
3821 PORTCR(274, 0xe6053112), /* PORT274CR */
3822 PORTCR(275, 0xe6053113), /* PORT275CR */
3823 PORTCR(276, 0xe6053114), /* PORT276CR */
3824 PORTCR(277, 0xe6053115), /* PORT277CR */
3825 PORTCR(278, 0xe6053116), /* PORT278CR */
3826 PORTCR(279, 0xe6053117), /* PORT279CR */
3827
3828 PORTCR(280, 0xe6053118), /* PORT280CR */
3829 PORTCR(281, 0xe6053119), /* PORT281CR */
3830 PORTCR(282, 0xe605311a), /* PORT282CR */
3831
3832 PORTCR(288, 0xe6052120), /* PORT288CR */
3833 PORTCR(289, 0xe6052121), /* PORT289CR */
3834
3835 PORTCR(290, 0xe6052122), /* PORT290CR */
3836 PORTCR(291, 0xe6052123), /* PORT291CR */
3837 PORTCR(292, 0xe6052124), /* PORT292CR */
3838 PORTCR(293, 0xe6052125), /* PORT293CR */
3839 PORTCR(294, 0xe6052126), /* PORT294CR */
3840 PORTCR(295, 0xe6052127), /* PORT295CR */
3841 PORTCR(296, 0xe6052128), /* PORT296CR */
3842 PORTCR(297, 0xe6052129), /* PORT297CR */
3843 PORTCR(298, 0xe605212a), /* PORT298CR */
3844 PORTCR(299, 0xe605212b), /* PORT299CR */
3845
3846 PORTCR(300, 0xe605212c), /* PORT300CR */
3847 PORTCR(301, 0xe605212d), /* PORT301CR */
3848 PORTCR(302, 0xe605212e), /* PORT302CR */
3849 PORTCR(303, 0xe605212f), /* PORT303CR */
3850 PORTCR(304, 0xe6052130), /* PORT304CR */
3851 PORTCR(305, 0xe6052131), /* PORT305CR */
3852 PORTCR(306, 0xe6052132), /* PORT306CR */
3853 PORTCR(307, 0xe6052133), /* PORT307CR */
3854 PORTCR(308, 0xe6052134), /* PORT308CR */
3855 PORTCR(309, 0xe6052135), /* PORT309CR */
3856
3857 { PINMUX_CFG_REG("MSEL2CR", 0xe605801c, 32, 1) {
3858 0, 0,
3859 0, 0,
3860 0, 0,
3861 0, 0,
3862 0, 0,
3863 0, 0,
3864 0, 0,
3865 0, 0,
3866 0, 0,
3867 0, 0,
3868 0, 0,
3869 0, 0,
3870 MSEL2CR_MSEL19_0, MSEL2CR_MSEL19_1,
3871 MSEL2CR_MSEL18_0, MSEL2CR_MSEL18_1,
3872 MSEL2CR_MSEL17_0, MSEL2CR_MSEL17_1,
3873 MSEL2CR_MSEL16_0, MSEL2CR_MSEL16_1,
3874 0, 0,
3875 MSEL2CR_MSEL14_0, MSEL2CR_MSEL14_1,
3876 MSEL2CR_MSEL13_0, MSEL2CR_MSEL13_1,
3877 MSEL2CR_MSEL12_0, MSEL2CR_MSEL12_1,
3878 MSEL2CR_MSEL11_0, MSEL2CR_MSEL11_1,
3879 MSEL2CR_MSEL10_0, MSEL2CR_MSEL10_1,
3880 MSEL2CR_MSEL9_0, MSEL2CR_MSEL9_1,
3881 MSEL2CR_MSEL8_0, MSEL2CR_MSEL8_1,
3882 MSEL2CR_MSEL7_0, MSEL2CR_MSEL7_1,
3883 MSEL2CR_MSEL6_0, MSEL2CR_MSEL6_1,
3884 MSEL2CR_MSEL5_0, MSEL2CR_MSEL5_1,
3885 MSEL2CR_MSEL4_0, MSEL2CR_MSEL4_1,
3886 MSEL2CR_MSEL3_0, MSEL2CR_MSEL3_1,
3887 MSEL2CR_MSEL2_0, MSEL2CR_MSEL2_1,
3888 MSEL2CR_MSEL1_0, MSEL2CR_MSEL1_1,
3889 MSEL2CR_MSEL0_0, MSEL2CR_MSEL0_1,
3890 }
3891 },
3892 { PINMUX_CFG_REG("MSEL3CR", 0xe6058020, 32, 1) {
3893 0, 0,
3894 0, 0,
3895 0, 0,
3896 MSEL3CR_MSEL28_0, MSEL3CR_MSEL28_1,
3897 0, 0,
3898 0, 0,
3899 0, 0,
3900 0, 0,
3901 0, 0,
3902 0, 0,
3903 0, 0,
3904 0, 0,
3905 0, 0,
3906 0, 0,
3907 0, 0,
3908 0, 0,
3909 MSEL3CR_MSEL15_0, MSEL3CR_MSEL15_1,
3910 0, 0,
3911 0, 0,
3912 0, 0,
3913 MSEL3CR_MSEL11_0, MSEL3CR_MSEL11_1,
3914 0, 0,
3915 MSEL3CR_MSEL9_0, MSEL3CR_MSEL9_1,
3916 0, 0,
3917 0, 0,
3918 MSEL3CR_MSEL6_0, MSEL3CR_MSEL6_1,
3919 0, 0,
3920 0, 0,
3921 0, 0,
3922 MSEL3CR_MSEL2_0, MSEL3CR_MSEL2_1,
3923 0, 0,
3924 0, 0,
3925 }
3926 },
3927 { PINMUX_CFG_REG("MSEL4CR", 0xe6058024, 32, 1) {
3928 0, 0,
3929 0, 0,
3930 MSEL4CR_MSEL29_0, MSEL4CR_MSEL29_1,
3931 0, 0,
3932 MSEL4CR_MSEL27_0, MSEL4CR_MSEL27_1,
3933 MSEL4CR_MSEL26_0, MSEL4CR_MSEL26_1,
3934 0, 0,
3935 0, 0,
3936 0, 0,
3937 MSEL4CR_MSEL22_0, MSEL4CR_MSEL22_1,
3938 MSEL4CR_MSEL21_0, MSEL4CR_MSEL21_1,
3939 MSEL4CR_MSEL20_0, MSEL4CR_MSEL20_1,
3940 MSEL4CR_MSEL19_0, MSEL4CR_MSEL19_1,
3941 0, 0,
3942 0, 0,
3943 0, 0,
3944 MSEL4CR_MSEL15_0, MSEL4CR_MSEL15_1,
3945 0, 0,
3946 MSEL4CR_MSEL13_0, MSEL4CR_MSEL13_1,
3947 MSEL4CR_MSEL12_0, MSEL4CR_MSEL12_1,
3948 MSEL4CR_MSEL11_0, MSEL4CR_MSEL11_1,
3949 MSEL4CR_MSEL10_0, MSEL4CR_MSEL10_1,
3950 MSEL4CR_MSEL9_0, MSEL4CR_MSEL9_1,
3951 MSEL4CR_MSEL8_0, MSEL4CR_MSEL8_1,
3952 MSEL4CR_MSEL7_0, MSEL4CR_MSEL7_1,
3953 0, 0,
3954 0, 0,
3955 MSEL4CR_MSEL4_0, MSEL4CR_MSEL4_1,
3956 0, 0,
3957 0, 0,
3958 MSEL4CR_MSEL1_0, MSEL4CR_MSEL1_1,
3959 0, 0,
3960 }
3961 },
3962 { },
3963};
3964
Laurent Pinchartcd3c1be2013-02-16 18:47:05 +0100[diff] [blame]3965static const struct pinmux_data_reg pinmux_data_regs[] = {
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]3966 { PINMUX_DATA_REG("PORTL031_000DR", 0xe6054000, 32) {
3967 PORT31_DATA, PORT30_DATA, PORT29_DATA, PORT28_DATA,
3968 PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA,
3969 PORT23_DATA, PORT22_DATA, PORT21_DATA, PORT20_DATA,
3970 PORT19_DATA, PORT18_DATA, PORT17_DATA, PORT16_DATA,
3971 PORT15_DATA, PORT14_DATA, PORT13_DATA, PORT12_DATA,
3972 PORT11_DATA, PORT10_DATA, PORT9_DATA, PORT8_DATA,
3973 PORT7_DATA, PORT6_DATA, PORT5_DATA, PORT4_DATA,
3974 PORT3_DATA, PORT2_DATA, PORT1_DATA, PORT0_DATA }
3975 },
3976 { PINMUX_DATA_REG("PORTD063_032DR", 0xe6055000, 32) {
3977 PORT63_DATA, PORT62_DATA, PORT61_DATA, PORT60_DATA,
3978 PORT59_DATA, PORT58_DATA, PORT57_DATA, PORT56_DATA,
3979 PORT55_DATA, PORT54_DATA, PORT53_DATA, PORT52_DATA,
3980 PORT51_DATA, PORT50_DATA, PORT49_DATA, PORT48_DATA,
3981 PORT47_DATA, PORT46_DATA, PORT45_DATA, PORT44_DATA,
3982 PORT43_DATA, PORT42_DATA, PORT41_DATA, PORT40_DATA,
3983 PORT39_DATA, PORT38_DATA, PORT37_DATA, PORT36_DATA,
3984 PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA }
3985 },
3986 { PINMUX_DATA_REG("PORTD095_064DR", 0xe6055004, 32) {
3987 PORT95_DATA, PORT94_DATA, PORT93_DATA, PORT92_DATA,
3988 PORT91_DATA, PORT90_DATA, PORT89_DATA, PORT88_DATA,
3989 PORT87_DATA, PORT86_DATA, PORT85_DATA, PORT84_DATA,
3990 PORT83_DATA, PORT82_DATA, PORT81_DATA, PORT80_DATA,
3991 PORT79_DATA, PORT78_DATA, PORT77_DATA, PORT76_DATA,
3992 PORT75_DATA, PORT74_DATA, PORT73_DATA, PORT72_DATA,
3993 PORT71_DATA, PORT70_DATA, PORT69_DATA, PORT68_DATA,
3994 PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA }
3995 },
3996 { PINMUX_DATA_REG("PORTR127_096DR", 0xe6056000, 32) {
3997 0, 0, 0, 0,
3998 0, 0, 0, 0,
3999 0, PORT118_DATA, PORT117_DATA, PORT116_DATA,
4000 PORT115_DATA, PORT114_DATA, PORT113_DATA, PORT112_DATA,
4001 PORT111_DATA, PORT110_DATA, PORT109_DATA, PORT108_DATA,
4002 PORT107_DATA, PORT106_DATA, PORT105_DATA, PORT104_DATA,
4003 PORT103_DATA, PORT102_DATA, PORT101_DATA, PORT100_DATA,
4004 PORT99_DATA, PORT98_DATA, PORT97_DATA, PORT96_DATA }
4005 },
4006 { PINMUX_DATA_REG("PORTR159_128DR", 0xe6056004, 32) {
4007 PORT159_DATA, PORT158_DATA, PORT157_DATA, PORT156_DATA,
4008 PORT155_DATA, PORT154_DATA, PORT153_DATA, PORT152_DATA,
4009 PORT151_DATA, PORT150_DATA, PORT149_DATA, PORT148_DATA,
4010 PORT147_DATA, PORT146_DATA, PORT145_DATA, PORT144_DATA,
4011 PORT143_DATA, PORT142_DATA, PORT141_DATA, PORT140_DATA,
4012 PORT139_DATA, PORT138_DATA, PORT137_DATA, PORT136_DATA,
4013 PORT135_DATA, PORT134_DATA, PORT133_DATA, PORT132_DATA,
4014 PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA }
4015 },
4016 { PINMUX_DATA_REG("PORTR191_160DR", 0xe6056008, 32) {
4017 0, 0, 0, 0,
4018 0, 0, 0, 0,
4019 0, 0, 0, 0,
4020 0, 0, 0, 0,
4021 0, 0, 0, 0,
4022 0, 0, 0, 0,
4023 0, 0, 0, PORT164_DATA,
4024 PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA }
4025 },
4026 { PINMUX_DATA_REG("PORTR223_192DR", 0xe605600C, 32) {
4027 PORT223_DATA, PORT222_DATA, PORT221_DATA, PORT220_DATA,
4028 PORT219_DATA, PORT218_DATA, PORT217_DATA, PORT216_DATA,
4029 PORT215_DATA, PORT214_DATA, PORT213_DATA, PORT212_DATA,
4030 PORT211_DATA, PORT210_DATA, PORT209_DATA, PORT208_DATA,
4031 PORT207_DATA, PORT206_DATA, PORT205_DATA, PORT204_DATA,
4032 PORT203_DATA, PORT202_DATA, PORT201_DATA, PORT200_DATA,
4033 PORT199_DATA, PORT198_DATA, PORT197_DATA, PORT196_DATA,
4034 PORT195_DATA, PORT194_DATA, PORT193_DATA, PORT192_DATA }
4035 },
4036 { PINMUX_DATA_REG("PORTU255_224DR", 0xe6057000, 32) {
4037 PORT255_DATA, PORT254_DATA, PORT253_DATA, PORT252_DATA,
4038 PORT251_DATA, PORT250_DATA, PORT249_DATA, PORT248_DATA,
4039 PORT247_DATA, PORT246_DATA, PORT245_DATA, PORT244_DATA,
4040 PORT243_DATA, PORT242_DATA, PORT241_DATA, PORT240_DATA,
4041 PORT239_DATA, PORT238_DATA, PORT237_DATA, PORT236_DATA,
4042 PORT235_DATA, PORT234_DATA, PORT233_DATA, PORT232_DATA,
4043 PORT231_DATA, PORT230_DATA, PORT229_DATA, PORT228_DATA,
4044 PORT227_DATA, PORT226_DATA, PORT225_DATA, PORT224_DATA }
4045 },
4046 { PINMUX_DATA_REG("PORTU287_256DR", 0xe6057004, 32) {
4047 0, 0, 0, 0,
4048 0, PORT282_DATA, PORT281_DATA, PORT280_DATA,
4049 PORT279_DATA, PORT278_DATA, PORT277_DATA, PORT276_DATA,
4050 PORT275_DATA, PORT274_DATA, PORT273_DATA, PORT272_DATA,
4051 PORT271_DATA, PORT270_DATA, PORT269_DATA, PORT268_DATA,
4052 PORT267_DATA, PORT266_DATA, PORT265_DATA, PORT264_DATA,
4053 PORT263_DATA, PORT262_DATA, PORT261_DATA, PORT260_DATA,
4054 PORT259_DATA, PORT258_DATA, PORT257_DATA, PORT256_DATA }
4055 },
4056 { PINMUX_DATA_REG("PORTR319_288DR", 0xe6056010, 32) {
4057 0, 0, 0, 0,
4058 0, 0, 0, 0,
4059 0, 0, PORT309_DATA, PORT308_DATA,
4060 PORT307_DATA, PORT306_DATA, PORT305_DATA, PORT304_DATA,
4061 PORT303_DATA, PORT302_DATA, PORT301_DATA, PORT300_DATA,
4062 PORT299_DATA, PORT298_DATA, PORT297_DATA, PORT296_DATA,
4063 PORT295_DATA, PORT294_DATA, PORT293_DATA, PORT292_DATA,
4064 PORT291_DATA, PORT290_DATA, PORT289_DATA, PORT288_DATA }
4065 },
4066 { },
4067};
4068
Magnus Damm341eb542013-02-26 12:01:09 +0900[diff] [blame]4069/* External IRQ pins mapped at IRQPIN_BASE */
4070#define EXT_IRQ16L(n) irq_pin(n)
4071#define EXT_IRQ16H(n) irq_pin(n)
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]4072
Laurent Pinchartcd3c1be2013-02-16 18:47:05 +0100[diff] [blame]4073static const struct pinmux_irq pinmux_irqs[] = {
Guennadi Liakhovetskib58e5fa2013-02-12 16:50:02 +0100[diff] [blame]4074 PINMUX_IRQ(EXT_IRQ16H(19), 9),
4075 PINMUX_IRQ(EXT_IRQ16L(1), 10),
4076 PINMUX_IRQ(EXT_IRQ16L(0), 11),
4077 PINMUX_IRQ(EXT_IRQ16H(18), 13),
4078 PINMUX_IRQ(EXT_IRQ16H(20), 14),
4079 PINMUX_IRQ(EXT_IRQ16H(21), 15),
4080 PINMUX_IRQ(EXT_IRQ16H(31), 26),
4081 PINMUX_IRQ(EXT_IRQ16H(30), 27),
4082 PINMUX_IRQ(EXT_IRQ16H(29), 28),
4083 PINMUX_IRQ(EXT_IRQ16H(22), 40),
4084 PINMUX_IRQ(EXT_IRQ16H(23), 53),
4085 PINMUX_IRQ(EXT_IRQ16L(10), 54),
4086 PINMUX_IRQ(EXT_IRQ16L(9), 56),
4087 PINMUX_IRQ(EXT_IRQ16H(26), 115),
4088 PINMUX_IRQ(EXT_IRQ16H(27), 116),
4089 PINMUX_IRQ(EXT_IRQ16H(28), 117),
4090 PINMUX_IRQ(EXT_IRQ16H(24), 118),
4091 PINMUX_IRQ(EXT_IRQ16L(6), 147),
4092 PINMUX_IRQ(EXT_IRQ16L(2), 149),
4093 PINMUX_IRQ(EXT_IRQ16L(7), 150),
4094 PINMUX_IRQ(EXT_IRQ16L(12), 156),
4095 PINMUX_IRQ(EXT_IRQ16L(4), 159),
4096 PINMUX_IRQ(EXT_IRQ16H(25), 164),
4097 PINMUX_IRQ(EXT_IRQ16L(8), 223),
4098 PINMUX_IRQ(EXT_IRQ16L(3), 224),
4099 PINMUX_IRQ(EXT_IRQ16L(5), 227),
4100 PINMUX_IRQ(EXT_IRQ16H(17), 234),
4101 PINMUX_IRQ(EXT_IRQ16L(11), 238),
4102 PINMUX_IRQ(EXT_IRQ16L(13), 239),
4103 PINMUX_IRQ(EXT_IRQ16H(16), 249),
4104 PINMUX_IRQ(EXT_IRQ16L(14), 251),
4105 PINMUX_IRQ(EXT_IRQ16L(9), 308),
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]4106};
4107
Laurent Pinchartea770ad2013-04-21 23:26:26 +0200[diff] [blame]4108/* -----------------------------------------------------------------------------
4109 * VCCQ MC0 regulator
4110 */
4111
4112static void sh73a0_vccq_mc0_endisable(struct regulator_dev *reg, bool enable)
4113{
4114 struct sh_pfc *pfc = reg->reg_data;
4115 void __iomem *addr = pfc->window[1].virt + 4;
4116 unsigned long flags;
4117 u32 value;
4118
4119 spin_lock_irqsave(&pfc->lock, flags);
4120
4121 value = ioread32(addr);
4122
4123 if (enable)
4124 value |= BIT(28);
4125 else
4126 value &= ~BIT(28);
4127
4128 iowrite32(value, addr);
4129
4130 spin_unlock_irqrestore(&pfc->lock, flags);
4131}
4132
4133static int sh73a0_vccq_mc0_enable(struct regulator_dev *reg)
4134{
4135 sh73a0_vccq_mc0_endisable(reg, true);
4136 return 0;
4137}
4138
4139static int sh73a0_vccq_mc0_disable(struct regulator_dev *reg)
4140{
4141 sh73a0_vccq_mc0_endisable(reg, false);
4142 return 0;
4143}
4144
4145static int sh73a0_vccq_mc0_is_enabled(struct regulator_dev *reg)
4146{
4147 struct sh_pfc *pfc = reg->reg_data;
4148 void __iomem *addr = pfc->window[1].virt + 4;
4149 unsigned long flags;
4150 u32 value;
4151
4152 spin_lock_irqsave(&pfc->lock, flags);
4153 value = ioread32(addr);
4154 spin_unlock_irqrestore(&pfc->lock, flags);
4155
4156 return !!(value & BIT(28));
4157}
4158
4159static int sh73a0_vccq_mc0_get_voltage(struct regulator_dev *reg)
4160{
4161 return 3300000;
4162}
4163
4164static struct regulator_ops sh73a0_vccq_mc0_ops = {
4165 .enable = sh73a0_vccq_mc0_enable,
4166 .disable = sh73a0_vccq_mc0_disable,
4167 .is_enabled = sh73a0_vccq_mc0_is_enabled,
4168 .get_voltage = sh73a0_vccq_mc0_get_voltage,
4169};
4170
4171static const struct regulator_desc sh73a0_vccq_mc0_desc = {
4172 .owner = THIS_MODULE,
4173 .name = "vccq_mc0",
4174 .type = REGULATOR_VOLTAGE,
4175 .ops = &sh73a0_vccq_mc0_ops,
4176};
4177
4178static struct regulator_consumer_supply sh73a0_vccq_mc0_consumers[] = {
4179 REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"),
4180};
4181
4182static const struct regulator_init_data sh73a0_vccq_mc0_init_data = {
4183 .constraints = {
4184 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
4185 },
4186 .num_consumer_supplies = ARRAY_SIZE(sh73a0_vccq_mc0_consumers),
4187 .consumer_supplies = sh73a0_vccq_mc0_consumers,
4188};
4189
4190/* -----------------------------------------------------------------------------
4191 * Pin bias
4192 */
4193
Laurent Pinchartb8238992013-03-13 01:31:23 +0100[diff] [blame]4194#define PORTnCR_PULMD_OFF (0 << 6)
4195#define PORTnCR_PULMD_DOWN (2 << 6)
4196#define PORTnCR_PULMD_UP (3 << 6)
4197#define PORTnCR_PULMD_MASK (3 << 6)
4198
4199static const unsigned int sh73a0_portcr_offsets[] = {
4200 0x00000000, 0x00001000, 0x00001000, 0x00002000, 0x00002000,
4201 0x00002000, 0x00002000, 0x00003000, 0x00003000, 0x00002000,
4202};
4203
4204static unsigned int sh73a0_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin)
4205{
4206 void __iomem *addr = pfc->window->virt
4207 + sh73a0_portcr_offsets[pin >> 5] + pin;
4208 u32 value = ioread8(addr) & PORTnCR_PULMD_MASK;
4209
4210 switch (value) {
4211 case PORTnCR_PULMD_UP:
4212 return PIN_CONFIG_BIAS_PULL_UP;
4213 case PORTnCR_PULMD_DOWN:
4214 return PIN_CONFIG_BIAS_PULL_DOWN;
4215 case PORTnCR_PULMD_OFF:
4216 default:
4217 return PIN_CONFIG_BIAS_DISABLE;
4218 }
4219}
4220
4221static void sh73a0_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
4222 unsigned int bias)
4223{
4224 void __iomem *addr = pfc->window->virt
4225 + sh73a0_portcr_offsets[pin >> 5] + pin;
4226 u32 value = ioread8(addr) & ~PORTnCR_PULMD_MASK;
4227
4228 switch (bias) {
4229 case PIN_CONFIG_BIAS_PULL_UP:
4230 value |= PORTnCR_PULMD_UP;
4231 break;
4232 case PIN_CONFIG_BIAS_PULL_DOWN:
4233 value |= PORTnCR_PULMD_DOWN;
4234 break;
4235 }
4236
4237 iowrite8(value, addr);
4238}
4239
Laurent Pinchartea770ad2013-04-21 23:26:26 +0200[diff] [blame]4240/* -----------------------------------------------------------------------------
4241 * SoC information
4242 */
4243
4244struct sh73a0_pinmux_data {
4245 struct regulator_dev *vccq_mc0;
4246};
4247
4248static int sh73a0_pinmux_soc_init(struct sh_pfc *pfc)
4249{
4250 struct sh73a0_pinmux_data *data;
4251 struct regulator_config cfg = { };
4252 int ret;
4253
4254 data = devm_kzalloc(pfc->dev, sizeof(*data), GFP_KERNEL);
4255 if (data == NULL)
4256 return -ENOMEM;
4257
4258 cfg.dev = pfc->dev;
4259 cfg.init_data = &sh73a0_vccq_mc0_init_data;
4260 cfg.driver_data = pfc;
4261
4262 data->vccq_mc0 = regulator_register(&sh73a0_vccq_mc0_desc, &cfg);
4263 if (IS_ERR(data->vccq_mc0)) {
4264 ret = PTR_ERR(data->vccq_mc0);
4265 dev_err(pfc->dev, "Failed to register VCCQ MC0 regulator: %d\n",
4266 ret);
4267 return ret;
4268 }
4269
4270 pfc->soc_data = data;
4271
4272 return 0;
4273}
4274
4275static void sh73a0_pinmux_soc_exit(struct sh_pfc *pfc)
4276{
4277 struct sh73a0_pinmux_data *data = pfc->soc_data;
4278
4279 regulator_unregister(data->vccq_mc0);
4280}
4281
Laurent Pinchartb8238992013-03-13 01:31:23 +0100[diff] [blame]4282static const struct sh_pfc_soc_operations sh73a0_pinmux_ops = {
Laurent Pinchartea770ad2013-04-21 23:26:26 +0200[diff] [blame]4283 .init = sh73a0_pinmux_soc_init,
4284 .exit = sh73a0_pinmux_soc_exit,
Laurent Pinchartb8238992013-03-13 01:31:23 +0100[diff] [blame]4285 .get_bias = sh73a0_pinmux_get_bias,
4286 .set_bias = sh73a0_pinmux_set_bias,
4287};
4288
Laurent Pinchartcd3c1be2013-02-16 18:47:05 +0100[diff] [blame]4289const struct sh_pfc_soc_info sh73a0_pinmux_info = {
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]4290 .name = "sh73a0_pfc",
Laurent Pinchartb8238992013-03-13 01:31:23 +0100[diff] [blame]4291 .ops = &sh73a0_pinmux_ops,
4292
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]4293 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]4294 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]4295 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
4296
Laurent Pincharta373ed02012-11-29 13:24:07 +0100[diff] [blame]4297 .pins = pinmux_pins,
4298 .nr_pins = ARRAY_SIZE(pinmux_pins),
Guennadi Liakhovetskib58e5fa2013-02-12 16:50:02 +0100[diff] [blame]4299 .ranges = pinmux_ranges,
4300 .nr_ranges = ARRAY_SIZE(pinmux_ranges),
Laurent Pinchartdf68a282013-01-03 13:07:05 +0100[diff] [blame]4301 .groups = pinmux_groups,
4302 .nr_groups = ARRAY_SIZE(pinmux_groups),
4303 .functions = pinmux_functions,
4304 .nr_functions = ARRAY_SIZE(pinmux_functions),
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]4305
Laurent Pincharta373ed02012-11-29 13:24:07 +0100[diff] [blame]4306 .func_gpios = pinmux_func_gpios,
4307 .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
Laurent Pinchartd7a7ca52012-11-28 17:51:00 +0100[diff] [blame]4308
Laurent Pinchart5d5166d2012-12-15 23:51:24 +0100[diff] [blame]4309 .cfg_regs = pinmux_config_regs,
4310 .data_regs = pinmux_data_regs,
4311
4312 .gpio_data = pinmux_data,
4313 .gpio_data_size = ARRAY_SIZE(pinmux_data),
4314
4315 .gpio_irq = pinmux_irqs,
4316 .gpio_irq_size = ARRAY_SIZE(pinmux_irqs),
4317};