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Erik Gillingc5f80062010-01-21 16:53:02 -08001/*
Peter De Schrijverc37c07d2011-12-14 17:03:17 +02002 * arch/arm/mach-tegra/common.c
Erik Gillingc5f80062010-01-21 16:53:02 -08003 *
4 * Copyright (C) 2010 Google, Inc.
5 *
6 * Author:
7 * Colin Cross <ccross@android.com>
8 *
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 */
19
20#include <linux/init.h>
21#include <linux/io.h>
Colin Cross4de3a8f2010-04-05 13:16:42 -070022#include <linux/clk.h>
23#include <linux/delay.h>
Peter De Schrijverc37c07d2011-12-14 17:03:17 +020024#include <linux/of_irq.h>
Erik Gillingc5f80062010-01-21 16:53:02 -080025
26#include <asm/hardware/cache-l2x0.h>
Peter De Schrijverc37c07d2011-12-14 17:03:17 +020027#include <asm/hardware/gic.h>
Erik Gillingc5f80062010-01-21 16:53:02 -080028
29#include <mach/iomap.h>
Peter De Schrijver65fe31d2012-02-10 01:47:49 +020030#include <mach/powergate.h>
Erik Gillingc5f80062010-01-21 16:53:02 -080031
32#include "board.h"
Colin Crossd8611962010-01-28 16:40:29 -080033#include "clock.h"
Colin Cross73625e32010-06-23 15:49:17 -070034#include "fuse.h"
Stephen Warrend3b8bdd2012-01-25 14:43:28 -070035#include "pmc.h"
Colin Crossd8611962010-01-28 16:40:29 -080036
Stephen Warren6d7d7b32012-01-06 10:43:22 +000037/*
38 * Storage for debug-macro.S's state.
39 *
40 * This must be in .data not .bss so that it gets initialized each time the
41 * kernel is loaded. The data is declared here rather than debug-macro.S so
42 * that multiple inclusions of debug-macro.S point at the same data.
43 */
44#define TEGRA_DEBUG_UART_OFFSET (TEGRA_DEBUG_UART_BASE & 0xFFFF)
45u32 tegra_uart_config[3] = {
46 /* Debug UART initialization required */
47 1,
48 /* Debug UART physical address */
49 (u32)(IO_APB_PHYS + TEGRA_DEBUG_UART_OFFSET),
50 /* Debug UART virtual address */
51 (u32)(IO_APB_VIRT + TEGRA_DEBUG_UART_OFFSET),
52};
Colin Crossd8611962010-01-28 16:40:29 -080053
Stephen Warren6cc04a42011-12-19 12:24:05 -070054#ifdef CONFIG_OF
Peter De Schrijverc37c07d2011-12-14 17:03:17 +020055static const struct of_device_id tegra_dt_irq_match[] __initconst = {
56 { .compatible = "arm,cortex-a9-gic", .data = gic_of_init },
57 { }
58};
59
60void __init tegra_dt_init_irq(void)
61{
62 tegra_init_irq();
63 of_irq_init(tegra_dt_irq_match);
64}
Stephen Warren6cc04a42011-12-19 12:24:05 -070065#endif
Peter De Schrijverc37c07d2011-12-14 17:03:17 +020066
Colin Cross699fe142010-08-23 18:37:25 -070067void tegra_assert_system_reset(char mode, const char *cmd)
68{
Peter De Schrijver9bfc3f02011-12-14 17:03:19 +020069 void __iomem *reset = IO_ADDRESS(TEGRA_PMC_BASE + 0);
Colin Cross699fe142010-08-23 18:37:25 -070070 u32 reg;
71
Simon Glass375b19c2011-02-17 08:13:57 -080072 reg = readl_relaxed(reset);
Peter De Schrijver9bfc3f02011-12-14 17:03:19 +020073 reg |= 0x10;
Simon Glass375b19c2011-02-17 08:13:57 -080074 writel_relaxed(reg, reset);
Colin Cross699fe142010-08-23 18:37:25 -070075}
76
Peter De Schrijverc37c07d2011-12-14 17:03:17 +020077#ifdef CONFIG_ARCH_TEGRA_2x_SOC
78static __initdata struct tegra_clk_init_table tegra20_clk_init_table[] = {
Colin Crossd8611962010-01-28 16:40:29 -080079 /* name parent rate enabled */
80 { "clk_m", NULL, 0, true },
81 { "pll_p", "clk_m", 216000000, true },
82 { "pll_p_out1", "pll_p", 28800000, true },
83 { "pll_p_out2", "pll_p", 48000000, true },
84 { "pll_p_out3", "pll_p", 72000000, true },
85 { "pll_p_out4", "pll_p", 108000000, true },
Stephen Warren60f975b2012-04-12 14:09:39 -060086 { "pll_c", "clk_m", 600000000, true },
87 { "pll_c_out1", "pll_c", 120000000, true },
88 { "sclk", "pll_c_out1", 120000000, true },
89 { "hclk", "sclk", 120000000, true },
Colin Crossd8611962010-01-28 16:40:29 -080090 { "pclk", "hclk", 54000000, true },
Colin Crosscd51d0e2011-02-21 17:05:36 -080091 { "csite", NULL, 0, true },
92 { "emc", NULL, 0, true },
93 { "cpu", NULL, 0, true },
Colin Crossd8611962010-01-28 16:40:29 -080094 { NULL, NULL, 0, 0},
95};
Peter De Schrijverc37c07d2011-12-14 17:03:17 +020096#endif
Erik Gillingc5f80062010-01-21 16:53:02 -080097
Peter De Schrijver01548672011-12-14 17:03:20 +020098static void __init tegra_init_cache(u32 tag_latency, u32 data_latency)
Erik Gillingc5f80062010-01-21 16:53:02 -080099{
100#ifdef CONFIG_CACHE_L2X0
101 void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000;
Peter De Schrijver01548672011-12-14 17:03:20 +0200102 u32 aux_ctrl, cache_type;
Erik Gillingc5f80062010-01-21 16:53:02 -0800103
Peter De Schrijver01548672011-12-14 17:03:20 +0200104 writel_relaxed(tag_latency, p + L2X0_TAG_LATENCY_CTRL);
105 writel_relaxed(data_latency, p + L2X0_DATA_LATENCY_CTRL);
Erik Gillingc5f80062010-01-21 16:53:02 -0800106
Peter De Schrijver01548672011-12-14 17:03:20 +0200107 cache_type = readl(p + L2X0_CACHE_TYPE);
108 aux_ctrl = (cache_type & 0x700) << (17-8);
109 aux_ctrl |= 0x6C000001;
110
111 l2x0_init(p, aux_ctrl, 0x8200c3fe);
Erik Gillingc5f80062010-01-21 16:53:02 -0800112#endif
Colin Cross4de3a8f2010-04-05 13:16:42 -0700113
Erik Gillingc5f80062010-01-21 16:53:02 -0800114}
115
Peter De Schrijverc37c07d2011-12-14 17:03:17 +0200116#ifdef CONFIG_ARCH_TEGRA_2x_SOC
117void __init tegra20_init_early(void)
Erik Gillingc5f80062010-01-21 16:53:02 -0800118{
Colin Cross73625e32010-06-23 15:49:17 -0700119 tegra_init_fuse();
Peter De Schrijverc37c07d2011-12-14 17:03:17 +0200120 tegra2_init_clocks();
121 tegra_clk_init_from_table(tegra20_clk_init_table);
Peter De Schrijver01548672011-12-14 17:03:20 +0200122 tegra_init_cache(0x331, 0x441);
Stephen Warrend3b8bdd2012-01-25 14:43:28 -0700123 tegra_pmc_init();
Peter De Schrijver65fe31d2012-02-10 01:47:49 +0200124 tegra_powergate_init();
Erik Gillingc5f80062010-01-21 16:53:02 -0800125}
Peter De Schrijverc37c07d2011-12-14 17:03:17 +0200126#endif
Peter De Schrijver44107d82011-12-14 17:03:25 +0200127#ifdef CONFIG_ARCH_TEGRA_3x_SOC
128void __init tegra30_init_early(void)
129{
Peter De Schrijvercec60062012-02-10 01:47:43 +0200130 tegra_init_fuse();
Peter De Schrijver7ff43ee2012-01-09 05:35:13 +0000131 tegra30_init_clocks();
Peter De Schrijver44107d82011-12-14 17:03:25 +0200132 tegra_init_cache(0x441, 0x551);
Stephen Warrend3b8bdd2012-01-25 14:43:28 -0700133 tegra_pmc_init();
Peter De Schrijver65fe31d2012-02-10 01:47:49 +0200134 tegra_powergate_init();
Peter De Schrijver44107d82011-12-14 17:03:25 +0200135}
136#endif