Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 1 | #include <dt-bindings/clock/tegra114-car.h> |
Stephen Warren | 3325f1b | 2013-02-12 17:25:15 -0700 | [diff] [blame] | 2 | #include <dt-bindings/gpio/tegra-gpio.h> |
Laxman Dewangan | 5fc6b0d | 2013-12-05 16:14:07 +0530 | [diff] [blame] | 3 | #include <dt-bindings/pinctrl/pinctrl-tegra.h> |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 4 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
Stephen Warren | 3325f1b | 2013-02-12 17:25:15 -0700 | [diff] [blame] | 5 | |
Stephen Warren | 1bd0bd4 | 2012-10-17 16:38:21 -0600 | [diff] [blame] | 6 | #include "skeleton.dtsi" |
Hiroshi Doyu | 18a4df7 | 2013-01-24 01:10:23 +0000 | [diff] [blame] | 7 | |
| 8 | / { |
| 9 | compatible = "nvidia,tegra114"; |
| 10 | interrupt-parent = <&gic>; |
| 11 | |
Laxman Dewangan | 0fb2209 | 2013-03-14 01:19:52 +0530 | [diff] [blame] | 12 | aliases { |
| 13 | serial0 = &uarta; |
| 14 | serial1 = &uartb; |
| 15 | serial2 = &uartc; |
| 16 | serial3 = &uartd; |
| 17 | }; |
| 18 | |
Mikko Perttunen | 65344b9 | 2013-12-19 16:59:28 +0100 | [diff] [blame^] | 19 | host1x@50000000 { |
| 20 | compatible = "nvidia,tegra114-host1x", "simple-bus"; |
| 21 | reg = <0x50000000 0x00028000>; |
| 22 | interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ |
| 23 | <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ |
| 24 | clocks = <&tegra_car TEGRA114_CLK_HOST1X>; |
| 25 | resets = <&tegra_car 28>; |
| 26 | reset-names = "host1x"; |
| 27 | |
| 28 | #address-cells = <1>; |
| 29 | #size-cells = <1>; |
| 30 | |
| 31 | ranges = <0x54000000 0x54000000 0x01000000>; |
| 32 | |
| 33 | dc@54200000 { |
| 34 | compatible = "nvidia,tegra114-dc", "nvidia,tegra20-dc"; |
| 35 | reg = <0x54200000 0x00040000>; |
| 36 | interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; |
| 37 | clocks = <&tegra_car TEGRA114_CLK_DISP1>, |
| 38 | <&tegra_car TEGRA114_CLK_PLL_P>; |
| 39 | clock-names = "dc", "parent"; |
| 40 | resets = <&tegra_car 27>; |
| 41 | reset-names = "dc"; |
| 42 | |
| 43 | rgb { |
| 44 | status = "disabled"; |
| 45 | }; |
| 46 | }; |
| 47 | |
| 48 | dc@54240000 { |
| 49 | compatible = "nvidia,tegra114-dc", "nvidia,tegra20-dc"; |
| 50 | reg = <0x54240000 0x00040000>; |
| 51 | interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; |
| 52 | clocks = <&tegra_car TEGRA114_CLK_DISP2>, |
| 53 | <&tegra_car TEGRA114_CLK_PLL_P>; |
| 54 | clock-names = "dc", "parent"; |
| 55 | resets = <&tegra_car 26>; |
| 56 | reset-names = "dc"; |
| 57 | |
| 58 | rgb { |
| 59 | status = "disabled"; |
| 60 | }; |
| 61 | }; |
| 62 | |
| 63 | hdmi@54280000 { |
| 64 | compatible = "nvidia,tegra114-hdmi"; |
| 65 | reg = <0x54280000 0x00040000>; |
| 66 | interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; |
| 67 | clocks = <&tegra_car TEGRA114_CLK_HDMI>, |
| 68 | <&tegra_car TEGRA114_CLK_PLL_D2_OUT0>; |
| 69 | clock-names = "hdmi", "parent"; |
| 70 | resets = <&tegra_car 51>; |
| 71 | reset-names = "hdmi"; |
| 72 | status = "disabled"; |
| 73 | }; |
| 74 | }; |
| 75 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 76 | gic: interrupt-controller@50041000 { |
Hiroshi Doyu | 18a4df7 | 2013-01-24 01:10:23 +0000 | [diff] [blame] | 77 | compatible = "arm,cortex-a15-gic"; |
| 78 | #interrupt-cells = <3>; |
| 79 | interrupt-controller; |
| 80 | reg = <0x50041000 0x1000>, |
| 81 | <0x50042000 0x1000>, |
| 82 | <0x50044000 0x2000>, |
| 83 | <0x50046000 0x2000>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 84 | interrupts = <GIC_PPI 9 |
| 85 | (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; |
Hiroshi Doyu | 18a4df7 | 2013-01-24 01:10:23 +0000 | [diff] [blame] | 86 | }; |
| 87 | |
| 88 | timer@60005000 { |
| 89 | compatible = "nvidia,tegra114-timer", "nvidia,tegra20-timer"; |
| 90 | reg = <0x60005000 0x400>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 91 | interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, |
| 92 | <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, |
| 93 | <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, |
| 94 | <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, |
| 95 | <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, |
| 96 | <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 97 | clocks = <&tegra_car TEGRA114_CLK_TIMER>; |
Hiroshi Doyu | 18a4df7 | 2013-01-24 01:10:23 +0000 | [diff] [blame] | 98 | }; |
| 99 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 100 | tegra_car: clock@60006000 { |
Peter De Schrijver | 672d889 | 2013-04-03 17:40:48 +0300 | [diff] [blame] | 101 | compatible = "nvidia,tegra114-car"; |
Hiroshi Doyu | 18a4df7 | 2013-01-24 01:10:23 +0000 | [diff] [blame] | 102 | reg = <0x60006000 0x1000>; |
| 103 | #clock-cells = <1>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 104 | #reset-cells = <1>; |
Hiroshi Doyu | 18a4df7 | 2013-01-24 01:10:23 +0000 | [diff] [blame] | 105 | }; |
| 106 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 107 | apbdma: dma@6000a000 { |
Laxman Dewangan | c5d9da4 | 2013-03-14 01:19:50 +0530 | [diff] [blame] | 108 | compatible = "nvidia,tegra114-apbdma"; |
| 109 | reg = <0x6000a000 0x1400>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 110 | interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, |
| 111 | <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, |
| 112 | <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, |
| 113 | <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, |
| 114 | <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, |
| 115 | <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, |
| 116 | <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, |
| 117 | <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, |
| 118 | <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, |
| 119 | <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, |
| 120 | <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, |
| 121 | <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, |
| 122 | <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, |
| 123 | <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, |
| 124 | <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, |
| 125 | <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, |
| 126 | <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, |
| 127 | <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, |
| 128 | <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, |
| 129 | <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, |
| 130 | <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, |
| 131 | <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, |
| 132 | <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, |
| 133 | <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, |
| 134 | <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, |
| 135 | <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, |
| 136 | <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, |
| 137 | <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, |
| 138 | <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, |
| 139 | <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, |
| 140 | <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, |
| 141 | <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 142 | clocks = <&tegra_car TEGRA114_CLK_APBDMA>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 143 | resets = <&tegra_car 34>; |
| 144 | reset-names = "dma"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 145 | #dma-cells = <1>; |
Laxman Dewangan | c5d9da4 | 2013-03-14 01:19:50 +0530 | [diff] [blame] | 146 | }; |
| 147 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 148 | ahb: ahb@6000c004 { |
Hiroshi Doyu | 0dfe42e | 2013-01-15 10:17:27 +0200 | [diff] [blame] | 149 | compatible = "nvidia,tegra114-ahb", "nvidia,tegra30-ahb"; |
| 150 | reg = <0x6000c004 0x14c>; |
| 151 | }; |
| 152 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 153 | gpio: gpio@6000d000 { |
Laxman Dewangan | b16f918 | 2013-01-29 18:26:18 +0530 | [diff] [blame] | 154 | compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio"; |
| 155 | reg = <0x6000d000 0x1000>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 156 | interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, |
| 157 | <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, |
| 158 | <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, |
| 159 | <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, |
| 160 | <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, |
| 161 | <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, |
| 162 | <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, |
| 163 | <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; |
Laxman Dewangan | b16f918 | 2013-01-29 18:26:18 +0530 | [diff] [blame] | 164 | #gpio-cells = <2>; |
| 165 | gpio-controller; |
| 166 | #interrupt-cells = <2>; |
| 167 | interrupt-controller; |
| 168 | }; |
| 169 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 170 | pinmux: pinmux@70000868 { |
Laxman Dewangan | 031b77a | 2013-01-29 18:26:20 +0530 | [diff] [blame] | 171 | compatible = "nvidia,tegra114-pinmux"; |
| 172 | reg = <0x70000868 0x148 /* Pad control registers */ |
| 173 | 0x70003000 0x40c>; /* Mux registers */ |
| 174 | }; |
| 175 | |
Laxman Dewangan | 0fb2209 | 2013-03-14 01:19:52 +0530 | [diff] [blame] | 176 | /* |
| 177 | * There are two serial driver i.e. 8250 based simple serial |
| 178 | * driver and APB DMA based serial driver for higher baudrate |
| 179 | * and performace. To enable the 8250 based driver, the compatible |
| 180 | * is "nvidia,tegra114-uart", "nvidia,tegra20-uart" and to enable |
| 181 | * the APB DMA based serial driver, the comptible is |
| 182 | * "nvidia,tegra114-hsuart", "nvidia,tegra30-hsuart". |
| 183 | */ |
| 184 | uarta: serial@70006000 { |
Hiroshi Doyu | 18a4df7 | 2013-01-24 01:10:23 +0000 | [diff] [blame] | 185 | compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; |
| 186 | reg = <0x70006000 0x40>; |
| 187 | reg-shift = <2>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 188 | interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 189 | clocks = <&tegra_car TEGRA114_CLK_UARTA>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 190 | resets = <&tegra_car 6>; |
| 191 | reset-names = "serial"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 192 | dmas = <&apbdma 8>, <&apbdma 8>; |
| 193 | dma-names = "rx", "tx"; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 194 | status = "disabled"; |
Hiroshi Doyu | 18a4df7 | 2013-01-24 01:10:23 +0000 | [diff] [blame] | 195 | }; |
| 196 | |
Laxman Dewangan | 0fb2209 | 2013-03-14 01:19:52 +0530 | [diff] [blame] | 197 | uartb: serial@70006040 { |
Hiroshi Doyu | 18a4df7 | 2013-01-24 01:10:23 +0000 | [diff] [blame] | 198 | compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; |
| 199 | reg = <0x70006040 0x40>; |
| 200 | reg-shift = <2>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 201 | interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 202 | clocks = <&tegra_car TEGRA114_CLK_UARTB>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 203 | resets = <&tegra_car 7>; |
| 204 | reset-names = "serial"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 205 | dmas = <&apbdma 9>, <&apbdma 9>; |
| 206 | dma-names = "rx", "tx"; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 207 | status = "disabled"; |
Hiroshi Doyu | 18a4df7 | 2013-01-24 01:10:23 +0000 | [diff] [blame] | 208 | }; |
| 209 | |
Laxman Dewangan | 0fb2209 | 2013-03-14 01:19:52 +0530 | [diff] [blame] | 210 | uartc: serial@70006200 { |
Hiroshi Doyu | 18a4df7 | 2013-01-24 01:10:23 +0000 | [diff] [blame] | 211 | compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; |
| 212 | reg = <0x70006200 0x100>; |
| 213 | reg-shift = <2>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 214 | interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 215 | clocks = <&tegra_car TEGRA114_CLK_UARTC>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 216 | resets = <&tegra_car 55>; |
| 217 | reset-names = "serial"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 218 | dmas = <&apbdma 10>, <&apbdma 10>; |
| 219 | dma-names = "rx", "tx"; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 220 | status = "disabled"; |
Hiroshi Doyu | 18a4df7 | 2013-01-24 01:10:23 +0000 | [diff] [blame] | 221 | }; |
| 222 | |
Laxman Dewangan | 0fb2209 | 2013-03-14 01:19:52 +0530 | [diff] [blame] | 223 | uartd: serial@70006300 { |
Hiroshi Doyu | 18a4df7 | 2013-01-24 01:10:23 +0000 | [diff] [blame] | 224 | compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; |
| 225 | reg = <0x70006300 0x100>; |
| 226 | reg-shift = <2>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 227 | interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 228 | clocks = <&tegra_car TEGRA114_CLK_UARTD>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 229 | resets = <&tegra_car 65>; |
| 230 | reset-names = "serial"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 231 | dmas = <&apbdma 19>, <&apbdma 19>; |
| 232 | dma-names = "rx", "tx"; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 233 | status = "disabled"; |
Hiroshi Doyu | 18a4df7 | 2013-01-24 01:10:23 +0000 | [diff] [blame] | 234 | }; |
| 235 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 236 | pwm: pwm@7000a000 { |
Andrew Chew | 6c716db | 2013-03-12 16:40:50 -0700 | [diff] [blame] | 237 | compatible = "nvidia,tegra114-pwm", "nvidia,tegra20-pwm"; |
| 238 | reg = <0x7000a000 0x100>; |
| 239 | #pwm-cells = <2>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 240 | clocks = <&tegra_car TEGRA114_CLK_PWM>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 241 | resets = <&tegra_car 17>; |
| 242 | reset-names = "pwm"; |
Andrew Chew | 6c716db | 2013-03-12 16:40:50 -0700 | [diff] [blame] | 243 | status = "disabled"; |
| 244 | }; |
| 245 | |
Laxman Dewangan | 3fc2f94 | 2013-03-14 01:19:51 +0530 | [diff] [blame] | 246 | i2c@7000c000 { |
| 247 | compatible = "nvidia,tegra114-i2c"; |
| 248 | reg = <0x7000c000 0x100>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 249 | interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; |
Laxman Dewangan | 3fc2f94 | 2013-03-14 01:19:51 +0530 | [diff] [blame] | 250 | #address-cells = <1>; |
| 251 | #size-cells = <0>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 252 | clocks = <&tegra_car TEGRA114_CLK_I2C1>; |
Laxman Dewangan | 3fc2f94 | 2013-03-14 01:19:51 +0530 | [diff] [blame] | 253 | clock-names = "div-clk"; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 254 | resets = <&tegra_car 12>; |
| 255 | reset-names = "i2c"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 256 | dmas = <&apbdma 21>, <&apbdma 21>; |
| 257 | dma-names = "rx", "tx"; |
Laxman Dewangan | 3fc2f94 | 2013-03-14 01:19:51 +0530 | [diff] [blame] | 258 | status = "disabled"; |
| 259 | }; |
| 260 | |
| 261 | i2c@7000c400 { |
| 262 | compatible = "nvidia,tegra114-i2c"; |
| 263 | reg = <0x7000c400 0x100>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 264 | interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; |
Laxman Dewangan | 3fc2f94 | 2013-03-14 01:19:51 +0530 | [diff] [blame] | 265 | #address-cells = <1>; |
| 266 | #size-cells = <0>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 267 | clocks = <&tegra_car TEGRA114_CLK_I2C2>; |
Laxman Dewangan | 3fc2f94 | 2013-03-14 01:19:51 +0530 | [diff] [blame] | 268 | clock-names = "div-clk"; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 269 | resets = <&tegra_car 54>; |
| 270 | reset-names = "i2c"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 271 | dmas = <&apbdma 22>, <&apbdma 22>; |
| 272 | dma-names = "rx", "tx"; |
Laxman Dewangan | 3fc2f94 | 2013-03-14 01:19:51 +0530 | [diff] [blame] | 273 | status = "disabled"; |
| 274 | }; |
| 275 | |
| 276 | i2c@7000c500 { |
| 277 | compatible = "nvidia,tegra114-i2c"; |
| 278 | reg = <0x7000c500 0x100>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 279 | interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; |
Laxman Dewangan | 3fc2f94 | 2013-03-14 01:19:51 +0530 | [diff] [blame] | 280 | #address-cells = <1>; |
| 281 | #size-cells = <0>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 282 | clocks = <&tegra_car TEGRA114_CLK_I2C3>; |
Laxman Dewangan | 3fc2f94 | 2013-03-14 01:19:51 +0530 | [diff] [blame] | 283 | clock-names = "div-clk"; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 284 | resets = <&tegra_car 67>; |
| 285 | reset-names = "i2c"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 286 | dmas = <&apbdma 23>, <&apbdma 23>; |
| 287 | dma-names = "rx", "tx"; |
Laxman Dewangan | 3fc2f94 | 2013-03-14 01:19:51 +0530 | [diff] [blame] | 288 | status = "disabled"; |
| 289 | }; |
| 290 | |
| 291 | i2c@7000c700 { |
| 292 | compatible = "nvidia,tegra114-i2c"; |
| 293 | reg = <0x7000c700 0x100>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 294 | interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; |
Laxman Dewangan | 3fc2f94 | 2013-03-14 01:19:51 +0530 | [diff] [blame] | 295 | #address-cells = <1>; |
| 296 | #size-cells = <0>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 297 | clocks = <&tegra_car TEGRA114_CLK_I2C4>; |
Laxman Dewangan | 3fc2f94 | 2013-03-14 01:19:51 +0530 | [diff] [blame] | 298 | clock-names = "div-clk"; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 299 | resets = <&tegra_car 103>; |
| 300 | reset-names = "i2c"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 301 | dmas = <&apbdma 26>, <&apbdma 26>; |
| 302 | dma-names = "rx", "tx"; |
Laxman Dewangan | 3fc2f94 | 2013-03-14 01:19:51 +0530 | [diff] [blame] | 303 | status = "disabled"; |
| 304 | }; |
| 305 | |
| 306 | i2c@7000d000 { |
| 307 | compatible = "nvidia,tegra114-i2c"; |
| 308 | reg = <0x7000d000 0x100>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 309 | interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; |
Laxman Dewangan | 3fc2f94 | 2013-03-14 01:19:51 +0530 | [diff] [blame] | 310 | #address-cells = <1>; |
| 311 | #size-cells = <0>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 312 | clocks = <&tegra_car TEGRA114_CLK_I2C5>; |
Laxman Dewangan | 3fc2f94 | 2013-03-14 01:19:51 +0530 | [diff] [blame] | 313 | clock-names = "div-clk"; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 314 | resets = <&tegra_car 47>; |
| 315 | reset-names = "i2c"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 316 | dmas = <&apbdma 24>, <&apbdma 24>; |
| 317 | dma-names = "rx", "tx"; |
Laxman Dewangan | 3fc2f94 | 2013-03-14 01:19:51 +0530 | [diff] [blame] | 318 | status = "disabled"; |
| 319 | }; |
| 320 | |
Laxman Dewangan | 6ea0297 | 2013-03-15 12:37:25 -0600 | [diff] [blame] | 321 | spi@7000d400 { |
| 322 | compatible = "nvidia,tegra114-spi"; |
| 323 | reg = <0x7000d400 0x200>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 324 | interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; |
Laxman Dewangan | 6ea0297 | 2013-03-15 12:37:25 -0600 | [diff] [blame] | 325 | #address-cells = <1>; |
| 326 | #size-cells = <0>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 327 | clocks = <&tegra_car TEGRA114_CLK_SBC1>; |
Laxman Dewangan | 6ea0297 | 2013-03-15 12:37:25 -0600 | [diff] [blame] | 328 | clock-names = "spi"; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 329 | resets = <&tegra_car 41>; |
| 330 | reset-names = "spi"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 331 | dmas = <&apbdma 15>, <&apbdma 15>; |
| 332 | dma-names = "rx", "tx"; |
Laxman Dewangan | 6ea0297 | 2013-03-15 12:37:25 -0600 | [diff] [blame] | 333 | status = "disabled"; |
| 334 | }; |
| 335 | |
| 336 | spi@7000d600 { |
| 337 | compatible = "nvidia,tegra114-spi"; |
| 338 | reg = <0x7000d600 0x200>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 339 | interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; |
Laxman Dewangan | 6ea0297 | 2013-03-15 12:37:25 -0600 | [diff] [blame] | 340 | #address-cells = <1>; |
| 341 | #size-cells = <0>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 342 | clocks = <&tegra_car TEGRA114_CLK_SBC2>; |
Laxman Dewangan | 6ea0297 | 2013-03-15 12:37:25 -0600 | [diff] [blame] | 343 | clock-names = "spi"; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 344 | resets = <&tegra_car 44>; |
| 345 | reset-names = "spi"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 346 | dmas = <&apbdma 16>, <&apbdma 16>; |
| 347 | dma-names = "rx", "tx"; |
Laxman Dewangan | 6ea0297 | 2013-03-15 12:37:25 -0600 | [diff] [blame] | 348 | status = "disabled"; |
| 349 | }; |
| 350 | |
| 351 | spi@7000d800 { |
| 352 | compatible = "nvidia,tegra114-spi"; |
| 353 | reg = <0x7000d800 0x200>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 354 | interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; |
Laxman Dewangan | 6ea0297 | 2013-03-15 12:37:25 -0600 | [diff] [blame] | 355 | #address-cells = <1>; |
| 356 | #size-cells = <0>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 357 | clocks = <&tegra_car TEGRA114_CLK_SBC3>; |
Laxman Dewangan | 6ea0297 | 2013-03-15 12:37:25 -0600 | [diff] [blame] | 358 | clock-names = "spi"; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 359 | resets = <&tegra_car 46>; |
| 360 | reset-names = "spi"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 361 | dmas = <&apbdma 17>, <&apbdma 17>; |
| 362 | dma-names = "rx", "tx"; |
Laxman Dewangan | 6ea0297 | 2013-03-15 12:37:25 -0600 | [diff] [blame] | 363 | status = "disabled"; |
| 364 | }; |
| 365 | |
| 366 | spi@7000da00 { |
| 367 | compatible = "nvidia,tegra114-spi"; |
| 368 | reg = <0x7000da00 0x200>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 369 | interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; |
Laxman Dewangan | 6ea0297 | 2013-03-15 12:37:25 -0600 | [diff] [blame] | 370 | #address-cells = <1>; |
| 371 | #size-cells = <0>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 372 | clocks = <&tegra_car TEGRA114_CLK_SBC4>; |
Laxman Dewangan | 6ea0297 | 2013-03-15 12:37:25 -0600 | [diff] [blame] | 373 | clock-names = "spi"; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 374 | resets = <&tegra_car 68>; |
| 375 | reset-names = "spi"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 376 | dmas = <&apbdma 18>, <&apbdma 18>; |
| 377 | dma-names = "rx", "tx"; |
Laxman Dewangan | 6ea0297 | 2013-03-15 12:37:25 -0600 | [diff] [blame] | 378 | status = "disabled"; |
| 379 | }; |
| 380 | |
| 381 | spi@7000dc00 { |
| 382 | compatible = "nvidia,tegra114-spi"; |
| 383 | reg = <0x7000dc00 0x200>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 384 | interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; |
Laxman Dewangan | 6ea0297 | 2013-03-15 12:37:25 -0600 | [diff] [blame] | 385 | #address-cells = <1>; |
| 386 | #size-cells = <0>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 387 | clocks = <&tegra_car TEGRA114_CLK_SBC5>; |
Laxman Dewangan | 6ea0297 | 2013-03-15 12:37:25 -0600 | [diff] [blame] | 388 | clock-names = "spi"; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 389 | resets = <&tegra_car 104>; |
| 390 | reset-names = "spi"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 391 | dmas = <&apbdma 27>, <&apbdma 27>; |
| 392 | dma-names = "rx", "tx"; |
Laxman Dewangan | 6ea0297 | 2013-03-15 12:37:25 -0600 | [diff] [blame] | 393 | status = "disabled"; |
| 394 | }; |
| 395 | |
| 396 | spi@7000de00 { |
| 397 | compatible = "nvidia,tegra114-spi"; |
| 398 | reg = <0x7000de00 0x200>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 399 | interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; |
Laxman Dewangan | 6ea0297 | 2013-03-15 12:37:25 -0600 | [diff] [blame] | 400 | #address-cells = <1>; |
| 401 | #size-cells = <0>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 402 | clocks = <&tegra_car TEGRA114_CLK_SBC6>; |
Laxman Dewangan | 6ea0297 | 2013-03-15 12:37:25 -0600 | [diff] [blame] | 403 | clock-names = "spi"; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 404 | resets = <&tegra_car 105>; |
| 405 | reset-names = "spi"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 406 | dmas = <&apbdma 28>, <&apbdma 28>; |
| 407 | dma-names = "rx", "tx"; |
Laxman Dewangan | 6ea0297 | 2013-03-15 12:37:25 -0600 | [diff] [blame] | 408 | status = "disabled"; |
| 409 | }; |
| 410 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 411 | rtc@7000e000 { |
Hiroshi Doyu | 18a4df7 | 2013-01-24 01:10:23 +0000 | [diff] [blame] | 412 | compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc"; |
| 413 | reg = <0x7000e000 0x100>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 414 | interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 415 | clocks = <&tegra_car TEGRA114_CLK_RTC>; |
Hiroshi Doyu | 18a4df7 | 2013-01-24 01:10:23 +0000 | [diff] [blame] | 416 | }; |
| 417 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 418 | kbc@7000e200 { |
Laxman Dewangan | cd467b7 | 2013-03-14 01:19:53 +0530 | [diff] [blame] | 419 | compatible = "nvidia,tegra114-kbc"; |
| 420 | reg = <0x7000e200 0x100>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 421 | interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 422 | clocks = <&tegra_car TEGRA114_CLK_KBC>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 423 | resets = <&tegra_car 36>; |
| 424 | reset-names = "kbc"; |
Laxman Dewangan | cd467b7 | 2013-03-14 01:19:53 +0530 | [diff] [blame] | 425 | status = "disabled"; |
| 426 | }; |
| 427 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 428 | pmc@7000e400 { |
Joseph Lo | 2b84e53 | 2013-02-26 16:27:43 +0000 | [diff] [blame] | 429 | compatible = "nvidia,tegra114-pmc"; |
Hiroshi Doyu | 18a4df7 | 2013-01-24 01:10:23 +0000 | [diff] [blame] | 430 | reg = <0x7000e400 0x400>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 431 | clocks = <&tegra_car TEGRA114_CLK_PCLK>, <&clk32k_in>; |
Joseph Lo | 7021d12 | 2013-04-03 19:31:27 +0800 | [diff] [blame] | 432 | clock-names = "pclk", "clk32k_in"; |
Hiroshi Doyu | 18a4df7 | 2013-01-24 01:10:23 +0000 | [diff] [blame] | 433 | }; |
| 434 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 435 | iommu@70019010 { |
Hiroshi Doyu | 2da1396 | 2013-01-15 10:17:28 +0200 | [diff] [blame] | 436 | compatible = "nvidia,tegra114-smmu", "nvidia,tegra30-smmu"; |
Hiroshi Doyu | 4cca9593 | 2013-10-30 17:17:48 -0600 | [diff] [blame] | 437 | reg = <0x70019010 0x02c |
| 438 | 0x700191f0 0x010 |
| 439 | 0x70019228 0x074>; |
Hiroshi Doyu | 2da1396 | 2013-01-15 10:17:28 +0200 | [diff] [blame] | 440 | nvidia,#asids = <4>; |
| 441 | dma-window = <0 0x40000000>; |
| 442 | nvidia,swgroups = <0x18659fe>; |
| 443 | nvidia,ahb = <&ahb>; |
| 444 | }; |
| 445 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 446 | ahub@70080000 { |
Stephen Warren | 15e5c64 | 2013-03-12 17:03:30 -0600 | [diff] [blame] | 447 | compatible = "nvidia,tegra114-ahub"; |
| 448 | reg = <0x70080000 0x200>, |
| 449 | <0x70080200 0x100>, |
| 450 | <0x70081000 0x200>; |
| 451 | interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; |
Stephen Warren | 15e5c64 | 2013-03-12 17:03:30 -0600 | [diff] [blame] | 452 | clocks = <&tegra_car TEGRA114_CLK_D_AUDIO>, |
Stephen Warren | 2bd541f | 2013-11-07 10:59:42 -0700 | [diff] [blame] | 453 | <&tegra_car TEGRA114_CLK_APBIF>; |
| 454 | clock-names = "d_audio", "apbif"; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 455 | resets = <&tegra_car 106>, /* d_audio */ |
| 456 | <&tegra_car 107>, /* apbif */ |
| 457 | <&tegra_car 30>, /* i2s0 */ |
| 458 | <&tegra_car 11>, /* i2s1 */ |
| 459 | <&tegra_car 18>, /* i2s2 */ |
| 460 | <&tegra_car 101>, /* i2s3 */ |
| 461 | <&tegra_car 102>, /* i2s4 */ |
| 462 | <&tegra_car 108>, /* dam0 */ |
| 463 | <&tegra_car 109>, /* dam1 */ |
| 464 | <&tegra_car 110>, /* dam2 */ |
| 465 | <&tegra_car 10>, /* spdif */ |
| 466 | <&tegra_car 153>, /* amx */ |
| 467 | <&tegra_car 154>; /* adx */ |
| 468 | reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2", |
| 469 | "i2s3", "i2s4", "dam0", "dam1", "dam2", |
| 470 | "spdif", "amx", "adx"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 471 | dmas = <&apbdma 1>, <&apbdma 1>, |
| 472 | <&apbdma 2>, <&apbdma 2>, |
| 473 | <&apbdma 3>, <&apbdma 3>, |
| 474 | <&apbdma 4>, <&apbdma 4>, |
| 475 | <&apbdma 6>, <&apbdma 6>, |
| 476 | <&apbdma 7>, <&apbdma 7>, |
| 477 | <&apbdma 12>, <&apbdma 12>, |
| 478 | <&apbdma 13>, <&apbdma 13>, |
| 479 | <&apbdma 14>, <&apbdma 14>, |
| 480 | <&apbdma 29>, <&apbdma 29>; |
| 481 | dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2", |
| 482 | "rx3", "tx3", "rx4", "tx4", "rx5", "tx5", |
| 483 | "rx6", "tx6", "rx7", "tx7", "rx8", "tx8", |
| 484 | "rx9", "tx9"; |
Stephen Warren | 15e5c64 | 2013-03-12 17:03:30 -0600 | [diff] [blame] | 485 | ranges; |
| 486 | #address-cells = <1>; |
| 487 | #size-cells = <1>; |
| 488 | |
| 489 | tegra_i2s0: i2s@70080300 { |
| 490 | compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s"; |
| 491 | reg = <0x70080300 0x100>; |
| 492 | nvidia,ahub-cif-ids = <4 4>; |
| 493 | clocks = <&tegra_car TEGRA114_CLK_I2S0>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 494 | resets = <&tegra_car 30>; |
| 495 | reset-names = "i2s"; |
Stephen Warren | 15e5c64 | 2013-03-12 17:03:30 -0600 | [diff] [blame] | 496 | status = "disabled"; |
| 497 | }; |
| 498 | |
| 499 | tegra_i2s1: i2s@70080400 { |
| 500 | compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s"; |
| 501 | reg = <0x70080400 0x100>; |
| 502 | nvidia,ahub-cif-ids = <5 5>; |
| 503 | clocks = <&tegra_car TEGRA114_CLK_I2S1>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 504 | resets = <&tegra_car 11>; |
| 505 | reset-names = "i2s"; |
Stephen Warren | 15e5c64 | 2013-03-12 17:03:30 -0600 | [diff] [blame] | 506 | status = "disabled"; |
| 507 | }; |
| 508 | |
| 509 | tegra_i2s2: i2s@70080500 { |
| 510 | compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s"; |
| 511 | reg = <0x70080500 0x100>; |
| 512 | nvidia,ahub-cif-ids = <6 6>; |
| 513 | clocks = <&tegra_car TEGRA114_CLK_I2S2>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 514 | resets = <&tegra_car 18>; |
| 515 | reset-names = "i2s"; |
Stephen Warren | 15e5c64 | 2013-03-12 17:03:30 -0600 | [diff] [blame] | 516 | status = "disabled"; |
| 517 | }; |
| 518 | |
| 519 | tegra_i2s3: i2s@70080600 { |
| 520 | compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s"; |
| 521 | reg = <0x70080600 0x100>; |
| 522 | nvidia,ahub-cif-ids = <7 7>; |
| 523 | clocks = <&tegra_car TEGRA114_CLK_I2S3>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 524 | resets = <&tegra_car 101>; |
| 525 | reset-names = "i2s"; |
Stephen Warren | 15e5c64 | 2013-03-12 17:03:30 -0600 | [diff] [blame] | 526 | status = "disabled"; |
| 527 | }; |
| 528 | |
| 529 | tegra_i2s4: i2s@70080700 { |
| 530 | compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s"; |
| 531 | reg = <0x70080700 0x100>; |
| 532 | nvidia,ahub-cif-ids = <8 8>; |
| 533 | clocks = <&tegra_car TEGRA114_CLK_I2S4>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 534 | resets = <&tegra_car 102>; |
| 535 | reset-names = "i2s"; |
Stephen Warren | 15e5c64 | 2013-03-12 17:03:30 -0600 | [diff] [blame] | 536 | status = "disabled"; |
| 537 | }; |
| 538 | }; |
| 539 | |
Thierry Reding | e3d04d1 | 2013-12-19 16:59:27 +0100 | [diff] [blame] | 540 | mipi: mipi@700e3000 { |
| 541 | compatible = "nvidia,tegra114-mipi"; |
| 542 | reg = <0x700e3000 0x100>; |
| 543 | clocks = <&tegra_car TEGRA114_CLK_MIPI_CAL>; |
| 544 | #nvidia,mipi-calibrate-cells = <1>; |
| 545 | }; |
| 546 | |
Pritesh Raithatha | 933d87a | 2013-02-20 13:35:14 -0500 | [diff] [blame] | 547 | sdhci@78000000 { |
| 548 | compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; |
| 549 | reg = <0x78000000 0x200>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 550 | interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 551 | clocks = <&tegra_car TEGRA114_CLK_SDMMC1>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 552 | resets = <&tegra_car 14>; |
| 553 | reset-names = "sdhci"; |
Pritesh Raithatha | 933d87a | 2013-02-20 13:35:14 -0500 | [diff] [blame] | 554 | status = "disable"; |
| 555 | }; |
| 556 | |
| 557 | sdhci@78000200 { |
| 558 | compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; |
| 559 | reg = <0x78000200 0x200>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 560 | interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 561 | clocks = <&tegra_car TEGRA114_CLK_SDMMC2>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 562 | resets = <&tegra_car 9>; |
| 563 | reset-names = "sdhci"; |
Pritesh Raithatha | 933d87a | 2013-02-20 13:35:14 -0500 | [diff] [blame] | 564 | status = "disable"; |
| 565 | }; |
| 566 | |
| 567 | sdhci@78000400 { |
| 568 | compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; |
| 569 | reg = <0x78000400 0x200>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 570 | interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 571 | clocks = <&tegra_car TEGRA114_CLK_SDMMC3>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 572 | resets = <&tegra_car 69>; |
| 573 | reset-names = "sdhci"; |
Pritesh Raithatha | 933d87a | 2013-02-20 13:35:14 -0500 | [diff] [blame] | 574 | status = "disable"; |
| 575 | }; |
| 576 | |
| 577 | sdhci@78000600 { |
| 578 | compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; |
| 579 | reg = <0x78000600 0x200>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 580 | interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 581 | clocks = <&tegra_car TEGRA114_CLK_SDMMC4>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 582 | resets = <&tegra_car 15>; |
| 583 | reset-names = "sdhci"; |
Pritesh Raithatha | 933d87a | 2013-02-20 13:35:14 -0500 | [diff] [blame] | 584 | status = "disable"; |
| 585 | }; |
| 586 | |
Mikko Perttunen | 328dc0e | 2013-08-01 18:00:18 +0300 | [diff] [blame] | 587 | usb@7d000000 { |
| 588 | compatible = "nvidia,tegra30-ehci", "usb-ehci"; |
| 589 | reg = <0x7d000000 0x4000>; |
| 590 | interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; |
| 591 | phy_type = "utmi"; |
| 592 | clocks = <&tegra_car TEGRA114_CLK_USBD>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 593 | resets = <&tegra_car 22>; |
| 594 | reset-names = "usb"; |
Mikko Perttunen | 328dc0e | 2013-08-01 18:00:18 +0300 | [diff] [blame] | 595 | nvidia,phy = <&phy1>; |
| 596 | status = "disabled"; |
| 597 | }; |
| 598 | |
| 599 | phy1: usb-phy@7d000000 { |
| 600 | compatible = "nvidia,tegra30-usb-phy"; |
| 601 | reg = <0x7d000000 0x4000 0x7d000000 0x4000>; |
| 602 | phy_type = "utmi"; |
| 603 | clocks = <&tegra_car TEGRA114_CLK_USBD>, |
| 604 | <&tegra_car TEGRA114_CLK_PLL_U>, |
| 605 | <&tegra_car TEGRA114_CLK_USBD>; |
| 606 | clock-names = "reg", "pll_u", "utmi-pads"; |
| 607 | nvidia,hssync-start-delay = <0>; |
| 608 | nvidia,idle-wait-delay = <17>; |
| 609 | nvidia,elastic-limit = <16>; |
| 610 | nvidia,term-range-adj = <6>; |
| 611 | nvidia,xcvr-setup = <9>; |
| 612 | nvidia,xcvr-lsfslew = <0>; |
| 613 | nvidia,xcvr-lsrslew = <3>; |
| 614 | nvidia,hssquelch-level = <2>; |
| 615 | nvidia,hsdiscon-level = <5>; |
| 616 | nvidia,xcvr-hsslew = <12>; |
| 617 | status = "disabled"; |
| 618 | }; |
| 619 | |
| 620 | usb@7d008000 { |
| 621 | compatible = "nvidia,tegra30-ehci", "usb-ehci"; |
| 622 | reg = <0x7d008000 0x4000>; |
| 623 | interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; |
| 624 | phy_type = "utmi"; |
| 625 | clocks = <&tegra_car TEGRA114_CLK_USB3>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 626 | resets = <&tegra_car 59>; |
| 627 | reset-names = "usb"; |
Mikko Perttunen | 328dc0e | 2013-08-01 18:00:18 +0300 | [diff] [blame] | 628 | nvidia,phy = <&phy3>; |
| 629 | status = "disabled"; |
| 630 | }; |
| 631 | |
| 632 | phy3: usb-phy@7d008000 { |
| 633 | compatible = "nvidia,tegra30-usb-phy"; |
| 634 | reg = <0x7d008000 0x4000 0x7d000000 0x4000>; |
| 635 | phy_type = "utmi"; |
| 636 | clocks = <&tegra_car TEGRA114_CLK_USB3>, |
| 637 | <&tegra_car TEGRA114_CLK_PLL_U>, |
| 638 | <&tegra_car TEGRA114_CLK_USBD>; |
| 639 | clock-names = "reg", "pll_u", "utmi-pads"; |
| 640 | nvidia,hssync-start-delay = <0>; |
| 641 | nvidia,idle-wait-delay = <17>; |
| 642 | nvidia,elastic-limit = <16>; |
| 643 | nvidia,term-range-adj = <6>; |
| 644 | nvidia,xcvr-setup = <9>; |
| 645 | nvidia,xcvr-lsfslew = <0>; |
| 646 | nvidia,xcvr-lsrslew = <3>; |
| 647 | nvidia,hssquelch-level = <2>; |
| 648 | nvidia,hsdiscon-level = <5>; |
| 649 | nvidia,xcvr-hsslew = <12>; |
| 650 | status = "disabled"; |
| 651 | }; |
| 652 | |
Hiroshi Doyu | 18a4df7 | 2013-01-24 01:10:23 +0000 | [diff] [blame] | 653 | cpus { |
| 654 | #address-cells = <1>; |
| 655 | #size-cells = <0>; |
| 656 | |
| 657 | cpu@0 { |
| 658 | device_type = "cpu"; |
| 659 | compatible = "arm,cortex-a15"; |
| 660 | reg = <0>; |
| 661 | }; |
| 662 | |
| 663 | cpu@1 { |
| 664 | device_type = "cpu"; |
| 665 | compatible = "arm,cortex-a15"; |
| 666 | reg = <1>; |
| 667 | }; |
| 668 | |
| 669 | cpu@2 { |
| 670 | device_type = "cpu"; |
| 671 | compatible = "arm,cortex-a15"; |
| 672 | reg = <2>; |
| 673 | }; |
| 674 | |
| 675 | cpu@3 { |
| 676 | device_type = "cpu"; |
| 677 | compatible = "arm,cortex-a15"; |
| 678 | reg = <3>; |
| 679 | }; |
| 680 | }; |
| 681 | |
| 682 | timer { |
| 683 | compatible = "arm,armv7-timer"; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 684 | interrupts = |
| 685 | <GIC_PPI 13 |
| 686 | (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
| 687 | <GIC_PPI 14 |
| 688 | (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
| 689 | <GIC_PPI 11 |
| 690 | (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
| 691 | <GIC_PPI 10 |
| 692 | (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; |
Hiroshi Doyu | 18a4df7 | 2013-01-24 01:10:23 +0000 | [diff] [blame] | 693 | }; |
| 694 | }; |