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Quinn Jensen52c543f2007-07-09 22:06:53 +01001/*
Anson Huangdf595742014-01-17 11:39:05 +08002 * Copyright 2004-2014 Freescale Semiconductor, Inc. All Rights Reserved.
Quinn Jensen52c543f2007-07-09 22:06:53 +01003 */
4
5/*
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __ASM_ARCH_MXC_COMMON_H__
12#define __ASM_ARCH_MXC_COMMON_H__
13
Robin Holt7b6d8642013-07-08 16:01:40 -070014#include <linux/reboot.h>
15
Shawn Guod48866f2013-10-16 19:52:00 +080016struct irq_data;
Sascha Hauer282b13d2008-09-09 10:19:40 +020017struct platform_device;
Shawn Guo009e63f2013-05-08 21:05:53 +080018struct pt_regs;
Sascha Hauer30c730f2009-02-16 14:36:49 +010019struct clk;
Gilles Chanteperdrix876292d2014-04-05 17:57:45 +020020struct device_node;
Shawn Guoa1f1c7e2011-09-06 15:08:40 +080021enum mxc_cpu_pwr_mode;
Steffen Trumtrare57e4ab2014-07-07 11:41:26 +020022struct of_device_id;
Sascha Hauer282b13d2008-09-09 10:19:40 +020023
Shawn Guo803648d2013-10-16 21:05:35 +080024void mx1_map_io(void);
25void mx21_map_io(void);
26void mx25_map_io(void);
27void mx27_map_io(void);
28void mx31_map_io(void);
29void mx35_map_io(void);
Shawn Guo803648d2013-10-16 21:05:35 +080030void imx1_init_early(void);
31void imx21_init_early(void);
32void imx25_init_early(void);
33void imx27_init_early(void);
34void imx31_init_early(void);
35void imx35_init_early(void);
Shawn Guo803648d2013-10-16 21:05:35 +080036void mxc_init_irq(void __iomem *);
Shawn Guofffa0512014-05-19 20:19:06 +080037void tzic_init_irq(void);
Shawn Guo803648d2013-10-16 21:05:35 +080038void mx1_init_irq(void);
39void mx21_init_irq(void);
40void mx25_init_irq(void);
41void mx27_init_irq(void);
42void mx31_init_irq(void);
43void mx35_init_irq(void);
Shawn Guo803648d2013-10-16 21:05:35 +080044void imx1_soc_init(void);
45void imx21_soc_init(void);
46void imx25_soc_init(void);
47void imx27_soc_init(void);
48void imx31_soc_init(void);
49void imx35_soc_init(void);
Shawn Guo803648d2013-10-16 21:05:35 +080050void epit_timer_init(void __iomem *base, int irq);
51void mxc_timer_init(void __iomem *, int);
52int mx1_clocks_init(unsigned long fref);
53int mx21_clocks_init(unsigned long lref, unsigned long fref);
54int mx25_clocks_init(void);
55int mx27_clocks_init(unsigned long fref);
56int mx31_clocks_init(unsigned long fref);
57int mx35_clocks_init(void);
Shawn Guo803648d2013-10-16 21:05:35 +080058int mx31_clocks_init_dt(void);
59struct platform_device *mxc_register_gpio(char *name, int id,
Shawn Guob78d8e52011-06-06 00:07:55 +080060 resource_size_t iobase, resource_size_t iosize, int irq, int irq_high);
Shawn Guo803648d2013-10-16 21:05:35 +080061void mxc_set_cpu_type(unsigned int type);
62void mxc_restart(enum reboot_mode, const char *);
63void mxc_arch_reset_init(void __iomem *);
64void mxc_arch_reset_init_dt(void);
Shawn Guo364b28a2014-05-20 15:09:42 +080065int mx51_revision(void);
Shawn Guo803648d2013-10-16 21:05:35 +080066int mx53_revision(void);
67void imx_set_aips(void __iomem *);
Steffen Trumtrare57e4ab2014-07-07 11:41:26 +020068void imx_aips_allow_unprivileged_access(const char *compat);
Shawn Guo803648d2013-10-16 21:05:35 +080069int mxc_device_init(void);
Shawn Guobfefdff2013-08-13 13:54:02 +080070void imx_set_soc_revision(unsigned int rev);
71unsigned int imx_get_soc_revision(void);
Shawn Guof1c6f312013-08-13 14:59:43 +080072void imx_init_revision_from_anatop(void);
Shawn Guoa2887542013-08-13 16:59:28 +080073struct device *imx_soc_device_init(void);
Shawn Guo73d2b4c2011-10-17 08:42:16 +080074
Shawn Guo41e7daf2011-09-28 17:16:06 +080075enum mxc_cpu_pwr_mode {
76 WAIT_CLOCKED, /* wfi only */
77 WAIT_UNCLOCKED, /* WAIT */
78 WAIT_UNCLOCKED_POWER_OFF, /* WAIT + SRPG */
79 STOP_POWER_ON, /* just STOP */
80 STOP_POWER_OFF, /* STOP + SRPG */
81};
82
Fabio Estevam3ac804e2012-02-02 20:02:32 -020083enum mx3_cpu_pwr_mode {
84 MX3_RUN,
85 MX3_WAIT,
86 MX3_DOZE,
87 MX3_SLEEP,
88};
89
Shawn Guo803648d2013-10-16 21:05:35 +080090void mx3_cpu_lp_set(enum mx3_cpu_pwr_mode mode);
91void imx_print_silicon_rev(const char *cpu, int srev);
Sascha Hauerb6de9432011-09-20 14:28:17 +020092
Shawn Guo803648d2013-10-16 21:05:35 +080093void imx_enable_cpu(int cpu, bool enable);
94void imx_set_cpu_jump(int cpu, void *jump_addr);
95u32 imx_get_cpu_arg(int cpu);
96void imx_set_cpu_arg(int cpu, u32 arg);
Shawn Guo69c31b72011-09-06 14:59:40 +080097#ifdef CONFIG_SMP
Shawn Guo803648d2013-10-16 21:05:35 +080098void v7_secondary_startup(void);
99void imx_scu_map_io(void);
100void imx_smp_prepare(void);
Shawn Guo13eed982011-09-06 15:05:25 +0800101#else
102static inline void imx_scu_map_io(void) {}
Shawn Guoa1f1c7e2011-09-06 15:08:40 +0800103static inline void imx_smp_prepare(void) {}
Shawn Guo69c31b72011-09-06 14:59:40 +0800104#endif
Shawn Guo803648d2013-10-16 21:05:35 +0800105void imx_src_init(void);
Shawn Guo803648d2013-10-16 21:05:35 +0800106void imx_gpc_init(void);
Anson Huang80c0ecd2014-06-23 16:42:44 +0800107void imx_gpc_pre_suspend(bool arm_power_off);
Shawn Guo803648d2013-10-16 21:05:35 +0800108void imx_gpc_post_resume(void);
109void imx_gpc_mask_all(void);
110void imx_gpc_restore_all(void);
Marc Zyngier65bb6882014-12-02 16:05:26 +0000111void imx_gpc_hwirq_mask(unsigned int hwirq);
112void imx_gpc_hwirq_unmask(unsigned int hwirq);
Shawn Guo803648d2013-10-16 21:05:35 +0800113void imx_anatop_init(void);
114void imx_anatop_pre_suspend(void);
115void imx_anatop_post_resume(void);
116int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode);
Anson Huangdfea9532014-06-23 16:42:43 +0800117void imx6q_set_int_mem_clk_lpm(bool enable);
Anson Huang751f7e92014-01-09 16:03:16 +0800118void imx6sl_set_wait_clk(bool enter);
Eric Miao46ec1b22011-12-21 22:38:23 +0800119
Shawn Guo803648d2013-10-16 21:05:35 +0800120void imx_cpu_die(unsigned int cpu);
121int imx_cpu_kill(unsigned int cpu);
Marc Zyngiere4f2d972011-09-08 13:15:22 +0100122
Shawn Guoc356bdb2014-02-26 19:48:33 +0800123#ifdef CONFIG_SUSPEND
124void v7_cpu_resume(void);
Anson Huangdf595742014-01-17 11:39:05 +0800125void imx6_suspend(void __iomem *ocram_vbase);
Shawn Guoc356bdb2014-02-26 19:48:33 +0800126#else
127static inline void v7_cpu_resume(void) {}
128static inline void imx6_suspend(void __iomem *ocram_vbase) {}
129#endif
130
Shawn Guo803648d2013-10-16 21:05:35 +0800131void imx6q_pm_init(void);
Anson Huangdf595742014-01-17 11:39:05 +0800132void imx6dl_pm_init(void);
133void imx6sl_pm_init(void);
Anson Huangff843d62014-06-20 13:20:54 +0800134void imx6sx_pm_init(void);
Shawn Guo9e8147b2013-09-25 23:09:36 +0800135void imx6q_pm_set_ccm_base(void __iomem *base);
Anson Huangdf595742014-01-17 11:39:05 +0800136
Shawn Guo28a9f3b2014-02-18 10:35:05 +0800137#ifdef CONFIG_PM
Shawn Guo36b66c32014-05-20 14:55:15 +0800138void imx51_pm_init(void);
139void imx53_pm_init(void);
Shawn Guo4ef5e382014-05-20 13:41:36 +0800140void imx5_pm_set_ccm_base(void __iomem *base);
Eric Miao46ec1b22011-12-21 22:38:23 +0800141#else
Shawn Guo36b66c32014-05-20 14:55:15 +0800142static inline void imx51_pm_init(void) {}
143static inline void imx53_pm_init(void) {}
Shawn Guo4ef5e382014-05-20 13:41:36 +0800144static inline void imx5_pm_set_ccm_base(void __iomem *base) {}
Eric Miao46ec1b22011-12-21 22:38:23 +0800145#endif
146
Shawn Guo8321b752012-04-26 11:42:34 +0800147#ifdef CONFIG_NEON
Shawn Guo803648d2013-10-16 21:05:35 +0800148int mx51_neon_fixup(void);
Shawn Guo8321b752012-04-26 11:42:34 +0800149#else
150static inline int mx51_neon_fixup(void) { return 0; }
151#endif
152
Shawn Guoe6a07562013-07-08 21:45:20 +0800153#ifdef CONFIG_CACHE_L2X0
Shawn Guo803648d2013-10-16 21:05:35 +0800154void imx_init_l2cache(void);
Shawn Guoe6a07562013-07-08 21:45:20 +0800155#else
156static inline void imx_init_l2cache(void) {}
157#endif
158
Marc Zyngiere4f2d972011-09-08 13:15:22 +0100159extern struct smp_operations imx_smp_ops;
160
Quinn Jensen52c543f2007-07-09 22:06:53 +0100161#endif