blob: e443f2c1dfd1685ab0bcf88be945e898a5373a55 [file] [log] [blame]
Alan Coxda9bb1d2006-01-18 17:44:13 -08001#
2# EDAC Kconfig
Doug Thompson4577ca52009-04-02 16:58:43 -07003# Copyright (c) 2008 Doug Thompson www.softwarebitmaker.com
Alan Coxda9bb1d2006-01-18 17:44:13 -08004# Licensed and distributed under the GPL
5#
Alan Coxda9bb1d2006-01-18 17:44:13 -08006
Borislav Petkov544516632012-12-18 22:02:56 +01007config EDAC_SUPPORT
8 bool
9
Jan Engelhardt751cb5e2007-07-15 23:39:27 -070010menuconfig EDAC
GeunSik Lime24aca62009-06-17 16:28:02 -070011 bool "EDAC (Error Detection And Correction) reporting"
Martin Schwidefskye25df122007-05-10 15:45:57 +020012 depends on HAS_IOMEM
Ralf Baechlef65aad42012-10-17 00:39:09 +020013 depends on X86 || PPC || TILE || ARM || EDAC_SUPPORT
Alan Coxda9bb1d2006-01-18 17:44:13 -080014 help
15 EDAC is designed to report errors in the core system.
16 These are low-level errors that are reported in the CPU or
Douglas Thompson8cb2a392007-07-19 01:50:12 -070017 supporting chipset or other subsystems:
18 memory errors, cache errors, PCI errors, thermal throttling, etc..
19 If unsure, select 'Y'.
Alan Coxda9bb1d2006-01-18 17:44:13 -080020
Tim Small57c432b2006-03-09 17:33:50 -080021 If this code is reporting problems on your system, please
22 see the EDAC project web pages for more information at:
23
24 <http://bluesmoke.sourceforge.net/>
25
26 and:
27
28 <http://buttersideup.com/edacwiki>
29
30 There is also a mailing list for the EDAC project, which can
31 be found via the sourceforge page.
32
Jan Engelhardt751cb5e2007-07-15 23:39:27 -070033if EDAC
Alan Coxda9bb1d2006-01-18 17:44:13 -080034
Mauro Carvalho Chehab19974712012-03-21 17:06:53 -030035config EDAC_LEGACY_SYSFS
36 bool "EDAC legacy sysfs"
37 default y
38 help
39 Enable the compatibility sysfs nodes.
40 Use 'Y' if your edac utilities aren't ported to work with the newer
41 structures.
42
Alan Coxda9bb1d2006-01-18 17:44:13 -080043config EDAC_DEBUG
44 bool "Debugging"
Alan Coxda9bb1d2006-01-18 17:44:13 -080045 help
Borislav Petkov37929872012-09-10 16:50:54 +020046 This turns on debugging information for the entire EDAC subsystem.
47 You do so by inserting edac_module with "edac_debug_level=x." Valid
48 levels are 0-4 (from low to high) and by default it is set to 2.
49 Usually you should select 'N' here.
Alan Coxda9bb1d2006-01-18 17:44:13 -080050
Borislav Petkov9cdeb402010-09-02 18:33:24 +020051config EDAC_DECODE_MCE
Borislav Petkov0d18b2e2009-10-02 15:31:48 +020052 tristate "Decode MCEs in human-readable form (only on AMD for now)"
Borislav Petkov168eb342011-08-10 09:43:30 -030053 depends on CPU_SUP_AMD && X86_MCE_AMD
Borislav Petkov0d18b2e2009-10-02 15:31:48 +020054 default y
55 ---help---
56 Enable this option if you want to decode Machine Check Exceptions
Lucas De Marchi25985ed2011-03-30 22:57:33 -030057 occurring on your machine in human-readable form.
Borislav Petkov0d18b2e2009-10-02 15:31:48 +020058
59 You should definitely say Y here in case you want to decode MCEs
60 which occur really early upon boot, before the module infrastructure
61 has been initialized.
62
Borislav Petkov9cdeb402010-09-02 18:33:24 +020063config EDAC_MCE_INJ
64 tristate "Simple MCE injection interface over /sysfs"
65 depends on EDAC_DECODE_MCE
66 default n
67 help
68 This is a simple interface to inject MCEs over /sysfs and test
69 the MCE decoding code in EDAC.
70
71 This is currently AMD-only.
72
Alan Coxda9bb1d2006-01-18 17:44:13 -080073config EDAC_MM_EDAC
74 tristate "Main Memory EDAC (Error Detection And Correction) reporting"
Alan Coxda9bb1d2006-01-18 17:44:13 -080075 help
76 Some systems are able to detect and correct errors in main
77 memory. EDAC can report statistics on memory error
78 detection and correction (EDAC - or commonly referred to ECC
79 errors). EDAC will also try to decode where these errors
80 occurred so that a particular failing memory module can be
81 replaced. If unsure, select 'Y'.
82
Mauro Carvalho Chehab77c5f5d2013-02-15 06:11:57 -030083config EDAC_GHES
84 bool "Output ACPI APEI/GHES BIOS detected errors via EDAC"
85 depends on ACPI_APEI_GHES && (EDAC_MM_EDAC=y)
86 default y
87 help
88 Not all machines support hardware-driven error report. Some of those
89 provide a BIOS-driven error report mechanism via ACPI, using the
90 APEI/GHES driver. By enabling this option, the error reports provided
91 by GHES are sent to userspace via the EDAC API.
92
93 When this option is enabled, it will disable the hardware-driven
94 mechanisms, if a GHES BIOS is detected, entering into the
95 "Firmware First" mode.
96
97 It should be noticed that keeping both GHES and a hardware-driven
98 error mechanism won't work well, as BIOS will race with OS, while
99 reading the error registers. So, if you want to not use "Firmware
100 first" GHES error mechanism, you should disable GHES either at
101 compilation time or by passing "ghes.disable=1" Kernel parameter
102 at boot time.
103
104 In doubt, say 'Y'.
105
Doug Thompson7d6034d2009-04-27 20:01:01 +0200106config EDAC_AMD64
Borislav Petkov027dbd62010-10-13 22:12:15 +0200107 tristate "AMD64 (Opteron, Athlon64) K8, F10h"
108 depends on EDAC_MM_EDAC && AMD_NB && X86_64 && EDAC_DECODE_MCE
Doug Thompson7d6034d2009-04-27 20:01:01 +0200109 help
Borislav Petkov027dbd62010-10-13 22:12:15 +0200110 Support for error detection and correction of DRAM ECC errors on
111 the AMD64 families of memory controllers (K8 and F10h)
Doug Thompson7d6034d2009-04-27 20:01:01 +0200112
113config EDAC_AMD64_ERROR_INJECTION
Borislav Petkov9cdeb402010-09-02 18:33:24 +0200114 bool "Sysfs HW Error injection facilities"
Doug Thompson7d6034d2009-04-27 20:01:01 +0200115 depends on EDAC_AMD64
116 help
117 Recent Opterons (Family 10h and later) provide for Memory Error
118 Injection into the ECC detection circuits. The amd64_edac module
119 allows the operator/user to inject Uncorrectable and Correctable
120 errors into DRAM.
121
122 When enabled, in each of the respective memory controller directories
123 (/sys/devices/system/edac/mc/mcX), there are 3 input files:
124
125 - inject_section (0..3, 16-byte section of 64-byte cacheline),
126 - inject_word (0..8, 16-bit word of 16-byte section),
127 - inject_ecc_vector (hex ecc vector: select bits of inject word)
128
129 In addition, there are two control files, inject_read and inject_write,
130 which trigger the DRAM ECC Read and Write respectively.
Alan Coxda9bb1d2006-01-18 17:44:13 -0800131
132config EDAC_AMD76X
133 tristate "AMD 76x (760, 762, 768)"
Dave Jones90cbc452006-02-03 03:04:11 -0800134 depends on EDAC_MM_EDAC && PCI && X86_32
Alan Coxda9bb1d2006-01-18 17:44:13 -0800135 help
136 Support for error detection and correction on the AMD 76x
137 series of chipsets used with the Athlon processor.
138
139config EDAC_E7XXX
140 tristate "Intel e7xxx (e7205, e7500, e7501, e7505)"
Dave Peterson39f1d8d2006-03-26 01:38:50 -0800141 depends on EDAC_MM_EDAC && PCI && X86_32
Alan Coxda9bb1d2006-01-18 17:44:13 -0800142 help
143 Support for error detection and correction on the Intel
144 E7205, E7500, E7501 and E7505 server chipsets.
145
146config EDAC_E752X
Andrei Konovalov5135b792008-04-29 01:03:13 -0700147 tristate "Intel e752x (e7520, e7525, e7320) and 3100"
Randy Dunlapda960a62006-03-31 02:30:34 -0800148 depends on EDAC_MM_EDAC && PCI && X86 && HOTPLUG
Alan Coxda9bb1d2006-01-18 17:44:13 -0800149 help
150 Support for error detection and correction on the Intel
151 E7520, E7525, E7320 server chipsets.
152
Tim Small5a2c6752007-07-19 01:49:42 -0700153config EDAC_I82443BXGX
154 tristate "Intel 82443BX/GX (440BX/GX)"
155 depends on EDAC_MM_EDAC && PCI && X86_32
Andrew Morton28f96eea2007-07-19 01:49:45 -0700156 depends on BROKEN
Tim Small5a2c6752007-07-19 01:49:42 -0700157 help
158 Support for error detection and correction on the Intel
159 82443BX/GX memory controllers (440BX/GX chipsets).
160
Alan Coxda9bb1d2006-01-18 17:44:13 -0800161config EDAC_I82875P
162 tristate "Intel 82875p (D82875P, E7210)"
Dave Peterson39f1d8d2006-03-26 01:38:50 -0800163 depends on EDAC_MM_EDAC && PCI && X86_32
Alan Coxda9bb1d2006-01-18 17:44:13 -0800164 help
165 Support for error detection and correction on the Intel
166 DP82785P and E7210 server chipsets.
167
Ranganathan Desikan420390f2007-07-19 01:50:31 -0700168config EDAC_I82975X
169 tristate "Intel 82975x (D82975x)"
170 depends on EDAC_MM_EDAC && PCI && X86
171 help
172 Support for error detection and correction on the Intel
173 DP82975x server chipsets.
174
Jason Uhlenkott535c6a52007-07-19 01:49:48 -0700175config EDAC_I3000
176 tristate "Intel 3000/3010"
Jason Uhlenkottf5c04542008-02-07 00:15:01 -0800177 depends on EDAC_MM_EDAC && PCI && X86
Jason Uhlenkott535c6a52007-07-19 01:49:48 -0700178 help
179 Support for error detection and correction on the Intel
180 3000 and 3010 server chipsets.
181
Jason Uhlenkottdd8ef1d2009-09-23 15:57:27 -0700182config EDAC_I3200
183 tristate "Intel 3200"
Kees Cook053417a2013-01-16 18:53:31 -0800184 depends on EDAC_MM_EDAC && PCI && X86
Jason Uhlenkottdd8ef1d2009-09-23 15:57:27 -0700185 help
186 Support for error detection and correction on the Intel
187 3200 and 3210 server chipsets.
188
Hitoshi Mitakedf8bc08c2008-10-29 14:00:50 -0700189config EDAC_X38
190 tristate "Intel X38"
191 depends on EDAC_MM_EDAC && PCI && X86
192 help
193 Support for error detection and correction on the Intel
194 X38 server chipsets.
195
Mauro Carvalho Chehab920c8df2009-01-06 14:43:00 -0800196config EDAC_I5400
197 tristate "Intel 5400 (Seaburg) chipsets"
198 depends on EDAC_MM_EDAC && PCI && X86
199 help
200 Support for error detection and correction the Intel
201 i5400 MCH chipset (Seaburg).
202
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300203config EDAC_I7CORE
204 tristate "Intel i7 Core (Nehalem) processors"
Borislav Petkov168eb342011-08-10 09:43:30 -0300205 depends on EDAC_MM_EDAC && PCI && X86 && X86_MCE_INTEL
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300206 help
207 Support for error detection and correction the Intel
Mauro Carvalho Chehab696e4092009-07-23 06:57:45 -0300208 i7 Core (Nehalem) Integrated Memory Controller that exists on
209 newer processors like i7 Core, i7 Core Extreme, Xeon 35xx
210 and Xeon 55xx processors.
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300211
Alan Coxda9bb1d2006-01-18 17:44:13 -0800212config EDAC_I82860
213 tristate "Intel 82860"
Dave Peterson39f1d8d2006-03-26 01:38:50 -0800214 depends on EDAC_MM_EDAC && PCI && X86_32
Alan Coxda9bb1d2006-01-18 17:44:13 -0800215 help
216 Support for error detection and correction on the Intel
217 82860 chipset.
218
219config EDAC_R82600
220 tristate "Radisys 82600 embedded chipset"
Dave Peterson39f1d8d2006-03-26 01:38:50 -0800221 depends on EDAC_MM_EDAC && PCI && X86_32
Alan Coxda9bb1d2006-01-18 17:44:13 -0800222 help
223 Support for error detection and correction on the Radisys
224 82600 embedded chipset.
225
Eric Wolleseneb607052007-07-19 01:49:39 -0700226config EDAC_I5000
227 tristate "Intel Greencreek/Blackford chipset"
228 depends on EDAC_MM_EDAC && X86 && PCI
229 help
230 Support for error detection and correction the Intel
231 Greekcreek/Blackford chipsets.
232
Arthur Jones8f421c592008-07-25 01:49:04 -0700233config EDAC_I5100
234 tristate "Intel San Clemente MCH"
235 depends on EDAC_MM_EDAC && X86 && PCI
236 help
237 Support for error detection and correction the Intel
238 San Clemente MCH.
239
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300240config EDAC_I7300
241 tristate "Intel Clarksboro MCH"
242 depends on EDAC_MM_EDAC && X86 && PCI
243 help
244 Support for error detection and correction the Intel
245 Clarksboro MCH (Intel 7300 chipset).
246
Mauro Carvalho Chehab3d78c9a2011-10-20 19:33:46 -0200247config EDAC_SBRIDGE
248 tristate "Intel Sandy-Bridge Integrated MC"
Hui Wang22a5c272012-02-06 04:10:59 -0300249 depends on EDAC_MM_EDAC && PCI && X86_64 && X86_MCE_INTEL
Kees Cook053417a2013-01-16 18:53:31 -0800250 depends on PCI_MMCONFIG
Mauro Carvalho Chehab3d78c9a2011-10-20 19:33:46 -0200251 help
252 Support for error detection and correction the Intel
253 Sandy Bridge Integrated Memory Controller.
254
Dave Jianga9a753d2008-02-07 00:14:55 -0800255config EDAC_MPC85XX
Ira W. Snyderb4846252009-09-23 15:57:25 -0700256 tristate "Freescale MPC83xx / MPC85xx"
Anton Vorontsov1cd85212010-07-20 13:24:27 -0700257 depends on EDAC_MM_EDAC && FSL_SOC && (PPC_83xx || PPC_85xx)
Dave Jianga9a753d2008-02-07 00:14:55 -0800258 help
259 Support for error detection and correction on the Freescale
Ira W. Snyderb4846252009-09-23 15:57:25 -0700260 MPC8349, MPC8560, MPC8540, MPC8548
Dave Jianga9a753d2008-02-07 00:14:55 -0800261
Dave Jiang4f4aeea2008-02-07 00:14:56 -0800262config EDAC_MV64X60
263 tristate "Marvell MV64x60"
264 depends on EDAC_MM_EDAC && MV64X60
265 help
266 Support for error detection and correction on the Marvell
267 MV64360 and MV64460 chipsets.
268
Egor Martovetsky7d8536f2007-07-19 01:50:24 -0700269config EDAC_PASEMI
270 tristate "PA Semi PWRficient"
271 depends on EDAC_MM_EDAC && PCI
Doug Thompsonddcc3052007-07-26 10:41:16 -0700272 depends on PPC_PASEMI
Egor Martovetsky7d8536f2007-07-19 01:50:24 -0700273 help
274 Support for error detection and correction on PA Semi
275 PWRficient.
276
Benjamin Herrenschmidt48764e42008-02-07 00:14:53 -0800277config EDAC_CELL
278 tristate "Cell Broadband Engine memory controller"
Benjamin Krilldef434c2008-11-27 16:15:44 +0100279 depends on EDAC_MM_EDAC && PPC_CELL_COMMON
Benjamin Herrenschmidt48764e42008-02-07 00:14:53 -0800280 help
281 Support for error detection and correction on the
282 Cell Broadband Engine internal memory controller
283 on platform without a hypervisor
Egor Martovetsky7d8536f2007-07-19 01:50:24 -0700284
Grant Ericksondba7a772009-04-02 16:58:45 -0700285config EDAC_PPC4XX
286 tristate "PPC4xx IBM DDR2 Memory Controller"
287 depends on EDAC_MM_EDAC && 4xx
288 help
289 This enables support for EDAC on the ECC memory used
290 with the IBM DDR2 memory controller found in various
291 PowerPC 4xx embedded processors such as the 405EX[r],
292 440SP, 440SPe, 460EX, 460GT and 460SX.
293
Harry Ciaoe8765582009-04-02 16:58:51 -0700294config EDAC_AMD8131
295 tristate "AMD8131 HyperTransport PCI-X Tunnel"
Harry Ciao715fe7a2009-05-28 14:34:43 -0700296 depends on EDAC_MM_EDAC && PCI && PPC_MAPLE
Harry Ciaoe8765582009-04-02 16:58:51 -0700297 help
298 Support for error detection and correction on the
299 AMD8131 HyperTransport PCI-X Tunnel chip.
Harry Ciao715fe7a2009-05-28 14:34:43 -0700300 Note, add more Kconfig dependency if it's adopted
301 on some machine other than Maple.
Harry Ciaoe8765582009-04-02 16:58:51 -0700302
Harry Ciao58b4ce62009-04-02 16:58:51 -0700303config EDAC_AMD8111
304 tristate "AMD8111 HyperTransport I/O Hub"
Harry Ciao715fe7a2009-05-28 14:34:43 -0700305 depends on EDAC_MM_EDAC && PCI && PPC_MAPLE
Harry Ciao58b4ce62009-04-02 16:58:51 -0700306 help
307 Support for error detection and correction on the
308 AMD8111 HyperTransport I/O Hub chip.
Harry Ciao715fe7a2009-05-28 14:34:43 -0700309 Note, add more Kconfig dependency if it's adopted
310 on some machine other than Maple.
Harry Ciao58b4ce62009-04-02 16:58:51 -0700311
Harry Ciao2a9036a2009-06-17 16:27:58 -0700312config EDAC_CPC925
313 tristate "IBM CPC925 Memory Controller (PPC970FX)"
314 depends on EDAC_MM_EDAC && PPC64
315 help
316 Support for error detection and correction on the
317 IBM CPC925 Bridge and Memory Controller, which is
318 a companion chip to the PowerPC 970 family of
319 processors.
320
Chris Metcalf5c770752011-03-01 13:01:49 -0500321config EDAC_TILE
322 tristate "Tilera Memory Controller"
323 depends on EDAC_MM_EDAC && TILE
324 default y
325 help
326 Support for error detection and correction on the
327 Tilera memory controller.
328
Rob Herringa1b01ed2012-06-13 12:01:55 -0500329config EDAC_HIGHBANK_MC
330 tristate "Highbank Memory Controller"
331 depends on EDAC_MM_EDAC && ARCH_HIGHBANK
332 help
333 Support for error detection and correction on the
334 Calxeda Highbank memory controller.
335
Rob Herring69154d02012-06-11 21:32:14 -0500336config EDAC_HIGHBANK_L2
337 tristate "Highbank L2 Cache"
338 depends on EDAC_MM_EDAC && ARCH_HIGHBANK
339 help
340 Support for error detection and correction on the
341 Calxeda Highbank memory controller.
342
Ralf Baechlef65aad42012-10-17 00:39:09 +0200343config EDAC_OCTEON_PC
344 tristate "Cavium Octeon Primary Caches"
345 depends on EDAC_MM_EDAC && CPU_CAVIUM_OCTEON
346 help
347 Support for error detection and correction on the primary caches of
348 the cnMIPS cores of Cavium Octeon family SOCs.
349
350config EDAC_OCTEON_L2C
351 tristate "Cavium Octeon Secondary Caches (L2C)"
352 depends on EDAC_MM_EDAC && CPU_CAVIUM_OCTEON
353 help
354 Support for error detection and correction on the
355 Cavium Octeon family of SOCs.
356
357config EDAC_OCTEON_LMC
358 tristate "Cavium Octeon DRAM Memory Controller (LMC)"
359 depends on EDAC_MM_EDAC && CPU_CAVIUM_OCTEON
360 help
361 Support for error detection and correction on the
362 Cavium Octeon family of SOCs.
363
364config EDAC_OCTEON_PCI
365 tristate "Cavium Octeon PCI Controller"
366 depends on EDAC_MM_EDAC && PCI && CPU_CAVIUM_OCTEON
367 help
368 Support for error detection and correction on the
369 Cavium Octeon family of SOCs.
370
Jan Engelhardt751cb5e2007-07-15 23:39:27 -0700371endif # EDAC