blob: 70caa63a8930e196229c1f8a5cd2654c7c21b597 [file] [log] [blame]
Giridhar Malavali6e980162010-03-19 17:03:58 -07001/*
2 * QLogic Fibre Channel HBA Driver
Andrew Vasquez07e264b2011-03-30 11:46:23 -07003 * Copyright (c) 2003-2011 QLogic Corporation
Giridhar Malavali6e980162010-03-19 17:03:58 -07004 *
5 * See LICENSE.qla2xxx for copyright and licensing details.
6 */
7#ifndef __QLA_BSG_H
8#define __QLA_BSG_H
9
10/* BSG Vendor specific commands */
11#define QL_VND_LOOPBACK 0x01
12#define QL_VND_A84_RESET 0x02
13#define QL_VND_A84_UPDATE_FW 0x03
14#define QL_VND_A84_MGMT_CMD 0x04
15#define QL_VND_IIDMA 0x05
16#define QL_VND_FCP_PRIO_CFG_CMD 0x06
Harish Zunjarraof19af162010-10-15 11:27:43 -070017#define QL_VND_READ_FLASH 0x07
18#define QL_VND_UPDATE_FLASH 0x08
Joe Carnuccio697a4bc2011-08-16 11:31:52 -070019#define QL_VND_SET_FRU_VERSION 0x0B
20#define QL_VND_READ_FRU_STATUS 0x0C
21#define QL_VND_WRITE_FRU_STATUS 0x0D
22
23/* BSG Vendor specific subcode returns */
24#define EXT_STATUS_OK 0
25#define EXT_STATUS_ERR 1
26#define EXT_STATUS_INVALID_PARAM 6
27#define EXT_STATUS_MAILBOX 11
28#define EXT_STATUS_NO_MEMORY 17
Giridhar Malavali6e980162010-03-19 17:03:58 -070029
30/* BSG definations for interpreting CommandSent field */
31#define INT_DEF_LB_LOOPBACK_CMD 0
32#define INT_DEF_LB_ECHO_CMD 1
33
Sarang Radke23f2ebd2010-05-28 15:08:21 -070034/* Loopback related definations */
35#define EXTERNAL_LOOPBACK 0xF2
36#define ENABLE_INTERNAL_LOOPBACK 0x02
37#define INTERNAL_LOOPBACK_MASK 0x000E
38#define MAX_ELS_FRAME_PAYLOAD 252
39#define ELS_OPCODE_BYTE 0x10
40
Giridhar Malavali6e980162010-03-19 17:03:58 -070041/* BSG Vendor specific definations */
42#define A84_ISSUE_WRITE_TYPE_CMD 0
43#define A84_ISSUE_READ_TYPE_CMD 1
44#define A84_CLEANUP_CMD 2
45#define A84_ISSUE_RESET_OP_FW 3
46#define A84_ISSUE_RESET_DIAG_FW 4
47#define A84_ISSUE_UPDATE_OPFW_CMD 5
48#define A84_ISSUE_UPDATE_DIAGFW_CMD 6
49
50struct qla84_mgmt_param {
51 union {
52 struct {
53 uint32_t start_addr;
54 } mem; /* for QLA84_MGMT_READ/WRITE_MEM */
55 struct {
56 uint32_t id;
57#define QLA84_MGMT_CONFIG_ID_UIF 1
58#define QLA84_MGMT_CONFIG_ID_FCOE_COS 2
59#define QLA84_MGMT_CONFIG_ID_PAUSE 3
60#define QLA84_MGMT_CONFIG_ID_TIMEOUTS 4
61
62 uint32_t param0;
63 uint32_t param1;
64 } config; /* for QLA84_MGMT_CHNG_CONFIG */
65
66 struct {
67 uint32_t type;
68#define QLA84_MGMT_INFO_CONFIG_LOG_DATA 1 /* Get Config Log Data */
69#define QLA84_MGMT_INFO_LOG_DATA 2 /* Get Log Data */
70#define QLA84_MGMT_INFO_PORT_STAT 3 /* Get Port Statistics */
71#define QLA84_MGMT_INFO_LIF_STAT 4 /* Get LIF Statistics */
72#define QLA84_MGMT_INFO_ASIC_STAT 5 /* Get ASIC Statistics */
73#define QLA84_MGMT_INFO_CONFIG_PARAMS 6 /* Get Config Parameters */
74#define QLA84_MGMT_INFO_PANIC_LOG 7 /* Get Panic Log */
75
76 uint32_t context;
77/*
78* context definitions for QLA84_MGMT_INFO_CONFIG_LOG_DATA
79*/
80#define IC_LOG_DATA_LOG_ID_DEBUG_LOG 0
81#define IC_LOG_DATA_LOG_ID_LEARN_LOG 1
82#define IC_LOG_DATA_LOG_ID_FC_ACL_INGRESS_LOG 2
83#define IC_LOG_DATA_LOG_ID_FC_ACL_EGRESS_LOG 3
84#define IC_LOG_DATA_LOG_ID_ETHERNET_ACL_INGRESS_LOG 4
85#define IC_LOG_DATA_LOG_ID_ETHERNET_ACL_EGRESS_LOG 5
86#define IC_LOG_DATA_LOG_ID_MESSAGE_TRANSMIT_LOG 6
87#define IC_LOG_DATA_LOG_ID_MESSAGE_RECEIVE_LOG 7
88#define IC_LOG_DATA_LOG_ID_LINK_EVENT_LOG 8
89#define IC_LOG_DATA_LOG_ID_DCX_LOG 9
90
91/*
92* context definitions for QLA84_MGMT_INFO_PORT_STAT
93*/
94#define IC_PORT_STATISTICS_PORT_NUMBER_ETHERNET_PORT0 0
95#define IC_PORT_STATISTICS_PORT_NUMBER_ETHERNET_PORT1 1
96#define IC_PORT_STATISTICS_PORT_NUMBER_NSL_PORT0 2
97#define IC_PORT_STATISTICS_PORT_NUMBER_NSL_PORT1 3
98#define IC_PORT_STATISTICS_PORT_NUMBER_FC_PORT0 4
99#define IC_PORT_STATISTICS_PORT_NUMBER_FC_PORT1 5
100
101
102/*
103* context definitions for QLA84_MGMT_INFO_LIF_STAT
104*/
105#define IC_LIF_STATISTICS_LIF_NUMBER_ETHERNET_PORT0 0
106#define IC_LIF_STATISTICS_LIF_NUMBER_ETHERNET_PORT1 1
107#define IC_LIF_STATISTICS_LIF_NUMBER_FC_PORT0 2
108#define IC_LIF_STATISTICS_LIF_NUMBER_FC_PORT1 3
109#define IC_LIF_STATISTICS_LIF_NUMBER_CPU 6
110
111 } info; /* for QLA84_MGMT_GET_INFO */
112 } u;
113};
114
115struct qla84_msg_mgmt {
116 uint16_t cmd;
117#define QLA84_MGMT_READ_MEM 0x00
118#define QLA84_MGMT_WRITE_MEM 0x01
119#define QLA84_MGMT_CHNG_CONFIG 0x02
120#define QLA84_MGMT_GET_INFO 0x03
121 uint16_t rsrvd;
122 struct qla84_mgmt_param mgmtp;/* parameters for cmd */
123 uint32_t len; /* bytes in payload following this struct */
124 uint8_t payload[0]; /* payload for cmd */
125};
126
127struct qla_bsg_a84_mgmt {
128 struct qla84_msg_mgmt mgmt;
129} __attribute__ ((packed));
130
131struct qla_scsi_addr {
132 uint16_t bus;
133 uint16_t target;
134} __attribute__ ((packed));
135
136struct qla_ext_dest_addr {
137 union {
138 uint8_t wwnn[8];
139 uint8_t wwpn[8];
140 uint8_t id[4];
141 struct qla_scsi_addr scsi_addr;
142 } dest_addr;
143 uint16_t dest_type;
144#define EXT_DEF_TYPE_WWPN 2
145 uint16_t lun;
146 uint16_t padding[2];
147} __attribute__ ((packed));
148
149struct qla_port_param {
150 struct qla_ext_dest_addr fc_scsi_addr;
151 uint16_t mode;
152 uint16_t speed;
153} __attribute__ ((packed));
Joe Carnuccio697a4bc2011-08-16 11:31:52 -0700154
155
156/* FRU VPD */
157
158#define MAX_FRU_SIZE 36
159
160struct qla_field_address {
161 uint16_t offset;
162 uint16_t device;
163 uint16_t option;
164} __packed;
165
166struct qla_field_info {
167 uint8_t version[MAX_FRU_SIZE];
168} __packed;
169
170struct qla_image_version {
171 struct qla_field_address field_address;
172 struct qla_field_info field_info;
173} __packed;
174
175struct qla_image_version_list {
176 uint32_t count;
177 struct qla_image_version version[0];
178} __packed;
179
180struct qla_status_reg {
181 struct qla_field_address field_address;
182 uint8_t status_reg;
183 uint8_t reserved[7];
184} __packed;
185
Giridhar Malavali6e980162010-03-19 17:03:58 -0700186#endif