Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1 | /* |
| 2 | * IOMMU API for ARM architected SMMU implementations. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 as |
| 6 | * published by the Free Software Foundation. |
| 7 | * |
| 8 | * This program is distributed in the hope that it will be useful, |
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 11 | * GNU General Public License for more details. |
| 12 | * |
| 13 | * You should have received a copy of the GNU General Public License |
| 14 | * along with this program; if not, write to the Free Software |
| 15 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. |
| 16 | * |
| 17 | * Copyright (C) 2013 ARM Limited |
| 18 | * |
| 19 | * Author: Will Deacon <will.deacon@arm.com> |
| 20 | * |
| 21 | * This driver currently supports: |
| 22 | * - SMMUv1 and v2 implementations |
| 23 | * - Stream-matching and stream-indexing |
| 24 | * - v7/v8 long-descriptor format |
| 25 | * - Non-secure access to the SMMU |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 26 | * - Context fault reporting |
| 27 | */ |
| 28 | |
| 29 | #define pr_fmt(fmt) "arm-smmu: " fmt |
| 30 | |
| 31 | #include <linux/delay.h> |
Robin Murphy | 9adb959 | 2016-01-26 18:06:36 +0000 | [diff] [blame] | 32 | #include <linux/dma-iommu.h> |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 33 | #include <linux/dma-mapping.h> |
| 34 | #include <linux/err.h> |
| 35 | #include <linux/interrupt.h> |
| 36 | #include <linux/io.h> |
Robin Murphy | f9a05f0 | 2016-04-13 18:13:01 +0100 | [diff] [blame] | 37 | #include <linux/io-64-nonatomic-hi-lo.h> |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 38 | #include <linux/iommu.h> |
Mitchel Humpherys | 859a732 | 2014-10-29 21:13:40 +0000 | [diff] [blame] | 39 | #include <linux/iopoll.h> |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 40 | #include <linux/module.h> |
| 41 | #include <linux/of.h> |
Robin Murphy | bae2c2d | 2015-07-29 19:46:05 +0100 | [diff] [blame] | 42 | #include <linux/of_address.h> |
Will Deacon | a9a1b0b | 2014-05-01 18:05:08 +0100 | [diff] [blame] | 43 | #include <linux/pci.h> |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 44 | #include <linux/platform_device.h> |
| 45 | #include <linux/slab.h> |
| 46 | #include <linux/spinlock.h> |
Patrick Daly | c11d108 | 2016-09-01 15:52:44 -0700 | [diff] [blame] | 47 | #include <soc/qcom/secure_buffer.h> |
Patrick Daly | 2764f95 | 2016-09-06 19:22:44 -0700 | [diff] [blame] | 48 | #include <linux/msm-bus.h> |
| 49 | #include <dt-bindings/msm/msm-bus-ids.h> |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 50 | |
| 51 | #include <linux/amba/bus.h> |
| 52 | |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame] | 53 | #include "io-pgtable.h" |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 54 | |
| 55 | /* Maximum number of stream IDs assigned to a single device */ |
Joerg Roedel | cb6c27b | 2016-04-04 17:49:22 +0200 | [diff] [blame] | 56 | #define MAX_MASTER_STREAMIDS 128 |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 57 | |
| 58 | /* Maximum number of context banks per SMMU */ |
| 59 | #define ARM_SMMU_MAX_CBS 128 |
| 60 | |
| 61 | /* Maximum number of mapping groups per SMMU */ |
| 62 | #define ARM_SMMU_MAX_SMRS 128 |
| 63 | |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 64 | /* SMMU global address space */ |
| 65 | #define ARM_SMMU_GR0(smmu) ((smmu)->base) |
Will Deacon | c757e85 | 2014-07-30 11:33:25 +0100 | [diff] [blame] | 66 | #define ARM_SMMU_GR1(smmu) ((smmu)->base + (1 << (smmu)->pgshift)) |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 67 | |
Andreas Herrmann | 3a5df8f | 2014-01-30 18:18:04 +0000 | [diff] [blame] | 68 | /* |
| 69 | * SMMU global address space with conditional offset to access secure |
| 70 | * aliases of non-secure registers (e.g. nsCR0: 0x400, nsGFSR: 0x448, |
| 71 | * nsGFSYNR0: 0x450) |
| 72 | */ |
| 73 | #define ARM_SMMU_GR0_NS(smmu) \ |
| 74 | ((smmu)->base + \ |
| 75 | ((smmu->options & ARM_SMMU_OPT_SECURE_CFG_ACCESS) \ |
| 76 | ? 0x400 : 0)) |
| 77 | |
Robin Murphy | f9a05f0 | 2016-04-13 18:13:01 +0100 | [diff] [blame] | 78 | /* |
| 79 | * Some 64-bit registers only make sense to write atomically, but in such |
| 80 | * cases all the data relevant to AArch32 formats lies within the lower word, |
| 81 | * therefore this actually makes more sense than it might first appear. |
| 82 | */ |
Tirumalesh Chalamarla | 668b4ad | 2015-08-19 00:40:30 +0100 | [diff] [blame] | 83 | #ifdef CONFIG_64BIT |
Robin Murphy | f9a05f0 | 2016-04-13 18:13:01 +0100 | [diff] [blame] | 84 | #define smmu_write_atomic_lq writeq_relaxed |
Tirumalesh Chalamarla | 668b4ad | 2015-08-19 00:40:30 +0100 | [diff] [blame] | 85 | #else |
Robin Murphy | f9a05f0 | 2016-04-13 18:13:01 +0100 | [diff] [blame] | 86 | #define smmu_write_atomic_lq writel_relaxed |
Tirumalesh Chalamarla | 668b4ad | 2015-08-19 00:40:30 +0100 | [diff] [blame] | 87 | #endif |
| 88 | |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 89 | /* Configuration registers */ |
| 90 | #define ARM_SMMU_GR0_sCR0 0x0 |
| 91 | #define sCR0_CLIENTPD (1 << 0) |
| 92 | #define sCR0_GFRE (1 << 1) |
| 93 | #define sCR0_GFIE (1 << 2) |
| 94 | #define sCR0_GCFGFRE (1 << 4) |
| 95 | #define sCR0_GCFGFIE (1 << 5) |
| 96 | #define sCR0_USFCFG (1 << 10) |
| 97 | #define sCR0_VMIDPNE (1 << 11) |
| 98 | #define sCR0_PTM (1 << 12) |
| 99 | #define sCR0_FB (1 << 13) |
Tirumalesh Chalamarla | 4e3e9b6 | 2016-02-23 10:19:00 -0800 | [diff] [blame] | 100 | #define sCR0_VMID16EN (1 << 31) |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 101 | #define sCR0_BSU_SHIFT 14 |
| 102 | #define sCR0_BSU_MASK 0x3 |
| 103 | |
Peng Fan | 3ca3712 | 2016-05-03 21:50:30 +0800 | [diff] [blame] | 104 | /* Auxiliary Configuration register */ |
| 105 | #define ARM_SMMU_GR0_sACR 0x10 |
| 106 | |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 107 | /* Identification registers */ |
| 108 | #define ARM_SMMU_GR0_ID0 0x20 |
| 109 | #define ARM_SMMU_GR0_ID1 0x24 |
| 110 | #define ARM_SMMU_GR0_ID2 0x28 |
| 111 | #define ARM_SMMU_GR0_ID3 0x2c |
| 112 | #define ARM_SMMU_GR0_ID4 0x30 |
| 113 | #define ARM_SMMU_GR0_ID5 0x34 |
| 114 | #define ARM_SMMU_GR0_ID6 0x38 |
| 115 | #define ARM_SMMU_GR0_ID7 0x3c |
| 116 | #define ARM_SMMU_GR0_sGFSR 0x48 |
| 117 | #define ARM_SMMU_GR0_sGFSYNR0 0x50 |
| 118 | #define ARM_SMMU_GR0_sGFSYNR1 0x54 |
| 119 | #define ARM_SMMU_GR0_sGFSYNR2 0x58 |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 120 | |
| 121 | #define ID0_S1TS (1 << 30) |
| 122 | #define ID0_S2TS (1 << 29) |
| 123 | #define ID0_NTS (1 << 28) |
| 124 | #define ID0_SMS (1 << 27) |
Mitchel Humpherys | 859a732 | 2014-10-29 21:13:40 +0000 | [diff] [blame] | 125 | #define ID0_ATOSNS (1 << 26) |
Robin Murphy | 7602b87 | 2016-04-28 17:12:09 +0100 | [diff] [blame] | 126 | #define ID0_PTFS_NO_AARCH32 (1 << 25) |
| 127 | #define ID0_PTFS_NO_AARCH32S (1 << 24) |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 128 | #define ID0_CTTW (1 << 14) |
| 129 | #define ID0_NUMIRPT_SHIFT 16 |
| 130 | #define ID0_NUMIRPT_MASK 0xff |
Olav Haugan | 3c8766d | 2014-08-22 17:12:32 -0700 | [diff] [blame] | 131 | #define ID0_NUMSIDB_SHIFT 9 |
| 132 | #define ID0_NUMSIDB_MASK 0xf |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 133 | #define ID0_NUMSMRG_SHIFT 0 |
| 134 | #define ID0_NUMSMRG_MASK 0xff |
| 135 | |
| 136 | #define ID1_PAGESIZE (1 << 31) |
| 137 | #define ID1_NUMPAGENDXB_SHIFT 28 |
| 138 | #define ID1_NUMPAGENDXB_MASK 7 |
| 139 | #define ID1_NUMS2CB_SHIFT 16 |
| 140 | #define ID1_NUMS2CB_MASK 0xff |
| 141 | #define ID1_NUMCB_SHIFT 0 |
| 142 | #define ID1_NUMCB_MASK 0xff |
| 143 | |
| 144 | #define ID2_OAS_SHIFT 4 |
| 145 | #define ID2_OAS_MASK 0xf |
| 146 | #define ID2_IAS_SHIFT 0 |
| 147 | #define ID2_IAS_MASK 0xf |
| 148 | #define ID2_UBS_SHIFT 8 |
| 149 | #define ID2_UBS_MASK 0xf |
| 150 | #define ID2_PTFS_4K (1 << 12) |
| 151 | #define ID2_PTFS_16K (1 << 13) |
| 152 | #define ID2_PTFS_64K (1 << 14) |
Tirumalesh Chalamarla | 4e3e9b6 | 2016-02-23 10:19:00 -0800 | [diff] [blame] | 153 | #define ID2_VMID16 (1 << 15) |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 154 | |
Peng Fan | 3ca3712 | 2016-05-03 21:50:30 +0800 | [diff] [blame] | 155 | #define ID7_MAJOR_SHIFT 4 |
| 156 | #define ID7_MAJOR_MASK 0xf |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 157 | |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 158 | /* Global TLB invalidation */ |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 159 | #define ARM_SMMU_GR0_TLBIVMID 0x64 |
| 160 | #define ARM_SMMU_GR0_TLBIALLNSNH 0x68 |
| 161 | #define ARM_SMMU_GR0_TLBIALLH 0x6c |
| 162 | #define ARM_SMMU_GR0_sTLBGSYNC 0x70 |
| 163 | #define ARM_SMMU_GR0_sTLBGSTATUS 0x74 |
| 164 | #define sTLBGSTATUS_GSACTIVE (1 << 0) |
Mitchel Humpherys | 849aa50 | 2015-11-09 11:50:58 -0800 | [diff] [blame] | 165 | #define TLB_LOOP_TIMEOUT 500000 /* 500ms */ |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 166 | |
| 167 | /* Stream mapping registers */ |
| 168 | #define ARM_SMMU_GR0_SMR(n) (0x800 + ((n) << 2)) |
| 169 | #define SMR_VALID (1 << 31) |
| 170 | #define SMR_MASK_SHIFT 16 |
| 171 | #define SMR_MASK_MASK 0x7fff |
| 172 | #define SMR_ID_SHIFT 0 |
| 173 | #define SMR_ID_MASK 0x7fff |
| 174 | |
| 175 | #define ARM_SMMU_GR0_S2CR(n) (0xc00 + ((n) << 2)) |
| 176 | #define S2CR_CBNDX_SHIFT 0 |
| 177 | #define S2CR_CBNDX_MASK 0xff |
| 178 | #define S2CR_TYPE_SHIFT 16 |
| 179 | #define S2CR_TYPE_MASK 0x3 |
| 180 | #define S2CR_TYPE_TRANS (0 << S2CR_TYPE_SHIFT) |
| 181 | #define S2CR_TYPE_BYPASS (1 << S2CR_TYPE_SHIFT) |
| 182 | #define S2CR_TYPE_FAULT (2 << S2CR_TYPE_SHIFT) |
| 183 | |
| 184 | /* Context bank attribute registers */ |
| 185 | #define ARM_SMMU_GR1_CBAR(n) (0x0 + ((n) << 2)) |
| 186 | #define CBAR_VMID_SHIFT 0 |
| 187 | #define CBAR_VMID_MASK 0xff |
Will Deacon | 57ca90f | 2014-02-06 14:59:05 +0000 | [diff] [blame] | 188 | #define CBAR_S1_BPSHCFG_SHIFT 8 |
| 189 | #define CBAR_S1_BPSHCFG_MASK 3 |
| 190 | #define CBAR_S1_BPSHCFG_NSH 3 |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 191 | #define CBAR_S1_MEMATTR_SHIFT 12 |
| 192 | #define CBAR_S1_MEMATTR_MASK 0xf |
| 193 | #define CBAR_S1_MEMATTR_WB 0xf |
| 194 | #define CBAR_TYPE_SHIFT 16 |
| 195 | #define CBAR_TYPE_MASK 0x3 |
| 196 | #define CBAR_TYPE_S2_TRANS (0 << CBAR_TYPE_SHIFT) |
| 197 | #define CBAR_TYPE_S1_TRANS_S2_BYPASS (1 << CBAR_TYPE_SHIFT) |
| 198 | #define CBAR_TYPE_S1_TRANS_S2_FAULT (2 << CBAR_TYPE_SHIFT) |
| 199 | #define CBAR_TYPE_S1_TRANS_S2_TRANS (3 << CBAR_TYPE_SHIFT) |
| 200 | #define CBAR_IRPTNDX_SHIFT 24 |
| 201 | #define CBAR_IRPTNDX_MASK 0xff |
| 202 | |
Shalaj Jain | 04059c5 | 2015-03-03 13:34:59 -0800 | [diff] [blame] | 203 | #define ARM_SMMU_GR1_CBFRSYNRA(n) (0x400 + ((n) << 2)) |
| 204 | #define CBFRSYNRA_SID_MASK (0xffff) |
| 205 | |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 206 | #define ARM_SMMU_GR1_CBA2R(n) (0x800 + ((n) << 2)) |
| 207 | #define CBA2R_RW64_32BIT (0 << 0) |
| 208 | #define CBA2R_RW64_64BIT (1 << 0) |
Tirumalesh Chalamarla | 4e3e9b6 | 2016-02-23 10:19:00 -0800 | [diff] [blame] | 209 | #define CBA2R_VMID_SHIFT 16 |
| 210 | #define CBA2R_VMID_MASK 0xffff |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 211 | |
| 212 | /* Translation context bank */ |
| 213 | #define ARM_SMMU_CB_BASE(smmu) ((smmu)->base + ((smmu)->size >> 1)) |
Will Deacon | c757e85 | 2014-07-30 11:33:25 +0100 | [diff] [blame] | 214 | #define ARM_SMMU_CB(smmu, n) ((n) * (1 << (smmu)->pgshift)) |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 215 | |
| 216 | #define ARM_SMMU_CB_SCTLR 0x0 |
Robin Murphy | f0cfffc | 2016-04-13 18:12:59 +0100 | [diff] [blame] | 217 | #define ARM_SMMU_CB_ACTLR 0x4 |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 218 | #define ARM_SMMU_CB_RESUME 0x8 |
| 219 | #define ARM_SMMU_CB_TTBCR2 0x10 |
Tirumalesh Chalamarla | 668b4ad | 2015-08-19 00:40:30 +0100 | [diff] [blame] | 220 | #define ARM_SMMU_CB_TTBR0 0x20 |
| 221 | #define ARM_SMMU_CB_TTBR1 0x28 |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 222 | #define ARM_SMMU_CB_TTBCR 0x30 |
Jeremy Gebben | 8ac927c | 2015-07-10 16:43:22 -0600 | [diff] [blame] | 223 | #define ARM_SMMU_CB_CONTEXTIDR 0x34 |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 224 | #define ARM_SMMU_CB_S1_MAIR0 0x38 |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame] | 225 | #define ARM_SMMU_CB_S1_MAIR1 0x3c |
Robin Murphy | f9a05f0 | 2016-04-13 18:13:01 +0100 | [diff] [blame] | 226 | #define ARM_SMMU_CB_PAR 0x50 |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 227 | #define ARM_SMMU_CB_FSR 0x58 |
Mitchel Humpherys | a52d6cc | 2015-07-09 17:26:15 -0700 | [diff] [blame] | 228 | #define ARM_SMMU_CB_FSRRESTORE 0x5c |
Robin Murphy | f9a05f0 | 2016-04-13 18:13:01 +0100 | [diff] [blame] | 229 | #define ARM_SMMU_CB_FAR 0x60 |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 230 | #define ARM_SMMU_CB_FSYNR0 0x68 |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame] | 231 | #define ARM_SMMU_CB_S1_TLBIVA 0x600 |
Will Deacon | 1463fe4 | 2013-07-31 19:21:27 +0100 | [diff] [blame] | 232 | #define ARM_SMMU_CB_S1_TLBIASID 0x610 |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame] | 233 | #define ARM_SMMU_CB_S1_TLBIVAL 0x620 |
| 234 | #define ARM_SMMU_CB_S2_TLBIIPAS2 0x630 |
| 235 | #define ARM_SMMU_CB_S2_TLBIIPAS2L 0x638 |
Mitchel Humpherys | f300799 | 2015-06-19 15:00:14 -0700 | [diff] [blame] | 236 | #define ARM_SMMU_CB_TLBSYNC 0x7f0 |
| 237 | #define ARM_SMMU_CB_TLBSTATUS 0x7f4 |
| 238 | #define TLBSTATUS_SACTIVE (1 << 0) |
Robin Murphy | 661d962 | 2015-05-27 17:09:34 +0100 | [diff] [blame] | 239 | #define ARM_SMMU_CB_ATS1PR 0x800 |
Mitchel Humpherys | 859a732 | 2014-10-29 21:13:40 +0000 | [diff] [blame] | 240 | #define ARM_SMMU_CB_ATSR 0x8f0 |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 241 | |
| 242 | #define SCTLR_S1_ASIDPNE (1 << 12) |
| 243 | #define SCTLR_CFCFG (1 << 7) |
| 244 | #define SCTLR_CFIE (1 << 6) |
| 245 | #define SCTLR_CFRE (1 << 5) |
| 246 | #define SCTLR_E (1 << 4) |
| 247 | #define SCTLR_AFE (1 << 2) |
| 248 | #define SCTLR_TRE (1 << 1) |
| 249 | #define SCTLR_M (1 << 0) |
| 250 | #define SCTLR_EAE_SBOP (SCTLR_AFE | SCTLR_TRE) |
| 251 | |
Robin Murphy | f0cfffc | 2016-04-13 18:12:59 +0100 | [diff] [blame] | 252 | #define ARM_MMU500_ACTLR_CPRE (1 << 1) |
| 253 | |
Peng Fan | 3ca3712 | 2016-05-03 21:50:30 +0800 | [diff] [blame] | 254 | #define ARM_MMU500_ACR_CACHE_LOCK (1 << 26) |
| 255 | |
Patrick Daly | f0d4e21 | 2016-06-20 15:50:14 -0700 | [diff] [blame] | 256 | /* Definitions for implementation-defined registers */ |
| 257 | #define ACTLR_QCOM_OSH_SHIFT 28 |
| 258 | #define ACTLR_QCOM_OSH 1 |
| 259 | |
| 260 | #define ACTLR_QCOM_ISH_SHIFT 29 |
| 261 | #define ACTLR_QCOM_ISH 1 |
| 262 | |
| 263 | #define ACTLR_QCOM_NSH_SHIFT 30 |
| 264 | #define ACTLR_QCOM_NSH 1 |
| 265 | |
Mitchel Humpherys | 952f40a | 2015-08-19 12:13:28 -0700 | [diff] [blame] | 266 | #define ARM_SMMU_IMPL_DEF0(smmu) \ |
| 267 | ((smmu)->base + (2 * (1 << (smmu)->pgshift))) |
| 268 | #define ARM_SMMU_IMPL_DEF1(smmu) \ |
| 269 | ((smmu)->base + (6 * (1 << (smmu)->pgshift))) |
| 270 | #define IMPL_DEF1_MICRO_MMU_CTRL 0 |
| 271 | #define MICRO_MMU_CTRL_LOCAL_HALT_REQ (1 << 2) |
| 272 | #define MICRO_MMU_CTRL_IDLE (1 << 3) |
| 273 | |
Mitchel Humpherys | 859a732 | 2014-10-29 21:13:40 +0000 | [diff] [blame] | 274 | #define CB_PAR_F (1 << 0) |
| 275 | |
| 276 | #define ATSR_ACTIVE (1 << 0) |
| 277 | |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 278 | #define RESUME_RETRY (0 << 0) |
| 279 | #define RESUME_TERMINATE (1 << 0) |
| 280 | |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 281 | #define TTBCR2_SEP_SHIFT 15 |
Will Deacon | 5dc5616 | 2015-05-08 17:44:22 +0100 | [diff] [blame] | 282 | #define TTBCR2_SEP_UPSTREAM (0x7 << TTBCR2_SEP_SHIFT) |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 283 | |
Tirumalesh Chalamarla | 668b4ad | 2015-08-19 00:40:30 +0100 | [diff] [blame] | 284 | #define TTBRn_ASID_SHIFT 48 |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 285 | |
| 286 | #define FSR_MULTI (1 << 31) |
| 287 | #define FSR_SS (1 << 30) |
| 288 | #define FSR_UUT (1 << 8) |
| 289 | #define FSR_ASF (1 << 7) |
| 290 | #define FSR_TLBLKF (1 << 6) |
| 291 | #define FSR_TLBMCF (1 << 5) |
| 292 | #define FSR_EF (1 << 4) |
| 293 | #define FSR_PF (1 << 3) |
| 294 | #define FSR_AFF (1 << 2) |
| 295 | #define FSR_TF (1 << 1) |
| 296 | |
Mitchel Humpherys | 2907320 | 2014-07-08 09:52:18 -0700 | [diff] [blame] | 297 | #define FSR_IGN (FSR_AFF | FSR_ASF | \ |
| 298 | FSR_TLBMCF | FSR_TLBLKF) |
| 299 | #define FSR_FAULT (FSR_MULTI | FSR_SS | FSR_UUT | \ |
Will Deacon | adaba32 | 2013-07-31 19:21:26 +0100 | [diff] [blame] | 300 | FSR_EF | FSR_PF | FSR_TF | FSR_IGN) |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 301 | |
| 302 | #define FSYNR0_WNR (1 << 4) |
| 303 | |
Will Deacon | 4cf740b | 2014-07-14 19:47:39 +0100 | [diff] [blame] | 304 | static int force_stage; |
Robin Murphy | 25a1c96 | 2016-02-10 14:25:33 +0000 | [diff] [blame] | 305 | module_param(force_stage, int, S_IRUGO); |
Will Deacon | 4cf740b | 2014-07-14 19:47:39 +0100 | [diff] [blame] | 306 | MODULE_PARM_DESC(force_stage, |
| 307 | "Force SMMU mappings to be installed at a particular stage of translation. A value of '1' or '2' forces the corresponding stage. All other values are ignored (i.e. no stage is forced). Note that selecting a specific stage will disable support for nested translation."); |
Patrick Daly | 6988454 | 2016-10-06 21:36:36 -0700 | [diff] [blame^] | 308 | static bool disable_bypass = 1; |
Robin Murphy | 25a1c96 | 2016-02-10 14:25:33 +0000 | [diff] [blame] | 309 | module_param(disable_bypass, bool, S_IRUGO); |
| 310 | MODULE_PARM_DESC(disable_bypass, |
| 311 | "Disable bypass streams such that incoming transactions from devices that are not attached to an iommu domain will report an abort back to the device and will not be allowed to pass through the SMMU."); |
Will Deacon | 4cf740b | 2014-07-14 19:47:39 +0100 | [diff] [blame] | 312 | |
Robin Murphy | 0936040 | 2014-08-28 17:51:59 +0100 | [diff] [blame] | 313 | enum arm_smmu_arch_version { |
Robin Murphy | b7862e3 | 2016-04-13 18:13:03 +0100 | [diff] [blame] | 314 | ARM_SMMU_V1, |
| 315 | ARM_SMMU_V1_64K, |
Robin Murphy | 0936040 | 2014-08-28 17:51:59 +0100 | [diff] [blame] | 316 | ARM_SMMU_V2, |
| 317 | }; |
| 318 | |
Robin Murphy | 67b65a3 | 2016-04-13 18:12:57 +0100 | [diff] [blame] | 319 | enum arm_smmu_implementation { |
| 320 | GENERIC_SMMU, |
Robin Murphy | f0cfffc | 2016-04-13 18:12:59 +0100 | [diff] [blame] | 321 | ARM_MMU500, |
Robin Murphy | e086d91 | 2016-04-13 18:12:58 +0100 | [diff] [blame] | 322 | CAVIUM_SMMUV2, |
Patrick Daly | f0d4e21 | 2016-06-20 15:50:14 -0700 | [diff] [blame] | 323 | QCOM_SMMUV2, |
Robin Murphy | 67b65a3 | 2016-04-13 18:12:57 +0100 | [diff] [blame] | 324 | }; |
| 325 | |
Mitchel Humpherys | 5494a5e | 2014-08-14 17:44:49 -0700 | [diff] [blame] | 326 | struct arm_smmu_impl_def_reg { |
| 327 | u32 offset; |
| 328 | u32 value; |
| 329 | }; |
| 330 | |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 331 | struct arm_smmu_smr { |
| 332 | u8 idx; |
| 333 | u16 mask; |
| 334 | u16 id; |
| 335 | }; |
| 336 | |
Will Deacon | a9a1b0b | 2014-05-01 18:05:08 +0100 | [diff] [blame] | 337 | struct arm_smmu_master_cfg { |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 338 | int num_streamids; |
| 339 | u16 streamids[MAX_MASTER_STREAMIDS]; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 340 | struct arm_smmu_smr *smrs; |
| 341 | }; |
| 342 | |
Will Deacon | a9a1b0b | 2014-05-01 18:05:08 +0100 | [diff] [blame] | 343 | struct arm_smmu_master { |
| 344 | struct device_node *of_node; |
Will Deacon | a9a1b0b | 2014-05-01 18:05:08 +0100 | [diff] [blame] | 345 | struct rb_node node; |
| 346 | struct arm_smmu_master_cfg cfg; |
| 347 | }; |
| 348 | |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 349 | struct arm_smmu_device { |
| 350 | struct device *dev; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 351 | |
| 352 | void __iomem *base; |
| 353 | unsigned long size; |
Will Deacon | c757e85 | 2014-07-30 11:33:25 +0100 | [diff] [blame] | 354 | unsigned long pgshift; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 355 | |
| 356 | #define ARM_SMMU_FEAT_COHERENT_WALK (1 << 0) |
| 357 | #define ARM_SMMU_FEAT_STREAM_MATCH (1 << 1) |
| 358 | #define ARM_SMMU_FEAT_TRANS_S1 (1 << 2) |
| 359 | #define ARM_SMMU_FEAT_TRANS_S2 (1 << 3) |
| 360 | #define ARM_SMMU_FEAT_TRANS_NESTED (1 << 4) |
Mitchel Humpherys | 859a732 | 2014-10-29 21:13:40 +0000 | [diff] [blame] | 361 | #define ARM_SMMU_FEAT_TRANS_OPS (1 << 5) |
Tirumalesh Chalamarla | 4e3e9b6 | 2016-02-23 10:19:00 -0800 | [diff] [blame] | 362 | #define ARM_SMMU_FEAT_VMID16 (1 << 6) |
Robin Murphy | 7602b87 | 2016-04-28 17:12:09 +0100 | [diff] [blame] | 363 | #define ARM_SMMU_FEAT_FMT_AARCH64_4K (1 << 7) |
| 364 | #define ARM_SMMU_FEAT_FMT_AARCH64_16K (1 << 8) |
| 365 | #define ARM_SMMU_FEAT_FMT_AARCH64_64K (1 << 9) |
| 366 | #define ARM_SMMU_FEAT_FMT_AARCH32_L (1 << 10) |
| 367 | #define ARM_SMMU_FEAT_FMT_AARCH32_S (1 << 11) |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 368 | u32 features; |
Andreas Herrmann | 3a5df8f | 2014-01-30 18:18:04 +0000 | [diff] [blame] | 369 | |
| 370 | #define ARM_SMMU_OPT_SECURE_CFG_ACCESS (1 << 0) |
Mitchel Humpherys | 07ba44b | 2015-01-30 14:58:52 -0800 | [diff] [blame] | 371 | #define ARM_SMMU_OPT_FATAL_ASF (1 << 1) |
Mitchel Humpherys | 9c2f648 | 2015-01-13 15:28:40 -0800 | [diff] [blame] | 372 | #define ARM_SMMU_OPT_SKIP_INIT (1 << 2) |
Patrick Daly | c190d93 | 2016-08-30 17:23:28 -0700 | [diff] [blame] | 373 | #define ARM_SMMU_OPT_DYNAMIC (1 << 3) |
Andreas Herrmann | 3a5df8f | 2014-01-30 18:18:04 +0000 | [diff] [blame] | 374 | u32 options; |
Robin Murphy | 0936040 | 2014-08-28 17:51:59 +0100 | [diff] [blame] | 375 | enum arm_smmu_arch_version version; |
Robin Murphy | 67b65a3 | 2016-04-13 18:12:57 +0100 | [diff] [blame] | 376 | enum arm_smmu_implementation model; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 377 | |
| 378 | u32 num_context_banks; |
| 379 | u32 num_s2_context_banks; |
| 380 | DECLARE_BITMAP(context_map, ARM_SMMU_MAX_CBS); |
| 381 | atomic_t irptndx; |
| 382 | |
| 383 | u32 num_mapping_groups; |
| 384 | DECLARE_BITMAP(smr_map, ARM_SMMU_MAX_SMRS); |
| 385 | |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame] | 386 | unsigned long va_size; |
| 387 | unsigned long ipa_size; |
| 388 | unsigned long pa_size; |
Robin Murphy | d546635 | 2016-05-09 17:20:09 +0100 | [diff] [blame] | 389 | unsigned long pgsize_bitmap; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 390 | |
| 391 | u32 num_global_irqs; |
| 392 | u32 num_context_irqs; |
| 393 | unsigned int *irqs; |
| 394 | |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 395 | struct list_head list; |
| 396 | struct rb_root masters; |
Tirumalesh Chalamarla | 1bd37a6 | 2016-03-04 13:56:09 -0800 | [diff] [blame] | 397 | |
| 398 | u32 cavium_id_base; /* Specific to Cavium */ |
Mitchel Humpherys | 5494a5e | 2014-08-14 17:44:49 -0700 | [diff] [blame] | 399 | /* Specific to QCOM */ |
| 400 | struct arm_smmu_impl_def_reg *impl_def_attach_registers; |
| 401 | unsigned int num_impl_def_attach_registers; |
Mitchel Humpherys | 2fbae2a | 2014-12-04 11:46:24 -0800 | [diff] [blame] | 402 | |
Patrick Daly | 3a8a88a | 2016-07-22 12:24:05 -0700 | [diff] [blame] | 403 | int num_clocks; |
| 404 | struct clk **clocks; |
| 405 | |
Mitchel Humpherys | f7666ae | 2014-07-23 17:35:07 -0700 | [diff] [blame] | 406 | struct regulator *gdsc; |
| 407 | |
Patrick Daly | 2764f95 | 2016-09-06 19:22:44 -0700 | [diff] [blame] | 408 | struct msm_bus_client_handle *bus_client; |
| 409 | char *bus_client_name; |
| 410 | |
Patrick Daly | 3a8a88a | 2016-07-22 12:24:05 -0700 | [diff] [blame] | 411 | /* Protects power_count */ |
| 412 | struct mutex power_lock; |
| 413 | int power_count; |
Patrick Daly | 8befb66 | 2016-08-17 20:03:28 -0700 | [diff] [blame] | 414 | /* Protects clock_refs_count */ |
| 415 | spinlock_t clock_refs_lock; |
| 416 | int clock_refs_count; |
Patrick Daly | 3a8a88a | 2016-07-22 12:24:05 -0700 | [diff] [blame] | 417 | |
Mitchel Humpherys | 2fbae2a | 2014-12-04 11:46:24 -0800 | [diff] [blame] | 418 | spinlock_t atos_lock; |
Patrick Daly | c190d93 | 2016-08-30 17:23:28 -0700 | [diff] [blame] | 419 | |
| 420 | /* protects idr */ |
| 421 | struct mutex idr_mutex; |
| 422 | struct idr asid_idr; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 423 | }; |
| 424 | |
Robin Murphy | 7602b87 | 2016-04-28 17:12:09 +0100 | [diff] [blame] | 425 | enum arm_smmu_context_fmt { |
| 426 | ARM_SMMU_CTX_FMT_NONE, |
| 427 | ARM_SMMU_CTX_FMT_AARCH64, |
| 428 | ARM_SMMU_CTX_FMT_AARCH32_L, |
| 429 | ARM_SMMU_CTX_FMT_AARCH32_S, |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 430 | }; |
| 431 | |
| 432 | struct arm_smmu_cfg { |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 433 | u8 cbndx; |
| 434 | u8 irptndx; |
| 435 | u32 cbar; |
Jeremy Gebben | 8ac927c | 2015-07-10 16:43:22 -0600 | [diff] [blame] | 436 | u32 procid; |
| 437 | u16 asid; |
Robin Murphy | 7602b87 | 2016-04-28 17:12:09 +0100 | [diff] [blame] | 438 | enum arm_smmu_context_fmt fmt; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 439 | }; |
Dan Carpenter | faea13b7 | 2013-08-21 09:33:30 +0100 | [diff] [blame] | 440 | #define INVALID_IRPTNDX 0xff |
Jeremy Gebben | 8ac927c | 2015-07-10 16:43:22 -0600 | [diff] [blame] | 441 | #define INVALID_CBNDX 0xff |
| 442 | #define INVALID_ASID 0xffff |
Patrick Daly | c190d93 | 2016-08-30 17:23:28 -0700 | [diff] [blame] | 443 | /* |
| 444 | * In V7L and V8L with TTBCR2.AS == 0, ASID is 8 bits. |
| 445 | * V8L 16 with TTBCR2.AS == 1 (16 bit ASID) isn't supported yet. |
| 446 | */ |
| 447 | #define MAX_ASID 0xff |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 448 | |
Jeremy Gebben | 8ac927c | 2015-07-10 16:43:22 -0600 | [diff] [blame] | 449 | #define ARM_SMMU_CB_ASID(smmu, cfg) ((cfg)->asid) |
Tirumalesh Chalamarla | 1bd37a6 | 2016-03-04 13:56:09 -0800 | [diff] [blame] | 450 | #define ARM_SMMU_CB_VMID(smmu, cfg) ((u16)(smmu)->cavium_id_base + (cfg)->cbndx + 1) |
Will Deacon | ecfadb6 | 2013-07-31 19:21:28 +0100 | [diff] [blame] | 451 | |
Will Deacon | c752ce4 | 2014-06-25 22:46:31 +0100 | [diff] [blame] | 452 | enum arm_smmu_domain_stage { |
| 453 | ARM_SMMU_DOMAIN_S1 = 0, |
| 454 | ARM_SMMU_DOMAIN_S2, |
| 455 | ARM_SMMU_DOMAIN_NESTED, |
| 456 | }; |
| 457 | |
Patrick Daly | c11d108 | 2016-09-01 15:52:44 -0700 | [diff] [blame] | 458 | struct arm_smmu_pte_info { |
| 459 | void *virt_addr; |
| 460 | size_t size; |
| 461 | struct list_head entry; |
| 462 | }; |
| 463 | |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 464 | struct arm_smmu_domain { |
Will Deacon | 44680ee | 2014-06-25 11:29:12 +0100 | [diff] [blame] | 465 | struct arm_smmu_device *smmu; |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame] | 466 | struct io_pgtable_ops *pgtbl_ops; |
Mitchel Humpherys | 39e9c91 | 2015-04-15 15:14:15 -0700 | [diff] [blame] | 467 | struct io_pgtable_cfg pgtbl_cfg; |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame] | 468 | spinlock_t pgtbl_lock; |
Will Deacon | 44680ee | 2014-06-25 11:29:12 +0100 | [diff] [blame] | 469 | struct arm_smmu_cfg cfg; |
Will Deacon | c752ce4 | 2014-06-25 22:46:31 +0100 | [diff] [blame] | 470 | enum arm_smmu_domain_stage stage; |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame] | 471 | struct mutex init_mutex; /* Protects smmu pointer */ |
Patrick Daly | c190d93 | 2016-08-30 17:23:28 -0700 | [diff] [blame] | 472 | u32 attributes; |
Patrick Daly | c11d108 | 2016-09-01 15:52:44 -0700 | [diff] [blame] | 473 | u32 secure_vmid; |
| 474 | struct list_head pte_info_list; |
| 475 | struct list_head unassign_list; |
Patrick Daly | e271f21 | 2016-10-04 13:24:49 -0700 | [diff] [blame] | 476 | struct mutex assign_lock; |
Patrick Daly | b7dfda7 | 2016-10-04 14:42:58 -0700 | [diff] [blame] | 477 | struct list_head secure_pool_list; |
Joerg Roedel | 1d67263 | 2015-03-26 13:43:10 +0100 | [diff] [blame] | 478 | struct iommu_domain domain; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 479 | }; |
| 480 | |
Joerg Roedel | cb6c27b | 2016-04-04 17:49:22 +0200 | [diff] [blame] | 481 | struct arm_smmu_phandle_args { |
| 482 | struct device_node *np; |
| 483 | int args_count; |
| 484 | uint32_t args[MAX_MASTER_STREAMIDS]; |
| 485 | }; |
| 486 | |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 487 | static DEFINE_SPINLOCK(arm_smmu_devices_lock); |
| 488 | static LIST_HEAD(arm_smmu_devices); |
| 489 | |
Andreas Herrmann | 3a5df8f | 2014-01-30 18:18:04 +0000 | [diff] [blame] | 490 | struct arm_smmu_option_prop { |
| 491 | u32 opt; |
| 492 | const char *prop; |
| 493 | }; |
| 494 | |
Tirumalesh Chalamarla | 1bd37a6 | 2016-03-04 13:56:09 -0800 | [diff] [blame] | 495 | static atomic_t cavium_smmu_context_count = ATOMIC_INIT(0); |
| 496 | |
Mitchel Humpherys | 2907320 | 2014-07-08 09:52:18 -0700 | [diff] [blame] | 497 | static struct arm_smmu_option_prop arm_smmu_options[] = { |
Andreas Herrmann | 3a5df8f | 2014-01-30 18:18:04 +0000 | [diff] [blame] | 498 | { ARM_SMMU_OPT_SECURE_CFG_ACCESS, "calxeda,smmu-secure-config-access" }, |
Mitchel Humpherys | 07ba44b | 2015-01-30 14:58:52 -0800 | [diff] [blame] | 499 | { ARM_SMMU_OPT_FATAL_ASF, "qcom,fatal-asf" }, |
Mitchel Humpherys | 9c2f648 | 2015-01-13 15:28:40 -0800 | [diff] [blame] | 500 | { ARM_SMMU_OPT_SKIP_INIT, "qcom,skip-init" }, |
Patrick Daly | c190d93 | 2016-08-30 17:23:28 -0700 | [diff] [blame] | 501 | { ARM_SMMU_OPT_DYNAMIC, "qcom,dynamic" }, |
Andreas Herrmann | 3a5df8f | 2014-01-30 18:18:04 +0000 | [diff] [blame] | 502 | { 0, NULL}, |
| 503 | }; |
| 504 | |
Mitchel Humpherys | 0ed5da6 | 2014-12-04 11:47:49 -0800 | [diff] [blame] | 505 | static int arm_smmu_halt(struct arm_smmu_device *smmu); |
Patrick Daly | d54eafd | 2016-08-23 17:01:43 -0700 | [diff] [blame] | 506 | static int arm_smmu_halt_nowait(struct arm_smmu_device *smmu); |
| 507 | static int arm_smmu_wait_for_halt(struct arm_smmu_device *smmu); |
Mitchel Humpherys | 0ed5da6 | 2014-12-04 11:47:49 -0800 | [diff] [blame] | 508 | static void arm_smmu_resume(struct arm_smmu_device *smmu); |
Mitchel Humpherys | b8be413 | 2015-02-06 14:25:10 -0800 | [diff] [blame] | 509 | static phys_addr_t arm_smmu_iova_to_phys(struct iommu_domain *domain, |
| 510 | dma_addr_t iova); |
Patrick Daly | d54eafd | 2016-08-23 17:01:43 -0700 | [diff] [blame] | 511 | static phys_addr_t arm_smmu_iova_to_phys_hard(struct iommu_domain *domain, |
| 512 | dma_addr_t iova); |
| 513 | static phys_addr_t arm_smmu_iova_to_phys_hard_no_halt( |
| 514 | struct iommu_domain *domain, dma_addr_t iova); |
Jeremy Gebben | fa24b0c | 2015-06-16 12:45:31 -0600 | [diff] [blame] | 515 | static void arm_smmu_destroy_domain_context(struct iommu_domain *domain); |
Mitchel Humpherys | 0ed5da6 | 2014-12-04 11:47:49 -0800 | [diff] [blame] | 516 | |
Patrick Daly | c11d108 | 2016-09-01 15:52:44 -0700 | [diff] [blame] | 517 | static int arm_smmu_prepare_pgtable(void *addr, void *cookie); |
| 518 | static void arm_smmu_unprepare_pgtable(void *cookie, void *addr, size_t size); |
Patrick Daly | e271f21 | 2016-10-04 13:24:49 -0700 | [diff] [blame] | 519 | static int arm_smmu_assign_table(struct arm_smmu_domain *smmu_domain); |
Patrick Daly | c11d108 | 2016-09-01 15:52:44 -0700 | [diff] [blame] | 520 | static void arm_smmu_unassign_table(struct arm_smmu_domain *smmu_domain); |
| 521 | |
Joerg Roedel | 1d67263 | 2015-03-26 13:43:10 +0100 | [diff] [blame] | 522 | static struct arm_smmu_domain *to_smmu_domain(struct iommu_domain *dom) |
| 523 | { |
| 524 | return container_of(dom, struct arm_smmu_domain, domain); |
| 525 | } |
| 526 | |
Andreas Herrmann | 3a5df8f | 2014-01-30 18:18:04 +0000 | [diff] [blame] | 527 | static void parse_driver_options(struct arm_smmu_device *smmu) |
| 528 | { |
| 529 | int i = 0; |
Mitchel Humpherys | 2907320 | 2014-07-08 09:52:18 -0700 | [diff] [blame] | 530 | |
Andreas Herrmann | 3a5df8f | 2014-01-30 18:18:04 +0000 | [diff] [blame] | 531 | do { |
| 532 | if (of_property_read_bool(smmu->dev->of_node, |
| 533 | arm_smmu_options[i].prop)) { |
| 534 | smmu->options |= arm_smmu_options[i].opt; |
Mitchel Humpherys | ba82258 | 2015-10-20 11:37:41 -0700 | [diff] [blame] | 535 | dev_dbg(smmu->dev, "option %s\n", |
Andreas Herrmann | 3a5df8f | 2014-01-30 18:18:04 +0000 | [diff] [blame] | 536 | arm_smmu_options[i].prop); |
| 537 | } |
| 538 | } while (arm_smmu_options[++i].opt); |
| 539 | } |
| 540 | |
Patrick Daly | c190d93 | 2016-08-30 17:23:28 -0700 | [diff] [blame] | 541 | static bool is_dynamic_domain(struct iommu_domain *domain) |
| 542 | { |
| 543 | struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); |
| 544 | |
| 545 | return !!(smmu_domain->attributes & (1 << DOMAIN_ATTR_DYNAMIC)); |
| 546 | } |
| 547 | |
Patrick Daly | e271f21 | 2016-10-04 13:24:49 -0700 | [diff] [blame] | 548 | static bool arm_smmu_is_domain_secure(struct arm_smmu_domain *smmu_domain) |
| 549 | { |
| 550 | return (smmu_domain->secure_vmid != VMID_INVAL); |
| 551 | } |
| 552 | |
| 553 | static void arm_smmu_secure_domain_lock(struct arm_smmu_domain *smmu_domain) |
| 554 | { |
| 555 | if (arm_smmu_is_domain_secure(smmu_domain)) |
| 556 | mutex_lock(&smmu_domain->assign_lock); |
| 557 | } |
| 558 | |
| 559 | static void arm_smmu_secure_domain_unlock(struct arm_smmu_domain *smmu_domain) |
| 560 | { |
| 561 | if (arm_smmu_is_domain_secure(smmu_domain)) |
| 562 | mutex_unlock(&smmu_domain->assign_lock); |
| 563 | } |
| 564 | |
Will Deacon | 8f68f8e | 2014-07-15 11:27:08 +0100 | [diff] [blame] | 565 | static struct device_node *dev_get_dev_node(struct device *dev) |
Will Deacon | a9a1b0b | 2014-05-01 18:05:08 +0100 | [diff] [blame] | 566 | { |
| 567 | if (dev_is_pci(dev)) { |
| 568 | struct pci_bus *bus = to_pci_dev(dev)->bus; |
Mitchel Humpherys | 2907320 | 2014-07-08 09:52:18 -0700 | [diff] [blame] | 569 | |
Will Deacon | a9a1b0b | 2014-05-01 18:05:08 +0100 | [diff] [blame] | 570 | while (!pci_is_root_bus(bus)) |
| 571 | bus = bus->parent; |
Will Deacon | 8f68f8e | 2014-07-15 11:27:08 +0100 | [diff] [blame] | 572 | return bus->bridge->parent->of_node; |
Will Deacon | a9a1b0b | 2014-05-01 18:05:08 +0100 | [diff] [blame] | 573 | } |
| 574 | |
Will Deacon | 8f68f8e | 2014-07-15 11:27:08 +0100 | [diff] [blame] | 575 | return dev->of_node; |
Will Deacon | a9a1b0b | 2014-05-01 18:05:08 +0100 | [diff] [blame] | 576 | } |
| 577 | |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 578 | static struct arm_smmu_master *find_smmu_master(struct arm_smmu_device *smmu, |
| 579 | struct device_node *dev_node) |
| 580 | { |
| 581 | struct rb_node *node = smmu->masters.rb_node; |
| 582 | |
| 583 | while (node) { |
| 584 | struct arm_smmu_master *master; |
Mitchel Humpherys | 2907320 | 2014-07-08 09:52:18 -0700 | [diff] [blame] | 585 | |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 586 | master = container_of(node, struct arm_smmu_master, node); |
| 587 | |
| 588 | if (dev_node < master->of_node) |
| 589 | node = node->rb_left; |
| 590 | else if (dev_node > master->of_node) |
| 591 | node = node->rb_right; |
| 592 | else |
| 593 | return master; |
| 594 | } |
| 595 | |
| 596 | return NULL; |
| 597 | } |
| 598 | |
Will Deacon | a9a1b0b | 2014-05-01 18:05:08 +0100 | [diff] [blame] | 599 | static struct arm_smmu_master_cfg * |
Will Deacon | 8f68f8e | 2014-07-15 11:27:08 +0100 | [diff] [blame] | 600 | find_smmu_master_cfg(struct device *dev) |
Will Deacon | a9a1b0b | 2014-05-01 18:05:08 +0100 | [diff] [blame] | 601 | { |
Will Deacon | 8f68f8e | 2014-07-15 11:27:08 +0100 | [diff] [blame] | 602 | struct arm_smmu_master_cfg *cfg = NULL; |
| 603 | struct iommu_group *group = iommu_group_get(dev); |
Will Deacon | a9a1b0b | 2014-05-01 18:05:08 +0100 | [diff] [blame] | 604 | |
Will Deacon | 8f68f8e | 2014-07-15 11:27:08 +0100 | [diff] [blame] | 605 | if (group) { |
| 606 | cfg = iommu_group_get_iommudata(group); |
| 607 | iommu_group_put(group); |
| 608 | } |
Will Deacon | a9a1b0b | 2014-05-01 18:05:08 +0100 | [diff] [blame] | 609 | |
Will Deacon | 8f68f8e | 2014-07-15 11:27:08 +0100 | [diff] [blame] | 610 | return cfg; |
Will Deacon | a9a1b0b | 2014-05-01 18:05:08 +0100 | [diff] [blame] | 611 | } |
| 612 | |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 613 | static int insert_smmu_master(struct arm_smmu_device *smmu, |
| 614 | struct arm_smmu_master *master) |
| 615 | { |
| 616 | struct rb_node **new, *parent; |
| 617 | |
| 618 | new = &smmu->masters.rb_node; |
| 619 | parent = NULL; |
| 620 | while (*new) { |
Mitchel Humpherys | 2907320 | 2014-07-08 09:52:18 -0700 | [diff] [blame] | 621 | struct arm_smmu_master *this |
| 622 | = container_of(*new, struct arm_smmu_master, node); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 623 | |
| 624 | parent = *new; |
| 625 | if (master->of_node < this->of_node) |
| 626 | new = &((*new)->rb_left); |
| 627 | else if (master->of_node > this->of_node) |
| 628 | new = &((*new)->rb_right); |
| 629 | else |
| 630 | return -EEXIST; |
| 631 | } |
| 632 | |
| 633 | rb_link_node(&master->node, parent, new); |
| 634 | rb_insert_color(&master->node, &smmu->masters); |
| 635 | return 0; |
| 636 | } |
| 637 | |
Mitchel Humpherys | c6dd1ed | 2014-08-04 16:45:53 -0700 | [diff] [blame] | 638 | struct iommus_entry { |
| 639 | struct list_head list; |
| 640 | struct device_node *node; |
| 641 | u16 streamids[MAX_MASTER_STREAMIDS]; |
| 642 | int num_sids; |
| 643 | }; |
| 644 | |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 645 | static int register_smmu_master(struct arm_smmu_device *smmu, |
Mitchel Humpherys | c6dd1ed | 2014-08-04 16:45:53 -0700 | [diff] [blame] | 646 | struct iommus_entry *entry) |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 647 | { |
| 648 | int i; |
| 649 | struct arm_smmu_master *master; |
Mitchel Humpherys | c6dd1ed | 2014-08-04 16:45:53 -0700 | [diff] [blame] | 650 | struct device *dev = smmu->dev; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 651 | |
Mitchel Humpherys | c6dd1ed | 2014-08-04 16:45:53 -0700 | [diff] [blame] | 652 | master = find_smmu_master(smmu, entry->node); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 653 | if (master) { |
| 654 | dev_err(dev, |
| 655 | "rejecting multiple registrations for master device %s\n", |
Mitchel Humpherys | c6dd1ed | 2014-08-04 16:45:53 -0700 | [diff] [blame] | 656 | entry->node->name); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 657 | return -EBUSY; |
| 658 | } |
| 659 | |
Mitchel Humpherys | c6dd1ed | 2014-08-04 16:45:53 -0700 | [diff] [blame] | 660 | if (entry->num_sids > MAX_MASTER_STREAMIDS) { |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 661 | dev_err(dev, |
| 662 | "reached maximum number (%d) of stream IDs for master device %s\n", |
Mitchel Humpherys | c6dd1ed | 2014-08-04 16:45:53 -0700 | [diff] [blame] | 663 | MAX_MASTER_STREAMIDS, entry->node->name); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 664 | return -ENOSPC; |
| 665 | } |
| 666 | |
| 667 | master = devm_kzalloc(dev, sizeof(*master), GFP_KERNEL); |
| 668 | if (!master) |
| 669 | return -ENOMEM; |
| 670 | |
Mitchel Humpherys | c6dd1ed | 2014-08-04 16:45:53 -0700 | [diff] [blame] | 671 | master->of_node = entry->node; |
| 672 | master->cfg.num_streamids = entry->num_sids; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 673 | |
Olav Haugan | 3c8766d | 2014-08-22 17:12:32 -0700 | [diff] [blame] | 674 | for (i = 0; i < master->cfg.num_streamids; ++i) { |
Mitchel Humpherys | c6dd1ed | 2014-08-04 16:45:53 -0700 | [diff] [blame] | 675 | u16 streamid = entry->streamids[i]; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 676 | |
Olav Haugan | 3c8766d | 2014-08-22 17:12:32 -0700 | [diff] [blame] | 677 | if (!(smmu->features & ARM_SMMU_FEAT_STREAM_MATCH) && |
| 678 | (streamid >= smmu->num_mapping_groups)) { |
| 679 | dev_err(dev, |
| 680 | "stream ID for master device %s greater than maximum allowed (%d)\n", |
Mitchel Humpherys | c6dd1ed | 2014-08-04 16:45:53 -0700 | [diff] [blame] | 681 | entry->node->name, smmu->num_mapping_groups); |
Olav Haugan | 3c8766d | 2014-08-22 17:12:32 -0700 | [diff] [blame] | 682 | return -ERANGE; |
| 683 | } |
| 684 | master->cfg.streamids[i] = streamid; |
| 685 | } |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 686 | return insert_smmu_master(smmu, master); |
| 687 | } |
| 688 | |
Mitchel Humpherys | c6dd1ed | 2014-08-04 16:45:53 -0700 | [diff] [blame] | 689 | static int arm_smmu_parse_iommus_properties(struct arm_smmu_device *smmu, |
| 690 | int *num_masters) |
| 691 | { |
| 692 | struct of_phandle_args iommuspec; |
| 693 | struct device_node *master; |
| 694 | |
| 695 | *num_masters = 0; |
| 696 | |
| 697 | for_each_node_with_property(master, "iommus") { |
| 698 | int arg_ind = 0; |
| 699 | struct iommus_entry *entry, *n; |
| 700 | LIST_HEAD(iommus); |
| 701 | |
| 702 | while (!of_parse_phandle_with_args( |
| 703 | master, "iommus", "#iommu-cells", |
| 704 | arg_ind, &iommuspec)) { |
| 705 | if (iommuspec.np != smmu->dev->of_node) { |
| 706 | arg_ind++; |
| 707 | continue; |
| 708 | } |
| 709 | |
| 710 | list_for_each_entry(entry, &iommus, list) |
| 711 | if (entry->node == master) |
| 712 | break; |
| 713 | if (&entry->list == &iommus) { |
| 714 | entry = devm_kzalloc(smmu->dev, sizeof(*entry), |
| 715 | GFP_KERNEL); |
| 716 | if (!entry) |
| 717 | return -ENOMEM; |
| 718 | entry->node = master; |
| 719 | list_add(&entry->list, &iommus); |
| 720 | } |
Patrick Daly | a571f73 | 2016-09-26 15:12:36 -0700 | [diff] [blame] | 721 | switch (iommuspec.args_count) { |
| 722 | case 0: |
| 723 | /* |
| 724 | * For pci-e devices the SIDs are provided |
| 725 | * at device attach time. |
| 726 | */ |
| 727 | break; |
| 728 | case 1: |
| 729 | entry->num_sids++; |
| 730 | entry->streamids[entry->num_sids - 1] |
| 731 | = iommuspec.args[0]; |
| 732 | break; |
| 733 | default: |
Mitchel Humpherys | c6dd1ed | 2014-08-04 16:45:53 -0700 | [diff] [blame] | 734 | dev_err(smmu->dev, "iommus property has wrong #iommu-cells"); |
| 735 | return -EINVAL; |
| 736 | } |
Mitchel Humpherys | c6dd1ed | 2014-08-04 16:45:53 -0700 | [diff] [blame] | 737 | arg_ind++; |
| 738 | } |
| 739 | |
| 740 | list_for_each_entry_safe(entry, n, &iommus, list) { |
Mitchel Humpherys | 4c77560 | 2014-10-02 17:55:41 -0700 | [diff] [blame] | 741 | int rc = register_smmu_master(smmu, entry); |
| 742 | |
| 743 | if (rc) { |
| 744 | dev_err(smmu->dev, "Couldn't register %s\n", |
| 745 | entry->node->name); |
| 746 | } else { |
| 747 | (*num_masters)++; |
| 748 | } |
Mitchel Humpherys | c6dd1ed | 2014-08-04 16:45:53 -0700 | [diff] [blame] | 749 | list_del(&entry->list); |
| 750 | devm_kfree(smmu->dev, entry); |
| 751 | } |
| 752 | } |
| 753 | |
| 754 | return 0; |
| 755 | } |
| 756 | |
Will Deacon | 44680ee | 2014-06-25 11:29:12 +0100 | [diff] [blame] | 757 | static struct arm_smmu_device *find_smmu_for_device(struct device *dev) |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 758 | { |
Will Deacon | 44680ee | 2014-06-25 11:29:12 +0100 | [diff] [blame] | 759 | struct arm_smmu_device *smmu; |
Will Deacon | a9a1b0b | 2014-05-01 18:05:08 +0100 | [diff] [blame] | 760 | struct arm_smmu_master *master = NULL; |
Will Deacon | 8f68f8e | 2014-07-15 11:27:08 +0100 | [diff] [blame] | 761 | struct device_node *dev_node = dev_get_dev_node(dev); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 762 | |
| 763 | spin_lock(&arm_smmu_devices_lock); |
Will Deacon | 44680ee | 2014-06-25 11:29:12 +0100 | [diff] [blame] | 764 | list_for_each_entry(smmu, &arm_smmu_devices, list) { |
Will Deacon | a9a1b0b | 2014-05-01 18:05:08 +0100 | [diff] [blame] | 765 | master = find_smmu_master(smmu, dev_node); |
| 766 | if (master) |
| 767 | break; |
| 768 | } |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 769 | spin_unlock(&arm_smmu_devices_lock); |
Will Deacon | 44680ee | 2014-06-25 11:29:12 +0100 | [diff] [blame] | 770 | |
Will Deacon | a9a1b0b | 2014-05-01 18:05:08 +0100 | [diff] [blame] | 771 | return master ? smmu : NULL; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 772 | } |
| 773 | |
| 774 | static int __arm_smmu_alloc_bitmap(unsigned long *map, int start, int end) |
| 775 | { |
| 776 | int idx; |
| 777 | |
| 778 | do { |
| 779 | idx = find_next_zero_bit(map, end, start); |
| 780 | if (idx == end) |
| 781 | return -ENOSPC; |
| 782 | } while (test_and_set_bit(idx, map)); |
| 783 | |
| 784 | return idx; |
| 785 | } |
| 786 | |
| 787 | static void __arm_smmu_free_bitmap(unsigned long *map, int idx) |
| 788 | { |
| 789 | clear_bit(idx, map); |
| 790 | } |
| 791 | |
Patrick Daly | 8befb66 | 2016-08-17 20:03:28 -0700 | [diff] [blame] | 792 | static int arm_smmu_prepare_clocks(struct arm_smmu_device *smmu) |
Patrick Daly | 3a8a88a | 2016-07-22 12:24:05 -0700 | [diff] [blame] | 793 | { |
| 794 | int i, ret = 0; |
| 795 | |
| 796 | for (i = 0; i < smmu->num_clocks; ++i) { |
Patrick Daly | 8befb66 | 2016-08-17 20:03:28 -0700 | [diff] [blame] | 797 | ret = clk_prepare(smmu->clocks[i]); |
Patrick Daly | 3a8a88a | 2016-07-22 12:24:05 -0700 | [diff] [blame] | 798 | if (ret) { |
Patrick Daly | 8befb66 | 2016-08-17 20:03:28 -0700 | [diff] [blame] | 799 | dev_err(smmu->dev, "Couldn't prepare clock #%d\n", i); |
Patrick Daly | 3a8a88a | 2016-07-22 12:24:05 -0700 | [diff] [blame] | 800 | while (i--) |
Patrick Daly | 8befb66 | 2016-08-17 20:03:28 -0700 | [diff] [blame] | 801 | clk_unprepare(smmu->clocks[i]); |
Patrick Daly | 3a8a88a | 2016-07-22 12:24:05 -0700 | [diff] [blame] | 802 | break; |
| 803 | } |
| 804 | } |
Patrick Daly | 3a8a88a | 2016-07-22 12:24:05 -0700 | [diff] [blame] | 805 | return ret; |
| 806 | } |
| 807 | |
Patrick Daly | 8befb66 | 2016-08-17 20:03:28 -0700 | [diff] [blame] | 808 | static void arm_smmu_unprepare_clocks(struct arm_smmu_device *smmu) |
Patrick Daly | 3a8a88a | 2016-07-22 12:24:05 -0700 | [diff] [blame] | 809 | { |
| 810 | int i; |
| 811 | |
Liam Mark | 3ddf8d1 | 2016-04-13 12:42:01 -0700 | [diff] [blame] | 812 | for (i = smmu->num_clocks; i; --i) |
| 813 | clk_unprepare(smmu->clocks[i - 1]); |
Patrick Daly | 3a8a88a | 2016-07-22 12:24:05 -0700 | [diff] [blame] | 814 | } |
| 815 | |
Patrick Daly | 8befb66 | 2016-08-17 20:03:28 -0700 | [diff] [blame] | 816 | /* Clocks must be prepared before this (arm_smmu_prepare_clocks) */ |
| 817 | static int arm_smmu_enable_clocks_atomic(struct arm_smmu_device *smmu) |
| 818 | { |
| 819 | int i, ret = 0; |
| 820 | unsigned long flags; |
| 821 | |
| 822 | spin_lock_irqsave(&smmu->clock_refs_lock, flags); |
| 823 | if (smmu->clock_refs_count > 0) { |
| 824 | smmu->clock_refs_count++; |
| 825 | spin_unlock_irqrestore(&smmu->clock_refs_lock, flags); |
| 826 | return 0; |
| 827 | } |
| 828 | |
| 829 | for (i = 0; i < smmu->num_clocks; ++i) { |
| 830 | ret = clk_enable(smmu->clocks[i]); |
| 831 | if (ret) { |
| 832 | dev_err(smmu->dev, "Couldn't enable clock #%d\n", i); |
| 833 | while (i--) |
| 834 | clk_disable(smmu->clocks[i]); |
| 835 | break; |
| 836 | } |
| 837 | } |
| 838 | |
| 839 | if (!ret) |
| 840 | smmu->clock_refs_count++; |
| 841 | |
| 842 | spin_unlock_irqrestore(&smmu->clock_refs_lock, flags); |
| 843 | return ret; |
| 844 | } |
| 845 | |
| 846 | /* Clocks should be unprepared after this (arm_smmu_unprepare_clocks) */ |
| 847 | static void arm_smmu_disable_clocks_atomic(struct arm_smmu_device *smmu) |
| 848 | { |
| 849 | int i; |
| 850 | unsigned long flags; |
| 851 | |
| 852 | spin_lock_irqsave(&smmu->clock_refs_lock, flags); |
| 853 | WARN_ON(smmu->clock_refs_count == 0); |
| 854 | if (smmu->clock_refs_count > 1) { |
| 855 | smmu->clock_refs_count--; |
| 856 | spin_unlock_irqrestore(&smmu->clock_refs_lock, flags); |
| 857 | return; |
| 858 | } |
| 859 | |
Liam Mark | 3ddf8d1 | 2016-04-13 12:42:01 -0700 | [diff] [blame] | 860 | for (i = smmu->num_clocks; i; --i) |
| 861 | clk_disable(smmu->clocks[i - 1]); |
Patrick Daly | 8befb66 | 2016-08-17 20:03:28 -0700 | [diff] [blame] | 862 | |
| 863 | smmu->clock_refs_count--; |
| 864 | spin_unlock_irqrestore(&smmu->clock_refs_lock, flags); |
| 865 | } |
| 866 | |
Mitchel Humpherys | f7666ae | 2014-07-23 17:35:07 -0700 | [diff] [blame] | 867 | static int arm_smmu_enable_regulators(struct arm_smmu_device *smmu) |
| 868 | { |
| 869 | if (!smmu->gdsc) |
| 870 | return 0; |
| 871 | |
| 872 | return regulator_enable(smmu->gdsc); |
| 873 | } |
| 874 | |
| 875 | static int arm_smmu_disable_regulators(struct arm_smmu_device *smmu) |
| 876 | { |
| 877 | if (!smmu->gdsc) |
| 878 | return 0; |
| 879 | |
| 880 | return regulator_disable(smmu->gdsc); |
| 881 | } |
| 882 | |
Patrick Daly | 2764f95 | 2016-09-06 19:22:44 -0700 | [diff] [blame] | 883 | static int arm_smmu_request_bus(struct arm_smmu_device *smmu) |
| 884 | { |
| 885 | if (!smmu->bus_client) |
| 886 | return 0; |
| 887 | return msm_bus_scale_update_bw(smmu->bus_client, 0, 1000); |
| 888 | } |
| 889 | |
| 890 | static int arm_smmu_unrequest_bus(struct arm_smmu_device *smmu) |
| 891 | { |
| 892 | if (!smmu->bus_client) |
| 893 | return 0; |
| 894 | return msm_bus_scale_update_bw(smmu->bus_client, 0, 0); |
| 895 | } |
| 896 | |
| 897 | |
Patrick Daly | 8befb66 | 2016-08-17 20:03:28 -0700 | [diff] [blame] | 898 | static int arm_smmu_power_on_slow(struct arm_smmu_device *smmu) |
Patrick Daly | 3a8a88a | 2016-07-22 12:24:05 -0700 | [diff] [blame] | 899 | { |
| 900 | int ret; |
| 901 | |
| 902 | mutex_lock(&smmu->power_lock); |
| 903 | if (smmu->power_count > 0) { |
| 904 | smmu->power_count += 1; |
| 905 | mutex_unlock(&smmu->power_lock); |
| 906 | return 0; |
| 907 | } |
| 908 | |
Mitchel Humpherys | f7666ae | 2014-07-23 17:35:07 -0700 | [diff] [blame] | 909 | ret = arm_smmu_enable_regulators(smmu); |
| 910 | if (ret) |
| 911 | goto out_unlock; |
| 912 | |
Patrick Daly | 2764f95 | 2016-09-06 19:22:44 -0700 | [diff] [blame] | 913 | ret = arm_smmu_request_bus(smmu); |
Mitchel Humpherys | f7666ae | 2014-07-23 17:35:07 -0700 | [diff] [blame] | 914 | if (ret) |
| 915 | goto out_disable_regulators; |
Patrick Daly | 3a8a88a | 2016-07-22 12:24:05 -0700 | [diff] [blame] | 916 | |
Patrick Daly | 2764f95 | 2016-09-06 19:22:44 -0700 | [diff] [blame] | 917 | ret = arm_smmu_prepare_clocks(smmu); |
| 918 | if (ret) |
| 919 | goto out_disable_bus; |
| 920 | |
Mitchel Humpherys | f7666ae | 2014-07-23 17:35:07 -0700 | [diff] [blame] | 921 | smmu->power_count += 1; |
Patrick Daly | 3a8a88a | 2016-07-22 12:24:05 -0700 | [diff] [blame] | 922 | mutex_unlock(&smmu->power_lock); |
Mitchel Humpherys | f7666ae | 2014-07-23 17:35:07 -0700 | [diff] [blame] | 923 | return 0; |
Patrick Daly | 3a8a88a | 2016-07-22 12:24:05 -0700 | [diff] [blame] | 924 | |
Patrick Daly | 2764f95 | 2016-09-06 19:22:44 -0700 | [diff] [blame] | 925 | out_disable_bus: |
| 926 | arm_smmu_unrequest_bus(smmu); |
Mitchel Humpherys | f7666ae | 2014-07-23 17:35:07 -0700 | [diff] [blame] | 927 | out_disable_regulators: |
| 928 | arm_smmu_disable_regulators(smmu); |
| 929 | out_unlock: |
| 930 | mutex_unlock(&smmu->power_lock); |
Patrick Daly | 3a8a88a | 2016-07-22 12:24:05 -0700 | [diff] [blame] | 931 | return ret; |
| 932 | } |
| 933 | |
Patrick Daly | 8befb66 | 2016-08-17 20:03:28 -0700 | [diff] [blame] | 934 | static void arm_smmu_power_off_slow(struct arm_smmu_device *smmu) |
Patrick Daly | 3a8a88a | 2016-07-22 12:24:05 -0700 | [diff] [blame] | 935 | { |
| 936 | mutex_lock(&smmu->power_lock); |
| 937 | smmu->power_count--; |
| 938 | WARN_ON(smmu->power_count < 0); |
| 939 | |
| 940 | if (smmu->power_count > 0) { |
| 941 | mutex_unlock(&smmu->power_lock); |
| 942 | return; |
| 943 | } |
| 944 | |
Patrick Daly | 8befb66 | 2016-08-17 20:03:28 -0700 | [diff] [blame] | 945 | arm_smmu_unprepare_clocks(smmu); |
Patrick Daly | 2764f95 | 2016-09-06 19:22:44 -0700 | [diff] [blame] | 946 | arm_smmu_unrequest_bus(smmu); |
Mitchel Humpherys | f7666ae | 2014-07-23 17:35:07 -0700 | [diff] [blame] | 947 | arm_smmu_disable_regulators(smmu); |
Patrick Daly | 3a8a88a | 2016-07-22 12:24:05 -0700 | [diff] [blame] | 948 | |
| 949 | mutex_unlock(&smmu->power_lock); |
| 950 | } |
| 951 | |
Patrick Daly | 8befb66 | 2016-08-17 20:03:28 -0700 | [diff] [blame] | 952 | static int arm_smmu_power_on(struct arm_smmu_device *smmu) |
| 953 | { |
| 954 | int ret; |
| 955 | |
| 956 | ret = arm_smmu_power_on_slow(smmu); |
| 957 | if (ret) |
| 958 | return ret; |
| 959 | |
| 960 | ret = arm_smmu_enable_clocks_atomic(smmu); |
| 961 | if (ret) |
| 962 | goto out_disable; |
| 963 | |
| 964 | return 0; |
| 965 | |
| 966 | out_disable: |
| 967 | arm_smmu_power_off_slow(smmu); |
| 968 | return ret; |
| 969 | } |
| 970 | |
| 971 | static void arm_smmu_power_off(struct arm_smmu_device *smmu) |
| 972 | { |
| 973 | arm_smmu_disable_clocks_atomic(smmu); |
| 974 | arm_smmu_power_off_slow(smmu); |
| 975 | } |
| 976 | |
| 977 | /* |
| 978 | * Must be used instead of arm_smmu_power_on if it may be called from |
| 979 | * atomic context |
| 980 | */ |
| 981 | static int arm_smmu_domain_power_on(struct iommu_domain *domain, |
| 982 | struct arm_smmu_device *smmu) |
| 983 | { |
| 984 | struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); |
| 985 | int atomic_domain = smmu_domain->attributes & (1 << DOMAIN_ATTR_ATOMIC); |
| 986 | |
| 987 | if (atomic_domain) |
| 988 | return arm_smmu_enable_clocks_atomic(smmu); |
| 989 | |
| 990 | return arm_smmu_power_on(smmu); |
| 991 | } |
| 992 | |
| 993 | /* |
| 994 | * Must be used instead of arm_smmu_power_on if it may be called from |
| 995 | * atomic context |
| 996 | */ |
| 997 | static void arm_smmu_domain_power_off(struct iommu_domain *domain, |
| 998 | struct arm_smmu_device *smmu) |
| 999 | { |
| 1000 | struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); |
| 1001 | int atomic_domain = smmu_domain->attributes & (1 << DOMAIN_ATTR_ATOMIC); |
| 1002 | |
| 1003 | if (atomic_domain) { |
| 1004 | arm_smmu_disable_clocks_atomic(smmu); |
| 1005 | return; |
| 1006 | } |
| 1007 | |
| 1008 | arm_smmu_power_off(smmu); |
| 1009 | } |
| 1010 | |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1011 | /* Wait for any pending TLB invalidations to complete */ |
Mitchel Humpherys | f300799 | 2015-06-19 15:00:14 -0700 | [diff] [blame] | 1012 | static void arm_smmu_tlb_sync_cb(struct arm_smmu_device *smmu, |
| 1013 | int cbndx) |
| 1014 | { |
| 1015 | void __iomem *base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cbndx); |
| 1016 | u32 val; |
| 1017 | |
| 1018 | writel_relaxed(0, base + ARM_SMMU_CB_TLBSYNC); |
| 1019 | if (readl_poll_timeout_atomic(base + ARM_SMMU_CB_TLBSTATUS, val, |
| 1020 | !(val & TLBSTATUS_SACTIVE), |
Mitchel Humpherys | 9b1b894 | 2015-06-25 18:17:15 -0700 | [diff] [blame] | 1021 | 0, TLB_LOOP_TIMEOUT)) |
Mitchel Humpherys | f300799 | 2015-06-19 15:00:14 -0700 | [diff] [blame] | 1022 | dev_err(smmu->dev, "TLBSYNC timeout!\n"); |
| 1023 | } |
| 1024 | |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame] | 1025 | static void __arm_smmu_tlb_sync(struct arm_smmu_device *smmu) |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1026 | { |
| 1027 | int count = 0; |
| 1028 | void __iomem *gr0_base = ARM_SMMU_GR0(smmu); |
| 1029 | |
| 1030 | writel_relaxed(0, gr0_base + ARM_SMMU_GR0_sTLBGSYNC); |
| 1031 | while (readl_relaxed(gr0_base + ARM_SMMU_GR0_sTLBGSTATUS) |
| 1032 | & sTLBGSTATUS_GSACTIVE) { |
| 1033 | cpu_relax(); |
| 1034 | if (++count == TLB_LOOP_TIMEOUT) { |
| 1035 | dev_err_ratelimited(smmu->dev, |
| 1036 | "TLB sync timed out -- SMMU may be deadlocked\n"); |
| 1037 | return; |
| 1038 | } |
| 1039 | udelay(1); |
| 1040 | } |
| 1041 | } |
| 1042 | |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame] | 1043 | static void arm_smmu_tlb_sync(void *cookie) |
Will Deacon | 1463fe4 | 2013-07-31 19:21:27 +0100 | [diff] [blame] | 1044 | { |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame] | 1045 | struct arm_smmu_domain *smmu_domain = cookie; |
Mitchel Humpherys | f300799 | 2015-06-19 15:00:14 -0700 | [diff] [blame] | 1046 | arm_smmu_tlb_sync_cb(smmu_domain->smmu, smmu_domain->cfg.cbndx); |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame] | 1047 | } |
| 1048 | |
Patrick Daly | 8befb66 | 2016-08-17 20:03:28 -0700 | [diff] [blame] | 1049 | /* Must be called with clocks/regulators enabled */ |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame] | 1050 | static void arm_smmu_tlb_inv_context(void *cookie) |
| 1051 | { |
| 1052 | struct arm_smmu_domain *smmu_domain = cookie; |
Will Deacon | 44680ee | 2014-06-25 11:29:12 +0100 | [diff] [blame] | 1053 | struct arm_smmu_cfg *cfg = &smmu_domain->cfg; |
| 1054 | struct arm_smmu_device *smmu = smmu_domain->smmu; |
Will Deacon | 1463fe4 | 2013-07-31 19:21:27 +0100 | [diff] [blame] | 1055 | bool stage1 = cfg->cbar != CBAR_TYPE_S2_TRANS; |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame] | 1056 | void __iomem *base; |
Will Deacon | 1463fe4 | 2013-07-31 19:21:27 +0100 | [diff] [blame] | 1057 | |
| 1058 | if (stage1) { |
| 1059 | base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx); |
Tirumalesh Chalamarla | 1bd37a6 | 2016-03-04 13:56:09 -0800 | [diff] [blame] | 1060 | writel_relaxed(ARM_SMMU_CB_ASID(smmu, cfg), |
Will Deacon | ecfadb6 | 2013-07-31 19:21:28 +0100 | [diff] [blame] | 1061 | base + ARM_SMMU_CB_S1_TLBIASID); |
Mitchel Humpherys | f300799 | 2015-06-19 15:00:14 -0700 | [diff] [blame] | 1062 | arm_smmu_tlb_sync_cb(smmu, cfg->cbndx); |
Will Deacon | 1463fe4 | 2013-07-31 19:21:27 +0100 | [diff] [blame] | 1063 | } else { |
| 1064 | base = ARM_SMMU_GR0(smmu); |
Tirumalesh Chalamarla | 1bd37a6 | 2016-03-04 13:56:09 -0800 | [diff] [blame] | 1065 | writel_relaxed(ARM_SMMU_CB_VMID(smmu, cfg), |
Will Deacon | ecfadb6 | 2013-07-31 19:21:28 +0100 | [diff] [blame] | 1066 | base + ARM_SMMU_GR0_TLBIVMID); |
Mitchel Humpherys | f300799 | 2015-06-19 15:00:14 -0700 | [diff] [blame] | 1067 | __arm_smmu_tlb_sync(smmu); |
Will Deacon | 1463fe4 | 2013-07-31 19:21:27 +0100 | [diff] [blame] | 1068 | } |
Will Deacon | 1463fe4 | 2013-07-31 19:21:27 +0100 | [diff] [blame] | 1069 | } |
| 1070 | |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame] | 1071 | static void arm_smmu_tlb_inv_range_nosync(unsigned long iova, size_t size, |
Robin Murphy | 06c610e | 2015-12-07 18:18:53 +0000 | [diff] [blame] | 1072 | size_t granule, bool leaf, void *cookie) |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame] | 1073 | { |
| 1074 | struct arm_smmu_domain *smmu_domain = cookie; |
| 1075 | struct arm_smmu_cfg *cfg = &smmu_domain->cfg; |
| 1076 | struct arm_smmu_device *smmu = smmu_domain->smmu; |
| 1077 | bool stage1 = cfg->cbar != CBAR_TYPE_S2_TRANS; |
| 1078 | void __iomem *reg; |
| 1079 | |
| 1080 | if (stage1) { |
| 1081 | reg = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx); |
| 1082 | reg += leaf ? ARM_SMMU_CB_S1_TLBIVAL : ARM_SMMU_CB_S1_TLBIVA; |
| 1083 | |
Robin Murphy | 7602b87 | 2016-04-28 17:12:09 +0100 | [diff] [blame] | 1084 | if (cfg->fmt != ARM_SMMU_CTX_FMT_AARCH64) { |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame] | 1085 | iova &= ~12UL; |
Tirumalesh Chalamarla | 1bd37a6 | 2016-03-04 13:56:09 -0800 | [diff] [blame] | 1086 | iova |= ARM_SMMU_CB_ASID(smmu, cfg); |
Robin Murphy | 75df138 | 2015-12-07 18:18:52 +0000 | [diff] [blame] | 1087 | do { |
| 1088 | writel_relaxed(iova, reg); |
| 1089 | iova += granule; |
| 1090 | } while (size -= granule); |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame] | 1091 | } else { |
| 1092 | iova >>= 12; |
Tirumalesh Chalamarla | 1bd37a6 | 2016-03-04 13:56:09 -0800 | [diff] [blame] | 1093 | iova |= (u64)ARM_SMMU_CB_ASID(smmu, cfg) << 48; |
Robin Murphy | 75df138 | 2015-12-07 18:18:52 +0000 | [diff] [blame] | 1094 | do { |
| 1095 | writeq_relaxed(iova, reg); |
| 1096 | iova += granule >> 12; |
| 1097 | } while (size -= granule); |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame] | 1098 | } |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame] | 1099 | } else if (smmu->version == ARM_SMMU_V2) { |
| 1100 | reg = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx); |
| 1101 | reg += leaf ? ARM_SMMU_CB_S2_TLBIIPAS2L : |
| 1102 | ARM_SMMU_CB_S2_TLBIIPAS2; |
Robin Murphy | 75df138 | 2015-12-07 18:18:52 +0000 | [diff] [blame] | 1103 | iova >>= 12; |
| 1104 | do { |
Robin Murphy | f9a05f0 | 2016-04-13 18:13:01 +0100 | [diff] [blame] | 1105 | smmu_write_atomic_lq(iova, reg); |
Robin Murphy | 75df138 | 2015-12-07 18:18:52 +0000 | [diff] [blame] | 1106 | iova += granule >> 12; |
| 1107 | } while (size -= granule); |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame] | 1108 | } else { |
| 1109 | reg = ARM_SMMU_GR0(smmu) + ARM_SMMU_GR0_TLBIVMID; |
Tirumalesh Chalamarla | 1bd37a6 | 2016-03-04 13:56:09 -0800 | [diff] [blame] | 1110 | writel_relaxed(ARM_SMMU_CB_VMID(smmu, cfg), reg); |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame] | 1111 | } |
| 1112 | } |
| 1113 | |
Patrick Daly | b7dfda7 | 2016-10-04 14:42:58 -0700 | [diff] [blame] | 1114 | struct arm_smmu_secure_pool_chunk { |
| 1115 | void *addr; |
| 1116 | size_t size; |
| 1117 | struct list_head list; |
| 1118 | }; |
| 1119 | |
| 1120 | static void *arm_smmu_secure_pool_remove(struct arm_smmu_domain *smmu_domain, |
| 1121 | size_t size) |
| 1122 | { |
| 1123 | struct arm_smmu_secure_pool_chunk *it; |
| 1124 | |
| 1125 | list_for_each_entry(it, &smmu_domain->secure_pool_list, list) { |
| 1126 | if (it->size == size) { |
| 1127 | void *addr = it->addr; |
| 1128 | |
| 1129 | list_del(&it->list); |
| 1130 | kfree(it); |
| 1131 | return addr; |
| 1132 | } |
| 1133 | } |
| 1134 | |
| 1135 | return NULL; |
| 1136 | } |
| 1137 | |
| 1138 | static int arm_smmu_secure_pool_add(struct arm_smmu_domain *smmu_domain, |
| 1139 | void *addr, size_t size) |
| 1140 | { |
| 1141 | struct arm_smmu_secure_pool_chunk *chunk; |
| 1142 | |
| 1143 | chunk = kmalloc(sizeof(*chunk), GFP_ATOMIC); |
| 1144 | if (!chunk) |
| 1145 | return -ENOMEM; |
| 1146 | |
| 1147 | chunk->addr = addr; |
| 1148 | chunk->size = size; |
| 1149 | memset(addr, 0, size); |
| 1150 | list_add(&chunk->list, &smmu_domain->secure_pool_list); |
| 1151 | |
| 1152 | return 0; |
| 1153 | } |
| 1154 | |
| 1155 | static void arm_smmu_secure_pool_destroy(struct arm_smmu_domain *smmu_domain) |
| 1156 | { |
| 1157 | struct arm_smmu_secure_pool_chunk *it, *i; |
| 1158 | |
| 1159 | list_for_each_entry_safe(it, i, &smmu_domain->secure_pool_list, list) { |
| 1160 | arm_smmu_unprepare_pgtable(smmu_domain, it->addr, it->size); |
| 1161 | /* pages will be freed later (after being unassigned) */ |
| 1162 | kfree(it); |
| 1163 | } |
| 1164 | } |
| 1165 | |
Patrick Daly | c11d108 | 2016-09-01 15:52:44 -0700 | [diff] [blame] | 1166 | static void *arm_smmu_alloc_pages_exact(void *cookie, |
| 1167 | size_t size, gfp_t gfp_mask) |
| 1168 | { |
| 1169 | int ret; |
Patrick Daly | b7dfda7 | 2016-10-04 14:42:58 -0700 | [diff] [blame] | 1170 | void *page; |
| 1171 | struct arm_smmu_domain *smmu_domain = cookie; |
Patrick Daly | c11d108 | 2016-09-01 15:52:44 -0700 | [diff] [blame] | 1172 | |
Patrick Daly | b7dfda7 | 2016-10-04 14:42:58 -0700 | [diff] [blame] | 1173 | if (!arm_smmu_is_domain_secure(smmu_domain)) |
| 1174 | return alloc_pages_exact(size, gfp_mask); |
| 1175 | |
| 1176 | page = arm_smmu_secure_pool_remove(smmu_domain, size); |
| 1177 | if (page) |
| 1178 | return page; |
| 1179 | |
| 1180 | page = alloc_pages_exact(size, gfp_mask); |
| 1181 | if (page) { |
Patrick Daly | c11d108 | 2016-09-01 15:52:44 -0700 | [diff] [blame] | 1182 | ret = arm_smmu_prepare_pgtable(page, cookie); |
| 1183 | if (ret) { |
| 1184 | free_pages_exact(page, size); |
| 1185 | return NULL; |
| 1186 | } |
| 1187 | } |
| 1188 | |
| 1189 | return page; |
| 1190 | } |
| 1191 | |
| 1192 | static void arm_smmu_free_pages_exact(void *cookie, void *virt, size_t size) |
| 1193 | { |
Patrick Daly | b7dfda7 | 2016-10-04 14:42:58 -0700 | [diff] [blame] | 1194 | struct arm_smmu_domain *smmu_domain = cookie; |
| 1195 | |
| 1196 | if (!arm_smmu_is_domain_secure(smmu_domain)) { |
| 1197 | free_pages_exact(virt, size); |
| 1198 | return; |
| 1199 | } |
| 1200 | |
| 1201 | if (arm_smmu_secure_pool_add(smmu_domain, virt, size)) |
| 1202 | arm_smmu_unprepare_pgtable(smmu_domain, virt, size); |
Patrick Daly | c11d108 | 2016-09-01 15:52:44 -0700 | [diff] [blame] | 1203 | } |
| 1204 | |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame] | 1205 | static struct iommu_gather_ops arm_smmu_gather_ops = { |
| 1206 | .tlb_flush_all = arm_smmu_tlb_inv_context, |
| 1207 | .tlb_add_flush = arm_smmu_tlb_inv_range_nosync, |
| 1208 | .tlb_sync = arm_smmu_tlb_sync, |
Patrick Daly | c11d108 | 2016-09-01 15:52:44 -0700 | [diff] [blame] | 1209 | .alloc_pages_exact = arm_smmu_alloc_pages_exact, |
| 1210 | .free_pages_exact = arm_smmu_free_pages_exact, |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame] | 1211 | }; |
| 1212 | |
Patrick Daly | d54eafd | 2016-08-23 17:01:43 -0700 | [diff] [blame] | 1213 | static phys_addr_t arm_smmu_verify_fault(struct iommu_domain *domain, |
| 1214 | dma_addr_t iova, u32 fsr) |
| 1215 | { |
| 1216 | struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); |
| 1217 | struct arm_smmu_cfg *cfg = &smmu_domain->cfg; |
| 1218 | struct arm_smmu_device *smmu; |
| 1219 | void __iomem *cb_base; |
| 1220 | u64 sctlr, sctlr_orig; |
| 1221 | phys_addr_t phys; |
| 1222 | |
| 1223 | smmu = smmu_domain->smmu; |
| 1224 | cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx); |
| 1225 | |
| 1226 | arm_smmu_halt_nowait(smmu); |
| 1227 | |
| 1228 | writel_relaxed(RESUME_TERMINATE, cb_base + ARM_SMMU_CB_RESUME); |
| 1229 | |
| 1230 | arm_smmu_wait_for_halt(smmu); |
| 1231 | |
| 1232 | /* clear FSR to allow ATOS to log any faults */ |
| 1233 | writel_relaxed(fsr, cb_base + ARM_SMMU_CB_FSR); |
| 1234 | |
| 1235 | /* disable stall mode momentarily */ |
| 1236 | sctlr_orig = readl_relaxed(cb_base + ARM_SMMU_CB_SCTLR); |
| 1237 | sctlr = sctlr_orig & ~SCTLR_CFCFG; |
| 1238 | writel_relaxed(sctlr, cb_base + ARM_SMMU_CB_SCTLR); |
| 1239 | |
| 1240 | phys = arm_smmu_iova_to_phys_hard_no_halt(domain, iova); |
| 1241 | |
| 1242 | if (!phys) { |
| 1243 | dev_err(smmu->dev, |
| 1244 | "ATOS failed. Will issue a TLBIALL and try again...\n"); |
| 1245 | arm_smmu_tlb_inv_context(smmu_domain); |
| 1246 | phys = arm_smmu_iova_to_phys_hard_no_halt(domain, iova); |
| 1247 | if (phys) |
| 1248 | dev_err(smmu->dev, |
| 1249 | "ATOS succeeded this time. Maybe we missed a TLB invalidation while messing with page tables earlier??\n"); |
| 1250 | else |
| 1251 | dev_err(smmu->dev, |
| 1252 | "ATOS still failed. If the page tables look good (check the software table walk) then hardware might be misbehaving.\n"); |
| 1253 | } |
| 1254 | |
| 1255 | /* restore SCTLR */ |
| 1256 | writel_relaxed(sctlr_orig, cb_base + ARM_SMMU_CB_SCTLR); |
| 1257 | |
| 1258 | arm_smmu_resume(smmu); |
| 1259 | |
| 1260 | return phys; |
| 1261 | } |
| 1262 | |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1263 | static irqreturn_t arm_smmu_context_fault(int irq, void *dev) |
| 1264 | { |
Sushmita Susheelendra | a474ae1 | 2015-06-02 15:46:24 -0600 | [diff] [blame] | 1265 | int flags, ret, tmp; |
Patrick Daly | 5ba2811 | 2016-08-30 19:18:52 -0700 | [diff] [blame] | 1266 | u32 fsr, fsynr, resume; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1267 | unsigned long iova; |
| 1268 | struct iommu_domain *domain = dev; |
Joerg Roedel | 1d67263 | 2015-03-26 13:43:10 +0100 | [diff] [blame] | 1269 | struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); |
Will Deacon | 44680ee | 2014-06-25 11:29:12 +0100 | [diff] [blame] | 1270 | struct arm_smmu_cfg *cfg = &smmu_domain->cfg; |
| 1271 | struct arm_smmu_device *smmu = smmu_domain->smmu; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1272 | void __iomem *cb_base; |
Shalaj Jain | 04059c5 | 2015-03-03 13:34:59 -0800 | [diff] [blame] | 1273 | void __iomem *gr1_base; |
Mitchel Humpherys | 07ba44b | 2015-01-30 14:58:52 -0800 | [diff] [blame] | 1274 | bool fatal_asf = smmu->options & ARM_SMMU_OPT_FATAL_ASF; |
Mitchel Humpherys | b8be413 | 2015-02-06 14:25:10 -0800 | [diff] [blame] | 1275 | phys_addr_t phys_soft; |
Shalaj Jain | 04059c5 | 2015-03-03 13:34:59 -0800 | [diff] [blame] | 1276 | u32 frsynra; |
Mitchel Humpherys | cc8d12f | 2015-09-25 17:29:27 -0700 | [diff] [blame] | 1277 | bool non_fatal_fault = !!(smmu_domain->attributes & |
| 1278 | DOMAIN_ATTR_NON_FATAL_FAULTS); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1279 | |
Mitchel Humpherys | a8dabc9 | 2015-09-14 12:08:09 -0700 | [diff] [blame] | 1280 | static DEFINE_RATELIMIT_STATE(_rs, |
| 1281 | DEFAULT_RATELIMIT_INTERVAL, |
| 1282 | DEFAULT_RATELIMIT_BURST); |
| 1283 | |
Mitchel Humpherys | 3e52a7e | 2015-10-19 17:13:47 -0700 | [diff] [blame] | 1284 | ret = arm_smmu_power_on(smmu); |
| 1285 | if (ret) |
| 1286 | return IRQ_NONE; |
Patrick Daly | 3a8a88a | 2016-07-22 12:24:05 -0700 | [diff] [blame] | 1287 | |
Shalaj Jain | 04059c5 | 2015-03-03 13:34:59 -0800 | [diff] [blame] | 1288 | gr1_base = ARM_SMMU_GR1(smmu); |
Will Deacon | 44680ee | 2014-06-25 11:29:12 +0100 | [diff] [blame] | 1289 | cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1290 | fsr = readl_relaxed(cb_base + ARM_SMMU_CB_FSR); |
| 1291 | |
Patrick Daly | 3a8a88a | 2016-07-22 12:24:05 -0700 | [diff] [blame] | 1292 | if (!(fsr & FSR_FAULT)) { |
| 1293 | ret = IRQ_NONE; |
| 1294 | goto out_power_off; |
| 1295 | } |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1296 | |
Mitchel Humpherys | 07ba44b | 2015-01-30 14:58:52 -0800 | [diff] [blame] | 1297 | if (fatal_asf && (fsr & FSR_ASF)) { |
| 1298 | dev_err(smmu->dev, |
| 1299 | "Took an address size fault. Refusing to recover.\n"); |
| 1300 | BUG(); |
| 1301 | } |
| 1302 | |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1303 | fsynr = readl_relaxed(cb_base + ARM_SMMU_CB_FSYNR0); |
Patrick Daly | 5ba2811 | 2016-08-30 19:18:52 -0700 | [diff] [blame] | 1304 | flags = fsynr & FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ; |
Sushmita Susheelendra | a474ae1 | 2015-06-02 15:46:24 -0600 | [diff] [blame] | 1305 | if (fsr & FSR_TF) |
| 1306 | flags |= IOMMU_FAULT_TRANSLATION; |
| 1307 | if (fsr & FSR_PF) |
| 1308 | flags |= IOMMU_FAULT_PERMISSION; |
Mitchel Humpherys | dd75e33 | 2015-08-19 11:02:33 -0700 | [diff] [blame] | 1309 | if (fsr & FSR_EF) |
| 1310 | flags |= IOMMU_FAULT_EXTERNAL; |
Sushmita Susheelendra | a474ae1 | 2015-06-02 15:46:24 -0600 | [diff] [blame] | 1311 | if (fsr & FSR_SS) |
| 1312 | flags |= IOMMU_FAULT_TRANSACTION_STALLED; |
Patrick Daly | 5ba2811 | 2016-08-30 19:18:52 -0700 | [diff] [blame] | 1313 | |
Robin Murphy | f9a05f0 | 2016-04-13 18:13:01 +0100 | [diff] [blame] | 1314 | iova = readq_relaxed(cb_base + ARM_SMMU_CB_FAR); |
Mitchel Humpherys | b8be413 | 2015-02-06 14:25:10 -0800 | [diff] [blame] | 1315 | phys_soft = arm_smmu_iova_to_phys(domain, iova); |
Shalaj Jain | 04059c5 | 2015-03-03 13:34:59 -0800 | [diff] [blame] | 1316 | frsynra = readl_relaxed(gr1_base + ARM_SMMU_GR1_CBFRSYNRA(cfg->cbndx)); |
| 1317 | frsynra &= CBFRSYNRA_SID_MASK; |
Sushmita Susheelendra | a474ae1 | 2015-06-02 15:46:24 -0600 | [diff] [blame] | 1318 | tmp = report_iommu_fault(domain, smmu->dev, iova, flags); |
| 1319 | if (!tmp || (tmp == -EBUSY)) { |
Mitchel Humpherys | b8be413 | 2015-02-06 14:25:10 -0800 | [diff] [blame] | 1320 | dev_dbg(smmu->dev, |
| 1321 | "Context fault handled by client: iova=0x%08lx, fsr=0x%x, fsynr=0x%x, cb=%d\n", |
| 1322 | iova, fsr, fsynr, cfg->cbndx); |
| 1323 | dev_dbg(smmu->dev, |
| 1324 | "soft iova-to-phys=%pa\n", &phys_soft); |
Patrick Daly | 5ba2811 | 2016-08-30 19:18:52 -0700 | [diff] [blame] | 1325 | ret = IRQ_HANDLED; |
Shrenuj Bansal | d5083c0 | 2015-09-18 14:59:09 -0700 | [diff] [blame] | 1326 | resume = RESUME_TERMINATE; |
Patrick Daly | 5ba2811 | 2016-08-30 19:18:52 -0700 | [diff] [blame] | 1327 | } else { |
Patrick Daly | d54eafd | 2016-08-23 17:01:43 -0700 | [diff] [blame] | 1328 | phys_addr_t phys_atos = arm_smmu_verify_fault(domain, iova, |
| 1329 | fsr); |
Mitchel Humpherys | a8dabc9 | 2015-09-14 12:08:09 -0700 | [diff] [blame] | 1330 | if (__ratelimit(&_rs)) { |
| 1331 | dev_err(smmu->dev, |
| 1332 | "Unhandled context fault: iova=0x%08lx, fsr=0x%x, fsynr=0x%x, cb=%d\n", |
| 1333 | iova, fsr, fsynr, cfg->cbndx); |
| 1334 | dev_err(smmu->dev, "FAR = %016lx\n", |
| 1335 | (unsigned long)iova); |
| 1336 | dev_err(smmu->dev, |
| 1337 | "FSR = %08x [%s%s%s%s%s%s%s%s%s]\n", |
| 1338 | fsr, |
| 1339 | (fsr & 0x02) ? "TF " : "", |
| 1340 | (fsr & 0x04) ? "AFF " : "", |
| 1341 | (fsr & 0x08) ? "PF " : "", |
| 1342 | (fsr & 0x10) ? "EF " : "", |
| 1343 | (fsr & 0x20) ? "TLBMCF " : "", |
| 1344 | (fsr & 0x40) ? "TLBLKF " : "", |
| 1345 | (fsr & 0x80) ? "MHF " : "", |
| 1346 | (fsr & 0x40000000) ? "SS " : "", |
| 1347 | (fsr & 0x80000000) ? "MULTI " : ""); |
| 1348 | dev_err(smmu->dev, |
| 1349 | "soft iova-to-phys=%pa\n", &phys_soft); |
Mitchel Humpherys | d03b65d | 2015-11-05 11:50:29 -0800 | [diff] [blame] | 1350 | if (!phys_soft) |
| 1351 | dev_err(smmu->dev, |
| 1352 | "SOFTWARE TABLE WALK FAILED! Looks like %s accessed an unmapped address!\n", |
| 1353 | dev_name(smmu->dev)); |
Mitchel Humpherys | a8dabc9 | 2015-09-14 12:08:09 -0700 | [diff] [blame] | 1354 | dev_err(smmu->dev, |
| 1355 | "hard iova-to-phys (ATOS)=%pa\n", &phys_atos); |
| 1356 | dev_err(smmu->dev, "SID=0x%x\n", frsynra); |
| 1357 | } |
Patrick Daly | 5ba2811 | 2016-08-30 19:18:52 -0700 | [diff] [blame] | 1358 | ret = IRQ_NONE; |
| 1359 | resume = RESUME_TERMINATE; |
Mitchel Humpherys | cc8d12f | 2015-09-25 17:29:27 -0700 | [diff] [blame] | 1360 | if (!non_fatal_fault) { |
| 1361 | dev_err(smmu->dev, |
| 1362 | "Unhandled arm-smmu context fault!\n"); |
| 1363 | BUG(); |
| 1364 | } |
Patrick Daly | 5ba2811 | 2016-08-30 19:18:52 -0700 | [diff] [blame] | 1365 | } |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1366 | |
Sushmita Susheelendra | a474ae1 | 2015-06-02 15:46:24 -0600 | [diff] [blame] | 1367 | /* |
| 1368 | * If the client returns -EBUSY, do not clear FSR and do not RESUME |
| 1369 | * if stalled. This is required to keep the IOMMU client stalled on |
| 1370 | * the outstanding fault. This gives the client a chance to take any |
| 1371 | * debug action and then terminate the stalled transaction. |
| 1372 | * So, the sequence in case of stall on fault should be: |
| 1373 | * 1) Do not clear FSR or write to RESUME here |
| 1374 | * 2) Client takes any debug action |
| 1375 | * 3) Client terminates the stalled transaction and resumes the IOMMU |
| 1376 | * 4) Client clears FSR. The FSR should only be cleared after 3) and |
| 1377 | * not before so that the fault remains outstanding. This ensures |
| 1378 | * SCTLR.HUPCF has the desired effect if subsequent transactions also |
| 1379 | * need to be terminated. |
| 1380 | */ |
| 1381 | if (tmp != -EBUSY) { |
| 1382 | /* Clear the faulting FSR */ |
| 1383 | writel_relaxed(fsr, cb_base + ARM_SMMU_CB_FSR); |
Patrick Daly | 5ba2811 | 2016-08-30 19:18:52 -0700 | [diff] [blame] | 1384 | |
Sushmita Susheelendra | a474ae1 | 2015-06-02 15:46:24 -0600 | [diff] [blame] | 1385 | /* |
| 1386 | * Barrier required to ensure that the FSR is cleared |
| 1387 | * before resuming SMMU operation |
| 1388 | */ |
| 1389 | wmb(); |
| 1390 | |
| 1391 | /* Retry or terminate any stalled transactions */ |
| 1392 | if (fsr & FSR_SS) |
| 1393 | writel_relaxed(resume, cb_base + ARM_SMMU_CB_RESUME); |
| 1394 | } |
Patrick Daly | 5ba2811 | 2016-08-30 19:18:52 -0700 | [diff] [blame] | 1395 | |
Patrick Daly | 3a8a88a | 2016-07-22 12:24:05 -0700 | [diff] [blame] | 1396 | out_power_off: |
| 1397 | arm_smmu_power_off(smmu); |
| 1398 | |
Patrick Daly | 5ba2811 | 2016-08-30 19:18:52 -0700 | [diff] [blame] | 1399 | return ret; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1400 | } |
| 1401 | |
| 1402 | static irqreturn_t arm_smmu_global_fault(int irq, void *dev) |
| 1403 | { |
| 1404 | u32 gfsr, gfsynr0, gfsynr1, gfsynr2; |
| 1405 | struct arm_smmu_device *smmu = dev; |
Andreas Herrmann | 3a5df8f | 2014-01-30 18:18:04 +0000 | [diff] [blame] | 1406 | void __iomem *gr0_base = ARM_SMMU_GR0_NS(smmu); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1407 | |
Mitchel Humpherys | 3e52a7e | 2015-10-19 17:13:47 -0700 | [diff] [blame] | 1408 | if (arm_smmu_power_on(smmu)) |
| 1409 | return IRQ_NONE; |
Patrick Daly | 3a8a88a | 2016-07-22 12:24:05 -0700 | [diff] [blame] | 1410 | |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1411 | gfsr = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSR); |
| 1412 | gfsynr0 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR0); |
| 1413 | gfsynr1 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR1); |
| 1414 | gfsynr2 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR2); |
| 1415 | |
Patrick Daly | 3a8a88a | 2016-07-22 12:24:05 -0700 | [diff] [blame] | 1416 | if (!gfsr) { |
| 1417 | arm_smmu_power_off(smmu); |
Andreas Herrmann | 3a5df8f | 2014-01-30 18:18:04 +0000 | [diff] [blame] | 1418 | return IRQ_NONE; |
Patrick Daly | 3a8a88a | 2016-07-22 12:24:05 -0700 | [diff] [blame] | 1419 | } |
Andreas Herrmann | 3a5df8f | 2014-01-30 18:18:04 +0000 | [diff] [blame] | 1420 | |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1421 | dev_err_ratelimited(smmu->dev, |
| 1422 | "Unexpected global fault, this could be serious\n"); |
| 1423 | dev_err_ratelimited(smmu->dev, |
| 1424 | "\tGFSR 0x%08x, GFSYNR0 0x%08x, GFSYNR1 0x%08x, GFSYNR2 0x%08x\n", |
| 1425 | gfsr, gfsynr0, gfsynr1, gfsynr2); |
| 1426 | |
| 1427 | writel(gfsr, gr0_base + ARM_SMMU_GR0_sGFSR); |
Patrick Daly | 3a8a88a | 2016-07-22 12:24:05 -0700 | [diff] [blame] | 1428 | arm_smmu_power_off(smmu); |
Will Deacon | adaba32 | 2013-07-31 19:21:26 +0100 | [diff] [blame] | 1429 | return IRQ_HANDLED; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1430 | } |
| 1431 | |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame] | 1432 | static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain, |
| 1433 | struct io_pgtable_cfg *pgtbl_cfg) |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1434 | { |
| 1435 | u32 reg; |
Tirumalesh Chalamarla | 668b4ad | 2015-08-19 00:40:30 +0100 | [diff] [blame] | 1436 | u64 reg64; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1437 | bool stage1; |
Will Deacon | 44680ee | 2014-06-25 11:29:12 +0100 | [diff] [blame] | 1438 | struct arm_smmu_cfg *cfg = &smmu_domain->cfg; |
| 1439 | struct arm_smmu_device *smmu = smmu_domain->smmu; |
Will Deacon | c88ae5d | 2015-10-13 17:53:24 +0100 | [diff] [blame] | 1440 | void __iomem *cb_base, *gr1_base; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1441 | |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1442 | gr1_base = ARM_SMMU_GR1(smmu); |
Will Deacon | 44680ee | 2014-06-25 11:29:12 +0100 | [diff] [blame] | 1443 | stage1 = cfg->cbar != CBAR_TYPE_S2_TRANS; |
| 1444 | cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1445 | |
Will Deacon | 4a1c93c | 2015-03-04 12:21:03 +0000 | [diff] [blame] | 1446 | if (smmu->version > ARM_SMMU_V1) { |
Robin Murphy | 7602b87 | 2016-04-28 17:12:09 +0100 | [diff] [blame] | 1447 | if (cfg->fmt == ARM_SMMU_CTX_FMT_AARCH64) |
| 1448 | reg = CBA2R_RW64_64BIT; |
| 1449 | else |
| 1450 | reg = CBA2R_RW64_32BIT; |
Tirumalesh Chalamarla | 4e3e9b6 | 2016-02-23 10:19:00 -0800 | [diff] [blame] | 1451 | /* 16-bit VMIDs live in CBA2R */ |
| 1452 | if (smmu->features & ARM_SMMU_FEAT_VMID16) |
Tirumalesh Chalamarla | 1bd37a6 | 2016-03-04 13:56:09 -0800 | [diff] [blame] | 1453 | reg |= ARM_SMMU_CB_VMID(smmu, cfg) << CBA2R_VMID_SHIFT; |
Tirumalesh Chalamarla | 4e3e9b6 | 2016-02-23 10:19:00 -0800 | [diff] [blame] | 1454 | |
Will Deacon | 4a1c93c | 2015-03-04 12:21:03 +0000 | [diff] [blame] | 1455 | writel_relaxed(reg, gr1_base + ARM_SMMU_GR1_CBA2R(cfg->cbndx)); |
| 1456 | } |
| 1457 | |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1458 | /* CBAR */ |
Will Deacon | 44680ee | 2014-06-25 11:29:12 +0100 | [diff] [blame] | 1459 | reg = cfg->cbar; |
Robin Murphy | b7862e3 | 2016-04-13 18:13:03 +0100 | [diff] [blame] | 1460 | if (smmu->version < ARM_SMMU_V2) |
Mitchel Humpherys | 2907320 | 2014-07-08 09:52:18 -0700 | [diff] [blame] | 1461 | reg |= cfg->irptndx << CBAR_IRPTNDX_SHIFT; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1462 | |
Will Deacon | 57ca90f | 2014-02-06 14:59:05 +0000 | [diff] [blame] | 1463 | /* |
| 1464 | * Use the weakest shareability/memory types, so they are |
| 1465 | * overridden by the ttbcr/pte. |
| 1466 | */ |
| 1467 | if (stage1) { |
| 1468 | reg |= (CBAR_S1_BPSHCFG_NSH << CBAR_S1_BPSHCFG_SHIFT) | |
| 1469 | (CBAR_S1_MEMATTR_WB << CBAR_S1_MEMATTR_SHIFT); |
Tirumalesh Chalamarla | 4e3e9b6 | 2016-02-23 10:19:00 -0800 | [diff] [blame] | 1470 | } else if (!(smmu->features & ARM_SMMU_FEAT_VMID16)) { |
| 1471 | /* 8-bit VMIDs live in CBAR */ |
Tirumalesh Chalamarla | 1bd37a6 | 2016-03-04 13:56:09 -0800 | [diff] [blame] | 1472 | reg |= ARM_SMMU_CB_VMID(smmu, cfg) << CBAR_VMID_SHIFT; |
Will Deacon | 57ca90f | 2014-02-06 14:59:05 +0000 | [diff] [blame] | 1473 | } |
Will Deacon | 44680ee | 2014-06-25 11:29:12 +0100 | [diff] [blame] | 1474 | writel_relaxed(reg, gr1_base + ARM_SMMU_GR1_CBAR(cfg->cbndx)); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1475 | |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame] | 1476 | /* TTBRs */ |
| 1477 | if (stage1) { |
Tirumalesh Chalamarla | 668b4ad | 2015-08-19 00:40:30 +0100 | [diff] [blame] | 1478 | reg64 = pgtbl_cfg->arm_lpae_s1_cfg.ttbr[0]; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1479 | |
Tirumalesh Chalamarla | 1bd37a6 | 2016-03-04 13:56:09 -0800 | [diff] [blame] | 1480 | reg64 |= ((u64)ARM_SMMU_CB_ASID(smmu, cfg)) << TTBRn_ASID_SHIFT; |
Robin Murphy | f9a05f0 | 2016-04-13 18:13:01 +0100 | [diff] [blame] | 1481 | writeq_relaxed(reg64, cb_base + ARM_SMMU_CB_TTBR0); |
Tirumalesh Chalamarla | 668b4ad | 2015-08-19 00:40:30 +0100 | [diff] [blame] | 1482 | |
| 1483 | reg64 = pgtbl_cfg->arm_lpae_s1_cfg.ttbr[1]; |
Tirumalesh Chalamarla | 1bd37a6 | 2016-03-04 13:56:09 -0800 | [diff] [blame] | 1484 | reg64 |= ((u64)ARM_SMMU_CB_ASID(smmu, cfg)) << TTBRn_ASID_SHIFT; |
Robin Murphy | f9a05f0 | 2016-04-13 18:13:01 +0100 | [diff] [blame] | 1485 | writeq_relaxed(reg64, cb_base + ARM_SMMU_CB_TTBR1); |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame] | 1486 | } else { |
Tirumalesh Chalamarla | 668b4ad | 2015-08-19 00:40:30 +0100 | [diff] [blame] | 1487 | reg64 = pgtbl_cfg->arm_lpae_s2_cfg.vttbr; |
Robin Murphy | f9a05f0 | 2016-04-13 18:13:01 +0100 | [diff] [blame] | 1488 | writeq_relaxed(reg64, cb_base + ARM_SMMU_CB_TTBR0); |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame] | 1489 | } |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1490 | |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame] | 1491 | /* TTBCR */ |
| 1492 | if (stage1) { |
| 1493 | reg = pgtbl_cfg->arm_lpae_s1_cfg.tcr; |
| 1494 | writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBCR); |
| 1495 | if (smmu->version > ARM_SMMU_V1) { |
| 1496 | reg = pgtbl_cfg->arm_lpae_s1_cfg.tcr >> 32; |
Will Deacon | 5dc5616 | 2015-05-08 17:44:22 +0100 | [diff] [blame] | 1497 | reg |= TTBCR2_SEP_UPSTREAM; |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame] | 1498 | writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBCR2); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1499 | } |
| 1500 | } else { |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame] | 1501 | reg = pgtbl_cfg->arm_lpae_s2_cfg.vtcr; |
| 1502 | writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBCR); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1503 | } |
| 1504 | |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame] | 1505 | /* MAIRs (stage-1 only) */ |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1506 | if (stage1) { |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame] | 1507 | reg = pgtbl_cfg->arm_lpae_s1_cfg.mair[0]; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1508 | writel_relaxed(reg, cb_base + ARM_SMMU_CB_S1_MAIR0); |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame] | 1509 | reg = pgtbl_cfg->arm_lpae_s1_cfg.mair[1]; |
| 1510 | writel_relaxed(reg, cb_base + ARM_SMMU_CB_S1_MAIR1); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1511 | } |
| 1512 | |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1513 | /* SCTLR */ |
Patrick Daly | e62d336 | 2016-03-15 18:58:28 -0700 | [diff] [blame] | 1514 | reg = SCTLR_CFCFG | SCTLR_CFIE | SCTLR_CFRE | SCTLR_EAE_SBOP; |
| 1515 | |
| 1516 | if (!(smmu_domain->attributes & (1 << DOMAIN_ATTR_S1_BYPASS)) || |
| 1517 | !stage1) |
| 1518 | reg |= SCTLR_M; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1519 | if (stage1) |
| 1520 | reg |= SCTLR_S1_ASIDPNE; |
| 1521 | #ifdef __BIG_ENDIAN |
| 1522 | reg |= SCTLR_E; |
| 1523 | #endif |
Will Deacon | 2572484 | 2013-08-21 13:49:53 +0100 | [diff] [blame] | 1524 | writel_relaxed(reg, cb_base + ARM_SMMU_CB_SCTLR); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1525 | } |
| 1526 | |
Patrick Daly | c190d93 | 2016-08-30 17:23:28 -0700 | [diff] [blame] | 1527 | static int arm_smmu_init_asid(struct iommu_domain *domain, |
| 1528 | struct arm_smmu_device *smmu) |
| 1529 | { |
| 1530 | struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); |
| 1531 | struct arm_smmu_cfg *cfg = &smmu_domain->cfg; |
| 1532 | bool dynamic = is_dynamic_domain(domain); |
| 1533 | int ret; |
| 1534 | |
| 1535 | if (!dynamic) { |
| 1536 | cfg->asid = cfg->cbndx + 1; |
| 1537 | } else { |
| 1538 | mutex_lock(&smmu->idr_mutex); |
| 1539 | ret = idr_alloc_cyclic(&smmu->asid_idr, domain, |
| 1540 | smmu->num_context_banks + 2, |
| 1541 | MAX_ASID + 1, GFP_KERNEL); |
| 1542 | |
| 1543 | mutex_unlock(&smmu->idr_mutex); |
| 1544 | if (ret < 0) { |
| 1545 | dev_err(smmu->dev, "dynamic ASID allocation failed: %d\n", |
| 1546 | ret); |
| 1547 | return ret; |
| 1548 | } |
| 1549 | cfg->asid = ret; |
| 1550 | } |
| 1551 | return 0; |
| 1552 | } |
| 1553 | |
| 1554 | static void arm_smmu_free_asid(struct iommu_domain *domain) |
| 1555 | { |
| 1556 | struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); |
| 1557 | struct arm_smmu_device *smmu = smmu_domain->smmu; |
| 1558 | struct arm_smmu_cfg *cfg = &smmu_domain->cfg; |
| 1559 | bool dynamic = is_dynamic_domain(domain); |
| 1560 | |
| 1561 | if (cfg->asid == INVALID_ASID || !dynamic) |
| 1562 | return; |
| 1563 | |
| 1564 | mutex_lock(&smmu->idr_mutex); |
| 1565 | idr_remove(&smmu->asid_idr, cfg->asid); |
| 1566 | mutex_unlock(&smmu->idr_mutex); |
| 1567 | } |
| 1568 | |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1569 | static int arm_smmu_init_domain_context(struct iommu_domain *domain, |
Will Deacon | 44680ee | 2014-06-25 11:29:12 +0100 | [diff] [blame] | 1570 | struct arm_smmu_device *smmu) |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1571 | { |
Mitchel Humpherys | a18037b | 2014-07-30 18:58:13 +0100 | [diff] [blame] | 1572 | int irq, start, ret = 0; |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame] | 1573 | unsigned long ias, oas; |
| 1574 | struct io_pgtable_ops *pgtbl_ops; |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame] | 1575 | enum io_pgtable_fmt fmt; |
Joerg Roedel | 1d67263 | 2015-03-26 13:43:10 +0100 | [diff] [blame] | 1576 | struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); |
Will Deacon | 44680ee | 2014-06-25 11:29:12 +0100 | [diff] [blame] | 1577 | struct arm_smmu_cfg *cfg = &smmu_domain->cfg; |
Mitchel Humpherys | c625ce0 | 2015-10-07 14:03:50 -0700 | [diff] [blame] | 1578 | bool is_fast = smmu_domain->attributes & (1 << DOMAIN_ATTR_FAST); |
Patrick Daly | c190d93 | 2016-08-30 17:23:28 -0700 | [diff] [blame] | 1579 | bool dynamic; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1580 | |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame] | 1581 | mutex_lock(&smmu_domain->init_mutex); |
Mitchel Humpherys | a18037b | 2014-07-30 18:58:13 +0100 | [diff] [blame] | 1582 | if (smmu_domain->smmu) |
| 1583 | goto out_unlock; |
| 1584 | |
Patrick Daly | c190d93 | 2016-08-30 17:23:28 -0700 | [diff] [blame] | 1585 | smmu_domain->cfg.irptndx = INVALID_IRPTNDX; |
| 1586 | smmu_domain->cfg.asid = INVALID_ASID; |
| 1587 | |
Robin Murphy | 9800699 | 2016-04-20 14:53:33 +0100 | [diff] [blame] | 1588 | /* We're bypassing these SIDs, so don't allocate an actual context */ |
| 1589 | if (domain->type == IOMMU_DOMAIN_DMA) { |
| 1590 | smmu_domain->smmu = smmu; |
| 1591 | goto out_unlock; |
| 1592 | } |
| 1593 | |
Patrick Daly | c190d93 | 2016-08-30 17:23:28 -0700 | [diff] [blame] | 1594 | dynamic = is_dynamic_domain(domain); |
| 1595 | if (dynamic && !(smmu->options & ARM_SMMU_OPT_DYNAMIC)) { |
| 1596 | dev_err(smmu->dev, "dynamic domains not supported\n"); |
| 1597 | ret = -EPERM; |
| 1598 | goto out_unlock; |
| 1599 | } |
| 1600 | |
Will Deacon | c752ce4 | 2014-06-25 22:46:31 +0100 | [diff] [blame] | 1601 | /* |
| 1602 | * Mapping the requested stage onto what we support is surprisingly |
| 1603 | * complicated, mainly because the spec allows S1+S2 SMMUs without |
| 1604 | * support for nested translation. That means we end up with the |
| 1605 | * following table: |
| 1606 | * |
| 1607 | * Requested Supported Actual |
| 1608 | * S1 N S1 |
| 1609 | * S1 S1+S2 S1 |
| 1610 | * S1 S2 S2 |
| 1611 | * S1 S1 S1 |
| 1612 | * N N N |
| 1613 | * N S1+S2 S2 |
| 1614 | * N S2 S2 |
| 1615 | * N S1 S1 |
| 1616 | * |
| 1617 | * Note that you can't actually request stage-2 mappings. |
| 1618 | */ |
| 1619 | if (!(smmu->features & ARM_SMMU_FEAT_TRANS_S1)) |
| 1620 | smmu_domain->stage = ARM_SMMU_DOMAIN_S2; |
| 1621 | if (!(smmu->features & ARM_SMMU_FEAT_TRANS_S2)) |
| 1622 | smmu_domain->stage = ARM_SMMU_DOMAIN_S1; |
| 1623 | |
Robin Murphy | 7602b87 | 2016-04-28 17:12:09 +0100 | [diff] [blame] | 1624 | /* |
| 1625 | * Choosing a suitable context format is even more fiddly. Until we |
| 1626 | * grow some way for the caller to express a preference, and/or move |
| 1627 | * the decision into the io-pgtable code where it arguably belongs, |
| 1628 | * just aim for the closest thing to the rest of the system, and hope |
| 1629 | * that the hardware isn't esoteric enough that we can't assume AArch64 |
| 1630 | * support to be a superset of AArch32 support... |
| 1631 | */ |
| 1632 | if (smmu->features & ARM_SMMU_FEAT_FMT_AARCH32_L) |
| 1633 | cfg->fmt = ARM_SMMU_CTX_FMT_AARCH32_L; |
| 1634 | if ((IS_ENABLED(CONFIG_64BIT) || cfg->fmt == ARM_SMMU_CTX_FMT_NONE) && |
| 1635 | (smmu->features & (ARM_SMMU_FEAT_FMT_AARCH64_64K | |
| 1636 | ARM_SMMU_FEAT_FMT_AARCH64_16K | |
| 1637 | ARM_SMMU_FEAT_FMT_AARCH64_4K))) |
| 1638 | cfg->fmt = ARM_SMMU_CTX_FMT_AARCH64; |
| 1639 | |
| 1640 | if (cfg->fmt == ARM_SMMU_CTX_FMT_NONE) { |
| 1641 | ret = -EINVAL; |
| 1642 | goto out_unlock; |
| 1643 | } |
| 1644 | |
Will Deacon | c752ce4 | 2014-06-25 22:46:31 +0100 | [diff] [blame] | 1645 | switch (smmu_domain->stage) { |
| 1646 | case ARM_SMMU_DOMAIN_S1: |
| 1647 | cfg->cbar = CBAR_TYPE_S1_TRANS_S2_BYPASS; |
| 1648 | start = smmu->num_s2_context_banks; |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame] | 1649 | ias = smmu->va_size; |
| 1650 | oas = smmu->ipa_size; |
Robin Murphy | 7602b87 | 2016-04-28 17:12:09 +0100 | [diff] [blame] | 1651 | if (cfg->fmt == ARM_SMMU_CTX_FMT_AARCH64) { |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame] | 1652 | fmt = ARM_64_LPAE_S1; |
Robin Murphy | 7602b87 | 2016-04-28 17:12:09 +0100 | [diff] [blame] | 1653 | } else { |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame] | 1654 | fmt = ARM_32_LPAE_S1; |
Robin Murphy | 7602b87 | 2016-04-28 17:12:09 +0100 | [diff] [blame] | 1655 | ias = min(ias, 32UL); |
| 1656 | oas = min(oas, 40UL); |
| 1657 | } |
Will Deacon | c752ce4 | 2014-06-25 22:46:31 +0100 | [diff] [blame] | 1658 | break; |
| 1659 | case ARM_SMMU_DOMAIN_NESTED: |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1660 | /* |
| 1661 | * We will likely want to change this if/when KVM gets |
| 1662 | * involved. |
| 1663 | */ |
Will Deacon | c752ce4 | 2014-06-25 22:46:31 +0100 | [diff] [blame] | 1664 | case ARM_SMMU_DOMAIN_S2: |
Will Deacon | 9c5c92e | 2014-06-25 12:12:41 +0100 | [diff] [blame] | 1665 | cfg->cbar = CBAR_TYPE_S2_TRANS; |
| 1666 | start = 0; |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame] | 1667 | ias = smmu->ipa_size; |
| 1668 | oas = smmu->pa_size; |
Robin Murphy | 7602b87 | 2016-04-28 17:12:09 +0100 | [diff] [blame] | 1669 | if (cfg->fmt == ARM_SMMU_CTX_FMT_AARCH64) { |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame] | 1670 | fmt = ARM_64_LPAE_S2; |
Robin Murphy | 7602b87 | 2016-04-28 17:12:09 +0100 | [diff] [blame] | 1671 | } else { |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame] | 1672 | fmt = ARM_32_LPAE_S2; |
Robin Murphy | 7602b87 | 2016-04-28 17:12:09 +0100 | [diff] [blame] | 1673 | ias = min(ias, 40UL); |
| 1674 | oas = min(oas, 40UL); |
| 1675 | } |
Will Deacon | c752ce4 | 2014-06-25 22:46:31 +0100 | [diff] [blame] | 1676 | break; |
| 1677 | default: |
| 1678 | ret = -EINVAL; |
| 1679 | goto out_unlock; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1680 | } |
| 1681 | |
Mitchel Humpherys | c625ce0 | 2015-10-07 14:03:50 -0700 | [diff] [blame] | 1682 | if (is_fast) |
| 1683 | fmt = ARM_V8L_FAST; |
| 1684 | |
| 1685 | |
Patrick Daly | c190d93 | 2016-08-30 17:23:28 -0700 | [diff] [blame] | 1686 | /* Dynamic domains must set cbndx through domain attribute */ |
| 1687 | if (!dynamic) { |
| 1688 | ret = __arm_smmu_alloc_bitmap(smmu->context_map, start, |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1689 | smmu->num_context_banks); |
Patrick Daly | c190d93 | 2016-08-30 17:23:28 -0700 | [diff] [blame] | 1690 | if (ret < 0) |
| 1691 | goto out_unlock; |
| 1692 | cfg->cbndx = ret; |
| 1693 | } |
Robin Murphy | b7862e3 | 2016-04-13 18:13:03 +0100 | [diff] [blame] | 1694 | if (smmu->version < ARM_SMMU_V2) { |
Will Deacon | 44680ee | 2014-06-25 11:29:12 +0100 | [diff] [blame] | 1695 | cfg->irptndx = atomic_inc_return(&smmu->irptndx); |
| 1696 | cfg->irptndx %= smmu->num_context_irqs; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1697 | } else { |
Will Deacon | 44680ee | 2014-06-25 11:29:12 +0100 | [diff] [blame] | 1698 | cfg->irptndx = cfg->cbndx; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1699 | } |
| 1700 | |
Mitchel Humpherys | 39e9c91 | 2015-04-15 15:14:15 -0700 | [diff] [blame] | 1701 | smmu_domain->pgtbl_cfg = (struct io_pgtable_cfg) { |
Robin Murphy | d546635 | 2016-05-09 17:20:09 +0100 | [diff] [blame] | 1702 | .pgsize_bitmap = smmu->pgsize_bitmap, |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame] | 1703 | .ias = ias, |
| 1704 | .oas = oas, |
| 1705 | .tlb = &arm_smmu_gather_ops, |
Robin Murphy | 2df7a25 | 2015-07-29 19:46:06 +0100 | [diff] [blame] | 1706 | .iommu_dev = smmu->dev, |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame] | 1707 | }; |
Mitchel Humpherys | a18037b | 2014-07-30 18:58:13 +0100 | [diff] [blame] | 1708 | |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame] | 1709 | smmu_domain->smmu = smmu; |
Mitchel Humpherys | 39e9c91 | 2015-04-15 15:14:15 -0700 | [diff] [blame] | 1710 | pgtbl_ops = alloc_io_pgtable_ops(fmt, &smmu_domain->pgtbl_cfg, |
| 1711 | smmu_domain); |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame] | 1712 | if (!pgtbl_ops) { |
| 1713 | ret = -ENOMEM; |
| 1714 | goto out_clear_smmu; |
| 1715 | } |
| 1716 | |
Patrick Daly | c11d108 | 2016-09-01 15:52:44 -0700 | [diff] [blame] | 1717 | /* |
| 1718 | * assign any page table memory that might have been allocated |
| 1719 | * during alloc_io_pgtable_ops |
| 1720 | */ |
Patrick Daly | e271f21 | 2016-10-04 13:24:49 -0700 | [diff] [blame] | 1721 | arm_smmu_secure_domain_lock(smmu_domain); |
Patrick Daly | c11d108 | 2016-09-01 15:52:44 -0700 | [diff] [blame] | 1722 | arm_smmu_assign_table(smmu_domain); |
Patrick Daly | e271f21 | 2016-10-04 13:24:49 -0700 | [diff] [blame] | 1723 | arm_smmu_secure_domain_unlock(smmu_domain); |
Patrick Daly | c11d108 | 2016-09-01 15:52:44 -0700 | [diff] [blame] | 1724 | |
Robin Murphy | d546635 | 2016-05-09 17:20:09 +0100 | [diff] [blame] | 1725 | /* Update the domain's page sizes to reflect the page table format */ |
Mitchel Humpherys | 39e9c91 | 2015-04-15 15:14:15 -0700 | [diff] [blame] | 1726 | domain->pgsize_bitmap = smmu_domain->pgtbl_cfg.pgsize_bitmap; |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame] | 1727 | |
Patrick Daly | c190d93 | 2016-08-30 17:23:28 -0700 | [diff] [blame] | 1728 | /* Assign an asid */ |
| 1729 | ret = arm_smmu_init_asid(domain, smmu); |
| 1730 | if (ret) |
| 1731 | goto out_clear_smmu; |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame] | 1732 | |
Patrick Daly | c190d93 | 2016-08-30 17:23:28 -0700 | [diff] [blame] | 1733 | if (!dynamic) { |
| 1734 | /* Initialise the context bank with our page table cfg */ |
| 1735 | arm_smmu_init_context_bank(smmu_domain, |
| 1736 | &smmu_domain->pgtbl_cfg); |
| 1737 | |
| 1738 | /* |
| 1739 | * Request context fault interrupt. Do this last to avoid the |
| 1740 | * handler seeing a half-initialised domain state. |
| 1741 | */ |
| 1742 | irq = smmu->irqs[smmu->num_global_irqs + cfg->irptndx]; |
| 1743 | ret = devm_request_threaded_irq(smmu->dev, irq, NULL, |
Mitchel Humpherys | cca6011 | 2015-01-13 13:38:12 -0800 | [diff] [blame] | 1744 | arm_smmu_context_fault, IRQF_ONESHOT | IRQF_SHARED, |
| 1745 | "arm-smmu-context-fault", domain); |
Patrick Daly | c190d93 | 2016-08-30 17:23:28 -0700 | [diff] [blame] | 1746 | if (ret < 0) { |
| 1747 | dev_err(smmu->dev, "failed to request context IRQ %d (%u)\n", |
| 1748 | cfg->irptndx, irq); |
| 1749 | cfg->irptndx = INVALID_IRPTNDX; |
| 1750 | goto out_clear_smmu; |
| 1751 | } |
| 1752 | } else { |
Will Deacon | 44680ee | 2014-06-25 11:29:12 +0100 | [diff] [blame] | 1753 | cfg->irptndx = INVALID_IRPTNDX; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1754 | } |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame] | 1755 | mutex_unlock(&smmu_domain->init_mutex); |
| 1756 | |
| 1757 | /* Publish page table ops for map/unmap */ |
| 1758 | smmu_domain->pgtbl_ops = pgtbl_ops; |
Will Deacon | a9a1b0b | 2014-05-01 18:05:08 +0100 | [diff] [blame] | 1759 | return 0; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1760 | |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame] | 1761 | out_clear_smmu: |
Jeremy Gebben | fa24b0c | 2015-06-16 12:45:31 -0600 | [diff] [blame] | 1762 | arm_smmu_destroy_domain_context(domain); |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame] | 1763 | smmu_domain->smmu = NULL; |
Mitchel Humpherys | a18037b | 2014-07-30 18:58:13 +0100 | [diff] [blame] | 1764 | out_unlock: |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame] | 1765 | mutex_unlock(&smmu_domain->init_mutex); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1766 | return ret; |
| 1767 | } |
| 1768 | |
| 1769 | static void arm_smmu_destroy_domain_context(struct iommu_domain *domain) |
| 1770 | { |
Joerg Roedel | 1d67263 | 2015-03-26 13:43:10 +0100 | [diff] [blame] | 1771 | struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); |
Will Deacon | 44680ee | 2014-06-25 11:29:12 +0100 | [diff] [blame] | 1772 | struct arm_smmu_device *smmu = smmu_domain->smmu; |
| 1773 | struct arm_smmu_cfg *cfg = &smmu_domain->cfg; |
Will Deacon | 1463fe4 | 2013-07-31 19:21:27 +0100 | [diff] [blame] | 1774 | void __iomem *cb_base; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1775 | int irq; |
Patrick Daly | c190d93 | 2016-08-30 17:23:28 -0700 | [diff] [blame] | 1776 | bool dynamic; |
Patrick Daly | 3a8a88a | 2016-07-22 12:24:05 -0700 | [diff] [blame] | 1777 | int ret; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1778 | |
Robin Murphy | 9800699 | 2016-04-20 14:53:33 +0100 | [diff] [blame] | 1779 | if (!smmu || domain->type == IOMMU_DOMAIN_DMA) |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1780 | return; |
| 1781 | |
Patrick Daly | 3a8a88a | 2016-07-22 12:24:05 -0700 | [diff] [blame] | 1782 | ret = arm_smmu_power_on(smmu); |
| 1783 | if (ret) { |
| 1784 | WARN_ONCE(ret, "Woops, powering on smmu %p failed. Leaking context bank\n", |
| 1785 | smmu); |
| 1786 | return; |
| 1787 | } |
| 1788 | |
Patrick Daly | c190d93 | 2016-08-30 17:23:28 -0700 | [diff] [blame] | 1789 | dynamic = is_dynamic_domain(domain); |
| 1790 | if (dynamic) { |
| 1791 | arm_smmu_free_asid(domain); |
| 1792 | free_io_pgtable_ops(smmu_domain->pgtbl_ops); |
Patrick Daly | 3a8a88a | 2016-07-22 12:24:05 -0700 | [diff] [blame] | 1793 | arm_smmu_power_off(smmu); |
Patrick Daly | e271f21 | 2016-10-04 13:24:49 -0700 | [diff] [blame] | 1794 | arm_smmu_secure_domain_lock(smmu_domain); |
Patrick Daly | b7dfda7 | 2016-10-04 14:42:58 -0700 | [diff] [blame] | 1795 | arm_smmu_secure_pool_destroy(smmu_domain); |
Patrick Daly | c11d108 | 2016-09-01 15:52:44 -0700 | [diff] [blame] | 1796 | arm_smmu_unassign_table(smmu_domain); |
Patrick Daly | e271f21 | 2016-10-04 13:24:49 -0700 | [diff] [blame] | 1797 | arm_smmu_secure_domain_unlock(smmu_domain); |
Patrick Daly | c190d93 | 2016-08-30 17:23:28 -0700 | [diff] [blame] | 1798 | return; |
| 1799 | } |
| 1800 | |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame] | 1801 | /* |
| 1802 | * Disable the context bank and free the page tables before freeing |
| 1803 | * it. |
| 1804 | */ |
Will Deacon | 44680ee | 2014-06-25 11:29:12 +0100 | [diff] [blame] | 1805 | cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx); |
Will Deacon | 1463fe4 | 2013-07-31 19:21:27 +0100 | [diff] [blame] | 1806 | writel_relaxed(0, cb_base + ARM_SMMU_CB_SCTLR); |
Will Deacon | 1463fe4 | 2013-07-31 19:21:27 +0100 | [diff] [blame] | 1807 | |
Will Deacon | 44680ee | 2014-06-25 11:29:12 +0100 | [diff] [blame] | 1808 | if (cfg->irptndx != INVALID_IRPTNDX) { |
| 1809 | irq = smmu->irqs[smmu->num_global_irqs + cfg->irptndx]; |
Peng Fan | bee1400 | 2016-07-04 17:38:22 +0800 | [diff] [blame] | 1810 | devm_free_irq(smmu->dev, irq, domain); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1811 | } |
| 1812 | |
Markus Elfring | 44830b0 | 2015-11-06 18:32:41 +0100 | [diff] [blame] | 1813 | free_io_pgtable_ops(smmu_domain->pgtbl_ops); |
Patrick Daly | e271f21 | 2016-10-04 13:24:49 -0700 | [diff] [blame] | 1814 | arm_smmu_secure_domain_lock(smmu_domain); |
Patrick Daly | b7dfda7 | 2016-10-04 14:42:58 -0700 | [diff] [blame] | 1815 | arm_smmu_secure_pool_destroy(smmu_domain); |
Patrick Daly | c11d108 | 2016-09-01 15:52:44 -0700 | [diff] [blame] | 1816 | arm_smmu_unassign_table(smmu_domain); |
Patrick Daly | e271f21 | 2016-10-04 13:24:49 -0700 | [diff] [blame] | 1817 | arm_smmu_secure_domain_unlock(smmu_domain); |
Will Deacon | 44680ee | 2014-06-25 11:29:12 +0100 | [diff] [blame] | 1818 | __arm_smmu_free_bitmap(smmu->context_map, cfg->cbndx); |
Patrick Daly | 3a8a88a | 2016-07-22 12:24:05 -0700 | [diff] [blame] | 1819 | |
| 1820 | arm_smmu_power_off(smmu); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1821 | } |
| 1822 | |
Joerg Roedel | 1d67263 | 2015-03-26 13:43:10 +0100 | [diff] [blame] | 1823 | static struct iommu_domain *arm_smmu_domain_alloc(unsigned type) |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1824 | { |
| 1825 | struct arm_smmu_domain *smmu_domain; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1826 | |
Patrick Daly | 0980131 | 2016-08-29 17:02:52 -0700 | [diff] [blame] | 1827 | /* Do not support DOMAIN_DMA for now */ |
| 1828 | if (type != IOMMU_DOMAIN_UNMANAGED) |
Joerg Roedel | 1d67263 | 2015-03-26 13:43:10 +0100 | [diff] [blame] | 1829 | return NULL; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1830 | /* |
| 1831 | * Allocate the domain and initialise some of its data structures. |
| 1832 | * We can't really do anything meaningful until we've added a |
| 1833 | * master. |
| 1834 | */ |
| 1835 | smmu_domain = kzalloc(sizeof(*smmu_domain), GFP_KERNEL); |
| 1836 | if (!smmu_domain) |
Joerg Roedel | 1d67263 | 2015-03-26 13:43:10 +0100 | [diff] [blame] | 1837 | return NULL; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1838 | |
Robin Murphy | 9adb959 | 2016-01-26 18:06:36 +0000 | [diff] [blame] | 1839 | if (type == IOMMU_DOMAIN_DMA && |
| 1840 | iommu_get_dma_cookie(&smmu_domain->domain)) { |
| 1841 | kfree(smmu_domain); |
| 1842 | return NULL; |
| 1843 | } |
| 1844 | |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame] | 1845 | mutex_init(&smmu_domain->init_mutex); |
| 1846 | spin_lock_init(&smmu_domain->pgtbl_lock); |
Jeremy Gebben | 8ac927c | 2015-07-10 16:43:22 -0600 | [diff] [blame] | 1847 | smmu_domain->cfg.cbndx = INVALID_CBNDX; |
Patrick Daly | c11d108 | 2016-09-01 15:52:44 -0700 | [diff] [blame] | 1848 | smmu_domain->secure_vmid = VMID_INVAL; |
| 1849 | INIT_LIST_HEAD(&smmu_domain->pte_info_list); |
| 1850 | INIT_LIST_HEAD(&smmu_domain->unassign_list); |
Patrick Daly | e271f21 | 2016-10-04 13:24:49 -0700 | [diff] [blame] | 1851 | mutex_init(&smmu_domain->assign_lock); |
Patrick Daly | b7dfda7 | 2016-10-04 14:42:58 -0700 | [diff] [blame] | 1852 | INIT_LIST_HEAD(&smmu_domain->secure_pool_list); |
Joerg Roedel | 1d67263 | 2015-03-26 13:43:10 +0100 | [diff] [blame] | 1853 | |
| 1854 | return &smmu_domain->domain; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1855 | } |
| 1856 | |
Joerg Roedel | 1d67263 | 2015-03-26 13:43:10 +0100 | [diff] [blame] | 1857 | static void arm_smmu_domain_free(struct iommu_domain *domain) |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1858 | { |
Joerg Roedel | 1d67263 | 2015-03-26 13:43:10 +0100 | [diff] [blame] | 1859 | struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); |
Will Deacon | 1463fe4 | 2013-07-31 19:21:27 +0100 | [diff] [blame] | 1860 | |
| 1861 | /* |
| 1862 | * Free the domain resources. We assume that all devices have |
| 1863 | * already been detached. |
| 1864 | */ |
Robin Murphy | 9adb959 | 2016-01-26 18:06:36 +0000 | [diff] [blame] | 1865 | iommu_put_dma_cookie(domain); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1866 | arm_smmu_destroy_domain_context(domain); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1867 | kfree(smmu_domain); |
| 1868 | } |
| 1869 | |
| 1870 | static int arm_smmu_master_configure_smrs(struct arm_smmu_device *smmu, |
Will Deacon | a9a1b0b | 2014-05-01 18:05:08 +0100 | [diff] [blame] | 1871 | struct arm_smmu_master_cfg *cfg) |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1872 | { |
| 1873 | int i; |
| 1874 | struct arm_smmu_smr *smrs; |
| 1875 | void __iomem *gr0_base = ARM_SMMU_GR0(smmu); |
| 1876 | |
| 1877 | if (!(smmu->features & ARM_SMMU_FEAT_STREAM_MATCH)) |
| 1878 | return 0; |
| 1879 | |
Will Deacon | a9a1b0b | 2014-05-01 18:05:08 +0100 | [diff] [blame] | 1880 | if (cfg->smrs) |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1881 | return -EEXIST; |
| 1882 | |
Mitchel Humpherys | 2907320 | 2014-07-08 09:52:18 -0700 | [diff] [blame] | 1883 | smrs = kmalloc_array(cfg->num_streamids, sizeof(*smrs), GFP_KERNEL); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1884 | if (!smrs) { |
Will Deacon | a9a1b0b | 2014-05-01 18:05:08 +0100 | [diff] [blame] | 1885 | dev_err(smmu->dev, "failed to allocate %d SMRs\n", |
| 1886 | cfg->num_streamids); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1887 | return -ENOMEM; |
| 1888 | } |
| 1889 | |
Will Deacon | 44680ee | 2014-06-25 11:29:12 +0100 | [diff] [blame] | 1890 | /* Allocate the SMRs on the SMMU */ |
Will Deacon | a9a1b0b | 2014-05-01 18:05:08 +0100 | [diff] [blame] | 1891 | for (i = 0; i < cfg->num_streamids; ++i) { |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1892 | int idx = __arm_smmu_alloc_bitmap(smmu->smr_map, 0, |
| 1893 | smmu->num_mapping_groups); |
Arnd Bergmann | 287980e | 2016-05-27 23:23:25 +0200 | [diff] [blame] | 1894 | if (idx < 0) { |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1895 | dev_err(smmu->dev, "failed to allocate free SMR\n"); |
| 1896 | goto err_free_smrs; |
| 1897 | } |
| 1898 | |
| 1899 | smrs[i] = (struct arm_smmu_smr) { |
| 1900 | .idx = idx, |
| 1901 | .mask = 0, /* We don't currently share SMRs */ |
Will Deacon | a9a1b0b | 2014-05-01 18:05:08 +0100 | [diff] [blame] | 1902 | .id = cfg->streamids[i], |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1903 | }; |
| 1904 | } |
| 1905 | |
| 1906 | /* It worked! Now, poke the actual hardware */ |
Will Deacon | a9a1b0b | 2014-05-01 18:05:08 +0100 | [diff] [blame] | 1907 | for (i = 0; i < cfg->num_streamids; ++i) { |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1908 | u32 reg = SMR_VALID | smrs[i].id << SMR_ID_SHIFT | |
| 1909 | smrs[i].mask << SMR_MASK_SHIFT; |
| 1910 | writel_relaxed(reg, gr0_base + ARM_SMMU_GR0_SMR(smrs[i].idx)); |
| 1911 | } |
| 1912 | |
Will Deacon | a9a1b0b | 2014-05-01 18:05:08 +0100 | [diff] [blame] | 1913 | cfg->smrs = smrs; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1914 | return 0; |
| 1915 | |
| 1916 | err_free_smrs: |
| 1917 | while (--i >= 0) |
| 1918 | __arm_smmu_free_bitmap(smmu->smr_map, smrs[i].idx); |
| 1919 | kfree(smrs); |
| 1920 | return -ENOSPC; |
| 1921 | } |
| 1922 | |
| 1923 | static void arm_smmu_master_free_smrs(struct arm_smmu_device *smmu, |
Will Deacon | a9a1b0b | 2014-05-01 18:05:08 +0100 | [diff] [blame] | 1924 | struct arm_smmu_master_cfg *cfg) |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1925 | { |
| 1926 | int i; |
| 1927 | void __iomem *gr0_base = ARM_SMMU_GR0(smmu); |
Will Deacon | a9a1b0b | 2014-05-01 18:05:08 +0100 | [diff] [blame] | 1928 | struct arm_smmu_smr *smrs = cfg->smrs; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1929 | |
Will Deacon | 43b412b | 2014-07-15 11:22:24 +0100 | [diff] [blame] | 1930 | if (!smrs) |
| 1931 | return; |
| 1932 | |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1933 | /* Invalidate the SMRs before freeing back to the allocator */ |
Will Deacon | a9a1b0b | 2014-05-01 18:05:08 +0100 | [diff] [blame] | 1934 | for (i = 0; i < cfg->num_streamids; ++i) { |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1935 | u8 idx = smrs[i].idx; |
Mitchel Humpherys | 2907320 | 2014-07-08 09:52:18 -0700 | [diff] [blame] | 1936 | |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1937 | writel_relaxed(~SMR_VALID, gr0_base + ARM_SMMU_GR0_SMR(idx)); |
| 1938 | __arm_smmu_free_bitmap(smmu->smr_map, idx); |
| 1939 | } |
| 1940 | |
Will Deacon | a9a1b0b | 2014-05-01 18:05:08 +0100 | [diff] [blame] | 1941 | cfg->smrs = NULL; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1942 | kfree(smrs); |
| 1943 | } |
| 1944 | |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1945 | static int arm_smmu_domain_add_master(struct arm_smmu_domain *smmu_domain, |
Will Deacon | a9a1b0b | 2014-05-01 18:05:08 +0100 | [diff] [blame] | 1946 | struct arm_smmu_master_cfg *cfg) |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1947 | { |
| 1948 | int i, ret; |
Will Deacon | 44680ee | 2014-06-25 11:29:12 +0100 | [diff] [blame] | 1949 | struct arm_smmu_device *smmu = smmu_domain->smmu; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1950 | void __iomem *gr0_base = ARM_SMMU_GR0(smmu); |
| 1951 | |
Will Deacon | 5f63495 | 2016-04-20 14:53:32 +0100 | [diff] [blame] | 1952 | /* |
| 1953 | * FIXME: This won't be needed once we have IOMMU-backed DMA ops |
| 1954 | * for all devices behind the SMMU. Note that we need to take |
| 1955 | * care configuring SMRs for devices both a platform_device and |
| 1956 | * and a PCI device (i.e. a PCI host controller) |
| 1957 | */ |
| 1958 | if (smmu_domain->domain.type == IOMMU_DOMAIN_DMA) |
| 1959 | return 0; |
| 1960 | |
Will Deacon | 8f68f8e | 2014-07-15 11:27:08 +0100 | [diff] [blame] | 1961 | /* Devices in an IOMMU group may already be configured */ |
Will Deacon | a9a1b0b | 2014-05-01 18:05:08 +0100 | [diff] [blame] | 1962 | ret = arm_smmu_master_configure_smrs(smmu, cfg); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1963 | if (ret) |
Will Deacon | 8f68f8e | 2014-07-15 11:27:08 +0100 | [diff] [blame] | 1964 | return ret == -EEXIST ? 0 : ret; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1965 | |
Will Deacon | a9a1b0b | 2014-05-01 18:05:08 +0100 | [diff] [blame] | 1966 | for (i = 0; i < cfg->num_streamids; ++i) { |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1967 | u32 idx, s2cr; |
Mitchel Humpherys | 2907320 | 2014-07-08 09:52:18 -0700 | [diff] [blame] | 1968 | |
Will Deacon | a9a1b0b | 2014-05-01 18:05:08 +0100 | [diff] [blame] | 1969 | idx = cfg->smrs ? cfg->smrs[i].idx : cfg->streamids[i]; |
Patrick Daly | f493044 | 2016-06-27 20:50:14 -0700 | [diff] [blame] | 1970 | s2cr = S2CR_TYPE_TRANS | |
Will Deacon | 44680ee | 2014-06-25 11:29:12 +0100 | [diff] [blame] | 1971 | (smmu_domain->cfg.cbndx << S2CR_CBNDX_SHIFT); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1972 | writel_relaxed(s2cr, gr0_base + ARM_SMMU_GR0_S2CR(idx)); |
| 1973 | } |
| 1974 | |
| 1975 | return 0; |
| 1976 | } |
| 1977 | |
| 1978 | static void arm_smmu_domain_remove_master(struct arm_smmu_domain *smmu_domain, |
Will Deacon | a9a1b0b | 2014-05-01 18:05:08 +0100 | [diff] [blame] | 1979 | struct arm_smmu_master_cfg *cfg) |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1980 | { |
Will Deacon | 43b412b | 2014-07-15 11:22:24 +0100 | [diff] [blame] | 1981 | int i; |
Will Deacon | 44680ee | 2014-06-25 11:29:12 +0100 | [diff] [blame] | 1982 | struct arm_smmu_device *smmu = smmu_domain->smmu; |
Will Deacon | 43b412b | 2014-07-15 11:22:24 +0100 | [diff] [blame] | 1983 | void __iomem *gr0_base = ARM_SMMU_GR0(smmu); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1984 | |
Will Deacon | 8f68f8e | 2014-07-15 11:27:08 +0100 | [diff] [blame] | 1985 | /* An IOMMU group is torn down by the first device to be removed */ |
| 1986 | if ((smmu->features & ARM_SMMU_FEAT_STREAM_MATCH) && !cfg->smrs) |
| 1987 | return; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1988 | |
| 1989 | /* |
| 1990 | * We *must* clear the S2CR first, because freeing the SMR means |
| 1991 | * that it can be re-allocated immediately. |
| 1992 | */ |
Will Deacon | 43b412b | 2014-07-15 11:22:24 +0100 | [diff] [blame] | 1993 | for (i = 0; i < cfg->num_streamids; ++i) { |
| 1994 | u32 idx = cfg->smrs ? cfg->smrs[i].idx : cfg->streamids[i]; |
Robin Murphy | 25a1c96 | 2016-02-10 14:25:33 +0000 | [diff] [blame] | 1995 | u32 reg = disable_bypass ? S2CR_TYPE_FAULT : S2CR_TYPE_BYPASS; |
Will Deacon | 43b412b | 2014-07-15 11:22:24 +0100 | [diff] [blame] | 1996 | |
Robin Murphy | 25a1c96 | 2016-02-10 14:25:33 +0000 | [diff] [blame] | 1997 | writel_relaxed(reg, gr0_base + ARM_SMMU_GR0_S2CR(idx)); |
Will Deacon | 43b412b | 2014-07-15 11:22:24 +0100 | [diff] [blame] | 1998 | } |
| 1999 | |
Will Deacon | a9a1b0b | 2014-05-01 18:05:08 +0100 | [diff] [blame] | 2000 | arm_smmu_master_free_smrs(smmu, cfg); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 2001 | } |
| 2002 | |
Patrick Daly | 0980131 | 2016-08-29 17:02:52 -0700 | [diff] [blame] | 2003 | static void arm_smmu_detach_dev(struct iommu_domain *domain, |
| 2004 | struct device *dev) |
Will Deacon | bc7f2ce | 2016-02-17 17:41:57 +0000 | [diff] [blame] | 2005 | { |
Will Deacon | bc7f2ce | 2016-02-17 17:41:57 +0000 | [diff] [blame] | 2006 | struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); |
Patrick Daly | 0980131 | 2016-08-29 17:02:52 -0700 | [diff] [blame] | 2007 | struct arm_smmu_device *smmu = smmu_domain->smmu; |
| 2008 | struct arm_smmu_master_cfg *cfg; |
| 2009 | int dynamic = smmu_domain->attributes & (1 << DOMAIN_ATTR_DYNAMIC); |
Patrick Daly | 8befb66 | 2016-08-17 20:03:28 -0700 | [diff] [blame] | 2010 | int atomic_domain = smmu_domain->attributes & (1 << DOMAIN_ATTR_ATOMIC); |
Patrick Daly | 0980131 | 2016-08-29 17:02:52 -0700 | [diff] [blame] | 2011 | |
| 2012 | if (dynamic) |
| 2013 | return; |
| 2014 | |
| 2015 | cfg = find_smmu_master_cfg(dev); |
| 2016 | if (!cfg) |
| 2017 | return; |
| 2018 | |
| 2019 | if (!smmu) { |
| 2020 | dev_err(dev, "Domain not attached; cannot detach!\n"); |
| 2021 | return; |
| 2022 | } |
Will Deacon | bc7f2ce | 2016-02-17 17:41:57 +0000 | [diff] [blame] | 2023 | |
| 2024 | dev->archdata.iommu = NULL; |
| 2025 | arm_smmu_domain_remove_master(smmu_domain, cfg); |
Patrick Daly | 8befb66 | 2016-08-17 20:03:28 -0700 | [diff] [blame] | 2026 | |
| 2027 | /* Remove additional vote for atomic power */ |
| 2028 | if (atomic_domain) { |
| 2029 | WARN_ON(arm_smmu_enable_clocks_atomic(smmu)); |
| 2030 | arm_smmu_power_off(smmu); |
| 2031 | } |
Will Deacon | bc7f2ce | 2016-02-17 17:41:57 +0000 | [diff] [blame] | 2032 | } |
| 2033 | |
Patrick Daly | e271f21 | 2016-10-04 13:24:49 -0700 | [diff] [blame] | 2034 | static int arm_smmu_assign_table(struct arm_smmu_domain *smmu_domain) |
Patrick Daly | c11d108 | 2016-09-01 15:52:44 -0700 | [diff] [blame] | 2035 | { |
Patrick Daly | e271f21 | 2016-10-04 13:24:49 -0700 | [diff] [blame] | 2036 | int ret = 0; |
Patrick Daly | c11d108 | 2016-09-01 15:52:44 -0700 | [diff] [blame] | 2037 | int dest_vmids[2] = {VMID_HLOS, smmu_domain->secure_vmid}; |
| 2038 | int dest_perms[2] = {PERM_READ | PERM_WRITE, PERM_READ}; |
| 2039 | int source_vmid = VMID_HLOS; |
| 2040 | struct arm_smmu_pte_info *pte_info, *temp; |
| 2041 | |
Patrick Daly | e271f21 | 2016-10-04 13:24:49 -0700 | [diff] [blame] | 2042 | if (!arm_smmu_is_domain_secure(smmu_domain)) |
| 2043 | return ret; |
Patrick Daly | c11d108 | 2016-09-01 15:52:44 -0700 | [diff] [blame] | 2044 | |
Patrick Daly | e271f21 | 2016-10-04 13:24:49 -0700 | [diff] [blame] | 2045 | list_for_each_entry(pte_info, &smmu_domain->pte_info_list, entry) { |
Patrick Daly | c11d108 | 2016-09-01 15:52:44 -0700 | [diff] [blame] | 2046 | ret = hyp_assign_phys(virt_to_phys(pte_info->virt_addr), |
| 2047 | PAGE_SIZE, &source_vmid, 1, |
| 2048 | dest_vmids, dest_perms, 2); |
| 2049 | if (WARN_ON(ret)) |
| 2050 | break; |
| 2051 | } |
| 2052 | |
| 2053 | list_for_each_entry_safe(pte_info, temp, &smmu_domain->pte_info_list, |
| 2054 | entry) { |
| 2055 | list_del(&pte_info->entry); |
| 2056 | kfree(pte_info); |
| 2057 | } |
Patrick Daly | e271f21 | 2016-10-04 13:24:49 -0700 | [diff] [blame] | 2058 | return ret; |
Patrick Daly | c11d108 | 2016-09-01 15:52:44 -0700 | [diff] [blame] | 2059 | } |
| 2060 | |
| 2061 | static void arm_smmu_unassign_table(struct arm_smmu_domain *smmu_domain) |
| 2062 | { |
| 2063 | int ret; |
| 2064 | int dest_vmids = VMID_HLOS; |
Neeti Desai | 6100737 | 2015-07-28 11:02:02 -0700 | [diff] [blame] | 2065 | int dest_perms = PERM_READ | PERM_WRITE | PERM_EXEC; |
Patrick Daly | c11d108 | 2016-09-01 15:52:44 -0700 | [diff] [blame] | 2066 | int source_vmlist[2] = {VMID_HLOS, smmu_domain->secure_vmid}; |
| 2067 | struct arm_smmu_pte_info *pte_info, *temp; |
| 2068 | |
Patrick Daly | e271f21 | 2016-10-04 13:24:49 -0700 | [diff] [blame] | 2069 | if (!arm_smmu_is_domain_secure(smmu_domain)) |
Patrick Daly | c11d108 | 2016-09-01 15:52:44 -0700 | [diff] [blame] | 2070 | return; |
| 2071 | |
| 2072 | list_for_each_entry(pte_info, &smmu_domain->unassign_list, entry) { |
| 2073 | ret = hyp_assign_phys(virt_to_phys(pte_info->virt_addr), |
| 2074 | PAGE_SIZE, source_vmlist, 2, |
| 2075 | &dest_vmids, &dest_perms, 1); |
| 2076 | if (WARN_ON(ret)) |
| 2077 | break; |
| 2078 | free_pages_exact(pte_info->virt_addr, pte_info->size); |
| 2079 | } |
| 2080 | |
| 2081 | list_for_each_entry_safe(pte_info, temp, &smmu_domain->unassign_list, |
| 2082 | entry) { |
| 2083 | list_del(&pte_info->entry); |
| 2084 | kfree(pte_info); |
| 2085 | } |
| 2086 | } |
| 2087 | |
| 2088 | static void arm_smmu_unprepare_pgtable(void *cookie, void *addr, size_t size) |
| 2089 | { |
| 2090 | struct arm_smmu_domain *smmu_domain = cookie; |
| 2091 | struct arm_smmu_pte_info *pte_info; |
| 2092 | |
Patrick Daly | b7dfda7 | 2016-10-04 14:42:58 -0700 | [diff] [blame] | 2093 | BUG_ON(!arm_smmu_is_domain_secure(smmu_domain)); |
Patrick Daly | c11d108 | 2016-09-01 15:52:44 -0700 | [diff] [blame] | 2094 | |
| 2095 | pte_info = kzalloc(sizeof(struct arm_smmu_pte_info), GFP_ATOMIC); |
| 2096 | if (!pte_info) |
| 2097 | return; |
| 2098 | |
| 2099 | pte_info->virt_addr = addr; |
| 2100 | pte_info->size = size; |
| 2101 | list_add_tail(&pte_info->entry, &smmu_domain->unassign_list); |
| 2102 | } |
| 2103 | |
| 2104 | static int arm_smmu_prepare_pgtable(void *addr, void *cookie) |
| 2105 | { |
| 2106 | struct arm_smmu_domain *smmu_domain = cookie; |
| 2107 | struct arm_smmu_pte_info *pte_info; |
| 2108 | |
Patrick Daly | b7dfda7 | 2016-10-04 14:42:58 -0700 | [diff] [blame] | 2109 | BUG_ON(!arm_smmu_is_domain_secure(smmu_domain)); |
Patrick Daly | c11d108 | 2016-09-01 15:52:44 -0700 | [diff] [blame] | 2110 | |
| 2111 | pte_info = kzalloc(sizeof(struct arm_smmu_pte_info), GFP_ATOMIC); |
| 2112 | if (!pte_info) |
| 2113 | return -ENOMEM; |
| 2114 | pte_info->virt_addr = addr; |
| 2115 | list_add_tail(&pte_info->entry, &smmu_domain->pte_info_list); |
| 2116 | return 0; |
| 2117 | } |
| 2118 | |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 2119 | static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev) |
| 2120 | { |
Mitchel Humpherys | a18037b | 2014-07-30 18:58:13 +0100 | [diff] [blame] | 2121 | int ret; |
Joerg Roedel | 1d67263 | 2015-03-26 13:43:10 +0100 | [diff] [blame] | 2122 | struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame] | 2123 | struct arm_smmu_device *smmu; |
Will Deacon | a9a1b0b | 2014-05-01 18:05:08 +0100 | [diff] [blame] | 2124 | struct arm_smmu_master_cfg *cfg; |
Patrick Daly | 8befb66 | 2016-08-17 20:03:28 -0700 | [diff] [blame] | 2125 | int atomic_domain = smmu_domain->attributes & (1 << DOMAIN_ATTR_ATOMIC); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 2126 | |
Will Deacon | 8f68f8e | 2014-07-15 11:27:08 +0100 | [diff] [blame] | 2127 | smmu = find_smmu_for_device(dev); |
Will Deacon | 44680ee | 2014-06-25 11:29:12 +0100 | [diff] [blame] | 2128 | if (!smmu) { |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 2129 | dev_err(dev, "cannot attach to SMMU, is it on the same bus?\n"); |
| 2130 | return -ENXIO; |
| 2131 | } |
| 2132 | |
Patrick Daly | 3a8a88a | 2016-07-22 12:24:05 -0700 | [diff] [blame] | 2133 | /* Enable Clocks and Power */ |
| 2134 | ret = arm_smmu_power_on(smmu); |
| 2135 | if (ret) |
| 2136 | return ret; |
| 2137 | |
Patrick Daly | 8befb66 | 2016-08-17 20:03:28 -0700 | [diff] [blame] | 2138 | /* |
| 2139 | * Keep an additional vote for non-atomic power until domain is |
| 2140 | * detached |
| 2141 | */ |
| 2142 | if (atomic_domain) { |
| 2143 | ret = arm_smmu_power_on(smmu); |
| 2144 | if (ret) |
| 2145 | goto out_power_off; |
| 2146 | |
| 2147 | arm_smmu_disable_clocks_atomic(smmu); |
| 2148 | } |
| 2149 | |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame] | 2150 | /* Ensure that the domain is finalised */ |
| 2151 | ret = arm_smmu_init_domain_context(domain, smmu); |
Arnd Bergmann | 287980e | 2016-05-27 23:23:25 +0200 | [diff] [blame] | 2152 | if (ret < 0) |
Patrick Daly | 3a8a88a | 2016-07-22 12:24:05 -0700 | [diff] [blame] | 2153 | goto out_power_off; |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame] | 2154 | |
Patrick Daly | c190d93 | 2016-08-30 17:23:28 -0700 | [diff] [blame] | 2155 | /* Do not modify the SIDs, HW is still running */ |
Patrick Daly | 3a8a88a | 2016-07-22 12:24:05 -0700 | [diff] [blame] | 2156 | if (is_dynamic_domain(domain)) { |
| 2157 | ret = 0; |
| 2158 | goto out_power_off; |
| 2159 | } |
Patrick Daly | c190d93 | 2016-08-30 17:23:28 -0700 | [diff] [blame] | 2160 | |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 2161 | /* |
Will Deacon | 44680ee | 2014-06-25 11:29:12 +0100 | [diff] [blame] | 2162 | * Sanity check the domain. We don't support domains across |
| 2163 | * different SMMUs. |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 2164 | */ |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame] | 2165 | if (smmu_domain->smmu != smmu) { |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 2166 | dev_err(dev, |
| 2167 | "cannot attach to SMMU %s whilst already attached to domain on SMMU %s\n", |
Mitchel Humpherys | a18037b | 2014-07-30 18:58:13 +0100 | [diff] [blame] | 2168 | dev_name(smmu_domain->smmu->dev), dev_name(smmu->dev)); |
Patrick Daly | 3a8a88a | 2016-07-22 12:24:05 -0700 | [diff] [blame] | 2169 | ret = -EINVAL; |
| 2170 | goto out_power_off; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 2171 | } |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 2172 | |
| 2173 | /* Looks ok, so add the device to the domain */ |
Will Deacon | 8f68f8e | 2014-07-15 11:27:08 +0100 | [diff] [blame] | 2174 | cfg = find_smmu_master_cfg(dev); |
Patrick Daly | 3a8a88a | 2016-07-22 12:24:05 -0700 | [diff] [blame] | 2175 | if (!cfg) { |
| 2176 | ret = -ENODEV; |
| 2177 | goto out_power_off; |
| 2178 | } |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 2179 | |
Will Deacon | bc7f2ce | 2016-02-17 17:41:57 +0000 | [diff] [blame] | 2180 | /* Detach the dev from its current domain */ |
| 2181 | if (dev->archdata.iommu) |
Patrick Daly | 0980131 | 2016-08-29 17:02:52 -0700 | [diff] [blame] | 2182 | arm_smmu_detach_dev(dev->archdata.iommu, dev); |
Will Deacon | bc7f2ce | 2016-02-17 17:41:57 +0000 | [diff] [blame] | 2183 | |
Will Deacon | 844e35b | 2014-07-17 11:23:51 +0100 | [diff] [blame] | 2184 | ret = arm_smmu_domain_add_master(smmu_domain, cfg); |
| 2185 | if (!ret) |
| 2186 | dev->archdata.iommu = domain; |
Patrick Daly | 3a8a88a | 2016-07-22 12:24:05 -0700 | [diff] [blame] | 2187 | |
| 2188 | out_power_off: |
| 2189 | arm_smmu_power_off(smmu); |
| 2190 | |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 2191 | return ret; |
| 2192 | } |
| 2193 | |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 2194 | static int arm_smmu_map(struct iommu_domain *domain, unsigned long iova, |
Will Deacon | b410aed | 2014-02-20 16:31:06 +0000 | [diff] [blame] | 2195 | phys_addr_t paddr, size_t size, int prot) |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 2196 | { |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame] | 2197 | int ret; |
| 2198 | unsigned long flags; |
Joerg Roedel | 1d67263 | 2015-03-26 13:43:10 +0100 | [diff] [blame] | 2199 | struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame] | 2200 | struct io_pgtable_ops *ops= smmu_domain->pgtbl_ops; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 2201 | |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame] | 2202 | if (!ops) |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 2203 | return -ENODEV; |
| 2204 | |
Patrick Daly | e271f21 | 2016-10-04 13:24:49 -0700 | [diff] [blame] | 2205 | arm_smmu_secure_domain_lock(smmu_domain); |
| 2206 | |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame] | 2207 | spin_lock_irqsave(&smmu_domain->pgtbl_lock, flags); |
| 2208 | ret = ops->map(ops, iova, paddr, size, prot); |
| 2209 | spin_unlock_irqrestore(&smmu_domain->pgtbl_lock, flags); |
Patrick Daly | c11d108 | 2016-09-01 15:52:44 -0700 | [diff] [blame] | 2210 | |
| 2211 | arm_smmu_assign_table(smmu_domain); |
Patrick Daly | e271f21 | 2016-10-04 13:24:49 -0700 | [diff] [blame] | 2212 | arm_smmu_secure_domain_unlock(smmu_domain); |
Patrick Daly | c11d108 | 2016-09-01 15:52:44 -0700 | [diff] [blame] | 2213 | |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame] | 2214 | return ret; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 2215 | } |
| 2216 | |
| 2217 | static size_t arm_smmu_unmap(struct iommu_domain *domain, unsigned long iova, |
| 2218 | size_t size) |
| 2219 | { |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame] | 2220 | size_t ret; |
| 2221 | unsigned long flags; |
Joerg Roedel | 1d67263 | 2015-03-26 13:43:10 +0100 | [diff] [blame] | 2222 | struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame] | 2223 | struct io_pgtable_ops *ops= smmu_domain->pgtbl_ops; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 2224 | |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame] | 2225 | if (!ops) |
| 2226 | return 0; |
| 2227 | |
Patrick Daly | 8befb66 | 2016-08-17 20:03:28 -0700 | [diff] [blame] | 2228 | ret = arm_smmu_domain_power_on(domain, smmu_domain->smmu); |
Patrick Daly | 3a8a88a | 2016-07-22 12:24:05 -0700 | [diff] [blame] | 2229 | if (ret) |
| 2230 | return ret; |
| 2231 | |
Patrick Daly | e271f21 | 2016-10-04 13:24:49 -0700 | [diff] [blame] | 2232 | arm_smmu_secure_domain_lock(smmu_domain); |
| 2233 | |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame] | 2234 | spin_lock_irqsave(&smmu_domain->pgtbl_lock, flags); |
| 2235 | ret = ops->unmap(ops, iova, size); |
| 2236 | spin_unlock_irqrestore(&smmu_domain->pgtbl_lock, flags); |
Patrick Daly | 3a8a88a | 2016-07-22 12:24:05 -0700 | [diff] [blame] | 2237 | |
Patrick Daly | 8befb66 | 2016-08-17 20:03:28 -0700 | [diff] [blame] | 2238 | arm_smmu_domain_power_off(domain, smmu_domain->smmu); |
Patrick Daly | c11d108 | 2016-09-01 15:52:44 -0700 | [diff] [blame] | 2239 | /* |
| 2240 | * While splitting up block mappings, we might allocate page table |
| 2241 | * memory during unmap, so the vmids needs to be assigned to the |
| 2242 | * memory here as well. |
| 2243 | */ |
| 2244 | arm_smmu_assign_table(smmu_domain); |
| 2245 | /* Also unassign any pages that were free'd during unmap */ |
| 2246 | arm_smmu_unassign_table(smmu_domain); |
Patrick Daly | e271f21 | 2016-10-04 13:24:49 -0700 | [diff] [blame] | 2247 | arm_smmu_secure_domain_unlock(smmu_domain); |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame] | 2248 | return ret; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 2249 | } |
| 2250 | |
Mitchel Humpherys | 622bc04 | 2015-04-23 16:29:23 -0700 | [diff] [blame] | 2251 | static size_t arm_smmu_map_sg(struct iommu_domain *domain, unsigned long iova, |
| 2252 | struct scatterlist *sg, unsigned int nents, int prot) |
| 2253 | { |
| 2254 | int ret; |
Rohit Vaswani | 4d7cdd9 | 2015-08-18 17:57:44 -0700 | [diff] [blame] | 2255 | size_t size; |
Mitchel Humpherys | 622bc04 | 2015-04-23 16:29:23 -0700 | [diff] [blame] | 2256 | unsigned long flags; |
| 2257 | struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); |
| 2258 | struct io_pgtable_ops *ops = smmu_domain->pgtbl_ops; |
| 2259 | |
| 2260 | if (!ops) |
| 2261 | return -ENODEV; |
| 2262 | |
Patrick Daly | 8befb66 | 2016-08-17 20:03:28 -0700 | [diff] [blame] | 2263 | ret = arm_smmu_domain_power_on(domain, smmu_domain->smmu); |
Patrick Daly | 3a8a88a | 2016-07-22 12:24:05 -0700 | [diff] [blame] | 2264 | if (ret) |
| 2265 | return ret; |
| 2266 | |
Mitchel Humpherys | 622bc04 | 2015-04-23 16:29:23 -0700 | [diff] [blame] | 2267 | spin_lock_irqsave(&smmu_domain->pgtbl_lock, flags); |
Rohit Vaswani | 4d7cdd9 | 2015-08-18 17:57:44 -0700 | [diff] [blame] | 2268 | ret = ops->map_sg(ops, iova, sg, nents, prot, &size); |
Mitchel Humpherys | 622bc04 | 2015-04-23 16:29:23 -0700 | [diff] [blame] | 2269 | spin_unlock_irqrestore(&smmu_domain->pgtbl_lock, flags); |
Rohit Vaswani | 4d7cdd9 | 2015-08-18 17:57:44 -0700 | [diff] [blame] | 2270 | |
| 2271 | if (!ret) |
| 2272 | arm_smmu_unmap(domain, iova, size); |
| 2273 | |
Patrick Daly | 8befb66 | 2016-08-17 20:03:28 -0700 | [diff] [blame] | 2274 | arm_smmu_domain_power_off(domain, smmu_domain->smmu); |
Patrick Daly | c11d108 | 2016-09-01 15:52:44 -0700 | [diff] [blame] | 2275 | arm_smmu_assign_table(smmu_domain); |
| 2276 | |
Mitchel Humpherys | 622bc04 | 2015-04-23 16:29:23 -0700 | [diff] [blame] | 2277 | return ret; |
| 2278 | } |
| 2279 | |
Mitchel Humpherys | fb11f70 | 2015-07-06 13:53:51 -0700 | [diff] [blame] | 2280 | static phys_addr_t __arm_smmu_iova_to_phys_hard(struct iommu_domain *domain, |
Patrick Daly | d54eafd | 2016-08-23 17:01:43 -0700 | [diff] [blame] | 2281 | dma_addr_t iova, bool do_halt) |
Mitchel Humpherys | 859a732 | 2014-10-29 21:13:40 +0000 | [diff] [blame] | 2282 | { |
Joerg Roedel | 1d67263 | 2015-03-26 13:43:10 +0100 | [diff] [blame] | 2283 | struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); |
Mitchel Humpherys | 859a732 | 2014-10-29 21:13:40 +0000 | [diff] [blame] | 2284 | struct arm_smmu_device *smmu = smmu_domain->smmu; |
| 2285 | struct arm_smmu_cfg *cfg = &smmu_domain->cfg; |
| 2286 | struct io_pgtable_ops *ops= smmu_domain->pgtbl_ops; |
| 2287 | struct device *dev = smmu->dev; |
| 2288 | void __iomem *cb_base; |
Mitchel Humpherys | 2fbae2a | 2014-12-04 11:46:24 -0800 | [diff] [blame] | 2289 | unsigned long flags; |
Mitchel Humpherys | 859a732 | 2014-10-29 21:13:40 +0000 | [diff] [blame] | 2290 | u32 tmp; |
| 2291 | u64 phys; |
Robin Murphy | 661d962 | 2015-05-27 17:09:34 +0100 | [diff] [blame] | 2292 | unsigned long va; |
Mitchel Humpherys | 859a732 | 2014-10-29 21:13:40 +0000 | [diff] [blame] | 2293 | |
Mitchel Humpherys | 2fbae2a | 2014-12-04 11:46:24 -0800 | [diff] [blame] | 2294 | spin_lock_irqsave(&smmu->atos_lock, flags); |
Patrick Daly | d54eafd | 2016-08-23 17:01:43 -0700 | [diff] [blame] | 2295 | if (do_halt && arm_smmu_halt(smmu)) { |
Mitchel Humpherys | 0ed5da6 | 2014-12-04 11:47:49 -0800 | [diff] [blame] | 2296 | phys = 0; |
| 2297 | goto out_unlock; |
| 2298 | } |
| 2299 | |
Mitchel Humpherys | 859a732 | 2014-10-29 21:13:40 +0000 | [diff] [blame] | 2300 | cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx); |
| 2301 | |
Robin Murphy | 661d962 | 2015-05-27 17:09:34 +0100 | [diff] [blame] | 2302 | /* ATS1 registers can only be written atomically */ |
| 2303 | va = iova & ~0xfffUL; |
Robin Murphy | 661d962 | 2015-05-27 17:09:34 +0100 | [diff] [blame] | 2304 | if (smmu->version == ARM_SMMU_V2) |
Robin Murphy | f9a05f0 | 2016-04-13 18:13:01 +0100 | [diff] [blame] | 2305 | smmu_write_atomic_lq(va, cb_base + ARM_SMMU_CB_ATS1PR); |
| 2306 | else /* Register is only 32-bit in v1 */ |
Robin Murphy | 661d962 | 2015-05-27 17:09:34 +0100 | [diff] [blame] | 2307 | writel_relaxed(va, cb_base + ARM_SMMU_CB_ATS1PR); |
Mitchel Humpherys | 859a732 | 2014-10-29 21:13:40 +0000 | [diff] [blame] | 2308 | |
| 2309 | if (readl_poll_timeout_atomic(cb_base + ARM_SMMU_CB_ATSR, tmp, |
| 2310 | !(tmp & ATSR_ACTIVE), 5, 50)) { |
Mitchel Humpherys | 0ed5da6 | 2014-12-04 11:47:49 -0800 | [diff] [blame] | 2311 | phys = ops->iova_to_phys(ops, iova); |
Mitchel Humpherys | d7e0971 | 2015-02-04 21:30:58 -0800 | [diff] [blame] | 2312 | dev_err(dev, |
| 2313 | "iova to phys timed out on %pad. software table walk result=%pa.\n", |
| 2314 | &iova, &phys); |
| 2315 | phys = 0; |
Mitchel Humpherys | 0ed5da6 | 2014-12-04 11:47:49 -0800 | [diff] [blame] | 2316 | goto out_resume; |
Mitchel Humpherys | 859a732 | 2014-10-29 21:13:40 +0000 | [diff] [blame] | 2317 | } |
| 2318 | |
Robin Murphy | f9a05f0 | 2016-04-13 18:13:01 +0100 | [diff] [blame] | 2319 | phys = readq_relaxed(cb_base + ARM_SMMU_CB_PAR); |
Mitchel Humpherys | 859a732 | 2014-10-29 21:13:40 +0000 | [diff] [blame] | 2320 | if (phys & CB_PAR_F) { |
| 2321 | dev_err(dev, "translation fault!\n"); |
| 2322 | dev_err(dev, "PAR = 0x%llx\n", phys); |
Mitchel Humpherys | 0ed5da6 | 2014-12-04 11:47:49 -0800 | [diff] [blame] | 2323 | phys = 0; |
| 2324 | } else { |
| 2325 | phys = (phys & (PHYS_MASK & ~0xfffULL)) | (iova & 0xfff); |
Mitchel Humpherys | 859a732 | 2014-10-29 21:13:40 +0000 | [diff] [blame] | 2326 | } |
Mitchel Humpherys | 0ed5da6 | 2014-12-04 11:47:49 -0800 | [diff] [blame] | 2327 | out_resume: |
Patrick Daly | d54eafd | 2016-08-23 17:01:43 -0700 | [diff] [blame] | 2328 | if (do_halt) |
| 2329 | arm_smmu_resume(smmu); |
Mitchel Humpherys | 0ed5da6 | 2014-12-04 11:47:49 -0800 | [diff] [blame] | 2330 | out_unlock: |
Mitchel Humpherys | 2fbae2a | 2014-12-04 11:46:24 -0800 | [diff] [blame] | 2331 | spin_unlock_irqrestore(&smmu->atos_lock, flags); |
Mitchel Humpherys | 0ed5da6 | 2014-12-04 11:47:49 -0800 | [diff] [blame] | 2332 | return phys; |
Mitchel Humpherys | 859a732 | 2014-10-29 21:13:40 +0000 | [diff] [blame] | 2333 | } |
| 2334 | |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 2335 | static phys_addr_t arm_smmu_iova_to_phys(struct iommu_domain *domain, |
Mitchel Humpherys | 859a732 | 2014-10-29 21:13:40 +0000 | [diff] [blame] | 2336 | dma_addr_t iova) |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 2337 | { |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame] | 2338 | phys_addr_t ret; |
| 2339 | unsigned long flags; |
Joerg Roedel | 1d67263 | 2015-03-26 13:43:10 +0100 | [diff] [blame] | 2340 | struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame] | 2341 | struct io_pgtable_ops *ops= smmu_domain->pgtbl_ops; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 2342 | |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame] | 2343 | if (!ops) |
Will Deacon | a44a979 | 2013-11-07 18:47:50 +0000 | [diff] [blame] | 2344 | return 0; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 2345 | |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame] | 2346 | spin_lock_irqsave(&smmu_domain->pgtbl_lock, flags); |
Patrick Daly | a85a2fb | 2016-06-21 19:23:06 -0700 | [diff] [blame] | 2347 | ret = ops->iova_to_phys(ops, iova); |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame] | 2348 | spin_unlock_irqrestore(&smmu_domain->pgtbl_lock, flags); |
Mitchel Humpherys | 859a732 | 2014-10-29 21:13:40 +0000 | [diff] [blame] | 2349 | |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame] | 2350 | return ret; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 2351 | } |
| 2352 | |
Mitchel Humpherys | fb11f70 | 2015-07-06 13:53:51 -0700 | [diff] [blame] | 2353 | /* |
| 2354 | * This function can sleep, and cannot be called from atomic context. Will |
| 2355 | * power on register block if required. This restriction does not apply to the |
| 2356 | * original iova_to_phys() op. |
| 2357 | */ |
| 2358 | static phys_addr_t arm_smmu_iova_to_phys_hard(struct iommu_domain *domain, |
| 2359 | dma_addr_t iova) |
| 2360 | { |
| 2361 | phys_addr_t ret = 0; |
| 2362 | unsigned long flags; |
| 2363 | struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); |
Patrick Daly | 3a8a88a | 2016-07-22 12:24:05 -0700 | [diff] [blame] | 2364 | int err; |
| 2365 | |
| 2366 | err = arm_smmu_power_on(smmu_domain->smmu); |
| 2367 | if (err) |
| 2368 | return 0; |
Mitchel Humpherys | fb11f70 | 2015-07-06 13:53:51 -0700 | [diff] [blame] | 2369 | |
| 2370 | spin_lock_irqsave(&smmu_domain->pgtbl_lock, flags); |
| 2371 | if (smmu_domain->smmu->features & ARM_SMMU_FEAT_TRANS_OPS && |
| 2372 | smmu_domain->stage == ARM_SMMU_DOMAIN_S1) |
Patrick Daly | d54eafd | 2016-08-23 17:01:43 -0700 | [diff] [blame] | 2373 | ret = __arm_smmu_iova_to_phys_hard(domain, iova, true); |
Mitchel Humpherys | fb11f70 | 2015-07-06 13:53:51 -0700 | [diff] [blame] | 2374 | |
| 2375 | spin_unlock_irqrestore(&smmu_domain->pgtbl_lock, flags); |
| 2376 | |
Patrick Daly | 3a8a88a | 2016-07-22 12:24:05 -0700 | [diff] [blame] | 2377 | arm_smmu_power_off(smmu_domain->smmu); |
Mitchel Humpherys | fb11f70 | 2015-07-06 13:53:51 -0700 | [diff] [blame] | 2378 | return ret; |
| 2379 | } |
| 2380 | |
Patrick Daly | d54eafd | 2016-08-23 17:01:43 -0700 | [diff] [blame] | 2381 | static phys_addr_t arm_smmu_iova_to_phys_hard_no_halt( |
| 2382 | struct iommu_domain *domain, dma_addr_t iova) |
| 2383 | { |
| 2384 | return __arm_smmu_iova_to_phys_hard(domain, iova, false); |
| 2385 | } |
| 2386 | |
Joerg Roedel | 1fd0c77 | 2014-09-05 10:49:34 +0200 | [diff] [blame] | 2387 | static bool arm_smmu_capable(enum iommu_cap cap) |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 2388 | { |
Will Deacon | d094894 | 2014-06-24 17:30:10 +0100 | [diff] [blame] | 2389 | switch (cap) { |
| 2390 | case IOMMU_CAP_CACHE_COHERENCY: |
Joerg Roedel | 1fd0c77 | 2014-09-05 10:49:34 +0200 | [diff] [blame] | 2391 | /* |
| 2392 | * Return true here as the SMMU can always send out coherent |
| 2393 | * requests. |
| 2394 | */ |
| 2395 | return true; |
Will Deacon | d094894 | 2014-06-24 17:30:10 +0100 | [diff] [blame] | 2396 | case IOMMU_CAP_INTR_REMAP: |
Joerg Roedel | 1fd0c77 | 2014-09-05 10:49:34 +0200 | [diff] [blame] | 2397 | return true; /* MSIs are just memory writes */ |
Antonios Motakis | 0029a8d | 2014-10-13 14:06:18 +0100 | [diff] [blame] | 2398 | case IOMMU_CAP_NOEXEC: |
| 2399 | return true; |
Will Deacon | d094894 | 2014-06-24 17:30:10 +0100 | [diff] [blame] | 2400 | default: |
Joerg Roedel | 1fd0c77 | 2014-09-05 10:49:34 +0200 | [diff] [blame] | 2401 | return false; |
Will Deacon | d094894 | 2014-06-24 17:30:10 +0100 | [diff] [blame] | 2402 | } |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 2403 | } |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 2404 | |
Will Deacon | a9a1b0b | 2014-05-01 18:05:08 +0100 | [diff] [blame] | 2405 | static int __arm_smmu_get_pci_sid(struct pci_dev *pdev, u16 alias, void *data) |
| 2406 | { |
| 2407 | *((u16 *)data) = alias; |
| 2408 | return 0; /* Continue walking */ |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 2409 | } |
| 2410 | |
Will Deacon | 8f68f8e | 2014-07-15 11:27:08 +0100 | [diff] [blame] | 2411 | static void __arm_smmu_release_pci_iommudata(void *data) |
| 2412 | { |
| 2413 | kfree(data); |
| 2414 | } |
| 2415 | |
Joerg Roedel | af65993 | 2015-10-21 23:51:41 +0200 | [diff] [blame] | 2416 | static int arm_smmu_init_pci_device(struct pci_dev *pdev, |
| 2417 | struct iommu_group *group) |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 2418 | { |
Will Deacon | 03edb22 | 2015-01-19 14:27:33 +0000 | [diff] [blame] | 2419 | struct arm_smmu_master_cfg *cfg; |
Joerg Roedel | af65993 | 2015-10-21 23:51:41 +0200 | [diff] [blame] | 2420 | u16 sid; |
| 2421 | int i; |
Antonios Motakis | 5fc63a7 | 2013-10-18 16:08:29 +0100 | [diff] [blame] | 2422 | |
Will Deacon | 03edb22 | 2015-01-19 14:27:33 +0000 | [diff] [blame] | 2423 | cfg = iommu_group_get_iommudata(group); |
| 2424 | if (!cfg) { |
Will Deacon | a9a1b0b | 2014-05-01 18:05:08 +0100 | [diff] [blame] | 2425 | cfg = kzalloc(sizeof(*cfg), GFP_KERNEL); |
Joerg Roedel | af65993 | 2015-10-21 23:51:41 +0200 | [diff] [blame] | 2426 | if (!cfg) |
| 2427 | return -ENOMEM; |
Will Deacon | a9a1b0b | 2014-05-01 18:05:08 +0100 | [diff] [blame] | 2428 | |
Will Deacon | 03edb22 | 2015-01-19 14:27:33 +0000 | [diff] [blame] | 2429 | iommu_group_set_iommudata(group, cfg, |
| 2430 | __arm_smmu_release_pci_iommudata); |
Will Deacon | a9a1b0b | 2014-05-01 18:05:08 +0100 | [diff] [blame] | 2431 | } |
| 2432 | |
Joerg Roedel | af65993 | 2015-10-21 23:51:41 +0200 | [diff] [blame] | 2433 | if (cfg->num_streamids >= MAX_MASTER_STREAMIDS) |
| 2434 | return -ENOSPC; |
Will Deacon | a9a1b0b | 2014-05-01 18:05:08 +0100 | [diff] [blame] | 2435 | |
Will Deacon | 03edb22 | 2015-01-19 14:27:33 +0000 | [diff] [blame] | 2436 | /* |
| 2437 | * Assume Stream ID == Requester ID for now. |
| 2438 | * We need a way to describe the ID mappings in FDT. |
| 2439 | */ |
| 2440 | pci_for_each_dma_alias(pdev, __arm_smmu_get_pci_sid, &sid); |
| 2441 | for (i = 0; i < cfg->num_streamids; ++i) |
| 2442 | if (cfg->streamids[i] == sid) |
| 2443 | break; |
| 2444 | |
| 2445 | /* Avoid duplicate SIDs, as this can lead to SMR conflicts */ |
| 2446 | if (i == cfg->num_streamids) |
| 2447 | cfg->streamids[cfg->num_streamids++] = sid; |
| 2448 | |
| 2449 | return 0; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 2450 | } |
| 2451 | |
Joerg Roedel | af65993 | 2015-10-21 23:51:41 +0200 | [diff] [blame] | 2452 | static int arm_smmu_init_platform_device(struct device *dev, |
| 2453 | struct iommu_group *group) |
Will Deacon | 03edb22 | 2015-01-19 14:27:33 +0000 | [diff] [blame] | 2454 | { |
Will Deacon | 03edb22 | 2015-01-19 14:27:33 +0000 | [diff] [blame] | 2455 | struct arm_smmu_device *smmu = find_smmu_for_device(dev); |
Joerg Roedel | af65993 | 2015-10-21 23:51:41 +0200 | [diff] [blame] | 2456 | struct arm_smmu_master *master; |
Will Deacon | 03edb22 | 2015-01-19 14:27:33 +0000 | [diff] [blame] | 2457 | |
| 2458 | if (!smmu) |
| 2459 | return -ENODEV; |
| 2460 | |
| 2461 | master = find_smmu_master(smmu, dev->of_node); |
| 2462 | if (!master) |
| 2463 | return -ENODEV; |
| 2464 | |
Will Deacon | 03edb22 | 2015-01-19 14:27:33 +0000 | [diff] [blame] | 2465 | iommu_group_set_iommudata(group, &master->cfg, NULL); |
Joerg Roedel | af65993 | 2015-10-21 23:51:41 +0200 | [diff] [blame] | 2466 | |
| 2467 | return 0; |
Will Deacon | 03edb22 | 2015-01-19 14:27:33 +0000 | [diff] [blame] | 2468 | } |
| 2469 | |
| 2470 | static int arm_smmu_add_device(struct device *dev) |
| 2471 | { |
Joerg Roedel | af65993 | 2015-10-21 23:51:41 +0200 | [diff] [blame] | 2472 | struct iommu_group *group; |
Will Deacon | 03edb22 | 2015-01-19 14:27:33 +0000 | [diff] [blame] | 2473 | |
Joerg Roedel | af65993 | 2015-10-21 23:51:41 +0200 | [diff] [blame] | 2474 | group = iommu_group_get_for_dev(dev); |
| 2475 | if (IS_ERR(group)) |
| 2476 | return PTR_ERR(group); |
| 2477 | |
Peng Fan | 9a4a9d8 | 2015-11-20 16:56:18 +0800 | [diff] [blame] | 2478 | iommu_group_put(group); |
Joerg Roedel | af65993 | 2015-10-21 23:51:41 +0200 | [diff] [blame] | 2479 | return 0; |
Will Deacon | 03edb22 | 2015-01-19 14:27:33 +0000 | [diff] [blame] | 2480 | } |
| 2481 | |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 2482 | static void arm_smmu_remove_device(struct device *dev) |
| 2483 | { |
Antonios Motakis | 5fc63a7 | 2013-10-18 16:08:29 +0100 | [diff] [blame] | 2484 | iommu_group_remove_device(dev); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 2485 | } |
| 2486 | |
Joerg Roedel | af65993 | 2015-10-21 23:51:41 +0200 | [diff] [blame] | 2487 | static struct iommu_group *arm_smmu_device_group(struct device *dev) |
| 2488 | { |
| 2489 | struct iommu_group *group; |
| 2490 | int ret; |
| 2491 | |
| 2492 | if (dev_is_pci(dev)) |
| 2493 | group = pci_device_group(dev); |
| 2494 | else |
| 2495 | group = generic_device_group(dev); |
| 2496 | |
| 2497 | if (IS_ERR(group)) |
| 2498 | return group; |
| 2499 | |
| 2500 | if (dev_is_pci(dev)) |
| 2501 | ret = arm_smmu_init_pci_device(to_pci_dev(dev), group); |
| 2502 | else |
| 2503 | ret = arm_smmu_init_platform_device(dev, group); |
| 2504 | |
| 2505 | if (ret) { |
| 2506 | iommu_group_put(group); |
| 2507 | group = ERR_PTR(ret); |
| 2508 | } |
| 2509 | |
| 2510 | return group; |
| 2511 | } |
| 2512 | |
Will Deacon | c752ce4 | 2014-06-25 22:46:31 +0100 | [diff] [blame] | 2513 | static int arm_smmu_domain_get_attr(struct iommu_domain *domain, |
| 2514 | enum iommu_attr attr, void *data) |
| 2515 | { |
Joerg Roedel | 1d67263 | 2015-03-26 13:43:10 +0100 | [diff] [blame] | 2516 | struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); |
Jeremy Gebben | 7e47f9b | 2015-06-16 10:59:29 -0600 | [diff] [blame] | 2517 | int ret = 0; |
Will Deacon | c752ce4 | 2014-06-25 22:46:31 +0100 | [diff] [blame] | 2518 | |
| 2519 | switch (attr) { |
| 2520 | case DOMAIN_ATTR_NESTING: |
| 2521 | *(int *)data = (smmu_domain->stage == ARM_SMMU_DOMAIN_NESTED); |
| 2522 | return 0; |
Mitchel Humpherys | cd9f07a | 2014-11-12 15:11:33 -0800 | [diff] [blame] | 2523 | case DOMAIN_ATTR_PT_BASE_ADDR: |
| 2524 | *((phys_addr_t *)data) = |
| 2525 | smmu_domain->pgtbl_cfg.arm_lpae_s1_cfg.ttbr[0]; |
| 2526 | return 0; |
Jeremy Gebben | 7e47f9b | 2015-06-16 10:59:29 -0600 | [diff] [blame] | 2527 | case DOMAIN_ATTR_CONTEXT_BANK: |
| 2528 | /* context bank index isn't valid until we are attached */ |
| 2529 | if (smmu_domain->smmu == NULL) |
| 2530 | return -ENODEV; |
| 2531 | |
| 2532 | *((unsigned int *) data) = smmu_domain->cfg.cbndx; |
| 2533 | ret = 0; |
| 2534 | break; |
Jeremy Gebben | 8ac927c | 2015-07-10 16:43:22 -0600 | [diff] [blame] | 2535 | case DOMAIN_ATTR_TTBR0: { |
| 2536 | u64 val; |
| 2537 | struct arm_smmu_device *smmu = smmu_domain->smmu; |
| 2538 | /* not valid until we are attached */ |
| 2539 | if (smmu == NULL) |
| 2540 | return -ENODEV; |
| 2541 | |
| 2542 | val = smmu_domain->pgtbl_cfg.arm_lpae_s1_cfg.ttbr[0]; |
| 2543 | if (smmu_domain->cfg.cbar != CBAR_TYPE_S2_TRANS) |
| 2544 | val |= (u64)ARM_SMMU_CB_ASID(smmu, &smmu_domain->cfg) |
| 2545 | << (TTBRn_ASID_SHIFT); |
| 2546 | *((u64 *)data) = val; |
| 2547 | ret = 0; |
| 2548 | break; |
| 2549 | } |
| 2550 | case DOMAIN_ATTR_CONTEXTIDR: |
| 2551 | /* not valid until attached */ |
| 2552 | if (smmu_domain->smmu == NULL) |
| 2553 | return -ENODEV; |
| 2554 | *((u32 *)data) = smmu_domain->cfg.procid; |
| 2555 | ret = 0; |
| 2556 | break; |
| 2557 | case DOMAIN_ATTR_PROCID: |
| 2558 | *((u32 *)data) = smmu_domain->cfg.procid; |
| 2559 | ret = 0; |
| 2560 | break; |
Patrick Daly | c190d93 | 2016-08-30 17:23:28 -0700 | [diff] [blame] | 2561 | case DOMAIN_ATTR_DYNAMIC: |
| 2562 | *((int *)data) = !!(smmu_domain->attributes |
| 2563 | & (1 << DOMAIN_ATTR_DYNAMIC)); |
| 2564 | ret = 0; |
| 2565 | break; |
Mitchel Humpherys | cc8d12f | 2015-09-25 17:29:27 -0700 | [diff] [blame] | 2566 | case DOMAIN_ATTR_NON_FATAL_FAULTS: |
| 2567 | *((int *)data) = !!(smmu_domain->attributes |
| 2568 | & (1 << DOMAIN_ATTR_NON_FATAL_FAULTS)); |
| 2569 | ret = 0; |
| 2570 | break; |
Patrick Daly | e62d336 | 2016-03-15 18:58:28 -0700 | [diff] [blame] | 2571 | case DOMAIN_ATTR_S1_BYPASS: |
| 2572 | *((int *)data) = !!(smmu_domain->attributes |
| 2573 | & (1 << DOMAIN_ATTR_S1_BYPASS)); |
| 2574 | ret = 0; |
| 2575 | break; |
Patrick Daly | c11d108 | 2016-09-01 15:52:44 -0700 | [diff] [blame] | 2576 | case DOMAIN_ATTR_SECURE_VMID: |
| 2577 | *((int *)data) = smmu_domain->secure_vmid; |
| 2578 | ret = 0; |
| 2579 | break; |
Mitchel Humpherys | b9dda59 | 2016-02-12 14:18:02 -0800 | [diff] [blame] | 2580 | case DOMAIN_ATTR_PGTBL_INFO: { |
| 2581 | struct iommu_pgtbl_info *info = data; |
| 2582 | |
| 2583 | if (!(smmu_domain->attributes & (1 << DOMAIN_ATTR_FAST))) { |
| 2584 | ret = -ENODEV; |
| 2585 | break; |
| 2586 | } |
| 2587 | info->pmds = smmu_domain->pgtbl_cfg.av8l_fast_cfg.pmds; |
| 2588 | ret = 0; |
| 2589 | break; |
| 2590 | } |
Mitchel Humpherys | c625ce0 | 2015-10-07 14:03:50 -0700 | [diff] [blame] | 2591 | case DOMAIN_ATTR_FAST: |
| 2592 | *((int *)data) = !!(smmu_domain->attributes |
| 2593 | & (1 << DOMAIN_ATTR_FAST)); |
| 2594 | ret = 0; |
| 2595 | break; |
Will Deacon | c752ce4 | 2014-06-25 22:46:31 +0100 | [diff] [blame] | 2596 | default: |
| 2597 | return -ENODEV; |
| 2598 | } |
Jeremy Gebben | 7e47f9b | 2015-06-16 10:59:29 -0600 | [diff] [blame] | 2599 | return ret; |
Will Deacon | c752ce4 | 2014-06-25 22:46:31 +0100 | [diff] [blame] | 2600 | } |
| 2601 | |
| 2602 | static int arm_smmu_domain_set_attr(struct iommu_domain *domain, |
| 2603 | enum iommu_attr attr, void *data) |
| 2604 | { |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame] | 2605 | int ret = 0; |
Joerg Roedel | 1d67263 | 2015-03-26 13:43:10 +0100 | [diff] [blame] | 2606 | struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); |
Will Deacon | c752ce4 | 2014-06-25 22:46:31 +0100 | [diff] [blame] | 2607 | |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame] | 2608 | mutex_lock(&smmu_domain->init_mutex); |
| 2609 | |
Will Deacon | c752ce4 | 2014-06-25 22:46:31 +0100 | [diff] [blame] | 2610 | switch (attr) { |
| 2611 | case DOMAIN_ATTR_NESTING: |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame] | 2612 | if (smmu_domain->smmu) { |
| 2613 | ret = -EPERM; |
| 2614 | goto out_unlock; |
| 2615 | } |
| 2616 | |
Will Deacon | c752ce4 | 2014-06-25 22:46:31 +0100 | [diff] [blame] | 2617 | if (*(int *)data) |
| 2618 | smmu_domain->stage = ARM_SMMU_DOMAIN_NESTED; |
| 2619 | else |
| 2620 | smmu_domain->stage = ARM_SMMU_DOMAIN_S1; |
| 2621 | |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame] | 2622 | break; |
Jeremy Gebben | 8ac927c | 2015-07-10 16:43:22 -0600 | [diff] [blame] | 2623 | case DOMAIN_ATTR_PROCID: |
| 2624 | if (smmu_domain->smmu != NULL) { |
| 2625 | dev_err(smmu_domain->smmu->dev, |
| 2626 | "cannot change procid attribute while attached\n"); |
| 2627 | ret = -EBUSY; |
| 2628 | break; |
| 2629 | } |
| 2630 | smmu_domain->cfg.procid = *((u32 *)data); |
| 2631 | ret = 0; |
| 2632 | break; |
Patrick Daly | c190d93 | 2016-08-30 17:23:28 -0700 | [diff] [blame] | 2633 | case DOMAIN_ATTR_DYNAMIC: { |
| 2634 | int dynamic = *((int *)data); |
| 2635 | |
| 2636 | if (smmu_domain->smmu != NULL) { |
| 2637 | dev_err(smmu_domain->smmu->dev, |
| 2638 | "cannot change dynamic attribute while attached\n"); |
| 2639 | ret = -EBUSY; |
| 2640 | break; |
| 2641 | } |
| 2642 | |
| 2643 | if (dynamic) |
| 2644 | smmu_domain->attributes |= 1 << DOMAIN_ATTR_DYNAMIC; |
| 2645 | else |
| 2646 | smmu_domain->attributes &= ~(1 << DOMAIN_ATTR_DYNAMIC); |
| 2647 | ret = 0; |
| 2648 | break; |
| 2649 | } |
| 2650 | case DOMAIN_ATTR_CONTEXT_BANK: |
| 2651 | /* context bank can't be set while attached */ |
| 2652 | if (smmu_domain->smmu != NULL) { |
| 2653 | ret = -EBUSY; |
| 2654 | break; |
| 2655 | } |
| 2656 | /* ... and it can only be set for dynamic contexts. */ |
| 2657 | if (!(smmu_domain->attributes & (1 << DOMAIN_ATTR_DYNAMIC))) { |
| 2658 | ret = -EINVAL; |
| 2659 | break; |
| 2660 | } |
| 2661 | |
| 2662 | /* this will be validated during attach */ |
| 2663 | smmu_domain->cfg.cbndx = *((unsigned int *)data); |
| 2664 | ret = 0; |
| 2665 | break; |
Mitchel Humpherys | cc8d12f | 2015-09-25 17:29:27 -0700 | [diff] [blame] | 2666 | case DOMAIN_ATTR_NON_FATAL_FAULTS: { |
| 2667 | u32 non_fatal_faults = *((int *)data); |
| 2668 | |
| 2669 | if (non_fatal_faults) |
| 2670 | smmu_domain->attributes |= |
| 2671 | 1 << DOMAIN_ATTR_NON_FATAL_FAULTS; |
| 2672 | else |
| 2673 | smmu_domain->attributes &= |
| 2674 | ~(1 << DOMAIN_ATTR_NON_FATAL_FAULTS); |
| 2675 | ret = 0; |
| 2676 | break; |
| 2677 | } |
Patrick Daly | e62d336 | 2016-03-15 18:58:28 -0700 | [diff] [blame] | 2678 | case DOMAIN_ATTR_S1_BYPASS: { |
| 2679 | int bypass = *((int *)data); |
| 2680 | |
| 2681 | /* bypass can't be changed while attached */ |
| 2682 | if (smmu_domain->smmu != NULL) { |
| 2683 | ret = -EBUSY; |
| 2684 | break; |
| 2685 | } |
| 2686 | if (bypass) |
| 2687 | smmu_domain->attributes |= 1 << DOMAIN_ATTR_S1_BYPASS; |
| 2688 | else |
| 2689 | smmu_domain->attributes &= |
| 2690 | ~(1 << DOMAIN_ATTR_S1_BYPASS); |
| 2691 | |
| 2692 | ret = 0; |
| 2693 | break; |
| 2694 | } |
Patrick Daly | 8befb66 | 2016-08-17 20:03:28 -0700 | [diff] [blame] | 2695 | case DOMAIN_ATTR_ATOMIC: |
| 2696 | { |
| 2697 | int atomic_ctx = *((int *)data); |
| 2698 | |
| 2699 | /* can't be changed while attached */ |
| 2700 | if (smmu_domain->smmu != NULL) { |
| 2701 | ret = -EBUSY; |
| 2702 | break; |
| 2703 | } |
| 2704 | if (atomic_ctx) |
| 2705 | smmu_domain->attributes |= (1 << DOMAIN_ATTR_ATOMIC); |
| 2706 | else |
| 2707 | smmu_domain->attributes &= ~(1 << DOMAIN_ATTR_ATOMIC); |
| 2708 | break; |
| 2709 | } |
Patrick Daly | c11d108 | 2016-09-01 15:52:44 -0700 | [diff] [blame] | 2710 | case DOMAIN_ATTR_SECURE_VMID: |
| 2711 | if (smmu_domain->secure_vmid != VMID_INVAL) { |
| 2712 | ret = -ENODEV; |
| 2713 | WARN(1, "secure vmid already set!"); |
| 2714 | break; |
| 2715 | } |
| 2716 | smmu_domain->secure_vmid = *((int *)data); |
| 2717 | break; |
Mitchel Humpherys | c625ce0 | 2015-10-07 14:03:50 -0700 | [diff] [blame] | 2718 | case DOMAIN_ATTR_FAST: |
| 2719 | if (*((int *)data)) |
| 2720 | smmu_domain->attributes |= 1 << DOMAIN_ATTR_FAST; |
| 2721 | ret = 0; |
| 2722 | break; |
Will Deacon | c752ce4 | 2014-06-25 22:46:31 +0100 | [diff] [blame] | 2723 | default: |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame] | 2724 | ret = -ENODEV; |
Will Deacon | c752ce4 | 2014-06-25 22:46:31 +0100 | [diff] [blame] | 2725 | } |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame] | 2726 | |
| 2727 | out_unlock: |
| 2728 | mutex_unlock(&smmu_domain->init_mutex); |
| 2729 | return ret; |
Will Deacon | c752ce4 | 2014-06-25 22:46:31 +0100 | [diff] [blame] | 2730 | } |
| 2731 | |
Mitchel Humpherys | a52d6cc | 2015-07-09 17:26:15 -0700 | [diff] [blame] | 2732 | static void arm_smmu_trigger_fault(struct iommu_domain *domain, |
| 2733 | unsigned long flags) |
| 2734 | { |
| 2735 | struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); |
| 2736 | struct arm_smmu_cfg *cfg = &smmu_domain->cfg; |
| 2737 | struct arm_smmu_device *smmu; |
| 2738 | void __iomem *cb_base; |
| 2739 | |
| 2740 | if (!smmu_domain->smmu) { |
| 2741 | pr_err("Can't trigger faults on non-attached domains\n"); |
| 2742 | return; |
| 2743 | } |
| 2744 | |
| 2745 | smmu = smmu_domain->smmu; |
Mitchel Humpherys | 3e52a7e | 2015-10-19 17:13:47 -0700 | [diff] [blame] | 2746 | if (arm_smmu_power_on(smmu)) |
| 2747 | return; |
Mitchel Humpherys | a52d6cc | 2015-07-09 17:26:15 -0700 | [diff] [blame] | 2748 | |
| 2749 | cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx); |
| 2750 | dev_err(smmu->dev, "Writing 0x%lx to FSRRESTORE on cb %d\n", |
| 2751 | flags, cfg->cbndx); |
| 2752 | writel_relaxed(flags, cb_base + ARM_SMMU_CB_FSRRESTORE); |
Mitchel Humpherys | 017ee4b | 2015-10-21 13:59:50 -0700 | [diff] [blame] | 2753 | /* give the interrupt time to fire... */ |
| 2754 | msleep(1000); |
Patrick Daly | 3a8a88a | 2016-07-22 12:24:05 -0700 | [diff] [blame] | 2755 | |
| 2756 | arm_smmu_power_off(smmu); |
Mitchel Humpherys | a52d6cc | 2015-07-09 17:26:15 -0700 | [diff] [blame] | 2757 | } |
| 2758 | |
Mitchel Humpherys | fd55700 | 2015-08-21 14:07:59 -0700 | [diff] [blame] | 2759 | static unsigned long arm_smmu_reg_read(struct iommu_domain *domain, |
| 2760 | unsigned long offset) |
| 2761 | { |
| 2762 | struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); |
| 2763 | struct arm_smmu_device *smmu; |
| 2764 | struct arm_smmu_cfg *cfg = &smmu_domain->cfg; |
| 2765 | void __iomem *cb_base; |
| 2766 | unsigned long val; |
| 2767 | |
| 2768 | if (offset >= SZ_4K) { |
| 2769 | pr_err("Invalid offset: 0x%lx\n", offset); |
| 2770 | return 0; |
| 2771 | } |
| 2772 | |
| 2773 | smmu = smmu_domain->smmu; |
| 2774 | if (!smmu) { |
| 2775 | WARN(1, "Can't read registers of a detached domain\n"); |
| 2776 | val = 0; |
| 2777 | return val; |
| 2778 | } |
| 2779 | |
Mitchel Humpherys | 3e52a7e | 2015-10-19 17:13:47 -0700 | [diff] [blame] | 2780 | if (arm_smmu_power_on(smmu)) |
| 2781 | return 0; |
Patrick Daly | 3a8a88a | 2016-07-22 12:24:05 -0700 | [diff] [blame] | 2782 | |
Mitchel Humpherys | fd55700 | 2015-08-21 14:07:59 -0700 | [diff] [blame] | 2783 | cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx); |
| 2784 | val = readl_relaxed(cb_base + offset); |
| 2785 | |
Patrick Daly | 3a8a88a | 2016-07-22 12:24:05 -0700 | [diff] [blame] | 2786 | arm_smmu_power_off(smmu); |
Mitchel Humpherys | fd55700 | 2015-08-21 14:07:59 -0700 | [diff] [blame] | 2787 | return val; |
| 2788 | } |
| 2789 | |
| 2790 | static void arm_smmu_reg_write(struct iommu_domain *domain, |
| 2791 | unsigned long offset, unsigned long val) |
| 2792 | { |
| 2793 | struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); |
| 2794 | struct arm_smmu_device *smmu; |
| 2795 | struct arm_smmu_cfg *cfg = &smmu_domain->cfg; |
| 2796 | void __iomem *cb_base; |
| 2797 | |
| 2798 | if (offset >= SZ_4K) { |
| 2799 | pr_err("Invalid offset: 0x%lx\n", offset); |
| 2800 | return; |
| 2801 | } |
| 2802 | |
| 2803 | smmu = smmu_domain->smmu; |
| 2804 | if (!smmu) { |
| 2805 | WARN(1, "Can't read registers of a detached domain\n"); |
| 2806 | return; |
| 2807 | } |
| 2808 | |
Mitchel Humpherys | 3e52a7e | 2015-10-19 17:13:47 -0700 | [diff] [blame] | 2809 | if (arm_smmu_power_on(smmu)) |
| 2810 | return; |
Patrick Daly | 3a8a88a | 2016-07-22 12:24:05 -0700 | [diff] [blame] | 2811 | |
Mitchel Humpherys | fd55700 | 2015-08-21 14:07:59 -0700 | [diff] [blame] | 2812 | cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx); |
| 2813 | writel_relaxed(val, cb_base + offset); |
Patrick Daly | 3a8a88a | 2016-07-22 12:24:05 -0700 | [diff] [blame] | 2814 | |
| 2815 | arm_smmu_power_off(smmu); |
Mitchel Humpherys | fd55700 | 2015-08-21 14:07:59 -0700 | [diff] [blame] | 2816 | } |
| 2817 | |
Mitchel Humpherys | 2dcc234 | 2015-12-03 11:20:03 -0800 | [diff] [blame] | 2818 | static void arm_smmu_tlbi_domain(struct iommu_domain *domain) |
| 2819 | { |
| 2820 | arm_smmu_tlb_inv_context(to_smmu_domain(domain)); |
| 2821 | } |
| 2822 | |
Mitchel Humpherys | 74299ca | 2015-12-14 16:12:00 -0800 | [diff] [blame] | 2823 | static int arm_smmu_enable_config_clocks(struct iommu_domain *domain) |
| 2824 | { |
| 2825 | struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); |
| 2826 | |
| 2827 | return arm_smmu_power_on(smmu_domain->smmu); |
| 2828 | } |
| 2829 | |
| 2830 | static void arm_smmu_disable_config_clocks(struct iommu_domain *domain) |
| 2831 | { |
| 2832 | struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); |
| 2833 | |
| 2834 | arm_smmu_power_off(smmu_domain->smmu); |
| 2835 | } |
| 2836 | |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame] | 2837 | static struct iommu_ops arm_smmu_ops = { |
Will Deacon | c752ce4 | 2014-06-25 22:46:31 +0100 | [diff] [blame] | 2838 | .capable = arm_smmu_capable, |
Joerg Roedel | 1d67263 | 2015-03-26 13:43:10 +0100 | [diff] [blame] | 2839 | .domain_alloc = arm_smmu_domain_alloc, |
| 2840 | .domain_free = arm_smmu_domain_free, |
Will Deacon | c752ce4 | 2014-06-25 22:46:31 +0100 | [diff] [blame] | 2841 | .attach_dev = arm_smmu_attach_dev, |
Patrick Daly | 0980131 | 2016-08-29 17:02:52 -0700 | [diff] [blame] | 2842 | .detach_dev = arm_smmu_detach_dev, |
Will Deacon | c752ce4 | 2014-06-25 22:46:31 +0100 | [diff] [blame] | 2843 | .map = arm_smmu_map, |
| 2844 | .unmap = arm_smmu_unmap, |
Mitchel Humpherys | 622bc04 | 2015-04-23 16:29:23 -0700 | [diff] [blame] | 2845 | .map_sg = arm_smmu_map_sg, |
Will Deacon | c752ce4 | 2014-06-25 22:46:31 +0100 | [diff] [blame] | 2846 | .iova_to_phys = arm_smmu_iova_to_phys, |
Mitchel Humpherys | fb11f70 | 2015-07-06 13:53:51 -0700 | [diff] [blame] | 2847 | .iova_to_phys_hard = arm_smmu_iova_to_phys_hard, |
Will Deacon | c752ce4 | 2014-06-25 22:46:31 +0100 | [diff] [blame] | 2848 | .add_device = arm_smmu_add_device, |
| 2849 | .remove_device = arm_smmu_remove_device, |
Joerg Roedel | af65993 | 2015-10-21 23:51:41 +0200 | [diff] [blame] | 2850 | .device_group = arm_smmu_device_group, |
Will Deacon | c752ce4 | 2014-06-25 22:46:31 +0100 | [diff] [blame] | 2851 | .domain_get_attr = arm_smmu_domain_get_attr, |
| 2852 | .domain_set_attr = arm_smmu_domain_set_attr, |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame] | 2853 | .pgsize_bitmap = -1UL, /* Restricted during device attach */ |
Mitchel Humpherys | a52d6cc | 2015-07-09 17:26:15 -0700 | [diff] [blame] | 2854 | .trigger_fault = arm_smmu_trigger_fault, |
Mitchel Humpherys | fd55700 | 2015-08-21 14:07:59 -0700 | [diff] [blame] | 2855 | .reg_read = arm_smmu_reg_read, |
| 2856 | .reg_write = arm_smmu_reg_write, |
Mitchel Humpherys | 2dcc234 | 2015-12-03 11:20:03 -0800 | [diff] [blame] | 2857 | .tlbi_domain = arm_smmu_tlbi_domain, |
Mitchel Humpherys | 74299ca | 2015-12-14 16:12:00 -0800 | [diff] [blame] | 2858 | .enable_config_clocks = arm_smmu_enable_config_clocks, |
| 2859 | .disable_config_clocks = arm_smmu_disable_config_clocks, |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 2860 | }; |
| 2861 | |
Patrick Daly | d54eafd | 2016-08-23 17:01:43 -0700 | [diff] [blame] | 2862 | static int arm_smmu_wait_for_halt(struct arm_smmu_device *smmu) |
Mitchel Humpherys | 952f40a | 2015-08-19 12:13:28 -0700 | [diff] [blame] | 2863 | { |
| 2864 | void __iomem *impl_def1_base = ARM_SMMU_IMPL_DEF1(smmu); |
Patrick Daly | d54eafd | 2016-08-23 17:01:43 -0700 | [diff] [blame] | 2865 | u32 tmp; |
Mitchel Humpherys | 952f40a | 2015-08-19 12:13:28 -0700 | [diff] [blame] | 2866 | |
| 2867 | if (readl_poll_timeout_atomic(impl_def1_base + IMPL_DEF1_MICRO_MMU_CTRL, |
| 2868 | tmp, (tmp & MICRO_MMU_CTRL_IDLE), |
| 2869 | 0, 30000)) { |
| 2870 | dev_err(smmu->dev, "Couldn't halt SMMU!\n"); |
| 2871 | return -EBUSY; |
| 2872 | } |
| 2873 | |
| 2874 | return 0; |
| 2875 | } |
| 2876 | |
Patrick Daly | d54eafd | 2016-08-23 17:01:43 -0700 | [diff] [blame] | 2877 | static int __arm_smmu_halt(struct arm_smmu_device *smmu, bool wait) |
| 2878 | { |
| 2879 | void __iomem *impl_def1_base = ARM_SMMU_IMPL_DEF1(smmu); |
| 2880 | u32 reg; |
| 2881 | |
| 2882 | reg = readl_relaxed(impl_def1_base + IMPL_DEF1_MICRO_MMU_CTRL); |
| 2883 | reg |= MICRO_MMU_CTRL_LOCAL_HALT_REQ; |
| 2884 | writel_relaxed(reg, impl_def1_base + IMPL_DEF1_MICRO_MMU_CTRL); |
| 2885 | |
| 2886 | return wait ? arm_smmu_wait_for_halt(smmu) : 0; |
| 2887 | } |
| 2888 | |
| 2889 | static int arm_smmu_halt(struct arm_smmu_device *smmu) |
| 2890 | { |
| 2891 | return __arm_smmu_halt(smmu, true); |
| 2892 | } |
| 2893 | |
| 2894 | static int arm_smmu_halt_nowait(struct arm_smmu_device *smmu) |
| 2895 | { |
| 2896 | return __arm_smmu_halt(smmu, false); |
| 2897 | } |
| 2898 | |
Mitchel Humpherys | 952f40a | 2015-08-19 12:13:28 -0700 | [diff] [blame] | 2899 | static void arm_smmu_resume(struct arm_smmu_device *smmu) |
| 2900 | { |
| 2901 | void __iomem *impl_def1_base = ARM_SMMU_IMPL_DEF1(smmu); |
| 2902 | u32 reg; |
| 2903 | |
| 2904 | reg = readl_relaxed(impl_def1_base + IMPL_DEF1_MICRO_MMU_CTRL); |
| 2905 | reg &= ~MICRO_MMU_CTRL_LOCAL_HALT_REQ; |
| 2906 | writel_relaxed(reg, impl_def1_base + IMPL_DEF1_MICRO_MMU_CTRL); |
| 2907 | } |
| 2908 | |
Mitchel Humpherys | 5494a5e | 2014-08-14 17:44:49 -0700 | [diff] [blame] | 2909 | static void arm_smmu_impl_def_programming(struct arm_smmu_device *smmu) |
| 2910 | { |
| 2911 | int i; |
| 2912 | struct arm_smmu_impl_def_reg *regs = smmu->impl_def_attach_registers; |
| 2913 | |
Mitchel Humpherys | 952f40a | 2015-08-19 12:13:28 -0700 | [diff] [blame] | 2914 | arm_smmu_halt(smmu); |
Mitchel Humpherys | 5494a5e | 2014-08-14 17:44:49 -0700 | [diff] [blame] | 2915 | for (i = 0; i < smmu->num_impl_def_attach_registers; ++i) |
| 2916 | writel_relaxed(regs[i].value, |
| 2917 | ARM_SMMU_GR0(smmu) + regs[i].offset); |
Mitchel Humpherys | 952f40a | 2015-08-19 12:13:28 -0700 | [diff] [blame] | 2918 | arm_smmu_resume(smmu); |
Mitchel Humpherys | 5494a5e | 2014-08-14 17:44:49 -0700 | [diff] [blame] | 2919 | } |
| 2920 | |
Mitchel Humpherys | 9c2f648 | 2015-01-13 15:28:40 -0800 | [diff] [blame] | 2921 | static void arm_smmu_context_bank_reset(struct arm_smmu_device *smmu) |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 2922 | { |
Mitchel Humpherys | 9c2f648 | 2015-01-13 15:28:40 -0800 | [diff] [blame] | 2923 | int i; |
| 2924 | u32 reg, major; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 2925 | void __iomem *gr0_base = ARM_SMMU_GR0(smmu); |
Andreas Herrmann | 659db6f | 2013-10-01 13:39:09 +0100 | [diff] [blame] | 2926 | void __iomem *cb_base; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 2927 | |
Peng Fan | 3ca3712 | 2016-05-03 21:50:30 +0800 | [diff] [blame] | 2928 | /* |
| 2929 | * Before clearing ARM_MMU500_ACTLR_CPRE, need to |
| 2930 | * clear CACHE_LOCK bit of ACR first. And, CACHE_LOCK |
| 2931 | * bit is only present in MMU-500r2 onwards. |
| 2932 | */ |
| 2933 | reg = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID7); |
| 2934 | major = (reg >> ID7_MAJOR_SHIFT) & ID7_MAJOR_MASK; |
| 2935 | if ((smmu->model == ARM_MMU500) && (major >= 2)) { |
| 2936 | reg = readl_relaxed(gr0_base + ARM_SMMU_GR0_sACR); |
| 2937 | reg &= ~ARM_MMU500_ACR_CACHE_LOCK; |
| 2938 | writel_relaxed(reg, gr0_base + ARM_SMMU_GR0_sACR); |
| 2939 | } |
| 2940 | |
Andreas Herrmann | 659db6f | 2013-10-01 13:39:09 +0100 | [diff] [blame] | 2941 | /* Make sure all context banks are disabled and clear CB_FSR */ |
| 2942 | for (i = 0; i < smmu->num_context_banks; ++i) { |
| 2943 | cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, i); |
| 2944 | writel_relaxed(0, cb_base + ARM_SMMU_CB_SCTLR); |
| 2945 | writel_relaxed(FSR_FAULT, cb_base + ARM_SMMU_CB_FSR); |
Robin Murphy | f0cfffc | 2016-04-13 18:12:59 +0100 | [diff] [blame] | 2946 | /* |
| 2947 | * Disable MMU-500's not-particularly-beneficial next-page |
| 2948 | * prefetcher for the sake of errata #841119 and #826419. |
| 2949 | */ |
| 2950 | if (smmu->model == ARM_MMU500) { |
| 2951 | reg = readl_relaxed(cb_base + ARM_SMMU_CB_ACTLR); |
| 2952 | reg &= ~ARM_MMU500_ACTLR_CPRE; |
| 2953 | writel_relaxed(reg, cb_base + ARM_SMMU_CB_ACTLR); |
| 2954 | } |
Patrick Daly | f0d4e21 | 2016-06-20 15:50:14 -0700 | [diff] [blame] | 2955 | |
| 2956 | if (smmu->model == QCOM_SMMUV2) { |
| 2957 | reg = ACTLR_QCOM_ISH << ACTLR_QCOM_ISH_SHIFT | |
| 2958 | ACTLR_QCOM_OSH << ACTLR_QCOM_OSH_SHIFT | |
| 2959 | ACTLR_QCOM_NSH << ACTLR_QCOM_NSH_SHIFT; |
| 2960 | writel_relaxed(reg, cb_base + ARM_SMMU_CB_ACTLR); |
| 2961 | } |
Andreas Herrmann | 659db6f | 2013-10-01 13:39:09 +0100 | [diff] [blame] | 2962 | } |
Mitchel Humpherys | 9c2f648 | 2015-01-13 15:28:40 -0800 | [diff] [blame] | 2963 | } |
| 2964 | |
| 2965 | static void arm_smmu_device_reset(struct arm_smmu_device *smmu) |
| 2966 | { |
| 2967 | void __iomem *gr0_base = ARM_SMMU_GR0(smmu); |
| 2968 | int i = 0; |
| 2969 | u32 reg; |
| 2970 | |
| 2971 | /* clear global FSR */ |
| 2972 | reg = readl_relaxed(ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sGFSR); |
| 2973 | writel_relaxed(reg, ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sGFSR); |
| 2974 | |
| 2975 | if (!(smmu->options & ARM_SMMU_OPT_SKIP_INIT)) { |
| 2976 | /* |
| 2977 | * Mark all SMRn as invalid and all S2CRn as bypass unless |
| 2978 | * overridden |
| 2979 | */ |
| 2980 | reg = disable_bypass ? S2CR_TYPE_FAULT : S2CR_TYPE_BYPASS; |
| 2981 | for (i = 0; i < smmu->num_mapping_groups; ++i) { |
| 2982 | writel_relaxed(0, gr0_base + ARM_SMMU_GR0_SMR(i)); |
| 2983 | writel_relaxed(reg, gr0_base + ARM_SMMU_GR0_S2CR(i)); |
| 2984 | } |
| 2985 | |
| 2986 | arm_smmu_context_bank_reset(smmu); |
| 2987 | } |
Will Deacon | 1463fe4 | 2013-07-31 19:21:27 +0100 | [diff] [blame] | 2988 | |
Mitchel Humpherys | 5494a5e | 2014-08-14 17:44:49 -0700 | [diff] [blame] | 2989 | /* Program implementation defined registers */ |
| 2990 | arm_smmu_impl_def_programming(smmu); |
| 2991 | |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 2992 | /* Invalidate the TLB, just in case */ |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 2993 | writel_relaxed(0, gr0_base + ARM_SMMU_GR0_TLBIALLH); |
| 2994 | writel_relaxed(0, gr0_base + ARM_SMMU_GR0_TLBIALLNSNH); |
| 2995 | |
Andreas Herrmann | 3a5df8f | 2014-01-30 18:18:04 +0000 | [diff] [blame] | 2996 | reg = readl_relaxed(ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sCR0); |
Andreas Herrmann | 659db6f | 2013-10-01 13:39:09 +0100 | [diff] [blame] | 2997 | |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 2998 | /* Enable fault reporting */ |
Andreas Herrmann | 659db6f | 2013-10-01 13:39:09 +0100 | [diff] [blame] | 2999 | reg |= (sCR0_GFRE | sCR0_GFIE | sCR0_GCFGFRE | sCR0_GCFGFIE); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 3000 | |
| 3001 | /* Disable TLB broadcasting. */ |
Andreas Herrmann | 659db6f | 2013-10-01 13:39:09 +0100 | [diff] [blame] | 3002 | reg |= (sCR0_VMIDPNE | sCR0_PTM); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 3003 | |
Robin Murphy | 25a1c96 | 2016-02-10 14:25:33 +0000 | [diff] [blame] | 3004 | /* Enable client access, handling unmatched streams as appropriate */ |
| 3005 | reg &= ~sCR0_CLIENTPD; |
| 3006 | if (disable_bypass) |
| 3007 | reg |= sCR0_USFCFG; |
| 3008 | else |
| 3009 | reg &= ~sCR0_USFCFG; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 3010 | |
| 3011 | /* Disable forced broadcasting */ |
Andreas Herrmann | 659db6f | 2013-10-01 13:39:09 +0100 | [diff] [blame] | 3012 | reg &= ~sCR0_FB; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 3013 | |
| 3014 | /* Don't upgrade barriers */ |
Andreas Herrmann | 659db6f | 2013-10-01 13:39:09 +0100 | [diff] [blame] | 3015 | reg &= ~(sCR0_BSU_MASK << sCR0_BSU_SHIFT); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 3016 | |
Tirumalesh Chalamarla | 4e3e9b6 | 2016-02-23 10:19:00 -0800 | [diff] [blame] | 3017 | if (smmu->features & ARM_SMMU_FEAT_VMID16) |
| 3018 | reg |= sCR0_VMID16EN; |
| 3019 | |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 3020 | /* Push the button */ |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame] | 3021 | __arm_smmu_tlb_sync(smmu); |
Andreas Herrmann | 3a5df8f | 2014-01-30 18:18:04 +0000 | [diff] [blame] | 3022 | writel(reg, ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sCR0); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 3023 | } |
| 3024 | |
| 3025 | static int arm_smmu_id_size_to_bits(int size) |
| 3026 | { |
| 3027 | switch (size) { |
| 3028 | case 0: |
| 3029 | return 32; |
| 3030 | case 1: |
| 3031 | return 36; |
| 3032 | case 2: |
| 3033 | return 40; |
| 3034 | case 3: |
| 3035 | return 42; |
| 3036 | case 4: |
| 3037 | return 44; |
| 3038 | case 5: |
| 3039 | default: |
| 3040 | return 48; |
| 3041 | } |
| 3042 | } |
| 3043 | |
Mitchel Humpherys | 5494a5e | 2014-08-14 17:44:49 -0700 | [diff] [blame] | 3044 | static int arm_smmu_parse_impl_def_registers(struct arm_smmu_device *smmu) |
| 3045 | { |
| 3046 | struct device *dev = smmu->dev; |
| 3047 | int i, ntuples, ret; |
| 3048 | u32 *tuples; |
| 3049 | struct arm_smmu_impl_def_reg *regs, *regit; |
| 3050 | |
| 3051 | if (!of_find_property(dev->of_node, "attach-impl-defs", &ntuples)) |
| 3052 | return 0; |
| 3053 | |
| 3054 | ntuples /= sizeof(u32); |
| 3055 | if (ntuples % 2) { |
| 3056 | dev_err(dev, |
| 3057 | "Invalid number of attach-impl-defs registers: %d\n", |
| 3058 | ntuples); |
| 3059 | return -EINVAL; |
| 3060 | } |
| 3061 | |
| 3062 | regs = devm_kmalloc( |
| 3063 | dev, sizeof(*smmu->impl_def_attach_registers) * ntuples, |
| 3064 | GFP_KERNEL); |
| 3065 | if (!regs) |
| 3066 | return -ENOMEM; |
| 3067 | |
| 3068 | tuples = devm_kmalloc(dev, sizeof(u32) * ntuples * 2, GFP_KERNEL); |
| 3069 | if (!tuples) |
| 3070 | return -ENOMEM; |
| 3071 | |
| 3072 | ret = of_property_read_u32_array(dev->of_node, "attach-impl-defs", |
| 3073 | tuples, ntuples); |
| 3074 | if (ret) |
| 3075 | return ret; |
| 3076 | |
| 3077 | for (i = 0, regit = regs; i < ntuples; i += 2, ++regit) { |
| 3078 | regit->offset = tuples[i]; |
| 3079 | regit->value = tuples[i + 1]; |
| 3080 | } |
| 3081 | |
| 3082 | devm_kfree(dev, tuples); |
| 3083 | |
| 3084 | smmu->impl_def_attach_registers = regs; |
| 3085 | smmu->num_impl_def_attach_registers = ntuples / 2; |
| 3086 | |
| 3087 | return 0; |
| 3088 | } |
| 3089 | |
Patrick Daly | 3a8a88a | 2016-07-22 12:24:05 -0700 | [diff] [blame] | 3090 | static int arm_smmu_init_clocks(struct arm_smmu_device *smmu) |
| 3091 | { |
| 3092 | const char *cname; |
| 3093 | struct property *prop; |
| 3094 | int i; |
| 3095 | struct device *dev = smmu->dev; |
| 3096 | |
| 3097 | smmu->num_clocks = |
| 3098 | of_property_count_strings(dev->of_node, "clock-names"); |
| 3099 | |
Patrick Daly | f0c58e1 | 2016-10-12 22:15:36 -0700 | [diff] [blame] | 3100 | if (smmu->num_clocks < 1) { |
| 3101 | smmu->num_clocks = 0; |
Patrick Daly | 3a8a88a | 2016-07-22 12:24:05 -0700 | [diff] [blame] | 3102 | return 0; |
Patrick Daly | f0c58e1 | 2016-10-12 22:15:36 -0700 | [diff] [blame] | 3103 | } |
Patrick Daly | 3a8a88a | 2016-07-22 12:24:05 -0700 | [diff] [blame] | 3104 | |
| 3105 | smmu->clocks = devm_kzalloc( |
| 3106 | dev, sizeof(*smmu->clocks) * smmu->num_clocks, |
| 3107 | GFP_KERNEL); |
| 3108 | |
| 3109 | if (!smmu->clocks) { |
| 3110 | dev_err(dev, |
| 3111 | "Failed to allocate memory for clocks\n"); |
| 3112 | return -ENODEV; |
| 3113 | } |
| 3114 | |
| 3115 | i = 0; |
| 3116 | of_property_for_each_string(dev->of_node, "clock-names", |
| 3117 | prop, cname) { |
| 3118 | struct clk *c = devm_clk_get(dev, cname); |
| 3119 | |
| 3120 | if (IS_ERR(c)) { |
| 3121 | dev_err(dev, "Couldn't get clock: %s", |
| 3122 | cname); |
Mathew Joseph Karimpanal | 0c4fd1b | 2016-03-16 11:48:34 -0700 | [diff] [blame] | 3123 | return PTR_ERR(c); |
Patrick Daly | 3a8a88a | 2016-07-22 12:24:05 -0700 | [diff] [blame] | 3124 | } |
| 3125 | |
| 3126 | if (clk_get_rate(c) == 0) { |
| 3127 | long rate = clk_round_rate(c, 1000); |
| 3128 | |
| 3129 | clk_set_rate(c, rate); |
| 3130 | } |
| 3131 | |
| 3132 | smmu->clocks[i] = c; |
| 3133 | |
| 3134 | ++i; |
| 3135 | } |
| 3136 | return 0; |
| 3137 | } |
| 3138 | |
Mitchel Humpherys | f7666ae | 2014-07-23 17:35:07 -0700 | [diff] [blame] | 3139 | static int arm_smmu_init_regulators(struct arm_smmu_device *smmu) |
| 3140 | { |
| 3141 | struct device *dev = smmu->dev; |
| 3142 | |
| 3143 | if (!of_get_property(dev->of_node, "vdd-supply", NULL)) |
| 3144 | return 0; |
| 3145 | |
| 3146 | smmu->gdsc = devm_regulator_get(dev, "vdd"); |
| 3147 | if (IS_ERR(smmu->gdsc)) |
| 3148 | return PTR_ERR(smmu->gdsc); |
| 3149 | |
| 3150 | return 0; |
| 3151 | } |
| 3152 | |
Patrick Daly | 2764f95 | 2016-09-06 19:22:44 -0700 | [diff] [blame] | 3153 | static int arm_smmu_init_bus_scaling(struct platform_device *pdev, |
| 3154 | struct arm_smmu_device *smmu) |
| 3155 | { |
| 3156 | u32 master_id; |
| 3157 | |
| 3158 | if (of_property_read_u32(pdev->dev.of_node, "qcom,bus-master-id", |
| 3159 | &master_id)) { |
| 3160 | dev_dbg(smmu->dev, "No bus scaling info\n"); |
| 3161 | return 0; |
| 3162 | } |
| 3163 | |
| 3164 | smmu->bus_client_name = devm_kasprintf( |
| 3165 | smmu->dev, GFP_KERNEL, "smmu-bus-client-%s", |
| 3166 | dev_name(smmu->dev)); |
| 3167 | |
| 3168 | if (!smmu->bus_client_name) |
| 3169 | return -ENOMEM; |
| 3170 | |
| 3171 | smmu->bus_client = msm_bus_scale_register( |
| 3172 | master_id, MSM_BUS_SLAVE_EBI_CH0, smmu->bus_client_name, true); |
| 3173 | if (IS_ERR(&smmu->bus_client)) { |
| 3174 | int ret = PTR_ERR(smmu->bus_client); |
| 3175 | |
| 3176 | if (ret != -EPROBE_DEFER) |
| 3177 | dev_err(smmu->dev, "Bus client registration failed\n"); |
| 3178 | return ret; |
| 3179 | } |
| 3180 | |
| 3181 | return 0; |
| 3182 | } |
| 3183 | |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 3184 | static int arm_smmu_device_cfg_probe(struct arm_smmu_device *smmu) |
| 3185 | { |
| 3186 | unsigned long size; |
| 3187 | void __iomem *gr0_base = ARM_SMMU_GR0(smmu); |
| 3188 | u32 id; |
Robin Murphy | bae2c2d | 2015-07-29 19:46:05 +0100 | [diff] [blame] | 3189 | bool cttw_dt, cttw_reg; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 3190 | |
Mitchel Humpherys | ba82258 | 2015-10-20 11:37:41 -0700 | [diff] [blame] | 3191 | dev_dbg(smmu->dev, "probing hardware configuration...\n"); |
| 3192 | dev_dbg(smmu->dev, "SMMUv%d with:\n", |
Robin Murphy | b7862e3 | 2016-04-13 18:13:03 +0100 | [diff] [blame] | 3193 | smmu->version == ARM_SMMU_V2 ? 2 : 1); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 3194 | |
| 3195 | /* ID0 */ |
| 3196 | id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID0); |
Will Deacon | 4cf740b | 2014-07-14 19:47:39 +0100 | [diff] [blame] | 3197 | |
| 3198 | /* Restrict available stages based on module parameter */ |
| 3199 | if (force_stage == 1) |
| 3200 | id &= ~(ID0_S2TS | ID0_NTS); |
| 3201 | else if (force_stage == 2) |
| 3202 | id &= ~(ID0_S1TS | ID0_NTS); |
| 3203 | |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 3204 | if (id & ID0_S1TS) { |
| 3205 | smmu->features |= ARM_SMMU_FEAT_TRANS_S1; |
Mitchel Humpherys | ba82258 | 2015-10-20 11:37:41 -0700 | [diff] [blame] | 3206 | dev_dbg(smmu->dev, "\tstage 1 translation\n"); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 3207 | } |
| 3208 | |
| 3209 | if (id & ID0_S2TS) { |
| 3210 | smmu->features |= ARM_SMMU_FEAT_TRANS_S2; |
Mitchel Humpherys | ba82258 | 2015-10-20 11:37:41 -0700 | [diff] [blame] | 3211 | dev_dbg(smmu->dev, "\tstage 2 translation\n"); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 3212 | } |
| 3213 | |
| 3214 | if (id & ID0_NTS) { |
| 3215 | smmu->features |= ARM_SMMU_FEAT_TRANS_NESTED; |
Mitchel Humpherys | ba82258 | 2015-10-20 11:37:41 -0700 | [diff] [blame] | 3216 | dev_dbg(smmu->dev, "\tnested translation\n"); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 3217 | } |
| 3218 | |
| 3219 | if (!(smmu->features & |
Will Deacon | 4cf740b | 2014-07-14 19:47:39 +0100 | [diff] [blame] | 3220 | (ARM_SMMU_FEAT_TRANS_S1 | ARM_SMMU_FEAT_TRANS_S2))) { |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 3221 | dev_err(smmu->dev, "\tno translation support!\n"); |
| 3222 | return -ENODEV; |
| 3223 | } |
| 3224 | |
Robin Murphy | b7862e3 | 2016-04-13 18:13:03 +0100 | [diff] [blame] | 3225 | if ((id & ID0_S1TS) && |
| 3226 | ((smmu->version < ARM_SMMU_V2) || !(id & ID0_ATOSNS))) { |
Mitchel Humpherys | 859a732 | 2014-10-29 21:13:40 +0000 | [diff] [blame] | 3227 | smmu->features |= ARM_SMMU_FEAT_TRANS_OPS; |
Mitchel Humpherys | ba82258 | 2015-10-20 11:37:41 -0700 | [diff] [blame] | 3228 | dev_dbg(smmu->dev, "\taddress translation ops\n"); |
Mitchel Humpherys | 859a732 | 2014-10-29 21:13:40 +0000 | [diff] [blame] | 3229 | } |
| 3230 | |
Robin Murphy | bae2c2d | 2015-07-29 19:46:05 +0100 | [diff] [blame] | 3231 | /* |
| 3232 | * In order for DMA API calls to work properly, we must defer to what |
| 3233 | * the DT says about coherency, regardless of what the hardware claims. |
| 3234 | * Fortunately, this also opens up a workaround for systems where the |
| 3235 | * ID register value has ended up configured incorrectly. |
| 3236 | */ |
| 3237 | cttw_dt = of_dma_is_coherent(smmu->dev->of_node); |
| 3238 | cttw_reg = !!(id & ID0_CTTW); |
| 3239 | if (cttw_dt) |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 3240 | smmu->features |= ARM_SMMU_FEAT_COHERENT_WALK; |
Robin Murphy | bae2c2d | 2015-07-29 19:46:05 +0100 | [diff] [blame] | 3241 | if (cttw_dt || cttw_reg) |
Mitchel Humpherys | ba82258 | 2015-10-20 11:37:41 -0700 | [diff] [blame] | 3242 | dev_dbg(smmu->dev, "\t%scoherent table walk\n", |
Robin Murphy | bae2c2d | 2015-07-29 19:46:05 +0100 | [diff] [blame] | 3243 | cttw_dt ? "" : "non-"); |
| 3244 | if (cttw_dt != cttw_reg) |
| 3245 | dev_notice(smmu->dev, |
| 3246 | "\t(IDR0.CTTW overridden by dma-coherent property)\n"); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 3247 | |
| 3248 | if (id & ID0_SMS) { |
| 3249 | u32 smr, sid, mask; |
| 3250 | |
| 3251 | smmu->features |= ARM_SMMU_FEAT_STREAM_MATCH; |
| 3252 | smmu->num_mapping_groups = (id >> ID0_NUMSMRG_SHIFT) & |
| 3253 | ID0_NUMSMRG_MASK; |
| 3254 | if (smmu->num_mapping_groups == 0) { |
| 3255 | dev_err(smmu->dev, |
| 3256 | "stream-matching supported, but no SMRs present!\n"); |
| 3257 | return -ENODEV; |
| 3258 | } |
| 3259 | |
Dhaval Patel | 031d746 | 2015-05-09 14:47:29 -0700 | [diff] [blame] | 3260 | if (!(smmu->options & ARM_SMMU_OPT_SKIP_INIT)) { |
| 3261 | smr = SMR_MASK_MASK << SMR_MASK_SHIFT; |
| 3262 | smr |= (SMR_ID_MASK << SMR_ID_SHIFT); |
| 3263 | writel_relaxed(smr, gr0_base + ARM_SMMU_GR0_SMR(0)); |
| 3264 | smr = readl_relaxed(gr0_base + ARM_SMMU_GR0_SMR(0)); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 3265 | |
Dhaval Patel | 031d746 | 2015-05-09 14:47:29 -0700 | [diff] [blame] | 3266 | mask = (smr >> SMR_MASK_SHIFT) & SMR_MASK_MASK; |
| 3267 | sid = (smr >> SMR_ID_SHIFT) & SMR_ID_MASK; |
| 3268 | if ((mask & sid) != sid) { |
| 3269 | dev_err(smmu->dev, |
| 3270 | "SMR mask bits (0x%x) insufficient for ID field (0x%x)\n", |
| 3271 | mask, sid); |
| 3272 | return -ENODEV; |
| 3273 | } |
| 3274 | |
Mitchel Humpherys | ba82258 | 2015-10-20 11:37:41 -0700 | [diff] [blame] | 3275 | dev_dbg(smmu->dev, |
Dhaval Patel | 031d746 | 2015-05-09 14:47:29 -0700 | [diff] [blame] | 3276 | "\tstream matching with %u register groups, mask 0x%x", |
| 3277 | smmu->num_mapping_groups, mask); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 3278 | } |
Olav Haugan | 3c8766d | 2014-08-22 17:12:32 -0700 | [diff] [blame] | 3279 | } else { |
| 3280 | smmu->num_mapping_groups = (id >> ID0_NUMSIDB_SHIFT) & |
| 3281 | ID0_NUMSIDB_MASK; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 3282 | } |
| 3283 | |
Robin Murphy | 7602b87 | 2016-04-28 17:12:09 +0100 | [diff] [blame] | 3284 | if (smmu->version < ARM_SMMU_V2 || !(id & ID0_PTFS_NO_AARCH32)) { |
| 3285 | smmu->features |= ARM_SMMU_FEAT_FMT_AARCH32_L; |
| 3286 | if (!(id & ID0_PTFS_NO_AARCH32S)) |
| 3287 | smmu->features |= ARM_SMMU_FEAT_FMT_AARCH32_S; |
| 3288 | } |
| 3289 | |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 3290 | /* ID1 */ |
| 3291 | id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID1); |
Will Deacon | c757e85 | 2014-07-30 11:33:25 +0100 | [diff] [blame] | 3292 | smmu->pgshift = (id & ID1_PAGESIZE) ? 16 : 12; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 3293 | |
Andreas Herrmann | c55af7f | 2013-10-01 13:39:06 +0100 | [diff] [blame] | 3294 | /* Check for size mismatch of SMMU address space from mapped region */ |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame] | 3295 | size = 1 << (((id >> ID1_NUMPAGENDXB_SHIFT) & ID1_NUMPAGENDXB_MASK) + 1); |
Will Deacon | c757e85 | 2014-07-30 11:33:25 +0100 | [diff] [blame] | 3296 | size *= 2 << smmu->pgshift; |
Andreas Herrmann | c55af7f | 2013-10-01 13:39:06 +0100 | [diff] [blame] | 3297 | if (smmu->size != size) |
Mitchel Humpherys | 2907320 | 2014-07-08 09:52:18 -0700 | [diff] [blame] | 3298 | dev_warn(smmu->dev, |
| 3299 | "SMMU address space size (0x%lx) differs from mapped region size (0x%lx)!\n", |
| 3300 | size, smmu->size); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 3301 | |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame] | 3302 | smmu->num_s2_context_banks = (id >> ID1_NUMS2CB_SHIFT) & ID1_NUMS2CB_MASK; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 3303 | smmu->num_context_banks = (id >> ID1_NUMCB_SHIFT) & ID1_NUMCB_MASK; |
| 3304 | if (smmu->num_s2_context_banks > smmu->num_context_banks) { |
| 3305 | dev_err(smmu->dev, "impossible number of S2 context banks!\n"); |
| 3306 | return -ENODEV; |
| 3307 | } |
Mitchel Humpherys | ba82258 | 2015-10-20 11:37:41 -0700 | [diff] [blame] | 3308 | dev_dbg(smmu->dev, "\t%u context banks (%u stage-2 only)\n", |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 3309 | smmu->num_context_banks, smmu->num_s2_context_banks); |
Robin Murphy | e086d91 | 2016-04-13 18:12:58 +0100 | [diff] [blame] | 3310 | /* |
| 3311 | * Cavium CN88xx erratum #27704. |
| 3312 | * Ensure ASID and VMID allocation is unique across all SMMUs in |
| 3313 | * the system. |
| 3314 | */ |
| 3315 | if (smmu->model == CAVIUM_SMMUV2) { |
| 3316 | smmu->cavium_id_base = |
| 3317 | atomic_add_return(smmu->num_context_banks, |
| 3318 | &cavium_smmu_context_count); |
| 3319 | smmu->cavium_id_base -= smmu->num_context_banks; |
| 3320 | } |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 3321 | |
| 3322 | /* ID2 */ |
| 3323 | id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID2); |
| 3324 | size = arm_smmu_id_size_to_bits((id >> ID2_IAS_SHIFT) & ID2_IAS_MASK); |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame] | 3325 | smmu->ipa_size = size; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 3326 | |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame] | 3327 | /* The output mask is also applied for bypass */ |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 3328 | size = arm_smmu_id_size_to_bits((id >> ID2_OAS_SHIFT) & ID2_OAS_MASK); |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame] | 3329 | smmu->pa_size = size; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 3330 | |
Tirumalesh Chalamarla | 4e3e9b6 | 2016-02-23 10:19:00 -0800 | [diff] [blame] | 3331 | if (id & ID2_VMID16) |
| 3332 | smmu->features |= ARM_SMMU_FEAT_VMID16; |
| 3333 | |
Robin Murphy | f1d8454 | 2015-03-04 16:41:05 +0000 | [diff] [blame] | 3334 | /* |
| 3335 | * What the page table walker can address actually depends on which |
| 3336 | * descriptor format is in use, but since a) we don't know that yet, |
| 3337 | * and b) it can vary per context bank, this will have to do... |
| 3338 | */ |
| 3339 | if (dma_set_mask_and_coherent(smmu->dev, DMA_BIT_MASK(size))) |
| 3340 | dev_warn(smmu->dev, |
| 3341 | "failed to set DMA mask for table walker\n"); |
| 3342 | |
Robin Murphy | b7862e3 | 2016-04-13 18:13:03 +0100 | [diff] [blame] | 3343 | if (smmu->version < ARM_SMMU_V2) { |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame] | 3344 | smmu->va_size = smmu->ipa_size; |
Robin Murphy | b7862e3 | 2016-04-13 18:13:03 +0100 | [diff] [blame] | 3345 | if (smmu->version == ARM_SMMU_V1_64K) |
| 3346 | smmu->features |= ARM_SMMU_FEAT_FMT_AARCH64_64K; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 3347 | } else { |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 3348 | size = (id >> ID2_UBS_SHIFT) & ID2_UBS_MASK; |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame] | 3349 | smmu->va_size = arm_smmu_id_size_to_bits(size); |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame] | 3350 | if (id & ID2_PTFS_4K) |
Robin Murphy | 7602b87 | 2016-04-28 17:12:09 +0100 | [diff] [blame] | 3351 | smmu->features |= ARM_SMMU_FEAT_FMT_AARCH64_4K; |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame] | 3352 | if (id & ID2_PTFS_16K) |
Robin Murphy | 7602b87 | 2016-04-28 17:12:09 +0100 | [diff] [blame] | 3353 | smmu->features |= ARM_SMMU_FEAT_FMT_AARCH64_16K; |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame] | 3354 | if (id & ID2_PTFS_64K) |
Robin Murphy | 7602b87 | 2016-04-28 17:12:09 +0100 | [diff] [blame] | 3355 | smmu->features |= ARM_SMMU_FEAT_FMT_AARCH64_64K; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 3356 | } |
| 3357 | |
Robin Murphy | 7602b87 | 2016-04-28 17:12:09 +0100 | [diff] [blame] | 3358 | /* Now we've corralled the various formats, what'll it do? */ |
Robin Murphy | 7602b87 | 2016-04-28 17:12:09 +0100 | [diff] [blame] | 3359 | if (smmu->features & ARM_SMMU_FEAT_FMT_AARCH32_S) |
Robin Murphy | d546635 | 2016-05-09 17:20:09 +0100 | [diff] [blame] | 3360 | smmu->pgsize_bitmap |= SZ_4K | SZ_64K | SZ_1M | SZ_16M; |
Robin Murphy | 7602b87 | 2016-04-28 17:12:09 +0100 | [diff] [blame] | 3361 | if (smmu->features & |
| 3362 | (ARM_SMMU_FEAT_FMT_AARCH32_L | ARM_SMMU_FEAT_FMT_AARCH64_4K)) |
Robin Murphy | d546635 | 2016-05-09 17:20:09 +0100 | [diff] [blame] | 3363 | smmu->pgsize_bitmap |= SZ_4K | SZ_2M | SZ_1G; |
Robin Murphy | 7602b87 | 2016-04-28 17:12:09 +0100 | [diff] [blame] | 3364 | if (smmu->features & ARM_SMMU_FEAT_FMT_AARCH64_16K) |
Robin Murphy | d546635 | 2016-05-09 17:20:09 +0100 | [diff] [blame] | 3365 | smmu->pgsize_bitmap |= SZ_16K | SZ_32M; |
Robin Murphy | 7602b87 | 2016-04-28 17:12:09 +0100 | [diff] [blame] | 3366 | if (smmu->features & ARM_SMMU_FEAT_FMT_AARCH64_64K) |
Robin Murphy | d546635 | 2016-05-09 17:20:09 +0100 | [diff] [blame] | 3367 | smmu->pgsize_bitmap |= SZ_64K | SZ_512M; |
Robin Murphy | 7602b87 | 2016-04-28 17:12:09 +0100 | [diff] [blame] | 3368 | |
Robin Murphy | d546635 | 2016-05-09 17:20:09 +0100 | [diff] [blame] | 3369 | if (arm_smmu_ops.pgsize_bitmap == -1UL) |
| 3370 | arm_smmu_ops.pgsize_bitmap = smmu->pgsize_bitmap; |
| 3371 | else |
| 3372 | arm_smmu_ops.pgsize_bitmap |= smmu->pgsize_bitmap; |
Mitchel Humpherys | ba82258 | 2015-10-20 11:37:41 -0700 | [diff] [blame] | 3373 | dev_dbg(smmu->dev, "\tSupported page sizes: 0x%08lx\n", |
Robin Murphy | d546635 | 2016-05-09 17:20:09 +0100 | [diff] [blame] | 3374 | smmu->pgsize_bitmap); |
| 3375 | |
Will Deacon | 518f713 | 2014-11-14 17:17:54 +0000 | [diff] [blame] | 3376 | |
Will Deacon | 28d6007 | 2014-09-01 16:24:48 +0100 | [diff] [blame] | 3377 | if (smmu->features & ARM_SMMU_FEAT_TRANS_S1) |
Mitchel Humpherys | ba82258 | 2015-10-20 11:37:41 -0700 | [diff] [blame] | 3378 | dev_dbg(smmu->dev, "\tStage-1: %lu-bit VA -> %lu-bit IPA\n", |
| 3379 | smmu->va_size, smmu->ipa_size); |
Will Deacon | 28d6007 | 2014-09-01 16:24:48 +0100 | [diff] [blame] | 3380 | |
| 3381 | if (smmu->features & ARM_SMMU_FEAT_TRANS_S2) |
Mitchel Humpherys | ba82258 | 2015-10-20 11:37:41 -0700 | [diff] [blame] | 3382 | dev_dbg(smmu->dev, "\tStage-2: %lu-bit IPA -> %lu-bit PA\n", |
| 3383 | smmu->ipa_size, smmu->pa_size); |
Will Deacon | 28d6007 | 2014-09-01 16:24:48 +0100 | [diff] [blame] | 3384 | |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 3385 | return 0; |
| 3386 | } |
| 3387 | |
Robin Murphy | 67b65a3 | 2016-04-13 18:12:57 +0100 | [diff] [blame] | 3388 | struct arm_smmu_match_data { |
| 3389 | enum arm_smmu_arch_version version; |
| 3390 | enum arm_smmu_implementation model; |
| 3391 | }; |
| 3392 | |
| 3393 | #define ARM_SMMU_MATCH_DATA(name, ver, imp) \ |
| 3394 | static struct arm_smmu_match_data name = { .version = ver, .model = imp } |
| 3395 | |
| 3396 | ARM_SMMU_MATCH_DATA(smmu_generic_v1, ARM_SMMU_V1, GENERIC_SMMU); |
| 3397 | ARM_SMMU_MATCH_DATA(smmu_generic_v2, ARM_SMMU_V2, GENERIC_SMMU); |
Robin Murphy | b7862e3 | 2016-04-13 18:13:03 +0100 | [diff] [blame] | 3398 | ARM_SMMU_MATCH_DATA(arm_mmu401, ARM_SMMU_V1_64K, GENERIC_SMMU); |
Robin Murphy | f0cfffc | 2016-04-13 18:12:59 +0100 | [diff] [blame] | 3399 | ARM_SMMU_MATCH_DATA(arm_mmu500, ARM_SMMU_V2, ARM_MMU500); |
Robin Murphy | e086d91 | 2016-04-13 18:12:58 +0100 | [diff] [blame] | 3400 | ARM_SMMU_MATCH_DATA(cavium_smmuv2, ARM_SMMU_V2, CAVIUM_SMMUV2); |
Patrick Daly | f0d4e21 | 2016-06-20 15:50:14 -0700 | [diff] [blame] | 3401 | ARM_SMMU_MATCH_DATA(qcom_smmuv2, ARM_SMMU_V2, QCOM_SMMUV2); |
Robin Murphy | 67b65a3 | 2016-04-13 18:12:57 +0100 | [diff] [blame] | 3402 | |
Joerg Roedel | 09b5269 | 2014-10-02 12:24:45 +0200 | [diff] [blame] | 3403 | static const struct of_device_id arm_smmu_of_match[] = { |
Robin Murphy | 67b65a3 | 2016-04-13 18:12:57 +0100 | [diff] [blame] | 3404 | { .compatible = "arm,smmu-v1", .data = &smmu_generic_v1 }, |
| 3405 | { .compatible = "arm,smmu-v2", .data = &smmu_generic_v2 }, |
| 3406 | { .compatible = "arm,mmu-400", .data = &smmu_generic_v1 }, |
Robin Murphy | b7862e3 | 2016-04-13 18:13:03 +0100 | [diff] [blame] | 3407 | { .compatible = "arm,mmu-401", .data = &arm_mmu401 }, |
Robin Murphy | f0cfffc | 2016-04-13 18:12:59 +0100 | [diff] [blame] | 3408 | { .compatible = "arm,mmu-500", .data = &arm_mmu500 }, |
Robin Murphy | e086d91 | 2016-04-13 18:12:58 +0100 | [diff] [blame] | 3409 | { .compatible = "cavium,smmu-v2", .data = &cavium_smmuv2 }, |
Patrick Daly | f0d4e21 | 2016-06-20 15:50:14 -0700 | [diff] [blame] | 3410 | { .compatible = "qcom,smmu-v2", .data = &qcom_smmuv2 }, |
Robin Murphy | 0936040 | 2014-08-28 17:51:59 +0100 | [diff] [blame] | 3411 | { }, |
| 3412 | }; |
| 3413 | MODULE_DEVICE_TABLE(of, arm_smmu_of_match); |
| 3414 | |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 3415 | static int arm_smmu_device_dt_probe(struct platform_device *pdev) |
| 3416 | { |
Robin Murphy | 0936040 | 2014-08-28 17:51:59 +0100 | [diff] [blame] | 3417 | const struct of_device_id *of_id; |
Robin Murphy | 67b65a3 | 2016-04-13 18:12:57 +0100 | [diff] [blame] | 3418 | const struct arm_smmu_match_data *data; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 3419 | struct resource *res; |
| 3420 | struct arm_smmu_device *smmu; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 3421 | struct device *dev = &pdev->dev; |
| 3422 | struct rb_node *node; |
Mitchel Humpherys | c6dd1ed | 2014-08-04 16:45:53 -0700 | [diff] [blame] | 3423 | int num_irqs, i, err, num_masters; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 3424 | |
| 3425 | smmu = devm_kzalloc(dev, sizeof(*smmu), GFP_KERNEL); |
| 3426 | if (!smmu) { |
| 3427 | dev_err(dev, "failed to allocate arm_smmu_device\n"); |
| 3428 | return -ENOMEM; |
| 3429 | } |
| 3430 | smmu->dev = dev; |
Mitchel Humpherys | 2fbae2a | 2014-12-04 11:46:24 -0800 | [diff] [blame] | 3431 | spin_lock_init(&smmu->atos_lock); |
Patrick Daly | 3a8a88a | 2016-07-22 12:24:05 -0700 | [diff] [blame] | 3432 | mutex_init(&smmu->power_lock); |
Patrick Daly | 8befb66 | 2016-08-17 20:03:28 -0700 | [diff] [blame] | 3433 | spin_lock_init(&smmu->clock_refs_lock); |
Patrick Daly | c190d93 | 2016-08-30 17:23:28 -0700 | [diff] [blame] | 3434 | idr_init(&smmu->asid_idr); |
| 3435 | mutex_init(&smmu->idr_mutex); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 3436 | |
Robin Murphy | 0936040 | 2014-08-28 17:51:59 +0100 | [diff] [blame] | 3437 | of_id = of_match_node(arm_smmu_of_match, dev->of_node); |
Robin Murphy | 67b65a3 | 2016-04-13 18:12:57 +0100 | [diff] [blame] | 3438 | data = of_id->data; |
| 3439 | smmu->version = data->version; |
| 3440 | smmu->model = data->model; |
Robin Murphy | 0936040 | 2014-08-28 17:51:59 +0100 | [diff] [blame] | 3441 | |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 3442 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
Julia Lawall | 8a7f431 | 2013-08-19 12:20:37 +0100 | [diff] [blame] | 3443 | smmu->base = devm_ioremap_resource(dev, res); |
| 3444 | if (IS_ERR(smmu->base)) |
| 3445 | return PTR_ERR(smmu->base); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 3446 | smmu->size = resource_size(res); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 3447 | |
| 3448 | if (of_property_read_u32(dev->of_node, "#global-interrupts", |
| 3449 | &smmu->num_global_irqs)) { |
| 3450 | dev_err(dev, "missing #global-interrupts property\n"); |
| 3451 | return -ENODEV; |
| 3452 | } |
| 3453 | |
| 3454 | num_irqs = 0; |
| 3455 | while ((res = platform_get_resource(pdev, IORESOURCE_IRQ, num_irqs))) { |
| 3456 | num_irqs++; |
| 3457 | if (num_irqs > smmu->num_global_irqs) |
| 3458 | smmu->num_context_irqs++; |
| 3459 | } |
| 3460 | |
Andreas Herrmann | 44a08de | 2013-10-01 13:39:07 +0100 | [diff] [blame] | 3461 | if (!smmu->num_context_irqs) { |
| 3462 | dev_err(dev, "found %d interrupts but expected at least %d\n", |
| 3463 | num_irqs, smmu->num_global_irqs + 1); |
| 3464 | return -ENODEV; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 3465 | } |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 3466 | |
| 3467 | smmu->irqs = devm_kzalloc(dev, sizeof(*smmu->irqs) * num_irqs, |
| 3468 | GFP_KERNEL); |
| 3469 | if (!smmu->irqs) { |
| 3470 | dev_err(dev, "failed to allocate %d irqs\n", num_irqs); |
| 3471 | return -ENOMEM; |
| 3472 | } |
| 3473 | |
| 3474 | for (i = 0; i < num_irqs; ++i) { |
| 3475 | int irq = platform_get_irq(pdev, i); |
Mitchel Humpherys | 2907320 | 2014-07-08 09:52:18 -0700 | [diff] [blame] | 3476 | |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 3477 | if (irq < 0) { |
| 3478 | dev_err(dev, "failed to get irq index %d\n", i); |
| 3479 | return -ENODEV; |
| 3480 | } |
| 3481 | smmu->irqs[i] = irq; |
| 3482 | } |
| 3483 | |
Dhaval Patel | 031d746 | 2015-05-09 14:47:29 -0700 | [diff] [blame] | 3484 | parse_driver_options(smmu); |
| 3485 | |
Patrick Daly | 3a8a88a | 2016-07-22 12:24:05 -0700 | [diff] [blame] | 3486 | err = arm_smmu_init_clocks(smmu); |
Olav Haugan | 3c8766d | 2014-08-22 17:12:32 -0700 | [diff] [blame] | 3487 | if (err) |
| 3488 | return err; |
| 3489 | |
Mitchel Humpherys | f7666ae | 2014-07-23 17:35:07 -0700 | [diff] [blame] | 3490 | err = arm_smmu_init_regulators(smmu); |
| 3491 | if (err) |
| 3492 | return err; |
| 3493 | |
Patrick Daly | 2764f95 | 2016-09-06 19:22:44 -0700 | [diff] [blame] | 3494 | err = arm_smmu_init_bus_scaling(pdev, smmu); |
| 3495 | if (err) |
| 3496 | return err; |
| 3497 | |
Patrick Daly | 3a8a88a | 2016-07-22 12:24:05 -0700 | [diff] [blame] | 3498 | err = arm_smmu_power_on(smmu); |
| 3499 | if (err) |
| 3500 | return err; |
| 3501 | |
| 3502 | err = arm_smmu_device_cfg_probe(smmu); |
| 3503 | if (err) |
| 3504 | goto out_power_off; |
| 3505 | |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 3506 | i = 0; |
| 3507 | smmu->masters = RB_ROOT; |
Joerg Roedel | cb6c27b | 2016-04-04 17:49:22 +0200 | [diff] [blame] | 3508 | |
Mitchel Humpherys | c6dd1ed | 2014-08-04 16:45:53 -0700 | [diff] [blame] | 3509 | err = arm_smmu_parse_iommus_properties(smmu, &num_masters); |
| 3510 | if (err) |
Joerg Roedel | cb6c27b | 2016-04-04 17:49:22 +0200 | [diff] [blame] | 3511 | goto out_put_masters; |
| 3512 | |
Mitchel Humpherys | ba82258 | 2015-10-20 11:37:41 -0700 | [diff] [blame] | 3513 | dev_dbg(dev, "registered %d master devices\n", num_masters); |
Joerg Roedel | cb6c27b | 2016-04-04 17:49:22 +0200 | [diff] [blame] | 3514 | |
Mitchel Humpherys | 5494a5e | 2014-08-14 17:44:49 -0700 | [diff] [blame] | 3515 | err = arm_smmu_parse_impl_def_registers(smmu); |
| 3516 | if (err) |
| 3517 | goto out_put_masters; |
| 3518 | |
Robin Murphy | b7862e3 | 2016-04-13 18:13:03 +0100 | [diff] [blame] | 3519 | if (smmu->version == ARM_SMMU_V2 && |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 3520 | smmu->num_context_banks != smmu->num_context_irqs) { |
| 3521 | dev_err(dev, |
Mitchel Humpherys | 73230ce | 2014-12-11 17:18:02 -0800 | [diff] [blame] | 3522 | "found %d context interrupt(s) but have %d context banks. assuming %d context interrupts.\n", |
| 3523 | smmu->num_context_irqs, smmu->num_context_banks, |
| 3524 | smmu->num_context_banks); |
| 3525 | smmu->num_context_irqs = smmu->num_context_banks; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 3526 | } |
| 3527 | |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 3528 | for (i = 0; i < smmu->num_global_irqs; ++i) { |
Mitchel Humpherys | c4f2a80 | 2015-02-04 21:29:46 -0800 | [diff] [blame] | 3529 | err = devm_request_threaded_irq(smmu->dev, smmu->irqs[i], |
| 3530 | NULL, arm_smmu_global_fault, |
| 3531 | IRQF_ONESHOT | IRQF_SHARED, |
| 3532 | "arm-smmu global fault", smmu); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 3533 | if (err) { |
| 3534 | dev_err(dev, "failed to request global IRQ %d (%u)\n", |
| 3535 | i, smmu->irqs[i]); |
Peng Fan | bee1400 | 2016-07-04 17:38:22 +0800 | [diff] [blame] | 3536 | goto out_put_masters; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 3537 | } |
| 3538 | } |
| 3539 | |
| 3540 | INIT_LIST_HEAD(&smmu->list); |
| 3541 | spin_lock(&arm_smmu_devices_lock); |
| 3542 | list_add(&smmu->list, &arm_smmu_devices); |
| 3543 | spin_unlock(&arm_smmu_devices_lock); |
Will Deacon | fd90cec | 2013-08-21 13:56:34 +0100 | [diff] [blame] | 3544 | |
| 3545 | arm_smmu_device_reset(smmu); |
Patrick Daly | 3a8a88a | 2016-07-22 12:24:05 -0700 | [diff] [blame] | 3546 | arm_smmu_power_off(smmu); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 3547 | return 0; |
| 3548 | |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 3549 | out_put_masters: |
| 3550 | for (node = rb_first(&smmu->masters); node; node = rb_next(node)) { |
Mitchel Humpherys | 2907320 | 2014-07-08 09:52:18 -0700 | [diff] [blame] | 3551 | struct arm_smmu_master *master |
| 3552 | = container_of(node, struct arm_smmu_master, node); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 3553 | of_node_put(master->of_node); |
| 3554 | } |
| 3555 | |
Patrick Daly | 3a8a88a | 2016-07-22 12:24:05 -0700 | [diff] [blame] | 3556 | out_power_off: |
| 3557 | arm_smmu_power_off(smmu); |
| 3558 | |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 3559 | return err; |
| 3560 | } |
| 3561 | |
| 3562 | static int arm_smmu_device_remove(struct platform_device *pdev) |
| 3563 | { |
| 3564 | int i; |
| 3565 | struct device *dev = &pdev->dev; |
| 3566 | struct arm_smmu_device *curr, *smmu = NULL; |
| 3567 | struct rb_node *node; |
| 3568 | |
| 3569 | spin_lock(&arm_smmu_devices_lock); |
| 3570 | list_for_each_entry(curr, &arm_smmu_devices, list) { |
| 3571 | if (curr->dev == dev) { |
| 3572 | smmu = curr; |
| 3573 | list_del(&smmu->list); |
| 3574 | break; |
| 3575 | } |
| 3576 | } |
| 3577 | spin_unlock(&arm_smmu_devices_lock); |
| 3578 | |
| 3579 | if (!smmu) |
| 3580 | return -ENODEV; |
| 3581 | |
Mitchel Humpherys | 3e52a7e | 2015-10-19 17:13:47 -0700 | [diff] [blame] | 3582 | if (arm_smmu_power_on(smmu)) |
| 3583 | return -EINVAL; |
| 3584 | |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 3585 | for (node = rb_first(&smmu->masters); node; node = rb_next(node)) { |
Mitchel Humpherys | 2907320 | 2014-07-08 09:52:18 -0700 | [diff] [blame] | 3586 | struct arm_smmu_master *master |
| 3587 | = container_of(node, struct arm_smmu_master, node); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 3588 | of_node_put(master->of_node); |
| 3589 | } |
| 3590 | |
Will Deacon | ecfadb6 | 2013-07-31 19:21:28 +0100 | [diff] [blame] | 3591 | if (!bitmap_empty(smmu->context_map, ARM_SMMU_MAX_CBS)) |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 3592 | dev_err(dev, "removing device with active domains!\n"); |
| 3593 | |
| 3594 | for (i = 0; i < smmu->num_global_irqs; ++i) |
Peng Fan | bee1400 | 2016-07-04 17:38:22 +0800 | [diff] [blame] | 3595 | devm_free_irq(smmu->dev, smmu->irqs[i], smmu); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 3596 | |
Patrick Daly | c190d93 | 2016-08-30 17:23:28 -0700 | [diff] [blame] | 3597 | idr_destroy(&smmu->asid_idr); |
| 3598 | |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 3599 | /* Turn the thing off */ |
Mitchel Humpherys | 2907320 | 2014-07-08 09:52:18 -0700 | [diff] [blame] | 3600 | writel(sCR0_CLIENTPD, ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sCR0); |
Patrick Daly | 3a8a88a | 2016-07-22 12:24:05 -0700 | [diff] [blame] | 3601 | arm_smmu_power_off(smmu); |
| 3602 | |
Patrick Daly | 2764f95 | 2016-09-06 19:22:44 -0700 | [diff] [blame] | 3603 | msm_bus_scale_unregister(smmu->bus_client); |
| 3604 | |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 3605 | return 0; |
| 3606 | } |
| 3607 | |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 3608 | static struct platform_driver arm_smmu_driver = { |
| 3609 | .driver = { |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 3610 | .name = "arm-smmu", |
| 3611 | .of_match_table = of_match_ptr(arm_smmu_of_match), |
| 3612 | }, |
| 3613 | .probe = arm_smmu_device_dt_probe, |
| 3614 | .remove = arm_smmu_device_remove, |
| 3615 | }; |
| 3616 | |
| 3617 | static int __init arm_smmu_init(void) |
| 3618 | { |
Thierry Reding | 0e7d37a | 2014-11-07 15:26:18 +0000 | [diff] [blame] | 3619 | struct device_node *np; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 3620 | int ret; |
| 3621 | |
Thierry Reding | 0e7d37a | 2014-11-07 15:26:18 +0000 | [diff] [blame] | 3622 | /* |
| 3623 | * Play nice with systems that don't have an ARM SMMU by checking that |
| 3624 | * an ARM SMMU exists in the system before proceeding with the driver |
| 3625 | * and IOMMU bus operation registration. |
| 3626 | */ |
| 3627 | np = of_find_matching_node(NULL, arm_smmu_of_match); |
| 3628 | if (!np) |
| 3629 | return 0; |
| 3630 | |
| 3631 | of_node_put(np); |
| 3632 | |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 3633 | ret = platform_driver_register(&arm_smmu_driver); |
| 3634 | if (ret) |
| 3635 | return ret; |
| 3636 | |
| 3637 | /* Oh, for a proper bus abstraction */ |
Dan Carpenter | 6614ee7 | 2013-08-21 09:34:20 +0100 | [diff] [blame] | 3638 | if (!iommu_present(&platform_bus_type)) |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 3639 | bus_set_iommu(&platform_bus_type, &arm_smmu_ops); |
| 3640 | |
Will Deacon | d123cf8 | 2014-02-04 22:17:53 +0000 | [diff] [blame] | 3641 | #ifdef CONFIG_ARM_AMBA |
Dan Carpenter | 6614ee7 | 2013-08-21 09:34:20 +0100 | [diff] [blame] | 3642 | if (!iommu_present(&amba_bustype)) |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 3643 | bus_set_iommu(&amba_bustype, &arm_smmu_ops); |
Will Deacon | d123cf8 | 2014-02-04 22:17:53 +0000 | [diff] [blame] | 3644 | #endif |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 3645 | |
Will Deacon | a9a1b0b | 2014-05-01 18:05:08 +0100 | [diff] [blame] | 3646 | #ifdef CONFIG_PCI |
Wei Chen | 112c898 | 2016-06-13 17:20:17 +0800 | [diff] [blame] | 3647 | if (!iommu_present(&pci_bus_type)) { |
| 3648 | pci_request_acs(); |
Will Deacon | a9a1b0b | 2014-05-01 18:05:08 +0100 | [diff] [blame] | 3649 | bus_set_iommu(&pci_bus_type, &arm_smmu_ops); |
Wei Chen | 112c898 | 2016-06-13 17:20:17 +0800 | [diff] [blame] | 3650 | } |
Will Deacon | a9a1b0b | 2014-05-01 18:05:08 +0100 | [diff] [blame] | 3651 | #endif |
| 3652 | |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 3653 | return 0; |
| 3654 | } |
| 3655 | |
| 3656 | static void __exit arm_smmu_exit(void) |
| 3657 | { |
| 3658 | return platform_driver_unregister(&arm_smmu_driver); |
| 3659 | } |
| 3660 | |
Andreas Herrmann | b1950b2 | 2013-10-01 13:39:05 +0100 | [diff] [blame] | 3661 | subsys_initcall(arm_smmu_init); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 3662 | module_exit(arm_smmu_exit); |
| 3663 | |
| 3664 | MODULE_DESCRIPTION("IOMMU API for ARM architected SMMU implementations"); |
| 3665 | MODULE_AUTHOR("Will Deacon <will.deacon@arm.com>"); |
| 3666 | MODULE_LICENSE("GPL v2"); |