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Oscar Mateob20385f2014-07-24 17:04:10 +01001/*
2 * Copyright © 2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Ben Widawsky <ben@bwidawsk.net>
25 * Michel Thierry <michel.thierry@intel.com>
26 * Thomas Daniel <thomas.daniel@intel.com>
27 * Oscar Mateo <oscar.mateo@intel.com>
28 *
29 */
30
Oscar Mateo73e4d072014-07-24 17:04:48 +010031/**
32 * DOC: Logical Rings, Logical Ring Contexts and Execlists
33 *
34 * Motivation:
Oscar Mateob20385f2014-07-24 17:04:10 +010035 * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts".
36 * These expanded contexts enable a number of new abilities, especially
37 * "Execlists" (also implemented in this file).
38 *
Oscar Mateo73e4d072014-07-24 17:04:48 +010039 * One of the main differences with the legacy HW contexts is that logical
40 * ring contexts incorporate many more things to the context's state, like
41 * PDPs or ringbuffer control registers:
42 *
43 * The reason why PDPs are included in the context is straightforward: as
44 * PPGTTs (per-process GTTs) are actually per-context, having the PDPs
45 * contained there mean you don't need to do a ppgtt->switch_mm yourself,
46 * instead, the GPU will do it for you on the context switch.
47 *
48 * But, what about the ringbuffer control registers (head, tail, etc..)?
49 * shouldn't we just need a set of those per engine command streamer? This is
50 * where the name "Logical Rings" starts to make sense: by virtualizing the
51 * rings, the engine cs shifts to a new "ring buffer" with every context
52 * switch. When you want to submit a workload to the GPU you: A) choose your
53 * context, B) find its appropriate virtualized ring, C) write commands to it
54 * and then, finally, D) tell the GPU to switch to that context.
55 *
56 * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch
57 * to a contexts is via a context execution list, ergo "Execlists".
58 *
59 * LRC implementation:
60 * Regarding the creation of contexts, we have:
61 *
62 * - One global default context.
63 * - One local default context for each opened fd.
64 * - One local extra context for each context create ioctl call.
65 *
66 * Now that ringbuffers belong per-context (and not per-engine, like before)
67 * and that contexts are uniquely tied to a given engine (and not reusable,
68 * like before) we need:
69 *
70 * - One ringbuffer per-engine inside each context.
71 * - One backing object per-engine inside each context.
72 *
73 * The global default context starts its life with these new objects fully
74 * allocated and populated. The local default context for each opened fd is
75 * more complex, because we don't know at creation time which engine is going
76 * to use them. To handle this, we have implemented a deferred creation of LR
77 * contexts:
78 *
79 * The local context starts its life as a hollow or blank holder, that only
80 * gets populated for a given engine once we receive an execbuffer. If later
81 * on we receive another execbuffer ioctl for the same context but a different
82 * engine, we allocate/populate a new ringbuffer and context backing object and
83 * so on.
84 *
85 * Finally, regarding local contexts created using the ioctl call: as they are
86 * only allowed with the render ring, we can allocate & populate them right
87 * away (no need to defer anything, at least for now).
88 *
89 * Execlists implementation:
Oscar Mateob20385f2014-07-24 17:04:10 +010090 * Execlists are the new method by which, on gen8+ hardware, workloads are
91 * submitted for execution (as opposed to the legacy, ringbuffer-based, method).
Oscar Mateo73e4d072014-07-24 17:04:48 +010092 * This method works as follows:
93 *
94 * When a request is committed, its commands (the BB start and any leading or
95 * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer
96 * for the appropriate context. The tail pointer in the hardware context is not
97 * updated at this time, but instead, kept by the driver in the ringbuffer
98 * structure. A structure representing this request is added to a request queue
99 * for the appropriate engine: this structure contains a copy of the context's
100 * tail after the request was written to the ring buffer and a pointer to the
101 * context itself.
102 *
103 * If the engine's request queue was empty before the request was added, the
104 * queue is processed immediately. Otherwise the queue will be processed during
105 * a context switch interrupt. In any case, elements on the queue will get sent
106 * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a
107 * globally unique 20-bits submission ID.
108 *
109 * When execution of a request completes, the GPU updates the context status
110 * buffer with a context complete event and generates a context switch interrupt.
111 * During the interrupt handling, the driver examines the events in the buffer:
112 * for each context complete event, if the announced ID matches that on the head
113 * of the request queue, then that request is retired and removed from the queue.
114 *
115 * After processing, if any requests were retired and the queue is not empty
116 * then a new execution list can be submitted. The two requests at the front of
117 * the queue are next to be submitted but since a context may not occur twice in
118 * an execution list, if subsequent requests have the same ID as the first then
119 * the two requests must be combined. This is done simply by discarding requests
120 * at the head of the queue until either only one requests is left (in which case
121 * we use a NULL second context) or the first two requests have unique IDs.
122 *
123 * By always executing the first two requests in the queue the driver ensures
124 * that the GPU is kept as busy as possible. In the case where a single context
125 * completes but a second context is still executing, the request for this second
126 * context will be at the head of the queue when we remove the first one. This
127 * request will then be resubmitted along with a new request for a different context,
128 * which will cause the hardware to continue executing the second request and queue
129 * the new request (the GPU detects the condition of a context getting preempted
130 * with the same context and optimizes the context switch flow by not doing
131 * preemption, but just sampling the new tail pointer).
132 *
Oscar Mateob20385f2014-07-24 17:04:10 +0100133 */
134
135#include <drm/drmP.h>
136#include <drm/i915_drm.h>
137#include "i915_drv.h"
Oscar Mateo127f1002014-07-24 17:04:11 +0100138
Michael H. Nguyen468c6812014-11-13 17:51:49 +0000139#define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE)
Oscar Mateo8c8579172014-07-24 17:04:14 +0100140#define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE)
141#define GEN8_LR_CONTEXT_OTHER_SIZE (2 * PAGE_SIZE)
142
Thomas Daniele981e7b2014-07-24 17:04:39 +0100143#define RING_EXECLIST_QFULL (1 << 0x2)
144#define RING_EXECLIST1_VALID (1 << 0x3)
145#define RING_EXECLIST0_VALID (1 << 0x4)
146#define RING_EXECLIST_ACTIVE_STATUS (3 << 0xE)
147#define RING_EXECLIST1_ACTIVE (1 << 0x11)
148#define RING_EXECLIST0_ACTIVE (1 << 0x12)
149
150#define GEN8_CTX_STATUS_IDLE_ACTIVE (1 << 0)
151#define GEN8_CTX_STATUS_PREEMPTED (1 << 1)
152#define GEN8_CTX_STATUS_ELEMENT_SWITCH (1 << 2)
153#define GEN8_CTX_STATUS_ACTIVE_IDLE (1 << 3)
154#define GEN8_CTX_STATUS_COMPLETE (1 << 4)
155#define GEN8_CTX_STATUS_LITE_RESTORE (1 << 15)
Oscar Mateo8670d6f2014-07-24 17:04:17 +0100156
157#define CTX_LRI_HEADER_0 0x01
158#define CTX_CONTEXT_CONTROL 0x02
159#define CTX_RING_HEAD 0x04
160#define CTX_RING_TAIL 0x06
161#define CTX_RING_BUFFER_START 0x08
162#define CTX_RING_BUFFER_CONTROL 0x0a
163#define CTX_BB_HEAD_U 0x0c
164#define CTX_BB_HEAD_L 0x0e
165#define CTX_BB_STATE 0x10
166#define CTX_SECOND_BB_HEAD_U 0x12
167#define CTX_SECOND_BB_HEAD_L 0x14
168#define CTX_SECOND_BB_STATE 0x16
169#define CTX_BB_PER_CTX_PTR 0x18
170#define CTX_RCS_INDIRECT_CTX 0x1a
171#define CTX_RCS_INDIRECT_CTX_OFFSET 0x1c
172#define CTX_LRI_HEADER_1 0x21
173#define CTX_CTX_TIMESTAMP 0x22
174#define CTX_PDP3_UDW 0x24
175#define CTX_PDP3_LDW 0x26
176#define CTX_PDP2_UDW 0x28
177#define CTX_PDP2_LDW 0x2a
178#define CTX_PDP1_UDW 0x2c
179#define CTX_PDP1_LDW 0x2e
180#define CTX_PDP0_UDW 0x30
181#define CTX_PDP0_LDW 0x32
182#define CTX_LRI_HEADER_2 0x41
183#define CTX_R_PWR_CLK_STATE 0x42
184#define CTX_GPGPU_CSR_BASE_ADDRESS 0x44
185
Ben Widawsky84b790f2014-07-24 17:04:36 +0100186#define GEN8_CTX_VALID (1<<0)
187#define GEN8_CTX_FORCE_PD_RESTORE (1<<1)
188#define GEN8_CTX_FORCE_RESTORE (1<<2)
189#define GEN8_CTX_L3LLC_COHERENT (1<<5)
190#define GEN8_CTX_PRIVILEGE (1<<8)
191enum {
192 ADVANCED_CONTEXT = 0,
193 LEGACY_CONTEXT,
194 ADVANCED_AD_CONTEXT,
195 LEGACY_64B_CONTEXT
196};
197#define GEN8_CTX_MODE_SHIFT 3
198enum {
199 FAULT_AND_HANG = 0,
200 FAULT_AND_HALT, /* Debug only */
201 FAULT_AND_STREAM,
202 FAULT_AND_CONTINUE /* Unsupported */
203};
204#define GEN8_CTX_ID_SHIFT 32
205
Thomas Daniel7ba717c2014-11-13 10:28:56 +0000206static int intel_lr_context_pin(struct intel_engine_cs *ring,
207 struct intel_context *ctx);
208
Oscar Mateo73e4d072014-07-24 17:04:48 +0100209/**
210 * intel_sanitize_enable_execlists() - sanitize i915.enable_execlists
211 * @dev: DRM device.
212 * @enable_execlists: value of i915.enable_execlists module parameter.
213 *
214 * Only certain platforms support Execlists (the prerequisites being
Thomas Daniel27401d12014-12-11 12:48:35 +0000215 * support for Logical Ring Contexts and Aliasing PPGTT or better).
Oscar Mateo73e4d072014-07-24 17:04:48 +0100216 *
217 * Return: 1 if Execlists is supported and has to be enabled.
218 */
Oscar Mateo127f1002014-07-24 17:04:11 +0100219int intel_sanitize_enable_execlists(struct drm_device *dev, int enable_execlists)
220{
Daniel Vetterbd84b1e2014-08-11 15:57:57 +0200221 WARN_ON(i915.enable_ppgtt == -1);
222
Damien Lespiau70ee45e2014-11-14 15:05:59 +0000223 if (INTEL_INFO(dev)->gen >= 9)
224 return 1;
225
Oscar Mateo127f1002014-07-24 17:04:11 +0100226 if (enable_execlists == 0)
227 return 0;
228
Oscar Mateo14bf9932014-07-24 17:04:34 +0100229 if (HAS_LOGICAL_RING_CONTEXTS(dev) && USES_PPGTT(dev) &&
230 i915.use_mmio_flip >= 0)
Oscar Mateo127f1002014-07-24 17:04:11 +0100231 return 1;
232
233 return 0;
234}
Oscar Mateoede7d422014-07-24 17:04:12 +0100235
Oscar Mateo73e4d072014-07-24 17:04:48 +0100236/**
237 * intel_execlists_ctx_id() - get the Execlists Context ID
238 * @ctx_obj: Logical Ring Context backing object.
239 *
240 * Do not confuse with ctx->id! Unfortunately we have a name overload
241 * here: the old context ID we pass to userspace as a handler so that
242 * they can refer to a context, and the new context ID we pass to the
243 * ELSP so that the GPU can inform us of the context status via
244 * interrupts.
245 *
246 * Return: 20-bits globally unique context ID.
247 */
Ben Widawsky84b790f2014-07-24 17:04:36 +0100248u32 intel_execlists_ctx_id(struct drm_i915_gem_object *ctx_obj)
249{
250 u32 lrca = i915_gem_obj_ggtt_offset(ctx_obj);
251
252 /* LRCA is required to be 4K aligned so the more significant 20 bits
253 * are globally unique */
254 return lrca >> 12;
255}
256
257static uint64_t execlists_ctx_descriptor(struct drm_i915_gem_object *ctx_obj)
258{
259 uint64_t desc;
260 uint64_t lrca = i915_gem_obj_ggtt_offset(ctx_obj);
Michel Thierryacdd8842014-07-24 17:04:38 +0100261
262 WARN_ON(lrca & 0xFFFFFFFF00000FFFULL);
Ben Widawsky84b790f2014-07-24 17:04:36 +0100263
264 desc = GEN8_CTX_VALID;
265 desc |= LEGACY_CONTEXT << GEN8_CTX_MODE_SHIFT;
266 desc |= GEN8_CTX_L3LLC_COHERENT;
267 desc |= GEN8_CTX_PRIVILEGE;
268 desc |= lrca;
269 desc |= (u64)intel_execlists_ctx_id(ctx_obj) << GEN8_CTX_ID_SHIFT;
270
271 /* TODO: WaDisableLiteRestore when we start using semaphore
272 * signalling between Command Streamers */
273 /* desc |= GEN8_CTX_FORCE_RESTORE; */
274
275 return desc;
276}
277
278static void execlists_elsp_write(struct intel_engine_cs *ring,
279 struct drm_i915_gem_object *ctx_obj0,
280 struct drm_i915_gem_object *ctx_obj1)
281{
Tvrtko Ursulin6e7cc472014-11-13 17:51:51 +0000282 struct drm_device *dev = ring->dev;
283 struct drm_i915_private *dev_priv = dev->dev_private;
Ben Widawsky84b790f2014-07-24 17:04:36 +0100284 uint64_t temp = 0;
285 uint32_t desc[4];
286
287 /* XXX: You must always write both descriptors in the order below. */
288 if (ctx_obj1)
289 temp = execlists_ctx_descriptor(ctx_obj1);
290 else
291 temp = 0;
292 desc[1] = (u32)(temp >> 32);
293 desc[0] = (u32)temp;
294
295 temp = execlists_ctx_descriptor(ctx_obj0);
296 desc[3] = (u32)(temp >> 32);
297 desc[2] = (u32)temp;
298
Mika Kuoppala59bad942015-01-16 11:34:40 +0200299 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
Ben Widawsky84b790f2014-07-24 17:04:36 +0100300 I915_WRITE(RING_ELSP(ring), desc[1]);
301 I915_WRITE(RING_ELSP(ring), desc[0]);
302 I915_WRITE(RING_ELSP(ring), desc[3]);
Chris Wilson6daccb02015-01-16 11:34:35 +0200303
Ben Widawsky84b790f2014-07-24 17:04:36 +0100304 /* The context is automatically loaded after the following */
305 I915_WRITE(RING_ELSP(ring), desc[2]);
306
307 /* ELSP is a wo register, so use another nearby reg for posting instead */
308 POSTING_READ(RING_EXECLIST_STATUS(ring));
Mika Kuoppala59bad942015-01-16 11:34:40 +0200309 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
Ben Widawsky84b790f2014-07-24 17:04:36 +0100310}
311
Thomas Daniel7ba717c2014-11-13 10:28:56 +0000312static int execlists_update_context(struct drm_i915_gem_object *ctx_obj,
313 struct drm_i915_gem_object *ring_obj,
314 u32 tail)
Oscar Mateoae1250b2014-07-24 17:04:37 +0100315{
316 struct page *page;
317 uint32_t *reg_state;
318
319 page = i915_gem_object_get_page(ctx_obj, 1);
320 reg_state = kmap_atomic(page);
321
322 reg_state[CTX_RING_TAIL+1] = tail;
Thomas Daniel7ba717c2014-11-13 10:28:56 +0000323 reg_state[CTX_RING_BUFFER_START+1] = i915_gem_obj_ggtt_offset(ring_obj);
Oscar Mateoae1250b2014-07-24 17:04:37 +0100324
325 kunmap_atomic(reg_state);
326
327 return 0;
328}
329
Dave Gordoncd0707c2014-10-30 15:41:56 +0000330static void execlists_submit_contexts(struct intel_engine_cs *ring,
331 struct intel_context *to0, u32 tail0,
332 struct intel_context *to1, u32 tail1)
Ben Widawsky84b790f2014-07-24 17:04:36 +0100333{
Thomas Daniel7ba717c2014-11-13 10:28:56 +0000334 struct drm_i915_gem_object *ctx_obj0 = to0->engine[ring->id].state;
335 struct intel_ringbuffer *ringbuf0 = to0->engine[ring->id].ringbuf;
Ben Widawsky84b790f2014-07-24 17:04:36 +0100336 struct drm_i915_gem_object *ctx_obj1 = NULL;
Thomas Daniel7ba717c2014-11-13 10:28:56 +0000337 struct intel_ringbuffer *ringbuf1 = NULL;
Ben Widawsky84b790f2014-07-24 17:04:36 +0100338
Ben Widawsky84b790f2014-07-24 17:04:36 +0100339 BUG_ON(!ctx_obj0);
Michel Thierryacdd8842014-07-24 17:04:38 +0100340 WARN_ON(!i915_gem_obj_is_pinned(ctx_obj0));
Thomas Daniel7ba717c2014-11-13 10:28:56 +0000341 WARN_ON(!i915_gem_obj_is_pinned(ringbuf0->obj));
Ben Widawsky84b790f2014-07-24 17:04:36 +0100342
Thomas Daniel7ba717c2014-11-13 10:28:56 +0000343 execlists_update_context(ctx_obj0, ringbuf0->obj, tail0);
Oscar Mateoae1250b2014-07-24 17:04:37 +0100344
Ben Widawsky84b790f2014-07-24 17:04:36 +0100345 if (to1) {
Thomas Daniel7ba717c2014-11-13 10:28:56 +0000346 ringbuf1 = to1->engine[ring->id].ringbuf;
Ben Widawsky84b790f2014-07-24 17:04:36 +0100347 ctx_obj1 = to1->engine[ring->id].state;
348 BUG_ON(!ctx_obj1);
Michel Thierryacdd8842014-07-24 17:04:38 +0100349 WARN_ON(!i915_gem_obj_is_pinned(ctx_obj1));
Thomas Daniel7ba717c2014-11-13 10:28:56 +0000350 WARN_ON(!i915_gem_obj_is_pinned(ringbuf1->obj));
Oscar Mateoae1250b2014-07-24 17:04:37 +0100351
Thomas Daniel7ba717c2014-11-13 10:28:56 +0000352 execlists_update_context(ctx_obj1, ringbuf1->obj, tail1);
Ben Widawsky84b790f2014-07-24 17:04:36 +0100353 }
354
355 execlists_elsp_write(ring, ctx_obj0, ctx_obj1);
Ben Widawsky84b790f2014-07-24 17:04:36 +0100356}
357
Michel Thierryacdd8842014-07-24 17:04:38 +0100358static void execlists_context_unqueue(struct intel_engine_cs *ring)
359{
Nick Hoath6d3d8272015-01-15 13:10:39 +0000360 struct drm_i915_gem_request *req0 = NULL, *req1 = NULL;
361 struct drm_i915_gem_request *cursor = NULL, *tmp = NULL;
Thomas Daniele981e7b2014-07-24 17:04:39 +0100362
363 assert_spin_locked(&ring->execlist_lock);
Michel Thierryacdd8842014-07-24 17:04:38 +0100364
365 if (list_empty(&ring->execlist_queue))
366 return;
367
368 /* Try to read in pairs */
369 list_for_each_entry_safe(cursor, tmp, &ring->execlist_queue,
370 execlist_link) {
371 if (!req0) {
372 req0 = cursor;
Nick Hoath6d3d8272015-01-15 13:10:39 +0000373 } else if (req0->ctx == cursor->ctx) {
Michel Thierryacdd8842014-07-24 17:04:38 +0100374 /* Same ctx: ignore first request, as second request
375 * will update tail past first request's workload */
Oscar Mateoe1fee722014-07-24 17:04:40 +0100376 cursor->elsp_submitted = req0->elsp_submitted;
Michel Thierryacdd8842014-07-24 17:04:38 +0100377 list_del(&req0->execlist_link);
Thomas Danielc86ee3a92014-11-13 10:27:05 +0000378 list_add_tail(&req0->execlist_link,
379 &ring->execlist_retired_req_list);
Michel Thierryacdd8842014-07-24 17:04:38 +0100380 req0 = cursor;
381 } else {
382 req1 = cursor;
383 break;
384 }
385 }
386
Oscar Mateoe1fee722014-07-24 17:04:40 +0100387 WARN_ON(req1 && req1->elsp_submitted);
388
Nick Hoath6d3d8272015-01-15 13:10:39 +0000389 execlists_submit_contexts(ring, req0->ctx, req0->tail,
390 req1 ? req1->ctx : NULL,
391 req1 ? req1->tail : 0);
Oscar Mateoe1fee722014-07-24 17:04:40 +0100392
393 req0->elsp_submitted++;
394 if (req1)
395 req1->elsp_submitted++;
Michel Thierryacdd8842014-07-24 17:04:38 +0100396}
397
Thomas Daniele981e7b2014-07-24 17:04:39 +0100398static bool execlists_check_remove_request(struct intel_engine_cs *ring,
399 u32 request_id)
400{
Nick Hoath6d3d8272015-01-15 13:10:39 +0000401 struct drm_i915_gem_request *head_req;
Thomas Daniele981e7b2014-07-24 17:04:39 +0100402
403 assert_spin_locked(&ring->execlist_lock);
404
405 head_req = list_first_entry_or_null(&ring->execlist_queue,
Nick Hoath6d3d8272015-01-15 13:10:39 +0000406 struct drm_i915_gem_request,
Thomas Daniele981e7b2014-07-24 17:04:39 +0100407 execlist_link);
408
409 if (head_req != NULL) {
410 struct drm_i915_gem_object *ctx_obj =
Nick Hoath6d3d8272015-01-15 13:10:39 +0000411 head_req->ctx->engine[ring->id].state;
Thomas Daniele981e7b2014-07-24 17:04:39 +0100412 if (intel_execlists_ctx_id(ctx_obj) == request_id) {
Oscar Mateoe1fee722014-07-24 17:04:40 +0100413 WARN(head_req->elsp_submitted == 0,
414 "Never submitted head request\n");
415
416 if (--head_req->elsp_submitted <= 0) {
417 list_del(&head_req->execlist_link);
Thomas Danielc86ee3a92014-11-13 10:27:05 +0000418 list_add_tail(&head_req->execlist_link,
419 &ring->execlist_retired_req_list);
Oscar Mateoe1fee722014-07-24 17:04:40 +0100420 return true;
421 }
Thomas Daniele981e7b2014-07-24 17:04:39 +0100422 }
423 }
424
425 return false;
426}
427
Oscar Mateo73e4d072014-07-24 17:04:48 +0100428/**
Daniel Vetter3f7531c2014-12-10 17:41:43 +0100429 * intel_lrc_irq_handler() - handle Context Switch interrupts
Oscar Mateo73e4d072014-07-24 17:04:48 +0100430 * @ring: Engine Command Streamer to handle.
431 *
432 * Check the unread Context Status Buffers and manage the submission of new
433 * contexts to the ELSP accordingly.
434 */
Daniel Vetter3f7531c2014-12-10 17:41:43 +0100435void intel_lrc_irq_handler(struct intel_engine_cs *ring)
Thomas Daniele981e7b2014-07-24 17:04:39 +0100436{
437 struct drm_i915_private *dev_priv = ring->dev->dev_private;
438 u32 status_pointer;
439 u8 read_pointer;
440 u8 write_pointer;
441 u32 status;
442 u32 status_id;
443 u32 submit_contexts = 0;
444
445 status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(ring));
446
447 read_pointer = ring->next_context_status_buffer;
448 write_pointer = status_pointer & 0x07;
449 if (read_pointer > write_pointer)
450 write_pointer += 6;
451
452 spin_lock(&ring->execlist_lock);
453
454 while (read_pointer < write_pointer) {
455 read_pointer++;
456 status = I915_READ(RING_CONTEXT_STATUS_BUF(ring) +
457 (read_pointer % 6) * 8);
458 status_id = I915_READ(RING_CONTEXT_STATUS_BUF(ring) +
459 (read_pointer % 6) * 8 + 4);
460
Oscar Mateoe1fee722014-07-24 17:04:40 +0100461 if (status & GEN8_CTX_STATUS_PREEMPTED) {
462 if (status & GEN8_CTX_STATUS_LITE_RESTORE) {
463 if (execlists_check_remove_request(ring, status_id))
464 WARN(1, "Lite Restored request removed from queue\n");
465 } else
466 WARN(1, "Preemption without Lite Restore\n");
467 }
468
469 if ((status & GEN8_CTX_STATUS_ACTIVE_IDLE) ||
470 (status & GEN8_CTX_STATUS_ELEMENT_SWITCH)) {
Thomas Daniele981e7b2014-07-24 17:04:39 +0100471 if (execlists_check_remove_request(ring, status_id))
472 submit_contexts++;
473 }
474 }
475
476 if (submit_contexts != 0)
477 execlists_context_unqueue(ring);
478
479 spin_unlock(&ring->execlist_lock);
480
481 WARN(submit_contexts > 2, "More than two context complete events?\n");
482 ring->next_context_status_buffer = write_pointer % 6;
483
484 I915_WRITE(RING_CONTEXT_STATUS_PTR(ring),
485 ((u32)ring->next_context_status_buffer & 0x07) << 8);
486}
487
Michel Thierryacdd8842014-07-24 17:04:38 +0100488static int execlists_context_queue(struct intel_engine_cs *ring,
489 struct intel_context *to,
Nick Hoath2d129552015-01-15 13:10:36 +0000490 u32 tail,
491 struct drm_i915_gem_request *request)
Michel Thierryacdd8842014-07-24 17:04:38 +0100492{
Nick Hoath6d3d8272015-01-15 13:10:39 +0000493 struct drm_i915_gem_request *cursor;
Thomas Daniele981e7b2014-07-24 17:04:39 +0100494 struct drm_i915_private *dev_priv = ring->dev->dev_private;
Michel Thierryacdd8842014-07-24 17:04:38 +0100495 unsigned long flags;
Oscar Mateof1ad5a12014-07-24 17:04:41 +0100496 int num_elements = 0;
Michel Thierryacdd8842014-07-24 17:04:38 +0100497
Thomas Daniel7ba717c2014-11-13 10:28:56 +0000498 if (to != ring->default_context)
499 intel_lr_context_pin(ring, to);
500
Nick Hoath2d129552015-01-15 13:10:36 +0000501 if (!request) {
502 /*
503 * If there isn't a request associated with this submission,
504 * create one as a temporary holder.
505 */
Nick Hoath2d129552015-01-15 13:10:36 +0000506 request = kzalloc(sizeof(*request), GFP_KERNEL);
507 if (request == NULL)
508 return -ENOMEM;
Nick Hoath2d129552015-01-15 13:10:36 +0000509 request->ring = ring;
Nick Hoath6d3d8272015-01-15 13:10:39 +0000510 request->ctx = to;
Nick Hoathb3a38992015-02-19 16:30:47 +0000511 kref_init(&request->ref);
512 request->uniq = dev_priv->request_uniq++;
513 i915_gem_context_reference(request->ctx);
Nick Hoath21076372015-01-15 13:10:38 +0000514 } else {
Nick Hoathb3a38992015-02-19 16:30:47 +0000515 i915_gem_request_reference(request);
Nick Hoath21076372015-01-15 13:10:38 +0000516 WARN_ON(to != request->ctx);
Nick Hoath2d129552015-01-15 13:10:36 +0000517 }
Nick Hoath72f95af2015-01-15 13:10:37 +0000518 request->tail = tail;
Nick Hoath2d129552015-01-15 13:10:36 +0000519
Thomas Daniele981e7b2014-07-24 17:04:39 +0100520 intel_runtime_pm_get(dev_priv);
Michel Thierryacdd8842014-07-24 17:04:38 +0100521
522 spin_lock_irqsave(&ring->execlist_lock, flags);
523
Oscar Mateof1ad5a12014-07-24 17:04:41 +0100524 list_for_each_entry(cursor, &ring->execlist_queue, execlist_link)
525 if (++num_elements > 2)
526 break;
527
528 if (num_elements > 2) {
Nick Hoath6d3d8272015-01-15 13:10:39 +0000529 struct drm_i915_gem_request *tail_req;
Oscar Mateof1ad5a12014-07-24 17:04:41 +0100530
531 tail_req = list_last_entry(&ring->execlist_queue,
Nick Hoath6d3d8272015-01-15 13:10:39 +0000532 struct drm_i915_gem_request,
Oscar Mateof1ad5a12014-07-24 17:04:41 +0100533 execlist_link);
534
Nick Hoath6d3d8272015-01-15 13:10:39 +0000535 if (to == tail_req->ctx) {
Oscar Mateof1ad5a12014-07-24 17:04:41 +0100536 WARN(tail_req->elsp_submitted != 0,
Thomas Daniel7ba717c2014-11-13 10:28:56 +0000537 "More than 2 already-submitted reqs queued\n");
Oscar Mateof1ad5a12014-07-24 17:04:41 +0100538 list_del(&tail_req->execlist_link);
Thomas Danielc86ee3a92014-11-13 10:27:05 +0000539 list_add_tail(&tail_req->execlist_link,
540 &ring->execlist_retired_req_list);
Oscar Mateof1ad5a12014-07-24 17:04:41 +0100541 }
542 }
543
Nick Hoath6d3d8272015-01-15 13:10:39 +0000544 list_add_tail(&request->execlist_link, &ring->execlist_queue);
Oscar Mateof1ad5a12014-07-24 17:04:41 +0100545 if (num_elements == 0)
Michel Thierryacdd8842014-07-24 17:04:38 +0100546 execlists_context_unqueue(ring);
547
548 spin_unlock_irqrestore(&ring->execlist_lock, flags);
549
550 return 0;
551}
552
Nick Hoath21076372015-01-15 13:10:38 +0000553static int logical_ring_invalidate_all_caches(struct intel_ringbuffer *ringbuf,
554 struct intel_context *ctx)
Oscar Mateoba8b7cc2014-07-24 17:04:33 +0100555{
556 struct intel_engine_cs *ring = ringbuf->ring;
557 uint32_t flush_domains;
558 int ret;
559
560 flush_domains = 0;
561 if (ring->gpu_caches_dirty)
562 flush_domains = I915_GEM_GPU_DOMAINS;
563
Nick Hoath21076372015-01-15 13:10:38 +0000564 ret = ring->emit_flush(ringbuf, ctx,
565 I915_GEM_GPU_DOMAINS, flush_domains);
Oscar Mateoba8b7cc2014-07-24 17:04:33 +0100566 if (ret)
567 return ret;
568
569 ring->gpu_caches_dirty = false;
570 return 0;
571}
572
573static int execlists_move_to_gpu(struct intel_ringbuffer *ringbuf,
Nick Hoath21076372015-01-15 13:10:38 +0000574 struct intel_context *ctx,
Oscar Mateoba8b7cc2014-07-24 17:04:33 +0100575 struct list_head *vmas)
576{
577 struct intel_engine_cs *ring = ringbuf->ring;
578 struct i915_vma *vma;
579 uint32_t flush_domains = 0;
580 bool flush_chipset = false;
581 int ret;
582
583 list_for_each_entry(vma, vmas, exec_list) {
584 struct drm_i915_gem_object *obj = vma->obj;
585
586 ret = i915_gem_object_sync(obj, ring);
587 if (ret)
588 return ret;
589
590 if (obj->base.write_domain & I915_GEM_DOMAIN_CPU)
591 flush_chipset |= i915_gem_clflush_object(obj, false);
592
593 flush_domains |= obj->base.write_domain;
594 }
595
596 if (flush_domains & I915_GEM_DOMAIN_GTT)
597 wmb();
598
599 /* Unconditionally invalidate gpu caches and ensure that we do flush
600 * any residual writes from the previous batch.
601 */
Nick Hoath21076372015-01-15 13:10:38 +0000602 return logical_ring_invalidate_all_caches(ringbuf, ctx);
Oscar Mateoba8b7cc2014-07-24 17:04:33 +0100603}
604
Oscar Mateo73e4d072014-07-24 17:04:48 +0100605/**
606 * execlists_submission() - submit a batchbuffer for execution, Execlists style
607 * @dev: DRM device.
608 * @file: DRM file.
609 * @ring: Engine Command Streamer to submit to.
610 * @ctx: Context to employ for this submission.
611 * @args: execbuffer call arguments.
612 * @vmas: list of vmas.
613 * @batch_obj: the batchbuffer to submit.
614 * @exec_start: batchbuffer start virtual address pointer.
615 * @flags: translated execbuffer call flags.
616 *
617 * This is the evil twin version of i915_gem_ringbuffer_submission. It abstracts
618 * away the submission details of the execbuffer ioctl call.
619 *
620 * Return: non-zero if the submission fails.
621 */
Oscar Mateo454afeb2014-07-24 17:04:22 +0100622int intel_execlists_submission(struct drm_device *dev, struct drm_file *file,
623 struct intel_engine_cs *ring,
624 struct intel_context *ctx,
625 struct drm_i915_gem_execbuffer2 *args,
626 struct list_head *vmas,
627 struct drm_i915_gem_object *batch_obj,
628 u64 exec_start, u32 flags)
629{
Oscar Mateoba8b7cc2014-07-24 17:04:33 +0100630 struct drm_i915_private *dev_priv = dev->dev_private;
631 struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf;
632 int instp_mode;
633 u32 instp_mask;
634 int ret;
635
636 instp_mode = args->flags & I915_EXEC_CONSTANTS_MASK;
637 instp_mask = I915_EXEC_CONSTANTS_MASK;
638 switch (instp_mode) {
639 case I915_EXEC_CONSTANTS_REL_GENERAL:
640 case I915_EXEC_CONSTANTS_ABSOLUTE:
641 case I915_EXEC_CONSTANTS_REL_SURFACE:
642 if (instp_mode != 0 && ring != &dev_priv->ring[RCS]) {
643 DRM_DEBUG("non-0 rel constants mode on non-RCS\n");
644 return -EINVAL;
645 }
646
647 if (instp_mode != dev_priv->relative_constants_mode) {
648 if (instp_mode == I915_EXEC_CONSTANTS_REL_SURFACE) {
649 DRM_DEBUG("rel surface constants mode invalid on gen5+\n");
650 return -EINVAL;
651 }
652
653 /* The HW changed the meaning on this bit on gen6 */
654 instp_mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE;
655 }
656 break;
657 default:
658 DRM_DEBUG("execbuf with unknown constants: %d\n", instp_mode);
659 return -EINVAL;
660 }
661
662 if (args->num_cliprects != 0) {
663 DRM_DEBUG("clip rectangles are only valid on pre-gen5\n");
664 return -EINVAL;
665 } else {
666 if (args->DR4 == 0xffffffff) {
667 DRM_DEBUG("UXA submitting garbage DR4, fixing up\n");
668 args->DR4 = 0;
669 }
670
671 if (args->DR1 || args->DR4 || args->cliprects_ptr) {
672 DRM_DEBUG("0 cliprects but dirt in cliprects fields\n");
673 return -EINVAL;
674 }
675 }
676
677 if (args->flags & I915_EXEC_GEN7_SOL_RESET) {
678 DRM_DEBUG("sol reset is gen7 only\n");
679 return -EINVAL;
680 }
681
Nick Hoath21076372015-01-15 13:10:38 +0000682 ret = execlists_move_to_gpu(ringbuf, ctx, vmas);
Oscar Mateoba8b7cc2014-07-24 17:04:33 +0100683 if (ret)
684 return ret;
685
686 if (ring == &dev_priv->ring[RCS] &&
687 instp_mode != dev_priv->relative_constants_mode) {
Nick Hoath21076372015-01-15 13:10:38 +0000688 ret = intel_logical_ring_begin(ringbuf, ctx, 4);
Oscar Mateoba8b7cc2014-07-24 17:04:33 +0100689 if (ret)
690 return ret;
691
692 intel_logical_ring_emit(ringbuf, MI_NOOP);
693 intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(1));
694 intel_logical_ring_emit(ringbuf, INSTPM);
695 intel_logical_ring_emit(ringbuf, instp_mask << 16 | instp_mode);
696 intel_logical_ring_advance(ringbuf);
697
698 dev_priv->relative_constants_mode = instp_mode;
699 }
700
Nick Hoath21076372015-01-15 13:10:38 +0000701 ret = ring->emit_bb_start(ringbuf, ctx, exec_start, flags);
Oscar Mateoba8b7cc2014-07-24 17:04:33 +0100702 if (ret)
703 return ret;
704
705 i915_gem_execbuffer_move_to_active(vmas, ring);
706 i915_gem_execbuffer_retire_commands(dev, file, ring, batch_obj);
707
Oscar Mateo454afeb2014-07-24 17:04:22 +0100708 return 0;
709}
710
Thomas Danielc86ee3a92014-11-13 10:27:05 +0000711void intel_execlists_retire_requests(struct intel_engine_cs *ring)
712{
Nick Hoath6d3d8272015-01-15 13:10:39 +0000713 struct drm_i915_gem_request *req, *tmp;
Thomas Danielc86ee3a92014-11-13 10:27:05 +0000714 struct drm_i915_private *dev_priv = ring->dev->dev_private;
715 unsigned long flags;
716 struct list_head retired_list;
717
718 WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex));
719 if (list_empty(&ring->execlist_retired_req_list))
720 return;
721
722 INIT_LIST_HEAD(&retired_list);
723 spin_lock_irqsave(&ring->execlist_lock, flags);
724 list_replace_init(&ring->execlist_retired_req_list, &retired_list);
725 spin_unlock_irqrestore(&ring->execlist_lock, flags);
726
727 list_for_each_entry_safe(req, tmp, &retired_list, execlist_link) {
Nick Hoath6d3d8272015-01-15 13:10:39 +0000728 struct intel_context *ctx = req->ctx;
Thomas Daniel7ba717c2014-11-13 10:28:56 +0000729 struct drm_i915_gem_object *ctx_obj =
730 ctx->engine[ring->id].state;
731
732 if (ctx_obj && (ctx != ring->default_context))
733 intel_lr_context_unpin(ring, ctx);
Thomas Danielc86ee3a92014-11-13 10:27:05 +0000734 intel_runtime_pm_put(dev_priv);
Thomas Danielc86ee3a92014-11-13 10:27:05 +0000735 list_del(&req->execlist_link);
Nick Hoathf8210792015-01-29 16:55:07 +0000736 i915_gem_request_unreference(req);
Thomas Danielc86ee3a92014-11-13 10:27:05 +0000737 }
738}
739
Oscar Mateo454afeb2014-07-24 17:04:22 +0100740void intel_logical_ring_stop(struct intel_engine_cs *ring)
741{
Oscar Mateo9832b9d2014-07-24 17:04:30 +0100742 struct drm_i915_private *dev_priv = ring->dev->dev_private;
743 int ret;
744
745 if (!intel_ring_initialized(ring))
746 return;
747
748 ret = intel_ring_idle(ring);
749 if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error))
750 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
751 ring->name, ret);
752
753 /* TODO: Is this correct with Execlists enabled? */
754 I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING));
755 if (wait_for_atomic((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) {
756 DRM_ERROR("%s :timed out trying to stop ring\n", ring->name);
757 return;
758 }
759 I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING));
Oscar Mateo454afeb2014-07-24 17:04:22 +0100760}
761
Nick Hoath21076372015-01-15 13:10:38 +0000762int logical_ring_flush_all_caches(struct intel_ringbuffer *ringbuf,
763 struct intel_context *ctx)
Oscar Mateo48e29f52014-07-24 17:04:29 +0100764{
765 struct intel_engine_cs *ring = ringbuf->ring;
766 int ret;
767
768 if (!ring->gpu_caches_dirty)
769 return 0;
770
Nick Hoath21076372015-01-15 13:10:38 +0000771 ret = ring->emit_flush(ringbuf, ctx, 0, I915_GEM_GPU_DOMAINS);
Oscar Mateo48e29f52014-07-24 17:04:29 +0100772 if (ret)
773 return ret;
774
775 ring->gpu_caches_dirty = false;
776 return 0;
777}
778
Oscar Mateo73e4d072014-07-24 17:04:48 +0100779/**
780 * intel_logical_ring_advance_and_submit() - advance the tail and submit the workload
781 * @ringbuf: Logical Ringbuffer to advance.
782 *
783 * The tail is updated in our logical ringbuffer struct, not in the actual context. What
784 * really happens during submission is that the context and current tail will be placed
785 * on a queue waiting for the ELSP to be ready to accept a new context submission. At that
786 * point, the tail *inside* the context is updated and the ELSP written to.
787 */
Nick Hoath2d129552015-01-15 13:10:36 +0000788void intel_logical_ring_advance_and_submit(struct intel_ringbuffer *ringbuf,
Nick Hoath21076372015-01-15 13:10:38 +0000789 struct intel_context *ctx,
Nick Hoath2d129552015-01-15 13:10:36 +0000790 struct drm_i915_gem_request *request)
Oscar Mateo82e104c2014-07-24 17:04:26 +0100791{
Ben Widawsky84b790f2014-07-24 17:04:36 +0100792 struct intel_engine_cs *ring = ringbuf->ring;
Ben Widawsky84b790f2014-07-24 17:04:36 +0100793
Oscar Mateo82e104c2014-07-24 17:04:26 +0100794 intel_logical_ring_advance(ringbuf);
795
Ben Widawsky84b790f2014-07-24 17:04:36 +0100796 if (intel_ring_stopped(ring))
Oscar Mateo82e104c2014-07-24 17:04:26 +0100797 return;
798
Nick Hoath2d129552015-01-15 13:10:36 +0000799 execlists_context_queue(ring, ctx, ringbuf->tail, request);
Oscar Mateo82e104c2014-07-24 17:04:26 +0100800}
801
Oscar Mateodcb4c122014-11-13 10:28:10 +0000802static int intel_lr_context_pin(struct intel_engine_cs *ring,
803 struct intel_context *ctx)
804{
805 struct drm_i915_gem_object *ctx_obj = ctx->engine[ring->id].state;
Thomas Daniel7ba717c2014-11-13 10:28:56 +0000806 struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf;
Oscar Mateodcb4c122014-11-13 10:28:10 +0000807 int ret = 0;
808
809 WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex));
Mika Kuoppalaa7cbede2015-01-13 11:32:25 +0200810 if (ctx->engine[ring->id].pin_count++ == 0) {
Oscar Mateodcb4c122014-11-13 10:28:10 +0000811 ret = i915_gem_obj_ggtt_pin(ctx_obj,
812 GEN8_LR_CONTEXT_ALIGN, 0);
813 if (ret)
Mika Kuoppalaa7cbede2015-01-13 11:32:25 +0200814 goto reset_pin_count;
Thomas Daniel7ba717c2014-11-13 10:28:56 +0000815
816 ret = intel_pin_and_map_ringbuffer_obj(ring->dev, ringbuf);
817 if (ret)
818 goto unpin_ctx_obj;
Oscar Mateodcb4c122014-11-13 10:28:10 +0000819 }
820
821 return ret;
Thomas Daniel7ba717c2014-11-13 10:28:56 +0000822
823unpin_ctx_obj:
824 i915_gem_object_ggtt_unpin(ctx_obj);
Mika Kuoppalaa7cbede2015-01-13 11:32:25 +0200825reset_pin_count:
826 ctx->engine[ring->id].pin_count = 0;
Thomas Daniel7ba717c2014-11-13 10:28:56 +0000827
828 return ret;
Oscar Mateodcb4c122014-11-13 10:28:10 +0000829}
830
831void intel_lr_context_unpin(struct intel_engine_cs *ring,
832 struct intel_context *ctx)
833{
834 struct drm_i915_gem_object *ctx_obj = ctx->engine[ring->id].state;
Thomas Daniel7ba717c2014-11-13 10:28:56 +0000835 struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf;
Oscar Mateodcb4c122014-11-13 10:28:10 +0000836
837 if (ctx_obj) {
838 WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex));
Mika Kuoppalaa7cbede2015-01-13 11:32:25 +0200839 if (--ctx->engine[ring->id].pin_count == 0) {
Thomas Daniel7ba717c2014-11-13 10:28:56 +0000840 intel_unpin_ringbuffer_obj(ringbuf);
Oscar Mateodcb4c122014-11-13 10:28:10 +0000841 i915_gem_object_ggtt_unpin(ctx_obj);
Thomas Daniel7ba717c2014-11-13 10:28:56 +0000842 }
Oscar Mateodcb4c122014-11-13 10:28:10 +0000843 }
844}
845
John Harrison6259cea2014-11-24 18:49:29 +0000846static int logical_ring_alloc_request(struct intel_engine_cs *ring,
847 struct intel_context *ctx)
Oscar Mateo82e104c2014-07-24 17:04:26 +0100848{
John Harrison9eba5d42014-11-24 18:49:23 +0000849 struct drm_i915_gem_request *request;
John Harrison67e29372014-12-05 13:49:35 +0000850 struct drm_i915_private *dev_private = ring->dev->dev_private;
Oscar Mateodcb4c122014-11-13 10:28:10 +0000851 int ret;
852
John Harrison6259cea2014-11-24 18:49:29 +0000853 if (ring->outstanding_lazy_request)
Oscar Mateo82e104c2014-07-24 17:04:26 +0100854 return 0;
855
John Harrisonaaeb1ba2014-12-05 13:49:34 +0000856 request = kzalloc(sizeof(*request), GFP_KERNEL);
John Harrison9eba5d42014-11-24 18:49:23 +0000857 if (request == NULL)
858 return -ENOMEM;
Oscar Mateo82e104c2014-07-24 17:04:26 +0100859
John Harrison9eba5d42014-11-24 18:49:23 +0000860 if (ctx != ring->default_context) {
861 ret = intel_lr_context_pin(ring, ctx);
862 if (ret) {
863 kfree(request);
864 return ret;
Oscar Mateodcb4c122014-11-13 10:28:10 +0000865 }
Oscar Mateo82e104c2014-07-24 17:04:26 +0100866 }
867
John Harrisonabfe2622014-11-24 18:49:24 +0000868 kref_init(&request->ref);
John Harrisonff79e852014-11-24 18:49:41 +0000869 request->ring = ring;
John Harrison67e29372014-12-05 13:49:35 +0000870 request->uniq = dev_private->request_uniq++;
John Harrisonabfe2622014-11-24 18:49:24 +0000871
John Harrison6259cea2014-11-24 18:49:29 +0000872 ret = i915_gem_get_seqno(ring->dev, &request->seqno);
John Harrison9eba5d42014-11-24 18:49:23 +0000873 if (ret) {
874 intel_lr_context_unpin(ring, ctx);
875 kfree(request);
876 return ret;
877 }
878
879 /* Hold a reference to the context this request belongs to
880 * (we will need it when the time comes to emit/retire the
881 * request).
882 */
883 request->ctx = ctx;
884 i915_gem_context_reference(request->ctx);
885
John Harrison6259cea2014-11-24 18:49:29 +0000886 ring->outstanding_lazy_request = request;
John Harrison9eba5d42014-11-24 18:49:23 +0000887 return 0;
Oscar Mateo82e104c2014-07-24 17:04:26 +0100888}
889
890static int logical_ring_wait_request(struct intel_ringbuffer *ringbuf,
891 int bytes)
892{
893 struct intel_engine_cs *ring = ringbuf->ring;
894 struct drm_i915_gem_request *request;
Oscar Mateo82e104c2014-07-24 17:04:26 +0100895 int ret;
896
Dave Gordonebd0fd42014-11-27 11:22:49 +0000897 if (intel_ring_space(ringbuf) >= bytes)
898 return 0;
Oscar Mateo82e104c2014-07-24 17:04:26 +0100899
900 list_for_each_entry(request, &ring->request_list, list) {
Dave Gordon57e21512014-11-18 20:07:20 +0000901 /*
902 * The request queue is per-engine, so can contain requests
903 * from multiple ringbuffers. Here, we must ignore any that
904 * aren't from the ringbuffer we're considering.
905 */
906 struct intel_context *ctx = request->ctx;
907 if (ctx->engine[ring->id].ringbuf != ringbuf)
908 continue;
909
910 /* Would completion of this request free enough space? */
Oscar Mateo82e104c2014-07-24 17:04:26 +0100911 if (__intel_ring_space(request->tail, ringbuf->tail,
912 ringbuf->size) >= bytes) {
Oscar Mateo82e104c2014-07-24 17:04:26 +0100913 break;
914 }
915 }
916
Daniel Vettera4b3a572014-11-26 14:17:05 +0100917 if (&request->list == &ring->request_list)
Oscar Mateo82e104c2014-07-24 17:04:26 +0100918 return -ENOSPC;
919
Daniel Vettera4b3a572014-11-26 14:17:05 +0100920 ret = i915_wait_request(request);
Oscar Mateo82e104c2014-07-24 17:04:26 +0100921 if (ret)
922 return ret;
923
Oscar Mateo82e104c2014-07-24 17:04:26 +0100924 i915_gem_retire_requests_ring(ring);
Oscar Mateo82e104c2014-07-24 17:04:26 +0100925
Dave Gordonebd0fd42014-11-27 11:22:49 +0000926 return intel_ring_space(ringbuf) >= bytes ? 0 : -ENOSPC;
Oscar Mateo82e104c2014-07-24 17:04:26 +0100927}
928
929static int logical_ring_wait_for_space(struct intel_ringbuffer *ringbuf,
Nick Hoath21076372015-01-15 13:10:38 +0000930 struct intel_context *ctx,
Oscar Mateo82e104c2014-07-24 17:04:26 +0100931 int bytes)
932{
933 struct intel_engine_cs *ring = ringbuf->ring;
934 struct drm_device *dev = ring->dev;
935 struct drm_i915_private *dev_priv = dev->dev_private;
936 unsigned long end;
937 int ret;
938
939 ret = logical_ring_wait_request(ringbuf, bytes);
940 if (ret != -ENOSPC)
941 return ret;
942
943 /* Force the context submission in case we have been skipping it */
Nick Hoath21076372015-01-15 13:10:38 +0000944 intel_logical_ring_advance_and_submit(ringbuf, ctx, NULL);
Oscar Mateo82e104c2014-07-24 17:04:26 +0100945
946 /* With GEM the hangcheck timer should kick us out of the loop,
947 * leaving it early runs the risk of corrupting GEM state (due
948 * to running on almost untested codepaths). But on resume
949 * timers don't work yet, so prevent a complete hang in that
950 * case by choosing an insanely large timeout. */
951 end = jiffies + 60 * HZ;
952
Dave Gordonebd0fd42014-11-27 11:22:49 +0000953 ret = 0;
Oscar Mateo82e104c2014-07-24 17:04:26 +0100954 do {
Dave Gordonebd0fd42014-11-27 11:22:49 +0000955 if (intel_ring_space(ringbuf) >= bytes)
Oscar Mateo82e104c2014-07-24 17:04:26 +0100956 break;
Oscar Mateo82e104c2014-07-24 17:04:26 +0100957
958 msleep(1);
959
960 if (dev_priv->mm.interruptible && signal_pending(current)) {
961 ret = -ERESTARTSYS;
962 break;
963 }
964
965 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
966 dev_priv->mm.interruptible);
967 if (ret)
968 break;
969
970 if (time_after(jiffies, end)) {
971 ret = -EBUSY;
972 break;
973 }
974 } while (1);
975
976 return ret;
977}
978
Nick Hoath21076372015-01-15 13:10:38 +0000979static int logical_ring_wrap_buffer(struct intel_ringbuffer *ringbuf,
980 struct intel_context *ctx)
Oscar Mateo82e104c2014-07-24 17:04:26 +0100981{
982 uint32_t __iomem *virt;
983 int rem = ringbuf->size - ringbuf->tail;
984
985 if (ringbuf->space < rem) {
Nick Hoath21076372015-01-15 13:10:38 +0000986 int ret = logical_ring_wait_for_space(ringbuf, ctx, rem);
Oscar Mateo82e104c2014-07-24 17:04:26 +0100987
988 if (ret)
989 return ret;
990 }
991
992 virt = ringbuf->virtual_start + ringbuf->tail;
993 rem /= 4;
994 while (rem--)
995 iowrite32(MI_NOOP, virt++);
996
997 ringbuf->tail = 0;
Dave Gordonebd0fd42014-11-27 11:22:49 +0000998 intel_ring_update_space(ringbuf);
Oscar Mateo82e104c2014-07-24 17:04:26 +0100999
1000 return 0;
1001}
1002
Nick Hoath21076372015-01-15 13:10:38 +00001003static int logical_ring_prepare(struct intel_ringbuffer *ringbuf,
1004 struct intel_context *ctx, int bytes)
Oscar Mateo82e104c2014-07-24 17:04:26 +01001005{
1006 int ret;
1007
1008 if (unlikely(ringbuf->tail + bytes > ringbuf->effective_size)) {
Nick Hoath21076372015-01-15 13:10:38 +00001009 ret = logical_ring_wrap_buffer(ringbuf, ctx);
Oscar Mateo82e104c2014-07-24 17:04:26 +01001010 if (unlikely(ret))
1011 return ret;
1012 }
1013
1014 if (unlikely(ringbuf->space < bytes)) {
Nick Hoath21076372015-01-15 13:10:38 +00001015 ret = logical_ring_wait_for_space(ringbuf, ctx, bytes);
Oscar Mateo82e104c2014-07-24 17:04:26 +01001016 if (unlikely(ret))
1017 return ret;
1018 }
1019
1020 return 0;
1021}
1022
Oscar Mateo73e4d072014-07-24 17:04:48 +01001023/**
1024 * intel_logical_ring_begin() - prepare the logical ringbuffer to accept some commands
1025 *
1026 * @ringbuf: Logical ringbuffer.
1027 * @num_dwords: number of DWORDs that we plan to write to the ringbuffer.
1028 *
1029 * The ringbuffer might not be ready to accept the commands right away (maybe it needs to
1030 * be wrapped, or wait a bit for the tail to be updated). This function takes care of that
1031 * and also preallocates a request (every workload submission is still mediated through
1032 * requests, same as it did with legacy ringbuffer submission).
1033 *
1034 * Return: non-zero if the ringbuffer is not ready to be written to.
1035 */
Nick Hoath21076372015-01-15 13:10:38 +00001036int intel_logical_ring_begin(struct intel_ringbuffer *ringbuf,
1037 struct intel_context *ctx, int num_dwords)
Oscar Mateo82e104c2014-07-24 17:04:26 +01001038{
1039 struct intel_engine_cs *ring = ringbuf->ring;
1040 struct drm_device *dev = ring->dev;
1041 struct drm_i915_private *dev_priv = dev->dev_private;
1042 int ret;
1043
1044 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
1045 dev_priv->mm.interruptible);
1046 if (ret)
1047 return ret;
1048
Nick Hoath21076372015-01-15 13:10:38 +00001049 ret = logical_ring_prepare(ringbuf, ctx, num_dwords * sizeof(uint32_t));
Oscar Mateo82e104c2014-07-24 17:04:26 +01001050 if (ret)
1051 return ret;
1052
1053 /* Preallocate the olr before touching the ring */
Nick Hoath21076372015-01-15 13:10:38 +00001054 ret = logical_ring_alloc_request(ring, ctx);
Oscar Mateo82e104c2014-07-24 17:04:26 +01001055 if (ret)
1056 return ret;
1057
1058 ringbuf->space -= num_dwords * sizeof(uint32_t);
1059 return 0;
1060}
1061
Michel Thierry771b9a52014-11-11 16:47:33 +00001062static int intel_logical_ring_workarounds_emit(struct intel_engine_cs *ring,
1063 struct intel_context *ctx)
1064{
1065 int ret, i;
1066 struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf;
1067 struct drm_device *dev = ring->dev;
1068 struct drm_i915_private *dev_priv = dev->dev_private;
1069 struct i915_workarounds *w = &dev_priv->workarounds;
1070
Michel Thierrye6c1abb2014-11-26 14:21:02 +00001071 if (WARN_ON_ONCE(w->count == 0))
Michel Thierry771b9a52014-11-11 16:47:33 +00001072 return 0;
1073
1074 ring->gpu_caches_dirty = true;
Nick Hoath21076372015-01-15 13:10:38 +00001075 ret = logical_ring_flush_all_caches(ringbuf, ctx);
Michel Thierry771b9a52014-11-11 16:47:33 +00001076 if (ret)
1077 return ret;
1078
Nick Hoath21076372015-01-15 13:10:38 +00001079 ret = intel_logical_ring_begin(ringbuf, ctx, w->count * 2 + 2);
Michel Thierry771b9a52014-11-11 16:47:33 +00001080 if (ret)
1081 return ret;
1082
1083 intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(w->count));
1084 for (i = 0; i < w->count; i++) {
1085 intel_logical_ring_emit(ringbuf, w->reg[i].addr);
1086 intel_logical_ring_emit(ringbuf, w->reg[i].value);
1087 }
1088 intel_logical_ring_emit(ringbuf, MI_NOOP);
1089
1090 intel_logical_ring_advance(ringbuf);
1091
1092 ring->gpu_caches_dirty = true;
Nick Hoath21076372015-01-15 13:10:38 +00001093 ret = logical_ring_flush_all_caches(ringbuf, ctx);
Michel Thierry771b9a52014-11-11 16:47:33 +00001094 if (ret)
1095 return ret;
1096
1097 return 0;
1098}
1099
Oscar Mateo9b1136d2014-07-24 17:04:24 +01001100static int gen8_init_common_ring(struct intel_engine_cs *ring)
1101{
1102 struct drm_device *dev = ring->dev;
1103 struct drm_i915_private *dev_priv = dev->dev_private;
1104
Oscar Mateo73d477f2014-07-24 17:04:31 +01001105 I915_WRITE_IMR(ring, ~(ring->irq_enable_mask | ring->irq_keep_mask));
1106 I915_WRITE(RING_HWSTAM(ring->mmio_base), 0xffffffff);
1107
Oscar Mateo9b1136d2014-07-24 17:04:24 +01001108 I915_WRITE(RING_MODE_GEN7(ring),
1109 _MASKED_BIT_DISABLE(GFX_REPLAY_MODE) |
1110 _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE));
1111 POSTING_READ(RING_MODE_GEN7(ring));
Thomas Danielc0a03a22015-01-09 11:09:37 +00001112 ring->next_context_status_buffer = 0;
Oscar Mateo9b1136d2014-07-24 17:04:24 +01001113 DRM_DEBUG_DRIVER("Execlists enabled for %s\n", ring->name);
1114
1115 memset(&ring->hangcheck, 0, sizeof(ring->hangcheck));
1116
1117 return 0;
1118}
1119
1120static int gen8_init_render_ring(struct intel_engine_cs *ring)
1121{
1122 struct drm_device *dev = ring->dev;
1123 struct drm_i915_private *dev_priv = dev->dev_private;
1124 int ret;
1125
1126 ret = gen8_init_common_ring(ring);
1127 if (ret)
1128 return ret;
1129
1130 /* We need to disable the AsyncFlip performance optimisations in order
1131 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1132 * programmed to '1' on all products.
1133 *
1134 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
1135 */
1136 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
1137
Oscar Mateo9b1136d2014-07-24 17:04:24 +01001138 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
1139
Michel Thierry771b9a52014-11-11 16:47:33 +00001140 return init_workarounds_ring(ring);
Oscar Mateo9b1136d2014-07-24 17:04:24 +01001141}
1142
Oscar Mateo15648582014-07-24 17:04:32 +01001143static int gen8_emit_bb_start(struct intel_ringbuffer *ringbuf,
Nick Hoath21076372015-01-15 13:10:38 +00001144 struct intel_context *ctx,
Oscar Mateo15648582014-07-24 17:04:32 +01001145 u64 offset, unsigned flags)
1146{
Oscar Mateo15648582014-07-24 17:04:32 +01001147 bool ppgtt = !(flags & I915_DISPATCH_SECURE);
1148 int ret;
1149
Nick Hoath21076372015-01-15 13:10:38 +00001150 ret = intel_logical_ring_begin(ringbuf, ctx, 4);
Oscar Mateo15648582014-07-24 17:04:32 +01001151 if (ret)
1152 return ret;
1153
1154 /* FIXME(BDW): Address space and security selectors. */
1155 intel_logical_ring_emit(ringbuf, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8));
1156 intel_logical_ring_emit(ringbuf, lower_32_bits(offset));
1157 intel_logical_ring_emit(ringbuf, upper_32_bits(offset));
1158 intel_logical_ring_emit(ringbuf, MI_NOOP);
1159 intel_logical_ring_advance(ringbuf);
1160
1161 return 0;
1162}
1163
Oscar Mateo73d477f2014-07-24 17:04:31 +01001164static bool gen8_logical_ring_get_irq(struct intel_engine_cs *ring)
1165{
1166 struct drm_device *dev = ring->dev;
1167 struct drm_i915_private *dev_priv = dev->dev_private;
1168 unsigned long flags;
1169
Daniel Vetter7cd512f2014-09-15 11:38:57 +02001170 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
Oscar Mateo73d477f2014-07-24 17:04:31 +01001171 return false;
1172
1173 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1174 if (ring->irq_refcount++ == 0) {
1175 I915_WRITE_IMR(ring, ~(ring->irq_enable_mask | ring->irq_keep_mask));
1176 POSTING_READ(RING_IMR(ring->mmio_base));
1177 }
1178 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1179
1180 return true;
1181}
1182
1183static void gen8_logical_ring_put_irq(struct intel_engine_cs *ring)
1184{
1185 struct drm_device *dev = ring->dev;
1186 struct drm_i915_private *dev_priv = dev->dev_private;
1187 unsigned long flags;
1188
1189 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1190 if (--ring->irq_refcount == 0) {
1191 I915_WRITE_IMR(ring, ~ring->irq_keep_mask);
1192 POSTING_READ(RING_IMR(ring->mmio_base));
1193 }
1194 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1195}
1196
Oscar Mateo47122742014-07-24 17:04:28 +01001197static int gen8_emit_flush(struct intel_ringbuffer *ringbuf,
Nick Hoath21076372015-01-15 13:10:38 +00001198 struct intel_context *ctx,
Oscar Mateo47122742014-07-24 17:04:28 +01001199 u32 invalidate_domains,
1200 u32 unused)
1201{
1202 struct intel_engine_cs *ring = ringbuf->ring;
1203 struct drm_device *dev = ring->dev;
1204 struct drm_i915_private *dev_priv = dev->dev_private;
1205 uint32_t cmd;
1206 int ret;
1207
Nick Hoath21076372015-01-15 13:10:38 +00001208 ret = intel_logical_ring_begin(ringbuf, ctx, 4);
Oscar Mateo47122742014-07-24 17:04:28 +01001209 if (ret)
1210 return ret;
1211
1212 cmd = MI_FLUSH_DW + 1;
1213
Chris Wilsonf0a1fb12015-01-22 13:42:00 +00001214 /* We always require a command barrier so that subsequent
1215 * commands, such as breadcrumb interrupts, are strictly ordered
1216 * wrt the contents of the write cache being flushed to memory
1217 * (and thus being coherent from the CPU).
1218 */
1219 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
1220
1221 if (invalidate_domains & I915_GEM_GPU_DOMAINS) {
1222 cmd |= MI_INVALIDATE_TLB;
1223 if (ring == &dev_priv->ring[VCS])
1224 cmd |= MI_INVALIDATE_BSD;
Oscar Mateo47122742014-07-24 17:04:28 +01001225 }
1226
1227 intel_logical_ring_emit(ringbuf, cmd);
1228 intel_logical_ring_emit(ringbuf,
1229 I915_GEM_HWS_SCRATCH_ADDR |
1230 MI_FLUSH_DW_USE_GTT);
1231 intel_logical_ring_emit(ringbuf, 0); /* upper addr */
1232 intel_logical_ring_emit(ringbuf, 0); /* value */
1233 intel_logical_ring_advance(ringbuf);
1234
1235 return 0;
1236}
1237
1238static int gen8_emit_flush_render(struct intel_ringbuffer *ringbuf,
Nick Hoath21076372015-01-15 13:10:38 +00001239 struct intel_context *ctx,
Oscar Mateo47122742014-07-24 17:04:28 +01001240 u32 invalidate_domains,
1241 u32 flush_domains)
1242{
1243 struct intel_engine_cs *ring = ringbuf->ring;
1244 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
1245 u32 flags = 0;
1246 int ret;
1247
1248 flags |= PIPE_CONTROL_CS_STALL;
1249
1250 if (flush_domains) {
1251 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
1252 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
1253 }
1254
1255 if (invalidate_domains) {
1256 flags |= PIPE_CONTROL_TLB_INVALIDATE;
1257 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
1258 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
1259 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
1260 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
1261 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
1262 flags |= PIPE_CONTROL_QW_WRITE;
1263 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
1264 }
1265
Nick Hoath21076372015-01-15 13:10:38 +00001266 ret = intel_logical_ring_begin(ringbuf, ctx, 6);
Oscar Mateo47122742014-07-24 17:04:28 +01001267 if (ret)
1268 return ret;
1269
1270 intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6));
1271 intel_logical_ring_emit(ringbuf, flags);
1272 intel_logical_ring_emit(ringbuf, scratch_addr);
1273 intel_logical_ring_emit(ringbuf, 0);
1274 intel_logical_ring_emit(ringbuf, 0);
1275 intel_logical_ring_emit(ringbuf, 0);
1276 intel_logical_ring_advance(ringbuf);
1277
1278 return 0;
1279}
1280
Oscar Mateoe94e37a2014-07-24 17:04:25 +01001281static u32 gen8_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1282{
1283 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1284}
1285
1286static void gen8_set_seqno(struct intel_engine_cs *ring, u32 seqno)
1287{
1288 intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
1289}
1290
Nick Hoath2d129552015-01-15 13:10:36 +00001291static int gen8_emit_request(struct intel_ringbuffer *ringbuf,
1292 struct drm_i915_gem_request *request)
Oscar Mateo4da46e12014-07-24 17:04:27 +01001293{
1294 struct intel_engine_cs *ring = ringbuf->ring;
1295 u32 cmd;
1296 int ret;
1297
Nick Hoath21076372015-01-15 13:10:38 +00001298 ret = intel_logical_ring_begin(ringbuf, request->ctx, 6);
Oscar Mateo4da46e12014-07-24 17:04:27 +01001299 if (ret)
1300 return ret;
1301
Ville Syrjälä8edfbb82014-11-14 18:16:56 +02001302 cmd = MI_STORE_DWORD_IMM_GEN4;
Oscar Mateo4da46e12014-07-24 17:04:27 +01001303 cmd |= MI_GLOBAL_GTT;
1304
1305 intel_logical_ring_emit(ringbuf, cmd);
1306 intel_logical_ring_emit(ringbuf,
1307 (ring->status_page.gfx_addr +
1308 (I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT)));
1309 intel_logical_ring_emit(ringbuf, 0);
John Harrison6259cea2014-11-24 18:49:29 +00001310 intel_logical_ring_emit(ringbuf,
1311 i915_gem_request_get_seqno(ring->outstanding_lazy_request));
Oscar Mateo4da46e12014-07-24 17:04:27 +01001312 intel_logical_ring_emit(ringbuf, MI_USER_INTERRUPT);
1313 intel_logical_ring_emit(ringbuf, MI_NOOP);
Nick Hoath21076372015-01-15 13:10:38 +00001314 intel_logical_ring_advance_and_submit(ringbuf, request->ctx, request);
Oscar Mateo4da46e12014-07-24 17:04:27 +01001315
1316 return 0;
1317}
1318
Thomas Daniele7778be2014-12-02 12:50:48 +00001319static int gen8_init_rcs_context(struct intel_engine_cs *ring,
1320 struct intel_context *ctx)
1321{
1322 int ret;
1323
1324 ret = intel_logical_ring_workarounds_emit(ring, ctx);
1325 if (ret)
1326 return ret;
1327
1328 return intel_lr_context_render_state_init(ring, ctx);
1329}
1330
Oscar Mateo73e4d072014-07-24 17:04:48 +01001331/**
1332 * intel_logical_ring_cleanup() - deallocate the Engine Command Streamer
1333 *
1334 * @ring: Engine Command Streamer.
1335 *
1336 */
Oscar Mateo454afeb2014-07-24 17:04:22 +01001337void intel_logical_ring_cleanup(struct intel_engine_cs *ring)
1338{
John Harrison6402c332014-10-31 12:00:26 +00001339 struct drm_i915_private *dev_priv;
Oscar Mateo9832b9d2014-07-24 17:04:30 +01001340
Oscar Mateo48d82382014-07-24 17:04:23 +01001341 if (!intel_ring_initialized(ring))
1342 return;
1343
John Harrison6402c332014-10-31 12:00:26 +00001344 dev_priv = ring->dev->dev_private;
1345
Oscar Mateo9832b9d2014-07-24 17:04:30 +01001346 intel_logical_ring_stop(ring);
1347 WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0);
John Harrison6259cea2014-11-24 18:49:29 +00001348 i915_gem_request_assign(&ring->outstanding_lazy_request, NULL);
Oscar Mateo48d82382014-07-24 17:04:23 +01001349
1350 if (ring->cleanup)
1351 ring->cleanup(ring);
1352
1353 i915_cmd_parser_fini_ring(ring);
1354
1355 if (ring->status_page.obj) {
1356 kunmap(sg_page(ring->status_page.obj->pages->sgl));
1357 ring->status_page.obj = NULL;
1358 }
Oscar Mateo454afeb2014-07-24 17:04:22 +01001359}
1360
1361static int logical_ring_init(struct drm_device *dev, struct intel_engine_cs *ring)
1362{
Oscar Mateo48d82382014-07-24 17:04:23 +01001363 int ret;
Oscar Mateo48d82382014-07-24 17:04:23 +01001364
1365 /* Intentionally left blank. */
1366 ring->buffer = NULL;
1367
1368 ring->dev = dev;
1369 INIT_LIST_HEAD(&ring->active_list);
1370 INIT_LIST_HEAD(&ring->request_list);
1371 init_waitqueue_head(&ring->irq_queue);
1372
Michel Thierryacdd8842014-07-24 17:04:38 +01001373 INIT_LIST_HEAD(&ring->execlist_queue);
Thomas Danielc86ee3a92014-11-13 10:27:05 +00001374 INIT_LIST_HEAD(&ring->execlist_retired_req_list);
Michel Thierryacdd8842014-07-24 17:04:38 +01001375 spin_lock_init(&ring->execlist_lock);
1376
Oscar Mateo48d82382014-07-24 17:04:23 +01001377 ret = i915_cmd_parser_init_ring(ring);
1378 if (ret)
1379 return ret;
1380
Oscar Mateo564ddb22014-08-21 11:40:54 +01001381 ret = intel_lr_context_deferred_create(ring->default_context, ring);
1382
1383 return ret;
Oscar Mateo454afeb2014-07-24 17:04:22 +01001384}
1385
1386static int logical_render_ring_init(struct drm_device *dev)
1387{
1388 struct drm_i915_private *dev_priv = dev->dev_private;
1389 struct intel_engine_cs *ring = &dev_priv->ring[RCS];
Daniel Vetter99be1df2014-11-20 00:33:06 +01001390 int ret;
Oscar Mateo454afeb2014-07-24 17:04:22 +01001391
1392 ring->name = "render ring";
1393 ring->id = RCS;
1394 ring->mmio_base = RENDER_RING_BASE;
1395 ring->irq_enable_mask =
1396 GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT;
Oscar Mateo73d477f2014-07-24 17:04:31 +01001397 ring->irq_keep_mask =
1398 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT;
1399 if (HAS_L3_DPF(dev))
1400 ring->irq_keep_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
Oscar Mateo454afeb2014-07-24 17:04:22 +01001401
Daniel Vetterecfe00d2014-11-20 00:33:04 +01001402 ring->init_hw = gen8_init_render_ring;
Thomas Daniele7778be2014-12-02 12:50:48 +00001403 ring->init_context = gen8_init_rcs_context;
Oscar Mateo9b1136d2014-07-24 17:04:24 +01001404 ring->cleanup = intel_fini_pipe_control;
Oscar Mateoe94e37a2014-07-24 17:04:25 +01001405 ring->get_seqno = gen8_get_seqno;
1406 ring->set_seqno = gen8_set_seqno;
Oscar Mateo4da46e12014-07-24 17:04:27 +01001407 ring->emit_request = gen8_emit_request;
Oscar Mateo47122742014-07-24 17:04:28 +01001408 ring->emit_flush = gen8_emit_flush_render;
Oscar Mateo73d477f2014-07-24 17:04:31 +01001409 ring->irq_get = gen8_logical_ring_get_irq;
1410 ring->irq_put = gen8_logical_ring_put_irq;
Oscar Mateo15648582014-07-24 17:04:32 +01001411 ring->emit_bb_start = gen8_emit_bb_start;
Oscar Mateo9b1136d2014-07-24 17:04:24 +01001412
Daniel Vetter99be1df2014-11-20 00:33:06 +01001413 ring->dev = dev;
1414 ret = logical_ring_init(dev, ring);
1415 if (ret)
1416 return ret;
1417
1418 return intel_init_pipe_control(ring);
Oscar Mateo454afeb2014-07-24 17:04:22 +01001419}
1420
1421static int logical_bsd_ring_init(struct drm_device *dev)
1422{
1423 struct drm_i915_private *dev_priv = dev->dev_private;
1424 struct intel_engine_cs *ring = &dev_priv->ring[VCS];
1425
1426 ring->name = "bsd ring";
1427 ring->id = VCS;
1428 ring->mmio_base = GEN6_BSD_RING_BASE;
1429 ring->irq_enable_mask =
1430 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
Oscar Mateo73d477f2014-07-24 17:04:31 +01001431 ring->irq_keep_mask =
1432 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
Oscar Mateo454afeb2014-07-24 17:04:22 +01001433
Daniel Vetterecfe00d2014-11-20 00:33:04 +01001434 ring->init_hw = gen8_init_common_ring;
Oscar Mateoe94e37a2014-07-24 17:04:25 +01001435 ring->get_seqno = gen8_get_seqno;
1436 ring->set_seqno = gen8_set_seqno;
Oscar Mateo4da46e12014-07-24 17:04:27 +01001437 ring->emit_request = gen8_emit_request;
Oscar Mateo47122742014-07-24 17:04:28 +01001438 ring->emit_flush = gen8_emit_flush;
Oscar Mateo73d477f2014-07-24 17:04:31 +01001439 ring->irq_get = gen8_logical_ring_get_irq;
1440 ring->irq_put = gen8_logical_ring_put_irq;
Oscar Mateo15648582014-07-24 17:04:32 +01001441 ring->emit_bb_start = gen8_emit_bb_start;
Oscar Mateo9b1136d2014-07-24 17:04:24 +01001442
Oscar Mateo454afeb2014-07-24 17:04:22 +01001443 return logical_ring_init(dev, ring);
1444}
1445
1446static int logical_bsd2_ring_init(struct drm_device *dev)
1447{
1448 struct drm_i915_private *dev_priv = dev->dev_private;
1449 struct intel_engine_cs *ring = &dev_priv->ring[VCS2];
1450
1451 ring->name = "bds2 ring";
1452 ring->id = VCS2;
1453 ring->mmio_base = GEN8_BSD2_RING_BASE;
1454 ring->irq_enable_mask =
1455 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
Oscar Mateo73d477f2014-07-24 17:04:31 +01001456 ring->irq_keep_mask =
1457 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
Oscar Mateo454afeb2014-07-24 17:04:22 +01001458
Daniel Vetterecfe00d2014-11-20 00:33:04 +01001459 ring->init_hw = gen8_init_common_ring;
Oscar Mateoe94e37a2014-07-24 17:04:25 +01001460 ring->get_seqno = gen8_get_seqno;
1461 ring->set_seqno = gen8_set_seqno;
Oscar Mateo4da46e12014-07-24 17:04:27 +01001462 ring->emit_request = gen8_emit_request;
Oscar Mateo47122742014-07-24 17:04:28 +01001463 ring->emit_flush = gen8_emit_flush;
Oscar Mateo73d477f2014-07-24 17:04:31 +01001464 ring->irq_get = gen8_logical_ring_get_irq;
1465 ring->irq_put = gen8_logical_ring_put_irq;
Oscar Mateo15648582014-07-24 17:04:32 +01001466 ring->emit_bb_start = gen8_emit_bb_start;
Oscar Mateo9b1136d2014-07-24 17:04:24 +01001467
Oscar Mateo454afeb2014-07-24 17:04:22 +01001468 return logical_ring_init(dev, ring);
1469}
1470
1471static int logical_blt_ring_init(struct drm_device *dev)
1472{
1473 struct drm_i915_private *dev_priv = dev->dev_private;
1474 struct intel_engine_cs *ring = &dev_priv->ring[BCS];
1475
1476 ring->name = "blitter ring";
1477 ring->id = BCS;
1478 ring->mmio_base = BLT_RING_BASE;
1479 ring->irq_enable_mask =
1480 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
Oscar Mateo73d477f2014-07-24 17:04:31 +01001481 ring->irq_keep_mask =
1482 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
Oscar Mateo454afeb2014-07-24 17:04:22 +01001483
Daniel Vetterecfe00d2014-11-20 00:33:04 +01001484 ring->init_hw = gen8_init_common_ring;
Oscar Mateoe94e37a2014-07-24 17:04:25 +01001485 ring->get_seqno = gen8_get_seqno;
1486 ring->set_seqno = gen8_set_seqno;
Oscar Mateo4da46e12014-07-24 17:04:27 +01001487 ring->emit_request = gen8_emit_request;
Oscar Mateo47122742014-07-24 17:04:28 +01001488 ring->emit_flush = gen8_emit_flush;
Oscar Mateo73d477f2014-07-24 17:04:31 +01001489 ring->irq_get = gen8_logical_ring_get_irq;
1490 ring->irq_put = gen8_logical_ring_put_irq;
Oscar Mateo15648582014-07-24 17:04:32 +01001491 ring->emit_bb_start = gen8_emit_bb_start;
Oscar Mateo9b1136d2014-07-24 17:04:24 +01001492
Oscar Mateo454afeb2014-07-24 17:04:22 +01001493 return logical_ring_init(dev, ring);
1494}
1495
1496static int logical_vebox_ring_init(struct drm_device *dev)
1497{
1498 struct drm_i915_private *dev_priv = dev->dev_private;
1499 struct intel_engine_cs *ring = &dev_priv->ring[VECS];
1500
1501 ring->name = "video enhancement ring";
1502 ring->id = VECS;
1503 ring->mmio_base = VEBOX_RING_BASE;
1504 ring->irq_enable_mask =
1505 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
Oscar Mateo73d477f2014-07-24 17:04:31 +01001506 ring->irq_keep_mask =
1507 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
Oscar Mateo454afeb2014-07-24 17:04:22 +01001508
Daniel Vetterecfe00d2014-11-20 00:33:04 +01001509 ring->init_hw = gen8_init_common_ring;
Oscar Mateoe94e37a2014-07-24 17:04:25 +01001510 ring->get_seqno = gen8_get_seqno;
1511 ring->set_seqno = gen8_set_seqno;
Oscar Mateo4da46e12014-07-24 17:04:27 +01001512 ring->emit_request = gen8_emit_request;
Oscar Mateo47122742014-07-24 17:04:28 +01001513 ring->emit_flush = gen8_emit_flush;
Oscar Mateo73d477f2014-07-24 17:04:31 +01001514 ring->irq_get = gen8_logical_ring_get_irq;
1515 ring->irq_put = gen8_logical_ring_put_irq;
Oscar Mateo15648582014-07-24 17:04:32 +01001516 ring->emit_bb_start = gen8_emit_bb_start;
Oscar Mateo9b1136d2014-07-24 17:04:24 +01001517
Oscar Mateo454afeb2014-07-24 17:04:22 +01001518 return logical_ring_init(dev, ring);
1519}
1520
Oscar Mateo73e4d072014-07-24 17:04:48 +01001521/**
1522 * intel_logical_rings_init() - allocate, populate and init the Engine Command Streamers
1523 * @dev: DRM device.
1524 *
1525 * This function inits the engines for an Execlists submission style (the equivalent in the
1526 * legacy ringbuffer submission world would be i915_gem_init_rings). It does it only for
1527 * those engines that are present in the hardware.
1528 *
1529 * Return: non-zero if the initialization failed.
1530 */
Oscar Mateo454afeb2014-07-24 17:04:22 +01001531int intel_logical_rings_init(struct drm_device *dev)
1532{
1533 struct drm_i915_private *dev_priv = dev->dev_private;
1534 int ret;
1535
1536 ret = logical_render_ring_init(dev);
1537 if (ret)
1538 return ret;
1539
1540 if (HAS_BSD(dev)) {
1541 ret = logical_bsd_ring_init(dev);
1542 if (ret)
1543 goto cleanup_render_ring;
1544 }
1545
1546 if (HAS_BLT(dev)) {
1547 ret = logical_blt_ring_init(dev);
1548 if (ret)
1549 goto cleanup_bsd_ring;
1550 }
1551
1552 if (HAS_VEBOX(dev)) {
1553 ret = logical_vebox_ring_init(dev);
1554 if (ret)
1555 goto cleanup_blt_ring;
1556 }
1557
1558 if (HAS_BSD2(dev)) {
1559 ret = logical_bsd2_ring_init(dev);
1560 if (ret)
1561 goto cleanup_vebox_ring;
1562 }
1563
1564 ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000));
1565 if (ret)
1566 goto cleanup_bsd2_ring;
1567
1568 return 0;
1569
1570cleanup_bsd2_ring:
1571 intel_logical_ring_cleanup(&dev_priv->ring[VCS2]);
1572cleanup_vebox_ring:
1573 intel_logical_ring_cleanup(&dev_priv->ring[VECS]);
1574cleanup_blt_ring:
1575 intel_logical_ring_cleanup(&dev_priv->ring[BCS]);
1576cleanup_bsd_ring:
1577 intel_logical_ring_cleanup(&dev_priv->ring[VCS]);
1578cleanup_render_ring:
1579 intel_logical_ring_cleanup(&dev_priv->ring[RCS]);
1580
1581 return ret;
1582}
1583
Oscar Mateo564ddb22014-08-21 11:40:54 +01001584int intel_lr_context_render_state_init(struct intel_engine_cs *ring,
1585 struct intel_context *ctx)
1586{
1587 struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf;
1588 struct render_state so;
1589 struct drm_i915_file_private *file_priv = ctx->file_priv;
1590 struct drm_file *file = file_priv ? file_priv->file : NULL;
1591 int ret;
1592
1593 ret = i915_gem_render_state_prepare(ring, &so);
1594 if (ret)
1595 return ret;
1596
1597 if (so.rodata == NULL)
1598 return 0;
1599
1600 ret = ring->emit_bb_start(ringbuf,
Nick Hoath21076372015-01-15 13:10:38 +00001601 ctx,
Oscar Mateo564ddb22014-08-21 11:40:54 +01001602 so.ggtt_offset,
1603 I915_DISPATCH_SECURE);
1604 if (ret)
1605 goto out;
1606
1607 i915_vma_move_to_active(i915_gem_obj_to_ggtt(so.obj), ring);
1608
John Harrison9400ae52014-11-24 18:49:36 +00001609 ret = __i915_add_request(ring, file, so.obj);
Oscar Mateo564ddb22014-08-21 11:40:54 +01001610 /* intel_logical_ring_add_request moves object to inactive if it
1611 * fails */
1612out:
1613 i915_gem_render_state_fini(&so);
1614 return ret;
1615}
1616
Oscar Mateo8670d6f2014-07-24 17:04:17 +01001617static int
1618populate_lr_context(struct intel_context *ctx, struct drm_i915_gem_object *ctx_obj,
1619 struct intel_engine_cs *ring, struct intel_ringbuffer *ringbuf)
1620{
Thomas Daniel2d965532014-08-19 10:13:36 +01001621 struct drm_device *dev = ring->dev;
1622 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetterae6c4802014-08-06 15:04:53 +02001623 struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
Oscar Mateo8670d6f2014-07-24 17:04:17 +01001624 struct page *page;
1625 uint32_t *reg_state;
1626 int ret;
1627
Thomas Daniel2d965532014-08-19 10:13:36 +01001628 if (!ppgtt)
1629 ppgtt = dev_priv->mm.aliasing_ppgtt;
1630
Oscar Mateo8670d6f2014-07-24 17:04:17 +01001631 ret = i915_gem_object_set_to_cpu_domain(ctx_obj, true);
1632 if (ret) {
1633 DRM_DEBUG_DRIVER("Could not set to CPU domain\n");
1634 return ret;
1635 }
1636
1637 ret = i915_gem_object_get_pages(ctx_obj);
1638 if (ret) {
1639 DRM_DEBUG_DRIVER("Could not get object pages\n");
1640 return ret;
1641 }
1642
1643 i915_gem_object_pin_pages(ctx_obj);
1644
1645 /* The second page of the context object contains some fields which must
1646 * be set up prior to the first execution. */
1647 page = i915_gem_object_get_page(ctx_obj, 1);
1648 reg_state = kmap_atomic(page);
1649
1650 /* A context is actually a big batch buffer with several MI_LOAD_REGISTER_IMM
1651 * commands followed by (reg, value) pairs. The values we are setting here are
1652 * only for the first context restore: on a subsequent save, the GPU will
1653 * recreate this batchbuffer with new values (including all the missing
1654 * MI_LOAD_REGISTER_IMM commands that we are not initializing here). */
1655 if (ring->id == RCS)
1656 reg_state[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(14);
1657 else
1658 reg_state[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(11);
1659 reg_state[CTX_LRI_HEADER_0] |= MI_LRI_FORCE_POSTED;
1660 reg_state[CTX_CONTEXT_CONTROL] = RING_CONTEXT_CONTROL(ring);
1661 reg_state[CTX_CONTEXT_CONTROL+1] =
1662 _MASKED_BIT_ENABLE((1<<3) | MI_RESTORE_INHIBIT);
1663 reg_state[CTX_RING_HEAD] = RING_HEAD(ring->mmio_base);
1664 reg_state[CTX_RING_HEAD+1] = 0;
1665 reg_state[CTX_RING_TAIL] = RING_TAIL(ring->mmio_base);
1666 reg_state[CTX_RING_TAIL+1] = 0;
1667 reg_state[CTX_RING_BUFFER_START] = RING_START(ring->mmio_base);
Thomas Daniel7ba717c2014-11-13 10:28:56 +00001668 /* Ring buffer start address is not known until the buffer is pinned.
1669 * It is written to the context image in execlists_update_context()
1670 */
Oscar Mateo8670d6f2014-07-24 17:04:17 +01001671 reg_state[CTX_RING_BUFFER_CONTROL] = RING_CTL(ring->mmio_base);
1672 reg_state[CTX_RING_BUFFER_CONTROL+1] =
1673 ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES) | RING_VALID;
1674 reg_state[CTX_BB_HEAD_U] = ring->mmio_base + 0x168;
1675 reg_state[CTX_BB_HEAD_U+1] = 0;
1676 reg_state[CTX_BB_HEAD_L] = ring->mmio_base + 0x140;
1677 reg_state[CTX_BB_HEAD_L+1] = 0;
1678 reg_state[CTX_BB_STATE] = ring->mmio_base + 0x110;
1679 reg_state[CTX_BB_STATE+1] = (1<<5);
1680 reg_state[CTX_SECOND_BB_HEAD_U] = ring->mmio_base + 0x11c;
1681 reg_state[CTX_SECOND_BB_HEAD_U+1] = 0;
1682 reg_state[CTX_SECOND_BB_HEAD_L] = ring->mmio_base + 0x114;
1683 reg_state[CTX_SECOND_BB_HEAD_L+1] = 0;
1684 reg_state[CTX_SECOND_BB_STATE] = ring->mmio_base + 0x118;
1685 reg_state[CTX_SECOND_BB_STATE+1] = 0;
1686 if (ring->id == RCS) {
1687 /* TODO: according to BSpec, the register state context
1688 * for CHV does not have these. OTOH, these registers do
1689 * exist in CHV. I'm waiting for a clarification */
1690 reg_state[CTX_BB_PER_CTX_PTR] = ring->mmio_base + 0x1c0;
1691 reg_state[CTX_BB_PER_CTX_PTR+1] = 0;
1692 reg_state[CTX_RCS_INDIRECT_CTX] = ring->mmio_base + 0x1c4;
1693 reg_state[CTX_RCS_INDIRECT_CTX+1] = 0;
1694 reg_state[CTX_RCS_INDIRECT_CTX_OFFSET] = ring->mmio_base + 0x1c8;
1695 reg_state[CTX_RCS_INDIRECT_CTX_OFFSET+1] = 0;
1696 }
1697 reg_state[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9);
1698 reg_state[CTX_LRI_HEADER_1] |= MI_LRI_FORCE_POSTED;
1699 reg_state[CTX_CTX_TIMESTAMP] = ring->mmio_base + 0x3a8;
1700 reg_state[CTX_CTX_TIMESTAMP+1] = 0;
1701 reg_state[CTX_PDP3_UDW] = GEN8_RING_PDP_UDW(ring, 3);
1702 reg_state[CTX_PDP3_LDW] = GEN8_RING_PDP_LDW(ring, 3);
1703 reg_state[CTX_PDP2_UDW] = GEN8_RING_PDP_UDW(ring, 2);
1704 reg_state[CTX_PDP2_LDW] = GEN8_RING_PDP_LDW(ring, 2);
1705 reg_state[CTX_PDP1_UDW] = GEN8_RING_PDP_UDW(ring, 1);
1706 reg_state[CTX_PDP1_LDW] = GEN8_RING_PDP_LDW(ring, 1);
1707 reg_state[CTX_PDP0_UDW] = GEN8_RING_PDP_UDW(ring, 0);
1708 reg_state[CTX_PDP0_LDW] = GEN8_RING_PDP_LDW(ring, 0);
1709 reg_state[CTX_PDP3_UDW+1] = upper_32_bits(ppgtt->pd_dma_addr[3]);
1710 reg_state[CTX_PDP3_LDW+1] = lower_32_bits(ppgtt->pd_dma_addr[3]);
1711 reg_state[CTX_PDP2_UDW+1] = upper_32_bits(ppgtt->pd_dma_addr[2]);
1712 reg_state[CTX_PDP2_LDW+1] = lower_32_bits(ppgtt->pd_dma_addr[2]);
1713 reg_state[CTX_PDP1_UDW+1] = upper_32_bits(ppgtt->pd_dma_addr[1]);
1714 reg_state[CTX_PDP1_LDW+1] = lower_32_bits(ppgtt->pd_dma_addr[1]);
1715 reg_state[CTX_PDP0_UDW+1] = upper_32_bits(ppgtt->pd_dma_addr[0]);
1716 reg_state[CTX_PDP0_LDW+1] = lower_32_bits(ppgtt->pd_dma_addr[0]);
1717 if (ring->id == RCS) {
1718 reg_state[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1);
1719 reg_state[CTX_R_PWR_CLK_STATE] = 0x20c8;
1720 reg_state[CTX_R_PWR_CLK_STATE+1] = 0;
1721 }
1722
1723 kunmap_atomic(reg_state);
1724
1725 ctx_obj->dirty = 1;
1726 set_page_dirty(page);
1727 i915_gem_object_unpin_pages(ctx_obj);
1728
1729 return 0;
1730}
1731
Oscar Mateo73e4d072014-07-24 17:04:48 +01001732/**
1733 * intel_lr_context_free() - free the LRC specific bits of a context
1734 * @ctx: the LR context to free.
1735 *
1736 * The real context freeing is done in i915_gem_context_free: this only
1737 * takes care of the bits that are LRC related: the per-engine backing
1738 * objects and the logical ringbuffer.
1739 */
Oscar Mateoede7d422014-07-24 17:04:12 +01001740void intel_lr_context_free(struct intel_context *ctx)
1741{
Oscar Mateo8c8579172014-07-24 17:04:14 +01001742 int i;
1743
1744 for (i = 0; i < I915_NUM_RINGS; i++) {
1745 struct drm_i915_gem_object *ctx_obj = ctx->engine[i].state;
Oscar Mateo84c23772014-07-24 17:04:15 +01001746
Oscar Mateo8c8579172014-07-24 17:04:14 +01001747 if (ctx_obj) {
Oscar Mateodcb4c122014-11-13 10:28:10 +00001748 struct intel_ringbuffer *ringbuf =
1749 ctx->engine[i].ringbuf;
1750 struct intel_engine_cs *ring = ringbuf->ring;
1751
Thomas Daniel7ba717c2014-11-13 10:28:56 +00001752 if (ctx == ring->default_context) {
1753 intel_unpin_ringbuffer_obj(ringbuf);
1754 i915_gem_object_ggtt_unpin(ctx_obj);
1755 }
Mika Kuoppalaa7cbede2015-01-13 11:32:25 +02001756 WARN_ON(ctx->engine[ring->id].pin_count);
Oscar Mateo84c23772014-07-24 17:04:15 +01001757 intel_destroy_ringbuffer_obj(ringbuf);
1758 kfree(ringbuf);
Oscar Mateo8c8579172014-07-24 17:04:14 +01001759 drm_gem_object_unreference(&ctx_obj->base);
1760 }
1761 }
1762}
1763
1764static uint32_t get_lr_context_size(struct intel_engine_cs *ring)
1765{
1766 int ret = 0;
1767
Michael H. Nguyen468c6812014-11-13 17:51:49 +00001768 WARN_ON(INTEL_INFO(ring->dev)->gen < 8);
Oscar Mateo8c8579172014-07-24 17:04:14 +01001769
1770 switch (ring->id) {
1771 case RCS:
Michael H. Nguyen468c6812014-11-13 17:51:49 +00001772 if (INTEL_INFO(ring->dev)->gen >= 9)
1773 ret = GEN9_LR_CONTEXT_RENDER_SIZE;
1774 else
1775 ret = GEN8_LR_CONTEXT_RENDER_SIZE;
Oscar Mateo8c8579172014-07-24 17:04:14 +01001776 break;
1777 case VCS:
1778 case BCS:
1779 case VECS:
1780 case VCS2:
1781 ret = GEN8_LR_CONTEXT_OTHER_SIZE;
1782 break;
1783 }
1784
1785 return ret;
Oscar Mateoede7d422014-07-24 17:04:12 +01001786}
1787
Daniel Vetter70b0ea82014-11-18 09:09:32 +01001788static void lrc_setup_hardware_status_page(struct intel_engine_cs *ring,
Thomas Daniel1df06b72014-10-29 09:52:51 +00001789 struct drm_i915_gem_object *default_ctx_obj)
1790{
1791 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1792
1793 /* The status page is offset 0 from the default context object
1794 * in LRC mode. */
1795 ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(default_ctx_obj);
1796 ring->status_page.page_addr =
1797 kmap(sg_page(default_ctx_obj->pages->sgl));
Thomas Daniel1df06b72014-10-29 09:52:51 +00001798 ring->status_page.obj = default_ctx_obj;
1799
1800 I915_WRITE(RING_HWS_PGA(ring->mmio_base),
1801 (u32)ring->status_page.gfx_addr);
1802 POSTING_READ(RING_HWS_PGA(ring->mmio_base));
Thomas Daniel1df06b72014-10-29 09:52:51 +00001803}
1804
Oscar Mateo73e4d072014-07-24 17:04:48 +01001805/**
1806 * intel_lr_context_deferred_create() - create the LRC specific bits of a context
1807 * @ctx: LR context to create.
1808 * @ring: engine to be used with the context.
1809 *
1810 * This function can be called more than once, with different engines, if we plan
1811 * to use the context with them. The context backing objects and the ringbuffers
1812 * (specially the ringbuffer backing objects) suck a lot of memory up, and that's why
1813 * the creation is a deferred call: it's better to make sure first that we need to use
1814 * a given ring with the context.
1815 *
Masanari Iida32197aa2014-10-20 23:53:13 +09001816 * Return: non-zero on error.
Oscar Mateo73e4d072014-07-24 17:04:48 +01001817 */
Oscar Mateoede7d422014-07-24 17:04:12 +01001818int intel_lr_context_deferred_create(struct intel_context *ctx,
1819 struct intel_engine_cs *ring)
1820{
Oscar Mateodcb4c122014-11-13 10:28:10 +00001821 const bool is_global_default_ctx = (ctx == ring->default_context);
Oscar Mateo8c8579172014-07-24 17:04:14 +01001822 struct drm_device *dev = ring->dev;
1823 struct drm_i915_gem_object *ctx_obj;
1824 uint32_t context_size;
Oscar Mateo84c23772014-07-24 17:04:15 +01001825 struct intel_ringbuffer *ringbuf;
Oscar Mateo8c8579172014-07-24 17:04:14 +01001826 int ret;
1827
Oscar Mateoede7d422014-07-24 17:04:12 +01001828 WARN_ON(ctx->legacy_hw_ctx.rcs_state != NULL);
Daniel Vetterbfc882b2014-11-20 00:33:08 +01001829 WARN_ON(ctx->engine[ring->id].state);
Oscar Mateoede7d422014-07-24 17:04:12 +01001830
Oscar Mateo8c8579172014-07-24 17:04:14 +01001831 context_size = round_up(get_lr_context_size(ring), 4096);
1832
1833 ctx_obj = i915_gem_alloc_context_obj(dev, context_size);
1834 if (IS_ERR(ctx_obj)) {
1835 ret = PTR_ERR(ctx_obj);
1836 DRM_DEBUG_DRIVER("Alloc LRC backing obj failed: %d\n", ret);
1837 return ret;
1838 }
1839
Oscar Mateodcb4c122014-11-13 10:28:10 +00001840 if (is_global_default_ctx) {
1841 ret = i915_gem_obj_ggtt_pin(ctx_obj, GEN8_LR_CONTEXT_ALIGN, 0);
1842 if (ret) {
1843 DRM_DEBUG_DRIVER("Pin LRC backing obj failed: %d\n",
1844 ret);
1845 drm_gem_object_unreference(&ctx_obj->base);
1846 return ret;
1847 }
Oscar Mateo8c8579172014-07-24 17:04:14 +01001848 }
1849
Oscar Mateo84c23772014-07-24 17:04:15 +01001850 ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL);
1851 if (!ringbuf) {
1852 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s\n",
1853 ring->name);
Oscar Mateo84c23772014-07-24 17:04:15 +01001854 ret = -ENOMEM;
Thomas Daniel7ba717c2014-11-13 10:28:56 +00001855 goto error_unpin_ctx;
Oscar Mateo84c23772014-07-24 17:04:15 +01001856 }
1857
Daniel Vetter0c7dd532014-08-11 16:17:44 +02001858 ringbuf->ring = ring;
Oscar Mateo582d67f2014-07-24 17:04:16 +01001859
Oscar Mateo84c23772014-07-24 17:04:15 +01001860 ringbuf->size = 32 * PAGE_SIZE;
1861 ringbuf->effective_size = ringbuf->size;
1862 ringbuf->head = 0;
1863 ringbuf->tail = 0;
Oscar Mateo84c23772014-07-24 17:04:15 +01001864 ringbuf->last_retired_head = -1;
Dave Gordonebd0fd42014-11-27 11:22:49 +00001865 intel_ring_update_space(ringbuf);
Oscar Mateo84c23772014-07-24 17:04:15 +01001866
Thomas Daniel7ba717c2014-11-13 10:28:56 +00001867 if (ringbuf->obj == NULL) {
1868 ret = intel_alloc_ringbuffer_obj(dev, ringbuf);
1869 if (ret) {
1870 DRM_DEBUG_DRIVER(
1871 "Failed to allocate ringbuffer obj %s: %d\n",
Oscar Mateo84c23772014-07-24 17:04:15 +01001872 ring->name, ret);
Thomas Daniel7ba717c2014-11-13 10:28:56 +00001873 goto error_free_rbuf;
1874 }
1875
1876 if (is_global_default_ctx) {
1877 ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf);
1878 if (ret) {
1879 DRM_ERROR(
1880 "Failed to pin and map ringbuffer %s: %d\n",
1881 ring->name, ret);
1882 goto error_destroy_rbuf;
1883 }
1884 }
1885
Oscar Mateo8670d6f2014-07-24 17:04:17 +01001886 }
1887
1888 ret = populate_lr_context(ctx, ctx_obj, ring, ringbuf);
1889 if (ret) {
1890 DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret);
Oscar Mateo8670d6f2014-07-24 17:04:17 +01001891 goto error;
Oscar Mateo84c23772014-07-24 17:04:15 +01001892 }
1893
1894 ctx->engine[ring->id].ringbuf = ringbuf;
Oscar Mateo8c8579172014-07-24 17:04:14 +01001895 ctx->engine[ring->id].state = ctx_obj;
Oscar Mateoede7d422014-07-24 17:04:12 +01001896
Daniel Vetter70b0ea82014-11-18 09:09:32 +01001897 if (ctx == ring->default_context)
1898 lrc_setup_hardware_status_page(ring, ctx_obj);
Thomas Daniele7778be2014-12-02 12:50:48 +00001899 else if (ring->id == RCS && !ctx->rcs_initialized) {
Michel Thierry771b9a52014-11-11 16:47:33 +00001900 if (ring->init_context) {
1901 ret = ring->init_context(ring, ctx);
Thomas Daniele7778be2014-12-02 12:50:48 +00001902 if (ret) {
Michel Thierry771b9a52014-11-11 16:47:33 +00001903 DRM_ERROR("ring init context: %d\n", ret);
Thomas Daniele7778be2014-12-02 12:50:48 +00001904 ctx->engine[ring->id].ringbuf = NULL;
1905 ctx->engine[ring->id].state = NULL;
1906 goto error;
1907 }
Michel Thierry771b9a52014-11-11 16:47:33 +00001908 }
1909
Oscar Mateo564ddb22014-08-21 11:40:54 +01001910 ctx->rcs_initialized = true;
1911 }
1912
Oscar Mateoede7d422014-07-24 17:04:12 +01001913 return 0;
Oscar Mateo8670d6f2014-07-24 17:04:17 +01001914
1915error:
Thomas Daniel7ba717c2014-11-13 10:28:56 +00001916 if (is_global_default_ctx)
1917 intel_unpin_ringbuffer_obj(ringbuf);
1918error_destroy_rbuf:
1919 intel_destroy_ringbuffer_obj(ringbuf);
1920error_free_rbuf:
Oscar Mateo8670d6f2014-07-24 17:04:17 +01001921 kfree(ringbuf);
Thomas Daniel7ba717c2014-11-13 10:28:56 +00001922error_unpin_ctx:
Oscar Mateodcb4c122014-11-13 10:28:10 +00001923 if (is_global_default_ctx)
1924 i915_gem_object_ggtt_unpin(ctx_obj);
Oscar Mateo8670d6f2014-07-24 17:04:17 +01001925 drm_gem_object_unreference(&ctx_obj->base);
1926 return ret;
Oscar Mateoede7d422014-07-24 17:04:12 +01001927}