Colin Cross | db811ca | 2011-02-20 17:14:21 -0800 | [diff] [blame] | 1 | /* |
| 2 | * drivers/i2c/busses/i2c-tegra.c |
| 3 | * |
| 4 | * Copyright (C) 2010 Google, Inc. |
| 5 | * Author: Colin Cross <ccross@android.com> |
| 6 | * |
| 7 | * This software is licensed under the terms of the GNU General Public |
| 8 | * License version 2, as published by the Free Software Foundation, and |
| 9 | * may be copied, distributed, and modified under those terms. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | */ |
| 17 | |
| 18 | #include <linux/kernel.h> |
| 19 | #include <linux/init.h> |
| 20 | #include <linux/platform_device.h> |
| 21 | #include <linux/clk.h> |
| 22 | #include <linux/err.h> |
| 23 | #include <linux/i2c.h> |
| 24 | #include <linux/io.h> |
| 25 | #include <linux/interrupt.h> |
| 26 | #include <linux/delay.h> |
| 27 | #include <linux/slab.h> |
| 28 | #include <linux/i2c-tegra.h> |
John Bonesio | 5c470f3 | 2011-06-22 09:16:56 -0700 | [diff] [blame] | 29 | #include <linux/of_i2c.h> |
Laxman Dewangan | 6ad068e | 2012-08-19 00:47:46 +0530 | [diff] [blame^] | 30 | #include <linux/of_device.h> |
Paul Gortmaker | 93cf5d7 | 2011-07-29 21:14:30 -0700 | [diff] [blame] | 31 | #include <linux/module.h> |
Colin Cross | db811ca | 2011-02-20 17:14:21 -0800 | [diff] [blame] | 32 | |
| 33 | #include <asm/unaligned.h> |
| 34 | |
| 35 | #include <mach/clk.h> |
| 36 | |
| 37 | #define TEGRA_I2C_TIMEOUT (msecs_to_jiffies(1000)) |
| 38 | #define BYTES_PER_FIFO_WORD 4 |
| 39 | |
| 40 | #define I2C_CNFG 0x000 |
Jay Cheng | 40abcf7 | 2011-04-25 15:32:27 -0600 | [diff] [blame] | 41 | #define I2C_CNFG_DEBOUNCE_CNT_SHIFT 12 |
Colin Cross | db811ca | 2011-02-20 17:14:21 -0800 | [diff] [blame] | 42 | #define I2C_CNFG_PACKET_MODE_EN (1<<10) |
| 43 | #define I2C_CNFG_NEW_MASTER_FSM (1<<11) |
Todd Poynor | cb63c62 | 2011-04-25 15:32:25 -0600 | [diff] [blame] | 44 | #define I2C_STATUS 0x01C |
Colin Cross | db811ca | 2011-02-20 17:14:21 -0800 | [diff] [blame] | 45 | #define I2C_SL_CNFG 0x020 |
Stephen Warren | 5afa9d3 | 2011-06-06 11:25:19 -0600 | [diff] [blame] | 46 | #define I2C_SL_CNFG_NACK (1<<1) |
Colin Cross | db811ca | 2011-02-20 17:14:21 -0800 | [diff] [blame] | 47 | #define I2C_SL_CNFG_NEWSL (1<<2) |
| 48 | #define I2C_SL_ADDR1 0x02c |
Stephen Warren | 5afa9d3 | 2011-06-06 11:25:19 -0600 | [diff] [blame] | 49 | #define I2C_SL_ADDR2 0x030 |
Colin Cross | db811ca | 2011-02-20 17:14:21 -0800 | [diff] [blame] | 50 | #define I2C_TX_FIFO 0x050 |
| 51 | #define I2C_RX_FIFO 0x054 |
| 52 | #define I2C_PACKET_TRANSFER_STATUS 0x058 |
| 53 | #define I2C_FIFO_CONTROL 0x05c |
| 54 | #define I2C_FIFO_CONTROL_TX_FLUSH (1<<1) |
| 55 | #define I2C_FIFO_CONTROL_RX_FLUSH (1<<0) |
| 56 | #define I2C_FIFO_CONTROL_TX_TRIG_SHIFT 5 |
| 57 | #define I2C_FIFO_CONTROL_RX_TRIG_SHIFT 2 |
| 58 | #define I2C_FIFO_STATUS 0x060 |
| 59 | #define I2C_FIFO_STATUS_TX_MASK 0xF0 |
| 60 | #define I2C_FIFO_STATUS_TX_SHIFT 4 |
| 61 | #define I2C_FIFO_STATUS_RX_MASK 0x0F |
| 62 | #define I2C_FIFO_STATUS_RX_SHIFT 0 |
| 63 | #define I2C_INT_MASK 0x064 |
| 64 | #define I2C_INT_STATUS 0x068 |
| 65 | #define I2C_INT_PACKET_XFER_COMPLETE (1<<7) |
| 66 | #define I2C_INT_ALL_PACKETS_XFER_COMPLETE (1<<6) |
| 67 | #define I2C_INT_TX_FIFO_OVERFLOW (1<<5) |
| 68 | #define I2C_INT_RX_FIFO_UNDERFLOW (1<<4) |
| 69 | #define I2C_INT_NO_ACK (1<<3) |
| 70 | #define I2C_INT_ARBITRATION_LOST (1<<2) |
| 71 | #define I2C_INT_TX_FIFO_DATA_REQ (1<<1) |
| 72 | #define I2C_INT_RX_FIFO_DATA_REQ (1<<0) |
| 73 | #define I2C_CLK_DIVISOR 0x06c |
| 74 | |
| 75 | #define DVC_CTRL_REG1 0x000 |
| 76 | #define DVC_CTRL_REG1_INTR_EN (1<<10) |
| 77 | #define DVC_CTRL_REG2 0x004 |
| 78 | #define DVC_CTRL_REG3 0x008 |
| 79 | #define DVC_CTRL_REG3_SW_PROG (1<<26) |
| 80 | #define DVC_CTRL_REG3_I2C_DONE_INTR_EN (1<<30) |
| 81 | #define DVC_STATUS 0x00c |
| 82 | #define DVC_STATUS_I2C_DONE_INTR (1<<30) |
| 83 | |
| 84 | #define I2C_ERR_NONE 0x00 |
| 85 | #define I2C_ERR_NO_ACK 0x01 |
| 86 | #define I2C_ERR_ARBITRATION_LOST 0x02 |
Todd Poynor | cb63c62 | 2011-04-25 15:32:25 -0600 | [diff] [blame] | 87 | #define I2C_ERR_UNKNOWN_INTERRUPT 0x04 |
Colin Cross | db811ca | 2011-02-20 17:14:21 -0800 | [diff] [blame] | 88 | |
| 89 | #define PACKET_HEADER0_HEADER_SIZE_SHIFT 28 |
| 90 | #define PACKET_HEADER0_PACKET_ID_SHIFT 16 |
| 91 | #define PACKET_HEADER0_CONT_ID_SHIFT 12 |
| 92 | #define PACKET_HEADER0_PROTOCOL_I2C (1<<4) |
| 93 | |
| 94 | #define I2C_HEADER_HIGHSPEED_MODE (1<<22) |
| 95 | #define I2C_HEADER_CONT_ON_NAK (1<<21) |
| 96 | #define I2C_HEADER_SEND_START_BYTE (1<<20) |
| 97 | #define I2C_HEADER_READ (1<<19) |
| 98 | #define I2C_HEADER_10BIT_ADDR (1<<18) |
| 99 | #define I2C_HEADER_IE_ENABLE (1<<17) |
| 100 | #define I2C_HEADER_REPEAT_START (1<<16) |
Laxman Dewangan | c8f5af2 | 2012-06-13 15:42:38 +0530 | [diff] [blame] | 101 | #define I2C_HEADER_CONTINUE_XFER (1<<15) |
Colin Cross | db811ca | 2011-02-20 17:14:21 -0800 | [diff] [blame] | 102 | #define I2C_HEADER_MASTER_ADDR_SHIFT 12 |
| 103 | #define I2C_HEADER_SLAVE_ADDR_SHIFT 1 |
Laxman Dewangan | c8f5af2 | 2012-06-13 15:42:38 +0530 | [diff] [blame] | 104 | /* |
| 105 | * msg_end_type: The bus control which need to be send at end of transfer. |
| 106 | * @MSG_END_STOP: Send stop pulse at end of transfer. |
| 107 | * @MSG_END_REPEAT_START: Send repeat start at end of transfer. |
| 108 | * @MSG_END_CONTINUE: The following on message is coming and so do not send |
| 109 | * stop or repeat start. |
| 110 | */ |
| 111 | enum msg_end_type { |
| 112 | MSG_END_STOP, |
| 113 | MSG_END_REPEAT_START, |
| 114 | MSG_END_CONTINUE, |
| 115 | }; |
Colin Cross | db811ca | 2011-02-20 17:14:21 -0800 | [diff] [blame] | 116 | |
| 117 | /** |
Laxman Dewangan | 6ad068e | 2012-08-19 00:47:46 +0530 | [diff] [blame^] | 118 | * struct tegra_i2c_hw_feature : Different HW support on Tegra |
| 119 | * @has_continue_xfer_support: Continue transfer supports. |
| 120 | */ |
| 121 | |
| 122 | struct tegra_i2c_hw_feature { |
| 123 | bool has_continue_xfer_support; |
| 124 | }; |
| 125 | |
| 126 | /** |
Colin Cross | db811ca | 2011-02-20 17:14:21 -0800 | [diff] [blame] | 127 | * struct tegra_i2c_dev - per device i2c context |
| 128 | * @dev: device reference for power management |
Laxman Dewangan | 6ad068e | 2012-08-19 00:47:46 +0530 | [diff] [blame^] | 129 | * @hw: Tegra i2c hw feature. |
Colin Cross | db811ca | 2011-02-20 17:14:21 -0800 | [diff] [blame] | 130 | * @adapter: core i2c layer adapter information |
Laxman Dewangan | 14e92bd | 2012-08-08 13:21:32 +0530 | [diff] [blame] | 131 | * @div_clk: clock reference for div clock of i2c controller. |
| 132 | * @fast_clk: clock reference for fast clock of i2c controller. |
Colin Cross | db811ca | 2011-02-20 17:14:21 -0800 | [diff] [blame] | 133 | * @base: ioremapped registers cookie |
| 134 | * @cont_id: i2c controller id, used for for packet header |
| 135 | * @irq: irq number of transfer complete interrupt |
| 136 | * @is_dvc: identifies the DVC i2c controller, has a different register layout |
| 137 | * @msg_complete: transfer completion notifier |
| 138 | * @msg_err: error code for completed message |
| 139 | * @msg_buf: pointer to current message data |
| 140 | * @msg_buf_remaining: size of unsent data in the message buffer |
| 141 | * @msg_read: identifies read transfers |
| 142 | * @bus_clk_rate: current i2c bus clock rate |
| 143 | * @is_suspended: prevents i2c controller accesses after suspend is called |
| 144 | */ |
| 145 | struct tegra_i2c_dev { |
| 146 | struct device *dev; |
Laxman Dewangan | 6ad068e | 2012-08-19 00:47:46 +0530 | [diff] [blame^] | 147 | const struct tegra_i2c_hw_feature *hw; |
Colin Cross | db811ca | 2011-02-20 17:14:21 -0800 | [diff] [blame] | 148 | struct i2c_adapter adapter; |
Laxman Dewangan | 14e92bd | 2012-08-08 13:21:32 +0530 | [diff] [blame] | 149 | struct clk *div_clk; |
| 150 | struct clk *fast_clk; |
Colin Cross | db811ca | 2011-02-20 17:14:21 -0800 | [diff] [blame] | 151 | void __iomem *base; |
| 152 | int cont_id; |
| 153 | int irq; |
Todd Poynor | cb63c62 | 2011-04-25 15:32:25 -0600 | [diff] [blame] | 154 | bool irq_disabled; |
Colin Cross | db811ca | 2011-02-20 17:14:21 -0800 | [diff] [blame] | 155 | int is_dvc; |
| 156 | struct completion msg_complete; |
| 157 | int msg_err; |
| 158 | u8 *msg_buf; |
| 159 | size_t msg_buf_remaining; |
| 160 | int msg_read; |
| 161 | unsigned long bus_clk_rate; |
| 162 | bool is_suspended; |
| 163 | }; |
| 164 | |
| 165 | static void dvc_writel(struct tegra_i2c_dev *i2c_dev, u32 val, unsigned long reg) |
| 166 | { |
| 167 | writel(val, i2c_dev->base + reg); |
| 168 | } |
| 169 | |
| 170 | static u32 dvc_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg) |
| 171 | { |
| 172 | return readl(i2c_dev->base + reg); |
| 173 | } |
| 174 | |
| 175 | /* |
| 176 | * i2c_writel and i2c_readl will offset the register if necessary to talk |
| 177 | * to the I2C block inside the DVC block |
| 178 | */ |
| 179 | static unsigned long tegra_i2c_reg_addr(struct tegra_i2c_dev *i2c_dev, |
| 180 | unsigned long reg) |
| 181 | { |
| 182 | if (i2c_dev->is_dvc) |
| 183 | reg += (reg >= I2C_TX_FIFO) ? 0x10 : 0x40; |
| 184 | return reg; |
| 185 | } |
| 186 | |
| 187 | static void i2c_writel(struct tegra_i2c_dev *i2c_dev, u32 val, |
| 188 | unsigned long reg) |
| 189 | { |
| 190 | writel(val, i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg)); |
Laxman Dewangan | ec7aaca | 2012-06-13 15:42:36 +0530 | [diff] [blame] | 191 | |
| 192 | /* Read back register to make sure that register writes completed */ |
| 193 | if (reg != I2C_TX_FIFO) |
| 194 | readl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg)); |
Colin Cross | db811ca | 2011-02-20 17:14:21 -0800 | [diff] [blame] | 195 | } |
| 196 | |
| 197 | static u32 i2c_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg) |
| 198 | { |
| 199 | return readl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg)); |
| 200 | } |
| 201 | |
| 202 | static void i2c_writesl(struct tegra_i2c_dev *i2c_dev, void *data, |
| 203 | unsigned long reg, int len) |
| 204 | { |
| 205 | writesl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len); |
| 206 | } |
| 207 | |
| 208 | static void i2c_readsl(struct tegra_i2c_dev *i2c_dev, void *data, |
| 209 | unsigned long reg, int len) |
| 210 | { |
| 211 | readsl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len); |
| 212 | } |
| 213 | |
| 214 | static void tegra_i2c_mask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask) |
| 215 | { |
| 216 | u32 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK); |
| 217 | int_mask &= ~mask; |
| 218 | i2c_writel(i2c_dev, int_mask, I2C_INT_MASK); |
| 219 | } |
| 220 | |
| 221 | static void tegra_i2c_unmask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask) |
| 222 | { |
| 223 | u32 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK); |
| 224 | int_mask |= mask; |
| 225 | i2c_writel(i2c_dev, int_mask, I2C_INT_MASK); |
| 226 | } |
| 227 | |
| 228 | static int tegra_i2c_flush_fifos(struct tegra_i2c_dev *i2c_dev) |
| 229 | { |
| 230 | unsigned long timeout = jiffies + HZ; |
| 231 | u32 val = i2c_readl(i2c_dev, I2C_FIFO_CONTROL); |
| 232 | val |= I2C_FIFO_CONTROL_TX_FLUSH | I2C_FIFO_CONTROL_RX_FLUSH; |
| 233 | i2c_writel(i2c_dev, val, I2C_FIFO_CONTROL); |
| 234 | |
| 235 | while (i2c_readl(i2c_dev, I2C_FIFO_CONTROL) & |
| 236 | (I2C_FIFO_CONTROL_TX_FLUSH | I2C_FIFO_CONTROL_RX_FLUSH)) { |
| 237 | if (time_after(jiffies, timeout)) { |
| 238 | dev_warn(i2c_dev->dev, "timeout waiting for fifo flush\n"); |
| 239 | return -ETIMEDOUT; |
| 240 | } |
| 241 | msleep(1); |
| 242 | } |
| 243 | return 0; |
| 244 | } |
| 245 | |
| 246 | static int tegra_i2c_empty_rx_fifo(struct tegra_i2c_dev *i2c_dev) |
| 247 | { |
| 248 | u32 val; |
| 249 | int rx_fifo_avail; |
| 250 | u8 *buf = i2c_dev->msg_buf; |
| 251 | size_t buf_remaining = i2c_dev->msg_buf_remaining; |
| 252 | int words_to_transfer; |
| 253 | |
| 254 | val = i2c_readl(i2c_dev, I2C_FIFO_STATUS); |
| 255 | rx_fifo_avail = (val & I2C_FIFO_STATUS_RX_MASK) >> |
| 256 | I2C_FIFO_STATUS_RX_SHIFT; |
| 257 | |
| 258 | /* Rounds down to not include partial word at the end of buf */ |
| 259 | words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD; |
| 260 | if (words_to_transfer > rx_fifo_avail) |
| 261 | words_to_transfer = rx_fifo_avail; |
| 262 | |
| 263 | i2c_readsl(i2c_dev, buf, I2C_RX_FIFO, words_to_transfer); |
| 264 | |
| 265 | buf += words_to_transfer * BYTES_PER_FIFO_WORD; |
| 266 | buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD; |
| 267 | rx_fifo_avail -= words_to_transfer; |
| 268 | |
| 269 | /* |
| 270 | * If there is a partial word at the end of buf, handle it manually to |
| 271 | * prevent overwriting past the end of buf |
| 272 | */ |
| 273 | if (rx_fifo_avail > 0 && buf_remaining > 0) { |
| 274 | BUG_ON(buf_remaining > 3); |
| 275 | val = i2c_readl(i2c_dev, I2C_RX_FIFO); |
| 276 | memcpy(buf, &val, buf_remaining); |
| 277 | buf_remaining = 0; |
| 278 | rx_fifo_avail--; |
| 279 | } |
| 280 | |
| 281 | BUG_ON(rx_fifo_avail > 0 && buf_remaining > 0); |
| 282 | i2c_dev->msg_buf_remaining = buf_remaining; |
| 283 | i2c_dev->msg_buf = buf; |
| 284 | return 0; |
| 285 | } |
| 286 | |
| 287 | static int tegra_i2c_fill_tx_fifo(struct tegra_i2c_dev *i2c_dev) |
| 288 | { |
| 289 | u32 val; |
| 290 | int tx_fifo_avail; |
| 291 | u8 *buf = i2c_dev->msg_buf; |
| 292 | size_t buf_remaining = i2c_dev->msg_buf_remaining; |
| 293 | int words_to_transfer; |
| 294 | |
| 295 | val = i2c_readl(i2c_dev, I2C_FIFO_STATUS); |
| 296 | tx_fifo_avail = (val & I2C_FIFO_STATUS_TX_MASK) >> |
| 297 | I2C_FIFO_STATUS_TX_SHIFT; |
| 298 | |
| 299 | /* Rounds down to not include partial word at the end of buf */ |
| 300 | words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD; |
Colin Cross | db811ca | 2011-02-20 17:14:21 -0800 | [diff] [blame] | 301 | |
Doug Anderson | 96219c3 | 2011-08-30 11:46:10 -0600 | [diff] [blame] | 302 | /* It's very common to have < 4 bytes, so optimize that case. */ |
| 303 | if (words_to_transfer) { |
| 304 | if (words_to_transfer > tx_fifo_avail) |
| 305 | words_to_transfer = tx_fifo_avail; |
Colin Cross | db811ca | 2011-02-20 17:14:21 -0800 | [diff] [blame] | 306 | |
Doug Anderson | 96219c3 | 2011-08-30 11:46:10 -0600 | [diff] [blame] | 307 | /* |
| 308 | * Update state before writing to FIFO. If this casues us |
| 309 | * to finish writing all bytes (AKA buf_remaining goes to 0) we |
| 310 | * have a potential for an interrupt (PACKET_XFER_COMPLETE is |
| 311 | * not maskable). We need to make sure that the isr sees |
| 312 | * buf_remaining as 0 and doesn't call us back re-entrantly. |
| 313 | */ |
| 314 | buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD; |
| 315 | tx_fifo_avail -= words_to_transfer; |
| 316 | i2c_dev->msg_buf_remaining = buf_remaining; |
| 317 | i2c_dev->msg_buf = buf + |
| 318 | words_to_transfer * BYTES_PER_FIFO_WORD; |
| 319 | barrier(); |
| 320 | |
| 321 | i2c_writesl(i2c_dev, buf, I2C_TX_FIFO, words_to_transfer); |
| 322 | |
| 323 | buf += words_to_transfer * BYTES_PER_FIFO_WORD; |
| 324 | } |
Colin Cross | db811ca | 2011-02-20 17:14:21 -0800 | [diff] [blame] | 325 | |
| 326 | /* |
| 327 | * If there is a partial word at the end of buf, handle it manually to |
| 328 | * prevent reading past the end of buf, which could cross a page |
| 329 | * boundary and fault. |
| 330 | */ |
| 331 | if (tx_fifo_avail > 0 && buf_remaining > 0) { |
| 332 | BUG_ON(buf_remaining > 3); |
| 333 | memcpy(&val, buf, buf_remaining); |
Doug Anderson | 96219c3 | 2011-08-30 11:46:10 -0600 | [diff] [blame] | 334 | |
| 335 | /* Again update before writing to FIFO to make sure isr sees. */ |
| 336 | i2c_dev->msg_buf_remaining = 0; |
| 337 | i2c_dev->msg_buf = NULL; |
| 338 | barrier(); |
| 339 | |
Colin Cross | db811ca | 2011-02-20 17:14:21 -0800 | [diff] [blame] | 340 | i2c_writel(i2c_dev, val, I2C_TX_FIFO); |
Colin Cross | db811ca | 2011-02-20 17:14:21 -0800 | [diff] [blame] | 341 | } |
| 342 | |
Colin Cross | db811ca | 2011-02-20 17:14:21 -0800 | [diff] [blame] | 343 | return 0; |
| 344 | } |
| 345 | |
| 346 | /* |
| 347 | * One of the Tegra I2C blocks is inside the DVC (Digital Voltage Controller) |
| 348 | * block. This block is identical to the rest of the I2C blocks, except that |
| 349 | * it only supports master mode, it has registers moved around, and it needs |
| 350 | * some extra init to get it into I2C mode. The register moves are handled |
| 351 | * by i2c_readl and i2c_writel |
| 352 | */ |
| 353 | static void tegra_dvc_init(struct tegra_i2c_dev *i2c_dev) |
| 354 | { |
| 355 | u32 val = 0; |
| 356 | val = dvc_readl(i2c_dev, DVC_CTRL_REG3); |
| 357 | val |= DVC_CTRL_REG3_SW_PROG; |
| 358 | val |= DVC_CTRL_REG3_I2C_DONE_INTR_EN; |
| 359 | dvc_writel(i2c_dev, val, DVC_CTRL_REG3); |
| 360 | |
| 361 | val = dvc_readl(i2c_dev, DVC_CTRL_REG1); |
| 362 | val |= DVC_CTRL_REG1_INTR_EN; |
| 363 | dvc_writel(i2c_dev, val, DVC_CTRL_REG1); |
| 364 | } |
| 365 | |
| 366 | static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev) |
| 367 | { |
| 368 | u32 val; |
| 369 | int err = 0; |
| 370 | |
Laxman Dewangan | 14e92bd | 2012-08-08 13:21:32 +0530 | [diff] [blame] | 371 | clk_prepare_enable(i2c_dev->div_clk); |
Colin Cross | db811ca | 2011-02-20 17:14:21 -0800 | [diff] [blame] | 372 | |
Laxman Dewangan | 14e92bd | 2012-08-08 13:21:32 +0530 | [diff] [blame] | 373 | tegra_periph_reset_assert(i2c_dev->div_clk); |
Colin Cross | db811ca | 2011-02-20 17:14:21 -0800 | [diff] [blame] | 374 | udelay(2); |
Laxman Dewangan | 14e92bd | 2012-08-08 13:21:32 +0530 | [diff] [blame] | 375 | tegra_periph_reset_deassert(i2c_dev->div_clk); |
Colin Cross | db811ca | 2011-02-20 17:14:21 -0800 | [diff] [blame] | 376 | |
| 377 | if (i2c_dev->is_dvc) |
| 378 | tegra_dvc_init(i2c_dev); |
| 379 | |
Jay Cheng | 40abcf7 | 2011-04-25 15:32:27 -0600 | [diff] [blame] | 380 | val = I2C_CNFG_NEW_MASTER_FSM | I2C_CNFG_PACKET_MODE_EN | |
| 381 | (0x2 << I2C_CNFG_DEBOUNCE_CNT_SHIFT); |
Colin Cross | db811ca | 2011-02-20 17:14:21 -0800 | [diff] [blame] | 382 | i2c_writel(i2c_dev, val, I2C_CNFG); |
| 383 | i2c_writel(i2c_dev, 0, I2C_INT_MASK); |
Laxman Dewangan | 14e92bd | 2012-08-08 13:21:32 +0530 | [diff] [blame] | 384 | clk_set_rate(i2c_dev->div_clk, i2c_dev->bus_clk_rate * 8); |
Colin Cross | db811ca | 2011-02-20 17:14:21 -0800 | [diff] [blame] | 385 | |
Kenneth Waters | 65a1a0a | 2011-04-25 12:29:54 -0600 | [diff] [blame] | 386 | if (!i2c_dev->is_dvc) { |
| 387 | u32 sl_cfg = i2c_readl(i2c_dev, I2C_SL_CNFG); |
Stephen Warren | 5afa9d3 | 2011-06-06 11:25:19 -0600 | [diff] [blame] | 388 | sl_cfg |= I2C_SL_CNFG_NACK | I2C_SL_CNFG_NEWSL; |
| 389 | i2c_writel(i2c_dev, sl_cfg, I2C_SL_CNFG); |
| 390 | i2c_writel(i2c_dev, 0xfc, I2C_SL_ADDR1); |
| 391 | i2c_writel(i2c_dev, 0x00, I2C_SL_ADDR2); |
| 392 | |
Kenneth Waters | 65a1a0a | 2011-04-25 12:29:54 -0600 | [diff] [blame] | 393 | } |
| 394 | |
Colin Cross | db811ca | 2011-02-20 17:14:21 -0800 | [diff] [blame] | 395 | val = 7 << I2C_FIFO_CONTROL_TX_TRIG_SHIFT | |
| 396 | 0 << I2C_FIFO_CONTROL_RX_TRIG_SHIFT; |
| 397 | i2c_writel(i2c_dev, val, I2C_FIFO_CONTROL); |
| 398 | |
| 399 | if (tegra_i2c_flush_fifos(i2c_dev)) |
| 400 | err = -ETIMEDOUT; |
| 401 | |
Laxman Dewangan | 14e92bd | 2012-08-08 13:21:32 +0530 | [diff] [blame] | 402 | clk_disable_unprepare(i2c_dev->div_clk); |
Todd Poynor | cb63c62 | 2011-04-25 15:32:25 -0600 | [diff] [blame] | 403 | |
| 404 | if (i2c_dev->irq_disabled) { |
| 405 | i2c_dev->irq_disabled = 0; |
| 406 | enable_irq(i2c_dev->irq); |
| 407 | } |
| 408 | |
Colin Cross | db811ca | 2011-02-20 17:14:21 -0800 | [diff] [blame] | 409 | return err; |
| 410 | } |
| 411 | |
| 412 | static irqreturn_t tegra_i2c_isr(int irq, void *dev_id) |
| 413 | { |
| 414 | u32 status; |
| 415 | const u32 status_err = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST; |
| 416 | struct tegra_i2c_dev *i2c_dev = dev_id; |
| 417 | |
| 418 | status = i2c_readl(i2c_dev, I2C_INT_STATUS); |
| 419 | |
| 420 | if (status == 0) { |
Todd Poynor | cb63c62 | 2011-04-25 15:32:25 -0600 | [diff] [blame] | 421 | dev_warn(i2c_dev->dev, "irq status 0 %08x %08x %08x\n", |
| 422 | i2c_readl(i2c_dev, I2C_PACKET_TRANSFER_STATUS), |
| 423 | i2c_readl(i2c_dev, I2C_STATUS), |
| 424 | i2c_readl(i2c_dev, I2C_CNFG)); |
| 425 | i2c_dev->msg_err |= I2C_ERR_UNKNOWN_INTERRUPT; |
| 426 | |
| 427 | if (!i2c_dev->irq_disabled) { |
| 428 | disable_irq_nosync(i2c_dev->irq); |
| 429 | i2c_dev->irq_disabled = 1; |
| 430 | } |
Todd Poynor | cb63c62 | 2011-04-25 15:32:25 -0600 | [diff] [blame] | 431 | goto err; |
Colin Cross | db811ca | 2011-02-20 17:14:21 -0800 | [diff] [blame] | 432 | } |
| 433 | |
| 434 | if (unlikely(status & status_err)) { |
| 435 | if (status & I2C_INT_NO_ACK) |
| 436 | i2c_dev->msg_err |= I2C_ERR_NO_ACK; |
| 437 | if (status & I2C_INT_ARBITRATION_LOST) |
| 438 | i2c_dev->msg_err |= I2C_ERR_ARBITRATION_LOST; |
Colin Cross | db811ca | 2011-02-20 17:14:21 -0800 | [diff] [blame] | 439 | goto err; |
| 440 | } |
| 441 | |
| 442 | if (i2c_dev->msg_read && (status & I2C_INT_RX_FIFO_DATA_REQ)) { |
| 443 | if (i2c_dev->msg_buf_remaining) |
| 444 | tegra_i2c_empty_rx_fifo(i2c_dev); |
| 445 | else |
| 446 | BUG(); |
| 447 | } |
| 448 | |
| 449 | if (!i2c_dev->msg_read && (status & I2C_INT_TX_FIFO_DATA_REQ)) { |
| 450 | if (i2c_dev->msg_buf_remaining) |
| 451 | tegra_i2c_fill_tx_fifo(i2c_dev); |
| 452 | else |
| 453 | tegra_i2c_mask_irq(i2c_dev, I2C_INT_TX_FIFO_DATA_REQ); |
| 454 | } |
| 455 | |
Laxman Dewangan | c889e91 | 2012-05-07 12:16:19 +0530 | [diff] [blame] | 456 | i2c_writel(i2c_dev, status, I2C_INT_STATUS); |
| 457 | if (i2c_dev->is_dvc) |
| 458 | dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS); |
| 459 | |
Doug Anderson | 96219c3 | 2011-08-30 11:46:10 -0600 | [diff] [blame] | 460 | if (status & I2C_INT_PACKET_XFER_COMPLETE) { |
| 461 | BUG_ON(i2c_dev->msg_buf_remaining); |
Colin Cross | db811ca | 2011-02-20 17:14:21 -0800 | [diff] [blame] | 462 | complete(&i2c_dev->msg_complete); |
Doug Anderson | 96219c3 | 2011-08-30 11:46:10 -0600 | [diff] [blame] | 463 | } |
Colin Cross | db811ca | 2011-02-20 17:14:21 -0800 | [diff] [blame] | 464 | return IRQ_HANDLED; |
| 465 | err: |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 466 | /* An error occurred, mask all interrupts */ |
Colin Cross | db811ca | 2011-02-20 17:14:21 -0800 | [diff] [blame] | 467 | tegra_i2c_mask_irq(i2c_dev, I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST | |
| 468 | I2C_INT_PACKET_XFER_COMPLETE | I2C_INT_TX_FIFO_DATA_REQ | |
| 469 | I2C_INT_RX_FIFO_DATA_REQ); |
| 470 | i2c_writel(i2c_dev, status, I2C_INT_STATUS); |
Todd Poynor | cb63c62 | 2011-04-25 15:32:25 -0600 | [diff] [blame] | 471 | if (i2c_dev->is_dvc) |
| 472 | dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS); |
Laxman Dewangan | c889e91 | 2012-05-07 12:16:19 +0530 | [diff] [blame] | 473 | |
| 474 | complete(&i2c_dev->msg_complete); |
Colin Cross | db811ca | 2011-02-20 17:14:21 -0800 | [diff] [blame] | 475 | return IRQ_HANDLED; |
| 476 | } |
| 477 | |
| 478 | static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev, |
Laxman Dewangan | c8f5af2 | 2012-06-13 15:42:38 +0530 | [diff] [blame] | 479 | struct i2c_msg *msg, enum msg_end_type end_state) |
Colin Cross | db811ca | 2011-02-20 17:14:21 -0800 | [diff] [blame] | 480 | { |
| 481 | u32 packet_header; |
| 482 | u32 int_mask; |
| 483 | int ret; |
| 484 | |
| 485 | tegra_i2c_flush_fifos(i2c_dev); |
Colin Cross | db811ca | 2011-02-20 17:14:21 -0800 | [diff] [blame] | 486 | |
| 487 | if (msg->len == 0) |
| 488 | return -EINVAL; |
| 489 | |
| 490 | i2c_dev->msg_buf = msg->buf; |
| 491 | i2c_dev->msg_buf_remaining = msg->len; |
| 492 | i2c_dev->msg_err = I2C_ERR_NONE; |
| 493 | i2c_dev->msg_read = (msg->flags & I2C_M_RD); |
| 494 | INIT_COMPLETION(i2c_dev->msg_complete); |
| 495 | |
| 496 | packet_header = (0 << PACKET_HEADER0_HEADER_SIZE_SHIFT) | |
| 497 | PACKET_HEADER0_PROTOCOL_I2C | |
| 498 | (i2c_dev->cont_id << PACKET_HEADER0_CONT_ID_SHIFT) | |
| 499 | (1 << PACKET_HEADER0_PACKET_ID_SHIFT); |
| 500 | i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO); |
| 501 | |
| 502 | packet_header = msg->len - 1; |
| 503 | i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO); |
| 504 | |
Laxman Dewangan | 353f56b | 2012-04-24 12:49:35 +0530 | [diff] [blame] | 505 | packet_header = I2C_HEADER_IE_ENABLE; |
Laxman Dewangan | c8f5af2 | 2012-06-13 15:42:38 +0530 | [diff] [blame] | 506 | if (end_state == MSG_END_CONTINUE) |
| 507 | packet_header |= I2C_HEADER_CONTINUE_XFER; |
| 508 | else if (end_state == MSG_END_REPEAT_START) |
Erik Gilling | 2078cf3 | 2011-04-25 15:32:26 -0600 | [diff] [blame] | 509 | packet_header |= I2C_HEADER_REPEAT_START; |
Laxman Dewangan | 353f56b | 2012-04-24 12:49:35 +0530 | [diff] [blame] | 510 | if (msg->flags & I2C_M_TEN) { |
| 511 | packet_header |= msg->addr; |
Colin Cross | db811ca | 2011-02-20 17:14:21 -0800 | [diff] [blame] | 512 | packet_header |= I2C_HEADER_10BIT_ADDR; |
Laxman Dewangan | 353f56b | 2012-04-24 12:49:35 +0530 | [diff] [blame] | 513 | } else { |
| 514 | packet_header |= msg->addr << I2C_HEADER_SLAVE_ADDR_SHIFT; |
| 515 | } |
Colin Cross | db811ca | 2011-02-20 17:14:21 -0800 | [diff] [blame] | 516 | if (msg->flags & I2C_M_IGNORE_NAK) |
| 517 | packet_header |= I2C_HEADER_CONT_ON_NAK; |
Colin Cross | db811ca | 2011-02-20 17:14:21 -0800 | [diff] [blame] | 518 | if (msg->flags & I2C_M_RD) |
| 519 | packet_header |= I2C_HEADER_READ; |
| 520 | i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO); |
| 521 | |
| 522 | if (!(msg->flags & I2C_M_RD)) |
| 523 | tegra_i2c_fill_tx_fifo(i2c_dev); |
| 524 | |
| 525 | int_mask = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST; |
| 526 | if (msg->flags & I2C_M_RD) |
| 527 | int_mask |= I2C_INT_RX_FIFO_DATA_REQ; |
| 528 | else if (i2c_dev->msg_buf_remaining) |
| 529 | int_mask |= I2C_INT_TX_FIFO_DATA_REQ; |
| 530 | tegra_i2c_unmask_irq(i2c_dev, int_mask); |
| 531 | dev_dbg(i2c_dev->dev, "unmasked irq: %02x\n", |
| 532 | i2c_readl(i2c_dev, I2C_INT_MASK)); |
| 533 | |
| 534 | ret = wait_for_completion_timeout(&i2c_dev->msg_complete, TEGRA_I2C_TIMEOUT); |
| 535 | tegra_i2c_mask_irq(i2c_dev, int_mask); |
| 536 | |
| 537 | if (WARN_ON(ret == 0)) { |
| 538 | dev_err(i2c_dev->dev, "i2c transfer timed out\n"); |
| 539 | |
| 540 | tegra_i2c_init(i2c_dev); |
| 541 | return -ETIMEDOUT; |
| 542 | } |
| 543 | |
| 544 | dev_dbg(i2c_dev->dev, "transfer complete: %d %d %d\n", |
| 545 | ret, completion_done(&i2c_dev->msg_complete), i2c_dev->msg_err); |
| 546 | |
| 547 | if (likely(i2c_dev->msg_err == I2C_ERR_NONE)) |
| 548 | return 0; |
| 549 | |
Alok Chauhan | f70893d0 | 2012-04-02 11:23:02 +0530 | [diff] [blame] | 550 | /* |
| 551 | * NACK interrupt is generated before the I2C controller generates the |
| 552 | * STOP condition on the bus. So wait for 2 clock periods before resetting |
| 553 | * the controller so that STOP condition has been delivered properly. |
| 554 | */ |
| 555 | if (i2c_dev->msg_err == I2C_ERR_NO_ACK) |
| 556 | udelay(DIV_ROUND_UP(2 * 1000000, i2c_dev->bus_clk_rate)); |
| 557 | |
Colin Cross | db811ca | 2011-02-20 17:14:21 -0800 | [diff] [blame] | 558 | tegra_i2c_init(i2c_dev); |
| 559 | if (i2c_dev->msg_err == I2C_ERR_NO_ACK) { |
| 560 | if (msg->flags & I2C_M_IGNORE_NAK) |
| 561 | return 0; |
| 562 | return -EREMOTEIO; |
| 563 | } |
| 564 | |
| 565 | return -EIO; |
| 566 | } |
| 567 | |
| 568 | static int tegra_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], |
| 569 | int num) |
| 570 | { |
| 571 | struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap); |
| 572 | int i; |
| 573 | int ret = 0; |
| 574 | |
| 575 | if (i2c_dev->is_suspended) |
| 576 | return -EBUSY; |
| 577 | |
Laxman Dewangan | 14e92bd | 2012-08-08 13:21:32 +0530 | [diff] [blame] | 578 | clk_prepare_enable(i2c_dev->div_clk); |
Colin Cross | db811ca | 2011-02-20 17:14:21 -0800 | [diff] [blame] | 579 | for (i = 0; i < num; i++) { |
Laxman Dewangan | c8f5af2 | 2012-06-13 15:42:38 +0530 | [diff] [blame] | 580 | enum msg_end_type end_type = MSG_END_STOP; |
| 581 | if (i < (num - 1)) { |
| 582 | if (msgs[i + 1].flags & I2C_M_NOSTART) |
| 583 | end_type = MSG_END_CONTINUE; |
| 584 | else |
| 585 | end_type = MSG_END_REPEAT_START; |
| 586 | } |
| 587 | ret = tegra_i2c_xfer_msg(i2c_dev, &msgs[i], end_type); |
Colin Cross | db811ca | 2011-02-20 17:14:21 -0800 | [diff] [blame] | 588 | if (ret) |
| 589 | break; |
| 590 | } |
Laxman Dewangan | 14e92bd | 2012-08-08 13:21:32 +0530 | [diff] [blame] | 591 | clk_disable_unprepare(i2c_dev->div_clk); |
Colin Cross | db811ca | 2011-02-20 17:14:21 -0800 | [diff] [blame] | 592 | return ret ?: i; |
| 593 | } |
| 594 | |
| 595 | static u32 tegra_i2c_func(struct i2c_adapter *adap) |
| 596 | { |
Laxman Dewangan | 6ad068e | 2012-08-19 00:47:46 +0530 | [diff] [blame^] | 597 | struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap); |
| 598 | u32 ret = I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR | |
| 599 | I2C_FUNC_PROTOCOL_MANGLING; |
| 600 | |
| 601 | if (i2c_dev->hw->has_continue_xfer_support) |
| 602 | ret |= I2C_FUNC_NOSTART; |
| 603 | return ret; |
Colin Cross | db811ca | 2011-02-20 17:14:21 -0800 | [diff] [blame] | 604 | } |
| 605 | |
| 606 | static const struct i2c_algorithm tegra_i2c_algo = { |
| 607 | .master_xfer = tegra_i2c_xfer, |
| 608 | .functionality = tegra_i2c_func, |
| 609 | }; |
| 610 | |
Laxman Dewangan | 6ad068e | 2012-08-19 00:47:46 +0530 | [diff] [blame^] | 611 | static const struct tegra_i2c_hw_feature tegra20_i2c_hw = { |
| 612 | .has_continue_xfer_support = false, |
| 613 | }; |
| 614 | |
| 615 | static const struct tegra_i2c_hw_feature tegra30_i2c_hw = { |
| 616 | .has_continue_xfer_support = true, |
| 617 | }; |
| 618 | |
| 619 | #if defined(CONFIG_OF) |
| 620 | /* Match table for of_platform binding */ |
| 621 | static const struct of_device_id tegra_i2c_of_match[] __devinitconst = { |
| 622 | { .compatible = "nvidia,tegra30-i2c", .data = &tegra30_i2c_hw, }, |
| 623 | { .compatible = "nvidia,tegra20-i2c", .data = &tegra20_i2c_hw, }, |
| 624 | { .compatible = "nvidia,tegra20-i2c-dvc", .data = &tegra20_i2c_hw, }, |
| 625 | {}, |
| 626 | }; |
| 627 | MODULE_DEVICE_TABLE(of, tegra_i2c_of_match); |
| 628 | #endif |
| 629 | |
Stephen Warren | 92891da1 | 2011-12-17 23:29:29 -0700 | [diff] [blame] | 630 | static int __devinit tegra_i2c_probe(struct platform_device *pdev) |
Colin Cross | db811ca | 2011-02-20 17:14:21 -0800 | [diff] [blame] | 631 | { |
| 632 | struct tegra_i2c_dev *i2c_dev; |
| 633 | struct tegra_i2c_platform_data *pdata = pdev->dev.platform_data; |
| 634 | struct resource *res; |
Laxman Dewangan | 14e92bd | 2012-08-08 13:21:32 +0530 | [diff] [blame] | 635 | struct clk *div_clk; |
| 636 | struct clk *fast_clk; |
John Bonesio | 5c470f3 | 2011-06-22 09:16:56 -0700 | [diff] [blame] | 637 | const unsigned int *prop; |
Olof Johansson | f533c61 | 2011-10-12 17:33:00 -0700 | [diff] [blame] | 638 | void __iomem *base; |
Colin Cross | db811ca | 2011-02-20 17:14:21 -0800 | [diff] [blame] | 639 | int irq; |
| 640 | int ret = 0; |
| 641 | |
| 642 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 643 | if (!res) { |
| 644 | dev_err(&pdev->dev, "no mem resource\n"); |
| 645 | return -EINVAL; |
| 646 | } |
Colin Cross | db811ca | 2011-02-20 17:14:21 -0800 | [diff] [blame] | 647 | |
Laxman Dewangan | 9cbb6b2 | 2012-06-13 15:42:39 +0530 | [diff] [blame] | 648 | base = devm_request_and_ioremap(&pdev->dev, res); |
Colin Cross | db811ca | 2011-02-20 17:14:21 -0800 | [diff] [blame] | 649 | if (!base) { |
Laxman Dewangan | 9cbb6b2 | 2012-06-13 15:42:39 +0530 | [diff] [blame] | 650 | dev_err(&pdev->dev, "Cannot request/ioremap I2C registers\n"); |
| 651 | return -EADDRNOTAVAIL; |
Colin Cross | db811ca | 2011-02-20 17:14:21 -0800 | [diff] [blame] | 652 | } |
| 653 | |
| 654 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); |
| 655 | if (!res) { |
| 656 | dev_err(&pdev->dev, "no irq resource\n"); |
Laxman Dewangan | 9cbb6b2 | 2012-06-13 15:42:39 +0530 | [diff] [blame] | 657 | return -EINVAL; |
Colin Cross | db811ca | 2011-02-20 17:14:21 -0800 | [diff] [blame] | 658 | } |
| 659 | irq = res->start; |
| 660 | |
Laxman Dewangan | 14e92bd | 2012-08-08 13:21:32 +0530 | [diff] [blame] | 661 | div_clk = devm_clk_get(&pdev->dev, "div-clk"); |
| 662 | if (IS_ERR(div_clk)) { |
Colin Cross | db811ca | 2011-02-20 17:14:21 -0800 | [diff] [blame] | 663 | dev_err(&pdev->dev, "missing controller clock"); |
Laxman Dewangan | 14e92bd | 2012-08-08 13:21:32 +0530 | [diff] [blame] | 664 | return PTR_ERR(div_clk); |
Colin Cross | db811ca | 2011-02-20 17:14:21 -0800 | [diff] [blame] | 665 | } |
| 666 | |
Laxman Dewangan | 14e92bd | 2012-08-08 13:21:32 +0530 | [diff] [blame] | 667 | fast_clk = devm_clk_get(&pdev->dev, "fast-clk"); |
| 668 | if (IS_ERR(fast_clk)) { |
Colin Cross | db811ca | 2011-02-20 17:14:21 -0800 | [diff] [blame] | 669 | dev_err(&pdev->dev, "missing bus clock"); |
Laxman Dewangan | 14e92bd | 2012-08-08 13:21:32 +0530 | [diff] [blame] | 670 | return PTR_ERR(fast_clk); |
Colin Cross | db811ca | 2011-02-20 17:14:21 -0800 | [diff] [blame] | 671 | } |
| 672 | |
Laxman Dewangan | 9cbb6b2 | 2012-06-13 15:42:39 +0530 | [diff] [blame] | 673 | i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL); |
Colin Cross | db811ca | 2011-02-20 17:14:21 -0800 | [diff] [blame] | 674 | if (!i2c_dev) { |
Laxman Dewangan | 9cbb6b2 | 2012-06-13 15:42:39 +0530 | [diff] [blame] | 675 | dev_err(&pdev->dev, "Could not allocate struct tegra_i2c_dev"); |
| 676 | return -ENOMEM; |
Colin Cross | db811ca | 2011-02-20 17:14:21 -0800 | [diff] [blame] | 677 | } |
| 678 | |
| 679 | i2c_dev->base = base; |
Laxman Dewangan | 14e92bd | 2012-08-08 13:21:32 +0530 | [diff] [blame] | 680 | i2c_dev->div_clk = div_clk; |
| 681 | i2c_dev->fast_clk = fast_clk; |
Colin Cross | db811ca | 2011-02-20 17:14:21 -0800 | [diff] [blame] | 682 | i2c_dev->adapter.algo = &tegra_i2c_algo; |
| 683 | i2c_dev->irq = irq; |
| 684 | i2c_dev->cont_id = pdev->id; |
| 685 | i2c_dev->dev = &pdev->dev; |
John Bonesio | 5c470f3 | 2011-06-22 09:16:56 -0700 | [diff] [blame] | 686 | |
| 687 | i2c_dev->bus_clk_rate = 100000; /* default clock rate */ |
| 688 | if (pdata) { |
| 689 | i2c_dev->bus_clk_rate = pdata->bus_clk_rate; |
| 690 | |
| 691 | } else if (i2c_dev->dev->of_node) { /* if there is a device tree node ... */ |
| 692 | prop = of_get_property(i2c_dev->dev->of_node, |
| 693 | "clock-frequency", NULL); |
| 694 | if (prop) |
| 695 | i2c_dev->bus_clk_rate = be32_to_cpup(prop); |
| 696 | } |
Colin Cross | db811ca | 2011-02-20 17:14:21 -0800 | [diff] [blame] | 697 | |
Laxman Dewangan | 6ad068e | 2012-08-19 00:47:46 +0530 | [diff] [blame^] | 698 | i2c_dev->hw = &tegra20_i2c_hw; |
| 699 | |
| 700 | if (pdev->dev.of_node) { |
| 701 | const struct of_device_id *match; |
| 702 | match = of_match_device(of_match_ptr(tegra_i2c_of_match), |
| 703 | &pdev->dev); |
| 704 | i2c_dev->hw = match->data; |
Stephen Warren | 68fb669 | 2011-12-17 23:29:30 -0700 | [diff] [blame] | 705 | i2c_dev->is_dvc = of_device_is_compatible(pdev->dev.of_node, |
| 706 | "nvidia,tegra20-i2c-dvc"); |
Laxman Dewangan | 6ad068e | 2012-08-19 00:47:46 +0530 | [diff] [blame^] | 707 | } else if (pdev->id == 3) { |
Colin Cross | db811ca | 2011-02-20 17:14:21 -0800 | [diff] [blame] | 708 | i2c_dev->is_dvc = 1; |
Laxman Dewangan | 6ad068e | 2012-08-19 00:47:46 +0530 | [diff] [blame^] | 709 | } |
Colin Cross | db811ca | 2011-02-20 17:14:21 -0800 | [diff] [blame] | 710 | init_completion(&i2c_dev->msg_complete); |
| 711 | |
| 712 | platform_set_drvdata(pdev, i2c_dev); |
| 713 | |
| 714 | ret = tegra_i2c_init(i2c_dev); |
| 715 | if (ret) { |
| 716 | dev_err(&pdev->dev, "Failed to initialize i2c controller"); |
Laxman Dewangan | 9cbb6b2 | 2012-06-13 15:42:39 +0530 | [diff] [blame] | 717 | return ret; |
Colin Cross | db811ca | 2011-02-20 17:14:21 -0800 | [diff] [blame] | 718 | } |
| 719 | |
Laxman Dewangan | 9cbb6b2 | 2012-06-13 15:42:39 +0530 | [diff] [blame] | 720 | ret = devm_request_irq(&pdev->dev, i2c_dev->irq, |
| 721 | tegra_i2c_isr, 0, pdev->name, i2c_dev); |
Colin Cross | db811ca | 2011-02-20 17:14:21 -0800 | [diff] [blame] | 722 | if (ret) { |
| 723 | dev_err(&pdev->dev, "Failed to request irq %i\n", i2c_dev->irq); |
Laxman Dewangan | 9cbb6b2 | 2012-06-13 15:42:39 +0530 | [diff] [blame] | 724 | return ret; |
Colin Cross | db811ca | 2011-02-20 17:14:21 -0800 | [diff] [blame] | 725 | } |
| 726 | |
Laxman Dewangan | 14e92bd | 2012-08-08 13:21:32 +0530 | [diff] [blame] | 727 | clk_prepare_enable(i2c_dev->fast_clk); |
Colin Cross | db811ca | 2011-02-20 17:14:21 -0800 | [diff] [blame] | 728 | |
| 729 | i2c_set_adapdata(&i2c_dev->adapter, i2c_dev); |
| 730 | i2c_dev->adapter.owner = THIS_MODULE; |
| 731 | i2c_dev->adapter.class = I2C_CLASS_HWMON; |
| 732 | strlcpy(i2c_dev->adapter.name, "Tegra I2C adapter", |
| 733 | sizeof(i2c_dev->adapter.name)); |
| 734 | i2c_dev->adapter.algo = &tegra_i2c_algo; |
| 735 | i2c_dev->adapter.dev.parent = &pdev->dev; |
| 736 | i2c_dev->adapter.nr = pdev->id; |
John Bonesio | 5c470f3 | 2011-06-22 09:16:56 -0700 | [diff] [blame] | 737 | i2c_dev->adapter.dev.of_node = pdev->dev.of_node; |
Colin Cross | db811ca | 2011-02-20 17:14:21 -0800 | [diff] [blame] | 738 | |
| 739 | ret = i2c_add_numbered_adapter(&i2c_dev->adapter); |
| 740 | if (ret) { |
| 741 | dev_err(&pdev->dev, "Failed to add I2C adapter\n"); |
Laxman Dewangan | 14e92bd | 2012-08-08 13:21:32 +0530 | [diff] [blame] | 742 | clk_disable_unprepare(i2c_dev->fast_clk); |
Laxman Dewangan | 9cbb6b2 | 2012-06-13 15:42:39 +0530 | [diff] [blame] | 743 | return ret; |
Colin Cross | db811ca | 2011-02-20 17:14:21 -0800 | [diff] [blame] | 744 | } |
| 745 | |
John Bonesio | 5c470f3 | 2011-06-22 09:16:56 -0700 | [diff] [blame] | 746 | of_i2c_register_devices(&i2c_dev->adapter); |
| 747 | |
Colin Cross | db811ca | 2011-02-20 17:14:21 -0800 | [diff] [blame] | 748 | return 0; |
Colin Cross | db811ca | 2011-02-20 17:14:21 -0800 | [diff] [blame] | 749 | } |
| 750 | |
Stephen Warren | 92891da1 | 2011-12-17 23:29:29 -0700 | [diff] [blame] | 751 | static int __devexit tegra_i2c_remove(struct platform_device *pdev) |
Colin Cross | db811ca | 2011-02-20 17:14:21 -0800 | [diff] [blame] | 752 | { |
| 753 | struct tegra_i2c_dev *i2c_dev = platform_get_drvdata(pdev); |
| 754 | i2c_del_adapter(&i2c_dev->adapter); |
Colin Cross | db811ca | 2011-02-20 17:14:21 -0800 | [diff] [blame] | 755 | return 0; |
| 756 | } |
| 757 | |
Laxman Dewangan | 371e67c | 2012-08-18 17:49:58 +0530 | [diff] [blame] | 758 | #ifdef CONFIG_PM_SLEEP |
Wolfram Sang | 5db20c4 | 2012-07-24 17:32:45 +0200 | [diff] [blame] | 759 | static int tegra_i2c_suspend(struct device *dev) |
Colin Cross | db811ca | 2011-02-20 17:14:21 -0800 | [diff] [blame] | 760 | { |
Rafael J. Wysocki | 6a7b3c3 | 2012-07-11 21:27:30 +0200 | [diff] [blame] | 761 | struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev); |
Colin Cross | db811ca | 2011-02-20 17:14:21 -0800 | [diff] [blame] | 762 | |
| 763 | i2c_lock_adapter(&i2c_dev->adapter); |
| 764 | i2c_dev->is_suspended = true; |
| 765 | i2c_unlock_adapter(&i2c_dev->adapter); |
| 766 | |
| 767 | return 0; |
| 768 | } |
| 769 | |
Wolfram Sang | 5db20c4 | 2012-07-24 17:32:45 +0200 | [diff] [blame] | 770 | static int tegra_i2c_resume(struct device *dev) |
Colin Cross | db811ca | 2011-02-20 17:14:21 -0800 | [diff] [blame] | 771 | { |
Rafael J. Wysocki | 6a7b3c3 | 2012-07-11 21:27:30 +0200 | [diff] [blame] | 772 | struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev); |
Colin Cross | db811ca | 2011-02-20 17:14:21 -0800 | [diff] [blame] | 773 | int ret; |
| 774 | |
| 775 | i2c_lock_adapter(&i2c_dev->adapter); |
| 776 | |
| 777 | ret = tegra_i2c_init(i2c_dev); |
| 778 | |
| 779 | if (ret) { |
| 780 | i2c_unlock_adapter(&i2c_dev->adapter); |
| 781 | return ret; |
| 782 | } |
| 783 | |
| 784 | i2c_dev->is_suspended = false; |
| 785 | |
| 786 | i2c_unlock_adapter(&i2c_dev->adapter); |
| 787 | |
| 788 | return 0; |
| 789 | } |
Rafael J. Wysocki | 6a7b3c3 | 2012-07-11 21:27:30 +0200 | [diff] [blame] | 790 | |
Wolfram Sang | 5db20c4 | 2012-07-24 17:32:45 +0200 | [diff] [blame] | 791 | static SIMPLE_DEV_PM_OPS(tegra_i2c_pm, tegra_i2c_suspend, tegra_i2c_resume); |
Rafael J. Wysocki | 6a7b3c3 | 2012-07-11 21:27:30 +0200 | [diff] [blame] | 792 | #define TEGRA_I2C_PM (&tegra_i2c_pm) |
| 793 | #else |
| 794 | #define TEGRA_I2C_PM NULL |
Colin Cross | db811ca | 2011-02-20 17:14:21 -0800 | [diff] [blame] | 795 | #endif |
| 796 | |
| 797 | static struct platform_driver tegra_i2c_driver = { |
| 798 | .probe = tegra_i2c_probe, |
Shubhrajyoti Datta | 218d06d | 2011-12-20 11:45:08 +0530 | [diff] [blame] | 799 | .remove = __devexit_p(tegra_i2c_remove), |
Colin Cross | db811ca | 2011-02-20 17:14:21 -0800 | [diff] [blame] | 800 | .driver = { |
| 801 | .name = "tegra-i2c", |
| 802 | .owner = THIS_MODULE, |
Laxman Dewangan | 02d8bf8 | 2012-07-10 16:50:42 +0530 | [diff] [blame] | 803 | .of_match_table = of_match_ptr(tegra_i2c_of_match), |
Rafael J. Wysocki | 6a7b3c3 | 2012-07-11 21:27:30 +0200 | [diff] [blame] | 804 | .pm = TEGRA_I2C_PM, |
Colin Cross | db811ca | 2011-02-20 17:14:21 -0800 | [diff] [blame] | 805 | }, |
| 806 | }; |
| 807 | |
| 808 | static int __init tegra_i2c_init_driver(void) |
| 809 | { |
| 810 | return platform_driver_register(&tegra_i2c_driver); |
| 811 | } |
| 812 | |
| 813 | static void __exit tegra_i2c_exit_driver(void) |
| 814 | { |
| 815 | platform_driver_unregister(&tegra_i2c_driver); |
| 816 | } |
| 817 | |
| 818 | subsys_initcall(tegra_i2c_init_driver); |
| 819 | module_exit(tegra_i2c_exit_driver); |
| 820 | |
| 821 | MODULE_DESCRIPTION("nVidia Tegra2 I2C Bus Controller driver"); |
| 822 | MODULE_AUTHOR("Colin Cross"); |
| 823 | MODULE_LICENSE("GPL v2"); |