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Andrew Vasquezfa90c542005-10-27 11:10:08 -07001/*
2 * QLogic Fibre Channel HBA Driver
Andrew Vasquez01e58d82008-04-03 13:13:13 -07003 * Copyright (c) 2003-2008 QLogic Corporation
Andrew Vasquezfa90c542005-10-27 11:10:08 -07004 *
5 * See LICENSE.qla2xxx for copyright and licensing details.
6 */
Linus Torvalds1da177e2005-04-16 15:20:36 -07007#ifndef __QLA_DEF_H
8#define __QLA_DEF_H
9
10#include <linux/kernel.h>
11#include <linux/init.h>
12#include <linux/types.h>
13#include <linux/module.h>
14#include <linux/list.h>
15#include <linux/pci.h>
16#include <linux/dma-mapping.h>
17#include <linux/sched.h>
18#include <linux/slab.h>
19#include <linux/dmapool.h>
20#include <linux/mempool.h>
21#include <linux/spinlock.h>
22#include <linux/completion.h>
Andrew Vasquezabbd8872005-07-06 10:30:05 -070023#include <linux/interrupt.h>
James.Smart@Emulex.Com19a7b4a2005-10-18 12:03:35 -040024#include <linux/workqueue.h>
Andrew Vasquez54333832005-11-09 15:49:04 -080025#include <linux/firmware.h>
Seokmann Ju14e660e2007-09-20 14:07:36 -070026#include <linux/aer.h>
Harihara Kadayam4d4df192008-04-03 13:13:26 -070027#include <linux/mutex.h>
Matthew Wilcox6188e102008-04-18 22:21:05 -040028#include <linux/semaphore.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070029
30#include <scsi/scsi.h>
31#include <scsi/scsi_host.h>
32#include <scsi/scsi_device.h>
33#include <scsi/scsi_cmnd.h>
andrew.vasquez@qlogic.com392e2f62006-01-31 16:05:02 -080034#include <scsi/scsi_transport_fc.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070035
Andrew Vasquezcb630672006-05-17 15:09:45 -070036#define QLA2XXX_DRIVER_NAME "qla2xxx"
37
Linus Torvalds1da177e2005-04-16 15:20:36 -070038/*
39 * We have MAILBOX_REGISTER_COUNT sized arrays in a few places,
40 * but that's fine as we don't look at the last 24 ones for
41 * ISP2100 HBAs.
42 */
43#define MAILBOX_REGISTER_COUNT_2100 8
44#define MAILBOX_REGISTER_COUNT 32
45
46#define QLA2200A_RISC_ROM_VER 4
47#define FPM_2300 6
48#define FPM_2310 7
49
50#include "qla_settings.h"
51
Andrew Vasquezfa2a1ce2005-07-06 10:32:07 -070052/*
Linus Torvalds1da177e2005-04-16 15:20:36 -070053 * Data bit definitions
54 */
55#define BIT_0 0x1
56#define BIT_1 0x2
57#define BIT_2 0x4
58#define BIT_3 0x8
59#define BIT_4 0x10
60#define BIT_5 0x20
61#define BIT_6 0x40
62#define BIT_7 0x80
63#define BIT_8 0x100
64#define BIT_9 0x200
65#define BIT_10 0x400
66#define BIT_11 0x800
67#define BIT_12 0x1000
68#define BIT_13 0x2000
69#define BIT_14 0x4000
70#define BIT_15 0x8000
71#define BIT_16 0x10000
72#define BIT_17 0x20000
73#define BIT_18 0x40000
74#define BIT_19 0x80000
75#define BIT_20 0x100000
76#define BIT_21 0x200000
77#define BIT_22 0x400000
78#define BIT_23 0x800000
79#define BIT_24 0x1000000
80#define BIT_25 0x2000000
81#define BIT_26 0x4000000
82#define BIT_27 0x8000000
83#define BIT_28 0x10000000
84#define BIT_29 0x20000000
85#define BIT_30 0x40000000
86#define BIT_31 0x80000000
87
88#define LSB(x) ((uint8_t)(x))
89#define MSB(x) ((uint8_t)((uint16_t)(x) >> 8))
90
91#define LSW(x) ((uint16_t)(x))
92#define MSW(x) ((uint16_t)((uint32_t)(x) >> 16))
93
94#define LSD(x) ((uint32_t)((uint64_t)(x)))
95#define MSD(x) ((uint32_t)((((uint64_t)(x)) >> 16) >> 16))
96
97
98/*
99 * I/O register
100*/
101
102#define RD_REG_BYTE(addr) readb(addr)
103#define RD_REG_WORD(addr) readw(addr)
104#define RD_REG_DWORD(addr) readl(addr)
105#define RD_REG_BYTE_RELAXED(addr) readb_relaxed(addr)
106#define RD_REG_WORD_RELAXED(addr) readw_relaxed(addr)
107#define RD_REG_DWORD_RELAXED(addr) readl_relaxed(addr)
108#define WRT_REG_BYTE(addr, data) writeb(data,addr)
109#define WRT_REG_WORD(addr, data) writew(data,addr)
110#define WRT_REG_DWORD(addr, data) writel(data,addr)
111
112/*
andrew.vasquez@qlogic.comf6df1442006-01-31 16:05:07 -0800113 * The ISP2312 v2 chip cannot access the FLASH/GPIO registers via MMIO in an
114 * 133Mhz slot.
115 */
116#define RD_REG_WORD_PIO(addr) (inw((unsigned long)addr))
117#define WRT_REG_WORD_PIO(addr, data) (outw(data,(unsigned long)addr))
118
119/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700120 * Fibre Channel device definitions.
121 */
122#define WWN_SIZE 8 /* Size of WWPN, WWN & WWNN */
123#define MAX_FIBRE_DEVICES 512
Andrew Vasquezcc4731f2005-07-06 10:32:37 -0700124#define MAX_FIBRE_LUNS 0xFFFF
Linus Torvalds1da177e2005-04-16 15:20:36 -0700125#define MAX_RSCN_COUNT 32
126#define MAX_HOST_COUNT 16
127
128/*
129 * Host adapter default definitions.
130 */
131#define MAX_BUSES 1 /* We only have one bus today */
132#define MAX_TARGETS_2100 MAX_FIBRE_DEVICES
133#define MAX_TARGETS_2200 MAX_FIBRE_DEVICES
Linus Torvalds1da177e2005-04-16 15:20:36 -0700134#define MIN_LUNS 8
135#define MAX_LUNS MAX_FIBRE_LUNS
Andrew Vasquezfa2a1ce2005-07-06 10:32:07 -0700136#define MAX_CMDS_PER_LUN 255
137
Linus Torvalds1da177e2005-04-16 15:20:36 -0700138/*
139 * Fibre Channel device definitions.
140 */
141#define SNS_LAST_LOOP_ID_2100 0xfe
142#define SNS_LAST_LOOP_ID_2300 0x7ff
143
144#define LAST_LOCAL_LOOP_ID 0x7d
145#define SNS_FL_PORT 0x7e
146#define FABRIC_CONTROLLER 0x7f
147#define SIMPLE_NAME_SERVER 0x80
148#define SNS_FIRST_LOOP_ID 0x81
149#define MANAGEMENT_SERVER 0xfe
150#define BROADCAST 0xff
151
Andrew Vasquez3d716442005-07-06 10:30:26 -0700152/*
153 * There is no correspondence between an N-PORT id and an AL_PA. Therefore the
154 * valid range of an N-PORT id is 0 through 0x7ef.
155 */
156#define NPH_LAST_HANDLE 0x7ef
Andrew Vasquezcca53352005-08-26 19:08:30 -0700157#define NPH_MGMT_SERVER 0x7fa /* FFFFFA */
Andrew Vasquez3d716442005-07-06 10:30:26 -0700158#define NPH_SNS 0x7fc /* FFFFFC */
159#define NPH_FABRIC_CONTROLLER 0x7fd /* FFFFFD */
160#define NPH_F_PORT 0x7fe /* FFFFFE */
161#define NPH_IP_BROADCAST 0x7ff /* FFFFFF */
162
163#define MAX_CMDSZ 16 /* SCSI maximum CDB size. */
164#include "qla_fw.h"
Linus Torvalds1da177e2005-04-16 15:20:36 -0700165
166/*
167 * Timeout timer counts in seconds
168 */
8482e1182005-04-17 15:04:54 -0500169#define PORT_RETRY_TIME 1
Linus Torvalds1da177e2005-04-16 15:20:36 -0700170#define LOOP_DOWN_TIMEOUT 60
171#define LOOP_DOWN_TIME 255 /* 240 */
172#define LOOP_DOWN_RESET (LOOP_DOWN_TIME - 30)
173
174/* Maximum outstanding commands in ISP queues (1-65535) */
175#define MAX_OUTSTANDING_COMMANDS 1024
176
177/* ISP request and response entry counts (37-65535) */
178#define REQUEST_ENTRY_CNT_2100 128 /* Number of request entries. */
179#define REQUEST_ENTRY_CNT_2200 2048 /* Number of request entries. */
180#define REQUEST_ENTRY_CNT_2XXX_EXT_MEM 4096 /* Number of request entries. */
Andrew Vasquez3d716442005-07-06 10:30:26 -0700181#define REQUEST_ENTRY_CNT_24XX 4096 /* Number of request entries. */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700182#define RESPONSE_ENTRY_CNT_2100 64 /* Number of response entries.*/
183#define RESPONSE_ENTRY_CNT_2300 512 /* Number of response entries.*/
184
185/*
Andrew Vasquezfa2a1ce2005-07-06 10:32:07 -0700186 * SCSI Request Block
Linus Torvalds1da177e2005-04-16 15:20:36 -0700187 */
188typedef struct srb {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700189 struct scsi_qla_host *ha; /* HA the SP is queued on */
bdf79622005-04-17 15:06:53 -0500190 struct fc_port *fcport;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700191
192 struct scsi_cmnd *cmd; /* Linux SCSI command pkt */
193
Linus Torvalds1da177e2005-04-16 15:20:36 -0700194 uint16_t flags;
195
Linus Torvalds1da177e2005-04-16 15:20:36 -0700196 uint32_t request_sense_length;
197 uint8_t *request_sense_ptr;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700198} srb_t;
199
200/*
201 * SRB flag definitions
202 */
203#define SRB_TIMEOUT BIT_0 /* Command timed out */
204#define SRB_DMA_VALID BIT_1 /* Command sent to ISP */
205#define SRB_WATCHDOG BIT_2 /* Command on watchdog list */
206#define SRB_ABORT_PENDING BIT_3 /* Command abort sent to device */
207
208#define SRB_ABORTED BIT_4 /* Command aborted command already */
209#define SRB_RETRY BIT_5 /* Command needs retrying */
210#define SRB_GOT_SENSE BIT_6 /* Command has sense data */
211#define SRB_FAILOVER BIT_7 /* Command in failover state */
212
213#define SRB_BUSY BIT_8 /* Command is in busy retry state */
214#define SRB_FO_CANCEL BIT_9 /* Command don't need to do failover */
215#define SRB_IOCTL BIT_10 /* IOCTL command. */
216#define SRB_TAPE BIT_11 /* FCP2 (Tape) command. */
217
218/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700219 * ISP I/O Register Set structure definitions.
220 */
Andrew Vasquez3d716442005-07-06 10:30:26 -0700221struct device_reg_2xxx {
222 uint16_t flash_address; /* Flash BIOS address */
223 uint16_t flash_data; /* Flash BIOS data */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700224 uint16_t unused_1[1]; /* Gap */
Andrew Vasquez3d716442005-07-06 10:30:26 -0700225 uint16_t ctrl_status; /* Control/Status */
Andrew Vasquezfa2a1ce2005-07-06 10:32:07 -0700226#define CSR_FLASH_64K_BANK BIT_3 /* Flash upper 64K bank select */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700227#define CSR_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable */
228#define CSR_ISP_SOFT_RESET BIT_0 /* ISP soft reset */
229
Andrew Vasquez3d716442005-07-06 10:30:26 -0700230 uint16_t ictrl; /* Interrupt control */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700231#define ICR_EN_INT BIT_15 /* ISP enable interrupts. */
232#define ICR_EN_RISC BIT_3 /* ISP enable RISC interrupts. */
233
Andrew Vasquez3d716442005-07-06 10:30:26 -0700234 uint16_t istatus; /* Interrupt status */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700235#define ISR_RISC_INT BIT_3 /* RISC interrupt */
236
Andrew Vasquez3d716442005-07-06 10:30:26 -0700237 uint16_t semaphore; /* Semaphore */
238 uint16_t nvram; /* NVRAM register. */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700239#define NVR_DESELECT 0
240#define NVR_BUSY BIT_15
241#define NVR_WRT_ENABLE BIT_14 /* Write enable */
242#define NVR_PR_ENABLE BIT_13 /* Protection register enable */
243#define NVR_DATA_IN BIT_3
244#define NVR_DATA_OUT BIT_2
245#define NVR_SELECT BIT_1
246#define NVR_CLOCK BIT_0
247
Ravi Anand45aeaf12006-05-17 15:08:49 -0700248#define NVR_WAIT_CNT 20000
249
Linus Torvalds1da177e2005-04-16 15:20:36 -0700250 union {
251 struct {
Andrew Vasquez3d716442005-07-06 10:30:26 -0700252 uint16_t mailbox0;
253 uint16_t mailbox1;
254 uint16_t mailbox2;
255 uint16_t mailbox3;
256 uint16_t mailbox4;
257 uint16_t mailbox5;
258 uint16_t mailbox6;
259 uint16_t mailbox7;
260 uint16_t unused_2[59]; /* Gap */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700261 } __attribute__((packed)) isp2100;
262 struct {
Andrew Vasquez3d716442005-07-06 10:30:26 -0700263 /* Request Queue */
264 uint16_t req_q_in; /* In-Pointer */
265 uint16_t req_q_out; /* Out-Pointer */
266 /* Response Queue */
267 uint16_t rsp_q_in; /* In-Pointer */
268 uint16_t rsp_q_out; /* Out-Pointer */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700269
270 /* RISC to Host Status */
Andrew Vasquezfa2a1ce2005-07-06 10:32:07 -0700271 uint32_t host_status;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700272#define HSR_RISC_INT BIT_15 /* RISC interrupt */
273#define HSR_RISC_PAUSED BIT_8 /* RISC Paused */
274
275 /* Host to Host Semaphore */
Andrew Vasquezfa2a1ce2005-07-06 10:32:07 -0700276 uint16_t host_semaphore;
Andrew Vasquez3d716442005-07-06 10:30:26 -0700277 uint16_t unused_3[17]; /* Gap */
278 uint16_t mailbox0;
279 uint16_t mailbox1;
280 uint16_t mailbox2;
281 uint16_t mailbox3;
282 uint16_t mailbox4;
283 uint16_t mailbox5;
284 uint16_t mailbox6;
285 uint16_t mailbox7;
286 uint16_t mailbox8;
287 uint16_t mailbox9;
288 uint16_t mailbox10;
289 uint16_t mailbox11;
290 uint16_t mailbox12;
291 uint16_t mailbox13;
292 uint16_t mailbox14;
293 uint16_t mailbox15;
294 uint16_t mailbox16;
295 uint16_t mailbox17;
296 uint16_t mailbox18;
297 uint16_t mailbox19;
298 uint16_t mailbox20;
299 uint16_t mailbox21;
300 uint16_t mailbox22;
301 uint16_t mailbox23;
302 uint16_t mailbox24;
303 uint16_t mailbox25;
304 uint16_t mailbox26;
305 uint16_t mailbox27;
306 uint16_t mailbox28;
307 uint16_t mailbox29;
308 uint16_t mailbox30;
309 uint16_t mailbox31;
310 uint16_t fb_cmd;
311 uint16_t unused_4[10]; /* Gap */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700312 } __attribute__((packed)) isp2300;
313 } u;
314
Andrew Vasquez3d716442005-07-06 10:30:26 -0700315 uint16_t fpm_diag_config;
Andrew Vasquezc81d04c2007-07-26 11:41:13 -0700316 uint16_t unused_5[0x4]; /* Gap */
317 uint16_t risc_hw;
318 uint16_t unused_5_1; /* Gap */
Andrew Vasquez3d716442005-07-06 10:30:26 -0700319 uint16_t pcr; /* Processor Control Register. */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700320 uint16_t unused_6[0x5]; /* Gap */
Andrew Vasquez3d716442005-07-06 10:30:26 -0700321 uint16_t mctr; /* Memory Configuration and Timing. */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700322 uint16_t unused_7[0x3]; /* Gap */
Andrew Vasquez3d716442005-07-06 10:30:26 -0700323 uint16_t fb_cmd_2100; /* Unused on 23XX */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700324 uint16_t unused_8[0x3]; /* Gap */
Andrew Vasquez3d716442005-07-06 10:30:26 -0700325 uint16_t hccr; /* Host command & control register. */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700326#define HCCR_HOST_INT BIT_7 /* Host interrupt bit */
327#define HCCR_RISC_PAUSE BIT_5 /* Pause mode bit */
328 /* HCCR commands */
329#define HCCR_RESET_RISC 0x1000 /* Reset RISC */
330#define HCCR_PAUSE_RISC 0x2000 /* Pause RISC */
331#define HCCR_RELEASE_RISC 0x3000 /* Release RISC from reset. */
332#define HCCR_SET_HOST_INT 0x5000 /* Set host interrupt */
333#define HCCR_CLR_HOST_INT 0x6000 /* Clear HOST interrupt */
334#define HCCR_CLR_RISC_INT 0x7000 /* Clear RISC interrupt */
335#define HCCR_DISABLE_PARITY_PAUSE 0x4001 /* Disable parity error RISC pause. */
336#define HCCR_ENABLE_PARITY 0xA000 /* Enable PARITY interrupt */
337
338 uint16_t unused_9[5]; /* Gap */
Andrew Vasquez3d716442005-07-06 10:30:26 -0700339 uint16_t gpiod; /* GPIO Data register. */
340 uint16_t gpioe; /* GPIO Enable register. */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700341#define GPIO_LED_MASK 0x00C0
342#define GPIO_LED_GREEN_OFF_AMBER_OFF 0x0000
343#define GPIO_LED_GREEN_ON_AMBER_OFF 0x0040
344#define GPIO_LED_GREEN_OFF_AMBER_ON 0x0080
345#define GPIO_LED_GREEN_ON_AMBER_ON 0x00C0
andrew.vasquez@qlogic.comf6df1442006-01-31 16:05:07 -0800346#define GPIO_LED_ALL_OFF 0x0000
347#define GPIO_LED_RED_ON_OTHER_OFF 0x0001 /* isp2322 */
348#define GPIO_LED_RGA_ON 0x00C1 /* isp2322: red green amber */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700349
350 union {
351 struct {
Andrew Vasquez3d716442005-07-06 10:30:26 -0700352 uint16_t unused_10[8]; /* Gap */
353 uint16_t mailbox8;
354 uint16_t mailbox9;
355 uint16_t mailbox10;
356 uint16_t mailbox11;
357 uint16_t mailbox12;
358 uint16_t mailbox13;
359 uint16_t mailbox14;
360 uint16_t mailbox15;
361 uint16_t mailbox16;
362 uint16_t mailbox17;
363 uint16_t mailbox18;
364 uint16_t mailbox19;
365 uint16_t mailbox20;
366 uint16_t mailbox21;
367 uint16_t mailbox22;
368 uint16_t mailbox23; /* Also probe reg. */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700369 } __attribute__((packed)) isp2200;
370 } u_end;
Andrew Vasquez3d716442005-07-06 10:30:26 -0700371};
372
Andrew Morton9a168bd2005-07-26 14:11:28 -0700373typedef union {
Andrew Vasquez3d716442005-07-06 10:30:26 -0700374 struct device_reg_2xxx isp;
375 struct device_reg_24xx isp24;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700376} device_reg_t;
377
378#define ISP_REQ_Q_IN(ha, reg) \
379 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
380 &(reg)->u.isp2100.mailbox4 : \
381 &(reg)->u.isp2300.req_q_in)
382#define ISP_REQ_Q_OUT(ha, reg) \
383 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
384 &(reg)->u.isp2100.mailbox4 : \
385 &(reg)->u.isp2300.req_q_out)
386#define ISP_RSP_Q_IN(ha, reg) \
387 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
388 &(reg)->u.isp2100.mailbox5 : \
389 &(reg)->u.isp2300.rsp_q_in)
390#define ISP_RSP_Q_OUT(ha, reg) \
391 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
392 &(reg)->u.isp2100.mailbox5 : \
393 &(reg)->u.isp2300.rsp_q_out)
394
395#define MAILBOX_REG(ha, reg, num) \
396 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
397 (num < 8 ? \
398 &(reg)->u.isp2100.mailbox0 + (num) : \
399 &(reg)->u_end.isp2200.mailbox8 + (num) - 8) : \
400 &(reg)->u.isp2300.mailbox0 + (num))
401#define RD_MAILBOX_REG(ha, reg, num) \
402 RD_REG_WORD(MAILBOX_REG(ha, reg, num))
403#define WRT_MAILBOX_REG(ha, reg, num, data) \
404 WRT_REG_WORD(MAILBOX_REG(ha, reg, num), data)
405
406#define FB_CMD_REG(ha, reg) \
407 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
408 &(reg)->fb_cmd_2100 : \
409 &(reg)->u.isp2300.fb_cmd)
410#define RD_FB_CMD_REG(ha, reg) \
411 RD_REG_WORD(FB_CMD_REG(ha, reg))
412#define WRT_FB_CMD_REG(ha, reg, data) \
413 WRT_REG_WORD(FB_CMD_REG(ha, reg), data)
414
415typedef struct {
416 uint32_t out_mb; /* outbound from driver */
417 uint32_t in_mb; /* Incoming from RISC */
418 uint16_t mb[MAILBOX_REGISTER_COUNT];
419 long buf_size;
420 void *bufp;
421 uint32_t tov;
422 uint8_t flags;
423#define MBX_DMA_IN BIT_0
424#define MBX_DMA_OUT BIT_1
425#define IOCTL_CMD BIT_2
426} mbx_cmd_t;
427
428#define MBX_TOV_SECONDS 30
429
430/*
431 * ISP product identification definitions in mailboxes after reset.
432 */
433#define PROD_ID_1 0x4953
434#define PROD_ID_2 0x0000
435#define PROD_ID_2a 0x5020
436#define PROD_ID_3 0x2020
437
438/*
439 * ISP mailbox Self-Test status codes
440 */
441#define MBS_FRM_ALIVE 0 /* Firmware Alive. */
442#define MBS_CHKSUM_ERR 1 /* Checksum Error. */
443#define MBS_BUSY 4 /* Busy. */
444
445/*
446 * ISP mailbox command complete status codes
447 */
448#define MBS_COMMAND_COMPLETE 0x4000
449#define MBS_INVALID_COMMAND 0x4001
450#define MBS_HOST_INTERFACE_ERROR 0x4002
451#define MBS_TEST_FAILED 0x4003
452#define MBS_COMMAND_ERROR 0x4005
453#define MBS_COMMAND_PARAMETER_ERROR 0x4006
454#define MBS_PORT_ID_USED 0x4007
455#define MBS_LOOP_ID_USED 0x4008
456#define MBS_ALL_IDS_IN_USE 0x4009
457#define MBS_NOT_LOGGED_IN 0x400A
Andrew Vasquez3d716442005-07-06 10:30:26 -0700458#define MBS_LINK_DOWN_ERROR 0x400B
459#define MBS_DIAG_ECHO_TEST_ERROR 0x400C
Linus Torvalds1da177e2005-04-16 15:20:36 -0700460
461/*
462 * ISP mailbox asynchronous event status codes
463 */
464#define MBA_ASYNC_EVENT 0x8000 /* Asynchronous event. */
465#define MBA_RESET 0x8001 /* Reset Detected. */
466#define MBA_SYSTEM_ERR 0x8002 /* System Error. */
467#define MBA_REQ_TRANSFER_ERR 0x8003 /* Request Transfer Error. */
468#define MBA_RSP_TRANSFER_ERR 0x8004 /* Response Transfer Error. */
469#define MBA_WAKEUP_THRES 0x8005 /* Request Queue Wake-up. */
470#define MBA_LIP_OCCURRED 0x8010 /* Loop Initialization Procedure */
471 /* occurred. */
472#define MBA_LOOP_UP 0x8011 /* FC Loop UP. */
473#define MBA_LOOP_DOWN 0x8012 /* FC Loop Down. */
474#define MBA_LIP_RESET 0x8013 /* LIP reset occurred. */
475#define MBA_PORT_UPDATE 0x8014 /* Port Database update. */
476#define MBA_RSCN_UPDATE 0x8015 /* Register State Chg Notification. */
477#define MBA_LIP_F8 0x8016 /* Received a LIP F8. */
478#define MBA_LOOP_INIT_ERR 0x8017 /* Loop Initialization Error. */
479#define MBA_FABRIC_AUTH_REQ 0x801b /* Fabric Authentication Required. */
480#define MBA_SCSI_COMPLETION 0x8020 /* SCSI Command Complete. */
481#define MBA_CTIO_COMPLETION 0x8021 /* CTIO Complete. */
482#define MBA_IP_COMPLETION 0x8022 /* IP Transmit Command Complete. */
483#define MBA_IP_RECEIVE 0x8023 /* IP Received. */
484#define MBA_IP_BROADCAST 0x8024 /* IP Broadcast Received. */
485#define MBA_IP_LOW_WATER_MARK 0x8025 /* IP Low Water Mark reached. */
486#define MBA_IP_RCV_BUFFER_EMPTY 0x8026 /* IP receive buffer queue empty. */
487#define MBA_IP_HDR_DATA_SPLIT 0x8027 /* IP header/data splitting feature */
488 /* used. */
Andrew Vasquez45ebeb52006-08-01 13:48:14 -0700489#define MBA_TRACE_NOTIFICATION 0x8028 /* Trace/Diagnostic notification. */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700490#define MBA_POINT_TO_POINT 0x8030 /* Point to point mode. */
491#define MBA_CMPLT_1_16BIT 0x8031 /* Completion 1 16bit IOSB. */
492#define MBA_CMPLT_2_16BIT 0x8032 /* Completion 2 16bit IOSB. */
493#define MBA_CMPLT_3_16BIT 0x8033 /* Completion 3 16bit IOSB. */
494#define MBA_CMPLT_4_16BIT 0x8034 /* Completion 4 16bit IOSB. */
495#define MBA_CMPLT_5_16BIT 0x8035 /* Completion 5 16bit IOSB. */
496#define MBA_CHG_IN_CONNECTION 0x8036 /* Change in connection mode. */
497#define MBA_RIO_RESPONSE 0x8040 /* RIO response queue update. */
498#define MBA_ZIO_RESPONSE 0x8040 /* ZIO response queue update. */
499#define MBA_CMPLT_2_32BIT 0x8042 /* Completion 2 32bit IOSB. */
500#define MBA_BYPASS_NOTIFICATION 0x8043 /* Auto bypass notification. */
501#define MBA_DISCARD_RND_FRAME 0x8048 /* discard RND frame due to error. */
502#define MBA_REJECTED_FCP_CMD 0x8049 /* rejected FCP_CMD. */
503
504/*
505 * Firmware options 1, 2, 3.
506 */
507#define FO1_AE_ON_LIPF8 BIT_0
508#define FO1_AE_ALL_LIP_RESET BIT_1
509#define FO1_CTIO_RETRY BIT_3
510#define FO1_DISABLE_LIP_F7_SW BIT_4
511#define FO1_DISABLE_100MS_LOS_WAIT BIT_5
Andrew Vasquez3d716442005-07-06 10:30:26 -0700512#define FO1_DISABLE_GPIO6_7 BIT_6 /* LED bits */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700513#define FO1_AE_ON_LOOP_INIT_ERR BIT_7
514#define FO1_SET_EMPHASIS_SWING BIT_8
515#define FO1_AE_AUTO_BYPASS BIT_9
516#define FO1_ENABLE_PURE_IOCB BIT_10
517#define FO1_AE_PLOGI_RJT BIT_11
518#define FO1_ENABLE_ABORT_SEQUENCE BIT_12
519#define FO1_AE_QUEUE_FULL BIT_13
520
521#define FO2_ENABLE_ATIO_TYPE_3 BIT_0
522#define FO2_REV_LOOPBACK BIT_1
523
524#define FO3_ENABLE_EMERG_IOCB BIT_0
525#define FO3_AE_RND_ERROR BIT_1
526
Andrew Vasquez3d716442005-07-06 10:30:26 -0700527/* 24XX additional firmware options */
528#define ADD_FO_COUNT 3
529#define ADD_FO1_DISABLE_GPIO_LED_CTRL BIT_6 /* LED bits */
530#define ADD_FO1_ENABLE_PUREX_IOCB BIT_10
531
532#define ADD_FO2_ENABLE_SEL_CLS2 BIT_5
533
534#define ADD_FO3_NO_ABT_ON_LINK_DOWN BIT_14
535
Linus Torvalds1da177e2005-04-16 15:20:36 -0700536/*
537 * ISP mailbox commands
538 */
539#define MBC_LOAD_RAM 1 /* Load RAM. */
540#define MBC_EXECUTE_FIRMWARE 2 /* Execute firmware. */
541#define MBC_WRITE_RAM_WORD 4 /* Write RAM word. */
542#define MBC_READ_RAM_WORD 5 /* Read RAM word. */
543#define MBC_MAILBOX_REGISTER_TEST 6 /* Wrap incoming mailboxes */
544#define MBC_VERIFY_CHECKSUM 7 /* Verify checksum. */
545#define MBC_GET_FIRMWARE_VERSION 8 /* Get firmware revision. */
546#define MBC_LOAD_RISC_RAM 9 /* Load RAM command. */
547#define MBC_DUMP_RISC_RAM 0xa /* Dump RAM command. */
548#define MBC_LOAD_RISC_RAM_EXTENDED 0xb /* Load RAM extended. */
549#define MBC_DUMP_RISC_RAM_EXTENDED 0xc /* Dump RAM extended. */
550#define MBC_WRITE_RAM_WORD_EXTENDED 0xd /* Write RAM word extended */
551#define MBC_READ_RAM_EXTENDED 0xf /* Read RAM extended. */
552#define MBC_IOCB_COMMAND 0x12 /* Execute IOCB command. */
Andrew Vasquezf6ef3b12005-08-26 19:10:20 -0700553#define MBC_STOP_FIRMWARE 0x14 /* Stop firmware. */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700554#define MBC_ABORT_COMMAND 0x15 /* Abort IOCB command. */
555#define MBC_ABORT_DEVICE 0x16 /* Abort device (ID/LUN). */
556#define MBC_ABORT_TARGET 0x17 /* Abort target (ID). */
557#define MBC_RESET 0x18 /* Reset. */
558#define MBC_GET_ADAPTER_LOOP_ID 0x20 /* Get loop id of ISP2200. */
559#define MBC_GET_RETRY_COUNT 0x22 /* Get f/w retry cnt/delay. */
560#define MBC_DISABLE_VI 0x24 /* Disable VI operation. */
561#define MBC_ENABLE_VI 0x25 /* Enable VI operation. */
562#define MBC_GET_FIRMWARE_OPTION 0x28 /* Get Firmware Options. */
563#define MBC_SET_FIRMWARE_OPTION 0x38 /* Set Firmware Options. */
564#define MBC_LOOP_PORT_BYPASS 0x40 /* Loop Port Bypass. */
565#define MBC_LOOP_PORT_ENABLE 0x41 /* Loop Port Enable. */
566#define MBC_GET_RESOURCE_COUNTS 0x42 /* Get Resource Counts. */
567#define MBC_NON_PARTICIPATE 0x43 /* Non-Participating Mode. */
568#define MBC_DIAGNOSTIC_ECHO 0x44 /* Diagnostic echo. */
569#define MBC_DIAGNOSTIC_LOOP_BACK 0x45 /* Diagnostic loop back. */
570#define MBC_ONLINE_SELF_TEST 0x46 /* Online self-test. */
571#define MBC_ENHANCED_GET_PORT_DATABASE 0x47 /* Get port database + login */
572#define MBC_RESET_LINK_STATUS 0x52 /* Reset Link Error Status */
573#define MBC_IOCB_COMMAND_A64 0x54 /* Execute IOCB command (64) */
574#define MBC_SEND_RNID_ELS 0x57 /* Send RNID ELS request */
575#define MBC_SET_RNID_PARAMS 0x59 /* Set RNID parameters */
576#define MBC_GET_RNID_PARAMS 0x5a /* Data Rate */
577#define MBC_DATA_RATE 0x5d /* Get RNID parameters */
578#define MBC_INITIALIZE_FIRMWARE 0x60 /* Initialize firmware */
579#define MBC_INITIATE_LIP 0x62 /* Initiate Loop */
580 /* Initialization Procedure */
581#define MBC_GET_FC_AL_POSITION_MAP 0x63 /* Get FC_AL Position Map. */
582#define MBC_GET_PORT_DATABASE 0x64 /* Get Port Database. */
583#define MBC_CLEAR_ACA 0x65 /* Clear ACA. */
584#define MBC_TARGET_RESET 0x66 /* Target Reset. */
585#define MBC_CLEAR_TASK_SET 0x67 /* Clear Task Set. */
586#define MBC_ABORT_TASK_SET 0x68 /* Abort Task Set. */
587#define MBC_GET_FIRMWARE_STATE 0x69 /* Get firmware state. */
588#define MBC_GET_PORT_NAME 0x6a /* Get port name. */
589#define MBC_GET_LINK_STATUS 0x6b /* Get port link status. */
590#define MBC_LIP_RESET 0x6c /* LIP reset. */
591#define MBC_SEND_SNS_COMMAND 0x6e /* Send Simple Name Server */
592 /* commandd. */
593#define MBC_LOGIN_FABRIC_PORT 0x6f /* Login fabric port. */
594#define MBC_SEND_CHANGE_REQUEST 0x70 /* Send Change Request. */
595#define MBC_LOGOUT_FABRIC_PORT 0x71 /* Logout fabric port. */
596#define MBC_LIP_FULL_LOGIN 0x72 /* Full login LIP. */
597#define MBC_LOGIN_LOOP_PORT 0x74 /* Login Loop Port. */
598#define MBC_PORT_NODE_NAME_LIST 0x75 /* Get port/node name list. */
599#define MBC_INITIALIZE_RECEIVE_QUEUE 0x77 /* Initialize receive queue */
600#define MBC_UNLOAD_IP 0x79 /* Shutdown IP */
601#define MBC_GET_ID_LIST 0x7C /* Get Port ID list. */
602#define MBC_SEND_LFA_COMMAND 0x7D /* Send Loop Fabric Address */
603#define MBC_LUN_RESET 0x7E /* Send LUN reset */
604
Andrew Vasquez3d716442005-07-06 10:30:26 -0700605/*
606 * ISP24xx mailbox commands
607 */
608#define MBC_SERDES_PARAMS 0x10 /* Serdes Tx Parameters. */
609#define MBC_GET_IOCB_STATUS 0x12 /* Get IOCB status command. */
Andrew Vasquezd8b45212006-10-02 12:00:43 -0700610#define MBC_PORT_PARAMS 0x1A /* Port iDMA Parameters. */
Andrew Vasquez3d716442005-07-06 10:30:26 -0700611#define MBC_GET_TIMEOUT_PARAMS 0x22 /* Get FW timeouts. */
Andrew Vasqueza7a167b2006-06-23 16:10:29 -0700612#define MBC_TRACE_CONTROL 0x27 /* Trace control command. */
Andrew Vasquez3d716442005-07-06 10:30:26 -0700613#define MBC_GEN_SYSTEM_ERROR 0x2a /* Generate System Error. */
Andrew Vasquez88729e52006-06-23 16:10:50 -0700614#define MBC_READ_SFP 0x31 /* Read SFP Data. */
Andrew Vasquez3d716442005-07-06 10:30:26 -0700615#define MBC_SET_TIMEOUT_PARAMS 0x32 /* Set FW timeouts. */
616#define MBC_MID_INITIALIZE_FIRMWARE 0x48 /* MID Initialize firmware. */
617#define MBC_MID_GET_VP_DATABASE 0x49 /* MID Get VP Database. */
618#define MBC_MID_GET_VP_ENTRY 0x4a /* MID Get VP Entry. */
619#define MBC_HOST_MEMORY_COPY 0x53 /* Host Memory Copy. */
620#define MBC_SEND_RNFT_ELS 0x5e /* Send RNFT ELS request */
621#define MBC_GET_LINK_PRIV_STATS 0x6d /* Get link & private data. */
622#define MBC_SET_VENDOR_ID 0x76 /* Set Vendor ID. */
623
Linus Torvalds1da177e2005-04-16 15:20:36 -0700624/* Firmware return data sizes */
625#define FCAL_MAP_SIZE 128
626
627/* Mailbox bit definitions for out_mb and in_mb */
628#define MBX_31 BIT_31
629#define MBX_30 BIT_30
630#define MBX_29 BIT_29
631#define MBX_28 BIT_28
632#define MBX_27 BIT_27
633#define MBX_26 BIT_26
634#define MBX_25 BIT_25
635#define MBX_24 BIT_24
636#define MBX_23 BIT_23
637#define MBX_22 BIT_22
638#define MBX_21 BIT_21
639#define MBX_20 BIT_20
640#define MBX_19 BIT_19
641#define MBX_18 BIT_18
642#define MBX_17 BIT_17
643#define MBX_16 BIT_16
644#define MBX_15 BIT_15
645#define MBX_14 BIT_14
646#define MBX_13 BIT_13
647#define MBX_12 BIT_12
648#define MBX_11 BIT_11
649#define MBX_10 BIT_10
650#define MBX_9 BIT_9
651#define MBX_8 BIT_8
652#define MBX_7 BIT_7
653#define MBX_6 BIT_6
654#define MBX_5 BIT_5
655#define MBX_4 BIT_4
656#define MBX_3 BIT_3
657#define MBX_2 BIT_2
658#define MBX_1 BIT_1
659#define MBX_0 BIT_0
660
661/*
662 * Firmware state codes from get firmware state mailbox command
663 */
664#define FSTATE_CONFIG_WAIT 0
665#define FSTATE_WAIT_AL_PA 1
666#define FSTATE_WAIT_LOGIN 2
667#define FSTATE_READY 3
668#define FSTATE_LOSS_OF_SYNC 4
669#define FSTATE_ERROR 5
670#define FSTATE_REINIT 6
671#define FSTATE_NON_PART 7
672
673#define FSTATE_CONFIG_CORRECT 0
674#define FSTATE_P2P_RCV_LIP 1
675#define FSTATE_P2P_CHOOSE_LOOP 2
676#define FSTATE_P2P_RCV_UNIDEN_LIP 3
677#define FSTATE_FATAL_ERROR 4
678#define FSTATE_LOOP_BACK_CONN 5
679
680/*
681 * Port Database structure definition
682 * Little endian except where noted.
683 */
684#define PORT_DATABASE_SIZE 128 /* bytes */
685typedef struct {
686 uint8_t options;
687 uint8_t control;
688 uint8_t master_state;
689 uint8_t slave_state;
690 uint8_t reserved[2];
691 uint8_t hard_address;
692 uint8_t reserved_1;
693 uint8_t port_id[4];
694 uint8_t node_name[WWN_SIZE];
695 uint8_t port_name[WWN_SIZE];
696 uint16_t execution_throttle;
697 uint16_t execution_count;
698 uint8_t reset_count;
699 uint8_t reserved_2;
700 uint16_t resource_allocation;
701 uint16_t current_allocation;
702 uint16_t queue_head;
703 uint16_t queue_tail;
704 uint16_t transmit_execution_list_next;
705 uint16_t transmit_execution_list_previous;
706 uint16_t common_features;
707 uint16_t total_concurrent_sequences;
708 uint16_t RO_by_information_category;
709 uint8_t recipient;
710 uint8_t initiator;
711 uint16_t receive_data_size;
712 uint16_t concurrent_sequences;
713 uint16_t open_sequences_per_exchange;
714 uint16_t lun_abort_flags;
715 uint16_t lun_stop_flags;
716 uint16_t stop_queue_head;
717 uint16_t stop_queue_tail;
718 uint16_t port_retry_timer;
719 uint16_t next_sequence_id;
720 uint16_t frame_count;
721 uint16_t PRLI_payload_length;
722 uint8_t prli_svc_param_word_0[2]; /* Big endian */
723 /* Bits 15-0 of word 0 */
724 uint8_t prli_svc_param_word_3[2]; /* Big endian */
725 /* Bits 15-0 of word 3 */
726 uint16_t loop_id;
727 uint16_t extended_lun_info_list_pointer;
728 uint16_t extended_lun_stop_list_pointer;
729} port_database_t;
730
731/*
732 * Port database slave/master states
733 */
734#define PD_STATE_DISCOVERY 0
735#define PD_STATE_WAIT_DISCOVERY_ACK 1
736#define PD_STATE_PORT_LOGIN 2
737#define PD_STATE_WAIT_PORT_LOGIN_ACK 3
738#define PD_STATE_PROCESS_LOGIN 4
739#define PD_STATE_WAIT_PROCESS_LOGIN_ACK 5
740#define PD_STATE_PORT_LOGGED_IN 6
741#define PD_STATE_PORT_UNAVAILABLE 7
742#define PD_STATE_PROCESS_LOGOUT 8
743#define PD_STATE_WAIT_PROCESS_LOGOUT_ACK 9
744#define PD_STATE_PORT_LOGOUT 10
745#define PD_STATE_WAIT_PORT_LOGOUT_ACK 11
746
747
Andrew Vasquez4fdfefe2005-10-27 11:09:48 -0700748#define QLA_ZIO_MODE_6 (BIT_2 | BIT_1)
749#define QLA_ZIO_DISABLED 0
750#define QLA_ZIO_DEFAULT_TIMER 2
751
Linus Torvalds1da177e2005-04-16 15:20:36 -0700752/*
753 * ISP Initialization Control Block.
754 * Little endian except where noted.
755 */
756#define ICB_VERSION 1
757typedef struct {
758 uint8_t version;
759 uint8_t reserved_1;
760
761 /*
762 * LSB BIT 0 = Enable Hard Loop Id
763 * LSB BIT 1 = Enable Fairness
764 * LSB BIT 2 = Enable Full-Duplex
765 * LSB BIT 3 = Enable Fast Posting
766 * LSB BIT 4 = Enable Target Mode
767 * LSB BIT 5 = Disable Initiator Mode
768 * LSB BIT 6 = Enable ADISC
769 * LSB BIT 7 = Enable Target Inquiry Data
770 *
771 * MSB BIT 0 = Enable PDBC Notify
772 * MSB BIT 1 = Non Participating LIP
773 * MSB BIT 2 = Descending Loop ID Search
774 * MSB BIT 3 = Acquire Loop ID in LIPA
775 * MSB BIT 4 = Stop PortQ on Full Status
776 * MSB BIT 5 = Full Login after LIP
777 * MSB BIT 6 = Node Name Option
778 * MSB BIT 7 = Ext IFWCB enable bit
779 */
780 uint8_t firmware_options[2];
781
782 uint16_t frame_payload_size;
783 uint16_t max_iocb_allocation;
784 uint16_t execution_throttle;
785 uint8_t retry_count;
786 uint8_t retry_delay; /* unused */
787 uint8_t port_name[WWN_SIZE]; /* Big endian. */
788 uint16_t hard_address;
789 uint8_t inquiry_data;
790 uint8_t login_timeout;
791 uint8_t node_name[WWN_SIZE]; /* Big endian. */
792
793 uint16_t request_q_outpointer;
794 uint16_t response_q_inpointer;
795 uint16_t request_q_length;
796 uint16_t response_q_length;
797 uint32_t request_q_address[2];
798 uint32_t response_q_address[2];
799
800 uint16_t lun_enables;
801 uint8_t command_resource_count;
802 uint8_t immediate_notify_resource_count;
803 uint16_t timeout;
804 uint8_t reserved_2[2];
805
806 /*
807 * LSB BIT 0 = Timer Operation mode bit 0
808 * LSB BIT 1 = Timer Operation mode bit 1
809 * LSB BIT 2 = Timer Operation mode bit 2
810 * LSB BIT 3 = Timer Operation mode bit 3
811 * LSB BIT 4 = Init Config Mode bit 0
812 * LSB BIT 5 = Init Config Mode bit 1
813 * LSB BIT 6 = Init Config Mode bit 2
814 * LSB BIT 7 = Enable Non part on LIHA failure
815 *
816 * MSB BIT 0 = Enable class 2
817 * MSB BIT 1 = Enable ACK0
818 * MSB BIT 2 =
819 * MSB BIT 3 =
820 * MSB BIT 4 = FC Tape Enable
821 * MSB BIT 5 = Enable FC Confirm
822 * MSB BIT 6 = Enable command queuing in target mode
823 * MSB BIT 7 = No Logo On Link Down
824 */
825 uint8_t add_firmware_options[2];
826
827 uint8_t response_accumulation_timer;
828 uint8_t interrupt_delay_timer;
829
830 /*
831 * LSB BIT 0 = Enable Read xfr_rdy
832 * LSB BIT 1 = Soft ID only
833 * LSB BIT 2 =
834 * LSB BIT 3 =
835 * LSB BIT 4 = FCP RSP Payload [0]
836 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200
837 * LSB BIT 6 = Enable Out-of-Order frame handling
838 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop
839 *
840 * MSB BIT 0 = Sbus enable - 2300
841 * MSB BIT 1 =
842 * MSB BIT 2 =
843 * MSB BIT 3 =
Andrew Vasquez06c22bd2005-08-26 19:09:00 -0700844 * MSB BIT 4 = LED mode
Linus Torvalds1da177e2005-04-16 15:20:36 -0700845 * MSB BIT 5 = enable 50 ohm termination
846 * MSB BIT 6 = Data Rate (2300 only)
847 * MSB BIT 7 = Data Rate (2300 only)
848 */
849 uint8_t special_options[2];
850
851 uint8_t reserved_3[26];
852} init_cb_t;
853
854/*
855 * Get Link Status mailbox command return buffer.
856 */
Andrew Vasquez3d716442005-07-06 10:30:26 -0700857#define GLSO_SEND_RPS BIT_0
858#define GLSO_USE_DID BIT_3
859
Andrew Vasquez43ef0582008-01-17 09:02:08 -0800860struct link_statistics {
861 uint32_t link_fail_cnt;
862 uint32_t loss_sync_cnt;
863 uint32_t loss_sig_cnt;
864 uint32_t prim_seq_err_cnt;
865 uint32_t inval_xmit_word_cnt;
866 uint32_t inval_crc_cnt;
867 uint32_t unused1[0x1b];
868 uint32_t tx_frames;
869 uint32_t rx_frames;
870 uint32_t dumped_frames;
871 uint32_t unused2[2];
872 uint32_t nos_rcvd;
873};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700874
875/*
876 * NVRAM Command values.
877 */
878#define NV_START_BIT BIT_2
879#define NV_WRITE_OP (BIT_26+BIT_24)
880#define NV_READ_OP (BIT_26+BIT_25)
881#define NV_ERASE_OP (BIT_26+BIT_25+BIT_24)
882#define NV_MASK_OP (BIT_26+BIT_25+BIT_24)
883#define NV_DELAY_COUNT 10
884
885/*
886 * QLogic ISP2100, ISP2200 and ISP2300 NVRAM structure definition.
887 */
888typedef struct {
889 /*
890 * NVRAM header
891 */
892 uint8_t id[4];
893 uint8_t nvram_version;
894 uint8_t reserved_0;
895
896 /*
897 * NVRAM RISC parameter block
898 */
899 uint8_t parameter_block_version;
900 uint8_t reserved_1;
901
902 /*
903 * LSB BIT 0 = Enable Hard Loop Id
904 * LSB BIT 1 = Enable Fairness
905 * LSB BIT 2 = Enable Full-Duplex
906 * LSB BIT 3 = Enable Fast Posting
907 * LSB BIT 4 = Enable Target Mode
908 * LSB BIT 5 = Disable Initiator Mode
909 * LSB BIT 6 = Enable ADISC
910 * LSB BIT 7 = Enable Target Inquiry Data
911 *
912 * MSB BIT 0 = Enable PDBC Notify
913 * MSB BIT 1 = Non Participating LIP
914 * MSB BIT 2 = Descending Loop ID Search
915 * MSB BIT 3 = Acquire Loop ID in LIPA
916 * MSB BIT 4 = Stop PortQ on Full Status
917 * MSB BIT 5 = Full Login after LIP
918 * MSB BIT 6 = Node Name Option
919 * MSB BIT 7 = Ext IFWCB enable bit
920 */
921 uint8_t firmware_options[2];
922
923 uint16_t frame_payload_size;
924 uint16_t max_iocb_allocation;
925 uint16_t execution_throttle;
926 uint8_t retry_count;
927 uint8_t retry_delay; /* unused */
928 uint8_t port_name[WWN_SIZE]; /* Big endian. */
929 uint16_t hard_address;
930 uint8_t inquiry_data;
931 uint8_t login_timeout;
932 uint8_t node_name[WWN_SIZE]; /* Big endian. */
933
934 /*
935 * LSB BIT 0 = Timer Operation mode bit 0
936 * LSB BIT 1 = Timer Operation mode bit 1
937 * LSB BIT 2 = Timer Operation mode bit 2
938 * LSB BIT 3 = Timer Operation mode bit 3
939 * LSB BIT 4 = Init Config Mode bit 0
940 * LSB BIT 5 = Init Config Mode bit 1
941 * LSB BIT 6 = Init Config Mode bit 2
942 * LSB BIT 7 = Enable Non part on LIHA failure
943 *
944 * MSB BIT 0 = Enable class 2
945 * MSB BIT 1 = Enable ACK0
946 * MSB BIT 2 =
947 * MSB BIT 3 =
948 * MSB BIT 4 = FC Tape Enable
949 * MSB BIT 5 = Enable FC Confirm
950 * MSB BIT 6 = Enable command queuing in target mode
951 * MSB BIT 7 = No Logo On Link Down
952 */
953 uint8_t add_firmware_options[2];
954
955 uint8_t response_accumulation_timer;
956 uint8_t interrupt_delay_timer;
957
958 /*
959 * LSB BIT 0 = Enable Read xfr_rdy
960 * LSB BIT 1 = Soft ID only
961 * LSB BIT 2 =
962 * LSB BIT 3 =
963 * LSB BIT 4 = FCP RSP Payload [0]
964 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200
965 * LSB BIT 6 = Enable Out-of-Order frame handling
966 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop
967 *
968 * MSB BIT 0 = Sbus enable - 2300
969 * MSB BIT 1 =
970 * MSB BIT 2 =
971 * MSB BIT 3 =
Andrew Vasquez06c22bd2005-08-26 19:09:00 -0700972 * MSB BIT 4 = LED mode
Linus Torvalds1da177e2005-04-16 15:20:36 -0700973 * MSB BIT 5 = enable 50 ohm termination
974 * MSB BIT 6 = Data Rate (2300 only)
975 * MSB BIT 7 = Data Rate (2300 only)
976 */
977 uint8_t special_options[2];
978
979 /* Reserved for expanded RISC parameter block */
980 uint8_t reserved_2[22];
981
982 /*
983 * LSB BIT 0 = Tx Sensitivity 1G bit 0
984 * LSB BIT 1 = Tx Sensitivity 1G bit 1
985 * LSB BIT 2 = Tx Sensitivity 1G bit 2
986 * LSB BIT 3 = Tx Sensitivity 1G bit 3
987 * LSB BIT 4 = Rx Sensitivity 1G bit 0
988 * LSB BIT 5 = Rx Sensitivity 1G bit 1
989 * LSB BIT 6 = Rx Sensitivity 1G bit 2
990 * LSB BIT 7 = Rx Sensitivity 1G bit 3
Andrew Vasquezfa2a1ce2005-07-06 10:32:07 -0700991 *
Linus Torvalds1da177e2005-04-16 15:20:36 -0700992 * MSB BIT 0 = Tx Sensitivity 2G bit 0
993 * MSB BIT 1 = Tx Sensitivity 2G bit 1
994 * MSB BIT 2 = Tx Sensitivity 2G bit 2
995 * MSB BIT 3 = Tx Sensitivity 2G bit 3
996 * MSB BIT 4 = Rx Sensitivity 2G bit 0
997 * MSB BIT 5 = Rx Sensitivity 2G bit 1
998 * MSB BIT 6 = Rx Sensitivity 2G bit 2
999 * MSB BIT 7 = Rx Sensitivity 2G bit 3
1000 *
1001 * LSB BIT 0 = Output Swing 1G bit 0
1002 * LSB BIT 1 = Output Swing 1G bit 1
1003 * LSB BIT 2 = Output Swing 1G bit 2
1004 * LSB BIT 3 = Output Emphasis 1G bit 0
1005 * LSB BIT 4 = Output Emphasis 1G bit 1
1006 * LSB BIT 5 = Output Swing 2G bit 0
1007 * LSB BIT 6 = Output Swing 2G bit 1
1008 * LSB BIT 7 = Output Swing 2G bit 2
Andrew Vasquezfa2a1ce2005-07-06 10:32:07 -07001009 *
Linus Torvalds1da177e2005-04-16 15:20:36 -07001010 * MSB BIT 0 = Output Emphasis 2G bit 0
1011 * MSB BIT 1 = Output Emphasis 2G bit 1
1012 * MSB BIT 2 = Output Enable
1013 * MSB BIT 3 =
1014 * MSB BIT 4 =
1015 * MSB BIT 5 =
1016 * MSB BIT 6 =
1017 * MSB BIT 7 =
1018 */
1019 uint8_t seriallink_options[4];
1020
1021 /*
1022 * NVRAM host parameter block
1023 *
1024 * LSB BIT 0 = Enable spinup delay
1025 * LSB BIT 1 = Disable BIOS
1026 * LSB BIT 2 = Enable Memory Map BIOS
1027 * LSB BIT 3 = Enable Selectable Boot
1028 * LSB BIT 4 = Disable RISC code load
1029 * LSB BIT 5 = Set cache line size 1
1030 * LSB BIT 6 = PCI Parity Disable
1031 * LSB BIT 7 = Enable extended logging
1032 *
1033 * MSB BIT 0 = Enable 64bit addressing
1034 * MSB BIT 1 = Enable lip reset
1035 * MSB BIT 2 = Enable lip full login
1036 * MSB BIT 3 = Enable target reset
1037 * MSB BIT 4 = Enable database storage
1038 * MSB BIT 5 = Enable cache flush read
1039 * MSB BIT 6 = Enable database load
1040 * MSB BIT 7 = Enable alternate WWN
1041 */
1042 uint8_t host_p[2];
1043
1044 uint8_t boot_node_name[WWN_SIZE];
1045 uint8_t boot_lun_number;
1046 uint8_t reset_delay;
1047 uint8_t port_down_retry_count;
1048 uint8_t boot_id_number;
1049 uint16_t max_luns_per_target;
1050 uint8_t fcode_boot_port_name[WWN_SIZE];
1051 uint8_t alternate_port_name[WWN_SIZE];
1052 uint8_t alternate_node_name[WWN_SIZE];
1053
1054 /*
1055 * BIT 0 = Selective Login
1056 * BIT 1 = Alt-Boot Enable
1057 * BIT 2 =
1058 * BIT 3 = Boot Order List
1059 * BIT 4 =
1060 * BIT 5 = Selective LUN
1061 * BIT 6 =
1062 * BIT 7 = unused
1063 */
1064 uint8_t efi_parameters;
1065
1066 uint8_t link_down_timeout;
1067
Andrew Vasquezcca53352005-08-26 19:08:30 -07001068 uint8_t adapter_id[16];
Linus Torvalds1da177e2005-04-16 15:20:36 -07001069
1070 uint8_t alt1_boot_node_name[WWN_SIZE];
1071 uint16_t alt1_boot_lun_number;
1072 uint8_t alt2_boot_node_name[WWN_SIZE];
1073 uint16_t alt2_boot_lun_number;
1074 uint8_t alt3_boot_node_name[WWN_SIZE];
1075 uint16_t alt3_boot_lun_number;
1076 uint8_t alt4_boot_node_name[WWN_SIZE];
1077 uint16_t alt4_boot_lun_number;
1078 uint8_t alt5_boot_node_name[WWN_SIZE];
1079 uint16_t alt5_boot_lun_number;
1080 uint8_t alt6_boot_node_name[WWN_SIZE];
1081 uint16_t alt6_boot_lun_number;
1082 uint8_t alt7_boot_node_name[WWN_SIZE];
1083 uint16_t alt7_boot_lun_number;
1084
1085 uint8_t reserved_3[2];
1086
1087 /* Offset 200-215 : Model Number */
1088 uint8_t model_number[16];
1089
1090 /* OEM related items */
1091 uint8_t oem_specific[16];
1092
1093 /*
1094 * NVRAM Adapter Features offset 232-239
1095 *
1096 * LSB BIT 0 = External GBIC
1097 * LSB BIT 1 = Risc RAM parity
1098 * LSB BIT 2 = Buffer Plus Module
1099 * LSB BIT 3 = Multi Chip Adapter
1100 * LSB BIT 4 = Internal connector
1101 * LSB BIT 5 =
1102 * LSB BIT 6 =
1103 * LSB BIT 7 =
1104 *
1105 * MSB BIT 0 =
1106 * MSB BIT 1 =
1107 * MSB BIT 2 =
1108 * MSB BIT 3 =
1109 * MSB BIT 4 =
1110 * MSB BIT 5 =
1111 * MSB BIT 6 =
1112 * MSB BIT 7 =
1113 */
1114 uint8_t adapter_features[2];
1115
1116 uint8_t reserved_4[16];
1117
1118 /* Subsystem vendor ID for ISP2200 */
1119 uint16_t subsystem_vendor_id_2200;
1120
1121 /* Subsystem device ID for ISP2200 */
1122 uint16_t subsystem_device_id_2200;
1123
1124 uint8_t reserved_5;
1125 uint8_t checksum;
1126} nvram_t;
1127
1128/*
1129 * ISP queue - response queue entry definition.
1130 */
1131typedef struct {
1132 uint8_t data[60];
1133 uint32_t signature;
1134#define RESPONSE_PROCESSED 0xDEADDEAD /* Signature */
1135} response_t;
1136
1137typedef union {
1138 uint16_t extended;
1139 struct {
1140 uint8_t reserved;
1141 uint8_t standard;
1142 } id;
1143} target_id_t;
1144
1145#define SET_TARGET_ID(ha, to, from) \
1146do { \
1147 if (HAS_EXTENDED_IDS(ha)) \
1148 to.extended = cpu_to_le16(from); \
1149 else \
1150 to.id.standard = (uint8_t)from; \
1151} while (0)
1152
1153/*
1154 * ISP queue - command entry structure definition.
1155 */
1156#define COMMAND_TYPE 0x11 /* Command entry */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001157typedef struct {
1158 uint8_t entry_type; /* Entry type. */
1159 uint8_t entry_count; /* Entry count. */
1160 uint8_t sys_define; /* System defined. */
1161 uint8_t entry_status; /* Entry Status. */
1162 uint32_t handle; /* System handle. */
1163 target_id_t target; /* SCSI ID */
1164 uint16_t lun; /* SCSI LUN */
1165 uint16_t control_flags; /* Control flags. */
1166#define CF_WRITE BIT_6
1167#define CF_READ BIT_5
1168#define CF_SIMPLE_TAG BIT_3
1169#define CF_ORDERED_TAG BIT_2
1170#define CF_HEAD_TAG BIT_1
1171 uint16_t reserved_1;
1172 uint16_t timeout; /* Command timeout. */
1173 uint16_t dseg_count; /* Data segment count. */
1174 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */
1175 uint32_t byte_count; /* Total byte count. */
1176 uint32_t dseg_0_address; /* Data segment 0 address. */
1177 uint32_t dseg_0_length; /* Data segment 0 length. */
1178 uint32_t dseg_1_address; /* Data segment 1 address. */
1179 uint32_t dseg_1_length; /* Data segment 1 length. */
1180 uint32_t dseg_2_address; /* Data segment 2 address. */
1181 uint32_t dseg_2_length; /* Data segment 2 length. */
1182} cmd_entry_t;
1183
1184/*
1185 * ISP queue - 64-Bit addressing, command entry structure definition.
1186 */
1187#define COMMAND_A64_TYPE 0x19 /* Command A64 entry */
1188typedef struct {
1189 uint8_t entry_type; /* Entry type. */
1190 uint8_t entry_count; /* Entry count. */
1191 uint8_t sys_define; /* System defined. */
1192 uint8_t entry_status; /* Entry Status. */
1193 uint32_t handle; /* System handle. */
1194 target_id_t target; /* SCSI ID */
1195 uint16_t lun; /* SCSI LUN */
1196 uint16_t control_flags; /* Control flags. */
1197 uint16_t reserved_1;
1198 uint16_t timeout; /* Command timeout. */
1199 uint16_t dseg_count; /* Data segment count. */
1200 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */
1201 uint32_t byte_count; /* Total byte count. */
1202 uint32_t dseg_0_address[2]; /* Data segment 0 address. */
1203 uint32_t dseg_0_length; /* Data segment 0 length. */
1204 uint32_t dseg_1_address[2]; /* Data segment 1 address. */
1205 uint32_t dseg_1_length; /* Data segment 1 length. */
1206} cmd_a64_entry_t, request_t;
1207
1208/*
1209 * ISP queue - continuation entry structure definition.
1210 */
1211#define CONTINUE_TYPE 0x02 /* Continuation entry. */
1212typedef struct {
1213 uint8_t entry_type; /* Entry type. */
1214 uint8_t entry_count; /* Entry count. */
1215 uint8_t sys_define; /* System defined. */
1216 uint8_t entry_status; /* Entry Status. */
1217 uint32_t reserved;
1218 uint32_t dseg_0_address; /* Data segment 0 address. */
1219 uint32_t dseg_0_length; /* Data segment 0 length. */
1220 uint32_t dseg_1_address; /* Data segment 1 address. */
1221 uint32_t dseg_1_length; /* Data segment 1 length. */
1222 uint32_t dseg_2_address; /* Data segment 2 address. */
1223 uint32_t dseg_2_length; /* Data segment 2 length. */
1224 uint32_t dseg_3_address; /* Data segment 3 address. */
1225 uint32_t dseg_3_length; /* Data segment 3 length. */
1226 uint32_t dseg_4_address; /* Data segment 4 address. */
1227 uint32_t dseg_4_length; /* Data segment 4 length. */
1228 uint32_t dseg_5_address; /* Data segment 5 address. */
1229 uint32_t dseg_5_length; /* Data segment 5 length. */
1230 uint32_t dseg_6_address; /* Data segment 6 address. */
1231 uint32_t dseg_6_length; /* Data segment 6 length. */
1232} cont_entry_t;
1233
1234/*
1235 * ISP queue - 64-Bit addressing, continuation entry structure definition.
1236 */
1237#define CONTINUE_A64_TYPE 0x0A /* Continuation A64 entry. */
1238typedef struct {
1239 uint8_t entry_type; /* Entry type. */
1240 uint8_t entry_count; /* Entry count. */
1241 uint8_t sys_define; /* System defined. */
1242 uint8_t entry_status; /* Entry Status. */
1243 uint32_t dseg_0_address[2]; /* Data segment 0 address. */
1244 uint32_t dseg_0_length; /* Data segment 0 length. */
1245 uint32_t dseg_1_address[2]; /* Data segment 1 address. */
1246 uint32_t dseg_1_length; /* Data segment 1 length. */
1247 uint32_t dseg_2_address [2]; /* Data segment 2 address. */
1248 uint32_t dseg_2_length; /* Data segment 2 length. */
1249 uint32_t dseg_3_address[2]; /* Data segment 3 address. */
1250 uint32_t dseg_3_length; /* Data segment 3 length. */
1251 uint32_t dseg_4_address[2]; /* Data segment 4 address. */
1252 uint32_t dseg_4_length; /* Data segment 4 length. */
1253} cont_a64_entry_t;
1254
1255/*
1256 * ISP queue - status entry structure definition.
1257 */
1258#define STATUS_TYPE 0x03 /* Status entry. */
1259typedef struct {
1260 uint8_t entry_type; /* Entry type. */
1261 uint8_t entry_count; /* Entry count. */
1262 uint8_t sys_define; /* System defined. */
1263 uint8_t entry_status; /* Entry Status. */
1264 uint32_t handle; /* System handle. */
1265 uint16_t scsi_status; /* SCSI status. */
1266 uint16_t comp_status; /* Completion status. */
1267 uint16_t state_flags; /* State flags. */
1268 uint16_t status_flags; /* Status flags. */
1269 uint16_t rsp_info_len; /* Response Info Length. */
1270 uint16_t req_sense_length; /* Request sense data length. */
1271 uint32_t residual_length; /* Residual transfer length. */
1272 uint8_t rsp_info[8]; /* FCP response information. */
1273 uint8_t req_sense_data[32]; /* Request sense data. */
1274} sts_entry_t;
1275
1276/*
1277 * Status entry entry status
1278 */
Andrew Vasquez3d716442005-07-06 10:30:26 -07001279#define RF_RQ_DMA_ERROR BIT_6 /* Request Queue DMA error. */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001280#define RF_INV_E_ORDER BIT_5 /* Invalid entry order. */
1281#define RF_INV_E_COUNT BIT_4 /* Invalid entry count. */
1282#define RF_INV_E_PARAM BIT_3 /* Invalid entry parameter. */
1283#define RF_INV_E_TYPE BIT_2 /* Invalid entry type. */
1284#define RF_BUSY BIT_1 /* Busy */
Andrew Vasquez3d716442005-07-06 10:30:26 -07001285#define RF_MASK (RF_RQ_DMA_ERROR | RF_INV_E_ORDER | RF_INV_E_COUNT | \
1286 RF_INV_E_PARAM | RF_INV_E_TYPE | RF_BUSY)
1287#define RF_MASK_24XX (RF_INV_E_ORDER | RF_INV_E_COUNT | RF_INV_E_PARAM | \
1288 RF_INV_E_TYPE)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001289
1290/*
1291 * Status entry SCSI status bit definitions.
1292 */
1293#define SS_MASK 0xfff /* Reserved bits BIT_12-BIT_15*/
1294#define SS_RESIDUAL_UNDER BIT_11
1295#define SS_RESIDUAL_OVER BIT_10
1296#define SS_SENSE_LEN_VALID BIT_9
1297#define SS_RESPONSE_INFO_LEN_VALID BIT_8
1298
1299#define SS_RESERVE_CONFLICT (BIT_4 | BIT_3)
1300#define SS_BUSY_CONDITION BIT_3
1301#define SS_CONDITION_MET BIT_2
1302#define SS_CHECK_CONDITION BIT_1
1303
1304/*
1305 * Status entry completion status
1306 */
1307#define CS_COMPLETE 0x0 /* No errors */
1308#define CS_INCOMPLETE 0x1 /* Incomplete transfer of cmd. */
1309#define CS_DMA 0x2 /* A DMA direction error. */
1310#define CS_TRANSPORT 0x3 /* Transport error. */
1311#define CS_RESET 0x4 /* SCSI bus reset occurred */
1312#define CS_ABORTED 0x5 /* System aborted command. */
1313#define CS_TIMEOUT 0x6 /* Timeout error. */
1314#define CS_DATA_OVERRUN 0x7 /* Data overrun. */
1315
1316#define CS_DATA_UNDERRUN 0x15 /* Data Underrun. */
1317#define CS_QUEUE_FULL 0x1C /* Queue Full. */
1318#define CS_PORT_UNAVAILABLE 0x28 /* Port unavailable */
1319 /* (selection timeout) */
1320#define CS_PORT_LOGGED_OUT 0x29 /* Port Logged Out */
1321#define CS_PORT_CONFIG_CHG 0x2A /* Port Configuration Changed */
1322#define CS_PORT_BUSY 0x2B /* Port Busy */
1323#define CS_COMPLETE_CHKCOND 0x30 /* Error? */
1324#define CS_BAD_PAYLOAD 0x80 /* Driver defined */
1325#define CS_UNKNOWN 0x81 /* Driver defined */
1326#define CS_RETRY 0x82 /* Driver defined */
1327#define CS_LOOP_DOWN_ABORT 0x83 /* Driver defined */
1328
1329/*
1330 * Status entry status flags
1331 */
1332#define SF_ABTS_TERMINATED BIT_10
1333#define SF_LOGOUT_SENT BIT_13
1334
1335/*
1336 * ISP queue - status continuation entry structure definition.
1337 */
1338#define STATUS_CONT_TYPE 0x10 /* Status continuation entry. */
1339typedef struct {
1340 uint8_t entry_type; /* Entry type. */
1341 uint8_t entry_count; /* Entry count. */
1342 uint8_t sys_define; /* System defined. */
1343 uint8_t entry_status; /* Entry Status. */
1344 uint8_t data[60]; /* data */
1345} sts_cont_entry_t;
1346
1347/*
1348 * ISP queue - RIO Type 1 status entry (32 bit I/O entry handles)
1349 * structure definition.
1350 */
1351#define STATUS_TYPE_21 0x21 /* Status entry. */
1352typedef struct {
1353 uint8_t entry_type; /* Entry type. */
1354 uint8_t entry_count; /* Entry count. */
1355 uint8_t handle_count; /* Handle count. */
1356 uint8_t entry_status; /* Entry Status. */
1357 uint32_t handle[15]; /* System handles. */
1358} sts21_entry_t;
1359
1360/*
1361 * ISP queue - RIO Type 2 status entry (16 bit I/O entry handles)
1362 * structure definition.
1363 */
1364#define STATUS_TYPE_22 0x22 /* Status entry. */
1365typedef struct {
1366 uint8_t entry_type; /* Entry type. */
1367 uint8_t entry_count; /* Entry count. */
1368 uint8_t handle_count; /* Handle count. */
1369 uint8_t entry_status; /* Entry Status. */
1370 uint16_t handle[30]; /* System handles. */
1371} sts22_entry_t;
1372
1373/*
1374 * ISP queue - marker entry structure definition.
1375 */
1376#define MARKER_TYPE 0x04 /* Marker entry. */
1377typedef struct {
1378 uint8_t entry_type; /* Entry type. */
1379 uint8_t entry_count; /* Entry count. */
1380 uint8_t handle_count; /* Handle count. */
1381 uint8_t entry_status; /* Entry Status. */
1382 uint32_t sys_define_2; /* System defined. */
1383 target_id_t target; /* SCSI ID */
1384 uint8_t modifier; /* Modifier (7-0). */
1385#define MK_SYNC_ID_LUN 0 /* Synchronize ID/LUN */
1386#define MK_SYNC_ID 1 /* Synchronize ID */
1387#define MK_SYNC_ALL 2 /* Synchronize all ID/LUN */
1388#define MK_SYNC_LIP 3 /* Synchronize all ID/LUN, */
1389 /* clear port changed, */
1390 /* use sequence number. */
1391 uint8_t reserved_1;
1392 uint16_t sequence_number; /* Sequence number of event */
1393 uint16_t lun; /* SCSI LUN */
1394 uint8_t reserved_2[48];
1395} mrk_entry_t;
1396
1397/*
1398 * ISP queue - Management Server entry structure definition.
1399 */
1400#define MS_IOCB_TYPE 0x29 /* Management Server IOCB entry */
1401typedef struct {
1402 uint8_t entry_type; /* Entry type. */
1403 uint8_t entry_count; /* Entry count. */
1404 uint8_t handle_count; /* Handle count. */
1405 uint8_t entry_status; /* Entry Status. */
1406 uint32_t handle1; /* System handle. */
1407 target_id_t loop_id;
1408 uint16_t status;
1409 uint16_t control_flags; /* Control flags. */
1410 uint16_t reserved2;
1411 uint16_t timeout;
1412 uint16_t cmd_dsd_count;
1413 uint16_t total_dsd_count;
1414 uint8_t type;
1415 uint8_t r_ctl;
1416 uint16_t rx_id;
1417 uint16_t reserved3;
1418 uint32_t handle2;
1419 uint32_t rsp_bytecount;
1420 uint32_t req_bytecount;
1421 uint32_t dseg_req_address[2]; /* Data segment 0 address. */
1422 uint32_t dseg_req_length; /* Data segment 0 length. */
1423 uint32_t dseg_rsp_address[2]; /* Data segment 1 address. */
1424 uint32_t dseg_rsp_length; /* Data segment 1 length. */
1425} ms_iocb_entry_t;
1426
1427
1428/*
1429 * ISP queue - Mailbox Command entry structure definition.
1430 */
1431#define MBX_IOCB_TYPE 0x39
1432struct mbx_entry {
1433 uint8_t entry_type;
1434 uint8_t entry_count;
1435 uint8_t sys_define1;
1436 /* Use sys_define1 for source type */
1437#define SOURCE_SCSI 0x00
1438#define SOURCE_IP 0x01
1439#define SOURCE_VI 0x02
1440#define SOURCE_SCTP 0x03
1441#define SOURCE_MP 0x04
1442#define SOURCE_MPIOCTL 0x05
1443#define SOURCE_ASYNC_IOCB 0x07
1444
1445 uint8_t entry_status;
1446
1447 uint32_t handle;
1448 target_id_t loop_id;
1449
1450 uint16_t status;
1451 uint16_t state_flags;
1452 uint16_t status_flags;
1453
1454 uint32_t sys_define2[2];
1455
1456 uint16_t mb0;
1457 uint16_t mb1;
1458 uint16_t mb2;
1459 uint16_t mb3;
1460 uint16_t mb6;
1461 uint16_t mb7;
1462 uint16_t mb9;
1463 uint16_t mb10;
1464 uint32_t reserved_2[2];
1465 uint8_t node_name[WWN_SIZE];
1466 uint8_t port_name[WWN_SIZE];
1467};
1468
1469/*
1470 * ISP request and response queue entry sizes
1471 */
1472#define RESPONSE_ENTRY_SIZE (sizeof(response_t))
1473#define REQUEST_ENTRY_SIZE (sizeof(request_t))
1474
1475
1476/*
1477 * 24 bit port ID type definition.
1478 */
1479typedef union {
1480 uint32_t b24 : 24;
1481
1482 struct {
Malahal Nainenib889d532007-03-12 10:41:26 -07001483#ifdef __BIG_ENDIAN
1484 uint8_t domain;
1485 uint8_t area;
1486 uint8_t al_pa;
1487#elif __LITTLE_ENDIAN
Linus Torvalds1da177e2005-04-16 15:20:36 -07001488 uint8_t al_pa;
1489 uint8_t area;
1490 uint8_t domain;
Malahal Nainenib889d532007-03-12 10:41:26 -07001491#else
1492#error "__BIG_ENDIAN or __LITTLE_ENDIAN must be defined!"
1493#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07001494 uint8_t rsvd_1;
1495 } b;
1496} port_id_t;
1497#define INVALID_PORT_ID 0xFFFFFF
1498
1499/*
1500 * Switch info gathering structure.
1501 */
1502typedef struct {
1503 port_id_t d_id;
1504 uint8_t node_name[WWN_SIZE];
1505 uint8_t port_name[WWN_SIZE];
Andrew Vasquezd8b45212006-10-02 12:00:43 -07001506 uint8_t fabric_port_name[WWN_SIZE];
Andrew Vasquezd8b45212006-10-02 12:00:43 -07001507 uint16_t fp_speed;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001508} sw_info_t;
1509
1510/*
Linus Torvalds1da177e2005-04-16 15:20:36 -07001511 * Fibre channel port type.
1512 */
1513 typedef enum {
1514 FCT_UNKNOWN,
1515 FCT_RSCN,
1516 FCT_SWITCH,
1517 FCT_BROADCAST,
1518 FCT_INITIATOR,
1519 FCT_TARGET
1520} fc_port_type_t;
1521
1522/*
1523 * Fibre channel port structure.
1524 */
1525typedef struct fc_port {
1526 struct list_head list;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001527 struct scsi_qla_host *ha;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001528
1529 uint8_t node_name[WWN_SIZE];
1530 uint8_t port_name[WWN_SIZE];
1531 port_id_t d_id;
1532 uint16_t loop_id;
1533 uint16_t old_loop_id;
1534
Andrew Vasquezd8b45212006-10-02 12:00:43 -07001535 uint8_t fabric_port_name[WWN_SIZE];
1536 uint16_t fp_speed;
1537
Linus Torvalds1da177e2005-04-16 15:20:36 -07001538 fc_port_type_t port_type;
1539
1540 atomic_t state;
1541 uint32_t flags;
1542
Linus Torvalds1da177e2005-04-16 15:20:36 -07001543 int port_login_retry_count;
1544 int login_retry;
1545 atomic_t port_down_timer;
1546
andrew.vasquez@qlogic.comd97994d2006-01-20 14:53:13 -08001547 spinlock_t rport_lock;
1548 struct fc_rport *rport, *drport;
Andrew Vasquezad3e0ed2005-08-26 19:08:10 -07001549 u32 supported_classes;
Andrew Vasquezdf7baa52006-10-13 09:33:39 -07001550
1551 unsigned long last_queue_full;
1552 unsigned long last_ramp_up;
Seokmann Ju2c3dfe32007-07-05 13:16:51 -07001553
1554 struct list_head vp_fcport;
1555 uint16_t vp_idx;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001556} fc_port_t;
1557
1558/*
1559 * Fibre channel port/lun states.
1560 */
1561#define FCS_UNCONFIGURED 1
1562#define FCS_DEVICE_DEAD 2
1563#define FCS_DEVICE_LOST 3
1564#define FCS_ONLINE 4
1565#define FCS_NOT_SUPPORTED 5
1566#define FCS_FAILOVER 6
1567#define FCS_FAILOVER_FAILED 7
1568
1569/*
1570 * FC port flags.
1571 */
1572#define FCF_FABRIC_DEVICE BIT_0
1573#define FCF_LOGIN_NEEDED BIT_1
1574#define FCF_FO_MASKED BIT_2
1575#define FCF_FAILOVER_NEEDED BIT_3
1576#define FCF_RESET_NEEDED BIT_4
1577#define FCF_PERSISTENT_BOUND BIT_5
1578#define FCF_TAPE_PRESENT BIT_6
1579#define FCF_FARP_DONE BIT_7
1580#define FCF_FARP_FAILED BIT_8
1581#define FCF_FARP_REPLY_NEEDED BIT_9
1582#define FCF_AUTH_REQ BIT_10
1583#define FCF_SEND_AUTH_REQ BIT_11
1584#define FCF_RECEIVE_AUTH_REQ BIT_12
1585#define FCF_AUTH_SUCCESS BIT_13
1586#define FCF_RLC_SUPPORT BIT_14
1587#define FCF_CONFIG BIT_15 /* Needed? */
1588#define FCF_RESCAN_NEEDED BIT_16
1589#define FCF_XP_DEVICE BIT_17
1590#define FCF_MSA_DEVICE BIT_18
1591#define FCF_EVA_DEVICE BIT_19
1592#define FCF_MSA_PORT_ACTIVE BIT_20
1593#define FCF_FAILBACK_DISABLE BIT_21
1594#define FCF_FAILOVER_DISABLE BIT_22
1595#define FCF_DSXXX_DEVICE BIT_23
1596#define FCF_AA_EVA_DEVICE BIT_24
Andrew Vasquez3d716442005-07-06 10:30:26 -07001597#define FCF_AA_MSA_DEVICE BIT_25
Linus Torvalds1da177e2005-04-16 15:20:36 -07001598
1599/* No loop ID flag. */
1600#define FC_NO_LOOP_ID 0x1000
1601
1602/*
Linus Torvalds1da177e2005-04-16 15:20:36 -07001603 * FC-CT interface
1604 *
1605 * NOTE: All structures are big-endian in form.
1606 */
1607
1608#define CT_REJECT_RESPONSE 0x8001
1609#define CT_ACCEPT_RESPONSE 0x8002
Andrew Vasquez4346b142006-12-13 19:20:28 -08001610#define CT_REASON_INVALID_COMMAND_CODE 0x01
Andrew Vasquezcca53352005-08-26 19:08:30 -07001611#define CT_REASON_CANNOT_PERFORM 0x09
Andrew Vasquez3fe7cfb2008-04-03 13:13:23 -07001612#define CT_REASON_COMMAND_UNSUPPORTED 0x0b
Andrew Vasquezcca53352005-08-26 19:08:30 -07001613#define CT_EXPL_ALREADY_REGISTERED 0x10
Linus Torvalds1da177e2005-04-16 15:20:36 -07001614
1615#define NS_N_PORT_TYPE 0x01
1616#define NS_NL_PORT_TYPE 0x02
1617#define NS_NX_PORT_TYPE 0x7F
1618
1619#define GA_NXT_CMD 0x100
1620#define GA_NXT_REQ_SIZE (16 + 4)
1621#define GA_NXT_RSP_SIZE (16 + 620)
1622
1623#define GID_PT_CMD 0x1A1
1624#define GID_PT_REQ_SIZE (16 + 4)
1625#define GID_PT_RSP_SIZE (16 + (MAX_FIBRE_DEVICES * 4))
1626
1627#define GPN_ID_CMD 0x112
1628#define GPN_ID_REQ_SIZE (16 + 4)
1629#define GPN_ID_RSP_SIZE (16 + 8)
1630
1631#define GNN_ID_CMD 0x113
1632#define GNN_ID_REQ_SIZE (16 + 4)
1633#define GNN_ID_RSP_SIZE (16 + 8)
1634
1635#define GFT_ID_CMD 0x117
1636#define GFT_ID_REQ_SIZE (16 + 4)
1637#define GFT_ID_RSP_SIZE (16 + 32)
1638
1639#define RFT_ID_CMD 0x217
1640#define RFT_ID_REQ_SIZE (16 + 4 + 32)
1641#define RFT_ID_RSP_SIZE 16
1642
1643#define RFF_ID_CMD 0x21F
1644#define RFF_ID_REQ_SIZE (16 + 4 + 2 + 1 + 1)
1645#define RFF_ID_RSP_SIZE 16
1646
1647#define RNN_ID_CMD 0x213
1648#define RNN_ID_REQ_SIZE (16 + 4 + 8)
1649#define RNN_ID_RSP_SIZE 16
1650
1651#define RSNN_NN_CMD 0x239
1652#define RSNN_NN_REQ_SIZE (16 + 8 + 1 + 255)
1653#define RSNN_NN_RSP_SIZE 16
1654
Andrew Vasquezd8b45212006-10-02 12:00:43 -07001655#define GFPN_ID_CMD 0x11C
1656#define GFPN_ID_REQ_SIZE (16 + 4)
1657#define GFPN_ID_RSP_SIZE (16 + 8)
1658
1659#define GPSC_CMD 0x127
1660#define GPSC_REQ_SIZE (16 + 8)
1661#define GPSC_RSP_SIZE (16 + 2 + 2)
1662
1663
Andrew Vasquezcca53352005-08-26 19:08:30 -07001664/*
1665 * HBA attribute types.
1666 */
1667#define FDMI_HBA_ATTR_COUNT 9
1668#define FDMI_HBA_NODE_NAME 1
1669#define FDMI_HBA_MANUFACTURER 2
1670#define FDMI_HBA_SERIAL_NUMBER 3
1671#define FDMI_HBA_MODEL 4
1672#define FDMI_HBA_MODEL_DESCRIPTION 5
1673#define FDMI_HBA_HARDWARE_VERSION 6
1674#define FDMI_HBA_DRIVER_VERSION 7
1675#define FDMI_HBA_OPTION_ROM_VERSION 8
1676#define FDMI_HBA_FIRMWARE_VERSION 9
1677#define FDMI_HBA_OS_NAME_AND_VERSION 0xa
1678#define FDMI_HBA_MAXIMUM_CT_PAYLOAD_LENGTH 0xb
1679
1680struct ct_fdmi_hba_attr {
1681 uint16_t type;
1682 uint16_t len;
1683 union {
1684 uint8_t node_name[WWN_SIZE];
1685 uint8_t manufacturer[32];
1686 uint8_t serial_num[8];
1687 uint8_t model[16];
1688 uint8_t model_desc[80];
1689 uint8_t hw_version[16];
1690 uint8_t driver_version[32];
1691 uint8_t orom_version[16];
1692 uint8_t fw_version[16];
1693 uint8_t os_version[128];
1694 uint8_t max_ct_len[4];
1695 } a;
1696};
1697
1698struct ct_fdmi_hba_attributes {
1699 uint32_t count;
1700 struct ct_fdmi_hba_attr entry[FDMI_HBA_ATTR_COUNT];
1701};
1702
1703/*
1704 * Port attribute types.
1705 */
Andrew Vasquez8a85e1712007-09-20 14:07:41 -07001706#define FDMI_PORT_ATTR_COUNT 6
Andrew Vasquezcca53352005-08-26 19:08:30 -07001707#define FDMI_PORT_FC4_TYPES 1
1708#define FDMI_PORT_SUPPORT_SPEED 2
1709#define FDMI_PORT_CURRENT_SPEED 3
1710#define FDMI_PORT_MAX_FRAME_SIZE 4
1711#define FDMI_PORT_OS_DEVICE_NAME 5
1712#define FDMI_PORT_HOST_NAME 6
1713
Andrew Vasquez58815692007-07-19 15:05:58 -07001714#define FDMI_PORT_SPEED_1GB 0x1
1715#define FDMI_PORT_SPEED_2GB 0x2
1716#define FDMI_PORT_SPEED_10GB 0x4
1717#define FDMI_PORT_SPEED_4GB 0x8
1718#define FDMI_PORT_SPEED_8GB 0x10
1719#define FDMI_PORT_SPEED_16GB 0x20
1720#define FDMI_PORT_SPEED_UNKNOWN 0x8000
1721
Andrew Vasquezcca53352005-08-26 19:08:30 -07001722struct ct_fdmi_port_attr {
1723 uint16_t type;
1724 uint16_t len;
1725 union {
1726 uint8_t fc4_types[32];
1727 uint32_t sup_speed;
1728 uint32_t cur_speed;
1729 uint32_t max_frame_size;
1730 uint8_t os_dev_name[32];
1731 uint8_t host_name[32];
1732 } a;
1733};
1734
1735/*
1736 * Port Attribute Block.
1737 */
1738struct ct_fdmi_port_attributes {
1739 uint32_t count;
1740 struct ct_fdmi_port_attr entry[FDMI_PORT_ATTR_COUNT];
1741};
1742
1743/* FDMI definitions. */
1744#define GRHL_CMD 0x100
1745#define GHAT_CMD 0x101
1746#define GRPL_CMD 0x102
1747#define GPAT_CMD 0x110
1748
1749#define RHBA_CMD 0x200
1750#define RHBA_RSP_SIZE 16
1751
1752#define RHAT_CMD 0x201
1753#define RPRT_CMD 0x210
1754
1755#define RPA_CMD 0x211
1756#define RPA_RSP_SIZE 16
1757
1758#define DHBA_CMD 0x300
1759#define DHBA_REQ_SIZE (16 + 8)
1760#define DHBA_RSP_SIZE 16
1761
1762#define DHAT_CMD 0x301
1763#define DPRT_CMD 0x310
1764#define DPA_CMD 0x311
1765
Linus Torvalds1da177e2005-04-16 15:20:36 -07001766/* CT command header -- request/response common fields */
1767struct ct_cmd_hdr {
1768 uint8_t revision;
1769 uint8_t in_id[3];
1770 uint8_t gs_type;
1771 uint8_t gs_subtype;
1772 uint8_t options;
1773 uint8_t reserved;
1774};
1775
1776/* CT command request */
1777struct ct_sns_req {
1778 struct ct_cmd_hdr header;
1779 uint16_t command;
1780 uint16_t max_rsp_size;
1781 uint8_t fragment_id;
1782 uint8_t reserved[3];
1783
1784 union {
Andrew Vasquezd8b45212006-10-02 12:00:43 -07001785 /* GA_NXT, GPN_ID, GNN_ID, GFT_ID, GFPN_ID */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001786 struct {
1787 uint8_t reserved;
1788 uint8_t port_id[3];
1789 } port_id;
1790
1791 struct {
1792 uint8_t port_type;
1793 uint8_t domain;
1794 uint8_t area;
1795 uint8_t reserved;
1796 } gid_pt;
1797
1798 struct {
1799 uint8_t reserved;
1800 uint8_t port_id[3];
1801 uint8_t fc4_types[32];
1802 } rft_id;
1803
1804 struct {
1805 uint8_t reserved;
1806 uint8_t port_id[3];
1807 uint16_t reserved2;
1808 uint8_t fc4_feature;
1809 uint8_t fc4_type;
1810 } rff_id;
1811
1812 struct {
1813 uint8_t reserved;
1814 uint8_t port_id[3];
1815 uint8_t node_name[8];
1816 } rnn_id;
1817
1818 struct {
1819 uint8_t node_name[8];
1820 uint8_t name_len;
1821 uint8_t sym_node_name[255];
1822 } rsnn_nn;
Andrew Vasquezcca53352005-08-26 19:08:30 -07001823
1824 struct {
1825 uint8_t hba_indentifier[8];
1826 } ghat;
1827
1828 struct {
1829 uint8_t hba_identifier[8];
1830 uint32_t entry_count;
1831 uint8_t port_name[8];
1832 struct ct_fdmi_hba_attributes attrs;
1833 } rhba;
1834
1835 struct {
1836 uint8_t hba_identifier[8];
1837 struct ct_fdmi_hba_attributes attrs;
1838 } rhat;
1839
1840 struct {
1841 uint8_t port_name[8];
1842 struct ct_fdmi_port_attributes attrs;
1843 } rpa;
1844
1845 struct {
1846 uint8_t port_name[8];
1847 } dhba;
1848
1849 struct {
1850 uint8_t port_name[8];
1851 } dhat;
1852
1853 struct {
1854 uint8_t port_name[8];
1855 } dprt;
1856
1857 struct {
1858 uint8_t port_name[8];
1859 } dpa;
Andrew Vasquezd8b45212006-10-02 12:00:43 -07001860
1861 struct {
1862 uint8_t port_name[8];
1863 } gpsc;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001864 } req;
1865};
1866
1867/* CT command response header */
1868struct ct_rsp_hdr {
1869 struct ct_cmd_hdr header;
1870 uint16_t response;
1871 uint16_t residual;
1872 uint8_t fragment_id;
1873 uint8_t reason_code;
1874 uint8_t explanation_code;
1875 uint8_t vendor_unique;
1876};
1877
1878struct ct_sns_gid_pt_data {
1879 uint8_t control_byte;
1880 uint8_t port_id[3];
1881};
1882
1883struct ct_sns_rsp {
1884 struct ct_rsp_hdr header;
1885
1886 union {
1887 struct {
1888 uint8_t port_type;
1889 uint8_t port_id[3];
1890 uint8_t port_name[8];
1891 uint8_t sym_port_name_len;
1892 uint8_t sym_port_name[255];
1893 uint8_t node_name[8];
1894 uint8_t sym_node_name_len;
1895 uint8_t sym_node_name[255];
1896 uint8_t init_proc_assoc[8];
1897 uint8_t node_ip_addr[16];
1898 uint8_t class_of_service[4];
1899 uint8_t fc4_types[32];
1900 uint8_t ip_address[16];
1901 uint8_t fabric_port_name[8];
1902 uint8_t reserved;
1903 uint8_t hard_address[3];
1904 } ga_nxt;
1905
1906 struct {
1907 struct ct_sns_gid_pt_data entries[MAX_FIBRE_DEVICES];
1908 } gid_pt;
1909
1910 struct {
1911 uint8_t port_name[8];
1912 } gpn_id;
1913
1914 struct {
1915 uint8_t node_name[8];
1916 } gnn_id;
1917
1918 struct {
1919 uint8_t fc4_types[32];
1920 } gft_id;
Andrew Vasquezcca53352005-08-26 19:08:30 -07001921
1922 struct {
1923 uint32_t entry_count;
1924 uint8_t port_name[8];
1925 struct ct_fdmi_hba_attributes attrs;
1926 } ghat;
Andrew Vasquezd8b45212006-10-02 12:00:43 -07001927
1928 struct {
1929 uint8_t port_name[8];
1930 } gfpn_id;
1931
1932 struct {
1933 uint16_t speeds;
1934 uint16_t speed;
1935 } gpsc;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001936 } rsp;
1937};
1938
1939struct ct_sns_pkt {
1940 union {
1941 struct ct_sns_req req;
1942 struct ct_sns_rsp rsp;
1943 } p;
1944};
1945
1946/*
1947 * SNS command structures -- for 2200 compatability.
1948 */
1949#define RFT_ID_SNS_SCMD_LEN 22
1950#define RFT_ID_SNS_CMD_SIZE 60
1951#define RFT_ID_SNS_DATA_SIZE 16
1952
1953#define RNN_ID_SNS_SCMD_LEN 10
1954#define RNN_ID_SNS_CMD_SIZE 36
1955#define RNN_ID_SNS_DATA_SIZE 16
1956
1957#define GA_NXT_SNS_SCMD_LEN 6
1958#define GA_NXT_SNS_CMD_SIZE 28
1959#define GA_NXT_SNS_DATA_SIZE (620 + 16)
1960
1961#define GID_PT_SNS_SCMD_LEN 6
1962#define GID_PT_SNS_CMD_SIZE 28
1963#define GID_PT_SNS_DATA_SIZE (MAX_FIBRE_DEVICES * 4 + 16)
1964
1965#define GPN_ID_SNS_SCMD_LEN 6
1966#define GPN_ID_SNS_CMD_SIZE 28
1967#define GPN_ID_SNS_DATA_SIZE (8 + 16)
1968
1969#define GNN_ID_SNS_SCMD_LEN 6
1970#define GNN_ID_SNS_CMD_SIZE 28
1971#define GNN_ID_SNS_DATA_SIZE (8 + 16)
1972
1973struct sns_cmd_pkt {
1974 union {
1975 struct {
1976 uint16_t buffer_length;
1977 uint16_t reserved_1;
1978 uint32_t buffer_address[2];
1979 uint16_t subcommand_length;
1980 uint16_t reserved_2;
1981 uint16_t subcommand;
1982 uint16_t size;
1983 uint32_t reserved_3;
1984 uint8_t param[36];
1985 } cmd;
1986
1987 uint8_t rft_data[RFT_ID_SNS_DATA_SIZE];
1988 uint8_t rnn_data[RNN_ID_SNS_DATA_SIZE];
1989 uint8_t gan_data[GA_NXT_SNS_DATA_SIZE];
1990 uint8_t gid_data[GID_PT_SNS_DATA_SIZE];
1991 uint8_t gpn_data[GPN_ID_SNS_DATA_SIZE];
1992 uint8_t gnn_data[GNN_ID_SNS_DATA_SIZE];
1993 } p;
1994};
1995
Andrew Vasquez54333832005-11-09 15:49:04 -08001996struct fw_blob {
1997 char *name;
1998 uint32_t segs[4];
1999 const struct firmware *fw;
2000};
2001
Linus Torvalds1da177e2005-04-16 15:20:36 -07002002/* Return data from MBC_GET_ID_LIST call. */
2003struct gid_list_info {
2004 uint8_t al_pa;
2005 uint8_t area;
Andrew Vasquezfa2a1ce2005-07-06 10:32:07 -07002006 uint8_t domain;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002007 uint8_t loop_id_2100; /* ISP2100/ISP2200 -- 4 bytes. */
2008 uint16_t loop_id; /* ISP23XX -- 6 bytes. */
Andrew Vasquez3d716442005-07-06 10:30:26 -07002009 uint16_t reserved_1; /* ISP24XX -- 8 bytes. */
Linus Torvalds1da177e2005-04-16 15:20:36 -07002010};
2011#define GID_LIST_SIZE (sizeof(struct gid_list_info) * MAX_FIBRE_DEVICES)
2012
Seokmann Ju2c3dfe32007-07-05 13:16:51 -07002013/* NPIV */
2014typedef struct vport_info {
2015 uint8_t port_name[WWN_SIZE];
2016 uint8_t node_name[WWN_SIZE];
2017 int vp_id;
2018 uint16_t loop_id;
2019 unsigned long host_no;
2020 uint8_t port_id[3];
2021 int loop_state;
2022} vport_info_t;
2023
2024typedef struct vport_params {
2025 uint8_t port_name[WWN_SIZE];
2026 uint8_t node_name[WWN_SIZE];
2027 uint32_t options;
2028#define VP_OPTS_RETRY_ENABLE BIT_0
2029#define VP_OPTS_VP_DISABLE BIT_1
2030} vport_params_t;
2031
2032/* NPIV - return codes of VP create and modify */
2033#define VP_RET_CODE_OK 0
2034#define VP_RET_CODE_FATAL 1
2035#define VP_RET_CODE_WRONG_ID 2
2036#define VP_RET_CODE_WWPN 3
2037#define VP_RET_CODE_RESOURCES 4
2038#define VP_RET_CODE_NO_MEM 5
2039#define VP_RET_CODE_NOT_FOUND 6
2040
Linus Torvalds1da177e2005-04-16 15:20:36 -07002041/*
Andrew Vasquezabbd8872005-07-06 10:30:05 -07002042 * ISP operations
2043 */
2044struct isp_operations {
2045
2046 int (*pci_config) (struct scsi_qla_host *);
2047 void (*reset_chip) (struct scsi_qla_host *);
2048 int (*chip_diag) (struct scsi_qla_host *);
2049 void (*config_rings) (struct scsi_qla_host *);
2050 void (*reset_adapter) (struct scsi_qla_host *);
2051 int (*nvram_config) (struct scsi_qla_host *);
2052 void (*update_fw_options) (struct scsi_qla_host *);
2053 int (*load_risc) (struct scsi_qla_host *, uint32_t *);
2054
2055 char * (*pci_info_str) (struct scsi_qla_host *, char *);
2056 char * (*fw_version_str) (struct scsi_qla_host *, char *);
2057
David Howells7d12e782006-10-05 14:55:46 +01002058 irq_handler_t intr_handler;
Andrew Vasquezabbd8872005-07-06 10:30:05 -07002059 void (*enable_intrs) (struct scsi_qla_host *);
2060 void (*disable_intrs) (struct scsi_qla_host *);
2061
2062 int (*abort_command) (struct scsi_qla_host *, srb_t *);
Andrew Vasquez523ec772008-04-03 13:13:24 -07002063 int (*target_reset) (struct fc_port *, unsigned int);
2064 int (*lun_reset) (struct fc_port *, unsigned int);
Andrew Vasquezabbd8872005-07-06 10:30:05 -07002065 int (*fabric_login) (struct scsi_qla_host *, uint16_t, uint8_t,
2066 uint8_t, uint8_t, uint16_t *, uint8_t);
Andrew Vasquez1c7c6352005-07-06 10:30:57 -07002067 int (*fabric_logout) (struct scsi_qla_host *, uint16_t, uint8_t,
2068 uint8_t, uint8_t);
Andrew Vasquezabbd8872005-07-06 10:30:05 -07002069
2070 uint16_t (*calc_req_entries) (uint16_t);
2071 void (*build_iocbs) (srb_t *, cmd_entry_t *, uint16_t);
Andrew Vasquez8c958a92005-07-06 10:30:47 -07002072 void * (*prep_ms_iocb) (struct scsi_qla_host *, uint32_t, uint32_t);
Andrew Vasquezcca53352005-08-26 19:08:30 -07002073 void * (*prep_ms_fdmi_iocb) (struct scsi_qla_host *, uint32_t,
2074 uint32_t);
Andrew Vasquezabbd8872005-07-06 10:30:05 -07002075
2076 uint8_t * (*read_nvram) (struct scsi_qla_host *, uint8_t *,
2077 uint32_t, uint32_t);
2078 int (*write_nvram) (struct scsi_qla_host *, uint8_t *, uint32_t,
2079 uint32_t);
2080
2081 void (*fw_dump) (struct scsi_qla_host *, int);
andrew.vasquez@qlogic.comf6df1442006-01-31 16:05:07 -08002082
2083 int (*beacon_on) (struct scsi_qla_host *);
2084 int (*beacon_off) (struct scsi_qla_host *);
2085 void (*beacon_blink) (struct scsi_qla_host *);
andrew.vasquez@qlogic.com854165f2006-01-31 16:05:17 -08002086
2087 uint8_t * (*read_optrom) (struct scsi_qla_host *, uint8_t *,
2088 uint32_t, uint32_t);
2089 int (*write_optrom) (struct scsi_qla_host *, uint8_t *, uint32_t,
2090 uint32_t);
Andrew Vasquez30c47662007-01-29 10:22:21 -08002091
2092 int (*get_flash_version) (struct scsi_qla_host *, void *);
Andrew Vasquezabbd8872005-07-06 10:30:05 -07002093};
2094
Andrew Vasqueza8488ab2007-01-29 10:22:19 -08002095/* MSI-X Support *************************************************************/
2096
2097#define QLA_MSIX_CHIP_REV_24XX 3
2098#define QLA_MSIX_FW_MODE(m) (((m) & (BIT_7|BIT_8|BIT_9)) >> 7)
2099#define QLA_MSIX_FW_MODE_1(m) (QLA_MSIX_FW_MODE(m) == 1)
2100
2101#define QLA_MSIX_DEFAULT 0x00
2102#define QLA_MSIX_RSP_Q 0x01
2103
2104#define QLA_MSIX_ENTRIES 2
2105#define QLA_MIDX_DEFAULT 0
2106#define QLA_MIDX_RSP_Q 1
2107
2108struct scsi_qla_host;
2109
2110struct qla_msix_entry {
2111 int have_irq;
2112 uint16_t msix_vector;
2113 uint16_t msix_entry;
2114};
2115
Seokmann Ju2c3dfe32007-07-05 13:16:51 -07002116#define WATCH_INTERVAL 1 /* number of seconds */
2117
Andrew Vasquez0971de72008-04-03 13:13:18 -07002118/* Work events. */
2119enum qla_work_type {
2120 QLA_EVT_AEN,
Andrew Vasquezcb8dacb2008-04-03 13:13:19 -07002121 QLA_EVT_HWE_LOG,
Andrew Vasquez0971de72008-04-03 13:13:18 -07002122};
2123
2124
2125struct qla_work_evt {
2126 struct list_head list;
2127 enum qla_work_type type;
2128 u32 flags;
2129#define QLA_EVT_FLAG_FREE 0x1
2130
2131 union {
2132 struct {
2133 enum fc_host_event_code code;
2134 u32 data;
2135 } aen;
Andrew Vasquezcb8dacb2008-04-03 13:13:19 -07002136 struct {
2137 uint16_t code;
2138 uint16_t d1, d2, d3;
2139 } hwe;
Andrew Vasquez0971de72008-04-03 13:13:18 -07002140 } u;
2141};
2142
Harihara Kadayam4d4df192008-04-03 13:13:26 -07002143struct qla_chip_state_84xx {
2144 struct list_head list;
2145 struct kref kref;
2146
2147 void *bus;
2148 spinlock_t access_lock;
2149 struct mutex fw_update_mutex;
2150 uint32_t fw_update;
2151 uint32_t op_fw_version;
2152 uint32_t op_fw_size;
2153 uint32_t op_fw_seq_size;
2154 uint32_t diag_fw_version;
2155 uint32_t gold_fw_version;
2156};
2157
Andrew Vasquezabbd8872005-07-06 10:30:05 -07002158/*
Linus Torvalds1da177e2005-04-16 15:20:36 -07002159 * Linux Host Adapter structure
2160 */
2161typedef struct scsi_qla_host {
2162 struct list_head list;
2163
2164 /* Commonly used flags and state information. */
2165 struct Scsi_Host *host;
2166 struct pci_dev *pdev;
2167
2168 unsigned long host_no;
2169 unsigned long instance;
2170
2171 volatile struct {
2172 uint32_t init_done :1;
2173 uint32_t online :1;
2174 uint32_t mbox_int :1;
2175 uint32_t mbox_busy :1;
2176 uint32_t rscn_queue_overflow :1;
2177 uint32_t reset_active :1;
2178
2179 uint32_t management_server_logged_in :1;
2180 uint32_t process_response_queue :1;
2181
2182 uint32_t disable_risc_code_load :1;
2183 uint32_t enable_64bit_addressing :1;
2184 uint32_t enable_lip_reset :1;
2185 uint32_t enable_lip_full_login :1;
2186 uint32_t enable_target_reset :1;
2187 uint32_t enable_led_scheme :1;
Andrew Vasquezd88021a2007-01-29 10:22:20 -08002188 uint32_t inta_enabled :1;
Andrew Vasquez3d716442005-07-06 10:30:26 -07002189 uint32_t msi_enabled :1;
2190 uint32_t msix_enabled :1;
Andrew Vasquezd4c760c2006-06-23 16:10:39 -07002191 uint32_t disable_serdes :1;
Andrew Vasquez4346b142006-12-13 19:20:28 -08002192 uint32_t gpsc_supported :1;
Seokmann Ju2c3dfe32007-07-05 13:16:51 -07002193 uint32_t vsan_enabled :1;
2194 uint32_t npiv_supported :1;
Andrew Vasquezdf613b92008-01-17 09:02:17 -08002195 uint32_t fce_enabled :1;
Andrew Vasquezcb8dacb2008-04-03 13:13:19 -07002196 uint32_t hw_event_marker_found :1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002197 } flags;
2198
2199 atomic_t loop_state;
2200#define LOOP_TIMEOUT 1
2201#define LOOP_DOWN 2
2202#define LOOP_UP 3
2203#define LOOP_UPDATE 4
2204#define LOOP_READY 5
2205#define LOOP_DEAD 6
2206
2207 unsigned long dpc_flags;
2208#define RESET_MARKER_NEEDED 0 /* Send marker to ISP. */
2209#define RESET_ACTIVE 1
2210#define ISP_ABORT_NEEDED 2 /* Initiate ISP abort. */
2211#define ABORT_ISP_ACTIVE 3 /* ISP abort in progress. */
2212#define LOOP_RESYNC_NEEDED 4 /* Device Resync needed. */
2213#define LOOP_RESYNC_ACTIVE 5
2214#define LOCAL_LOOP_UPDATE 6 /* Perform a local loop update. */
2215#define RSCN_UPDATE 7 /* Perform an RSCN update. */
2216#define MAILBOX_RETRY 8
2217#define ISP_RESET_NEEDED 9 /* Initiate a ISP reset. */
2218#define FAILOVER_EVENT_NEEDED 10
2219#define FAILOVER_EVENT 11
2220#define FAILOVER_NEEDED 12
2221#define SCSI_RESTART_NEEDED 13 /* Processes SCSI retry queue. */
2222#define PORT_RESTART_NEEDED 14 /* Processes Retry queue. */
2223#define RESTART_QUEUES_NEEDED 15 /* Restarts the Lun queue. */
2224#define ABORT_QUEUES_NEEDED 16
2225#define RELOGIN_NEEDED 17
2226#define LOGIN_RETRY_NEEDED 18 /* Initiate required fabric logins. */
2227#define REGISTER_FC4_NEEDED 19 /* SNS FC4 registration required. */
2228#define ISP_ABORT_RETRY 20 /* ISP aborted. */
2229#define FCPORT_RESCAN_NEEDED 21 /* IO descriptor processing needed */
2230#define IODESC_PROCESS_NEEDED 22 /* IO descriptor processing needed */
Andrew Vasquezfa2a1ce2005-07-06 10:32:07 -07002231#define IOCTL_ERROR_RECOVERY 23
Linus Torvalds1da177e2005-04-16 15:20:36 -07002232#define LOOP_RESET_NEEDED 24
Andrew Vasquez3d716442005-07-06 10:30:26 -07002233#define BEACON_BLINK_NEEDED 25
Andrew Vasquezcca53352005-08-26 19:08:30 -07002234#define REGISTER_FDMI_NEEDED 26
andrew.vasquez@qlogic.comd97994d2006-01-20 14:53:13 -08002235#define FCPORT_UPDATE_NEEDED 27
Seokmann Ju2c3dfe32007-07-05 13:16:51 -07002236#define VP_DPC_NEEDED 28 /* wake up for VP dpc handling */
Linus Torvalds1da177e2005-04-16 15:20:36 -07002237
2238 uint32_t device_flags;
2239#define DFLG_LOCAL_DEVICES BIT_0
2240#define DFLG_RETRY_LOCAL_DEVICES BIT_1
2241#define DFLG_FABRIC_DEVICES BIT_2
2242#define SWITCH_FOUND BIT_3
2243#define DFLG_NO_CABLE BIT_4
2244
Andrew Vasquezc3a2f0d2007-07-19 20:37:34 -07002245#define PCI_DEVICE_ID_QLOGIC_ISP2532 0x2532
Harihara Kadayam4d4df192008-04-03 13:13:26 -07002246#define PCI_DEVICE_ID_QLOGIC_ISP8432 0x8432
andrew.vasquez@qlogic.comea5b6382006-03-09 14:27:08 -08002247 uint32_t device_type;
2248#define DT_ISP2100 BIT_0
2249#define DT_ISP2200 BIT_1
2250#define DT_ISP2300 BIT_2
2251#define DT_ISP2312 BIT_3
2252#define DT_ISP2322 BIT_4
2253#define DT_ISP6312 BIT_5
2254#define DT_ISP6322 BIT_6
2255#define DT_ISP2422 BIT_7
2256#define DT_ISP2432 BIT_8
andrew.vasquez@qlogic.com044cc6c2006-03-09 14:27:13 -08002257#define DT_ISP5422 BIT_9
2258#define DT_ISP5432 BIT_10
Andrew Vasquezc3a2f0d2007-07-19 20:37:34 -07002259#define DT_ISP2532 BIT_11
Harihara Kadayam4d4df192008-04-03 13:13:26 -07002260#define DT_ISP8432 BIT_12
2261#define DT_ISP_LAST (DT_ISP8432 << 1)
andrew.vasquez@qlogic.comea5b6382006-03-09 14:27:08 -08002262
Andrew Vasquezc76f2c02007-07-19 15:05:57 -07002263#define DT_IIDMA BIT_26
Andrew Vasqueze4289242007-07-19 15:05:56 -07002264#define DT_FWI2 BIT_27
andrew.vasquez@qlogic.com4a59f712006-03-09 14:27:39 -08002265#define DT_ZIO_SUPPORTED BIT_28
andrew.vasquez@qlogic.comea5b6382006-03-09 14:27:08 -08002266#define DT_OEM_001 BIT_29
2267#define DT_ISP2200A BIT_30
2268#define DT_EXTENDED_IDS BIT_31
2269
2270#define DT_MASK(ha) ((ha)->device_type & (DT_ISP_LAST - 1))
2271#define IS_QLA2100(ha) (DT_MASK(ha) & DT_ISP2100)
2272#define IS_QLA2200(ha) (DT_MASK(ha) & DT_ISP2200)
2273#define IS_QLA2300(ha) (DT_MASK(ha) & DT_ISP2300)
2274#define IS_QLA2312(ha) (DT_MASK(ha) & DT_ISP2312)
2275#define IS_QLA2322(ha) (DT_MASK(ha) & DT_ISP2322)
2276#define IS_QLA6312(ha) (DT_MASK(ha) & DT_ISP6312)
2277#define IS_QLA6322(ha) (DT_MASK(ha) & DT_ISP6322)
2278#define IS_QLA2422(ha) (DT_MASK(ha) & DT_ISP2422)
2279#define IS_QLA2432(ha) (DT_MASK(ha) & DT_ISP2432)
andrew.vasquez@qlogic.com044cc6c2006-03-09 14:27:13 -08002280#define IS_QLA5422(ha) (DT_MASK(ha) & DT_ISP5422)
2281#define IS_QLA5432(ha) (DT_MASK(ha) & DT_ISP5432)
Andrew Vasquezc3a2f0d2007-07-19 20:37:34 -07002282#define IS_QLA2532(ha) (DT_MASK(ha) & DT_ISP2532)
Harihara Kadayam4d4df192008-04-03 13:13:26 -07002283#define IS_QLA8432(ha) (DT_MASK(ha) & DT_ISP8432)
andrew.vasquez@qlogic.comea5b6382006-03-09 14:27:08 -08002284
2285#define IS_QLA23XX(ha) (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA2322(ha) || \
2286 IS_QLA6312(ha) || IS_QLA6322(ha))
2287#define IS_QLA24XX(ha) (IS_QLA2422(ha) || IS_QLA2432(ha))
andrew.vasquez@qlogic.com044cc6c2006-03-09 14:27:13 -08002288#define IS_QLA54XX(ha) (IS_QLA5422(ha) || IS_QLA5432(ha))
Andrew Vasquezc3a2f0d2007-07-19 20:37:34 -07002289#define IS_QLA25XX(ha) (IS_QLA2532(ha))
Harihara Kadayam4d4df192008-04-03 13:13:26 -07002290#define IS_QLA84XX(ha) (IS_QLA8432(ha))
2291#define IS_QLA24XX_TYPE(ha) (IS_QLA24XX(ha) || IS_QLA54XX(ha) || \
2292 IS_QLA84XX(ha))
andrew.vasquez@qlogic.comea5b6382006-03-09 14:27:08 -08002293
Andrew Vasquezc76f2c02007-07-19 15:05:57 -07002294#define IS_IIDMA_CAPABLE(ha) ((ha)->device_type & DT_IIDMA)
Andrew Vasqueze4289242007-07-19 15:05:56 -07002295#define IS_FWI2_CAPABLE(ha) ((ha)->device_type & DT_FWI2)
andrew.vasquez@qlogic.com4a59f712006-03-09 14:27:39 -08002296#define IS_ZIO_SUPPORTED(ha) ((ha)->device_type & DT_ZIO_SUPPORTED)
andrew.vasquez@qlogic.comea5b6382006-03-09 14:27:08 -08002297#define IS_OEM_001(ha) ((ha)->device_type & DT_OEM_001)
2298#define HAS_EXTENDED_IDS(ha) ((ha)->device_type & DT_EXTENDED_IDS)
2299
Linus Torvalds1da177e2005-04-16 15:20:36 -07002300 /* SRB cache. */
2301#define SRB_MIN_REQ 128
2302 mempool_t *srb_mempool;
2303
Andrew Vasquezfa2a1ce2005-07-06 10:32:07 -07002304 /* This spinlock is used to protect "io transactions", you must
Adrian Bunk04187262006-06-30 18:23:04 +02002305 * acquire it before doing any IO to the card, eg with RD_REG*() and
Linus Torvalds1da177e2005-04-16 15:20:36 -07002306 * WRT_REG*() for the duration of your entire commandtransaction.
2307 *
2308 * This spinlock is of lower priority than the io request lock.
2309 */
2310
2311 spinlock_t hardware_lock ____cacheline_aligned;
2312
Andrew Vasquez285d0322007-10-19 15:59:17 -07002313 int bars;
Benjamin Herrenschmidt09483912007-12-20 15:28:09 +11002314 int mem_only;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002315 device_reg_t __iomem *iobase; /* Base I/O address */
Andrew Vasquez37765412008-01-17 09:02:09 -08002316 resource_size_t pio_address;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002317#define MIN_IOBASE_LEN 0x100
2318
2319 /* ISP ring lock, rings, and indexes */
2320 dma_addr_t request_dma; /* Physical address. */
2321 request_t *request_ring; /* Base virtual address */
2322 request_t *request_ring_ptr; /* Current address. */
2323 uint16_t req_ring_index; /* Current index. */
2324 uint16_t req_q_cnt; /* Number of available entries. */
2325 uint16_t request_q_length;
2326
2327 dma_addr_t response_dma; /* Physical address. */
2328 response_t *response_ring; /* Base virtual address */
2329 response_t *response_ring_ptr; /* Current address. */
2330 uint16_t rsp_ring_index; /* Current index. */
2331 uint16_t response_q_length;
Andrew Vasquezfa2a1ce2005-07-06 10:32:07 -07002332
Andrew Vasquezfd34f552007-07-19 15:06:00 -07002333 struct isp_operations *isp_ops;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002334
2335 /* Outstandings ISP commands. */
2336 srb_t *outstanding_cmds[MAX_OUTSTANDING_COMMANDS];
Andrew Vasquezfa2a1ce2005-07-06 10:32:07 -07002337 uint32_t current_outstanding_cmd;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002338 srb_t *status_srb; /* Status continuation entry. */
2339
Linus Torvalds1da177e2005-04-16 15:20:36 -07002340 /* ISP configuration data. */
2341 uint16_t loop_id; /* Host adapter loop id */
Seokmann Ju2c3dfe32007-07-05 13:16:51 -07002342 uint16_t switch_cap;
2343#define FLOGI_SEQ_DEL BIT_8
2344#define FLOGI_MID_SUPPORT BIT_10
2345#define FLOGI_VSAN_SUPPORT BIT_12
2346#define FLOGI_SP_SUPPORT BIT_13
Linus Torvalds1da177e2005-04-16 15:20:36 -07002347 uint16_t fb_rev;
2348
2349 port_id_t d_id; /* Host adapter port id */
2350 uint16_t max_public_loop_ids;
2351 uint16_t min_external_loopid; /* First external loop Id */
2352
Andrew Vasquezd8b45212006-10-02 12:00:43 -07002353#define PORT_SPEED_UNKNOWN 0xFFFF
2354#define PORT_SPEED_1GB 0x00
2355#define PORT_SPEED_2GB 0x01
2356#define PORT_SPEED_4GB 0x03
Andrew Vasquezc3a2f0d2007-07-19 20:37:34 -07002357#define PORT_SPEED_8GB 0x04
Linus Torvalds1da177e2005-04-16 15:20:36 -07002358 uint16_t link_data_rate; /* F/W operating speed */
2359
2360 uint8_t current_topology;
2361 uint8_t prev_topology;
2362#define ISP_CFG_NL 1
2363#define ISP_CFG_N 2
2364#define ISP_CFG_FL 4
2365#define ISP_CFG_F 8
2366
2367 uint8_t operating_mode; /* F/W operating mode */
2368#define LOOP 0
2369#define P2P 1
2370#define LOOP_P2P 2
2371#define P2P_LOOP 3
2372
Andrew Vasquezfa2a1ce2005-07-06 10:32:07 -07002373 uint8_t marker_needed;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002374
2375 uint8_t interrupts_on;
2376
2377 /* HBA serial number */
2378 uint8_t serial0;
2379 uint8_t serial1;
2380 uint8_t serial2;
2381
2382 /* NVRAM configuration data */
Seokmann Ju281afe12007-07-26 13:43:34 -07002383#define MAX_NVRAM_SIZE 4096
2384#define VPD_OFFSET MAX_NVRAM_SIZE / 2
Andrew Vasquez3d716442005-07-06 10:30:26 -07002385 uint16_t nvram_size;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002386 uint16_t nvram_base;
Seokmann Ju281afe12007-07-26 13:43:34 -07002387 void *nvram;
andrew.vasquez@qlogic.com6f641792006-03-09 14:27:34 -08002388 uint16_t vpd_size;
2389 uint16_t vpd_base;
Seokmann Ju281afe12007-07-26 13:43:34 -07002390 void *vpd;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002391
2392 uint16_t loop_reset_delay;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002393 uint8_t retry_count;
2394 uint8_t login_timeout;
2395 uint16_t r_a_tov;
2396 int port_down_retry_count;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002397 uint8_t mbx_count;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002398 uint16_t last_loop_id;
Andrew Vasquezcca53352005-08-26 19:08:30 -07002399 uint16_t mgmt_svr_loop_id;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002400
Andrew Vasquezfa2a1ce2005-07-06 10:32:07 -07002401 uint32_t login_retry_count;
Andrew Vasquezdf7baa52006-10-13 09:33:39 -07002402 int max_q_depth;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002403
Andrew Vasquez0971de72008-04-03 13:13:18 -07002404 struct list_head work_list;
2405
Linus Torvalds1da177e2005-04-16 15:20:36 -07002406 /* Fibre Channel Device List. */
2407 struct list_head fcports;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002408
Linus Torvalds1da177e2005-04-16 15:20:36 -07002409 /* RSCN queue. */
2410 uint32_t rscn_queue[MAX_RSCN_COUNT];
2411 uint8_t rscn_in_ptr;
2412 uint8_t rscn_out_ptr;
2413
2414 /* SNS command interfaces. */
2415 ms_iocb_entry_t *ms_iocb;
2416 dma_addr_t ms_iocb_dma;
2417 struct ct_sns_pkt *ct_sns;
2418 dma_addr_t ct_sns_dma;
2419 /* SNS command interfaces for 2200. */
2420 struct sns_cmd_pkt *sns_cmd;
2421 dma_addr_t sns_cmd_dma;
2422
Andrew Vasquez88729e52006-06-23 16:10:50 -07002423#define SFP_DEV_SIZE 256
2424#define SFP_BLOCK_SIZE 64
2425 void *sfp_data;
2426 dma_addr_t sfp_data_dma;
2427
Christoph Hellwig39a11242006-02-14 18:46:22 +01002428 struct task_struct *dpc_thread;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002429 uint8_t dpc_active; /* DPC routine is active */
2430
2431 /* Timeout timers. */
Linus Torvalds1da177e2005-04-16 15:20:36 -07002432 uint8_t loop_down_abort_time; /* port down timer */
2433 atomic_t loop_down_timer; /* loop down timer */
2434 uint8_t link_down_timeout; /* link down timeout */
2435
2436 uint32_t timer_active;
2437 struct timer_list timer;
2438
2439 dma_addr_t gid_list_dma;
2440 struct gid_list_info *gid_list;
Andrew Vasquezabbd8872005-07-06 10:30:05 -07002441 int gid_list_info_size;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002442
Andrew Vasquezfa2a1ce2005-07-06 10:32:07 -07002443 /* Small DMA pool allocations -- maximum 256 bytes in length. */
Linus Torvalds1da177e2005-04-16 15:20:36 -07002444#define DMA_POOL_SIZE 256
2445 struct dma_pool *s_dma_pool;
2446
2447 dma_addr_t init_cb_dma;
Andrew Vasquez3d716442005-07-06 10:30:26 -07002448 init_cb_t *init_cb;
2449 int init_cb_size;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002450
Linus Torvalds1da177e2005-04-16 15:20:36 -07002451 /* These are used by mailbox operations. */
2452 volatile uint16_t mailbox_out[MAILBOX_REGISTER_COUNT];
2453
2454 mbx_cmd_t *mcp;
2455 unsigned long mbx_cmd_flags;
2456#define MBX_INTERRUPT 1
2457#define MBX_INTR_WAIT 2
2458#define MBX_UPDATE_FLASH_ACTIVE 3
2459
Seokmann Ju2c3dfe32007-07-05 13:16:51 -07002460 struct semaphore vport_sem; /* Virtual port synchronization */
Marcus Barrow0b05a1f2008-01-17 09:02:13 -08002461 struct completion mbx_cmd_comp; /* Serialize mbx access */
2462 struct completion mbx_intr_comp; /* Used for completion notification */
Linus Torvalds1da177e2005-04-16 15:20:36 -07002463
2464 uint32_t mbx_flags;
2465#define MBX_IN_PROGRESS BIT_0
2466#define MBX_BUSY BIT_1 /* Got the Access */
Andrew Vasquezfa2a1ce2005-07-06 10:32:07 -07002467#define MBX_SLEEPING_ON_SEM BIT_2
Linus Torvalds1da177e2005-04-16 15:20:36 -07002468#define MBX_POLLING_FOR_COMP BIT_3
2469#define MBX_COMPLETED BIT_4
Andrew Vasquezfa2a1ce2005-07-06 10:32:07 -07002470#define MBX_TIMEDOUT BIT_5
Linus Torvalds1da177e2005-04-16 15:20:36 -07002471#define MBX_ACCESS_TIMEDOUT BIT_6
2472
Linus Torvalds1da177e2005-04-16 15:20:36 -07002473 /* Basic firmware related information. */
Linus Torvalds1da177e2005-04-16 15:20:36 -07002474 uint16_t fw_major_version;
2475 uint16_t fw_minor_version;
2476 uint16_t fw_subminor_version;
2477 uint16_t fw_attributes;
2478 uint32_t fw_memory_size;
2479 uint32_t fw_transfer_size;
Andrew Vasquez441d1072006-05-17 15:09:34 -07002480 uint32_t fw_srisc_address;
2481#define RISC_START_ADDRESS_2100 0x1000
2482#define RISC_START_ADDRESS_2300 0x800
2483#define RISC_START_ADDRESS_2400 0x100000
Linus Torvalds1da177e2005-04-16 15:20:36 -07002484
2485 uint16_t fw_options[16]; /* slots: 1,2,3,10,11 */
2486 uint8_t fw_seriallink_options[4];
Andrew Vasquez3d716442005-07-06 10:30:26 -07002487 uint16_t fw_seriallink_options24[4];
Linus Torvalds1da177e2005-04-16 15:20:36 -07002488
2489 /* Firmware dump information. */
Andrew Vasqueza7a167b2006-06-23 16:10:29 -07002490 struct qla2xxx_fw_dump *fw_dump;
2491 uint32_t fw_dump_len;
Andrew Vasquezd4e3e042006-05-17 15:09:50 -07002492 int fw_dumped;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002493 int fw_dump_reading;
Andrew Vasqueza7a167b2006-06-23 16:10:29 -07002494 dma_addr_t eft_dma;
2495 void *eft;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002496
Andrew Vasquezdf613b92008-01-17 09:02:17 -08002497 struct dentry *dfs_dir;
2498 struct dentry *dfs_fce;
2499 dma_addr_t fce_dma;
2500 void *fce;
2501 uint32_t fce_bufs;
2502 uint16_t fce_mb[8];
2503 uint64_t fce_wr, fce_rd;
2504 struct mutex fce_mutex;
2505
Andrew Vasquezcb8dacb2008-04-03 13:13:19 -07002506 uint32_t hw_event_start;
2507 uint32_t hw_event_ptr;
2508 uint32_t hw_event_pause_errors;
2509
Linus Torvalds1da177e2005-04-16 15:20:36 -07002510 uint8_t host_str[16];
Andrew Vasquez3d716442005-07-06 10:30:26 -07002511 uint32_t pci_attr;
Andrew Vasqueza8488ab2007-01-29 10:22:19 -08002512 uint16_t chip_revision;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002513
2514 uint16_t product_id[4];
2515
2516 uint8_t model_number[16+1];
2517#define BINZERO "\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0"
2518 char *model_desc;
Andrew Vasquezcca53352005-08-26 19:08:30 -07002519 uint8_t adapter_id[16+1];
Linus Torvalds1da177e2005-04-16 15:20:36 -07002520
Andrew Vasquez3d716442005-07-06 10:30:26 -07002521 uint8_t *node_name;
2522 uint8_t *port_name;
Andrew Vasquez90991c82006-10-02 12:00:46 -07002523 uint8_t fabric_node_name[WWN_SIZE];
Linus Torvalds1da177e2005-04-16 15:20:36 -07002524 uint32_t isp_abort_cnt;
2525
andrew.vasquez@qlogic.com854165f2006-01-31 16:05:17 -08002526 /* Option ROM information. */
2527 char *optrom_buffer;
2528 uint32_t optrom_size;
2529 int optrom_state;
2530#define QLA_SWAITING 0
2531#define QLA_SREADING 1
2532#define QLA_SWRITING 2
Joe Carnucciob7cc1762007-09-20 14:07:35 -07002533 uint32_t optrom_region_start;
2534 uint32_t optrom_region_size;
andrew.vasquez@qlogic.com854165f2006-01-31 16:05:17 -08002535
Andrew Vasquez30c47662007-01-29 10:22:21 -08002536 /* PCI expansion ROM image information. */
2537#define ROM_CODE_TYPE_BIOS 0
2538#define ROM_CODE_TYPE_FCODE 1
2539#define ROM_CODE_TYPE_EFI 3
2540 uint8_t bios_revision[2];
2541 uint8_t efi_revision[2];
2542 uint8_t fcode_revision[16];
2543 uint32_t fw_revision[4];
2544
Andrew Vasquez7d232c72008-04-03 13:13:22 -07002545 uint16_t fdt_odd_index;
2546 uint32_t fdt_wrt_disable;
2547 uint32_t fdt_erase_cmd;
2548 uint32_t fdt_block_size;
2549 uint32_t fdt_unprotect_sec_cmd;
2550 uint32_t fdt_protect_sec_cmd;
2551
Linus Torvalds1da177e2005-04-16 15:20:36 -07002552 /* Needed for BEACON */
2553 uint16_t beacon_blink_led;
andrew.vasquez@qlogic.comf6df1442006-01-31 16:05:07 -08002554 uint8_t beacon_color_state;
2555#define QLA_LED_GRN_ON 0x01
2556#define QLA_LED_YLW_ON 0x02
2557#define QLA_LED_ABR_ON 0x04
2558#define QLA_LED_ALL_ON 0x07 /* yellow, green, amber. */
2559 /* ISP2322: red, green, amber. */
Andrew Vasquez4fdfefe2005-10-27 11:09:48 -07002560
2561 uint16_t zio_mode;
2562 uint16_t zio_timer;
andrew.vasquez@qlogic.com392e2f62006-01-31 16:05:02 -08002563 struct fc_host_statistics fc_host_stat;
Andrew Vasqueza8488ab2007-01-29 10:22:19 -08002564
2565 struct qla_msix_entry msix_entries[QLA_MSIX_ENTRIES];
Seokmann Ju2c3dfe32007-07-05 13:16:51 -07002566
2567 struct list_head vp_list; /* list of VP */
2568 struct fc_vport *fc_vport; /* holds fc_vport * for each vport */
Andrew Vasquezeb66dc62007-11-12 10:30:58 -08002569 unsigned long vp_idx_map[(MAX_MULTI_ID_FABRIC / 8) / sizeof(unsigned long)];
Seokmann Ju2c3dfe32007-07-05 13:16:51 -07002570 uint16_t num_vhosts; /* number of vports created */
2571 uint16_t num_vsans; /* number of vsan created */
2572 uint16_t vp_idx; /* vport ID */
2573
2574 struct scsi_qla_host *parent; /* holds pport */
2575 unsigned long vp_flags;
2576 struct list_head vp_fcports; /* list of fcports */
2577#define VP_IDX_ACQUIRED 0 /* bit no 0 */
2578#define VP_CREATE_NEEDED 1
2579#define VP_BIND_NEEDED 2
2580#define VP_DELETE_NEEDED 3
2581#define VP_SCR_NEEDED 4 /* State Change Request registration */
2582 atomic_t vp_state;
2583#define VP_OFFLINE 0
2584#define VP_ACTIVE 1
2585#define VP_FAILED 2
2586// #define VP_DISABLE 3
2587 uint16_t vp_err_state;
2588 uint16_t vp_prev_err_state;
2589#define VP_ERR_UNKWN 0
2590#define VP_ERR_PORTDWN 1
2591#define VP_ERR_FAB_UNSUPPORTED 2
2592#define VP_ERR_FAB_NORESOURCES 3
2593#define VP_ERR_FAB_LOGOUT 4
2594#define VP_ERR_ADAP_NORESOURCES 5
Seokmann Ju4d0ea242007-09-20 14:07:43 -07002595 uint16_t max_npiv_vports; /* 63 or 125 per topoloty */
Seokmann Ju2c3dfe32007-07-05 13:16:51 -07002596 int cur_vport_count;
Harihara Kadayam4d4df192008-04-03 13:13:26 -07002597
2598 struct qla_chip_state_84xx *cs84xx;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002599} scsi_qla_host_t;
2600
2601
2602/*
2603 * Macros to help code, maintain, etc.
2604 */
2605#define LOOP_TRANSITION(ha) \
2606 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \
Andrew Vasquez23443b12005-12-06 10:57:06 -08002607 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags) || \
Linus Torvalds1da177e2005-04-16 15:20:36 -07002608 atomic_read(&ha->loop_state) == LOOP_DOWN)
Andrew Vasquezfa2a1ce2005-07-06 10:32:07 -07002609
Linus Torvalds1da177e2005-04-16 15:20:36 -07002610#define qla_printk(level, ha, format, arg...) \
2611 dev_printk(level , &((ha)->pdev->dev) , format , ## arg)
2612
2613/*
2614 * qla2x00 local function return status codes
2615 */
2616#define MBS_MASK 0x3fff
2617
2618#define QLA_SUCCESS (MBS_COMMAND_COMPLETE & MBS_MASK)
2619#define QLA_INVALID_COMMAND (MBS_INVALID_COMMAND & MBS_MASK)
2620#define QLA_INTERFACE_ERROR (MBS_HOST_INTERFACE_ERROR & MBS_MASK)
2621#define QLA_TEST_FAILED (MBS_TEST_FAILED & MBS_MASK)
2622#define QLA_COMMAND_ERROR (MBS_COMMAND_ERROR & MBS_MASK)
2623#define QLA_PARAMETER_ERROR (MBS_COMMAND_PARAMETER_ERROR & MBS_MASK)
2624#define QLA_PORT_ID_USED (MBS_PORT_ID_USED & MBS_MASK)
2625#define QLA_LOOP_ID_USED (MBS_LOOP_ID_USED & MBS_MASK)
2626#define QLA_ALL_IDS_IN_USE (MBS_ALL_IDS_IN_USE & MBS_MASK)
2627#define QLA_NOT_LOGGED_IN (MBS_NOT_LOGGED_IN & MBS_MASK)
2628
2629#define QLA_FUNCTION_TIMEOUT 0x100
2630#define QLA_FUNCTION_PARAMETER_ERROR 0x101
2631#define QLA_FUNCTION_FAILED 0x102
2632#define QLA_MEMORY_ALLOC_FAILED 0x103
2633#define QLA_LOCK_TIMEOUT 0x104
2634#define QLA_ABORTED 0x105
2635#define QLA_SUSPENDED 0x106
2636#define QLA_BUSY 0x107
2637#define QLA_RSCNS_HANDLED 0x108
Andrew Vasquezcca53352005-08-26 19:08:30 -07002638#define QLA_ALREADY_REGISTERED 0x109
Linus Torvalds1da177e2005-04-16 15:20:36 -07002639
Linus Torvalds1da177e2005-04-16 15:20:36 -07002640#define NVRAM_DELAY() udelay(10)
2641
2642#define INVALID_HANDLE (MAX_OUTSTANDING_COMMANDS+1)
2643
2644/*
2645 * Flash support definitions
2646 */
andrew.vasquez@qlogic.com854165f2006-01-31 16:05:17 -08002647#define OPTROM_SIZE_2300 0x20000
2648#define OPTROM_SIZE_2322 0x100000
2649#define OPTROM_SIZE_24XX 0x100000
Andrew Vasquezc3a2f0d2007-07-19 20:37:34 -07002650#define OPTROM_SIZE_25XX 0x200000
Linus Torvalds1da177e2005-04-16 15:20:36 -07002651
2652#include "qla_gbl.h"
2653#include "qla_dbg.h"
2654#include "qla_inline.h"
Linus Torvalds1da177e2005-04-16 15:20:36 -07002655
Linus Torvalds1da177e2005-04-16 15:20:36 -07002656#define CMD_SP(Cmnd) ((Cmnd)->SCp.ptr)
2657#define CMD_COMPL_STATUS(Cmnd) ((Cmnd)->SCp.this_residual)
2658#define CMD_RESID_LEN(Cmnd) ((Cmnd)->SCp.buffers_residual)
2659#define CMD_SCSI_STATUS(Cmnd) ((Cmnd)->SCp.Status)
2660#define CMD_ACTUAL_SNSLEN(Cmnd) ((Cmnd)->SCp.Message)
2661#define CMD_ENTRY_STATUS(Cmnd) ((Cmnd)->SCp.have_data_in)
2662
2663#endif