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Zhang Wei173acc72008-03-01 07:42:48 -07001/*
2 * Freescale MPC85xx, MPC83xx DMA Engine support
3 *
4 * Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved.
5 *
6 * Author:
7 * Zhang Wei <wei.zhang@freescale.com>, Jul 2007
8 * Ebony Zhu <ebony.zhu@freescale.com>, May 2007
9 *
10 * Description:
11 * DMA engine driver for Freescale MPC8540 DMA controller, which is
12 * also fit for MPC8560, MPC8555, MPC8548, MPC8641, and etc.
13 * The support for MPC8349 DMA contorller is also added.
14 *
Ira W. Snydera7aea372009-04-23 16:17:54 -070015 * This driver instructs the DMA controller to issue the PCI Read Multiple
16 * command for PCI read operations, instead of using the default PCI Read Line
17 * command. Please be aware that this setting may result in read pre-fetching
18 * on some platforms.
19 *
Zhang Wei173acc72008-03-01 07:42:48 -070020 * This is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2 of the License, or
23 * (at your option) any later version.
24 *
25 */
26
27#include <linux/init.h>
28#include <linux/module.h>
29#include <linux/pci.h>
30#include <linux/interrupt.h>
31#include <linux/dmaengine.h>
32#include <linux/delay.h>
33#include <linux/dma-mapping.h>
34#include <linux/dmapool.h>
35#include <linux/of_platform.h>
36
Ira Snyderbbea0b62009-09-08 17:53:04 -070037#include <asm/fsldma.h>
Zhang Wei173acc72008-03-01 07:42:48 -070038#include "fsldma.h"
39
Ira Snydera1c03312010-01-06 13:34:05 +000040static void dma_init(struct fsldma_chan *chan)
Zhang Wei173acc72008-03-01 07:42:48 -070041{
42 /* Reset the channel */
Ira Snydera1c03312010-01-06 13:34:05 +000043 DMA_OUT(chan, &chan->regs->mr, 0, 32);
Zhang Wei173acc72008-03-01 07:42:48 -070044
Ira Snydera1c03312010-01-06 13:34:05 +000045 switch (chan->feature & FSL_DMA_IP_MASK) {
Zhang Wei173acc72008-03-01 07:42:48 -070046 case FSL_DMA_IP_85XX:
47 /* Set the channel to below modes:
48 * EIE - Error interrupt enable
49 * EOSIE - End of segments interrupt enable (basic mode)
50 * EOLNIE - End of links interrupt enable
51 */
Ira Snydera1c03312010-01-06 13:34:05 +000052 DMA_OUT(chan, &chan->regs->mr, FSL_DMA_MR_EIE
Zhang Wei173acc72008-03-01 07:42:48 -070053 | FSL_DMA_MR_EOLNIE | FSL_DMA_MR_EOSIE, 32);
54 break;
55 case FSL_DMA_IP_83XX:
56 /* Set the channel to below modes:
57 * EOTIE - End-of-transfer interrupt enable
Ira W. Snydera7aea372009-04-23 16:17:54 -070058 * PRC_RM - PCI read multiple
Zhang Wei173acc72008-03-01 07:42:48 -070059 */
Ira Snydera1c03312010-01-06 13:34:05 +000060 DMA_OUT(chan, &chan->regs->mr, FSL_DMA_MR_EOTIE
Ira W. Snydera7aea372009-04-23 16:17:54 -070061 | FSL_DMA_MR_PRC_RM, 32);
Zhang Wei173acc72008-03-01 07:42:48 -070062 break;
63 }
Zhang Wei173acc72008-03-01 07:42:48 -070064}
65
Ira Snydera1c03312010-01-06 13:34:05 +000066static void set_sr(struct fsldma_chan *chan, u32 val)
Zhang Wei173acc72008-03-01 07:42:48 -070067{
Ira Snydera1c03312010-01-06 13:34:05 +000068 DMA_OUT(chan, &chan->regs->sr, val, 32);
Zhang Wei173acc72008-03-01 07:42:48 -070069}
70
Ira Snydera1c03312010-01-06 13:34:05 +000071static u32 get_sr(struct fsldma_chan *chan)
Zhang Wei173acc72008-03-01 07:42:48 -070072{
Ira Snydera1c03312010-01-06 13:34:05 +000073 return DMA_IN(chan, &chan->regs->sr, 32);
Zhang Wei173acc72008-03-01 07:42:48 -070074}
75
Ira Snydera1c03312010-01-06 13:34:05 +000076static void set_desc_cnt(struct fsldma_chan *chan,
Zhang Wei173acc72008-03-01 07:42:48 -070077 struct fsl_dma_ld_hw *hw, u32 count)
78{
Ira Snydera1c03312010-01-06 13:34:05 +000079 hw->count = CPU_TO_DMA(chan, count, 32);
Zhang Wei173acc72008-03-01 07:42:48 -070080}
81
Ira Snydera1c03312010-01-06 13:34:05 +000082static void set_desc_src(struct fsldma_chan *chan,
Zhang Wei173acc72008-03-01 07:42:48 -070083 struct fsl_dma_ld_hw *hw, dma_addr_t src)
84{
85 u64 snoop_bits;
86
Ira Snydera1c03312010-01-06 13:34:05 +000087 snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX)
Zhang Wei173acc72008-03-01 07:42:48 -070088 ? ((u64)FSL_DMA_SATR_SREADTYPE_SNOOP_READ << 32) : 0;
Ira Snydera1c03312010-01-06 13:34:05 +000089 hw->src_addr = CPU_TO_DMA(chan, snoop_bits | src, 64);
Zhang Wei173acc72008-03-01 07:42:48 -070090}
91
Ira Snydera1c03312010-01-06 13:34:05 +000092static void set_desc_dst(struct fsldma_chan *chan,
Ira Snyder738f5f72010-01-06 13:34:02 +000093 struct fsl_dma_ld_hw *hw, dma_addr_t dst)
Zhang Wei173acc72008-03-01 07:42:48 -070094{
95 u64 snoop_bits;
96
Ira Snydera1c03312010-01-06 13:34:05 +000097 snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX)
Zhang Wei173acc72008-03-01 07:42:48 -070098 ? ((u64)FSL_DMA_DATR_DWRITETYPE_SNOOP_WRITE << 32) : 0;
Ira Snydera1c03312010-01-06 13:34:05 +000099 hw->dst_addr = CPU_TO_DMA(chan, snoop_bits | dst, 64);
Zhang Wei173acc72008-03-01 07:42:48 -0700100}
101
Ira Snydera1c03312010-01-06 13:34:05 +0000102static void set_desc_next(struct fsldma_chan *chan,
Zhang Wei173acc72008-03-01 07:42:48 -0700103 struct fsl_dma_ld_hw *hw, dma_addr_t next)
104{
105 u64 snoop_bits;
106
Ira Snydera1c03312010-01-06 13:34:05 +0000107 snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX)
Zhang Wei173acc72008-03-01 07:42:48 -0700108 ? FSL_DMA_SNEN : 0;
Ira Snydera1c03312010-01-06 13:34:05 +0000109 hw->next_ln_addr = CPU_TO_DMA(chan, snoop_bits | next, 64);
Zhang Wei173acc72008-03-01 07:42:48 -0700110}
111
Ira Snydera1c03312010-01-06 13:34:05 +0000112static void set_cdar(struct fsldma_chan *chan, dma_addr_t addr)
Zhang Wei173acc72008-03-01 07:42:48 -0700113{
Ira Snydera1c03312010-01-06 13:34:05 +0000114 DMA_OUT(chan, &chan->regs->cdar, addr | FSL_DMA_SNEN, 64);
Zhang Wei173acc72008-03-01 07:42:48 -0700115}
116
Ira Snydera1c03312010-01-06 13:34:05 +0000117static dma_addr_t get_cdar(struct fsldma_chan *chan)
Zhang Wei173acc72008-03-01 07:42:48 -0700118{
Ira Snydera1c03312010-01-06 13:34:05 +0000119 return DMA_IN(chan, &chan->regs->cdar, 64) & ~FSL_DMA_SNEN;
Zhang Wei173acc72008-03-01 07:42:48 -0700120}
121
Ira Snydera1c03312010-01-06 13:34:05 +0000122static dma_addr_t get_ndar(struct fsldma_chan *chan)
Zhang Wei173acc72008-03-01 07:42:48 -0700123{
Ira Snydera1c03312010-01-06 13:34:05 +0000124 return DMA_IN(chan, &chan->regs->ndar, 64);
Zhang Wei173acc72008-03-01 07:42:48 -0700125}
126
Ira Snydera1c03312010-01-06 13:34:05 +0000127static u32 get_bcr(struct fsldma_chan *chan)
Zhang Weif79abb62008-03-18 18:45:00 -0700128{
Ira Snydera1c03312010-01-06 13:34:05 +0000129 return DMA_IN(chan, &chan->regs->bcr, 32);
Zhang Weif79abb62008-03-18 18:45:00 -0700130}
131
Ira Snydera1c03312010-01-06 13:34:05 +0000132static int dma_is_idle(struct fsldma_chan *chan)
Zhang Wei173acc72008-03-01 07:42:48 -0700133{
Ira Snydera1c03312010-01-06 13:34:05 +0000134 u32 sr = get_sr(chan);
Zhang Wei173acc72008-03-01 07:42:48 -0700135 return (!(sr & FSL_DMA_SR_CB)) || (sr & FSL_DMA_SR_CH);
136}
137
Ira Snydera1c03312010-01-06 13:34:05 +0000138static void dma_start(struct fsldma_chan *chan)
Zhang Wei173acc72008-03-01 07:42:48 -0700139{
Ira Snyder272ca652010-01-06 13:33:59 +0000140 u32 mode;
Zhang Wei173acc72008-03-01 07:42:48 -0700141
Ira Snydera1c03312010-01-06 13:34:05 +0000142 mode = DMA_IN(chan, &chan->regs->mr, 32);
Ira Snyder272ca652010-01-06 13:33:59 +0000143
Ira Snydera1c03312010-01-06 13:34:05 +0000144 if ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) {
145 if (chan->feature & FSL_DMA_CHAN_PAUSE_EXT) {
146 DMA_OUT(chan, &chan->regs->bcr, 0, 32);
Ira Snyder272ca652010-01-06 13:33:59 +0000147 mode |= FSL_DMA_MR_EMP_EN;
148 } else {
149 mode &= ~FSL_DMA_MR_EMP_EN;
150 }
Ira Snyder43a1a3e2009-05-28 09:26:40 +0000151 }
Zhang Wei173acc72008-03-01 07:42:48 -0700152
Ira Snydera1c03312010-01-06 13:34:05 +0000153 if (chan->feature & FSL_DMA_CHAN_START_EXT)
Ira Snyder272ca652010-01-06 13:33:59 +0000154 mode |= FSL_DMA_MR_EMS_EN;
Zhang Wei173acc72008-03-01 07:42:48 -0700155 else
Ira Snyder272ca652010-01-06 13:33:59 +0000156 mode |= FSL_DMA_MR_CS;
Zhang Wei173acc72008-03-01 07:42:48 -0700157
Ira Snydera1c03312010-01-06 13:34:05 +0000158 DMA_OUT(chan, &chan->regs->mr, mode, 32);
Zhang Wei173acc72008-03-01 07:42:48 -0700159}
160
Ira Snydera1c03312010-01-06 13:34:05 +0000161static void dma_halt(struct fsldma_chan *chan)
Zhang Wei173acc72008-03-01 07:42:48 -0700162{
Ira Snyder272ca652010-01-06 13:33:59 +0000163 u32 mode;
Dan Williams900325a2009-03-02 15:33:46 -0700164 int i;
165
Ira Snydera1c03312010-01-06 13:34:05 +0000166 mode = DMA_IN(chan, &chan->regs->mr, 32);
Ira Snyder272ca652010-01-06 13:33:59 +0000167 mode |= FSL_DMA_MR_CA;
Ira Snydera1c03312010-01-06 13:34:05 +0000168 DMA_OUT(chan, &chan->regs->mr, mode, 32);
Ira Snyder272ca652010-01-06 13:33:59 +0000169
170 mode &= ~(FSL_DMA_MR_CS | FSL_DMA_MR_EMS_EN | FSL_DMA_MR_CA);
Ira Snydera1c03312010-01-06 13:34:05 +0000171 DMA_OUT(chan, &chan->regs->mr, mode, 32);
Zhang Wei173acc72008-03-01 07:42:48 -0700172
Dan Williams900325a2009-03-02 15:33:46 -0700173 for (i = 0; i < 100; i++) {
Ira Snydera1c03312010-01-06 13:34:05 +0000174 if (dma_is_idle(chan))
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000175 return;
176
Zhang Wei173acc72008-03-01 07:42:48 -0700177 udelay(10);
Dan Williams900325a2009-03-02 15:33:46 -0700178 }
Ira Snyder272ca652010-01-06 13:33:59 +0000179
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000180 if (!dma_is_idle(chan))
Ira Snydera1c03312010-01-06 13:34:05 +0000181 dev_err(chan->dev, "DMA halt timeout!\n");
Zhang Wei173acc72008-03-01 07:42:48 -0700182}
183
Ira Snydera1c03312010-01-06 13:34:05 +0000184static void set_ld_eol(struct fsldma_chan *chan,
Zhang Wei173acc72008-03-01 07:42:48 -0700185 struct fsl_desc_sw *desc)
186{
Ira Snyder776c8942009-05-15 11:33:20 -0700187 u64 snoop_bits;
188
Ira Snydera1c03312010-01-06 13:34:05 +0000189 snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX)
Ira Snyder776c8942009-05-15 11:33:20 -0700190 ? FSL_DMA_SNEN : 0;
191
Ira Snydera1c03312010-01-06 13:34:05 +0000192 desc->hw.next_ln_addr = CPU_TO_DMA(chan,
193 DMA_TO_CPU(chan, desc->hw.next_ln_addr, 64) | FSL_DMA_EOL
Ira Snyder776c8942009-05-15 11:33:20 -0700194 | snoop_bits, 64);
Zhang Wei173acc72008-03-01 07:42:48 -0700195}
196
Zhang Wei173acc72008-03-01 07:42:48 -0700197/**
198 * fsl_chan_set_src_loop_size - Set source address hold transfer size
Ira Snydera1c03312010-01-06 13:34:05 +0000199 * @chan : Freescale DMA channel
Zhang Wei173acc72008-03-01 07:42:48 -0700200 * @size : Address loop size, 0 for disable loop
201 *
202 * The set source address hold transfer size. The source
203 * address hold or loop transfer size is when the DMA transfer
204 * data from source address (SA), if the loop size is 4, the DMA will
205 * read data from SA, SA + 1, SA + 2, SA + 3, then loop back to SA,
206 * SA + 1 ... and so on.
207 */
Ira Snydera1c03312010-01-06 13:34:05 +0000208static void fsl_chan_set_src_loop_size(struct fsldma_chan *chan, int size)
Zhang Wei173acc72008-03-01 07:42:48 -0700209{
Ira Snyder272ca652010-01-06 13:33:59 +0000210 u32 mode;
211
Ira Snydera1c03312010-01-06 13:34:05 +0000212 mode = DMA_IN(chan, &chan->regs->mr, 32);
Ira Snyder272ca652010-01-06 13:33:59 +0000213
Zhang Wei173acc72008-03-01 07:42:48 -0700214 switch (size) {
215 case 0:
Ira Snyder272ca652010-01-06 13:33:59 +0000216 mode &= ~FSL_DMA_MR_SAHE;
Zhang Wei173acc72008-03-01 07:42:48 -0700217 break;
218 case 1:
219 case 2:
220 case 4:
221 case 8:
Ira Snyder272ca652010-01-06 13:33:59 +0000222 mode |= FSL_DMA_MR_SAHE | (__ilog2(size) << 14);
Zhang Wei173acc72008-03-01 07:42:48 -0700223 break;
224 }
Ira Snyder272ca652010-01-06 13:33:59 +0000225
Ira Snydera1c03312010-01-06 13:34:05 +0000226 DMA_OUT(chan, &chan->regs->mr, mode, 32);
Zhang Wei173acc72008-03-01 07:42:48 -0700227}
228
229/**
Ira Snyder738f5f72010-01-06 13:34:02 +0000230 * fsl_chan_set_dst_loop_size - Set destination address hold transfer size
Ira Snydera1c03312010-01-06 13:34:05 +0000231 * @chan : Freescale DMA channel
Zhang Wei173acc72008-03-01 07:42:48 -0700232 * @size : Address loop size, 0 for disable loop
233 *
234 * The set destination address hold transfer size. The destination
235 * address hold or loop transfer size is when the DMA transfer
236 * data to destination address (TA), if the loop size is 4, the DMA will
237 * write data to TA, TA + 1, TA + 2, TA + 3, then loop back to TA,
238 * TA + 1 ... and so on.
239 */
Ira Snydera1c03312010-01-06 13:34:05 +0000240static void fsl_chan_set_dst_loop_size(struct fsldma_chan *chan, int size)
Zhang Wei173acc72008-03-01 07:42:48 -0700241{
Ira Snyder272ca652010-01-06 13:33:59 +0000242 u32 mode;
243
Ira Snydera1c03312010-01-06 13:34:05 +0000244 mode = DMA_IN(chan, &chan->regs->mr, 32);
Ira Snyder272ca652010-01-06 13:33:59 +0000245
Zhang Wei173acc72008-03-01 07:42:48 -0700246 switch (size) {
247 case 0:
Ira Snyder272ca652010-01-06 13:33:59 +0000248 mode &= ~FSL_DMA_MR_DAHE;
Zhang Wei173acc72008-03-01 07:42:48 -0700249 break;
250 case 1:
251 case 2:
252 case 4:
253 case 8:
Ira Snyder272ca652010-01-06 13:33:59 +0000254 mode |= FSL_DMA_MR_DAHE | (__ilog2(size) << 16);
Zhang Wei173acc72008-03-01 07:42:48 -0700255 break;
256 }
Ira Snyder272ca652010-01-06 13:33:59 +0000257
Ira Snydera1c03312010-01-06 13:34:05 +0000258 DMA_OUT(chan, &chan->regs->mr, mode, 32);
Zhang Wei173acc72008-03-01 07:42:48 -0700259}
260
261/**
Ira Snydere6c7ecb2009-09-08 17:53:04 -0700262 * fsl_chan_set_request_count - Set DMA Request Count for external control
Ira Snydera1c03312010-01-06 13:34:05 +0000263 * @chan : Freescale DMA channel
Ira Snydere6c7ecb2009-09-08 17:53:04 -0700264 * @size : Number of bytes to transfer in a single request
265 *
266 * The Freescale DMA channel can be controlled by the external signal DREQ#.
267 * The DMA request count is how many bytes are allowed to transfer before
268 * pausing the channel, after which a new assertion of DREQ# resumes channel
269 * operation.
270 *
271 * A size of 0 disables external pause control. The maximum size is 1024.
272 */
Ira Snydera1c03312010-01-06 13:34:05 +0000273static void fsl_chan_set_request_count(struct fsldma_chan *chan, int size)
Ira Snydere6c7ecb2009-09-08 17:53:04 -0700274{
Ira Snyder272ca652010-01-06 13:33:59 +0000275 u32 mode;
276
Ira Snydere6c7ecb2009-09-08 17:53:04 -0700277 BUG_ON(size > 1024);
Ira Snyder272ca652010-01-06 13:33:59 +0000278
Ira Snydera1c03312010-01-06 13:34:05 +0000279 mode = DMA_IN(chan, &chan->regs->mr, 32);
Ira Snyder272ca652010-01-06 13:33:59 +0000280 mode |= (__ilog2(size) << 24) & 0x0f000000;
281
Ira Snydera1c03312010-01-06 13:34:05 +0000282 DMA_OUT(chan, &chan->regs->mr, mode, 32);
Ira Snydere6c7ecb2009-09-08 17:53:04 -0700283}
284
285/**
Zhang Wei173acc72008-03-01 07:42:48 -0700286 * fsl_chan_toggle_ext_pause - Toggle channel external pause status
Ira Snydera1c03312010-01-06 13:34:05 +0000287 * @chan : Freescale DMA channel
Ira Snydere6c7ecb2009-09-08 17:53:04 -0700288 * @enable : 0 is disabled, 1 is enabled.
Zhang Wei173acc72008-03-01 07:42:48 -0700289 *
Ira Snydere6c7ecb2009-09-08 17:53:04 -0700290 * The Freescale DMA channel can be controlled by the external signal DREQ#.
291 * The DMA Request Count feature should be used in addition to this feature
292 * to set the number of bytes to transfer before pausing the channel.
Zhang Wei173acc72008-03-01 07:42:48 -0700293 */
Ira Snydera1c03312010-01-06 13:34:05 +0000294static void fsl_chan_toggle_ext_pause(struct fsldma_chan *chan, int enable)
Zhang Wei173acc72008-03-01 07:42:48 -0700295{
Ira Snydere6c7ecb2009-09-08 17:53:04 -0700296 if (enable)
Ira Snydera1c03312010-01-06 13:34:05 +0000297 chan->feature |= FSL_DMA_CHAN_PAUSE_EXT;
Ira Snydere6c7ecb2009-09-08 17:53:04 -0700298 else
Ira Snydera1c03312010-01-06 13:34:05 +0000299 chan->feature &= ~FSL_DMA_CHAN_PAUSE_EXT;
Zhang Wei173acc72008-03-01 07:42:48 -0700300}
301
302/**
303 * fsl_chan_toggle_ext_start - Toggle channel external start status
Ira Snydera1c03312010-01-06 13:34:05 +0000304 * @chan : Freescale DMA channel
Zhang Wei173acc72008-03-01 07:42:48 -0700305 * @enable : 0 is disabled, 1 is enabled.
306 *
307 * If enable the external start, the channel can be started by an
308 * external DMA start pin. So the dma_start() does not start the
309 * transfer immediately. The DMA channel will wait for the
310 * control pin asserted.
311 */
Ira Snydera1c03312010-01-06 13:34:05 +0000312static void fsl_chan_toggle_ext_start(struct fsldma_chan *chan, int enable)
Zhang Wei173acc72008-03-01 07:42:48 -0700313{
314 if (enable)
Ira Snydera1c03312010-01-06 13:34:05 +0000315 chan->feature |= FSL_DMA_CHAN_START_EXT;
Zhang Wei173acc72008-03-01 07:42:48 -0700316 else
Ira Snydera1c03312010-01-06 13:34:05 +0000317 chan->feature &= ~FSL_DMA_CHAN_START_EXT;
Zhang Wei173acc72008-03-01 07:42:48 -0700318}
319
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000320static void append_ld_queue(struct fsldma_chan *chan,
321 struct fsl_desc_sw *desc)
322{
323 struct fsl_desc_sw *tail = to_fsl_desc(chan->ld_pending.prev);
324
325 if (list_empty(&chan->ld_pending))
326 goto out_splice;
327
328 /*
329 * Add the hardware descriptor to the chain of hardware descriptors
330 * that already exists in memory.
331 *
332 * This will un-set the EOL bit of the existing transaction, and the
333 * last link in this transaction will become the EOL descriptor.
334 */
335 set_desc_next(chan, &tail->hw, desc->async_tx.phys);
336
337 /*
338 * Add the software descriptor and all children to the list
339 * of pending transactions
340 */
341out_splice:
342 list_splice_tail_init(&desc->tx_list, &chan->ld_pending);
343}
344
Zhang Wei173acc72008-03-01 07:42:48 -0700345static dma_cookie_t fsl_dma_tx_submit(struct dma_async_tx_descriptor *tx)
346{
Ira Snydera1c03312010-01-06 13:34:05 +0000347 struct fsldma_chan *chan = to_fsl_chan(tx->chan);
Dan Williamseda34232009-09-08 17:53:02 -0700348 struct fsl_desc_sw *desc = tx_to_fsl_desc(tx);
349 struct fsl_desc_sw *child;
Zhang Wei173acc72008-03-01 07:42:48 -0700350 unsigned long flags;
351 dma_cookie_t cookie;
352
Ira Snydera1c03312010-01-06 13:34:05 +0000353 spin_lock_irqsave(&chan->desc_lock, flags);
Zhang Wei173acc72008-03-01 07:42:48 -0700354
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000355 /*
356 * assign cookies to all of the software descriptors
357 * that make up this transaction
358 */
Ira Snydera1c03312010-01-06 13:34:05 +0000359 cookie = chan->common.cookie;
Dan Williamseda34232009-09-08 17:53:02 -0700360 list_for_each_entry(child, &desc->tx_list, node) {
Ira Snyderbcfb7462009-05-15 14:27:16 -0700361 cookie++;
362 if (cookie < 0)
363 cookie = 1;
Zhang Wei173acc72008-03-01 07:42:48 -0700364
Steven J. Magnani6ca3a7a2010-02-25 13:39:30 -0600365 child->async_tx.cookie = cookie;
Ira Snyderbcfb7462009-05-15 14:27:16 -0700366 }
367
Ira Snydera1c03312010-01-06 13:34:05 +0000368 chan->common.cookie = cookie;
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000369
370 /* put this transaction onto the tail of the pending queue */
Ira Snydera1c03312010-01-06 13:34:05 +0000371 append_ld_queue(chan, desc);
Zhang Wei173acc72008-03-01 07:42:48 -0700372
Ira Snydera1c03312010-01-06 13:34:05 +0000373 spin_unlock_irqrestore(&chan->desc_lock, flags);
Zhang Wei173acc72008-03-01 07:42:48 -0700374
375 return cookie;
376}
377
378/**
379 * fsl_dma_alloc_descriptor - Allocate descriptor from channel's DMA pool.
Ira Snydera1c03312010-01-06 13:34:05 +0000380 * @chan : Freescale DMA channel
Zhang Wei173acc72008-03-01 07:42:48 -0700381 *
382 * Return - The descriptor allocated. NULL for failed.
383 */
384static struct fsl_desc_sw *fsl_dma_alloc_descriptor(
Ira Snydera1c03312010-01-06 13:34:05 +0000385 struct fsldma_chan *chan)
Zhang Wei173acc72008-03-01 07:42:48 -0700386{
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000387 struct fsl_desc_sw *desc;
Zhang Wei173acc72008-03-01 07:42:48 -0700388 dma_addr_t pdesc;
Zhang Wei173acc72008-03-01 07:42:48 -0700389
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000390 desc = dma_pool_alloc(chan->desc_pool, GFP_ATOMIC, &pdesc);
391 if (!desc) {
392 dev_dbg(chan->dev, "out of memory for link desc\n");
393 return NULL;
Zhang Wei173acc72008-03-01 07:42:48 -0700394 }
395
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000396 memset(desc, 0, sizeof(*desc));
397 INIT_LIST_HEAD(&desc->tx_list);
398 dma_async_tx_descriptor_init(&desc->async_tx, &chan->common);
399 desc->async_tx.tx_submit = fsl_dma_tx_submit;
400 desc->async_tx.phys = pdesc;
401
402 return desc;
Zhang Wei173acc72008-03-01 07:42:48 -0700403}
404
405
406/**
407 * fsl_dma_alloc_chan_resources - Allocate resources for DMA channel.
Ira Snydera1c03312010-01-06 13:34:05 +0000408 * @chan : Freescale DMA channel
Zhang Wei173acc72008-03-01 07:42:48 -0700409 *
410 * This function will create a dma pool for descriptor allocation.
411 *
412 * Return - The number of descriptors allocated.
413 */
Ira Snydera1c03312010-01-06 13:34:05 +0000414static int fsl_dma_alloc_chan_resources(struct dma_chan *dchan)
Zhang Wei173acc72008-03-01 07:42:48 -0700415{
Ira Snydera1c03312010-01-06 13:34:05 +0000416 struct fsldma_chan *chan = to_fsl_chan(dchan);
Timur Tabi77cd62e2008-09-26 17:00:11 -0700417
418 /* Has this channel already been allocated? */
Ira Snydera1c03312010-01-06 13:34:05 +0000419 if (chan->desc_pool)
Timur Tabi77cd62e2008-09-26 17:00:11 -0700420 return 1;
Zhang Wei173acc72008-03-01 07:42:48 -0700421
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000422 /*
423 * We need the descriptor to be aligned to 32bytes
Zhang Wei173acc72008-03-01 07:42:48 -0700424 * for meeting FSL DMA specification requirement.
425 */
Ira Snydera1c03312010-01-06 13:34:05 +0000426 chan->desc_pool = dma_pool_create("fsl_dma_engine_desc_pool",
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000427 chan->dev,
428 sizeof(struct fsl_desc_sw),
429 __alignof__(struct fsl_desc_sw), 0);
Ira Snydera1c03312010-01-06 13:34:05 +0000430 if (!chan->desc_pool) {
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000431 dev_err(chan->dev, "unable to allocate channel %d "
432 "descriptor pool\n", chan->id);
433 return -ENOMEM;
Zhang Wei173acc72008-03-01 07:42:48 -0700434 }
435
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000436 /* there is at least one descriptor free to be allocated */
Zhang Wei173acc72008-03-01 07:42:48 -0700437 return 1;
438}
439
440/**
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000441 * fsldma_free_desc_list - Free all descriptors in a queue
442 * @chan: Freescae DMA channel
443 * @list: the list to free
444 *
445 * LOCKING: must hold chan->desc_lock
446 */
447static void fsldma_free_desc_list(struct fsldma_chan *chan,
448 struct list_head *list)
449{
450 struct fsl_desc_sw *desc, *_desc;
451
452 list_for_each_entry_safe(desc, _desc, list, node) {
453 list_del(&desc->node);
454 dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys);
455 }
456}
457
458static void fsldma_free_desc_list_reverse(struct fsldma_chan *chan,
459 struct list_head *list)
460{
461 struct fsl_desc_sw *desc, *_desc;
462
463 list_for_each_entry_safe_reverse(desc, _desc, list, node) {
464 list_del(&desc->node);
465 dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys);
466 }
467}
468
469/**
Zhang Wei173acc72008-03-01 07:42:48 -0700470 * fsl_dma_free_chan_resources - Free all resources of the channel.
Ira Snydera1c03312010-01-06 13:34:05 +0000471 * @chan : Freescale DMA channel
Zhang Wei173acc72008-03-01 07:42:48 -0700472 */
Ira Snydera1c03312010-01-06 13:34:05 +0000473static void fsl_dma_free_chan_resources(struct dma_chan *dchan)
Zhang Wei173acc72008-03-01 07:42:48 -0700474{
Ira Snydera1c03312010-01-06 13:34:05 +0000475 struct fsldma_chan *chan = to_fsl_chan(dchan);
Zhang Wei173acc72008-03-01 07:42:48 -0700476 unsigned long flags;
477
Ira Snydera1c03312010-01-06 13:34:05 +0000478 dev_dbg(chan->dev, "Free all channel resources.\n");
479 spin_lock_irqsave(&chan->desc_lock, flags);
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000480 fsldma_free_desc_list(chan, &chan->ld_pending);
481 fsldma_free_desc_list(chan, &chan->ld_running);
Ira Snydera1c03312010-01-06 13:34:05 +0000482 spin_unlock_irqrestore(&chan->desc_lock, flags);
Timur Tabi77cd62e2008-09-26 17:00:11 -0700483
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000484 dma_pool_destroy(chan->desc_pool);
Ira Snydera1c03312010-01-06 13:34:05 +0000485 chan->desc_pool = NULL;
Zhang Wei173acc72008-03-01 07:42:48 -0700486}
487
Zhang Wei2187c262008-03-13 17:45:28 -0700488static struct dma_async_tx_descriptor *
Ira Snydera1c03312010-01-06 13:34:05 +0000489fsl_dma_prep_interrupt(struct dma_chan *dchan, unsigned long flags)
Zhang Wei2187c262008-03-13 17:45:28 -0700490{
Ira Snydera1c03312010-01-06 13:34:05 +0000491 struct fsldma_chan *chan;
Zhang Wei2187c262008-03-13 17:45:28 -0700492 struct fsl_desc_sw *new;
493
Ira Snydera1c03312010-01-06 13:34:05 +0000494 if (!dchan)
Zhang Wei2187c262008-03-13 17:45:28 -0700495 return NULL;
496
Ira Snydera1c03312010-01-06 13:34:05 +0000497 chan = to_fsl_chan(dchan);
Zhang Wei2187c262008-03-13 17:45:28 -0700498
Ira Snydera1c03312010-01-06 13:34:05 +0000499 new = fsl_dma_alloc_descriptor(chan);
Zhang Wei2187c262008-03-13 17:45:28 -0700500 if (!new) {
Ira Snydera1c03312010-01-06 13:34:05 +0000501 dev_err(chan->dev, "No free memory for link descriptor\n");
Zhang Wei2187c262008-03-13 17:45:28 -0700502 return NULL;
503 }
504
505 new->async_tx.cookie = -EBUSY;
Dan Williams636bdea2008-04-17 20:17:26 -0700506 new->async_tx.flags = flags;
Zhang Wei2187c262008-03-13 17:45:28 -0700507
Zhang Weif79abb62008-03-18 18:45:00 -0700508 /* Insert the link descriptor to the LD ring */
Dan Williamseda34232009-09-08 17:53:02 -0700509 list_add_tail(&new->node, &new->tx_list);
Zhang Weif79abb62008-03-18 18:45:00 -0700510
Zhang Wei2187c262008-03-13 17:45:28 -0700511 /* Set End-of-link to the last link descriptor of new list*/
Ira Snydera1c03312010-01-06 13:34:05 +0000512 set_ld_eol(chan, new);
Zhang Wei2187c262008-03-13 17:45:28 -0700513
514 return &new->async_tx;
515}
516
Zhang Wei173acc72008-03-01 07:42:48 -0700517static struct dma_async_tx_descriptor *fsl_dma_prep_memcpy(
Ira Snydera1c03312010-01-06 13:34:05 +0000518 struct dma_chan *dchan, dma_addr_t dma_dst, dma_addr_t dma_src,
Zhang Wei173acc72008-03-01 07:42:48 -0700519 size_t len, unsigned long flags)
520{
Ira Snydera1c03312010-01-06 13:34:05 +0000521 struct fsldma_chan *chan;
Zhang Wei173acc72008-03-01 07:42:48 -0700522 struct fsl_desc_sw *first = NULL, *prev = NULL, *new;
523 size_t copy;
Zhang Wei173acc72008-03-01 07:42:48 -0700524
Ira Snydera1c03312010-01-06 13:34:05 +0000525 if (!dchan)
Zhang Wei173acc72008-03-01 07:42:48 -0700526 return NULL;
527
528 if (!len)
529 return NULL;
530
Ira Snydera1c03312010-01-06 13:34:05 +0000531 chan = to_fsl_chan(dchan);
Zhang Wei173acc72008-03-01 07:42:48 -0700532
533 do {
534
535 /* Allocate the link descriptor from DMA pool */
Ira Snydera1c03312010-01-06 13:34:05 +0000536 new = fsl_dma_alloc_descriptor(chan);
Zhang Wei173acc72008-03-01 07:42:48 -0700537 if (!new) {
Ira Snydera1c03312010-01-06 13:34:05 +0000538 dev_err(chan->dev,
Zhang Wei173acc72008-03-01 07:42:48 -0700539 "No free memory for link descriptor\n");
Ira Snyder2e077f82009-05-15 09:59:46 -0700540 goto fail;
Zhang Wei173acc72008-03-01 07:42:48 -0700541 }
542#ifdef FSL_DMA_LD_DEBUG
Ira Snydera1c03312010-01-06 13:34:05 +0000543 dev_dbg(chan->dev, "new link desc alloc %p\n", new);
Zhang Wei173acc72008-03-01 07:42:48 -0700544#endif
545
Zhang Wei56822842008-03-13 10:45:27 -0700546 copy = min(len, (size_t)FSL_DMA_BCR_MAX_CNT);
Zhang Wei173acc72008-03-01 07:42:48 -0700547
Ira Snydera1c03312010-01-06 13:34:05 +0000548 set_desc_cnt(chan, &new->hw, copy);
549 set_desc_src(chan, &new->hw, dma_src);
550 set_desc_dst(chan, &new->hw, dma_dst);
Zhang Wei173acc72008-03-01 07:42:48 -0700551
552 if (!first)
553 first = new;
554 else
Ira Snydera1c03312010-01-06 13:34:05 +0000555 set_desc_next(chan, &prev->hw, new->async_tx.phys);
Zhang Wei173acc72008-03-01 07:42:48 -0700556
557 new->async_tx.cookie = 0;
Dan Williams636bdea2008-04-17 20:17:26 -0700558 async_tx_ack(&new->async_tx);
Zhang Wei173acc72008-03-01 07:42:48 -0700559
560 prev = new;
561 len -= copy;
562 dma_src += copy;
Ira Snyder738f5f72010-01-06 13:34:02 +0000563 dma_dst += copy;
Zhang Wei173acc72008-03-01 07:42:48 -0700564
565 /* Insert the link descriptor to the LD ring */
Dan Williamseda34232009-09-08 17:53:02 -0700566 list_add_tail(&new->node, &first->tx_list);
Zhang Wei173acc72008-03-01 07:42:48 -0700567 } while (len);
568
Dan Williams636bdea2008-04-17 20:17:26 -0700569 new->async_tx.flags = flags; /* client is in control of this ack */
Zhang Wei173acc72008-03-01 07:42:48 -0700570 new->async_tx.cookie = -EBUSY;
571
572 /* Set End-of-link to the last link descriptor of new list*/
Ira Snydera1c03312010-01-06 13:34:05 +0000573 set_ld_eol(chan, new);
Zhang Wei173acc72008-03-01 07:42:48 -0700574
Ira Snyder2e077f82009-05-15 09:59:46 -0700575 return &first->async_tx;
576
577fail:
578 if (!first)
579 return NULL;
580
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000581 fsldma_free_desc_list_reverse(chan, &first->tx_list);
Ira Snyder2e077f82009-05-15 09:59:46 -0700582 return NULL;
Zhang Wei173acc72008-03-01 07:42:48 -0700583}
584
585/**
Ira Snyderbbea0b62009-09-08 17:53:04 -0700586 * fsl_dma_prep_slave_sg - prepare descriptors for a DMA_SLAVE transaction
587 * @chan: DMA channel
588 * @sgl: scatterlist to transfer to/from
589 * @sg_len: number of entries in @scatterlist
590 * @direction: DMA direction
591 * @flags: DMAEngine flags
592 *
593 * Prepare a set of descriptors for a DMA_SLAVE transaction. Following the
594 * DMA_SLAVE API, this gets the device-specific information from the
595 * chan->private variable.
596 */
597static struct dma_async_tx_descriptor *fsl_dma_prep_slave_sg(
Ira Snydera1c03312010-01-06 13:34:05 +0000598 struct dma_chan *dchan, struct scatterlist *sgl, unsigned int sg_len,
Ira Snyderbbea0b62009-09-08 17:53:04 -0700599 enum dma_data_direction direction, unsigned long flags)
600{
Ira Snydera1c03312010-01-06 13:34:05 +0000601 struct fsldma_chan *chan;
Ira Snyderbbea0b62009-09-08 17:53:04 -0700602 struct fsl_desc_sw *first = NULL, *prev = NULL, *new = NULL;
603 struct fsl_dma_slave *slave;
Ira Snyderbbea0b62009-09-08 17:53:04 -0700604 size_t copy;
605
606 int i;
607 struct scatterlist *sg;
608 size_t sg_used;
609 size_t hw_used;
610 struct fsl_dma_hw_addr *hw;
611 dma_addr_t dma_dst, dma_src;
612
Ira Snydera1c03312010-01-06 13:34:05 +0000613 if (!dchan)
Ira Snyderbbea0b62009-09-08 17:53:04 -0700614 return NULL;
615
Ira Snydera1c03312010-01-06 13:34:05 +0000616 if (!dchan->private)
Ira Snyderbbea0b62009-09-08 17:53:04 -0700617 return NULL;
618
Ira Snydera1c03312010-01-06 13:34:05 +0000619 chan = to_fsl_chan(dchan);
620 slave = dchan->private;
Ira Snyderbbea0b62009-09-08 17:53:04 -0700621
622 if (list_empty(&slave->addresses))
623 return NULL;
624
625 hw = list_first_entry(&slave->addresses, struct fsl_dma_hw_addr, entry);
626 hw_used = 0;
627
628 /*
629 * Build the hardware transaction to copy from the scatterlist to
630 * the hardware, or from the hardware to the scatterlist
631 *
632 * If you are copying from the hardware to the scatterlist and it
633 * takes two hardware entries to fill an entire page, then both
634 * hardware entries will be coalesced into the same page
635 *
636 * If you are copying from the scatterlist to the hardware and a
637 * single page can fill two hardware entries, then the data will
638 * be read out of the page into the first hardware entry, and so on
639 */
640 for_each_sg(sgl, sg, sg_len, i) {
641 sg_used = 0;
642
643 /* Loop until the entire scatterlist entry is used */
644 while (sg_used < sg_dma_len(sg)) {
645
646 /*
647 * If we've used up the current hardware address/length
648 * pair, we need to load a new one
649 *
650 * This is done in a while loop so that descriptors with
651 * length == 0 will be skipped
652 */
653 while (hw_used >= hw->length) {
654
655 /*
656 * If the current hardware entry is the last
657 * entry in the list, we're finished
658 */
659 if (list_is_last(&hw->entry, &slave->addresses))
660 goto finished;
661
662 /* Get the next hardware address/length pair */
663 hw = list_entry(hw->entry.next,
664 struct fsl_dma_hw_addr, entry);
665 hw_used = 0;
666 }
667
668 /* Allocate the link descriptor from DMA pool */
Ira Snydera1c03312010-01-06 13:34:05 +0000669 new = fsl_dma_alloc_descriptor(chan);
Ira Snyderbbea0b62009-09-08 17:53:04 -0700670 if (!new) {
Ira Snydera1c03312010-01-06 13:34:05 +0000671 dev_err(chan->dev, "No free memory for "
Ira Snyderbbea0b62009-09-08 17:53:04 -0700672 "link descriptor\n");
673 goto fail;
674 }
675#ifdef FSL_DMA_LD_DEBUG
Ira Snydera1c03312010-01-06 13:34:05 +0000676 dev_dbg(chan->dev, "new link desc alloc %p\n", new);
Ira Snyderbbea0b62009-09-08 17:53:04 -0700677#endif
678
679 /*
680 * Calculate the maximum number of bytes to transfer,
681 * making sure it is less than the DMA controller limit
682 */
683 copy = min_t(size_t, sg_dma_len(sg) - sg_used,
684 hw->length - hw_used);
685 copy = min_t(size_t, copy, FSL_DMA_BCR_MAX_CNT);
686
687 /*
688 * DMA_FROM_DEVICE
689 * from the hardware to the scatterlist
690 *
691 * DMA_TO_DEVICE
692 * from the scatterlist to the hardware
693 */
694 if (direction == DMA_FROM_DEVICE) {
695 dma_src = hw->address + hw_used;
696 dma_dst = sg_dma_address(sg) + sg_used;
697 } else {
698 dma_src = sg_dma_address(sg) + sg_used;
699 dma_dst = hw->address + hw_used;
700 }
701
702 /* Fill in the descriptor */
Ira Snydera1c03312010-01-06 13:34:05 +0000703 set_desc_cnt(chan, &new->hw, copy);
704 set_desc_src(chan, &new->hw, dma_src);
705 set_desc_dst(chan, &new->hw, dma_dst);
Ira Snyderbbea0b62009-09-08 17:53:04 -0700706
707 /*
708 * If this is not the first descriptor, chain the
709 * current descriptor after the previous descriptor
710 */
711 if (!first) {
712 first = new;
713 } else {
Ira Snydera1c03312010-01-06 13:34:05 +0000714 set_desc_next(chan, &prev->hw,
Ira Snyderbbea0b62009-09-08 17:53:04 -0700715 new->async_tx.phys);
716 }
717
718 new->async_tx.cookie = 0;
719 async_tx_ack(&new->async_tx);
720
721 prev = new;
722 sg_used += copy;
723 hw_used += copy;
724
725 /* Insert the link descriptor into the LD ring */
726 list_add_tail(&new->node, &first->tx_list);
727 }
728 }
729
730finished:
731
732 /* All of the hardware address/length pairs had length == 0 */
733 if (!first || !new)
734 return NULL;
735
736 new->async_tx.flags = flags;
737 new->async_tx.cookie = -EBUSY;
738
739 /* Set End-of-link to the last link descriptor of new list */
Ira Snydera1c03312010-01-06 13:34:05 +0000740 set_ld_eol(chan, new);
Ira Snyderbbea0b62009-09-08 17:53:04 -0700741
742 /* Enable extra controller features */
Ira Snydera1c03312010-01-06 13:34:05 +0000743 if (chan->set_src_loop_size)
744 chan->set_src_loop_size(chan, slave->src_loop_size);
Ira Snyderbbea0b62009-09-08 17:53:04 -0700745
Ira Snydera1c03312010-01-06 13:34:05 +0000746 if (chan->set_dst_loop_size)
747 chan->set_dst_loop_size(chan, slave->dst_loop_size);
Ira Snyderbbea0b62009-09-08 17:53:04 -0700748
Ira Snydera1c03312010-01-06 13:34:05 +0000749 if (chan->toggle_ext_start)
750 chan->toggle_ext_start(chan, slave->external_start);
Ira Snyderbbea0b62009-09-08 17:53:04 -0700751
Ira Snydera1c03312010-01-06 13:34:05 +0000752 if (chan->toggle_ext_pause)
753 chan->toggle_ext_pause(chan, slave->external_pause);
Ira Snyderbbea0b62009-09-08 17:53:04 -0700754
Ira Snydera1c03312010-01-06 13:34:05 +0000755 if (chan->set_request_count)
756 chan->set_request_count(chan, slave->request_count);
Ira Snyderbbea0b62009-09-08 17:53:04 -0700757
758 return &first->async_tx;
759
760fail:
761 /* If first was not set, then we failed to allocate the very first
762 * descriptor, and we're done */
763 if (!first)
764 return NULL;
765
766 /*
767 * First is set, so all of the descriptors we allocated have been added
768 * to first->tx_list, INCLUDING "first" itself. Therefore we
769 * must traverse the list backwards freeing each descriptor in turn
770 *
771 * We're re-using variables for the loop, oh well
772 */
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000773 fsldma_free_desc_list_reverse(chan, &first->tx_list);
Ira Snyderbbea0b62009-09-08 17:53:04 -0700774 return NULL;
775}
776
Ira Snydera1c03312010-01-06 13:34:05 +0000777static void fsl_dma_device_terminate_all(struct dma_chan *dchan)
Ira Snyderbbea0b62009-09-08 17:53:04 -0700778{
Ira Snydera1c03312010-01-06 13:34:05 +0000779 struct fsldma_chan *chan;
Ira Snyderbbea0b62009-09-08 17:53:04 -0700780 unsigned long flags;
781
Ira Snydera1c03312010-01-06 13:34:05 +0000782 if (!dchan)
Ira Snyderbbea0b62009-09-08 17:53:04 -0700783 return;
784
Ira Snydera1c03312010-01-06 13:34:05 +0000785 chan = to_fsl_chan(dchan);
Ira Snyderbbea0b62009-09-08 17:53:04 -0700786
787 /* Halt the DMA engine */
Ira Snydera1c03312010-01-06 13:34:05 +0000788 dma_halt(chan);
Ira Snyderbbea0b62009-09-08 17:53:04 -0700789
Ira Snydera1c03312010-01-06 13:34:05 +0000790 spin_lock_irqsave(&chan->desc_lock, flags);
Ira Snyderbbea0b62009-09-08 17:53:04 -0700791
792 /* Remove and free all of the descriptors in the LD queue */
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000793 fsldma_free_desc_list(chan, &chan->ld_pending);
794 fsldma_free_desc_list(chan, &chan->ld_running);
Ira Snyderbbea0b62009-09-08 17:53:04 -0700795
Ira Snydera1c03312010-01-06 13:34:05 +0000796 spin_unlock_irqrestore(&chan->desc_lock, flags);
Ira Snyderbbea0b62009-09-08 17:53:04 -0700797}
798
799/**
Zhang Wei173acc72008-03-01 07:42:48 -0700800 * fsl_dma_update_completed_cookie - Update the completed cookie.
Ira Snydera1c03312010-01-06 13:34:05 +0000801 * @chan : Freescale DMA channel
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000802 *
803 * CONTEXT: hardirq
Zhang Wei173acc72008-03-01 07:42:48 -0700804 */
Ira Snydera1c03312010-01-06 13:34:05 +0000805static void fsl_dma_update_completed_cookie(struct fsldma_chan *chan)
Zhang Wei173acc72008-03-01 07:42:48 -0700806{
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000807 struct fsl_desc_sw *desc;
808 unsigned long flags;
809 dma_cookie_t cookie;
Zhang Wei173acc72008-03-01 07:42:48 -0700810
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000811 spin_lock_irqsave(&chan->desc_lock, flags);
Zhang Wei173acc72008-03-01 07:42:48 -0700812
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000813 if (list_empty(&chan->ld_running)) {
814 dev_dbg(chan->dev, "no running descriptors\n");
815 goto out_unlock;
Zhang Wei173acc72008-03-01 07:42:48 -0700816 }
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000817
818 /* Get the last descriptor, update the cookie to that */
819 desc = to_fsl_desc(chan->ld_running.prev);
820 if (dma_is_idle(chan))
821 cookie = desc->async_tx.cookie;
822 else
823 cookie = desc->async_tx.cookie - 1;
824
825 chan->completed_cookie = cookie;
826
827out_unlock:
828 spin_unlock_irqrestore(&chan->desc_lock, flags);
829}
830
831/**
832 * fsldma_desc_status - Check the status of a descriptor
833 * @chan: Freescale DMA channel
834 * @desc: DMA SW descriptor
835 *
836 * This function will return the status of the given descriptor
837 */
838static enum dma_status fsldma_desc_status(struct fsldma_chan *chan,
839 struct fsl_desc_sw *desc)
840{
841 return dma_async_is_complete(desc->async_tx.cookie,
842 chan->completed_cookie,
843 chan->common.cookie);
Zhang Wei173acc72008-03-01 07:42:48 -0700844}
845
846/**
847 * fsl_chan_ld_cleanup - Clean up link descriptors
Ira Snydera1c03312010-01-06 13:34:05 +0000848 * @chan : Freescale DMA channel
Zhang Wei173acc72008-03-01 07:42:48 -0700849 *
850 * This function clean up the ld_queue of DMA channel.
Zhang Wei173acc72008-03-01 07:42:48 -0700851 */
Ira Snydera1c03312010-01-06 13:34:05 +0000852static void fsl_chan_ld_cleanup(struct fsldma_chan *chan)
Zhang Wei173acc72008-03-01 07:42:48 -0700853{
854 struct fsl_desc_sw *desc, *_desc;
855 unsigned long flags;
856
Ira Snydera1c03312010-01-06 13:34:05 +0000857 spin_lock_irqsave(&chan->desc_lock, flags);
Zhang Wei173acc72008-03-01 07:42:48 -0700858
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000859 dev_dbg(chan->dev, "chan completed_cookie = %d\n", chan->completed_cookie);
860 list_for_each_entry_safe(desc, _desc, &chan->ld_running, node) {
Zhang Wei173acc72008-03-01 07:42:48 -0700861 dma_async_tx_callback callback;
862 void *callback_param;
863
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000864 if (fsldma_desc_status(chan, desc) == DMA_IN_PROGRESS)
Zhang Wei173acc72008-03-01 07:42:48 -0700865 break;
866
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000867 /* Remove from the list of running transactions */
Zhang Wei173acc72008-03-01 07:42:48 -0700868 list_del(&desc->node);
869
Zhang Wei173acc72008-03-01 07:42:48 -0700870 /* Run the link descriptor callback function */
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000871 callback = desc->async_tx.callback;
872 callback_param = desc->async_tx.callback_param;
Zhang Wei173acc72008-03-01 07:42:48 -0700873 if (callback) {
Ira Snydera1c03312010-01-06 13:34:05 +0000874 spin_unlock_irqrestore(&chan->desc_lock, flags);
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000875 dev_dbg(chan->dev, "LD %p callback\n", desc);
Zhang Wei173acc72008-03-01 07:42:48 -0700876 callback(callback_param);
Ira Snydera1c03312010-01-06 13:34:05 +0000877 spin_lock_irqsave(&chan->desc_lock, flags);
Zhang Wei173acc72008-03-01 07:42:48 -0700878 }
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000879
880 /* Run any dependencies, then free the descriptor */
881 dma_run_dependencies(&desc->async_tx);
882 dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys);
Zhang Wei173acc72008-03-01 07:42:48 -0700883 }
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000884
Ira Snydera1c03312010-01-06 13:34:05 +0000885 spin_unlock_irqrestore(&chan->desc_lock, flags);
Zhang Wei173acc72008-03-01 07:42:48 -0700886}
887
888/**
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000889 * fsl_chan_xfer_ld_queue - transfer any pending transactions
Ira Snydera1c03312010-01-06 13:34:05 +0000890 * @chan : Freescale DMA channel
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000891 *
892 * This will make sure that any pending transactions will be run.
893 * If the DMA controller is idle, it will be started. Otherwise,
894 * the DMA controller's interrupt handler will start any pending
895 * transactions when it becomes idle.
Zhang Wei173acc72008-03-01 07:42:48 -0700896 */
Ira Snydera1c03312010-01-06 13:34:05 +0000897static void fsl_chan_xfer_ld_queue(struct fsldma_chan *chan)
Zhang Wei173acc72008-03-01 07:42:48 -0700898{
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000899 struct fsl_desc_sw *desc;
Zhang Wei173acc72008-03-01 07:42:48 -0700900 unsigned long flags;
901
Ira Snydera1c03312010-01-06 13:34:05 +0000902 spin_lock_irqsave(&chan->desc_lock, flags);
Ira Snyder138ef012009-05-19 15:42:13 -0700903
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000904 /*
905 * If the list of pending descriptors is empty, then we
906 * don't need to do any work at all
907 */
908 if (list_empty(&chan->ld_pending)) {
909 dev_dbg(chan->dev, "no pending LDs\n");
Ira Snyder138ef012009-05-19 15:42:13 -0700910 goto out_unlock;
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000911 }
Zhang Wei173acc72008-03-01 07:42:48 -0700912
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000913 /*
914 * The DMA controller is not idle, which means the interrupt
915 * handler will start any queued transactions when it runs
916 * at the end of the current transaction
917 */
918 if (!dma_is_idle(chan)) {
919 dev_dbg(chan->dev, "DMA controller still busy\n");
920 goto out_unlock;
921 }
922
923 /*
924 * TODO:
925 * make sure the dma_halt() function really un-wedges the
926 * controller as much as possible
927 */
Ira Snydera1c03312010-01-06 13:34:05 +0000928 dma_halt(chan);
Zhang Wei173acc72008-03-01 07:42:48 -0700929
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000930 /*
931 * If there are some link descriptors which have not been
932 * transferred, we need to start the controller
Zhang Wei173acc72008-03-01 07:42:48 -0700933 */
Zhang Wei173acc72008-03-01 07:42:48 -0700934
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000935 /*
936 * Move all elements from the queue of pending transactions
937 * onto the list of running transactions
938 */
939 desc = list_first_entry(&chan->ld_pending, struct fsl_desc_sw, node);
940 list_splice_tail_init(&chan->ld_pending, &chan->ld_running);
Zhang Wei173acc72008-03-01 07:42:48 -0700941
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000942 /*
943 * Program the descriptor's address into the DMA controller,
944 * then start the DMA transaction
945 */
946 set_cdar(chan, desc->async_tx.phys);
947 dma_start(chan);
Ira Snyder138ef012009-05-19 15:42:13 -0700948
949out_unlock:
Ira Snydera1c03312010-01-06 13:34:05 +0000950 spin_unlock_irqrestore(&chan->desc_lock, flags);
Zhang Wei173acc72008-03-01 07:42:48 -0700951}
952
953/**
954 * fsl_dma_memcpy_issue_pending - Issue the DMA start command
Ira Snydera1c03312010-01-06 13:34:05 +0000955 * @chan : Freescale DMA channel
Zhang Wei173acc72008-03-01 07:42:48 -0700956 */
Ira Snydera1c03312010-01-06 13:34:05 +0000957static void fsl_dma_memcpy_issue_pending(struct dma_chan *dchan)
Zhang Wei173acc72008-03-01 07:42:48 -0700958{
Ira Snydera1c03312010-01-06 13:34:05 +0000959 struct fsldma_chan *chan = to_fsl_chan(dchan);
Ira Snydera1c03312010-01-06 13:34:05 +0000960 fsl_chan_xfer_ld_queue(chan);
Zhang Wei173acc72008-03-01 07:42:48 -0700961}
962
Zhang Wei173acc72008-03-01 07:42:48 -0700963/**
964 * fsl_dma_is_complete - Determine the DMA status
Ira Snydera1c03312010-01-06 13:34:05 +0000965 * @chan : Freescale DMA channel
Zhang Wei173acc72008-03-01 07:42:48 -0700966 */
Ira Snydera1c03312010-01-06 13:34:05 +0000967static enum dma_status fsl_dma_is_complete(struct dma_chan *dchan,
Zhang Wei173acc72008-03-01 07:42:48 -0700968 dma_cookie_t cookie,
969 dma_cookie_t *done,
970 dma_cookie_t *used)
971{
Ira Snydera1c03312010-01-06 13:34:05 +0000972 struct fsldma_chan *chan = to_fsl_chan(dchan);
Zhang Wei173acc72008-03-01 07:42:48 -0700973 dma_cookie_t last_used;
974 dma_cookie_t last_complete;
975
Ira Snydera1c03312010-01-06 13:34:05 +0000976 fsl_chan_ld_cleanup(chan);
Zhang Wei173acc72008-03-01 07:42:48 -0700977
Ira Snydera1c03312010-01-06 13:34:05 +0000978 last_used = dchan->cookie;
979 last_complete = chan->completed_cookie;
Zhang Wei173acc72008-03-01 07:42:48 -0700980
981 if (done)
982 *done = last_complete;
983
984 if (used)
985 *used = last_used;
986
987 return dma_async_is_complete(cookie, last_complete, last_used);
988}
989
Ira Snyderd3f620b2010-01-06 13:34:04 +0000990/*----------------------------------------------------------------------------*/
991/* Interrupt Handling */
992/*----------------------------------------------------------------------------*/
993
Ira Snydere7a29152010-01-06 13:34:03 +0000994static irqreturn_t fsldma_chan_irq(int irq, void *data)
Zhang Wei173acc72008-03-01 07:42:48 -0700995{
Ira Snydera1c03312010-01-06 13:34:05 +0000996 struct fsldma_chan *chan = data;
Zhang Wei1c629792008-04-17 20:17:25 -0700997 int update_cookie = 0;
998 int xfer_ld_q = 0;
Ira Snydera1c03312010-01-06 13:34:05 +0000999 u32 stat;
Zhang Wei173acc72008-03-01 07:42:48 -07001000
Ira Snyder9c3a50b2010-01-06 13:34:06 +00001001 /* save and clear the status register */
Ira Snydera1c03312010-01-06 13:34:05 +00001002 stat = get_sr(chan);
Ira Snyder9c3a50b2010-01-06 13:34:06 +00001003 set_sr(chan, stat);
1004 dev_dbg(chan->dev, "irq: channel %d, stat = 0x%x\n", chan->id, stat);
Zhang Wei173acc72008-03-01 07:42:48 -07001005
1006 stat &= ~(FSL_DMA_SR_CB | FSL_DMA_SR_CH);
1007 if (!stat)
1008 return IRQ_NONE;
1009
1010 if (stat & FSL_DMA_SR_TE)
Ira Snydera1c03312010-01-06 13:34:05 +00001011 dev_err(chan->dev, "Transfer Error!\n");
Zhang Wei173acc72008-03-01 07:42:48 -07001012
Ira Snyder9c3a50b2010-01-06 13:34:06 +00001013 /*
1014 * Programming Error
Zhang Weif79abb62008-03-18 18:45:00 -07001015 * The DMA_INTERRUPT async_tx is a NULL transfer, which will
1016 * triger a PE interrupt.
1017 */
1018 if (stat & FSL_DMA_SR_PE) {
Ira Snyder9c3a50b2010-01-06 13:34:06 +00001019 dev_dbg(chan->dev, "irq: Programming Error INT\n");
Ira Snydera1c03312010-01-06 13:34:05 +00001020 if (get_bcr(chan) == 0) {
Zhang Weif79abb62008-03-18 18:45:00 -07001021 /* BCR register is 0, this is a DMA_INTERRUPT async_tx.
1022 * Now, update the completed cookie, and continue the
1023 * next uncompleted transfer.
1024 */
Zhang Wei1c629792008-04-17 20:17:25 -07001025 update_cookie = 1;
1026 xfer_ld_q = 1;
Zhang Weif79abb62008-03-18 18:45:00 -07001027 }
1028 stat &= ~FSL_DMA_SR_PE;
1029 }
1030
Ira Snyder9c3a50b2010-01-06 13:34:06 +00001031 /*
1032 * If the link descriptor segment transfer finishes,
Zhang Wei173acc72008-03-01 07:42:48 -07001033 * we will recycle the used descriptor.
1034 */
1035 if (stat & FSL_DMA_SR_EOSI) {
Ira Snyder9c3a50b2010-01-06 13:34:06 +00001036 dev_dbg(chan->dev, "irq: End-of-segments INT\n");
1037 dev_dbg(chan->dev, "irq: clndar 0x%llx, nlndar 0x%llx\n",
Ira Snydera1c03312010-01-06 13:34:05 +00001038 (unsigned long long)get_cdar(chan),
1039 (unsigned long long)get_ndar(chan));
Zhang Wei173acc72008-03-01 07:42:48 -07001040 stat &= ~FSL_DMA_SR_EOSI;
Zhang Wei1c629792008-04-17 20:17:25 -07001041 update_cookie = 1;
1042 }
1043
Ira Snyder9c3a50b2010-01-06 13:34:06 +00001044 /*
1045 * For MPC8349, EOCDI event need to update cookie
Zhang Wei1c629792008-04-17 20:17:25 -07001046 * and start the next transfer if it exist.
1047 */
1048 if (stat & FSL_DMA_SR_EOCDI) {
Ira Snyder9c3a50b2010-01-06 13:34:06 +00001049 dev_dbg(chan->dev, "irq: End-of-Chain link INT\n");
Zhang Wei1c629792008-04-17 20:17:25 -07001050 stat &= ~FSL_DMA_SR_EOCDI;
1051 update_cookie = 1;
1052 xfer_ld_q = 1;
Zhang Wei173acc72008-03-01 07:42:48 -07001053 }
1054
Ira Snyder9c3a50b2010-01-06 13:34:06 +00001055 /*
1056 * If it current transfer is the end-of-transfer,
Zhang Wei173acc72008-03-01 07:42:48 -07001057 * we should clear the Channel Start bit for
1058 * prepare next transfer.
1059 */
Zhang Wei1c629792008-04-17 20:17:25 -07001060 if (stat & FSL_DMA_SR_EOLNI) {
Ira Snyder9c3a50b2010-01-06 13:34:06 +00001061 dev_dbg(chan->dev, "irq: End-of-link INT\n");
Zhang Wei173acc72008-03-01 07:42:48 -07001062 stat &= ~FSL_DMA_SR_EOLNI;
Zhang Wei1c629792008-04-17 20:17:25 -07001063 xfer_ld_q = 1;
Zhang Wei173acc72008-03-01 07:42:48 -07001064 }
1065
Zhang Wei1c629792008-04-17 20:17:25 -07001066 if (update_cookie)
Ira Snydera1c03312010-01-06 13:34:05 +00001067 fsl_dma_update_completed_cookie(chan);
Zhang Wei1c629792008-04-17 20:17:25 -07001068 if (xfer_ld_q)
Ira Snydera1c03312010-01-06 13:34:05 +00001069 fsl_chan_xfer_ld_queue(chan);
Zhang Wei173acc72008-03-01 07:42:48 -07001070 if (stat)
Ira Snyder9c3a50b2010-01-06 13:34:06 +00001071 dev_dbg(chan->dev, "irq: unhandled sr 0x%02x\n", stat);
Zhang Wei173acc72008-03-01 07:42:48 -07001072
Ira Snyder9c3a50b2010-01-06 13:34:06 +00001073 dev_dbg(chan->dev, "irq: Exit\n");
Ira Snydera1c03312010-01-06 13:34:05 +00001074 tasklet_schedule(&chan->tasklet);
Zhang Wei173acc72008-03-01 07:42:48 -07001075 return IRQ_HANDLED;
1076}
1077
Zhang Wei173acc72008-03-01 07:42:48 -07001078static void dma_do_tasklet(unsigned long data)
1079{
Ira Snydera1c03312010-01-06 13:34:05 +00001080 struct fsldma_chan *chan = (struct fsldma_chan *)data;
1081 fsl_chan_ld_cleanup(chan);
Zhang Wei173acc72008-03-01 07:42:48 -07001082}
1083
Ira Snyderd3f620b2010-01-06 13:34:04 +00001084static irqreturn_t fsldma_ctrl_irq(int irq, void *data)
1085{
1086 struct fsldma_device *fdev = data;
1087 struct fsldma_chan *chan;
1088 unsigned int handled = 0;
1089 u32 gsr, mask;
1090 int i;
1091
1092 gsr = (fdev->feature & FSL_DMA_BIG_ENDIAN) ? in_be32(fdev->regs)
1093 : in_le32(fdev->regs);
1094 mask = 0xff000000;
1095 dev_dbg(fdev->dev, "IRQ: gsr 0x%.8x\n", gsr);
1096
1097 for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
1098 chan = fdev->chan[i];
1099 if (!chan)
1100 continue;
1101
1102 if (gsr & mask) {
1103 dev_dbg(fdev->dev, "IRQ: chan %d\n", chan->id);
1104 fsldma_chan_irq(irq, chan);
1105 handled++;
1106 }
1107
1108 gsr &= ~mask;
1109 mask >>= 8;
1110 }
1111
1112 return IRQ_RETVAL(handled);
1113}
1114
1115static void fsldma_free_irqs(struct fsldma_device *fdev)
1116{
1117 struct fsldma_chan *chan;
1118 int i;
1119
1120 if (fdev->irq != NO_IRQ) {
1121 dev_dbg(fdev->dev, "free per-controller IRQ\n");
1122 free_irq(fdev->irq, fdev);
1123 return;
1124 }
1125
1126 for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
1127 chan = fdev->chan[i];
1128 if (chan && chan->irq != NO_IRQ) {
1129 dev_dbg(fdev->dev, "free channel %d IRQ\n", chan->id);
1130 free_irq(chan->irq, chan);
1131 }
1132 }
1133}
1134
1135static int fsldma_request_irqs(struct fsldma_device *fdev)
1136{
1137 struct fsldma_chan *chan;
1138 int ret;
1139 int i;
1140
1141 /* if we have a per-controller IRQ, use that */
1142 if (fdev->irq != NO_IRQ) {
1143 dev_dbg(fdev->dev, "request per-controller IRQ\n");
1144 ret = request_irq(fdev->irq, fsldma_ctrl_irq, IRQF_SHARED,
1145 "fsldma-controller", fdev);
1146 return ret;
1147 }
1148
1149 /* no per-controller IRQ, use the per-channel IRQs */
1150 for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
1151 chan = fdev->chan[i];
1152 if (!chan)
1153 continue;
1154
1155 if (chan->irq == NO_IRQ) {
1156 dev_err(fdev->dev, "no interrupts property defined for "
1157 "DMA channel %d. Please fix your "
1158 "device tree\n", chan->id);
1159 ret = -ENODEV;
1160 goto out_unwind;
1161 }
1162
1163 dev_dbg(fdev->dev, "request channel %d IRQ\n", chan->id);
1164 ret = request_irq(chan->irq, fsldma_chan_irq, IRQF_SHARED,
1165 "fsldma-chan", chan);
1166 if (ret) {
1167 dev_err(fdev->dev, "unable to request IRQ for DMA "
1168 "channel %d\n", chan->id);
1169 goto out_unwind;
1170 }
1171 }
1172
1173 return 0;
1174
1175out_unwind:
1176 for (/* none */; i >= 0; i--) {
1177 chan = fdev->chan[i];
1178 if (!chan)
1179 continue;
1180
1181 if (chan->irq == NO_IRQ)
1182 continue;
1183
1184 free_irq(chan->irq, chan);
1185 }
1186
1187 return ret;
1188}
1189
Ira Snydera4f56d42010-01-06 13:34:01 +00001190/*----------------------------------------------------------------------------*/
1191/* OpenFirmware Subsystem */
1192/*----------------------------------------------------------------------------*/
1193
1194static int __devinit fsl_dma_chan_probe(struct fsldma_device *fdev,
Timur Tabi77cd62e2008-09-26 17:00:11 -07001195 struct device_node *node, u32 feature, const char *compatible)
Zhang Wei173acc72008-03-01 07:42:48 -07001196{
Ira Snydera1c03312010-01-06 13:34:05 +00001197 struct fsldma_chan *chan;
Ira Snyder4ce0e952010-01-06 13:34:00 +00001198 struct resource res;
Zhang Wei173acc72008-03-01 07:42:48 -07001199 int err;
1200
Zhang Wei173acc72008-03-01 07:42:48 -07001201 /* alloc channel */
Ira Snydera1c03312010-01-06 13:34:05 +00001202 chan = kzalloc(sizeof(*chan), GFP_KERNEL);
1203 if (!chan) {
Ira Snydere7a29152010-01-06 13:34:03 +00001204 dev_err(fdev->dev, "no free memory for DMA channels!\n");
1205 err = -ENOMEM;
1206 goto out_return;
Zhang Wei173acc72008-03-01 07:42:48 -07001207 }
1208
Ira Snydere7a29152010-01-06 13:34:03 +00001209 /* ioremap registers for use */
Ira Snydera1c03312010-01-06 13:34:05 +00001210 chan->regs = of_iomap(node, 0);
1211 if (!chan->regs) {
Ira Snydere7a29152010-01-06 13:34:03 +00001212 dev_err(fdev->dev, "unable to ioremap registers\n");
1213 err = -ENOMEM;
Ira Snydera1c03312010-01-06 13:34:05 +00001214 goto out_free_chan;
Ira Snydere7a29152010-01-06 13:34:03 +00001215 }
1216
Ira Snyder4ce0e952010-01-06 13:34:00 +00001217 err = of_address_to_resource(node, 0, &res);
Zhang Wei173acc72008-03-01 07:42:48 -07001218 if (err) {
Ira Snydere7a29152010-01-06 13:34:03 +00001219 dev_err(fdev->dev, "unable to find 'reg' property\n");
1220 goto out_iounmap_regs;
Zhang Wei173acc72008-03-01 07:42:48 -07001221 }
1222
Ira Snydera1c03312010-01-06 13:34:05 +00001223 chan->feature = feature;
Zhang Wei173acc72008-03-01 07:42:48 -07001224 if (!fdev->feature)
Ira Snydera1c03312010-01-06 13:34:05 +00001225 fdev->feature = chan->feature;
Zhang Wei173acc72008-03-01 07:42:48 -07001226
Ira Snydere7a29152010-01-06 13:34:03 +00001227 /*
1228 * If the DMA device's feature is different than the feature
1229 * of its channels, report the bug
Zhang Wei173acc72008-03-01 07:42:48 -07001230 */
Ira Snydera1c03312010-01-06 13:34:05 +00001231 WARN_ON(fdev->feature != chan->feature);
Zhang Wei173acc72008-03-01 07:42:48 -07001232
Ira Snydera1c03312010-01-06 13:34:05 +00001233 chan->dev = fdev->dev;
1234 chan->id = ((res.start - 0x100) & 0xfff) >> 7;
1235 if (chan->id >= FSL_DMA_MAX_CHANS_PER_DEVICE) {
Ira Snydere7a29152010-01-06 13:34:03 +00001236 dev_err(fdev->dev, "too many channels for device\n");
Zhang Wei173acc72008-03-01 07:42:48 -07001237 err = -EINVAL;
Ira Snydere7a29152010-01-06 13:34:03 +00001238 goto out_iounmap_regs;
Zhang Wei173acc72008-03-01 07:42:48 -07001239 }
Zhang Wei173acc72008-03-01 07:42:48 -07001240
Ira Snydera1c03312010-01-06 13:34:05 +00001241 fdev->chan[chan->id] = chan;
1242 tasklet_init(&chan->tasklet, dma_do_tasklet, (unsigned long)chan);
Ira Snydere7a29152010-01-06 13:34:03 +00001243
1244 /* Initialize the channel */
Ira Snydera1c03312010-01-06 13:34:05 +00001245 dma_init(chan);
Zhang Wei173acc72008-03-01 07:42:48 -07001246
1247 /* Clear cdar registers */
Ira Snydera1c03312010-01-06 13:34:05 +00001248 set_cdar(chan, 0);
Zhang Wei173acc72008-03-01 07:42:48 -07001249
Ira Snydera1c03312010-01-06 13:34:05 +00001250 switch (chan->feature & FSL_DMA_IP_MASK) {
Zhang Wei173acc72008-03-01 07:42:48 -07001251 case FSL_DMA_IP_85XX:
Ira Snydera1c03312010-01-06 13:34:05 +00001252 chan->toggle_ext_pause = fsl_chan_toggle_ext_pause;
Zhang Wei173acc72008-03-01 07:42:48 -07001253 case FSL_DMA_IP_83XX:
Ira Snydera1c03312010-01-06 13:34:05 +00001254 chan->toggle_ext_start = fsl_chan_toggle_ext_start;
1255 chan->set_src_loop_size = fsl_chan_set_src_loop_size;
1256 chan->set_dst_loop_size = fsl_chan_set_dst_loop_size;
1257 chan->set_request_count = fsl_chan_set_request_count;
Zhang Wei173acc72008-03-01 07:42:48 -07001258 }
1259
Ira Snydera1c03312010-01-06 13:34:05 +00001260 spin_lock_init(&chan->desc_lock);
Ira Snyder9c3a50b2010-01-06 13:34:06 +00001261 INIT_LIST_HEAD(&chan->ld_pending);
1262 INIT_LIST_HEAD(&chan->ld_running);
Zhang Wei173acc72008-03-01 07:42:48 -07001263
Ira Snydera1c03312010-01-06 13:34:05 +00001264 chan->common.device = &fdev->common;
Zhang Wei173acc72008-03-01 07:42:48 -07001265
Ira Snyderd3f620b2010-01-06 13:34:04 +00001266 /* find the IRQ line, if it exists in the device tree */
Ira Snydera1c03312010-01-06 13:34:05 +00001267 chan->irq = irq_of_parse_and_map(node, 0);
Ira Snyderd3f620b2010-01-06 13:34:04 +00001268
Zhang Wei173acc72008-03-01 07:42:48 -07001269 /* Add the channel to DMA device channel list */
Ira Snydera1c03312010-01-06 13:34:05 +00001270 list_add_tail(&chan->common.device_node, &fdev->common.channels);
Zhang Wei173acc72008-03-01 07:42:48 -07001271 fdev->common.chancnt++;
1272
Ira Snydera1c03312010-01-06 13:34:05 +00001273 dev_info(fdev->dev, "#%d (%s), irq %d\n", chan->id, compatible,
1274 chan->irq != NO_IRQ ? chan->irq : fdev->irq);
Zhang Wei173acc72008-03-01 07:42:48 -07001275
1276 return 0;
Li Yang51ee87f2008-05-29 23:25:45 -07001277
Ira Snydere7a29152010-01-06 13:34:03 +00001278out_iounmap_regs:
Ira Snydera1c03312010-01-06 13:34:05 +00001279 iounmap(chan->regs);
1280out_free_chan:
1281 kfree(chan);
Ira Snydere7a29152010-01-06 13:34:03 +00001282out_return:
Zhang Wei173acc72008-03-01 07:42:48 -07001283 return err;
1284}
1285
Ira Snydera1c03312010-01-06 13:34:05 +00001286static void fsl_dma_chan_remove(struct fsldma_chan *chan)
Zhang Wei173acc72008-03-01 07:42:48 -07001287{
Ira Snydera1c03312010-01-06 13:34:05 +00001288 irq_dispose_mapping(chan->irq);
1289 list_del(&chan->common.device_node);
1290 iounmap(chan->regs);
1291 kfree(chan);
Zhang Wei173acc72008-03-01 07:42:48 -07001292}
1293
Ira Snydere7a29152010-01-06 13:34:03 +00001294static int __devinit fsldma_of_probe(struct of_device *op,
Zhang Wei173acc72008-03-01 07:42:48 -07001295 const struct of_device_id *match)
1296{
Ira Snydera4f56d42010-01-06 13:34:01 +00001297 struct fsldma_device *fdev;
Timur Tabi77cd62e2008-09-26 17:00:11 -07001298 struct device_node *child;
Ira Snydere7a29152010-01-06 13:34:03 +00001299 int err;
Zhang Wei173acc72008-03-01 07:42:48 -07001300
Ira Snydera4f56d42010-01-06 13:34:01 +00001301 fdev = kzalloc(sizeof(*fdev), GFP_KERNEL);
Zhang Wei173acc72008-03-01 07:42:48 -07001302 if (!fdev) {
Ira Snydere7a29152010-01-06 13:34:03 +00001303 dev_err(&op->dev, "No enough memory for 'priv'\n");
1304 err = -ENOMEM;
1305 goto out_return;
Zhang Wei173acc72008-03-01 07:42:48 -07001306 }
Ira Snydere7a29152010-01-06 13:34:03 +00001307
1308 fdev->dev = &op->dev;
Zhang Wei173acc72008-03-01 07:42:48 -07001309 INIT_LIST_HEAD(&fdev->common.channels);
1310
Ira Snydere7a29152010-01-06 13:34:03 +00001311 /* ioremap the registers for use */
1312 fdev->regs = of_iomap(op->node, 0);
1313 if (!fdev->regs) {
1314 dev_err(&op->dev, "unable to ioremap registers\n");
1315 err = -ENOMEM;
1316 goto out_free_fdev;
Zhang Wei173acc72008-03-01 07:42:48 -07001317 }
1318
Ira Snyderd3f620b2010-01-06 13:34:04 +00001319 /* map the channel IRQ if it exists, but don't hookup the handler yet */
1320 fdev->irq = irq_of_parse_and_map(op->node, 0);
1321
Zhang Wei173acc72008-03-01 07:42:48 -07001322 dma_cap_set(DMA_MEMCPY, fdev->common.cap_mask);
1323 dma_cap_set(DMA_INTERRUPT, fdev->common.cap_mask);
Ira Snyderbbea0b62009-09-08 17:53:04 -07001324 dma_cap_set(DMA_SLAVE, fdev->common.cap_mask);
Zhang Wei173acc72008-03-01 07:42:48 -07001325 fdev->common.device_alloc_chan_resources = fsl_dma_alloc_chan_resources;
1326 fdev->common.device_free_chan_resources = fsl_dma_free_chan_resources;
Zhang Wei2187c262008-03-13 17:45:28 -07001327 fdev->common.device_prep_dma_interrupt = fsl_dma_prep_interrupt;
Zhang Wei173acc72008-03-01 07:42:48 -07001328 fdev->common.device_prep_dma_memcpy = fsl_dma_prep_memcpy;
1329 fdev->common.device_is_tx_complete = fsl_dma_is_complete;
1330 fdev->common.device_issue_pending = fsl_dma_memcpy_issue_pending;
Ira Snyderbbea0b62009-09-08 17:53:04 -07001331 fdev->common.device_prep_slave_sg = fsl_dma_prep_slave_sg;
1332 fdev->common.device_terminate_all = fsl_dma_device_terminate_all;
Ira Snydere7a29152010-01-06 13:34:03 +00001333 fdev->common.dev = &op->dev;
Zhang Wei173acc72008-03-01 07:42:48 -07001334
Ira Snydere7a29152010-01-06 13:34:03 +00001335 dev_set_drvdata(&op->dev, fdev);
Timur Tabi77cd62e2008-09-26 17:00:11 -07001336
Ira Snydere7a29152010-01-06 13:34:03 +00001337 /*
1338 * We cannot use of_platform_bus_probe() because there is no
1339 * of_platform_bus_remove(). Instead, we manually instantiate every DMA
Timur Tabi77cd62e2008-09-26 17:00:11 -07001340 * channel object.
1341 */
Ira Snydere7a29152010-01-06 13:34:03 +00001342 for_each_child_of_node(op->node, child) {
1343 if (of_device_is_compatible(child, "fsl,eloplus-dma-channel")) {
Timur Tabi77cd62e2008-09-26 17:00:11 -07001344 fsl_dma_chan_probe(fdev, child,
1345 FSL_DMA_IP_85XX | FSL_DMA_BIG_ENDIAN,
1346 "fsl,eloplus-dma-channel");
Ira Snydere7a29152010-01-06 13:34:03 +00001347 }
1348
1349 if (of_device_is_compatible(child, "fsl,elo-dma-channel")) {
Timur Tabi77cd62e2008-09-26 17:00:11 -07001350 fsl_dma_chan_probe(fdev, child,
1351 FSL_DMA_IP_83XX | FSL_DMA_LITTLE_ENDIAN,
1352 "fsl,elo-dma-channel");
Ira Snydere7a29152010-01-06 13:34:03 +00001353 }
Timur Tabi77cd62e2008-09-26 17:00:11 -07001354 }
Zhang Wei173acc72008-03-01 07:42:48 -07001355
Ira Snyderd3f620b2010-01-06 13:34:04 +00001356 /*
1357 * Hookup the IRQ handler(s)
1358 *
1359 * If we have a per-controller interrupt, we prefer that to the
1360 * per-channel interrupts to reduce the number of shared interrupt
1361 * handlers on the same IRQ line
1362 */
1363 err = fsldma_request_irqs(fdev);
1364 if (err) {
1365 dev_err(fdev->dev, "unable to request IRQs\n");
1366 goto out_free_fdev;
1367 }
1368
Zhang Wei173acc72008-03-01 07:42:48 -07001369 dma_async_device_register(&fdev->common);
1370 return 0;
1371
Ira Snydere7a29152010-01-06 13:34:03 +00001372out_free_fdev:
Ira Snyderd3f620b2010-01-06 13:34:04 +00001373 irq_dispose_mapping(fdev->irq);
Zhang Wei173acc72008-03-01 07:42:48 -07001374 kfree(fdev);
Ira Snydere7a29152010-01-06 13:34:03 +00001375out_return:
Zhang Wei173acc72008-03-01 07:42:48 -07001376 return err;
1377}
1378
Ira Snydere7a29152010-01-06 13:34:03 +00001379static int fsldma_of_remove(struct of_device *op)
Timur Tabi77cd62e2008-09-26 17:00:11 -07001380{
Ira Snydera4f56d42010-01-06 13:34:01 +00001381 struct fsldma_device *fdev;
Timur Tabi77cd62e2008-09-26 17:00:11 -07001382 unsigned int i;
1383
Ira Snydere7a29152010-01-06 13:34:03 +00001384 fdev = dev_get_drvdata(&op->dev);
Timur Tabi77cd62e2008-09-26 17:00:11 -07001385 dma_async_device_unregister(&fdev->common);
1386
Ira Snyderd3f620b2010-01-06 13:34:04 +00001387 fsldma_free_irqs(fdev);
1388
Ira Snydere7a29152010-01-06 13:34:03 +00001389 for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
Timur Tabi77cd62e2008-09-26 17:00:11 -07001390 if (fdev->chan[i])
1391 fsl_dma_chan_remove(fdev->chan[i]);
Ira Snydere7a29152010-01-06 13:34:03 +00001392 }
Timur Tabi77cd62e2008-09-26 17:00:11 -07001393
Ira Snydere7a29152010-01-06 13:34:03 +00001394 iounmap(fdev->regs);
1395 dev_set_drvdata(&op->dev, NULL);
Timur Tabi77cd62e2008-09-26 17:00:11 -07001396 kfree(fdev);
Timur Tabi77cd62e2008-09-26 17:00:11 -07001397
1398 return 0;
1399}
1400
Márton Németh4b1cf1f2010-02-02 23:41:06 -07001401static const struct of_device_id fsldma_of_ids[] = {
Kumar Gala049c9d42008-03-31 11:13:21 -05001402 { .compatible = "fsl,eloplus-dma", },
1403 { .compatible = "fsl,elo-dma", },
Zhang Wei173acc72008-03-01 07:42:48 -07001404 {}
1405};
1406
Ira Snydera4f56d42010-01-06 13:34:01 +00001407static struct of_platform_driver fsldma_of_driver = {
1408 .name = "fsl-elo-dma",
1409 .match_table = fsldma_of_ids,
1410 .probe = fsldma_of_probe,
1411 .remove = fsldma_of_remove,
Zhang Wei173acc72008-03-01 07:42:48 -07001412};
1413
Ira Snydera4f56d42010-01-06 13:34:01 +00001414/*----------------------------------------------------------------------------*/
1415/* Module Init / Exit */
1416/*----------------------------------------------------------------------------*/
1417
1418static __init int fsldma_init(void)
Zhang Wei173acc72008-03-01 07:42:48 -07001419{
Timur Tabi77cd62e2008-09-26 17:00:11 -07001420 int ret;
1421
1422 pr_info("Freescale Elo / Elo Plus DMA driver\n");
1423
Ira Snydera4f56d42010-01-06 13:34:01 +00001424 ret = of_register_platform_driver(&fsldma_of_driver);
Timur Tabi77cd62e2008-09-26 17:00:11 -07001425 if (ret)
1426 pr_err("fsldma: failed to register platform driver\n");
1427
1428 return ret;
Zhang Wei173acc72008-03-01 07:42:48 -07001429}
1430
Ira Snydera4f56d42010-01-06 13:34:01 +00001431static void __exit fsldma_exit(void)
Timur Tabi77cd62e2008-09-26 17:00:11 -07001432{
Ira Snydera4f56d42010-01-06 13:34:01 +00001433 of_unregister_platform_driver(&fsldma_of_driver);
Timur Tabi77cd62e2008-09-26 17:00:11 -07001434}
1435
Ira Snydera4f56d42010-01-06 13:34:01 +00001436subsys_initcall(fsldma_init);
1437module_exit(fsldma_exit);
Timur Tabi77cd62e2008-09-26 17:00:11 -07001438
1439MODULE_DESCRIPTION("Freescale Elo / Elo Plus DMA driver");
1440MODULE_LICENSE("GPL");