Colin Cross | 73625e3 | 2010-06-23 15:49:17 -0700 | [diff] [blame] | 1 | /* |
| 2 | * arch/arm/mach-tegra/fuse.c |
| 3 | * |
| 4 | * Copyright (C) 2010 Google, Inc. |
Danny Huang | 7495b2e | 2013-03-18 19:17:34 +0800 | [diff] [blame] | 5 | * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. |
Colin Cross | 73625e3 | 2010-06-23 15:49:17 -0700 | [diff] [blame] | 6 | * |
| 7 | * Author: |
| 8 | * Colin Cross <ccross@android.com> |
| 9 | * |
| 10 | * This software is licensed under the terms of the GNU General Public |
| 11 | * License version 2, as published by the Free Software Foundation, and |
| 12 | * may be copied, distributed, and modified under those terms. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | * |
| 19 | */ |
| 20 | |
| 21 | #include <linux/kernel.h> |
| 22 | #include <linux/io.h> |
Linus Torvalds | 3480059 | 2012-03-27 16:41:24 -0700 | [diff] [blame] | 23 | #include <linux/export.h> |
Stephen Warren | 3bd1ae5 | 2013-09-12 16:51:19 -0600 | [diff] [blame] | 24 | #include <linux/random.h> |
Prashant Gaikwad | c7736ed | 2013-01-11 13:16:19 +0530 | [diff] [blame] | 25 | #include <linux/tegra-soc.h> |
Colin Cross | 73625e3 | 2010-06-23 15:49:17 -0700 | [diff] [blame] | 26 | |
Colin Cross | 73625e3 | 2010-06-23 15:49:17 -0700 | [diff] [blame] | 27 | #include "fuse.h" |
Stephen Warren | 2be39c0 | 2012-10-04 14:24:09 -0600 | [diff] [blame] | 28 | #include "iomap.h" |
Olof Johansson | d262f49 | 2011-10-13 00:14:08 -0700 | [diff] [blame] | 29 | #include "apbio.h" |
Colin Cross | 73625e3 | 2010-06-23 15:49:17 -0700 | [diff] [blame] | 30 | |
Stephen Warren | 3bd1ae5 | 2013-09-12 16:51:19 -0600 | [diff] [blame] | 31 | /* Tegra20 only */ |
Colin Cross | 73625e3 | 2010-06-23 15:49:17 -0700 | [diff] [blame] | 32 | #define FUSE_UID_LOW 0x108 |
| 33 | #define FUSE_UID_HIGH 0x10c |
Stephen Warren | 3bd1ae5 | 2013-09-12 16:51:19 -0600 | [diff] [blame] | 34 | |
| 35 | /* Tegra30 and later */ |
| 36 | #define FUSE_VENDOR_CODE 0x200 |
| 37 | #define FUSE_FAB_CODE 0x204 |
| 38 | #define FUSE_LOT_CODE_0 0x208 |
| 39 | #define FUSE_LOT_CODE_1 0x20c |
| 40 | #define FUSE_WAFER_ID 0x210 |
| 41 | #define FUSE_X_COORDINATE 0x214 |
| 42 | #define FUSE_Y_COORDINATE 0x218 |
| 43 | |
Colin Cross | 73625e3 | 2010-06-23 15:49:17 -0700 | [diff] [blame] | 44 | #define FUSE_SKU_INFO 0x110 |
Danny Huang | 1f851a2 | 2012-11-15 15:42:32 +0800 | [diff] [blame] | 45 | |
| 46 | #define TEGRA20_FUSE_SPARE_BIT 0x200 |
Danny Huang | f8ddda7 | 2012-11-15 15:42:34 +0800 | [diff] [blame] | 47 | #define TEGRA30_FUSE_SPARE_BIT 0x244 |
Colin Cross | 73625e3 | 2010-06-23 15:49:17 -0700 | [diff] [blame] | 48 | |
Olof Johansson | 9a1086d | 2011-10-13 00:31:20 -0700 | [diff] [blame] | 49 | int tegra_sku_id; |
| 50 | int tegra_cpu_process_id; |
| 51 | int tegra_core_process_id; |
Peter De Schrijver | 4c4ad66 | 2012-02-10 01:47:42 +0200 | [diff] [blame] | 52 | int tegra_chip_id; |
Danny Huang | f8ddda7 | 2012-11-15 15:42:34 +0800 | [diff] [blame] | 53 | int tegra_cpu_speedo_id; /* only exist in Tegra30 and later */ |
Danny Huang | 25cd5a3 | 2012-11-15 15:42:33 +0800 | [diff] [blame] | 54 | int tegra_soc_speedo_id; |
Olof Johansson | 9a1086d | 2011-10-13 00:31:20 -0700 | [diff] [blame] | 55 | enum tegra_revision tegra_revision; |
| 56 | |
Danny Huang | 1f851a2 | 2012-11-15 15:42:32 +0800 | [diff] [blame] | 57 | static int tegra_fuse_spare_bit; |
Danny Huang | 25cd5a3 | 2012-11-15 15:42:33 +0800 | [diff] [blame] | 58 | static void (*tegra_init_speedo_data)(void); |
Danny Huang | 1f851a2 | 2012-11-15 15:42:32 +0800 | [diff] [blame] | 59 | |
Olof Johansson | dee4718 | 2011-10-17 16:39:24 -0700 | [diff] [blame] | 60 | /* The BCT to use at boot is specified by board straps that can be read |
| 61 | * through a APB misc register and decoded. 2 bits, i.e. 4 possible BCTs. |
| 62 | */ |
| 63 | int tegra_bct_strapping; |
| 64 | |
| 65 | #define STRAP_OPT 0x008 |
| 66 | #define GMI_AD0 (1 << 4) |
| 67 | #define GMI_AD1 (1 << 5) |
| 68 | #define RAM_ID_MASK (GMI_AD0 | GMI_AD1) |
| 69 | #define RAM_CODE_SHIFT 4 |
| 70 | |
Olof Johansson | 9a1086d | 2011-10-13 00:31:20 -0700 | [diff] [blame] | 71 | static const char *tegra_revision_name[TEGRA_REVISION_MAX] = { |
| 72 | [TEGRA_REVISION_UNKNOWN] = "unknown", |
| 73 | [TEGRA_REVISION_A01] = "A01", |
| 74 | [TEGRA_REVISION_A02] = "A02", |
| 75 | [TEGRA_REVISION_A03] = "A03", |
| 76 | [TEGRA_REVISION_A03p] = "A03 prime", |
| 77 | [TEGRA_REVISION_A04] = "A04", |
| 78 | }; |
| 79 | |
Danny Huang | 1f851a2 | 2012-11-15 15:42:32 +0800 | [diff] [blame] | 80 | u32 tegra_fuse_readl(unsigned long offset) |
Colin Cross | 73625e3 | 2010-06-23 15:49:17 -0700 | [diff] [blame] | 81 | { |
Olof Johansson | d262f49 | 2011-10-13 00:14:08 -0700 | [diff] [blame] | 82 | return tegra_apb_readl(TEGRA_FUSE_BASE + offset); |
Colin Cross | 73625e3 | 2010-06-23 15:49:17 -0700 | [diff] [blame] | 83 | } |
| 84 | |
Danny Huang | 1f851a2 | 2012-11-15 15:42:32 +0800 | [diff] [blame] | 85 | bool tegra_spare_fuse(int bit) |
Colin Cross | 73625e3 | 2010-06-23 15:49:17 -0700 | [diff] [blame] | 86 | { |
Danny Huang | 1f851a2 | 2012-11-15 15:42:32 +0800 | [diff] [blame] | 87 | return tegra_fuse_readl(tegra_fuse_spare_bit + bit * 4); |
Olof Johansson | 9a1086d | 2011-10-13 00:31:20 -0700 | [diff] [blame] | 88 | } |
| 89 | |
Peter De Schrijver | 35b1498 | 2012-02-10 01:47:41 +0200 | [diff] [blame] | 90 | static enum tegra_revision tegra_get_revision(u32 id) |
Olof Johansson | 9a1086d | 2011-10-13 00:31:20 -0700 | [diff] [blame] | 91 | { |
Olof Johansson | 9a1086d | 2011-10-13 00:31:20 -0700 | [diff] [blame] | 92 | u32 minor_rev = (id >> 16) & 0xf; |
Olof Johansson | 9a1086d | 2011-10-13 00:31:20 -0700 | [diff] [blame] | 93 | |
| 94 | switch (minor_rev) { |
| 95 | case 1: |
| 96 | return TEGRA_REVISION_A01; |
| 97 | case 2: |
| 98 | return TEGRA_REVISION_A02; |
| 99 | case 3: |
Peter De Schrijver | 35b1498 | 2012-02-10 01:47:41 +0200 | [diff] [blame] | 100 | if (tegra_chip_id == TEGRA20 && |
Danny Huang | 1f851a2 | 2012-11-15 15:42:32 +0800 | [diff] [blame] | 101 | (tegra_spare_fuse(18) || tegra_spare_fuse(19))) |
Olof Johansson | 9a1086d | 2011-10-13 00:31:20 -0700 | [diff] [blame] | 102 | return TEGRA_REVISION_A03p; |
| 103 | else |
| 104 | return TEGRA_REVISION_A03; |
| 105 | case 4: |
| 106 | return TEGRA_REVISION_A04; |
| 107 | default: |
| 108 | return TEGRA_REVISION_UNKNOWN; |
| 109 | } |
Colin Cross | 73625e3 | 2010-06-23 15:49:17 -0700 | [diff] [blame] | 110 | } |
| 111 | |
Danny Huang | 25cd5a3 | 2012-11-15 15:42:33 +0800 | [diff] [blame] | 112 | static void tegra_get_process_id(void) |
| 113 | { |
| 114 | u32 reg; |
| 115 | |
| 116 | reg = tegra_fuse_readl(tegra_fuse_spare_bit); |
| 117 | tegra_cpu_process_id = (reg >> 6) & 3; |
| 118 | reg = tegra_fuse_readl(tegra_fuse_spare_bit); |
| 119 | tegra_core_process_id = (reg >> 12) & 3; |
| 120 | } |
| 121 | |
Prashant Gaikwad | c7736ed | 2013-01-11 13:16:19 +0530 | [diff] [blame] | 122 | u32 tegra_read_chipid(void) |
| 123 | { |
| 124 | return readl_relaxed(IO_ADDRESS(TEGRA_APB_MISC_BASE) + 0x804); |
| 125 | } |
| 126 | |
Stephen Warren | 3bd1ae5 | 2013-09-12 16:51:19 -0600 | [diff] [blame] | 127 | static void __init tegra20_fuse_init_randomness(void) |
| 128 | { |
| 129 | u32 randomness[2]; |
| 130 | |
| 131 | randomness[0] = tegra_fuse_readl(FUSE_UID_LOW); |
| 132 | randomness[1] = tegra_fuse_readl(FUSE_UID_HIGH); |
| 133 | |
| 134 | add_device_randomness(randomness, sizeof(randomness)); |
| 135 | } |
| 136 | |
| 137 | /* Applies to Tegra30 or later */ |
| 138 | static void __init tegra30_fuse_init_randomness(void) |
| 139 | { |
| 140 | u32 randomness[7]; |
| 141 | |
| 142 | randomness[0] = tegra_fuse_readl(FUSE_VENDOR_CODE); |
| 143 | randomness[1] = tegra_fuse_readl(FUSE_FAB_CODE); |
| 144 | randomness[2] = tegra_fuse_readl(FUSE_LOT_CODE_0); |
| 145 | randomness[3] = tegra_fuse_readl(FUSE_LOT_CODE_1); |
| 146 | randomness[4] = tegra_fuse_readl(FUSE_WAFER_ID); |
| 147 | randomness[5] = tegra_fuse_readl(FUSE_X_COORDINATE); |
| 148 | randomness[6] = tegra_fuse_readl(FUSE_Y_COORDINATE); |
| 149 | |
| 150 | add_device_randomness(randomness, sizeof(randomness)); |
| 151 | } |
| 152 | |
Stephen Warren | 5875df1 | 2013-09-13 12:18:44 -0600 | [diff] [blame] | 153 | void __init tegra_init_fuse(void) |
Colin Cross | 73625e3 | 2010-06-23 15:49:17 -0700 | [diff] [blame] | 154 | { |
Peter De Schrijver | 35b1498 | 2012-02-10 01:47:41 +0200 | [diff] [blame] | 155 | u32 id; |
Stephen Warren | 3bd1ae5 | 2013-09-12 16:51:19 -0600 | [diff] [blame] | 156 | u32 randomness[5]; |
Peter De Schrijver | 35b1498 | 2012-02-10 01:47:41 +0200 | [diff] [blame] | 157 | |
Laxman Dewangan | f8e798a | 2012-08-10 18:33:02 +0530 | [diff] [blame] | 158 | u32 reg = readl(IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x48)); |
Colin Cross | 73625e3 | 2010-06-23 15:49:17 -0700 | [diff] [blame] | 159 | reg |= 1 << 28; |
Laxman Dewangan | f8e798a | 2012-08-10 18:33:02 +0530 | [diff] [blame] | 160 | writel(reg, IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x48)); |
Colin Cross | 73625e3 | 2010-06-23 15:49:17 -0700 | [diff] [blame] | 161 | |
Olof Johansson | 9a1086d | 2011-10-13 00:31:20 -0700 | [diff] [blame] | 162 | reg = tegra_fuse_readl(FUSE_SKU_INFO); |
Stephen Warren | 3bd1ae5 | 2013-09-12 16:51:19 -0600 | [diff] [blame] | 163 | randomness[0] = reg; |
Olof Johansson | 9a1086d | 2011-10-13 00:31:20 -0700 | [diff] [blame] | 164 | tegra_sku_id = reg & 0xFF; |
| 165 | |
Olof Johansson | dee4718 | 2011-10-17 16:39:24 -0700 | [diff] [blame] | 166 | reg = tegra_apb_readl(TEGRA_APB_MISC_BASE + STRAP_OPT); |
Stephen Warren | 3bd1ae5 | 2013-09-12 16:51:19 -0600 | [diff] [blame] | 167 | randomness[1] = reg; |
Olof Johansson | dee4718 | 2011-10-17 16:39:24 -0700 | [diff] [blame] | 168 | tegra_bct_strapping = (reg & RAM_ID_MASK) >> RAM_CODE_SHIFT; |
| 169 | |
Prashant Gaikwad | c7736ed | 2013-01-11 13:16:19 +0530 | [diff] [blame] | 170 | id = tegra_read_chipid(); |
Stephen Warren | 3bd1ae5 | 2013-09-12 16:51:19 -0600 | [diff] [blame] | 171 | randomness[2] = id; |
Peter De Schrijver | 35b1498 | 2012-02-10 01:47:41 +0200 | [diff] [blame] | 172 | tegra_chip_id = (id >> 8) & 0xff; |
| 173 | |
Danny Huang | 25cd5a3 | 2012-11-15 15:42:33 +0800 | [diff] [blame] | 174 | switch (tegra_chip_id) { |
| 175 | case TEGRA20: |
Danny Huang | f8ddda7 | 2012-11-15 15:42:34 +0800 | [diff] [blame] | 176 | tegra_fuse_spare_bit = TEGRA20_FUSE_SPARE_BIT; |
Danny Huang | 25cd5a3 | 2012-11-15 15:42:33 +0800 | [diff] [blame] | 177 | tegra_init_speedo_data = &tegra20_init_speedo_data; |
| 178 | break; |
Danny Huang | f8ddda7 | 2012-11-15 15:42:34 +0800 | [diff] [blame] | 179 | case TEGRA30: |
| 180 | tegra_fuse_spare_bit = TEGRA30_FUSE_SPARE_BIT; |
| 181 | tegra_init_speedo_data = &tegra30_init_speedo_data; |
| 182 | break; |
Danny Huang | 7495b2e | 2013-03-18 19:17:34 +0800 | [diff] [blame] | 183 | case TEGRA114: |
| 184 | tegra_init_speedo_data = &tegra114_init_speedo_data; |
| 185 | break; |
Danny Huang | 25cd5a3 | 2012-11-15 15:42:33 +0800 | [diff] [blame] | 186 | default: |
Danny Huang | f8ddda7 | 2012-11-15 15:42:34 +0800 | [diff] [blame] | 187 | pr_warn("Tegra: unknown chip id %d\n", tegra_chip_id); |
| 188 | tegra_fuse_spare_bit = TEGRA20_FUSE_SPARE_BIT; |
Danny Huang | 25cd5a3 | 2012-11-15 15:42:33 +0800 | [diff] [blame] | 189 | tegra_init_speedo_data = &tegra_get_process_id; |
| 190 | } |
| 191 | |
Peter De Schrijver | 35b1498 | 2012-02-10 01:47:41 +0200 | [diff] [blame] | 192 | tegra_revision = tegra_get_revision(id); |
Danny Huang | 25cd5a3 | 2012-11-15 15:42:33 +0800 | [diff] [blame] | 193 | tegra_init_speedo_data(); |
Stephen Warren | 3bd1ae5 | 2013-09-12 16:51:19 -0600 | [diff] [blame] | 194 | randomness[3] = (tegra_cpu_process_id << 16) | tegra_core_process_id; |
| 195 | randomness[4] = (tegra_cpu_speedo_id << 16) | tegra_soc_speedo_id; |
| 196 | |
| 197 | add_device_randomness(randomness, sizeof(randomness)); |
| 198 | switch (tegra_chip_id) { |
| 199 | case TEGRA20: |
| 200 | tegra20_fuse_init_randomness(); |
| 201 | case TEGRA30: |
| 202 | case TEGRA114: |
| 203 | default: |
| 204 | tegra30_fuse_init_randomness(); |
| 205 | } |
Olof Johansson | 9a1086d | 2011-10-13 00:31:20 -0700 | [diff] [blame] | 206 | |
| 207 | pr_info("Tegra Revision: %s SKU: %d CPU Process: %d Core Process: %d\n", |
Peter De Schrijver | 35b1498 | 2012-02-10 01:47:41 +0200 | [diff] [blame] | 208 | tegra_revision_name[tegra_revision], |
Olof Johansson | 9a1086d | 2011-10-13 00:31:20 -0700 | [diff] [blame] | 209 | tegra_sku_id, tegra_cpu_process_id, |
| 210 | tegra_core_process_id); |
Colin Cross | 73625e3 | 2010-06-23 15:49:17 -0700 | [diff] [blame] | 211 | } |