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Alan Coxda9bb1d2006-01-18 17:44:13 -08001#
2# EDAC Kconfig
Doug Thompson4577ca52009-04-02 16:58:43 -07003# Copyright (c) 2008 Doug Thompson www.softwarebitmaker.com
Alan Coxda9bb1d2006-01-18 17:44:13 -08004# Licensed and distributed under the GPL
5#
Alan Coxda9bb1d2006-01-18 17:44:13 -08006
Jan Engelhardt751cb5e2007-07-15 23:39:27 -07007menuconfig EDAC
GeunSik Lime24aca62009-06-17 16:28:02 -07008 bool "EDAC (Error Detection And Correction) reporting"
Martin Schwidefskye25df122007-05-10 15:45:57 +02009 depends on HAS_IOMEM
Chris Metcalf5c770752011-03-01 13:01:49 -050010 depends on X86 || PPC || TILE
Alan Coxda9bb1d2006-01-18 17:44:13 -080011 help
12 EDAC is designed to report errors in the core system.
13 These are low-level errors that are reported in the CPU or
Douglas Thompson8cb2a392007-07-19 01:50:12 -070014 supporting chipset or other subsystems:
15 memory errors, cache errors, PCI errors, thermal throttling, etc..
16 If unsure, select 'Y'.
Alan Coxda9bb1d2006-01-18 17:44:13 -080017
Tim Small57c432b2006-03-09 17:33:50 -080018 If this code is reporting problems on your system, please
19 see the EDAC project web pages for more information at:
20
21 <http://bluesmoke.sourceforge.net/>
22
23 and:
24
25 <http://buttersideup.com/edacwiki>
26
27 There is also a mailing list for the EDAC project, which can
28 be found via the sourceforge page.
29
Jan Engelhardt751cb5e2007-07-15 23:39:27 -070030if EDAC
Alan Coxda9bb1d2006-01-18 17:44:13 -080031
32comment "Reporting subsystems"
Alan Coxda9bb1d2006-01-18 17:44:13 -080033
34config EDAC_DEBUG
35 bool "Debugging"
Alan Coxda9bb1d2006-01-18 17:44:13 -080036 help
37 This turns on debugging information for the entire EDAC
38 sub-system. You can insert module with "debug_level=x", current
39 there're four debug levels (x=0,1,2,3 from low to high).
40 Usually you should select 'N'.
41
Borislav Petkov9cdeb402010-09-02 18:33:24 +020042config EDAC_DECODE_MCE
Borislav Petkov0d18b2e2009-10-02 15:31:48 +020043 tristate "Decode MCEs in human-readable form (only on AMD for now)"
44 depends on CPU_SUP_AMD && X86_MCE
45 default y
46 ---help---
47 Enable this option if you want to decode Machine Check Exceptions
Lucas De Marchi25985ed2011-03-30 22:57:33 -030048 occurring on your machine in human-readable form.
Borislav Petkov0d18b2e2009-10-02 15:31:48 +020049
50 You should definitely say Y here in case you want to decode MCEs
51 which occur really early upon boot, before the module infrastructure
52 has been initialized.
53
Borislav Petkov9cdeb402010-09-02 18:33:24 +020054config EDAC_MCE_INJ
55 tristate "Simple MCE injection interface over /sysfs"
56 depends on EDAC_DECODE_MCE
57 default n
58 help
59 This is a simple interface to inject MCEs over /sysfs and test
60 the MCE decoding code in EDAC.
61
62 This is currently AMD-only.
63
Alan Coxda9bb1d2006-01-18 17:44:13 -080064config EDAC_MM_EDAC
65 tristate "Main Memory EDAC (Error Detection And Correction) reporting"
Alan Coxda9bb1d2006-01-18 17:44:13 -080066 help
67 Some systems are able to detect and correct errors in main
68 memory. EDAC can report statistics on memory error
69 detection and correction (EDAC - or commonly referred to ECC
70 errors). EDAC will also try to decode where these errors
71 occurred so that a particular failing memory module can be
72 replaced. If unsure, select 'Y'.
73
Mauro Carvalho Chehab696e4092009-07-23 06:57:45 -030074config EDAC_MCE
Mauro Carvalho Chehab963c5ba2009-07-09 22:04:30 -030075 bool
Mauro Carvalho Chehab696e4092009-07-23 06:57:45 -030076
Doug Thompson7d6034d2009-04-27 20:01:01 +020077config EDAC_AMD64
Borislav Petkov027dbd62010-10-13 22:12:15 +020078 tristate "AMD64 (Opteron, Athlon64) K8, F10h"
79 depends on EDAC_MM_EDAC && AMD_NB && X86_64 && EDAC_DECODE_MCE
Doug Thompson7d6034d2009-04-27 20:01:01 +020080 help
Borislav Petkov027dbd62010-10-13 22:12:15 +020081 Support for error detection and correction of DRAM ECC errors on
82 the AMD64 families of memory controllers (K8 and F10h)
Doug Thompson7d6034d2009-04-27 20:01:01 +020083
84config EDAC_AMD64_ERROR_INJECTION
Borislav Petkov9cdeb402010-09-02 18:33:24 +020085 bool "Sysfs HW Error injection facilities"
Doug Thompson7d6034d2009-04-27 20:01:01 +020086 depends on EDAC_AMD64
87 help
88 Recent Opterons (Family 10h and later) provide for Memory Error
89 Injection into the ECC detection circuits. The amd64_edac module
90 allows the operator/user to inject Uncorrectable and Correctable
91 errors into DRAM.
92
93 When enabled, in each of the respective memory controller directories
94 (/sys/devices/system/edac/mc/mcX), there are 3 input files:
95
96 - inject_section (0..3, 16-byte section of 64-byte cacheline),
97 - inject_word (0..8, 16-bit word of 16-byte section),
98 - inject_ecc_vector (hex ecc vector: select bits of inject word)
99
100 In addition, there are two control files, inject_read and inject_write,
101 which trigger the DRAM ECC Read and Write respectively.
Alan Coxda9bb1d2006-01-18 17:44:13 -0800102
103config EDAC_AMD76X
104 tristate "AMD 76x (760, 762, 768)"
Dave Jones90cbc452006-02-03 03:04:11 -0800105 depends on EDAC_MM_EDAC && PCI && X86_32
Alan Coxda9bb1d2006-01-18 17:44:13 -0800106 help
107 Support for error detection and correction on the AMD 76x
108 series of chipsets used with the Athlon processor.
109
110config EDAC_E7XXX
111 tristate "Intel e7xxx (e7205, e7500, e7501, e7505)"
Dave Peterson39f1d8d2006-03-26 01:38:50 -0800112 depends on EDAC_MM_EDAC && PCI && X86_32
Alan Coxda9bb1d2006-01-18 17:44:13 -0800113 help
114 Support for error detection and correction on the Intel
115 E7205, E7500, E7501 and E7505 server chipsets.
116
117config EDAC_E752X
Andrei Konovalov5135b792008-04-29 01:03:13 -0700118 tristate "Intel e752x (e7520, e7525, e7320) and 3100"
Randy Dunlapda960a62006-03-31 02:30:34 -0800119 depends on EDAC_MM_EDAC && PCI && X86 && HOTPLUG
Alan Coxda9bb1d2006-01-18 17:44:13 -0800120 help
121 Support for error detection and correction on the Intel
122 E7520, E7525, E7320 server chipsets.
123
Tim Small5a2c6752007-07-19 01:49:42 -0700124config EDAC_I82443BXGX
125 tristate "Intel 82443BX/GX (440BX/GX)"
126 depends on EDAC_MM_EDAC && PCI && X86_32
Andrew Morton28f96eea2007-07-19 01:49:45 -0700127 depends on BROKEN
Tim Small5a2c6752007-07-19 01:49:42 -0700128 help
129 Support for error detection and correction on the Intel
130 82443BX/GX memory controllers (440BX/GX chipsets).
131
Alan Coxda9bb1d2006-01-18 17:44:13 -0800132config EDAC_I82875P
133 tristate "Intel 82875p (D82875P, E7210)"
Dave Peterson39f1d8d2006-03-26 01:38:50 -0800134 depends on EDAC_MM_EDAC && PCI && X86_32
Alan Coxda9bb1d2006-01-18 17:44:13 -0800135 help
136 Support for error detection and correction on the Intel
137 DP82785P and E7210 server chipsets.
138
Ranganathan Desikan420390f2007-07-19 01:50:31 -0700139config EDAC_I82975X
140 tristate "Intel 82975x (D82975x)"
141 depends on EDAC_MM_EDAC && PCI && X86
142 help
143 Support for error detection and correction on the Intel
144 DP82975x server chipsets.
145
Jason Uhlenkott535c6a52007-07-19 01:49:48 -0700146config EDAC_I3000
147 tristate "Intel 3000/3010"
Jason Uhlenkottf5c04542008-02-07 00:15:01 -0800148 depends on EDAC_MM_EDAC && PCI && X86
Jason Uhlenkott535c6a52007-07-19 01:49:48 -0700149 help
150 Support for error detection and correction on the Intel
151 3000 and 3010 server chipsets.
152
Jason Uhlenkottdd8ef1d2009-09-23 15:57:27 -0700153config EDAC_I3200
154 tristate "Intel 3200"
155 depends on EDAC_MM_EDAC && PCI && X86 && EXPERIMENTAL
156 help
157 Support for error detection and correction on the Intel
158 3200 and 3210 server chipsets.
159
Hitoshi Mitakedf8bc08c2008-10-29 14:00:50 -0700160config EDAC_X38
161 tristate "Intel X38"
162 depends on EDAC_MM_EDAC && PCI && X86
163 help
164 Support for error detection and correction on the Intel
165 X38 server chipsets.
166
Mauro Carvalho Chehab920c8df2009-01-06 14:43:00 -0800167config EDAC_I5400
168 tristate "Intel 5400 (Seaburg) chipsets"
169 depends on EDAC_MM_EDAC && PCI && X86
170 help
171 Support for error detection and correction the Intel
172 i5400 MCH chipset (Seaburg).
173
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300174config EDAC_I7CORE
175 tristate "Intel i7 Core (Nehalem) processors"
176 depends on EDAC_MM_EDAC && PCI && X86
Mauro Carvalho Chehab696e4092009-07-23 06:57:45 -0300177 select EDAC_MCE
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300178 help
179 Support for error detection and correction the Intel
Mauro Carvalho Chehab696e4092009-07-23 06:57:45 -0300180 i7 Core (Nehalem) Integrated Memory Controller that exists on
181 newer processors like i7 Core, i7 Core Extreme, Xeon 35xx
182 and Xeon 55xx processors.
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300183
Alan Coxda9bb1d2006-01-18 17:44:13 -0800184config EDAC_I82860
185 tristate "Intel 82860"
Dave Peterson39f1d8d2006-03-26 01:38:50 -0800186 depends on EDAC_MM_EDAC && PCI && X86_32
Alan Coxda9bb1d2006-01-18 17:44:13 -0800187 help
188 Support for error detection and correction on the Intel
189 82860 chipset.
190
191config EDAC_R82600
192 tristate "Radisys 82600 embedded chipset"
Dave Peterson39f1d8d2006-03-26 01:38:50 -0800193 depends on EDAC_MM_EDAC && PCI && X86_32
Alan Coxda9bb1d2006-01-18 17:44:13 -0800194 help
195 Support for error detection and correction on the Radisys
196 82600 embedded chipset.
197
Eric Wolleseneb607052007-07-19 01:49:39 -0700198config EDAC_I5000
199 tristate "Intel Greencreek/Blackford chipset"
200 depends on EDAC_MM_EDAC && X86 && PCI
201 help
202 Support for error detection and correction the Intel
203 Greekcreek/Blackford chipsets.
204
Arthur Jones8f421c592008-07-25 01:49:04 -0700205config EDAC_I5100
206 tristate "Intel San Clemente MCH"
207 depends on EDAC_MM_EDAC && X86 && PCI
208 help
209 Support for error detection and correction the Intel
210 San Clemente MCH.
211
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300212config EDAC_I7300
213 tristate "Intel Clarksboro MCH"
214 depends on EDAC_MM_EDAC && X86 && PCI
215 help
216 Support for error detection and correction the Intel
217 Clarksboro MCH (Intel 7300 chipset).
218
Dave Jianga9a753d2008-02-07 00:14:55 -0800219config EDAC_MPC85XX
Ira W. Snyderb4846252009-09-23 15:57:25 -0700220 tristate "Freescale MPC83xx / MPC85xx"
Anton Vorontsov1cd85212010-07-20 13:24:27 -0700221 depends on EDAC_MM_EDAC && FSL_SOC && (PPC_83xx || PPC_85xx)
Dave Jianga9a753d2008-02-07 00:14:55 -0800222 help
223 Support for error detection and correction on the Freescale
Ira W. Snyderb4846252009-09-23 15:57:25 -0700224 MPC8349, MPC8560, MPC8540, MPC8548
Dave Jianga9a753d2008-02-07 00:14:55 -0800225
Dave Jiang4f4aeea2008-02-07 00:14:56 -0800226config EDAC_MV64X60
227 tristate "Marvell MV64x60"
228 depends on EDAC_MM_EDAC && MV64X60
229 help
230 Support for error detection and correction on the Marvell
231 MV64360 and MV64460 chipsets.
232
Egor Martovetsky7d8536f2007-07-19 01:50:24 -0700233config EDAC_PASEMI
234 tristate "PA Semi PWRficient"
235 depends on EDAC_MM_EDAC && PCI
Doug Thompsonddcc3052007-07-26 10:41:16 -0700236 depends on PPC_PASEMI
Egor Martovetsky7d8536f2007-07-19 01:50:24 -0700237 help
238 Support for error detection and correction on PA Semi
239 PWRficient.
240
Benjamin Herrenschmidt48764e42008-02-07 00:14:53 -0800241config EDAC_CELL
242 tristate "Cell Broadband Engine memory controller"
Benjamin Krilldef434c2008-11-27 16:15:44 +0100243 depends on EDAC_MM_EDAC && PPC_CELL_COMMON
Benjamin Herrenschmidt48764e42008-02-07 00:14:53 -0800244 help
245 Support for error detection and correction on the
246 Cell Broadband Engine internal memory controller
247 on platform without a hypervisor
Egor Martovetsky7d8536f2007-07-19 01:50:24 -0700248
Grant Ericksondba7a772009-04-02 16:58:45 -0700249config EDAC_PPC4XX
250 tristate "PPC4xx IBM DDR2 Memory Controller"
251 depends on EDAC_MM_EDAC && 4xx
252 help
253 This enables support for EDAC on the ECC memory used
254 with the IBM DDR2 memory controller found in various
255 PowerPC 4xx embedded processors such as the 405EX[r],
256 440SP, 440SPe, 460EX, 460GT and 460SX.
257
Harry Ciaoe8765582009-04-02 16:58:51 -0700258config EDAC_AMD8131
259 tristate "AMD8131 HyperTransport PCI-X Tunnel"
Harry Ciao715fe7a2009-05-28 14:34:43 -0700260 depends on EDAC_MM_EDAC && PCI && PPC_MAPLE
Harry Ciaoe8765582009-04-02 16:58:51 -0700261 help
262 Support for error detection and correction on the
263 AMD8131 HyperTransport PCI-X Tunnel chip.
Harry Ciao715fe7a2009-05-28 14:34:43 -0700264 Note, add more Kconfig dependency if it's adopted
265 on some machine other than Maple.
Harry Ciaoe8765582009-04-02 16:58:51 -0700266
Harry Ciao58b4ce62009-04-02 16:58:51 -0700267config EDAC_AMD8111
268 tristate "AMD8111 HyperTransport I/O Hub"
Harry Ciao715fe7a2009-05-28 14:34:43 -0700269 depends on EDAC_MM_EDAC && PCI && PPC_MAPLE
Harry Ciao58b4ce62009-04-02 16:58:51 -0700270 help
271 Support for error detection and correction on the
272 AMD8111 HyperTransport I/O Hub chip.
Harry Ciao715fe7a2009-05-28 14:34:43 -0700273 Note, add more Kconfig dependency if it's adopted
274 on some machine other than Maple.
Harry Ciao58b4ce62009-04-02 16:58:51 -0700275
Harry Ciao2a9036a2009-06-17 16:27:58 -0700276config EDAC_CPC925
277 tristate "IBM CPC925 Memory Controller (PPC970FX)"
278 depends on EDAC_MM_EDAC && PPC64
279 help
280 Support for error detection and correction on the
281 IBM CPC925 Bridge and Memory Controller, which is
282 a companion chip to the PowerPC 970 family of
283 processors.
284
Chris Metcalf5c770752011-03-01 13:01:49 -0500285config EDAC_TILE
286 tristate "Tilera Memory Controller"
287 depends on EDAC_MM_EDAC && TILE
288 default y
289 help
290 Support for error detection and correction on the
291 Tilera memory controller.
292
Jan Engelhardt751cb5e2007-07-15 23:39:27 -0700293endif # EDAC