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Wei WANG4c4b8c12013-04-11 10:43:40 +08001/* Driver for Realtek PCI-Express card reader
2 *
3 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2, or (at your option) any
8 * later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, see <http://www.gnu.org/licenses/>.
17 *
18 * Author:
19 * Wei WANG <wei_wang@realsil.com.cn>
20 * No. 128, West Shenhu Road, Suzhou Industry Park, Suzhou, China
21 */
22
23#include <linux/module.h>
24#include <linux/delay.h>
25#include <linux/mfd/rtsx_pci.h>
26
27#include "rtsx_pcr.h"
28
29static u8 rts5249_get_ic_version(struct rtsx_pcr *pcr)
30{
31 u8 val;
32
33 rtsx_pci_read_register(pcr, DUMMY_REG_RESET_0, &val);
34 return val & 0x0F;
35}
36
Wei WANG773ccdf2013-08-20 14:18:51 +080037static void rts5249_fill_driving(struct rtsx_pcr *pcr, u8 voltage)
38{
39 u8 driving_3v3[4][3] = {
40 {0x11, 0x11, 0x11},
41 {0x55, 0x55, 0x5C},
42 {0x99, 0x99, 0x92},
43 {0x99, 0x99, 0x92},
44 };
45 u8 driving_1v8[4][3] = {
46 {0x3C, 0x3C, 0x3C},
47 {0xB3, 0xB3, 0xB3},
48 {0xFE, 0xFE, 0xFE},
49 {0xC4, 0xC4, 0xC4},
50 };
51 u8 (*driving)[3], drive_sel;
52
53 if (voltage == OUTPUT_3V3) {
54 driving = driving_3v3;
55 drive_sel = pcr->sd30_drive_sel_3v3;
56 } else {
57 driving = driving_1v8;
58 drive_sel = pcr->sd30_drive_sel_1v8;
59 }
60
61 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CLK_DRIVE_SEL,
62 0xFF, driving[drive_sel][0]);
63 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CMD_DRIVE_SEL,
64 0xFF, driving[drive_sel][1]);
65 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_DAT_DRIVE_SEL,
66 0xFF, driving[drive_sel][2]);
67}
68
69static void rts5249_fetch_vendor_settings(struct rtsx_pcr *pcr)
70{
71 u32 reg;
72
73 rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG1, &reg);
74 dev_dbg(&(pcr->pci->dev), "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg);
75
76 if (!rtsx_vendor_setting_valid(reg))
77 return;
78
79 pcr->aspm_en = rtsx_reg_to_aspm(reg);
80 pcr->sd30_drive_sel_1v8 = rtsx_reg_to_sd30_drive_sel_1v8(reg);
81 pcr->card_drive_sel &= 0x3F;
82 pcr->card_drive_sel |= rtsx_reg_to_card_drive_sel(reg);
83
84 rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG2, &reg);
85 dev_dbg(&(pcr->pci->dev), "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg);
86 pcr->sd30_drive_sel_3v3 = rtsx_reg_to_sd30_drive_sel_3v3(reg);
87 if (rtsx_reg_check_reverse_socket(reg))
88 pcr->flags |= PCR_REVERSE_SOCKET;
89}
90
Wei WANG5947c162013-08-20 14:18:52 +080091static void rts5249_force_power_down(struct rtsx_pcr *pcr)
92{
93 /* Set relink_time to 0 */
94 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 1, 0xFF, 0);
95 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 2, 0xFF, 0);
96 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 3, 0x01, 0);
97
98 rtsx_pci_write_register(pcr, FPDCTL, 0x03, 0x03);
99}
100
Wei WANG4c4b8c12013-04-11 10:43:40 +0800101static int rts5249_extra_init_hw(struct rtsx_pcr *pcr)
102{
103 rtsx_pci_init_cmd(pcr);
104
105 /* Configure GPIO as output */
106 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, GPIO_CTL, 0x02, 0x02);
Wei WANG71408122013-08-20 14:18:53 +0800107 /* Reset ASPM state to default value */
108 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, ASPM_FORCE_CTL, 0x3F, 0);
Wei WANG4c4b8c12013-04-11 10:43:40 +0800109 /* Switch LDO3318 source from DV33 to card_3v3 */
110 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x00);
111 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x01);
112 /* LED shine disabled, set initial shine cycle period */
113 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, OLT_LED_CTL, 0x0F, 0x02);
Wei WANG773ccdf2013-08-20 14:18:51 +0800114 /* Configure driving */
115 rts5249_fill_driving(pcr, OUTPUT_3V3);
116 if (pcr->flags & PCR_REVERSE_SOCKET)
117 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
118 AUTOLOAD_CFG_BASE + 3, 0xB0, 0xB0);
119 else
120 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
121 AUTOLOAD_CFG_BASE + 3, 0xB0, 0x80);
Wei WANG4c4b8c12013-04-11 10:43:40 +0800122
123 return rtsx_pci_send_cmd(pcr, 100);
124}
125
126static int rts5249_optimize_phy(struct rtsx_pcr *pcr)
127{
128 int err;
129
130 err = rtsx_pci_write_phy_register(pcr, PHY_REG_REV, 0xFE46);
131 if (err < 0)
132 return err;
133
134 msleep(1);
135
136 return rtsx_pci_write_phy_register(pcr, PHY_BPCR, 0x05C0);
137}
138
139static int rts5249_turn_on_led(struct rtsx_pcr *pcr)
140{
141 return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x02);
142}
143
144static int rts5249_turn_off_led(struct rtsx_pcr *pcr)
145{
146 return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x00);
147}
148
149static int rts5249_enable_auto_blink(struct rtsx_pcr *pcr)
150{
151 return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x08);
152}
153
154static int rts5249_disable_auto_blink(struct rtsx_pcr *pcr)
155{
156 return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x00);
157}
158
159static int rts5249_card_power_on(struct rtsx_pcr *pcr, int card)
160{
161 int err;
162
163 rtsx_pci_init_cmd(pcr);
164 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
165 SD_POWER_MASK, SD_VCC_PARTIAL_POWER_ON);
166 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
167 LDO3318_PWR_MASK, 0x02);
168 err = rtsx_pci_send_cmd(pcr, 100);
169 if (err < 0)
170 return err;
171
172 msleep(5);
173
174 rtsx_pci_init_cmd(pcr);
175 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
176 SD_POWER_MASK, SD_VCC_POWER_ON);
177 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
178 LDO3318_PWR_MASK, 0x06);
179 err = rtsx_pci_send_cmd(pcr, 100);
180 if (err < 0)
181 return err;
182
183 return 0;
184}
185
186static int rts5249_card_power_off(struct rtsx_pcr *pcr, int card)
187{
188 rtsx_pci_init_cmd(pcr);
189 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
190 SD_POWER_MASK, SD_POWER_OFF);
191 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
192 LDO3318_PWR_MASK, 0x00);
193 return rtsx_pci_send_cmd(pcr, 100);
194}
195
196static int rts5249_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
197{
198 int err;
Wei WANG4c4b8c12013-04-11 10:43:40 +0800199
200 if (voltage == OUTPUT_3V3) {
201 err = rtsx_pci_write_phy_register(pcr, PHY_TUNE, 0x4FC0 | 0x24);
202 if (err < 0)
203 return err;
Wei WANG4c4b8c12013-04-11 10:43:40 +0800204 } else if (voltage == OUTPUT_1V8) {
205 err = rtsx_pci_write_phy_register(pcr, PHY_BACR, 0x3C02);
206 if (err < 0)
207 return err;
208 err = rtsx_pci_write_phy_register(pcr, PHY_TUNE, 0x4C40 | 0x24);
209 if (err < 0)
210 return err;
Wei WANG4c4b8c12013-04-11 10:43:40 +0800211 } else {
212 return -EINVAL;
213 }
214
215 /* set pad drive */
216 rtsx_pci_init_cmd(pcr);
Wei WANG773ccdf2013-08-20 14:18:51 +0800217 rts5249_fill_driving(pcr, voltage);
Wei WANG4c4b8c12013-04-11 10:43:40 +0800218 return rtsx_pci_send_cmd(pcr, 100);
219}
220
221static const struct pcr_ops rts5249_pcr_ops = {
Wei WANG773ccdf2013-08-20 14:18:51 +0800222 .fetch_vendor_settings = rts5249_fetch_vendor_settings,
Wei WANG4c4b8c12013-04-11 10:43:40 +0800223 .extra_init_hw = rts5249_extra_init_hw,
224 .optimize_phy = rts5249_optimize_phy,
225 .turn_on_led = rts5249_turn_on_led,
226 .turn_off_led = rts5249_turn_off_led,
227 .enable_auto_blink = rts5249_enable_auto_blink,
228 .disable_auto_blink = rts5249_disable_auto_blink,
229 .card_power_on = rts5249_card_power_on,
230 .card_power_off = rts5249_card_power_off,
231 .switch_output_voltage = rts5249_switch_output_voltage,
Wei WANG5947c162013-08-20 14:18:52 +0800232 .force_power_down = rts5249_force_power_down,
Wei WANG4c4b8c12013-04-11 10:43:40 +0800233};
234
235/* SD Pull Control Enable:
236 * SD_DAT[3:0] ==> pull up
237 * SD_CD ==> pull up
238 * SD_WP ==> pull up
239 * SD_CMD ==> pull up
240 * SD_CLK ==> pull down
241 */
242static const u32 rts5249_sd_pull_ctl_enable_tbl[] = {
243 RTSX_REG_PAIR(CARD_PULL_CTL1, 0x66),
244 RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA),
245 RTSX_REG_PAIR(CARD_PULL_CTL3, 0xE9),
246 RTSX_REG_PAIR(CARD_PULL_CTL4, 0xAA),
247 0,
248};
249
250/* SD Pull Control Disable:
251 * SD_DAT[3:0] ==> pull down
252 * SD_CD ==> pull up
253 * SD_WP ==> pull down
254 * SD_CMD ==> pull down
255 * SD_CLK ==> pull down
256 */
257static const u32 rts5249_sd_pull_ctl_disable_tbl[] = {
258 RTSX_REG_PAIR(CARD_PULL_CTL1, 0x66),
259 RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
260 RTSX_REG_PAIR(CARD_PULL_CTL3, 0xD5),
261 RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55),
262 0,
263};
264
265/* MS Pull Control Enable:
266 * MS CD ==> pull up
267 * others ==> pull down
268 */
269static const u32 rts5249_ms_pull_ctl_enable_tbl[] = {
270 RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55),
271 RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
272 RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
273 0,
274};
275
276/* MS Pull Control Disable:
277 * MS CD ==> pull up
278 * others ==> pull down
279 */
280static const u32 rts5249_ms_pull_ctl_disable_tbl[] = {
281 RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55),
282 RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
283 RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
284 0,
285};
286
287void rts5249_init_params(struct rtsx_pcr *pcr)
288{
289 pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104;
290 pcr->num_slots = 2;
291 pcr->ops = &rts5249_pcr_ops;
292
Wei WANG773ccdf2013-08-20 14:18:51 +0800293 pcr->flags = 0;
294 pcr->card_drive_sel = RTSX_CARD_DRIVE_DEFAULT;
295 pcr->sd30_drive_sel_1v8 = CFG_DRIVER_TYPE_C;
296 pcr->sd30_drive_sel_3v3 = CFG_DRIVER_TYPE_B;
297 pcr->aspm_en = ASPM_L1_EN;
298
Wei WANG4c4b8c12013-04-11 10:43:40 +0800299 pcr->ic_version = rts5249_get_ic_version(pcr);
300 pcr->sd_pull_ctl_enable_tbl = rts5249_sd_pull_ctl_enable_tbl;
301 pcr->sd_pull_ctl_disable_tbl = rts5249_sd_pull_ctl_disable_tbl;
302 pcr->ms_pull_ctl_enable_tbl = rts5249_ms_pull_ctl_enable_tbl;
303 pcr->ms_pull_ctl_disable_tbl = rts5249_ms_pull_ctl_disable_tbl;
304}