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Alan Coxda9bb1d2006-01-18 17:44:13 -08001#
2# EDAC Kconfig
Doug Thompson4577ca52009-04-02 16:58:43 -07003# Copyright (c) 2008 Doug Thompson www.softwarebitmaker.com
Alan Coxda9bb1d2006-01-18 17:44:13 -08004# Licensed and distributed under the GPL
5#
Alan Coxda9bb1d2006-01-18 17:44:13 -08006
Borislav Petkov544516632012-12-18 22:02:56 +01007config EDAC_SUPPORT
8 bool
9
Jan Engelhardt751cb5e2007-07-15 23:39:27 -070010menuconfig EDAC
GeunSik Lime24aca62009-06-17 16:28:02 -070011 bool "EDAC (Error Detection And Correction) reporting"
Martin Schwidefskye25df122007-05-10 15:45:57 +020012 depends on HAS_IOMEM
Ralf Baechlef65aad42012-10-17 00:39:09 +020013 depends on X86 || PPC || TILE || ARM || EDAC_SUPPORT
Alan Coxda9bb1d2006-01-18 17:44:13 -080014 help
15 EDAC is designed to report errors in the core system.
16 These are low-level errors that are reported in the CPU or
Douglas Thompson8cb2a392007-07-19 01:50:12 -070017 supporting chipset or other subsystems:
18 memory errors, cache errors, PCI errors, thermal throttling, etc..
19 If unsure, select 'Y'.
Alan Coxda9bb1d2006-01-18 17:44:13 -080020
Tim Small57c432b2006-03-09 17:33:50 -080021 If this code is reporting problems on your system, please
22 see the EDAC project web pages for more information at:
23
24 <http://bluesmoke.sourceforge.net/>
25
26 and:
27
28 <http://buttersideup.com/edacwiki>
29
30 There is also a mailing list for the EDAC project, which can
31 be found via the sourceforge page.
32
Jan Engelhardt751cb5e2007-07-15 23:39:27 -070033if EDAC
Alan Coxda9bb1d2006-01-18 17:44:13 -080034
Mauro Carvalho Chehab19974712012-03-21 17:06:53 -030035config EDAC_LEGACY_SYSFS
36 bool "EDAC legacy sysfs"
37 default y
38 help
39 Enable the compatibility sysfs nodes.
40 Use 'Y' if your edac utilities aren't ported to work with the newer
41 structures.
42
Alan Coxda9bb1d2006-01-18 17:44:13 -080043config EDAC_DEBUG
44 bool "Debugging"
Alan Coxda9bb1d2006-01-18 17:44:13 -080045 help
Borislav Petkov37929872012-09-10 16:50:54 +020046 This turns on debugging information for the entire EDAC subsystem.
47 You do so by inserting edac_module with "edac_debug_level=x." Valid
48 levels are 0-4 (from low to high) and by default it is set to 2.
49 Usually you should select 'N' here.
Alan Coxda9bb1d2006-01-18 17:44:13 -080050
Borislav Petkov9cdeb402010-09-02 18:33:24 +020051config EDAC_DECODE_MCE
Borislav Petkov0d18b2e2009-10-02 15:31:48 +020052 tristate "Decode MCEs in human-readable form (only on AMD for now)"
Borislav Petkov168eb342011-08-10 09:43:30 -030053 depends on CPU_SUP_AMD && X86_MCE_AMD
Borislav Petkov0d18b2e2009-10-02 15:31:48 +020054 default y
55 ---help---
56 Enable this option if you want to decode Machine Check Exceptions
Lucas De Marchi25985ed2011-03-30 22:57:33 -030057 occurring on your machine in human-readable form.
Borislav Petkov0d18b2e2009-10-02 15:31:48 +020058
59 You should definitely say Y here in case you want to decode MCEs
60 which occur really early upon boot, before the module infrastructure
61 has been initialized.
62
Borislav Petkov9cdeb402010-09-02 18:33:24 +020063config EDAC_MCE_INJ
64 tristate "Simple MCE injection interface over /sysfs"
65 depends on EDAC_DECODE_MCE
66 default n
67 help
68 This is a simple interface to inject MCEs over /sysfs and test
69 the MCE decoding code in EDAC.
70
71 This is currently AMD-only.
72
Alan Coxda9bb1d2006-01-18 17:44:13 -080073config EDAC_MM_EDAC
74 tristate "Main Memory EDAC (Error Detection And Correction) reporting"
Chen, Gong76ac8272014-06-11 13:54:04 -070075 select RAS
Alan Coxda9bb1d2006-01-18 17:44:13 -080076 help
77 Some systems are able to detect and correct errors in main
78 memory. EDAC can report statistics on memory error
79 detection and correction (EDAC - or commonly referred to ECC
80 errors). EDAC will also try to decode where these errors
81 occurred so that a particular failing memory module can be
82 replaced. If unsure, select 'Y'.
83
Mauro Carvalho Chehab77c5f5d2013-02-15 06:11:57 -030084config EDAC_GHES
85 bool "Output ACPI APEI/GHES BIOS detected errors via EDAC"
86 depends on ACPI_APEI_GHES && (EDAC_MM_EDAC=y)
87 default y
88 help
89 Not all machines support hardware-driven error report. Some of those
90 provide a BIOS-driven error report mechanism via ACPI, using the
91 APEI/GHES driver. By enabling this option, the error reports provided
92 by GHES are sent to userspace via the EDAC API.
93
94 When this option is enabled, it will disable the hardware-driven
95 mechanisms, if a GHES BIOS is detected, entering into the
96 "Firmware First" mode.
97
98 It should be noticed that keeping both GHES and a hardware-driven
99 error mechanism won't work well, as BIOS will race with OS, while
100 reading the error registers. So, if you want to not use "Firmware
101 first" GHES error mechanism, you should disable GHES either at
102 compilation time or by passing "ghes.disable=1" Kernel parameter
103 at boot time.
104
105 In doubt, say 'Y'.
106
Doug Thompson7d6034d2009-04-27 20:01:01 +0200107config EDAC_AMD64
Borislav Petkov027dbd62010-10-13 22:12:15 +0200108 tristate "AMD64 (Opteron, Athlon64) K8, F10h"
109 depends on EDAC_MM_EDAC && AMD_NB && X86_64 && EDAC_DECODE_MCE
Doug Thompson7d6034d2009-04-27 20:01:01 +0200110 help
Borislav Petkov027dbd62010-10-13 22:12:15 +0200111 Support for error detection and correction of DRAM ECC errors on
112 the AMD64 families of memory controllers (K8 and F10h)
Doug Thompson7d6034d2009-04-27 20:01:01 +0200113
114config EDAC_AMD64_ERROR_INJECTION
Borislav Petkov9cdeb402010-09-02 18:33:24 +0200115 bool "Sysfs HW Error injection facilities"
Doug Thompson7d6034d2009-04-27 20:01:01 +0200116 depends on EDAC_AMD64
117 help
118 Recent Opterons (Family 10h and later) provide for Memory Error
119 Injection into the ECC detection circuits. The amd64_edac module
120 allows the operator/user to inject Uncorrectable and Correctable
121 errors into DRAM.
122
123 When enabled, in each of the respective memory controller directories
124 (/sys/devices/system/edac/mc/mcX), there are 3 input files:
125
126 - inject_section (0..3, 16-byte section of 64-byte cacheline),
127 - inject_word (0..8, 16-bit word of 16-byte section),
128 - inject_ecc_vector (hex ecc vector: select bits of inject word)
129
130 In addition, there are two control files, inject_read and inject_write,
131 which trigger the DRAM ECC Read and Write respectively.
Alan Coxda9bb1d2006-01-18 17:44:13 -0800132
133config EDAC_AMD76X
134 tristate "AMD 76x (760, 762, 768)"
Dave Jones90cbc452006-02-03 03:04:11 -0800135 depends on EDAC_MM_EDAC && PCI && X86_32
Alan Coxda9bb1d2006-01-18 17:44:13 -0800136 help
137 Support for error detection and correction on the AMD 76x
138 series of chipsets used with the Athlon processor.
139
140config EDAC_E7XXX
141 tristate "Intel e7xxx (e7205, e7500, e7501, e7505)"
Dave Peterson39f1d8d2006-03-26 01:38:50 -0800142 depends on EDAC_MM_EDAC && PCI && X86_32
Alan Coxda9bb1d2006-01-18 17:44:13 -0800143 help
144 Support for error detection and correction on the Intel
145 E7205, E7500, E7501 and E7505 server chipsets.
146
147config EDAC_E752X
Andrei Konovalov5135b792008-04-29 01:03:13 -0700148 tristate "Intel e752x (e7520, e7525, e7320) and 3100"
Stephen Rothwell40b31362013-05-21 13:49:35 +1000149 depends on EDAC_MM_EDAC && PCI && X86
Alan Coxda9bb1d2006-01-18 17:44:13 -0800150 help
151 Support for error detection and correction on the Intel
152 E7520, E7525, E7320 server chipsets.
153
Tim Small5a2c6752007-07-19 01:49:42 -0700154config EDAC_I82443BXGX
155 tristate "Intel 82443BX/GX (440BX/GX)"
156 depends on EDAC_MM_EDAC && PCI && X86_32
Andrew Morton28f96eea2007-07-19 01:49:45 -0700157 depends on BROKEN
Tim Small5a2c6752007-07-19 01:49:42 -0700158 help
159 Support for error detection and correction on the Intel
160 82443BX/GX memory controllers (440BX/GX chipsets).
161
Alan Coxda9bb1d2006-01-18 17:44:13 -0800162config EDAC_I82875P
163 tristate "Intel 82875p (D82875P, E7210)"
Dave Peterson39f1d8d2006-03-26 01:38:50 -0800164 depends on EDAC_MM_EDAC && PCI && X86_32
Alan Coxda9bb1d2006-01-18 17:44:13 -0800165 help
166 Support for error detection and correction on the Intel
167 DP82785P and E7210 server chipsets.
168
Ranganathan Desikan420390f2007-07-19 01:50:31 -0700169config EDAC_I82975X
170 tristate "Intel 82975x (D82975x)"
171 depends on EDAC_MM_EDAC && PCI && X86
172 help
173 Support for error detection and correction on the Intel
174 DP82975x server chipsets.
175
Jason Uhlenkott535c6a52007-07-19 01:49:48 -0700176config EDAC_I3000
177 tristate "Intel 3000/3010"
Jason Uhlenkottf5c04542008-02-07 00:15:01 -0800178 depends on EDAC_MM_EDAC && PCI && X86
Jason Uhlenkott535c6a52007-07-19 01:49:48 -0700179 help
180 Support for error detection and correction on the Intel
181 3000 and 3010 server chipsets.
182
Jason Uhlenkottdd8ef1d2009-09-23 15:57:27 -0700183config EDAC_I3200
184 tristate "Intel 3200"
Kees Cook053417a2013-01-16 18:53:31 -0800185 depends on EDAC_MM_EDAC && PCI && X86
Jason Uhlenkottdd8ef1d2009-09-23 15:57:27 -0700186 help
187 Support for error detection and correction on the Intel
188 3200 and 3210 server chipsets.
189
Jason Baron7ee40b82014-07-04 13:48:32 +0200190config EDAC_IE31200
191 tristate "Intel e312xx"
192 depends on EDAC_MM_EDAC && PCI && X86
193 help
194 Support for error detection and correction on the Intel
195 E3-1200 based DRAM controllers.
196
Hitoshi Mitakedf8bc08c2008-10-29 14:00:50 -0700197config EDAC_X38
198 tristate "Intel X38"
199 depends on EDAC_MM_EDAC && PCI && X86
200 help
201 Support for error detection and correction on the Intel
202 X38 server chipsets.
203
Mauro Carvalho Chehab920c8df2009-01-06 14:43:00 -0800204config EDAC_I5400
205 tristate "Intel 5400 (Seaburg) chipsets"
206 depends on EDAC_MM_EDAC && PCI && X86
207 help
208 Support for error detection and correction the Intel
209 i5400 MCH chipset (Seaburg).
210
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300211config EDAC_I7CORE
212 tristate "Intel i7 Core (Nehalem) processors"
Borislav Petkov168eb342011-08-10 09:43:30 -0300213 depends on EDAC_MM_EDAC && PCI && X86 && X86_MCE_INTEL
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300214 help
215 Support for error detection and correction the Intel
Mauro Carvalho Chehab696e4092009-07-23 06:57:45 -0300216 i7 Core (Nehalem) Integrated Memory Controller that exists on
217 newer processors like i7 Core, i7 Core Extreme, Xeon 35xx
218 and Xeon 55xx processors.
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300219
Alan Coxda9bb1d2006-01-18 17:44:13 -0800220config EDAC_I82860
221 tristate "Intel 82860"
Dave Peterson39f1d8d2006-03-26 01:38:50 -0800222 depends on EDAC_MM_EDAC && PCI && X86_32
Alan Coxda9bb1d2006-01-18 17:44:13 -0800223 help
224 Support for error detection and correction on the Intel
225 82860 chipset.
226
227config EDAC_R82600
228 tristate "Radisys 82600 embedded chipset"
Dave Peterson39f1d8d2006-03-26 01:38:50 -0800229 depends on EDAC_MM_EDAC && PCI && X86_32
Alan Coxda9bb1d2006-01-18 17:44:13 -0800230 help
231 Support for error detection and correction on the Radisys
232 82600 embedded chipset.
233
Eric Wolleseneb607052007-07-19 01:49:39 -0700234config EDAC_I5000
235 tristate "Intel Greencreek/Blackford chipset"
236 depends on EDAC_MM_EDAC && X86 && PCI
237 help
238 Support for error detection and correction the Intel
239 Greekcreek/Blackford chipsets.
240
Arthur Jones8f421c592008-07-25 01:49:04 -0700241config EDAC_I5100
242 tristate "Intel San Clemente MCH"
243 depends on EDAC_MM_EDAC && X86 && PCI
244 help
245 Support for error detection and correction the Intel
246 San Clemente MCH.
247
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300248config EDAC_I7300
249 tristate "Intel Clarksboro MCH"
250 depends on EDAC_MM_EDAC && X86 && PCI
251 help
252 Support for error detection and correction the Intel
253 Clarksboro MCH (Intel 7300 chipset).
254
Mauro Carvalho Chehab3d78c9a2011-10-20 19:33:46 -0200255config EDAC_SBRIDGE
Aristeu Rozanski50d1bb92014-06-20 10:27:54 -0300256 tristate "Intel Sandy-Bridge/Ivy-Bridge/Haswell Integrated MC"
Hui Wang22a5c272012-02-06 04:10:59 -0300257 depends on EDAC_MM_EDAC && PCI && X86_64 && X86_MCE_INTEL
Kees Cook053417a2013-01-16 18:53:31 -0800258 depends on PCI_MMCONFIG
Mauro Carvalho Chehab3d78c9a2011-10-20 19:33:46 -0200259 help
260 Support for error detection and correction the Intel
Aristeu Rozanski50d1bb92014-06-20 10:27:54 -0300261 Sandy Bridge, Ivy Bridge and Haswell Integrated Memory Controllers.
Mauro Carvalho Chehab3d78c9a2011-10-20 19:33:46 -0200262
Dave Jianga9a753d2008-02-07 00:14:55 -0800263config EDAC_MPC85XX
Ira W. Snyderb4846252009-09-23 15:57:25 -0700264 tristate "Freescale MPC83xx / MPC85xx"
Anton Vorontsov1cd85212010-07-20 13:24:27 -0700265 depends on EDAC_MM_EDAC && FSL_SOC && (PPC_83xx || PPC_85xx)
Dave Jianga9a753d2008-02-07 00:14:55 -0800266 help
267 Support for error detection and correction on the Freescale
Ira W. Snyderb4846252009-09-23 15:57:25 -0700268 MPC8349, MPC8560, MPC8540, MPC8548
Dave Jianga9a753d2008-02-07 00:14:55 -0800269
Dave Jiang4f4aeea2008-02-07 00:14:56 -0800270config EDAC_MV64X60
271 tristate "Marvell MV64x60"
272 depends on EDAC_MM_EDAC && MV64X60
273 help
274 Support for error detection and correction on the Marvell
275 MV64360 and MV64460 chipsets.
276
Egor Martovetsky7d8536f2007-07-19 01:50:24 -0700277config EDAC_PASEMI
278 tristate "PA Semi PWRficient"
279 depends on EDAC_MM_EDAC && PCI
Doug Thompsonddcc3052007-07-26 10:41:16 -0700280 depends on PPC_PASEMI
Egor Martovetsky7d8536f2007-07-19 01:50:24 -0700281 help
282 Support for error detection and correction on PA Semi
283 PWRficient.
284
Benjamin Herrenschmidt48764e42008-02-07 00:14:53 -0800285config EDAC_CELL
286 tristate "Cell Broadband Engine memory controller"
Benjamin Krilldef434c2008-11-27 16:15:44 +0100287 depends on EDAC_MM_EDAC && PPC_CELL_COMMON
Benjamin Herrenschmidt48764e42008-02-07 00:14:53 -0800288 help
289 Support for error detection and correction on the
290 Cell Broadband Engine internal memory controller
291 on platform without a hypervisor
Egor Martovetsky7d8536f2007-07-19 01:50:24 -0700292
Grant Ericksondba7a772009-04-02 16:58:45 -0700293config EDAC_PPC4XX
294 tristate "PPC4xx IBM DDR2 Memory Controller"
295 depends on EDAC_MM_EDAC && 4xx
296 help
297 This enables support for EDAC on the ECC memory used
298 with the IBM DDR2 memory controller found in various
299 PowerPC 4xx embedded processors such as the 405EX[r],
300 440SP, 440SPe, 460EX, 460GT and 460SX.
301
Harry Ciaoe8765582009-04-02 16:58:51 -0700302config EDAC_AMD8131
303 tristate "AMD8131 HyperTransport PCI-X Tunnel"
Harry Ciao715fe7a2009-05-28 14:34:43 -0700304 depends on EDAC_MM_EDAC && PCI && PPC_MAPLE
Harry Ciaoe8765582009-04-02 16:58:51 -0700305 help
306 Support for error detection and correction on the
307 AMD8131 HyperTransport PCI-X Tunnel chip.
Harry Ciao715fe7a2009-05-28 14:34:43 -0700308 Note, add more Kconfig dependency if it's adopted
309 on some machine other than Maple.
Harry Ciaoe8765582009-04-02 16:58:51 -0700310
Harry Ciao58b4ce62009-04-02 16:58:51 -0700311config EDAC_AMD8111
312 tristate "AMD8111 HyperTransport I/O Hub"
Harry Ciao715fe7a2009-05-28 14:34:43 -0700313 depends on EDAC_MM_EDAC && PCI && PPC_MAPLE
Harry Ciao58b4ce62009-04-02 16:58:51 -0700314 help
315 Support for error detection and correction on the
316 AMD8111 HyperTransport I/O Hub chip.
Harry Ciao715fe7a2009-05-28 14:34:43 -0700317 Note, add more Kconfig dependency if it's adopted
318 on some machine other than Maple.
Harry Ciao58b4ce62009-04-02 16:58:51 -0700319
Harry Ciao2a9036a2009-06-17 16:27:58 -0700320config EDAC_CPC925
321 tristate "IBM CPC925 Memory Controller (PPC970FX)"
322 depends on EDAC_MM_EDAC && PPC64
323 help
324 Support for error detection and correction on the
325 IBM CPC925 Bridge and Memory Controller, which is
326 a companion chip to the PowerPC 970 family of
327 processors.
328
Chris Metcalf5c770752011-03-01 13:01:49 -0500329config EDAC_TILE
330 tristate "Tilera Memory Controller"
331 depends on EDAC_MM_EDAC && TILE
332 default y
333 help
334 Support for error detection and correction on the
335 Tilera memory controller.
336
Rob Herringa1b01ed2012-06-13 12:01:55 -0500337config EDAC_HIGHBANK_MC
338 tristate "Highbank Memory Controller"
339 depends on EDAC_MM_EDAC && ARCH_HIGHBANK
340 help
341 Support for error detection and correction on the
342 Calxeda Highbank memory controller.
343
Rob Herring69154d02012-06-11 21:32:14 -0500344config EDAC_HIGHBANK_L2
345 tristate "Highbank L2 Cache"
346 depends on EDAC_MM_EDAC && ARCH_HIGHBANK
347 help
348 Support for error detection and correction on the
349 Calxeda Highbank memory controller.
350
Ralf Baechlef65aad42012-10-17 00:39:09 +0200351config EDAC_OCTEON_PC
352 tristate "Cavium Octeon Primary Caches"
353 depends on EDAC_MM_EDAC && CPU_CAVIUM_OCTEON
354 help
355 Support for error detection and correction on the primary caches of
356 the cnMIPS cores of Cavium Octeon family SOCs.
357
358config EDAC_OCTEON_L2C
359 tristate "Cavium Octeon Secondary Caches (L2C)"
David Daney9ddebc42013-05-22 15:10:46 +0000360 depends on EDAC_MM_EDAC && CAVIUM_OCTEON_SOC
Ralf Baechlef65aad42012-10-17 00:39:09 +0200361 help
362 Support for error detection and correction on the
363 Cavium Octeon family of SOCs.
364
365config EDAC_OCTEON_LMC
366 tristate "Cavium Octeon DRAM Memory Controller (LMC)"
David Daney9ddebc42013-05-22 15:10:46 +0000367 depends on EDAC_MM_EDAC && CAVIUM_OCTEON_SOC
Ralf Baechlef65aad42012-10-17 00:39:09 +0200368 help
369 Support for error detection and correction on the
370 Cavium Octeon family of SOCs.
371
372config EDAC_OCTEON_PCI
373 tristate "Cavium Octeon PCI Controller"
David Daney9ddebc42013-05-22 15:10:46 +0000374 depends on EDAC_MM_EDAC && PCI && CAVIUM_OCTEON_SOC
Ralf Baechlef65aad42012-10-17 00:39:09 +0200375 help
376 Support for error detection and correction on the
377 Cavium Octeon family of SOCs.
378
Thor Thayer71bcada2014-09-03 10:27:54 -0500379config EDAC_ALTERA_MC
380 tristate "Altera SDRAM Memory Controller EDAC"
381 depends on EDAC_MM_EDAC && ARCH_SOCFPGA
382 help
383 Support for error detection and correction on the
384 Altera SDRAM memory controller. Note that the
385 preloader must initialize the SDRAM before loading
386 the kernel.
387
Jan Engelhardt751cb5e2007-07-15 23:39:27 -0700388endif # EDAC