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gerrit-public.fairphone.software / kernel / msm-4.9 / d70a8ed3121e67da8e8bb713d592d9498916c58e / . / drivers / dma / coh901318.c
blob: 0604273deafb731cf9109683f288d321ce828a0b [file] [log] [blame]
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1/*
2 * driver/dma/coh901318.c
3 *
4 * Copyright (C) 2007-2009 ST-Ericsson
5 * License terms: GNU General Public License (GPL) version 2
6 * DMA driver for COH 901 318
7 * Author: Per Friden <per.friden@stericsson.com>
8 */
9
10#include <linux/init.h>
11#include <linux/module.h>
12#include <linux/kernel.h> /* printk() */
13#include <linux/fs.h> /* everything... */
Alexey Dobriyanb7f080c2011-06-16 11:01:34 +0000[diff] [blame]14#include <linux/scatterlist.h>
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]15#include <linux/slab.h> /* kmalloc() */
16#include <linux/dmaengine.h>
17#include <linux/platform_device.h>
18#include <linux/device.h>
19#include <linux/irqreturn.h>
20#include <linux/interrupt.h>
21#include <linux/io.h>
22#include <linux/uaccess.h>
23#include <linux/debugfs.h>
Linus Walleij9f575d92013-01-04 10:35:06 +0100[diff] [blame]24#include <linux/platform_data/dma-coh901318.h>
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]25
Linus Walleij2b9277a2013-01-04 13:56:16 +0100[diff] [blame]26#include "coh901318.h"
Russell King - ARM Linuxd2ebfb32012-03-06 22:34:26 +0000[diff] [blame]27#include "dmaengine.h"
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]28
Linus Walleij03b53572013-01-04 14:07:51 +0100[diff] [blame]29#define COH901318_MOD32_MASK (0x1F)
30#define COH901318_WORD_MASK (0xFFFFFFFF)
31/* INT_STATUS - Interrupt Status Registers 32bit (R/-) */
32#define COH901318_INT_STATUS1 (0x0000)
33#define COH901318_INT_STATUS2 (0x0004)
34/* TC_INT_STATUS - Terminal Count Interrupt Status Registers 32bit (R/-) */
35#define COH901318_TC_INT_STATUS1 (0x0008)
36#define COH901318_TC_INT_STATUS2 (0x000C)
37/* TC_INT_CLEAR - Terminal Count Interrupt Clear Registers 32bit (-/W) */
38#define COH901318_TC_INT_CLEAR1 (0x0010)
39#define COH901318_TC_INT_CLEAR2 (0x0014)
40/* RAW_TC_INT_STATUS - Raw Term Count Interrupt Status Registers 32bit (R/-) */
41#define COH901318_RAW_TC_INT_STATUS1 (0x0018)
42#define COH901318_RAW_TC_INT_STATUS2 (0x001C)
43/* BE_INT_STATUS - Bus Error Interrupt Status Registers 32bit (R/-) */
44#define COH901318_BE_INT_STATUS1 (0x0020)
45#define COH901318_BE_INT_STATUS2 (0x0024)
46/* BE_INT_CLEAR - Bus Error Interrupt Clear Registers 32bit (-/W) */
47#define COH901318_BE_INT_CLEAR1 (0x0028)
48#define COH901318_BE_INT_CLEAR2 (0x002C)
49/* RAW_BE_INT_STATUS - Raw Term Count Interrupt Status Registers 32bit (R/-) */
50#define COH901318_RAW_BE_INT_STATUS1 (0x0030)
51#define COH901318_RAW_BE_INT_STATUS2 (0x0034)
52
53/*
54 * CX_CFG - Channel Configuration Registers 32bit (R/W)
55 */
56#define COH901318_CX_CFG (0x0100)
57#define COH901318_CX_CFG_SPACING (0x04)
58/* Channel enable activates tha dma job */
59#define COH901318_CX_CFG_CH_ENABLE (0x00000001)
60#define COH901318_CX_CFG_CH_DISABLE (0x00000000)
61/* Request Mode */
62#define COH901318_CX_CFG_RM_MASK (0x00000006)
63#define COH901318_CX_CFG_RM_MEMORY_TO_MEMORY (0x0 << 1)
64#define COH901318_CX_CFG_RM_PRIMARY_TO_MEMORY (0x1 << 1)
65#define COH901318_CX_CFG_RM_MEMORY_TO_PRIMARY (0x1 << 1)
66#define COH901318_CX_CFG_RM_PRIMARY_TO_SECONDARY (0x3 << 1)
67#define COH901318_CX_CFG_RM_SECONDARY_TO_PRIMARY (0x3 << 1)
68/* Linked channel request field. RM must == 11 */
69#define COH901318_CX_CFG_LCRF_SHIFT 3
70#define COH901318_CX_CFG_LCRF_MASK (0x000001F8)
71#define COH901318_CX_CFG_LCR_DISABLE (0x00000000)
72/* Terminal Counter Interrupt Request Mask */
73#define COH901318_CX_CFG_TC_IRQ_ENABLE (0x00000200)
74#define COH901318_CX_CFG_TC_IRQ_DISABLE (0x00000000)
75/* Bus Error interrupt Mask */
76#define COH901318_CX_CFG_BE_IRQ_ENABLE (0x00000400)
77#define COH901318_CX_CFG_BE_IRQ_DISABLE (0x00000000)
78
79/*
80 * CX_STAT - Channel Status Registers 32bit (R/-)
81 */
82#define COH901318_CX_STAT (0x0200)
83#define COH901318_CX_STAT_SPACING (0x04)
84#define COH901318_CX_STAT_RBE_IRQ_IND (0x00000008)
85#define COH901318_CX_STAT_RTC_IRQ_IND (0x00000004)
86#define COH901318_CX_STAT_ACTIVE (0x00000002)
87#define COH901318_CX_STAT_ENABLED (0x00000001)
88
89/*
90 * CX_CTRL - Channel Control Registers 32bit (R/W)
91 */
92#define COH901318_CX_CTRL (0x0400)
93#define COH901318_CX_CTRL_SPACING (0x10)
94/* Transfer Count Enable */
95#define COH901318_CX_CTRL_TC_ENABLE (0x00001000)
96#define COH901318_CX_CTRL_TC_DISABLE (0x00000000)
97/* Transfer Count Value 0 - 4095 */
98#define COH901318_CX_CTRL_TC_VALUE_MASK (0x00000FFF)
99/* Burst count */
100#define COH901318_CX_CTRL_BURST_COUNT_MASK (0x0000E000)
101#define COH901318_CX_CTRL_BURST_COUNT_64_BYTES (0x7 << 13)
102#define COH901318_CX_CTRL_BURST_COUNT_48_BYTES (0x6 << 13)
103#define COH901318_CX_CTRL_BURST_COUNT_32_BYTES (0x5 << 13)
104#define COH901318_CX_CTRL_BURST_COUNT_16_BYTES (0x4 << 13)
105#define COH901318_CX_CTRL_BURST_COUNT_8_BYTES (0x3 << 13)
106#define COH901318_CX_CTRL_BURST_COUNT_4_BYTES (0x2 << 13)
107#define COH901318_CX_CTRL_BURST_COUNT_2_BYTES (0x1 << 13)
108#define COH901318_CX_CTRL_BURST_COUNT_1_BYTE (0x0 << 13)
109/* Source bus size */
110#define COH901318_CX_CTRL_SRC_BUS_SIZE_MASK (0x00030000)
111#define COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS (0x2 << 16)
112#define COH901318_CX_CTRL_SRC_BUS_SIZE_16_BITS (0x1 << 16)
113#define COH901318_CX_CTRL_SRC_BUS_SIZE_8_BITS (0x0 << 16)
114/* Source address increment */
115#define COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE (0x00040000)
116#define COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE (0x00000000)
117/* Destination Bus Size */
118#define COH901318_CX_CTRL_DST_BUS_SIZE_MASK (0x00180000)
119#define COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS (0x2 << 19)
120#define COH901318_CX_CTRL_DST_BUS_SIZE_16_BITS (0x1 << 19)
121#define COH901318_CX_CTRL_DST_BUS_SIZE_8_BITS (0x0 << 19)
122/* Destination address increment */
123#define COH901318_CX_CTRL_DST_ADDR_INC_ENABLE (0x00200000)
124#define COH901318_CX_CTRL_DST_ADDR_INC_DISABLE (0x00000000)
125/* Master Mode (Master2 is only connected to MSL) */
126#define COH901318_CX_CTRL_MASTER_MODE_MASK (0x00C00000)
127#define COH901318_CX_CTRL_MASTER_MODE_M2R_M1W (0x3 << 22)
128#define COH901318_CX_CTRL_MASTER_MODE_M1R_M2W (0x2 << 22)
129#define COH901318_CX_CTRL_MASTER_MODE_M2RW (0x1 << 22)
130#define COH901318_CX_CTRL_MASTER_MODE_M1RW (0x0 << 22)
131/* Terminal Count flag to PER enable */
132#define COH901318_CX_CTRL_TCP_ENABLE (0x01000000)
133#define COH901318_CX_CTRL_TCP_DISABLE (0x00000000)
134/* Terminal Count flags to CPU enable */
135#define COH901318_CX_CTRL_TC_IRQ_ENABLE (0x02000000)
136#define COH901318_CX_CTRL_TC_IRQ_DISABLE (0x00000000)
137/* Hand shake to peripheral */
138#define COH901318_CX_CTRL_HSP_ENABLE (0x04000000)
139#define COH901318_CX_CTRL_HSP_DISABLE (0x00000000)
140#define COH901318_CX_CTRL_HSS_ENABLE (0x08000000)
141#define COH901318_CX_CTRL_HSS_DISABLE (0x00000000)
142/* DMA mode */
143#define COH901318_CX_CTRL_DDMA_MASK (0x30000000)
144#define COH901318_CX_CTRL_DDMA_LEGACY (0x0 << 28)
145#define COH901318_CX_CTRL_DDMA_DEMAND_DMA1 (0x1 << 28)
146#define COH901318_CX_CTRL_DDMA_DEMAND_DMA2 (0x2 << 28)
147/* Primary Request Data Destination */
148#define COH901318_CX_CTRL_PRDD_MASK (0x40000000)
149#define COH901318_CX_CTRL_PRDD_DEST (0x1 << 30)
150#define COH901318_CX_CTRL_PRDD_SOURCE (0x0 << 30)
151
152/*
153 * CX_SRC_ADDR - Channel Source Address Registers 32bit (R/W)
154 */
155#define COH901318_CX_SRC_ADDR (0x0404)
156#define COH901318_CX_SRC_ADDR_SPACING (0x10)
157
158/*
159 * CX_DST_ADDR - Channel Destination Address Registers 32bit R/W
160 */
161#define COH901318_CX_DST_ADDR (0x0408)
162#define COH901318_CX_DST_ADDR_SPACING (0x10)
163
164/*
165 * CX_LNK_ADDR - Channel Link Address Registers 32bit (R/W)
166 */
167#define COH901318_CX_LNK_ADDR (0x040C)
168#define COH901318_CX_LNK_ADDR_SPACING (0x10)
169#define COH901318_CX_LNK_LINK_IMMEDIATE (0x00000001)
170
171/**
172 * struct coh901318_params - parameters for DMAC configuration
173 * @config: DMA config register
174 * @ctrl_lli_last: DMA control register for the last lli in the list
175 * @ctrl_lli: DMA control register for an lli
176 * @ctrl_lli_chained: DMA control register for a chained lli
177 */
178struct coh901318_params {
179 u32 config;
180 u32 ctrl_lli_last;
181 u32 ctrl_lli;
182 u32 ctrl_lli_chained;
183};
184
185/**
186 * struct coh_dma_channel - dma channel base
187 * @name: ascii name of dma channel
188 * @number: channel id number
189 * @desc_nbr_max: number of preallocated descriptors
190 * @priority_high: prio of channel, 0 low otherwise high.
191 * @param: configuration parameters
192 */
193struct coh_dma_channel {
194 const char name[32];
195 const int number;
196 const int desc_nbr_max;
197 const int priority_high;
198 const struct coh901318_params param;
199};
200
201/**
202 * dma_access_memory_state_t - register dma for memory access
203 *
204 * @dev: The dma device
205 * @active: 1 means dma intends to access memory
206 * 0 means dma wont access memory
207 */
208typedef void (*dma_access_memory_state_t)(struct device *dev,
209 bool active);
210
211/**
212 * struct powersave - DMA power save structure
213 * @lock: lock protecting data in this struct
214 * @started_channels: bit mask indicating active dma channels
215 */
216struct powersave {
217 spinlock_t lock;
218 u64 started_channels;
219};
220
221/**
222 * struct coh901318_platform - platform arch structure
223 * @chans_slave: specifying dma slave channels
224 * @chans_memcpy: specifying dma memcpy channels
225 * @access_memory_state: requesting DMA memory access (on / off)
226 * @chan_conf: dma channel configurations
227 * @max_channels: max number of dma chanenls
228 */
229struct coh901318_platform {
230 const int *chans_slave;
231 const int *chans_memcpy;
232 const dma_access_memory_state_t access_memory_state;
233 const struct coh_dma_channel *chan_conf;
234 const int max_channels;
235};
236
Linus Walleij24dbcd82013-01-04 13:38:18 +0100[diff] [blame]237/* points out all dma slave channels.
238 * Syntax is [A1, B1, A2, B2, .... ,-1,-1]
239 * Select all channels from A to B, end of list is marked with -1,-1
240 */
241static int dma_slave_channels[] = {
242 U300_DMA_MSL_TX_0, U300_DMA_SPI_RX,
243 U300_DMA_UART1_TX, U300_DMA_UART1_RX, -1, -1};
244
245/* points out all dma memcpy channels. */
246static int dma_memcpy_channels[] = {
247 U300_DMA_GENERAL_PURPOSE_0, U300_DMA_GENERAL_PURPOSE_8, -1, -1};
248
249/** register dma for memory access
250 *
251 * active 1 means dma intends to access memory
252 * 0 means dma wont access memory
253 */
254static void coh901318_access_memory_state(struct device *dev, bool active)
255{
256}
257
258#define flags_memcpy_config (COH901318_CX_CFG_CH_DISABLE | \
259 COH901318_CX_CFG_RM_MEMORY_TO_MEMORY | \
260 COH901318_CX_CFG_LCR_DISABLE | \
261 COH901318_CX_CFG_TC_IRQ_ENABLE | \
262 COH901318_CX_CFG_BE_IRQ_ENABLE)
263#define flags_memcpy_lli_chained (COH901318_CX_CTRL_TC_ENABLE | \
264 COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
265 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
266 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
267 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
268 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
269 COH901318_CX_CTRL_MASTER_MODE_M1RW | \
270 COH901318_CX_CTRL_TCP_DISABLE | \
271 COH901318_CX_CTRL_TC_IRQ_DISABLE | \
272 COH901318_CX_CTRL_HSP_DISABLE | \
273 COH901318_CX_CTRL_HSS_DISABLE | \
274 COH901318_CX_CTRL_DDMA_LEGACY | \
275 COH901318_CX_CTRL_PRDD_SOURCE)
276#define flags_memcpy_lli (COH901318_CX_CTRL_TC_ENABLE | \
277 COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
278 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
279 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
280 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
281 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
282 COH901318_CX_CTRL_MASTER_MODE_M1RW | \
283 COH901318_CX_CTRL_TCP_DISABLE | \
284 COH901318_CX_CTRL_TC_IRQ_DISABLE | \
285 COH901318_CX_CTRL_HSP_DISABLE | \
286 COH901318_CX_CTRL_HSS_DISABLE | \
287 COH901318_CX_CTRL_DDMA_LEGACY | \
288 COH901318_CX_CTRL_PRDD_SOURCE)
289#define flags_memcpy_lli_last (COH901318_CX_CTRL_TC_ENABLE | \
290 COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
291 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
292 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
293 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
294 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
295 COH901318_CX_CTRL_MASTER_MODE_M1RW | \
296 COH901318_CX_CTRL_TCP_DISABLE | \
297 COH901318_CX_CTRL_TC_IRQ_ENABLE | \
298 COH901318_CX_CTRL_HSP_DISABLE | \
299 COH901318_CX_CTRL_HSS_DISABLE | \
300 COH901318_CX_CTRL_DDMA_LEGACY | \
301 COH901318_CX_CTRL_PRDD_SOURCE)
302
303const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
304 {
305 .number = U300_DMA_MSL_TX_0,
306 .name = "MSL TX 0",
307 .priority_high = 0,
Linus Walleij24dbcd82013-01-04 13:38:18 +0100[diff] [blame]308 },
309 {
310 .number = U300_DMA_MSL_TX_1,
311 .name = "MSL TX 1",
312 .priority_high = 0,
Linus Walleij24dbcd82013-01-04 13:38:18 +0100[diff] [blame]313 .param.config = COH901318_CX_CFG_CH_DISABLE |
314 COH901318_CX_CFG_LCR_DISABLE |
315 COH901318_CX_CFG_TC_IRQ_ENABLE |
316 COH901318_CX_CFG_BE_IRQ_ENABLE,
317 .param.ctrl_lli_chained = 0 |
318 COH901318_CX_CTRL_TC_ENABLE |
319 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
320 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
321 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
322 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
323 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
324 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
325 COH901318_CX_CTRL_TCP_DISABLE |
326 COH901318_CX_CTRL_TC_IRQ_DISABLE |
327 COH901318_CX_CTRL_HSP_ENABLE |
328 COH901318_CX_CTRL_HSS_DISABLE |
329 COH901318_CX_CTRL_DDMA_LEGACY |
330 COH901318_CX_CTRL_PRDD_SOURCE,
331 .param.ctrl_lli = 0 |
332 COH901318_CX_CTRL_TC_ENABLE |
333 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
334 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
335 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
336 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
337 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
338 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
339 COH901318_CX_CTRL_TCP_ENABLE |
340 COH901318_CX_CTRL_TC_IRQ_DISABLE |
341 COH901318_CX_CTRL_HSP_ENABLE |
342 COH901318_CX_CTRL_HSS_DISABLE |
343 COH901318_CX_CTRL_DDMA_LEGACY |
344 COH901318_CX_CTRL_PRDD_SOURCE,
345 .param.ctrl_lli_last = 0 |
346 COH901318_CX_CTRL_TC_ENABLE |
347 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
348 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
349 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
350 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
351 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
352 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
353 COH901318_CX_CTRL_TCP_ENABLE |
354 COH901318_CX_CTRL_TC_IRQ_ENABLE |
355 COH901318_CX_CTRL_HSP_ENABLE |
356 COH901318_CX_CTRL_HSS_DISABLE |
357 COH901318_CX_CTRL_DDMA_LEGACY |
358 COH901318_CX_CTRL_PRDD_SOURCE,
359 },
360 {
361 .number = U300_DMA_MSL_TX_2,
362 .name = "MSL TX 2",
363 .priority_high = 0,
Linus Walleij24dbcd82013-01-04 13:38:18 +0100[diff] [blame]364 .param.config = COH901318_CX_CFG_CH_DISABLE |
365 COH901318_CX_CFG_LCR_DISABLE |
366 COH901318_CX_CFG_TC_IRQ_ENABLE |
367 COH901318_CX_CFG_BE_IRQ_ENABLE,
368 .param.ctrl_lli_chained = 0 |
369 COH901318_CX_CTRL_TC_ENABLE |
370 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
371 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
372 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
373 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
374 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
375 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
376 COH901318_CX_CTRL_TCP_DISABLE |
377 COH901318_CX_CTRL_TC_IRQ_DISABLE |
378 COH901318_CX_CTRL_HSP_ENABLE |
379 COH901318_CX_CTRL_HSS_DISABLE |
380 COH901318_CX_CTRL_DDMA_LEGACY |
381 COH901318_CX_CTRL_PRDD_SOURCE,
382 .param.ctrl_lli = 0 |
383 COH901318_CX_CTRL_TC_ENABLE |
384 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
385 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
386 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
387 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
388 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
389 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
390 COH901318_CX_CTRL_TCP_ENABLE |
391 COH901318_CX_CTRL_TC_IRQ_DISABLE |
392 COH901318_CX_CTRL_HSP_ENABLE |
393 COH901318_CX_CTRL_HSS_DISABLE |
394 COH901318_CX_CTRL_DDMA_LEGACY |
395 COH901318_CX_CTRL_PRDD_SOURCE,
396 .param.ctrl_lli_last = 0 |
397 COH901318_CX_CTRL_TC_ENABLE |
398 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
399 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
400 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
401 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
402 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
403 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
404 COH901318_CX_CTRL_TCP_ENABLE |
405 COH901318_CX_CTRL_TC_IRQ_ENABLE |
406 COH901318_CX_CTRL_HSP_ENABLE |
407 COH901318_CX_CTRL_HSS_DISABLE |
408 COH901318_CX_CTRL_DDMA_LEGACY |
409 COH901318_CX_CTRL_PRDD_SOURCE,
410 .desc_nbr_max = 10,
411 },
412 {
413 .number = U300_DMA_MSL_TX_3,
414 .name = "MSL TX 3",
415 .priority_high = 0,
Linus Walleij24dbcd82013-01-04 13:38:18 +0100[diff] [blame]416 .param.config = COH901318_CX_CFG_CH_DISABLE |
417 COH901318_CX_CFG_LCR_DISABLE |
418 COH901318_CX_CFG_TC_IRQ_ENABLE |
419 COH901318_CX_CFG_BE_IRQ_ENABLE,
420 .param.ctrl_lli_chained = 0 |
421 COH901318_CX_CTRL_TC_ENABLE |
422 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
423 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
424 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
425 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
426 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
427 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
428 COH901318_CX_CTRL_TCP_DISABLE |
429 COH901318_CX_CTRL_TC_IRQ_DISABLE |
430 COH901318_CX_CTRL_HSP_ENABLE |
431 COH901318_CX_CTRL_HSS_DISABLE |
432 COH901318_CX_CTRL_DDMA_LEGACY |
433 COH901318_CX_CTRL_PRDD_SOURCE,
434 .param.ctrl_lli = 0 |
435 COH901318_CX_CTRL_TC_ENABLE |
436 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
437 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
438 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
439 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
440 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
441 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
442 COH901318_CX_CTRL_TCP_ENABLE |
443 COH901318_CX_CTRL_TC_IRQ_DISABLE |
444 COH901318_CX_CTRL_HSP_ENABLE |
445 COH901318_CX_CTRL_HSS_DISABLE |
446 COH901318_CX_CTRL_DDMA_LEGACY |
447 COH901318_CX_CTRL_PRDD_SOURCE,
448 .param.ctrl_lli_last = 0 |
449 COH901318_CX_CTRL_TC_ENABLE |
450 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
451 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
452 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
453 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
454 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
455 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
456 COH901318_CX_CTRL_TCP_ENABLE |
457 COH901318_CX_CTRL_TC_IRQ_ENABLE |
458 COH901318_CX_CTRL_HSP_ENABLE |
459 COH901318_CX_CTRL_HSS_DISABLE |
460 COH901318_CX_CTRL_DDMA_LEGACY |
461 COH901318_CX_CTRL_PRDD_SOURCE,
462 },
463 {
464 .number = U300_DMA_MSL_TX_4,
465 .name = "MSL TX 4",
466 .priority_high = 0,
Linus Walleij24dbcd82013-01-04 13:38:18 +0100[diff] [blame]467 .param.config = COH901318_CX_CFG_CH_DISABLE |
468 COH901318_CX_CFG_LCR_DISABLE |
469 COH901318_CX_CFG_TC_IRQ_ENABLE |
470 COH901318_CX_CFG_BE_IRQ_ENABLE,
471 .param.ctrl_lli_chained = 0 |
472 COH901318_CX_CTRL_TC_ENABLE |
473 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
474 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
475 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
476 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
477 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
478 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
479 COH901318_CX_CTRL_TCP_DISABLE |
480 COH901318_CX_CTRL_TC_IRQ_DISABLE |
481 COH901318_CX_CTRL_HSP_ENABLE |
482 COH901318_CX_CTRL_HSS_DISABLE |
483 COH901318_CX_CTRL_DDMA_LEGACY |
484 COH901318_CX_CTRL_PRDD_SOURCE,
485 .param.ctrl_lli = 0 |
486 COH901318_CX_CTRL_TC_ENABLE |
487 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
488 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
489 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
490 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
491 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
492 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
493 COH901318_CX_CTRL_TCP_ENABLE |
494 COH901318_CX_CTRL_TC_IRQ_DISABLE |
495 COH901318_CX_CTRL_HSP_ENABLE |
496 COH901318_CX_CTRL_HSS_DISABLE |
497 COH901318_CX_CTRL_DDMA_LEGACY |
498 COH901318_CX_CTRL_PRDD_SOURCE,
499 .param.ctrl_lli_last = 0 |
500 COH901318_CX_CTRL_TC_ENABLE |
501 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
502 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
503 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
504 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
505 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
506 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
507 COH901318_CX_CTRL_TCP_ENABLE |
508 COH901318_CX_CTRL_TC_IRQ_ENABLE |
509 COH901318_CX_CTRL_HSP_ENABLE |
510 COH901318_CX_CTRL_HSS_DISABLE |
511 COH901318_CX_CTRL_DDMA_LEGACY |
512 COH901318_CX_CTRL_PRDD_SOURCE,
513 },
514 {
515 .number = U300_DMA_MSL_TX_5,
516 .name = "MSL TX 5",
517 .priority_high = 0,
Linus Walleij24dbcd82013-01-04 13:38:18 +0100[diff] [blame]518 },
519 {
520 .number = U300_DMA_MSL_TX_6,
521 .name = "MSL TX 6",
522 .priority_high = 0,
Linus Walleij24dbcd82013-01-04 13:38:18 +0100[diff] [blame]523 },
524 {
525 .number = U300_DMA_MSL_RX_0,
526 .name = "MSL RX 0",
527 .priority_high = 0,
Linus Walleij24dbcd82013-01-04 13:38:18 +0100[diff] [blame]528 },
529 {
530 .number = U300_DMA_MSL_RX_1,
531 .name = "MSL RX 1",
532 .priority_high = 0,
Linus Walleij24dbcd82013-01-04 13:38:18 +0100[diff] [blame]533 .param.config = COH901318_CX_CFG_CH_DISABLE |
534 COH901318_CX_CFG_LCR_DISABLE |
535 COH901318_CX_CFG_TC_IRQ_ENABLE |
536 COH901318_CX_CFG_BE_IRQ_ENABLE,
537 .param.ctrl_lli_chained = 0 |
538 COH901318_CX_CTRL_TC_ENABLE |
539 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
540 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
541 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
542 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
543 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
544 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
545 COH901318_CX_CTRL_TCP_DISABLE |
546 COH901318_CX_CTRL_TC_IRQ_DISABLE |
547 COH901318_CX_CTRL_HSP_ENABLE |
548 COH901318_CX_CTRL_HSS_DISABLE |
549 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
550 COH901318_CX_CTRL_PRDD_DEST,
551 .param.ctrl_lli = 0,
552 .param.ctrl_lli_last = 0 |
553 COH901318_CX_CTRL_TC_ENABLE |
554 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
555 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
556 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
557 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
558 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
559 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
560 COH901318_CX_CTRL_TCP_DISABLE |
561 COH901318_CX_CTRL_TC_IRQ_ENABLE |
562 COH901318_CX_CTRL_HSP_ENABLE |
563 COH901318_CX_CTRL_HSS_DISABLE |
564 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
565 COH901318_CX_CTRL_PRDD_DEST,
566 },
567 {
568 .number = U300_DMA_MSL_RX_2,
569 .name = "MSL RX 2",
570 .priority_high = 0,
Linus Walleij24dbcd82013-01-04 13:38:18 +0100[diff] [blame]571 .param.config = COH901318_CX_CFG_CH_DISABLE |
572 COH901318_CX_CFG_LCR_DISABLE |
573 COH901318_CX_CFG_TC_IRQ_ENABLE |
574 COH901318_CX_CFG_BE_IRQ_ENABLE,
575 .param.ctrl_lli_chained = 0 |
576 COH901318_CX_CTRL_TC_ENABLE |
577 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
578 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
579 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
580 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
581 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
582 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
583 COH901318_CX_CTRL_TCP_DISABLE |
584 COH901318_CX_CTRL_TC_IRQ_DISABLE |
585 COH901318_CX_CTRL_HSP_ENABLE |
586 COH901318_CX_CTRL_HSS_DISABLE |
587 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
588 COH901318_CX_CTRL_PRDD_DEST,
589 .param.ctrl_lli = 0 |
590 COH901318_CX_CTRL_TC_ENABLE |
591 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
592 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
593 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
594 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
595 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
596 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
597 COH901318_CX_CTRL_TCP_DISABLE |
598 COH901318_CX_CTRL_TC_IRQ_ENABLE |
599 COH901318_CX_CTRL_HSP_ENABLE |
600 COH901318_CX_CTRL_HSS_DISABLE |
601 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
602 COH901318_CX_CTRL_PRDD_DEST,
603 .param.ctrl_lli_last = 0 |
604 COH901318_CX_CTRL_TC_ENABLE |
605 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
606 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
607 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
608 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
609 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
610 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
611 COH901318_CX_CTRL_TCP_DISABLE |
612 COH901318_CX_CTRL_TC_IRQ_ENABLE |
613 COH901318_CX_CTRL_HSP_ENABLE |
614 COH901318_CX_CTRL_HSS_DISABLE |
615 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
616 COH901318_CX_CTRL_PRDD_DEST,
617 },
618 {
619 .number = U300_DMA_MSL_RX_3,
620 .name = "MSL RX 3",
621 .priority_high = 0,
Linus Walleij24dbcd82013-01-04 13:38:18 +0100[diff] [blame]622 .param.config = COH901318_CX_CFG_CH_DISABLE |
623 COH901318_CX_CFG_LCR_DISABLE |
624 COH901318_CX_CFG_TC_IRQ_ENABLE |
625 COH901318_CX_CFG_BE_IRQ_ENABLE,
626 .param.ctrl_lli_chained = 0 |
627 COH901318_CX_CTRL_TC_ENABLE |
628 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
629 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
630 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
631 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
632 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
633 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
634 COH901318_CX_CTRL_TCP_DISABLE |
635 COH901318_CX_CTRL_TC_IRQ_DISABLE |
636 COH901318_CX_CTRL_HSP_ENABLE |
637 COH901318_CX_CTRL_HSS_DISABLE |
638 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
639 COH901318_CX_CTRL_PRDD_DEST,
640 .param.ctrl_lli = 0 |
641 COH901318_CX_CTRL_TC_ENABLE |
642 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
643 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
644 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
645 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
646 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
647 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
648 COH901318_CX_CTRL_TCP_DISABLE |
649 COH901318_CX_CTRL_TC_IRQ_ENABLE |
650 COH901318_CX_CTRL_HSP_ENABLE |
651 COH901318_CX_CTRL_HSS_DISABLE |
652 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
653 COH901318_CX_CTRL_PRDD_DEST,
654 .param.ctrl_lli_last = 0 |
655 COH901318_CX_CTRL_TC_ENABLE |
656 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
657 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
658 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
659 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
660 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
661 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
662 COH901318_CX_CTRL_TCP_DISABLE |
663 COH901318_CX_CTRL_TC_IRQ_ENABLE |
664 COH901318_CX_CTRL_HSP_ENABLE |
665 COH901318_CX_CTRL_HSS_DISABLE |
666 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
667 COH901318_CX_CTRL_PRDD_DEST,
668 },
669 {
670 .number = U300_DMA_MSL_RX_4,
671 .name = "MSL RX 4",
672 .priority_high = 0,
Linus Walleij24dbcd82013-01-04 13:38:18 +0100[diff] [blame]673 .param.config = COH901318_CX_CFG_CH_DISABLE |
674 COH901318_CX_CFG_LCR_DISABLE |
675 COH901318_CX_CFG_TC_IRQ_ENABLE |
676 COH901318_CX_CFG_BE_IRQ_ENABLE,
677 .param.ctrl_lli_chained = 0 |
678 COH901318_CX_CTRL_TC_ENABLE |
679 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
680 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
681 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
682 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
683 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
684 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
685 COH901318_CX_CTRL_TCP_DISABLE |
686 COH901318_CX_CTRL_TC_IRQ_DISABLE |
687 COH901318_CX_CTRL_HSP_ENABLE |
688 COH901318_CX_CTRL_HSS_DISABLE |
689 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
690 COH901318_CX_CTRL_PRDD_DEST,
691 .param.ctrl_lli = 0 |
692 COH901318_CX_CTRL_TC_ENABLE |
693 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
694 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
695 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
696 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
697 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
698 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
699 COH901318_CX_CTRL_TCP_DISABLE |
700 COH901318_CX_CTRL_TC_IRQ_ENABLE |
701 COH901318_CX_CTRL_HSP_ENABLE |
702 COH901318_CX_CTRL_HSS_DISABLE |
703 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
704 COH901318_CX_CTRL_PRDD_DEST,
705 .param.ctrl_lli_last = 0 |
706 COH901318_CX_CTRL_TC_ENABLE |
707 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
708 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
709 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
710 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
711 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
712 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
713 COH901318_CX_CTRL_TCP_DISABLE |
714 COH901318_CX_CTRL_TC_IRQ_ENABLE |
715 COH901318_CX_CTRL_HSP_ENABLE |
716 COH901318_CX_CTRL_HSS_DISABLE |
717 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
718 COH901318_CX_CTRL_PRDD_DEST,
719 },
720 {
721 .number = U300_DMA_MSL_RX_5,
722 .name = "MSL RX 5",
723 .priority_high = 0,
Linus Walleij24dbcd82013-01-04 13:38:18 +0100[diff] [blame]724 .param.config = COH901318_CX_CFG_CH_DISABLE |
725 COH901318_CX_CFG_LCR_DISABLE |
726 COH901318_CX_CFG_TC_IRQ_ENABLE |
727 COH901318_CX_CFG_BE_IRQ_ENABLE,
728 .param.ctrl_lli_chained = 0 |
729 COH901318_CX_CTRL_TC_ENABLE |
730 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
731 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
732 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
733 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
734 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
735 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
736 COH901318_CX_CTRL_TCP_DISABLE |
737 COH901318_CX_CTRL_TC_IRQ_DISABLE |
738 COH901318_CX_CTRL_HSP_ENABLE |
739 COH901318_CX_CTRL_HSS_DISABLE |
740 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
741 COH901318_CX_CTRL_PRDD_DEST,
742 .param.ctrl_lli = 0 |
743 COH901318_CX_CTRL_TC_ENABLE |
744 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
745 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
746 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
747 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
748 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
749 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
750 COH901318_CX_CTRL_TCP_DISABLE |
751 COH901318_CX_CTRL_TC_IRQ_ENABLE |
752 COH901318_CX_CTRL_HSP_ENABLE |
753 COH901318_CX_CTRL_HSS_DISABLE |
754 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
755 COH901318_CX_CTRL_PRDD_DEST,
756 .param.ctrl_lli_last = 0 |
757 COH901318_CX_CTRL_TC_ENABLE |
758 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
759 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
760 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
761 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
762 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
763 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
764 COH901318_CX_CTRL_TCP_DISABLE |
765 COH901318_CX_CTRL_TC_IRQ_ENABLE |
766 COH901318_CX_CTRL_HSP_ENABLE |
767 COH901318_CX_CTRL_HSS_DISABLE |
768 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
769 COH901318_CX_CTRL_PRDD_DEST,
770 },
771 {
772 .number = U300_DMA_MSL_RX_6,
773 .name = "MSL RX 6",
774 .priority_high = 0,
Linus Walleij24dbcd82013-01-04 13:38:18 +0100[diff] [blame]775 },
776 /*
777 * Don't set up device address, burst count or size of src
778 * or dst bus for this peripheral - handled by PrimeCell
779 * DMA extension.
780 */
781 {
782 .number = U300_DMA_MMCSD_RX_TX,
783 .name = "MMCSD RX TX",
784 .priority_high = 0,
785 .param.config = COH901318_CX_CFG_CH_DISABLE |
786 COH901318_CX_CFG_LCR_DISABLE |
787 COH901318_CX_CFG_TC_IRQ_ENABLE |
788 COH901318_CX_CFG_BE_IRQ_ENABLE,
789 .param.ctrl_lli_chained = 0 |
790 COH901318_CX_CTRL_TC_ENABLE |
791 COH901318_CX_CTRL_MASTER_MODE_M1RW |
792 COH901318_CX_CTRL_TCP_ENABLE |
793 COH901318_CX_CTRL_TC_IRQ_DISABLE |
794 COH901318_CX_CTRL_HSP_ENABLE |
795 COH901318_CX_CTRL_HSS_DISABLE |
796 COH901318_CX_CTRL_DDMA_LEGACY,
797 .param.ctrl_lli = 0 |
798 COH901318_CX_CTRL_TC_ENABLE |
799 COH901318_CX_CTRL_MASTER_MODE_M1RW |
800 COH901318_CX_CTRL_TCP_ENABLE |
801 COH901318_CX_CTRL_TC_IRQ_DISABLE |
802 COH901318_CX_CTRL_HSP_ENABLE |
803 COH901318_CX_CTRL_HSS_DISABLE |
804 COH901318_CX_CTRL_DDMA_LEGACY,
805 .param.ctrl_lli_last = 0 |
806 COH901318_CX_CTRL_TC_ENABLE |
807 COH901318_CX_CTRL_MASTER_MODE_M1RW |
808 COH901318_CX_CTRL_TCP_DISABLE |
809 COH901318_CX_CTRL_TC_IRQ_ENABLE |
810 COH901318_CX_CTRL_HSP_ENABLE |
811 COH901318_CX_CTRL_HSS_DISABLE |
812 COH901318_CX_CTRL_DDMA_LEGACY,
813
814 },
815 {
816 .number = U300_DMA_MSPRO_TX,
817 .name = "MSPRO TX",
818 .priority_high = 0,
819 },
820 {
821 .number = U300_DMA_MSPRO_RX,
822 .name = "MSPRO RX",
823 .priority_high = 0,
824 },
825 /*
826 * Don't set up device address, burst count or size of src
827 * or dst bus for this peripheral - handled by PrimeCell
828 * DMA extension.
829 */
830 {
831 .number = U300_DMA_UART0_TX,
832 .name = "UART0 TX",
833 .priority_high = 0,
834 .param.config = COH901318_CX_CFG_CH_DISABLE |
835 COH901318_CX_CFG_LCR_DISABLE |
836 COH901318_CX_CFG_TC_IRQ_ENABLE |
837 COH901318_CX_CFG_BE_IRQ_ENABLE,
838 .param.ctrl_lli_chained = 0 |
839 COH901318_CX_CTRL_TC_ENABLE |
840 COH901318_CX_CTRL_MASTER_MODE_M1RW |
841 COH901318_CX_CTRL_TCP_ENABLE |
842 COH901318_CX_CTRL_TC_IRQ_DISABLE |
843 COH901318_CX_CTRL_HSP_ENABLE |
844 COH901318_CX_CTRL_HSS_DISABLE |
845 COH901318_CX_CTRL_DDMA_LEGACY,
846 .param.ctrl_lli = 0 |
847 COH901318_CX_CTRL_TC_ENABLE |
848 COH901318_CX_CTRL_MASTER_MODE_M1RW |
849 COH901318_CX_CTRL_TCP_ENABLE |
850 COH901318_CX_CTRL_TC_IRQ_ENABLE |
851 COH901318_CX_CTRL_HSP_ENABLE |
852 COH901318_CX_CTRL_HSS_DISABLE |
853 COH901318_CX_CTRL_DDMA_LEGACY,
854 .param.ctrl_lli_last = 0 |
855 COH901318_CX_CTRL_TC_ENABLE |
856 COH901318_CX_CTRL_MASTER_MODE_M1RW |
857 COH901318_CX_CTRL_TCP_ENABLE |
858 COH901318_CX_CTRL_TC_IRQ_ENABLE |
859 COH901318_CX_CTRL_HSP_ENABLE |
860 COH901318_CX_CTRL_HSS_DISABLE |
861 COH901318_CX_CTRL_DDMA_LEGACY,
862 },
863 {
864 .number = U300_DMA_UART0_RX,
865 .name = "UART0 RX",
866 .priority_high = 0,
867 .param.config = COH901318_CX_CFG_CH_DISABLE |
868 COH901318_CX_CFG_LCR_DISABLE |
869 COH901318_CX_CFG_TC_IRQ_ENABLE |
870 COH901318_CX_CFG_BE_IRQ_ENABLE,
871 .param.ctrl_lli_chained = 0 |
872 COH901318_CX_CTRL_TC_ENABLE |
873 COH901318_CX_CTRL_MASTER_MODE_M1RW |
874 COH901318_CX_CTRL_TCP_ENABLE |
875 COH901318_CX_CTRL_TC_IRQ_DISABLE |
876 COH901318_CX_CTRL_HSP_ENABLE |
877 COH901318_CX_CTRL_HSS_DISABLE |
878 COH901318_CX_CTRL_DDMA_LEGACY,
879 .param.ctrl_lli = 0 |
880 COH901318_CX_CTRL_TC_ENABLE |
881 COH901318_CX_CTRL_MASTER_MODE_M1RW |
882 COH901318_CX_CTRL_TCP_ENABLE |
883 COH901318_CX_CTRL_TC_IRQ_ENABLE |
884 COH901318_CX_CTRL_HSP_ENABLE |
885 COH901318_CX_CTRL_HSS_DISABLE |
886 COH901318_CX_CTRL_DDMA_LEGACY,
887 .param.ctrl_lli_last = 0 |
888 COH901318_CX_CTRL_TC_ENABLE |
889 COH901318_CX_CTRL_MASTER_MODE_M1RW |
890 COH901318_CX_CTRL_TCP_ENABLE |
891 COH901318_CX_CTRL_TC_IRQ_ENABLE |
892 COH901318_CX_CTRL_HSP_ENABLE |
893 COH901318_CX_CTRL_HSS_DISABLE |
894 COH901318_CX_CTRL_DDMA_LEGACY,
895 },
896 {
897 .number = U300_DMA_APEX_TX,
898 .name = "APEX TX",
899 .priority_high = 0,
900 },
901 {
902 .number = U300_DMA_APEX_RX,
903 .name = "APEX RX",
904 .priority_high = 0,
905 },
906 {
907 .number = U300_DMA_PCM_I2S0_TX,
908 .name = "PCM I2S0 TX",
909 .priority_high = 1,
Linus Walleij24dbcd82013-01-04 13:38:18 +0100[diff] [blame]910 .param.config = COH901318_CX_CFG_CH_DISABLE |
911 COH901318_CX_CFG_LCR_DISABLE |
912 COH901318_CX_CFG_TC_IRQ_ENABLE |
913 COH901318_CX_CFG_BE_IRQ_ENABLE,
914 .param.ctrl_lli_chained = 0 |
915 COH901318_CX_CTRL_TC_ENABLE |
916 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
917 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
918 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
919 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
920 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
921 COH901318_CX_CTRL_MASTER_MODE_M1RW |
922 COH901318_CX_CTRL_TCP_DISABLE |
923 COH901318_CX_CTRL_TC_IRQ_DISABLE |
924 COH901318_CX_CTRL_HSP_ENABLE |
925 COH901318_CX_CTRL_HSS_DISABLE |
926 COH901318_CX_CTRL_DDMA_LEGACY |
927 COH901318_CX_CTRL_PRDD_SOURCE,
928 .param.ctrl_lli = 0 |
929 COH901318_CX_CTRL_TC_ENABLE |
930 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
931 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
932 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
933 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
934 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
935 COH901318_CX_CTRL_MASTER_MODE_M1RW |
936 COH901318_CX_CTRL_TCP_ENABLE |
937 COH901318_CX_CTRL_TC_IRQ_DISABLE |
938 COH901318_CX_CTRL_HSP_ENABLE |
939 COH901318_CX_CTRL_HSS_DISABLE |
940 COH901318_CX_CTRL_DDMA_LEGACY |
941 COH901318_CX_CTRL_PRDD_SOURCE,
942 .param.ctrl_lli_last = 0 |
943 COH901318_CX_CTRL_TC_ENABLE |
944 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
945 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
946 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
947 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
948 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
949 COH901318_CX_CTRL_MASTER_MODE_M1RW |
950 COH901318_CX_CTRL_TCP_ENABLE |
951 COH901318_CX_CTRL_TC_IRQ_DISABLE |
952 COH901318_CX_CTRL_HSP_ENABLE |
953 COH901318_CX_CTRL_HSS_DISABLE |
954 COH901318_CX_CTRL_DDMA_LEGACY |
955 COH901318_CX_CTRL_PRDD_SOURCE,
956 },
957 {
958 .number = U300_DMA_PCM_I2S0_RX,
959 .name = "PCM I2S0 RX",
960 .priority_high = 1,
Linus Walleij24dbcd82013-01-04 13:38:18 +0100[diff] [blame]961 .param.config = COH901318_CX_CFG_CH_DISABLE |
962 COH901318_CX_CFG_LCR_DISABLE |
963 COH901318_CX_CFG_TC_IRQ_ENABLE |
964 COH901318_CX_CFG_BE_IRQ_ENABLE,
965 .param.ctrl_lli_chained = 0 |
966 COH901318_CX_CTRL_TC_ENABLE |
967 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
968 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
969 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
970 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
971 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
972 COH901318_CX_CTRL_MASTER_MODE_M1RW |
973 COH901318_CX_CTRL_TCP_DISABLE |
974 COH901318_CX_CTRL_TC_IRQ_DISABLE |
975 COH901318_CX_CTRL_HSP_ENABLE |
976 COH901318_CX_CTRL_HSS_DISABLE |
977 COH901318_CX_CTRL_DDMA_LEGACY |
978 COH901318_CX_CTRL_PRDD_DEST,
979 .param.ctrl_lli = 0 |
980 COH901318_CX_CTRL_TC_ENABLE |
981 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
982 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
983 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
984 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
985 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
986 COH901318_CX_CTRL_MASTER_MODE_M1RW |
987 COH901318_CX_CTRL_TCP_ENABLE |
988 COH901318_CX_CTRL_TC_IRQ_DISABLE |
989 COH901318_CX_CTRL_HSP_ENABLE |
990 COH901318_CX_CTRL_HSS_DISABLE |
991 COH901318_CX_CTRL_DDMA_LEGACY |
992 COH901318_CX_CTRL_PRDD_DEST,
993 .param.ctrl_lli_last = 0 |
994 COH901318_CX_CTRL_TC_ENABLE |
995 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
996 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
997 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
998 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
999 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1000 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1001 COH901318_CX_CTRL_TCP_ENABLE |
1002 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1003 COH901318_CX_CTRL_HSP_ENABLE |
1004 COH901318_CX_CTRL_HSS_DISABLE |
1005 COH901318_CX_CTRL_DDMA_LEGACY |
1006 COH901318_CX_CTRL_PRDD_DEST,
1007 },
1008 {
1009 .number = U300_DMA_PCM_I2S1_TX,
1010 .name = "PCM I2S1 TX",
1011 .priority_high = 1,
Linus Walleij24dbcd82013-01-04 13:38:18 +0100[diff] [blame]1012 .param.config = COH901318_CX_CFG_CH_DISABLE |
1013 COH901318_CX_CFG_LCR_DISABLE |
1014 COH901318_CX_CFG_TC_IRQ_ENABLE |
1015 COH901318_CX_CFG_BE_IRQ_ENABLE,
1016 .param.ctrl_lli_chained = 0 |
1017 COH901318_CX_CTRL_TC_ENABLE |
1018 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1019 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1020 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1021 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1022 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1023 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1024 COH901318_CX_CTRL_TCP_DISABLE |
1025 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1026 COH901318_CX_CTRL_HSP_ENABLE |
1027 COH901318_CX_CTRL_HSS_DISABLE |
1028 COH901318_CX_CTRL_DDMA_LEGACY |
1029 COH901318_CX_CTRL_PRDD_SOURCE,
1030 .param.ctrl_lli = 0 |
1031 COH901318_CX_CTRL_TC_ENABLE |
1032 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1033 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1034 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1035 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1036 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1037 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1038 COH901318_CX_CTRL_TCP_ENABLE |
1039 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1040 COH901318_CX_CTRL_HSP_ENABLE |
1041 COH901318_CX_CTRL_HSS_DISABLE |
1042 COH901318_CX_CTRL_DDMA_LEGACY |
1043 COH901318_CX_CTRL_PRDD_SOURCE,
1044 .param.ctrl_lli_last = 0 |
1045 COH901318_CX_CTRL_TC_ENABLE |
1046 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1047 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1048 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1049 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1050 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1051 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1052 COH901318_CX_CTRL_TCP_ENABLE |
1053 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1054 COH901318_CX_CTRL_HSP_ENABLE |
1055 COH901318_CX_CTRL_HSS_DISABLE |
1056 COH901318_CX_CTRL_DDMA_LEGACY |
1057 COH901318_CX_CTRL_PRDD_SOURCE,
1058 },
1059 {
1060 .number = U300_DMA_PCM_I2S1_RX,
1061 .name = "PCM I2S1 RX",
1062 .priority_high = 1,
Linus Walleij24dbcd82013-01-04 13:38:18 +0100[diff] [blame]1063 .param.config = COH901318_CX_CFG_CH_DISABLE |
1064 COH901318_CX_CFG_LCR_DISABLE |
1065 COH901318_CX_CFG_TC_IRQ_ENABLE |
1066 COH901318_CX_CFG_BE_IRQ_ENABLE,
1067 .param.ctrl_lli_chained = 0 |
1068 COH901318_CX_CTRL_TC_ENABLE |
1069 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1070 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1071 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1072 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1073 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1074 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1075 COH901318_CX_CTRL_TCP_DISABLE |
1076 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1077 COH901318_CX_CTRL_HSP_ENABLE |
1078 COH901318_CX_CTRL_HSS_DISABLE |
1079 COH901318_CX_CTRL_DDMA_LEGACY |
1080 COH901318_CX_CTRL_PRDD_DEST,
1081 .param.ctrl_lli = 0 |
1082 COH901318_CX_CTRL_TC_ENABLE |
1083 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1084 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1085 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1086 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1087 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1088 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1089 COH901318_CX_CTRL_TCP_ENABLE |
1090 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1091 COH901318_CX_CTRL_HSP_ENABLE |
1092 COH901318_CX_CTRL_HSS_DISABLE |
1093 COH901318_CX_CTRL_DDMA_LEGACY |
1094 COH901318_CX_CTRL_PRDD_DEST,
1095 .param.ctrl_lli_last = 0 |
1096 COH901318_CX_CTRL_TC_ENABLE |
1097 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1098 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1099 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1100 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1101 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1102 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1103 COH901318_CX_CTRL_TCP_ENABLE |
1104 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1105 COH901318_CX_CTRL_HSP_ENABLE |
1106 COH901318_CX_CTRL_HSS_DISABLE |
1107 COH901318_CX_CTRL_DDMA_LEGACY |
1108 COH901318_CX_CTRL_PRDD_DEST,
1109 },
1110 {
1111 .number = U300_DMA_XGAM_CDI,
1112 .name = "XGAM CDI",
1113 .priority_high = 0,
1114 },
1115 {
1116 .number = U300_DMA_XGAM_PDI,
1117 .name = "XGAM PDI",
1118 .priority_high = 0,
1119 },
1120 /*
1121 * Don't set up device address, burst count or size of src
1122 * or dst bus for this peripheral - handled by PrimeCell
1123 * DMA extension.
1124 */
1125 {
1126 .number = U300_DMA_SPI_TX,
1127 .name = "SPI TX",
1128 .priority_high = 0,
1129 .param.config = COH901318_CX_CFG_CH_DISABLE |
1130 COH901318_CX_CFG_LCR_DISABLE |
1131 COH901318_CX_CFG_TC_IRQ_ENABLE |
1132 COH901318_CX_CFG_BE_IRQ_ENABLE,
1133 .param.ctrl_lli_chained = 0 |
1134 COH901318_CX_CTRL_TC_ENABLE |
1135 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1136 COH901318_CX_CTRL_TCP_DISABLE |
1137 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1138 COH901318_CX_CTRL_HSP_ENABLE |
1139 COH901318_CX_CTRL_HSS_DISABLE |
1140 COH901318_CX_CTRL_DDMA_LEGACY,
1141 .param.ctrl_lli = 0 |
1142 COH901318_CX_CTRL_TC_ENABLE |
1143 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1144 COH901318_CX_CTRL_TCP_DISABLE |
1145 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1146 COH901318_CX_CTRL_HSP_ENABLE |
1147 COH901318_CX_CTRL_HSS_DISABLE |
1148 COH901318_CX_CTRL_DDMA_LEGACY,
1149 .param.ctrl_lli_last = 0 |
1150 COH901318_CX_CTRL_TC_ENABLE |
1151 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1152 COH901318_CX_CTRL_TCP_DISABLE |
1153 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1154 COH901318_CX_CTRL_HSP_ENABLE |
1155 COH901318_CX_CTRL_HSS_DISABLE |
1156 COH901318_CX_CTRL_DDMA_LEGACY,
1157 },
1158 {
1159 .number = U300_DMA_SPI_RX,
1160 .name = "SPI RX",
1161 .priority_high = 0,
1162 .param.config = COH901318_CX_CFG_CH_DISABLE |
1163 COH901318_CX_CFG_LCR_DISABLE |
1164 COH901318_CX_CFG_TC_IRQ_ENABLE |
1165 COH901318_CX_CFG_BE_IRQ_ENABLE,
1166 .param.ctrl_lli_chained = 0 |
1167 COH901318_CX_CTRL_TC_ENABLE |
1168 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1169 COH901318_CX_CTRL_TCP_DISABLE |
1170 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1171 COH901318_CX_CTRL_HSP_ENABLE |
1172 COH901318_CX_CTRL_HSS_DISABLE |
1173 COH901318_CX_CTRL_DDMA_LEGACY,
1174 .param.ctrl_lli = 0 |
1175 COH901318_CX_CTRL_TC_ENABLE |
1176 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1177 COH901318_CX_CTRL_TCP_DISABLE |
1178 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1179 COH901318_CX_CTRL_HSP_ENABLE |
1180 COH901318_CX_CTRL_HSS_DISABLE |
1181 COH901318_CX_CTRL_DDMA_LEGACY,
1182 .param.ctrl_lli_last = 0 |
1183 COH901318_CX_CTRL_TC_ENABLE |
1184 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1185 COH901318_CX_CTRL_TCP_DISABLE |
1186 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1187 COH901318_CX_CTRL_HSP_ENABLE |
1188 COH901318_CX_CTRL_HSS_DISABLE |
1189 COH901318_CX_CTRL_DDMA_LEGACY,
1190
1191 },
1192 {
1193 .number = U300_DMA_GENERAL_PURPOSE_0,
1194 .name = "GENERAL 00",
1195 .priority_high = 0,
1196
1197 .param.config = flags_memcpy_config,
1198 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1199 .param.ctrl_lli = flags_memcpy_lli,
1200 .param.ctrl_lli_last = flags_memcpy_lli_last,
1201 },
1202 {
1203 .number = U300_DMA_GENERAL_PURPOSE_1,
1204 .name = "GENERAL 01",
1205 .priority_high = 0,
1206
1207 .param.config = flags_memcpy_config,
1208 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1209 .param.ctrl_lli = flags_memcpy_lli,
1210 .param.ctrl_lli_last = flags_memcpy_lli_last,
1211 },
1212 {
1213 .number = U300_DMA_GENERAL_PURPOSE_2,
1214 .name = "GENERAL 02",
1215 .priority_high = 0,
1216
1217 .param.config = flags_memcpy_config,
1218 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1219 .param.ctrl_lli = flags_memcpy_lli,
1220 .param.ctrl_lli_last = flags_memcpy_lli_last,
1221 },
1222 {
1223 .number = U300_DMA_GENERAL_PURPOSE_3,
1224 .name = "GENERAL 03",
1225 .priority_high = 0,
1226
1227 .param.config = flags_memcpy_config,
1228 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1229 .param.ctrl_lli = flags_memcpy_lli,
1230 .param.ctrl_lli_last = flags_memcpy_lli_last,
1231 },
1232 {
1233 .number = U300_DMA_GENERAL_PURPOSE_4,
1234 .name = "GENERAL 04",
1235 .priority_high = 0,
1236
1237 .param.config = flags_memcpy_config,
1238 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1239 .param.ctrl_lli = flags_memcpy_lli,
1240 .param.ctrl_lli_last = flags_memcpy_lli_last,
1241 },
1242 {
1243 .number = U300_DMA_GENERAL_PURPOSE_5,
1244 .name = "GENERAL 05",
1245 .priority_high = 0,
1246
1247 .param.config = flags_memcpy_config,
1248 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1249 .param.ctrl_lli = flags_memcpy_lli,
1250 .param.ctrl_lli_last = flags_memcpy_lli_last,
1251 },
1252 {
1253 .number = U300_DMA_GENERAL_PURPOSE_6,
1254 .name = "GENERAL 06",
1255 .priority_high = 0,
1256
1257 .param.config = flags_memcpy_config,
1258 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1259 .param.ctrl_lli = flags_memcpy_lli,
1260 .param.ctrl_lli_last = flags_memcpy_lli_last,
1261 },
1262 {
1263 .number = U300_DMA_GENERAL_PURPOSE_7,
1264 .name = "GENERAL 07",
1265 .priority_high = 0,
1266
1267 .param.config = flags_memcpy_config,
1268 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1269 .param.ctrl_lli = flags_memcpy_lli,
1270 .param.ctrl_lli_last = flags_memcpy_lli_last,
1271 },
1272 {
1273 .number = U300_DMA_GENERAL_PURPOSE_8,
1274 .name = "GENERAL 08",
1275 .priority_high = 0,
1276
1277 .param.config = flags_memcpy_config,
1278 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1279 .param.ctrl_lli = flags_memcpy_lli,
1280 .param.ctrl_lli_last = flags_memcpy_lli_last,
1281 },
1282 {
1283 .number = U300_DMA_UART1_TX,
1284 .name = "UART1 TX",
1285 .priority_high = 0,
1286 },
1287 {
1288 .number = U300_DMA_UART1_RX,
1289 .name = "UART1 RX",
1290 .priority_high = 0,
1291 }
1292};
1293
1294static struct coh901318_platform coh901318_platform = {
1295 .chans_slave = dma_slave_channels,
1296 .chans_memcpy = dma_memcpy_channels,
1297 .access_memory_state = coh901318_access_memory_state,
1298 .chan_conf = chan_config,
1299 .max_channels = U300_DMA_CHANNELS,
1300};
1301
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1302#define COHC_2_DEV(cohc) (&cohc->chan.dev->device)
1303
1304#ifdef VERBOSE_DEBUG
1305#define COH_DBG(x) ({ if (1) x; 0; })
1306#else
1307#define COH_DBG(x) ({ if (0) x; 0; })
1308#endif
1309
1310struct coh901318_desc {
1311 struct dma_async_tx_descriptor desc;
1312 struct list_head node;
1313 struct scatterlist *sg;
1314 unsigned int sg_len;
Linus Walleijcecd87d2010-03-04 14:31:47 +0100[diff] [blame]1315 struct coh901318_lli *lli;
Vinod Kouldb8196d2011-10-13 22:34:23 +0530[diff] [blame]1316 enum dma_transfer_direction dir;
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1317 unsigned long flags;
Linus Walleijb89243d2011-07-01 16:47:28 +0200[diff] [blame]1318 u32 head_config;
1319 u32 head_ctrl;
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1320};
1321
1322struct coh901318_base {
1323 struct device *dev;
1324 void __iomem *virtbase;
1325 struct coh901318_pool pool;
1326 struct powersave pm;
1327 struct dma_device dma_slave;
1328 struct dma_device dma_memcpy;
1329 struct coh901318_chan *chans;
1330 struct coh901318_platform *platform;
1331};
1332
1333struct coh901318_chan {
1334 spinlock_t lock;
1335 int allocated;
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1336 int id;
1337 int stopped;
1338
1339 struct work_struct free_work;
1340 struct dma_chan chan;
1341
1342 struct tasklet_struct tasklet;
1343
1344 struct list_head active;
1345 struct list_head queue;
1346 struct list_head free;
1347
1348 unsigned long nbr_active_done;
1349 unsigned long busy;
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1350
Linus Walleij9aab4d62013-01-04 13:50:49 +0100[diff] [blame]1351 u32 addr;
1352 u32 ctrl;
Linus Walleij128f9042010-08-04 13:37:53 +0200[diff] [blame]1353
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1354 struct coh901318_base *base;
1355};
1356
1357static void coh901318_list_print(struct coh901318_chan *cohc,
1358 struct coh901318_lli *lli)
1359{
Linus Walleij848ad122010-03-02 14:17:15 -0700[diff] [blame]1360 struct coh901318_lli *l = lli;
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1361 int i = 0;
1362
Linus Walleij848ad122010-03-02 14:17:15 -0700[diff] [blame]1363 while (l) {
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1364 dev_vdbg(COHC_2_DEV(cohc), "i %d, lli %p, ctrl 0x%x, src 0x%x"
Linus Walleij848ad122010-03-02 14:17:15 -0700[diff] [blame]1365 ", dst 0x%x, link 0x%x virt_link_addr 0x%p\n",
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1366 i, l, l->control, l->src_addr, l->dst_addr,
Linus Walleij848ad122010-03-02 14:17:15 -0700[diff] [blame]1367 l->link_addr, l->virt_link_addr);
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1368 i++;
Linus Walleij848ad122010-03-02 14:17:15 -0700[diff] [blame]1369 l = l->virt_link_addr;
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1370 }
1371}
1372
1373#ifdef CONFIG_DEBUG_FS
1374
1375#define COH901318_DEBUGFS_ASSIGN(x, y) (x = y)
1376
1377static struct coh901318_base *debugfs_dma_base;
1378static struct dentry *dma_dentry;
1379
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1380static int coh901318_debugfs_read(struct file *file, char __user *buf,
1381 size_t count, loff_t *f_pos)
1382{
1383 u64 started_channels = debugfs_dma_base->pm.started_channels;
1384 int pool_count = debugfs_dma_base->pool.debugfs_pool_counter;
1385 int i;
1386 int ret = 0;
1387 char *dev_buf;
1388 char *tmp;
1389 int dev_size;
1390
1391 dev_buf = kmalloc(4*1024, GFP_KERNEL);
1392 if (dev_buf == NULL)
1393 goto err_kmalloc;
1394 tmp = dev_buf;
1395
Linus Walleij848ad122010-03-02 14:17:15 -0700[diff] [blame]1396 tmp += sprintf(tmp, "DMA -- enabled dma channels\n");
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1397
1398 for (i = 0; i < debugfs_dma_base->platform->max_channels; i++)
1399 if (started_channels & (1 << i))
1400 tmp += sprintf(tmp, "channel %d\n", i);
1401
1402 tmp += sprintf(tmp, "Pool alloc nbr %d\n", pool_count);
1403 dev_size = tmp - dev_buf;
1404
1405 /* No more to read if offset != 0 */
1406 if (*f_pos > dev_size)
1407 goto out;
1408
1409 if (count > dev_size - *f_pos)
1410 count = dev_size - *f_pos;
1411
1412 if (copy_to_user(buf, dev_buf + *f_pos, count))
1413 ret = -EINVAL;
1414 ret = count;
1415 *f_pos += count;
1416
1417 out:
1418 kfree(dev_buf);
1419 return ret;
1420
1421 err_kmalloc:
1422 return 0;
1423}
1424
1425static const struct file_operations coh901318_debugfs_status_operations = {
1426 .owner = THIS_MODULE,
Stephen Boyd234e3402012-04-05 14:25:11 -0700[diff] [blame]1427 .open = simple_open,
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1428 .read = coh901318_debugfs_read,
Arnd Bergmann6038f372010-08-15 18:52:59 +0200[diff] [blame]1429 .llseek = default_llseek,
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1430};
1431
1432
1433static int __init init_coh901318_debugfs(void)
1434{
1435
1436 dma_dentry = debugfs_create_dir("dma", NULL);
1437
1438 (void) debugfs_create_file("status",
1439 S_IFREG | S_IRUGO,
1440 dma_dentry, NULL,
1441 &coh901318_debugfs_status_operations);
1442 return 0;
1443}
1444
1445static void __exit exit_coh901318_debugfs(void)
1446{
1447 debugfs_remove_recursive(dma_dentry);
1448}
1449
1450module_init(init_coh901318_debugfs);
1451module_exit(exit_coh901318_debugfs);
1452#else
1453
1454#define COH901318_DEBUGFS_ASSIGN(x, y)
1455
1456#endif /* CONFIG_DEBUG_FS */
1457
1458static inline struct coh901318_chan *to_coh901318_chan(struct dma_chan *chan)
1459{
1460 return container_of(chan, struct coh901318_chan, chan);
1461}
1462
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1463static inline const struct coh901318_params *
1464cohc_chan_param(struct coh901318_chan *cohc)
1465{
1466 return &cohc->base->platform->chan_conf[cohc->id].param;
1467}
1468
1469static inline const struct coh_dma_channel *
1470cohc_chan_conf(struct coh901318_chan *cohc)
1471{
1472 return &cohc->base->platform->chan_conf[cohc->id];
1473}
1474
1475static void enable_powersave(struct coh901318_chan *cohc)
1476{
1477 unsigned long flags;
1478 struct powersave *pm = &cohc->base->pm;
1479
1480 spin_lock_irqsave(&pm->lock, flags);
1481
1482 pm->started_channels &= ~(1ULL << cohc->id);
1483
1484 if (!pm->started_channels) {
1485 /* DMA no longer intends to access memory */
1486 cohc->base->platform->access_memory_state(cohc->base->dev,
1487 false);
1488 }
1489
1490 spin_unlock_irqrestore(&pm->lock, flags);
1491}
1492static void disable_powersave(struct coh901318_chan *cohc)
1493{
1494 unsigned long flags;
1495 struct powersave *pm = &cohc->base->pm;
1496
1497 spin_lock_irqsave(&pm->lock, flags);
1498
1499 if (!pm->started_channels) {
1500 /* DMA intends to access memory */
1501 cohc->base->platform->access_memory_state(cohc->base->dev,
1502 true);
1503 }
1504
1505 pm->started_channels |= (1ULL << cohc->id);
1506
1507 spin_unlock_irqrestore(&pm->lock, flags);
1508}
1509
1510static inline int coh901318_set_ctrl(struct coh901318_chan *cohc, u32 control)
1511{
1512 int channel = cohc->id;
1513 void __iomem *virtbase = cohc->base->virtbase;
1514
1515 writel(control,
1516 virtbase + COH901318_CX_CTRL +
1517 COH901318_CX_CTRL_SPACING * channel);
1518 return 0;
1519}
1520
1521static inline int coh901318_set_conf(struct coh901318_chan *cohc, u32 conf)
1522{
1523 int channel = cohc->id;
1524 void __iomem *virtbase = cohc->base->virtbase;
1525
1526 writel(conf,
1527 virtbase + COH901318_CX_CFG +
1528 COH901318_CX_CFG_SPACING*channel);
1529 return 0;
1530}
1531
1532
1533static int coh901318_start(struct coh901318_chan *cohc)
1534{
1535 u32 val;
1536 int channel = cohc->id;
1537 void __iomem *virtbase = cohc->base->virtbase;
1538
1539 disable_powersave(cohc);
1540
1541 val = readl(virtbase + COH901318_CX_CFG +
1542 COH901318_CX_CFG_SPACING * channel);
1543
1544 /* Enable channel */
1545 val |= COH901318_CX_CFG_CH_ENABLE;
1546 writel(val, virtbase + COH901318_CX_CFG +
1547 COH901318_CX_CFG_SPACING * channel);
1548
1549 return 0;
1550}
1551
1552static int coh901318_prep_linked_list(struct coh901318_chan *cohc,
Linus Walleijcecd87d2010-03-04 14:31:47 +0100[diff] [blame]1553 struct coh901318_lli *lli)
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1554{
1555 int channel = cohc->id;
1556 void __iomem *virtbase = cohc->base->virtbase;
1557
1558 BUG_ON(readl(virtbase + COH901318_CX_STAT +
1559 COH901318_CX_STAT_SPACING*channel) &
1560 COH901318_CX_STAT_ACTIVE);
1561
Linus Walleijcecd87d2010-03-04 14:31:47 +0100[diff] [blame]1562 writel(lli->src_addr,
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1563 virtbase + COH901318_CX_SRC_ADDR +
1564 COH901318_CX_SRC_ADDR_SPACING * channel);
1565
Linus Walleijcecd87d2010-03-04 14:31:47 +0100[diff] [blame]1566 writel(lli->dst_addr, virtbase +
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1567 COH901318_CX_DST_ADDR +
1568 COH901318_CX_DST_ADDR_SPACING * channel);
1569
Linus Walleijcecd87d2010-03-04 14:31:47 +0100[diff] [blame]1570 writel(lli->link_addr, virtbase + COH901318_CX_LNK_ADDR +
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1571 COH901318_CX_LNK_ADDR_SPACING * channel);
1572
Linus Walleijcecd87d2010-03-04 14:31:47 +0100[diff] [blame]1573 writel(lli->control, virtbase + COH901318_CX_CTRL +
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1574 COH901318_CX_CTRL_SPACING * channel);
1575
1576 return 0;
1577}
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1578
1579static struct coh901318_desc *
1580coh901318_desc_get(struct coh901318_chan *cohc)
1581{
1582 struct coh901318_desc *desc;
1583
1584 if (list_empty(&cohc->free)) {
1585 /* alloc new desc because we're out of used ones
1586 * TODO: alloc a pile of descs instead of just one,
1587 * avoid many small allocations.
1588 */
Linus Walleijb87108a2010-03-02 14:17:20 -0700[diff] [blame]1589 desc = kzalloc(sizeof(struct coh901318_desc), GFP_NOWAIT);
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1590 if (desc == NULL)
1591 goto out;
1592 INIT_LIST_HEAD(&desc->node);
Linus Walleijb87108a2010-03-02 14:17:20 -0700[diff] [blame]1593 dma_async_tx_descriptor_init(&desc->desc, &cohc->chan);
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1594 } else {
1595 /* Reuse an old desc. */
1596 desc = list_first_entry(&cohc->free,
1597 struct coh901318_desc,
1598 node);
1599 list_del(&desc->node);
Linus Walleijb87108a2010-03-02 14:17:20 -0700[diff] [blame]1600 /* Initialize it a bit so it's not insane */
1601 desc->sg = NULL;
1602 desc->sg_len = 0;
1603 desc->desc.callback = NULL;
1604 desc->desc.callback_param = NULL;
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1605 }
1606
1607 out:
1608 return desc;
1609}
1610
1611static void
1612coh901318_desc_free(struct coh901318_chan *cohc, struct coh901318_desc *cohd)
1613{
1614 list_add_tail(&cohd->node, &cohc->free);
1615}
1616
1617/* call with irq lock held */
1618static void
1619coh901318_desc_submit(struct coh901318_chan *cohc, struct coh901318_desc *desc)
1620{
1621 list_add_tail(&desc->node, &cohc->active);
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1622}
1623
1624static struct coh901318_desc *
1625coh901318_first_active_get(struct coh901318_chan *cohc)
1626{
1627 struct coh901318_desc *d;
1628
1629 if (list_empty(&cohc->active))
1630 return NULL;
1631
1632 d = list_first_entry(&cohc->active,
1633 struct coh901318_desc,
1634 node);
1635 return d;
1636}
1637
1638static void
1639coh901318_desc_remove(struct coh901318_desc *cohd)
1640{
1641 list_del(&cohd->node);
1642}
1643
1644static void
1645coh901318_desc_queue(struct coh901318_chan *cohc, struct coh901318_desc *desc)
1646{
1647 list_add_tail(&desc->node, &cohc->queue);
1648}
1649
1650static struct coh901318_desc *
1651coh901318_first_queued(struct coh901318_chan *cohc)
1652{
1653 struct coh901318_desc *d;
1654
1655 if (list_empty(&cohc->queue))
1656 return NULL;
1657
1658 d = list_first_entry(&cohc->queue,
1659 struct coh901318_desc,
1660 node);
1661 return d;
1662}
1663
Linus Walleij84c84472010-03-04 14:40:30 +0100[diff] [blame]1664static inline u32 coh901318_get_bytes_in_lli(struct coh901318_lli *in_lli)
1665{
1666 struct coh901318_lli *lli = in_lli;
1667 u32 bytes = 0;
1668
1669 while (lli) {
1670 bytes += lli->control & COH901318_CX_CTRL_TC_VALUE_MASK;
1671 lli = lli->virt_link_addr;
1672 }
1673 return bytes;
1674}
1675
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1676/*
Linus Walleij84c84472010-03-04 14:40:30 +0100[diff] [blame]1677 * Get the number of bytes left to transfer on this channel,
1678 * it is unwise to call this before stopping the channel for
1679 * absolute measures, but for a rough guess you can still call
1680 * it.
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1681 */
Linus Walleij07934482010-03-26 16:50:49 -0700[diff] [blame]1682static u32 coh901318_get_bytes_left(struct dma_chan *chan)
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1683{
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1684 struct coh901318_chan *cohc = to_coh901318_chan(chan);
Linus Walleij84c84472010-03-04 14:40:30 +0100[diff] [blame]1685 struct coh901318_desc *cohd;
1686 struct list_head *pos;
1687 unsigned long flags;
1688 u32 left = 0;
1689 int i = 0;
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1690
1691 spin_lock_irqsave(&cohc->lock, flags);
1692
Linus Walleij84c84472010-03-04 14:40:30 +0100[diff] [blame]1693 /*
1694 * If there are many queued jobs, we iterate and add the
1695 * size of them all. We take a special look on the first
1696 * job though, since it is probably active.
1697 */
1698 list_for_each(pos, &cohc->active) {
1699 /*
1700 * The first job in the list will be working on the
1701 * hardware. The job can be stopped but still active,
1702 * so that the transfer counter is somewhere inside
1703 * the buffer.
1704 */
1705 cohd = list_entry(pos, struct coh901318_desc, node);
1706
1707 if (i == 0) {
1708 struct coh901318_lli *lli;
1709 dma_addr_t ladd;
1710
1711 /* Read current transfer count value */
1712 left = readl(cohc->base->virtbase +
1713 COH901318_CX_CTRL +
1714 COH901318_CX_CTRL_SPACING * cohc->id) &
1715 COH901318_CX_CTRL_TC_VALUE_MASK;
1716
1717 /* See if the transfer is linked... */
1718 ladd = readl(cohc->base->virtbase +
1719 COH901318_CX_LNK_ADDR +
1720 COH901318_CX_LNK_ADDR_SPACING *
1721 cohc->id) &
1722 ~COH901318_CX_LNK_LINK_IMMEDIATE;
1723 /* Single transaction */
1724 if (!ladd)
1725 continue;
1726
1727 /*
1728 * Linked transaction, follow the lli, find the
1729 * currently processing lli, and proceed to the next
1730 */
1731 lli = cohd->lli;
1732 while (lli && lli->link_addr != ladd)
1733 lli = lli->virt_link_addr;
1734
1735 if (lli)
1736 lli = lli->virt_link_addr;
1737
1738 /*
1739 * Follow remaining lli links around to count the total
1740 * number of bytes left
1741 */
1742 left += coh901318_get_bytes_in_lli(lli);
1743 } else {
1744 left += coh901318_get_bytes_in_lli(cohd->lli);
1745 }
1746 i++;
1747 }
1748
1749 /* Also count bytes in the queued jobs */
1750 list_for_each(pos, &cohc->queue) {
1751 cohd = list_entry(pos, struct coh901318_desc, node);
1752 left += coh901318_get_bytes_in_lli(cohd->lli);
1753 }
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1754
1755 spin_unlock_irqrestore(&cohc->lock, flags);
1756
Linus Walleij84c84472010-03-04 14:40:30 +0100[diff] [blame]1757 return left;
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1758}
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1759
Linus Walleijc3635c72010-03-26 16:44:01 -0700[diff] [blame]1760/*
1761 * Pauses a transfer without losing data. Enables power save.
1762 * Use this function in conjunction with coh901318_resume.
1763 */
1764static void coh901318_pause(struct dma_chan *chan)
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1765{
1766 u32 val;
1767 unsigned long flags;
1768 struct coh901318_chan *cohc = to_coh901318_chan(chan);
1769 int channel = cohc->id;
1770 void __iomem *virtbase = cohc->base->virtbase;
1771
1772 spin_lock_irqsave(&cohc->lock, flags);
1773
1774 /* Disable channel in HW */
1775 val = readl(virtbase + COH901318_CX_CFG +
1776 COH901318_CX_CFG_SPACING * channel);
1777
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300[diff] [blame]1778 /* Stopping infinite transfer */
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1779 if ((val & COH901318_CX_CTRL_TC_ENABLE) == 0 &&
1780 (val & COH901318_CX_CFG_CH_ENABLE))
1781 cohc->stopped = 1;
1782
1783
1784 val &= ~COH901318_CX_CFG_CH_ENABLE;
1785 /* Enable twice, HW bug work around */
1786 writel(val, virtbase + COH901318_CX_CFG +
1787 COH901318_CX_CFG_SPACING * channel);
1788 writel(val, virtbase + COH901318_CX_CFG +
1789 COH901318_CX_CFG_SPACING * channel);
1790
1791 /* Spin-wait for it to actually go inactive */
1792 while (readl(virtbase + COH901318_CX_STAT+COH901318_CX_STAT_SPACING *
1793 channel) & COH901318_CX_STAT_ACTIVE)
1794 cpu_relax();
1795
1796 /* Check if we stopped an active job */
1797 if ((readl(virtbase + COH901318_CX_CTRL+COH901318_CX_CTRL_SPACING *
1798 channel) & COH901318_CX_CTRL_TC_VALUE_MASK) > 0)
1799 cohc->stopped = 1;
1800
1801 enable_powersave(cohc);
1802
1803 spin_unlock_irqrestore(&cohc->lock, flags);
1804}
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1805
Linus Walleijc3635c72010-03-26 16:44:01 -0700[diff] [blame]1806/* Resumes a transfer that has been stopped via 300_dma_stop(..).
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1807 Power save is handled.
1808*/
Linus Walleijc3635c72010-03-26 16:44:01 -0700[diff] [blame]1809static void coh901318_resume(struct dma_chan *chan)
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1810{
1811 u32 val;
1812 unsigned long flags;
1813 struct coh901318_chan *cohc = to_coh901318_chan(chan);
1814 int channel = cohc->id;
1815
1816 spin_lock_irqsave(&cohc->lock, flags);
1817
1818 disable_powersave(cohc);
1819
1820 if (cohc->stopped) {
1821 /* Enable channel in HW */
1822 val = readl(cohc->base->virtbase + COH901318_CX_CFG +
1823 COH901318_CX_CFG_SPACING * channel);
1824
1825 val |= COH901318_CX_CFG_CH_ENABLE;
1826
1827 writel(val, cohc->base->virtbase + COH901318_CX_CFG +
1828 COH901318_CX_CFG_SPACING*channel);
1829
1830 cohc->stopped = 0;
1831 }
1832
1833 spin_unlock_irqrestore(&cohc->lock, flags);
1834}
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1835
1836bool coh901318_filter_id(struct dma_chan *chan, void *chan_id)
1837{
1838 unsigned int ch_nr = (unsigned int) chan_id;
1839
1840 if (ch_nr == to_coh901318_chan(chan)->id)
1841 return true;
1842
1843 return false;
1844}
1845EXPORT_SYMBOL(coh901318_filter_id);
1846
1847/*
1848 * DMA channel allocation
1849 */
1850static int coh901318_config(struct coh901318_chan *cohc,
1851 struct coh901318_params *param)
1852{
1853 unsigned long flags;
1854 const struct coh901318_params *p;
1855 int channel = cohc->id;
1856 void __iomem *virtbase = cohc->base->virtbase;
1857
1858 spin_lock_irqsave(&cohc->lock, flags);
1859
1860 if (param)
1861 p = param;
1862 else
1863 p = &cohc->base->platform->chan_conf[channel].param;
1864
1865 /* Clear any pending BE or TC interrupt */
1866 if (channel < 32) {
1867 writel(1 << channel, virtbase + COH901318_BE_INT_CLEAR1);
1868 writel(1 << channel, virtbase + COH901318_TC_INT_CLEAR1);
1869 } else {
1870 writel(1 << (channel - 32), virtbase +
1871 COH901318_BE_INT_CLEAR2);
1872 writel(1 << (channel - 32), virtbase +
1873 COH901318_TC_INT_CLEAR2);
1874 }
1875
1876 coh901318_set_conf(cohc, p->config);
1877 coh901318_set_ctrl(cohc, p->ctrl_lli_last);
1878
1879 spin_unlock_irqrestore(&cohc->lock, flags);
1880
1881 return 0;
1882}
1883
1884/* must lock when calling this function
1885 * start queued jobs, if any
1886 * TODO: start all queued jobs in one go
1887 *
1888 * Returns descriptor if queued job is started otherwise NULL.
1889 * If the queue is empty NULL is returned.
1890 */
1891static struct coh901318_desc *coh901318_queue_start(struct coh901318_chan *cohc)
1892{
Linus Walleijcecd87d2010-03-04 14:31:47 +0100[diff] [blame]1893 struct coh901318_desc *cohd;
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1894
Linus Walleijcecd87d2010-03-04 14:31:47 +0100[diff] [blame]1895 /*
1896 * start queued jobs, if any
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1897 * TODO: transmit all queued jobs in one go
1898 */
Linus Walleijcecd87d2010-03-04 14:31:47 +0100[diff] [blame]1899 cohd = coh901318_first_queued(cohc);
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1900
Linus Walleijcecd87d2010-03-04 14:31:47 +0100[diff] [blame]1901 if (cohd != NULL) {
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1902 /* Remove from queue */
Linus Walleijcecd87d2010-03-04 14:31:47 +0100[diff] [blame]1903 coh901318_desc_remove(cohd);
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1904 /* initiate DMA job */
1905 cohc->busy = 1;
1906
Linus Walleijcecd87d2010-03-04 14:31:47 +0100[diff] [blame]1907 coh901318_desc_submit(cohc, cohd);
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1908
Linus Walleijb89243d2011-07-01 16:47:28 +0200[diff] [blame]1909 /* Program the transaction head */
1910 coh901318_set_conf(cohc, cohd->head_config);
1911 coh901318_set_ctrl(cohc, cohd->head_ctrl);
Linus Walleijcecd87d2010-03-04 14:31:47 +0100[diff] [blame]1912 coh901318_prep_linked_list(cohc, cohd->lli);
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1913
Linus Walleijcecd87d2010-03-04 14:31:47 +0100[diff] [blame]1914 /* start dma job on this channel */
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1915 coh901318_start(cohc);
1916
1917 }
1918
Linus Walleijcecd87d2010-03-04 14:31:47 +0100[diff] [blame]1919 return cohd;
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1920}
1921
Linus Walleij848ad122010-03-02 14:17:15 -0700[diff] [blame]1922/*
1923 * This tasklet is called from the interrupt handler to
1924 * handle each descriptor (DMA job) that is sent to a channel.
1925 */
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1926static void dma_tasklet(unsigned long data)
1927{
1928 struct coh901318_chan *cohc = (struct coh901318_chan *) data;
1929 struct coh901318_desc *cohd_fin;
1930 unsigned long flags;
1931 dma_async_tx_callback callback;
1932 void *callback_param;
1933
Linus Walleij848ad122010-03-02 14:17:15 -0700[diff] [blame]1934 dev_vdbg(COHC_2_DEV(cohc), "[%s] chan_id %d"
1935 " nbr_active_done %ld\n", __func__,
1936 cohc->id, cohc->nbr_active_done);
1937
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1938 spin_lock_irqsave(&cohc->lock, flags);
1939
Linus Walleij848ad122010-03-02 14:17:15 -0700[diff] [blame]1940 /* get first active descriptor entry from list */
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1941 cohd_fin = coh901318_first_active_get(cohc);
1942
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1943 if (cohd_fin == NULL)
1944 goto err;
1945
Linus Walleij0b588282010-03-02 14:17:44 -0700[diff] [blame]1946 /* locate callback to client */
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1947 callback = cohd_fin->desc.callback;
1948 callback_param = cohd_fin->desc.callback_param;
1949
Linus Walleij0b588282010-03-02 14:17:44 -0700[diff] [blame]1950 /* sign this job as completed on the channel */
Russell King - ARM Linuxf7fbce02012-03-06 22:35:07 +0000[diff] [blame]1951 dma_cookie_complete(&cohd_fin->desc);
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1952
Linus Walleij0b588282010-03-02 14:17:44 -0700[diff] [blame]1953 /* release the lli allocation and remove the descriptor */
Linus Walleijcecd87d2010-03-04 14:31:47 +0100[diff] [blame]1954 coh901318_lli_free(&cohc->base->pool, &cohd_fin->lli);
Linus Walleij0b588282010-03-02 14:17:44 -0700[diff] [blame]1955
1956 /* return desc to free-list */
1957 coh901318_desc_remove(cohd_fin);
1958 coh901318_desc_free(cohc, cohd_fin);
1959
1960 spin_unlock_irqrestore(&cohc->lock, flags);
1961
1962 /* Call the callback when we're done */
1963 if (callback)
1964 callback(callback_param);
1965
1966 spin_lock_irqsave(&cohc->lock, flags);
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1967
Linus Walleij848ad122010-03-02 14:17:15 -0700[diff] [blame]1968 /*
1969 * If another interrupt fired while the tasklet was scheduling,
1970 * we don't get called twice, so we have this number of active
1971 * counter that keep track of the number of IRQs expected to
1972 * be handled for this channel. If there happen to be more than
1973 * one IRQ to be ack:ed, we simply schedule this tasklet again.
1974 */
Linus Walleij0b588282010-03-02 14:17:44 -0700[diff] [blame]1975 cohc->nbr_active_done--;
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1976 if (cohc->nbr_active_done) {
Linus Walleij848ad122010-03-02 14:17:15 -0700[diff] [blame]1977 dev_dbg(COHC_2_DEV(cohc), "scheduling tasklet again, new IRQs "
1978 "came in while we were scheduling this tasklet\n");
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1979 if (cohc_chan_conf(cohc)->priority_high)
1980 tasklet_hi_schedule(&cohc->tasklet);
1981 else
1982 tasklet_schedule(&cohc->tasklet);
1983 }
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1984
Linus Walleij0b588282010-03-02 14:17:44 -0700[diff] [blame]1985 spin_unlock_irqrestore(&cohc->lock, flags);
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]1986
1987 return;
1988
1989 err:
1990 spin_unlock_irqrestore(&cohc->lock, flags);
1991 dev_err(COHC_2_DEV(cohc), "[%s] No active dma desc\n", __func__);
1992}
1993
1994
1995/* called from interrupt context */
1996static void dma_tc_handle(struct coh901318_chan *cohc)
1997{
Linus Walleijcecd87d2010-03-04 14:31:47 +0100[diff] [blame]1998 /*
1999 * If the channel is not allocated, then we shouldn't have
2000 * any TC interrupts on it.
2001 */
2002 if (!cohc->allocated) {
2003 dev_err(COHC_2_DEV(cohc), "spurious interrupt from "
2004 "unallocated channel\n");
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2005 return;
Linus Walleijcecd87d2010-03-04 14:31:47 +0100[diff] [blame]2006 }
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2007
Linus Walleij0b588282010-03-02 14:17:44 -0700[diff] [blame]2008 spin_lock(&cohc->lock);
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2009
Linus Walleijcecd87d2010-03-04 14:31:47 +0100[diff] [blame]2010 /*
2011 * When we reach this point, at least one queue item
2012 * should have been moved over from cohc->queue to
2013 * cohc->active and run to completion, that is why we're
2014 * getting a terminal count interrupt is it not?
2015 * If you get this BUG() the most probable cause is that
2016 * the individual nodes in the lli chain have IRQ enabled,
2017 * so check your platform config for lli chain ctrl.
2018 */
2019 BUG_ON(list_empty(&cohc->active));
2020
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2021 cohc->nbr_active_done++;
2022
Linus Walleijcecd87d2010-03-04 14:31:47 +0100[diff] [blame]2023 /*
2024 * This attempt to take a job from cohc->queue, put it
2025 * into cohc->active and start it.
2026 */
Linus Walleij0b588282010-03-02 14:17:44 -0700[diff] [blame]2027 if (coh901318_queue_start(cohc) == NULL)
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2028 cohc->busy = 0;
2029
Linus Walleij0b588282010-03-02 14:17:44 -0700[diff] [blame]2030 spin_unlock(&cohc->lock);
2031
Linus Walleijcecd87d2010-03-04 14:31:47 +0100[diff] [blame]2032 /*
2033 * This tasklet will remove items from cohc->active
2034 * and thus terminates them.
2035 */
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2036 if (cohc_chan_conf(cohc)->priority_high)
2037 tasklet_hi_schedule(&cohc->tasklet);
2038 else
2039 tasklet_schedule(&cohc->tasklet);
2040}
2041
2042
2043static irqreturn_t dma_irq_handler(int irq, void *dev_id)
2044{
2045 u32 status1;
2046 u32 status2;
2047 int i;
2048 int ch;
2049 struct coh901318_base *base = dev_id;
2050 struct coh901318_chan *cohc;
2051 void __iomem *virtbase = base->virtbase;
2052
2053 status1 = readl(virtbase + COH901318_INT_STATUS1);
2054 status2 = readl(virtbase + COH901318_INT_STATUS2);
2055
2056 if (unlikely(status1 == 0 && status2 == 0)) {
2057 dev_warn(base->dev, "spurious DMA IRQ from no channel!\n");
2058 return IRQ_HANDLED;
2059 }
2060
2061 /* TODO: consider handle IRQ in tasklet here to
2062 * minimize interrupt latency */
2063
2064 /* Check the first 32 DMA channels for IRQ */
2065 while (status1) {
2066 /* Find first bit set, return as a number. */
2067 i = ffs(status1) - 1;
2068 ch = i;
2069
2070 cohc = &base->chans[ch];
2071 spin_lock(&cohc->lock);
2072
2073 /* Mask off this bit */
2074 status1 &= ~(1 << i);
2075 /* Check the individual channel bits */
2076 if (test_bit(i, virtbase + COH901318_BE_INT_STATUS1)) {
2077 dev_crit(COHC_2_DEV(cohc),
2078 "DMA bus error on channel %d!\n", ch);
2079 BUG_ON(1);
2080 /* Clear BE interrupt */
2081 __set_bit(i, virtbase + COH901318_BE_INT_CLEAR1);
2082 } else {
2083 /* Caused by TC, really? */
2084 if (unlikely(!test_bit(i, virtbase +
2085 COH901318_TC_INT_STATUS1))) {
2086 dev_warn(COHC_2_DEV(cohc),
2087 "ignoring interrupt not caused by terminal count on channel %d\n", ch);
2088 /* Clear TC interrupt */
2089 BUG_ON(1);
2090 __set_bit(i, virtbase + COH901318_TC_INT_CLEAR1);
2091 } else {
2092 /* Enable powersave if transfer has finished */
2093 if (!(readl(virtbase + COH901318_CX_STAT +
2094 COH901318_CX_STAT_SPACING*ch) &
2095 COH901318_CX_STAT_ENABLED)) {
2096 enable_powersave(cohc);
2097 }
2098
2099 /* Must clear TC interrupt before calling
2100 * dma_tc_handle
Justin P. Mattockbc0b44c2011-01-28 11:48:18 -0800[diff] [blame]2101 * in case tc_handle initiate a new dma job
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2102 */
2103 __set_bit(i, virtbase + COH901318_TC_INT_CLEAR1);
2104
2105 dma_tc_handle(cohc);
2106 }
2107 }
2108 spin_unlock(&cohc->lock);
2109 }
2110
2111 /* Check the remaining 32 DMA channels for IRQ */
2112 while (status2) {
2113 /* Find first bit set, return as a number. */
2114 i = ffs(status2) - 1;
2115 ch = i + 32;
2116 cohc = &base->chans[ch];
2117 spin_lock(&cohc->lock);
2118
2119 /* Mask off this bit */
2120 status2 &= ~(1 << i);
2121 /* Check the individual channel bits */
2122 if (test_bit(i, virtbase + COH901318_BE_INT_STATUS2)) {
2123 dev_crit(COHC_2_DEV(cohc),
2124 "DMA bus error on channel %d!\n", ch);
2125 /* Clear BE interrupt */
2126 BUG_ON(1);
2127 __set_bit(i, virtbase + COH901318_BE_INT_CLEAR2);
2128 } else {
2129 /* Caused by TC, really? */
2130 if (unlikely(!test_bit(i, virtbase +
2131 COH901318_TC_INT_STATUS2))) {
2132 dev_warn(COHC_2_DEV(cohc),
2133 "ignoring interrupt not caused by terminal count on channel %d\n", ch);
2134 /* Clear TC interrupt */
2135 __set_bit(i, virtbase + COH901318_TC_INT_CLEAR2);
2136 BUG_ON(1);
2137 } else {
2138 /* Enable powersave if transfer has finished */
2139 if (!(readl(virtbase + COH901318_CX_STAT +
2140 COH901318_CX_STAT_SPACING*ch) &
2141 COH901318_CX_STAT_ENABLED)) {
2142 enable_powersave(cohc);
2143 }
2144 /* Must clear TC interrupt before calling
2145 * dma_tc_handle
Justin P. Mattockbc0b44c2011-01-28 11:48:18 -0800[diff] [blame]2146 * in case tc_handle initiate a new dma job
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2147 */
2148 __set_bit(i, virtbase + COH901318_TC_INT_CLEAR2);
2149
2150 dma_tc_handle(cohc);
2151 }
2152 }
2153 spin_unlock(&cohc->lock);
2154 }
2155
2156 return IRQ_HANDLED;
2157}
2158
2159static int coh901318_alloc_chan_resources(struct dma_chan *chan)
2160{
2161 struct coh901318_chan *cohc = to_coh901318_chan(chan);
Linus Walleij84c84472010-03-04 14:40:30 +0100[diff] [blame]2162 unsigned long flags;
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2163
2164 dev_vdbg(COHC_2_DEV(cohc), "[%s] DMA channel %d\n",
2165 __func__, cohc->id);
2166
2167 if (chan->client_count > 1)
2168 return -EBUSY;
2169
Linus Walleij84c84472010-03-04 14:40:30 +0100[diff] [blame]2170 spin_lock_irqsave(&cohc->lock, flags);
2171
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2172 coh901318_config(cohc, NULL);
2173
2174 cohc->allocated = 1;
Russell King - ARM Linuxd3ee98cdc2012-03-06 22:35:47 +0000[diff] [blame]2175 dma_cookie_init(chan);
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2176
Linus Walleij84c84472010-03-04 14:40:30 +0100[diff] [blame]2177 spin_unlock_irqrestore(&cohc->lock, flags);
2178
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2179 return 1;
2180}
2181
2182static void
2183coh901318_free_chan_resources(struct dma_chan *chan)
2184{
2185 struct coh901318_chan *cohc = to_coh901318_chan(chan);
2186 int channel = cohc->id;
2187 unsigned long flags;
2188
2189 spin_lock_irqsave(&cohc->lock, flags);
2190
2191 /* Disable HW */
2192 writel(0x00000000U, cohc->base->virtbase + COH901318_CX_CFG +
2193 COH901318_CX_CFG_SPACING*channel);
2194 writel(0x00000000U, cohc->base->virtbase + COH901318_CX_CTRL +
2195 COH901318_CX_CTRL_SPACING*channel);
2196
2197 cohc->allocated = 0;
2198
2199 spin_unlock_irqrestore(&cohc->lock, flags);
2200
Linus Walleij05827632010-05-17 16:30:42 -0700[diff] [blame]2201 chan->device->device_control(chan, DMA_TERMINATE_ALL, 0);
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2202}
2203
2204
2205static dma_cookie_t
2206coh901318_tx_submit(struct dma_async_tx_descriptor *tx)
2207{
2208 struct coh901318_desc *cohd = container_of(tx, struct coh901318_desc,
2209 desc);
2210 struct coh901318_chan *cohc = to_coh901318_chan(tx->chan);
2211 unsigned long flags;
Russell King - ARM Linux884485e2012-03-06 22:34:46 +0000[diff] [blame]2212 dma_cookie_t cookie;
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2213
2214 spin_lock_irqsave(&cohc->lock, flags);
Russell King - ARM Linux884485e2012-03-06 22:34:46 +0000[diff] [blame]2215 cookie = dma_cookie_assign(tx);
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2216
2217 coh901318_desc_queue(cohc, cohd);
2218
2219 spin_unlock_irqrestore(&cohc->lock, flags);
2220
Russell King - ARM Linux884485e2012-03-06 22:34:46 +0000[diff] [blame]2221 return cookie;
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2222}
2223
2224static struct dma_async_tx_descriptor *
2225coh901318_prep_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
2226 size_t size, unsigned long flags)
2227{
Linus Walleijcecd87d2010-03-04 14:31:47 +0100[diff] [blame]2228 struct coh901318_lli *lli;
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2229 struct coh901318_desc *cohd;
2230 unsigned long flg;
2231 struct coh901318_chan *cohc = to_coh901318_chan(chan);
2232 int lli_len;
2233 u32 ctrl_last = cohc_chan_param(cohc)->ctrl_lli_last;
Linus Walleijb87108a2010-03-02 14:17:20 -0700[diff] [blame]2234 int ret;
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2235
2236 spin_lock_irqsave(&cohc->lock, flg);
2237
2238 dev_vdbg(COHC_2_DEV(cohc),
2239 "[%s] channel %d src 0x%x dest 0x%x size %d\n",
2240 __func__, cohc->id, src, dest, size);
2241
2242 if (flags & DMA_PREP_INTERRUPT)
2243 /* Trigger interrupt after last lli */
2244 ctrl_last |= COH901318_CX_CTRL_TC_IRQ_ENABLE;
2245
2246 lli_len = size >> MAX_DMA_PACKET_SIZE_SHIFT;
2247 if ((lli_len << MAX_DMA_PACKET_SIZE_SHIFT) < size)
2248 lli_len++;
2249
Linus Walleijcecd87d2010-03-04 14:31:47 +0100[diff] [blame]2250 lli = coh901318_lli_alloc(&cohc->base->pool, lli_len);
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2251
Linus Walleijcecd87d2010-03-04 14:31:47 +0100[diff] [blame]2252 if (lli == NULL)
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2253 goto err;
2254
Linus Walleijb87108a2010-03-02 14:17:20 -0700[diff] [blame]2255 ret = coh901318_lli_fill_memcpy(
Linus Walleijcecd87d2010-03-04 14:31:47 +0100[diff] [blame]2256 &cohc->base->pool, lli, src, size, dest,
Linus Walleijb87108a2010-03-02 14:17:20 -0700[diff] [blame]2257 cohc_chan_param(cohc)->ctrl_lli_chained,
2258 ctrl_last);
2259 if (ret)
2260 goto err;
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2261
Linus Walleijcecd87d2010-03-04 14:31:47 +0100[diff] [blame]2262 COH_DBG(coh901318_list_print(cohc, lli));
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2263
Linus Walleijb87108a2010-03-02 14:17:20 -0700[diff] [blame]2264 /* Pick a descriptor to handle this transfer */
2265 cohd = coh901318_desc_get(cohc);
Linus Walleijcecd87d2010-03-04 14:31:47 +0100[diff] [blame]2266 cohd->lli = lli;
Linus Walleijb87108a2010-03-02 14:17:20 -0700[diff] [blame]2267 cohd->flags = flags;
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2268 cohd->desc.tx_submit = coh901318_tx_submit;
2269
2270 spin_unlock_irqrestore(&cohc->lock, flg);
2271
2272 return &cohd->desc;
2273 err:
2274 spin_unlock_irqrestore(&cohc->lock, flg);
2275 return NULL;
2276}
2277
2278static struct dma_async_tx_descriptor *
2279coh901318_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
Vinod Kouldb8196d2011-10-13 22:34:23 +0530[diff] [blame]2280 unsigned int sg_len, enum dma_transfer_direction direction,
Alexandre Bounine185ecb52012-03-08 15:35:13 -0500[diff] [blame]2281 unsigned long flags, void *context)
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2282{
2283 struct coh901318_chan *cohc = to_coh901318_chan(chan);
Linus Walleijcecd87d2010-03-04 14:31:47 +0100[diff] [blame]2284 struct coh901318_lli *lli;
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2285 struct coh901318_desc *cohd;
Linus Walleij516fd432010-03-02 20:12:46 +0100[diff] [blame]2286 const struct coh901318_params *params;
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2287 struct scatterlist *sg;
2288 int len = 0;
2289 int size;
2290 int i;
2291 u32 ctrl_chained = cohc_chan_param(cohc)->ctrl_lli_chained;
2292 u32 ctrl = cohc_chan_param(cohc)->ctrl_lli;
2293 u32 ctrl_last = cohc_chan_param(cohc)->ctrl_lli_last;
Linus Walleij516fd432010-03-02 20:12:46 +0100[diff] [blame]2294 u32 config;
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2295 unsigned long flg;
Linus Walleij0b588282010-03-02 14:17:44 -0700[diff] [blame]2296 int ret;
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2297
2298 if (!sgl)
2299 goto out;
Lars-Peter Clausenfdaf9c42012-04-25 20:50:52 +0200[diff] [blame]2300 if (sg_dma_len(sgl) == 0)
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2301 goto out;
2302
2303 spin_lock_irqsave(&cohc->lock, flg);
2304
2305 dev_vdbg(COHC_2_DEV(cohc), "[%s] sg_len %d dir %d\n",
2306 __func__, sg_len, direction);
2307
2308 if (flags & DMA_PREP_INTERRUPT)
2309 /* Trigger interrupt after last lli */
2310 ctrl_last |= COH901318_CX_CTRL_TC_IRQ_ENABLE;
2311
Linus Walleij516fd432010-03-02 20:12:46 +0100[diff] [blame]2312 params = cohc_chan_param(cohc);
2313 config = params->config;
Linus Walleij128f9042010-08-04 13:37:53 +0200[diff] [blame]2314 /*
2315 * Add runtime-specific control on top, make
2316 * sure the bits you set per peripheral channel are
2317 * cleared in the default config from the platform.
2318 */
Linus Walleij9aab4d62013-01-04 13:50:49 +0100[diff] [blame]2319 ctrl_chained |= cohc->ctrl;
2320 ctrl_last |= cohc->ctrl;
2321 ctrl |= cohc->ctrl;
Linus Walleij516fd432010-03-02 20:12:46 +0100[diff] [blame]2322
Vinod Kouldb8196d2011-10-13 22:34:23 +0530[diff] [blame]2323 if (direction == DMA_MEM_TO_DEV) {
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2324 u32 tx_flags = COH901318_CX_CTRL_PRDD_SOURCE |
2325 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE;
2326
Linus Walleij516fd432010-03-02 20:12:46 +0100[diff] [blame]2327 config |= COH901318_CX_CFG_RM_MEMORY_TO_PRIMARY;
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2328 ctrl_chained |= tx_flags;
2329 ctrl_last |= tx_flags;
2330 ctrl |= tx_flags;
Vinod Kouldb8196d2011-10-13 22:34:23 +0530[diff] [blame]2331 } else if (direction == DMA_DEV_TO_MEM) {
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2332 u32 rx_flags = COH901318_CX_CTRL_PRDD_DEST |
2333 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE;
2334
Linus Walleij516fd432010-03-02 20:12:46 +0100[diff] [blame]2335 config |= COH901318_CX_CFG_RM_PRIMARY_TO_MEMORY;
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2336 ctrl_chained |= rx_flags;
2337 ctrl_last |= rx_flags;
2338 ctrl |= rx_flags;
2339 } else
2340 goto err_direction;
2341
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2342 /* The dma only supports transmitting packages up to
2343 * MAX_DMA_PACKET_SIZE. Calculate to total number of
2344 * dma elemts required to send the entire sg list
2345 */
2346 for_each_sg(sgl, sg, sg_len, i) {
2347 unsigned int factor;
2348 size = sg_dma_len(sg);
2349
2350 if (size <= MAX_DMA_PACKET_SIZE) {
2351 len++;
2352 continue;
2353 }
2354
2355 factor = size >> MAX_DMA_PACKET_SIZE_SHIFT;
2356 if ((factor << MAX_DMA_PACKET_SIZE_SHIFT) < size)
2357 factor++;
2358
2359 len += factor;
2360 }
2361
Linus Walleij848ad122010-03-02 14:17:15 -0700[diff] [blame]2362 pr_debug("Allocate %d lli:s for this transfer\n", len);
Linus Walleijcecd87d2010-03-04 14:31:47 +0100[diff] [blame]2363 lli = coh901318_lli_alloc(&cohc->base->pool, len);
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2364
Linus Walleijcecd87d2010-03-04 14:31:47 +0100[diff] [blame]2365 if (lli == NULL)
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2366 goto err_dma_alloc;
2367
Linus Walleijcecd87d2010-03-04 14:31:47 +0100[diff] [blame]2368 /* initiate allocated lli list */
2369 ret = coh901318_lli_fill_sg(&cohc->base->pool, lli, sgl, sg_len,
Linus Walleij9aab4d62013-01-04 13:50:49 +0100[diff] [blame]2370 cohc->addr,
Linus Walleij0b588282010-03-02 14:17:44 -0700[diff] [blame]2371 ctrl_chained,
2372 ctrl,
2373 ctrl_last,
2374 direction, COH901318_CX_CTRL_TC_IRQ_ENABLE);
2375 if (ret)
2376 goto err_lli_fill;
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2377
Linus Walleij128f9042010-08-04 13:37:53 +0200[diff] [blame]2378
Linus Walleijcecd87d2010-03-04 14:31:47 +0100[diff] [blame]2379 COH_DBG(coh901318_list_print(cohc, lli));
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2380
Linus Walleijb87108a2010-03-02 14:17:20 -0700[diff] [blame]2381 /* Pick a descriptor to handle this transfer */
2382 cohd = coh901318_desc_get(cohc);
Linus Walleijb89243d2011-07-01 16:47:28 +0200[diff] [blame]2383 cohd->head_config = config;
2384 /*
2385 * Set the default head ctrl for the channel to the one from the
2386 * lli, things may have changed due to odd buffer alignment
2387 * etc.
2388 */
2389 cohd->head_ctrl = lli->control;
Linus Walleijb87108a2010-03-02 14:17:20 -0700[diff] [blame]2390 cohd->dir = direction;
2391 cohd->flags = flags;
2392 cohd->desc.tx_submit = coh901318_tx_submit;
Linus Walleijcecd87d2010-03-04 14:31:47 +0100[diff] [blame]2393 cohd->lli = lli;
Linus Walleijb87108a2010-03-02 14:17:20 -0700[diff] [blame]2394
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2395 spin_unlock_irqrestore(&cohc->lock, flg);
2396
2397 return &cohd->desc;
Linus Walleij0b588282010-03-02 14:17:44 -0700[diff] [blame]2398 err_lli_fill:
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2399 err_dma_alloc:
2400 err_direction:
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2401 spin_unlock_irqrestore(&cohc->lock, flg);
2402 out:
2403 return NULL;
2404}
2405
2406static enum dma_status
Linus Walleij07934482010-03-26 16:50:49 -0700[diff] [blame]2407coh901318_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
2408 struct dma_tx_state *txstate)
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2409{
2410 struct coh901318_chan *cohc = to_coh901318_chan(chan);
Russell King - ARM Linux96a2af42012-03-06 22:35:27 +0000[diff] [blame]2411 enum dma_status ret;
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2412
Russell King - ARM Linux96a2af42012-03-06 22:35:27 +0000[diff] [blame]2413 ret = dma_cookie_status(chan, cookie, txstate);
2414 /* FIXME: should be conditional on ret != DMA_SUCCESS? */
2415 dma_set_residue(txstate, coh901318_get_bytes_left(chan));
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2416
Linus Walleij07934482010-03-26 16:50:49 -0700[diff] [blame]2417 if (ret == DMA_IN_PROGRESS && cohc->stopped)
2418 ret = DMA_PAUSED;
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2419
2420 return ret;
2421}
2422
2423static void
2424coh901318_issue_pending(struct dma_chan *chan)
2425{
2426 struct coh901318_chan *cohc = to_coh901318_chan(chan);
2427 unsigned long flags;
2428
2429 spin_lock_irqsave(&cohc->lock, flags);
2430
Linus Walleijcecd87d2010-03-04 14:31:47 +0100[diff] [blame]2431 /*
2432 * Busy means that pending jobs are already being processed,
2433 * and then there is no point in starting the queue: the
2434 * terminal count interrupt on the channel will take the next
2435 * job on the queue and execute it anyway.
2436 */
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2437 if (!cohc->busy)
2438 coh901318_queue_start(cohc);
2439
2440 spin_unlock_irqrestore(&cohc->lock, flags);
2441}
2442
Linus Walleij128f9042010-08-04 13:37:53 +0200[diff] [blame]2443/*
2444 * Here we wrap in the runtime dma control interface
2445 */
2446struct burst_table {
2447 int burst_8bit;
2448 int burst_16bit;
2449 int burst_32bit;
2450 u32 reg;
2451};
2452
2453static const struct burst_table burst_sizes[] = {
2454 {
2455 .burst_8bit = 64,
2456 .burst_16bit = 32,
2457 .burst_32bit = 16,
2458 .reg = COH901318_CX_CTRL_BURST_COUNT_64_BYTES,
2459 },
2460 {
2461 .burst_8bit = 48,
2462 .burst_16bit = 24,
2463 .burst_32bit = 12,
2464 .reg = COH901318_CX_CTRL_BURST_COUNT_48_BYTES,
2465 },
2466 {
2467 .burst_8bit = 32,
2468 .burst_16bit = 16,
2469 .burst_32bit = 8,
2470 .reg = COH901318_CX_CTRL_BURST_COUNT_32_BYTES,
2471 },
2472 {
2473 .burst_8bit = 16,
2474 .burst_16bit = 8,
2475 .burst_32bit = 4,
2476 .reg = COH901318_CX_CTRL_BURST_COUNT_16_BYTES,
2477 },
2478 {
2479 .burst_8bit = 8,
2480 .burst_16bit = 4,
2481 .burst_32bit = 2,
2482 .reg = COH901318_CX_CTRL_BURST_COUNT_8_BYTES,
2483 },
2484 {
2485 .burst_8bit = 4,
2486 .burst_16bit = 2,
2487 .burst_32bit = 1,
2488 .reg = COH901318_CX_CTRL_BURST_COUNT_4_BYTES,
2489 },
2490 {
2491 .burst_8bit = 2,
2492 .burst_16bit = 1,
2493 .burst_32bit = 0,
2494 .reg = COH901318_CX_CTRL_BURST_COUNT_2_BYTES,
2495 },
2496 {
2497 .burst_8bit = 1,
2498 .burst_16bit = 0,
2499 .burst_32bit = 0,
2500 .reg = COH901318_CX_CTRL_BURST_COUNT_1_BYTE,
2501 },
2502};
2503
2504static void coh901318_dma_set_runtimeconfig(struct dma_chan *chan,
2505 struct dma_slave_config *config)
2506{
2507 struct coh901318_chan *cohc = to_coh901318_chan(chan);
2508 dma_addr_t addr;
2509 enum dma_slave_buswidth addr_width;
2510 u32 maxburst;
Linus Walleij9aab4d62013-01-04 13:50:49 +0100[diff] [blame]2511 u32 ctrl = 0;
Linus Walleij128f9042010-08-04 13:37:53 +0200[diff] [blame]2512 int i = 0;
2513
2514 /* We only support mem to per or per to mem transfers */
Vinod Kouldb8196d2011-10-13 22:34:23 +0530[diff] [blame]2515 if (config->direction == DMA_DEV_TO_MEM) {
Linus Walleij128f9042010-08-04 13:37:53 +0200[diff] [blame]2516 addr = config->src_addr;
2517 addr_width = config->src_addr_width;
2518 maxburst = config->src_maxburst;
Vinod Kouldb8196d2011-10-13 22:34:23 +0530[diff] [blame]2519 } else if (config->direction == DMA_MEM_TO_DEV) {
Linus Walleij128f9042010-08-04 13:37:53 +0200[diff] [blame]2520 addr = config->dst_addr;
2521 addr_width = config->dst_addr_width;
2522 maxburst = config->dst_maxburst;
2523 } else {
2524 dev_err(COHC_2_DEV(cohc), "illegal channel mode\n");
2525 return;
2526 }
2527
2528 dev_dbg(COHC_2_DEV(cohc), "configure channel for %d byte transfers\n",
2529 addr_width);
2530 switch (addr_width) {
2531 case DMA_SLAVE_BUSWIDTH_1_BYTE:
Linus Walleij9aab4d62013-01-04 13:50:49 +0100[diff] [blame]2532 ctrl |=
Linus Walleij128f9042010-08-04 13:37:53 +0200[diff] [blame]2533 COH901318_CX_CTRL_SRC_BUS_SIZE_8_BITS |
2534 COH901318_CX_CTRL_DST_BUS_SIZE_8_BITS;
2535
2536 while (i < ARRAY_SIZE(burst_sizes)) {
2537 if (burst_sizes[i].burst_8bit <= maxburst)
2538 break;
2539 i++;
2540 }
2541
2542 break;
2543 case DMA_SLAVE_BUSWIDTH_2_BYTES:
Linus Walleij9aab4d62013-01-04 13:50:49 +0100[diff] [blame]2544 ctrl |=
Linus Walleij128f9042010-08-04 13:37:53 +0200[diff] [blame]2545 COH901318_CX_CTRL_SRC_BUS_SIZE_16_BITS |
2546 COH901318_CX_CTRL_DST_BUS_SIZE_16_BITS;
2547
2548 while (i < ARRAY_SIZE(burst_sizes)) {
2549 if (burst_sizes[i].burst_16bit <= maxburst)
2550 break;
2551 i++;
2552 }
2553
2554 break;
2555 case DMA_SLAVE_BUSWIDTH_4_BYTES:
2556 /* Direction doesn't matter here, it's 32/32 bits */
Linus Walleij9aab4d62013-01-04 13:50:49 +0100[diff] [blame]2557 ctrl |=
Linus Walleij128f9042010-08-04 13:37:53 +0200[diff] [blame]2558 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
2559 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS;
2560
2561 while (i < ARRAY_SIZE(burst_sizes)) {
2562 if (burst_sizes[i].burst_32bit <= maxburst)
2563 break;
2564 i++;
2565 }
2566
2567 break;
2568 default:
2569 dev_err(COHC_2_DEV(cohc),
2570 "bad runtimeconfig: alien address width\n");
2571 return;
2572 }
2573
Linus Walleij9aab4d62013-01-04 13:50:49 +0100[diff] [blame]2574 ctrl |= burst_sizes[i].reg;
Linus Walleij128f9042010-08-04 13:37:53 +0200[diff] [blame]2575 dev_dbg(COHC_2_DEV(cohc),
2576 "selected burst size %d bytes for address width %d bytes, maxburst %d\n",
2577 burst_sizes[i].burst_8bit, addr_width, maxburst);
2578
Linus Walleij9aab4d62013-01-04 13:50:49 +0100[diff] [blame]2579 cohc->addr = addr;
2580 cohc->ctrl = ctrl;
Linus Walleij128f9042010-08-04 13:37:53 +0200[diff] [blame]2581}
2582
Linus Walleijc3635c72010-03-26 16:44:01 -0700[diff] [blame]2583static int
Linus Walleij05827632010-05-17 16:30:42 -0700[diff] [blame]2584coh901318_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
2585 unsigned long arg)
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2586{
2587 unsigned long flags;
2588 struct coh901318_chan *cohc = to_coh901318_chan(chan);
2589 struct coh901318_desc *cohd;
2590 void __iomem *virtbase = cohc->base->virtbase;
2591
Linus Walleij128f9042010-08-04 13:37:53 +0200[diff] [blame]2592 if (cmd == DMA_SLAVE_CONFIG) {
2593 struct dma_slave_config *config =
2594 (struct dma_slave_config *) arg;
2595
2596 coh901318_dma_set_runtimeconfig(chan, config);
2597 return 0;
2598 }
2599
Linus Walleijc3635c72010-03-26 16:44:01 -0700[diff] [blame]2600 if (cmd == DMA_PAUSE) {
2601 coh901318_pause(chan);
2602 return 0;
2603 }
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2604
Linus Walleijc3635c72010-03-26 16:44:01 -0700[diff] [blame]2605 if (cmd == DMA_RESUME) {
2606 coh901318_resume(chan);
2607 return 0;
2608 }
2609
2610 if (cmd != DMA_TERMINATE_ALL)
2611 return -ENXIO;
2612
2613 /* The remainder of this function terminates the transfer */
2614 coh901318_pause(chan);
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2615 spin_lock_irqsave(&cohc->lock, flags);
2616
2617 /* Clear any pending BE or TC interrupt */
2618 if (cohc->id < 32) {
2619 writel(1 << cohc->id, virtbase + COH901318_BE_INT_CLEAR1);
2620 writel(1 << cohc->id, virtbase + COH901318_TC_INT_CLEAR1);
2621 } else {
2622 writel(1 << (cohc->id - 32), virtbase +
2623 COH901318_BE_INT_CLEAR2);
2624 writel(1 << (cohc->id - 32), virtbase +
2625 COH901318_TC_INT_CLEAR2);
2626 }
2627
2628 enable_powersave(cohc);
2629
2630 while ((cohd = coh901318_first_active_get(cohc))) {
2631 /* release the lli allocation*/
Linus Walleijcecd87d2010-03-04 14:31:47 +0100[diff] [blame]2632 coh901318_lli_free(&cohc->base->pool, &cohd->lli);
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2633
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2634 /* return desc to free-list */
Linus Walleij848ad122010-03-02 14:17:15 -0700[diff] [blame]2635 coh901318_desc_remove(cohd);
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2636 coh901318_desc_free(cohc, cohd);
2637 }
2638
2639 while ((cohd = coh901318_first_queued(cohc))) {
2640 /* release the lli allocation*/
Linus Walleijcecd87d2010-03-04 14:31:47 +0100[diff] [blame]2641 coh901318_lli_free(&cohc->base->pool, &cohd->lli);
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2642
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2643 /* return desc to free-list */
Linus Walleij848ad122010-03-02 14:17:15 -0700[diff] [blame]2644 coh901318_desc_remove(cohd);
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2645 coh901318_desc_free(cohc, cohd);
2646 }
2647
2648
2649 cohc->nbr_active_done = 0;
2650 cohc->busy = 0;
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2651
2652 spin_unlock_irqrestore(&cohc->lock, flags);
Linus Walleijc3635c72010-03-26 16:44:01 -0700[diff] [blame]2653
2654 return 0;
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2655}
Linus Walleij128f9042010-08-04 13:37:53 +0200[diff] [blame]2656
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2657void coh901318_base_init(struct dma_device *dma, const int *pick_chans,
2658 struct coh901318_base *base)
2659{
2660 int chans_i;
2661 int i = 0;
2662 struct coh901318_chan *cohc;
2663
2664 INIT_LIST_HEAD(&dma->channels);
2665
2666 for (chans_i = 0; pick_chans[chans_i] != -1; chans_i += 2) {
2667 for (i = pick_chans[chans_i]; i <= pick_chans[chans_i+1]; i++) {
2668 cohc = &base->chans[i];
2669
2670 cohc->base = base;
2671 cohc->chan.device = dma;
2672 cohc->id = i;
2673
2674 /* TODO: do we really need this lock if only one
2675 * client is connected to each channel?
2676 */
2677
2678 spin_lock_init(&cohc->lock);
2679
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2680 cohc->nbr_active_done = 0;
2681 cohc->busy = 0;
2682 INIT_LIST_HEAD(&cohc->free);
2683 INIT_LIST_HEAD(&cohc->active);
2684 INIT_LIST_HEAD(&cohc->queue);
2685
2686 tasklet_init(&cohc->tasklet, dma_tasklet,
2687 (unsigned long) cohc);
2688
2689 list_add_tail(&cohc->chan.device_node,
2690 &dma->channels);
2691 }
2692 }
2693}
2694
2695static int __init coh901318_probe(struct platform_device *pdev)
2696{
2697 int err = 0;
2698 struct coh901318_platform *pdata;
2699 struct coh901318_base *base;
2700 int irq;
2701 struct resource *io;
2702
2703 io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2704 if (!io)
Linus Walleijf7ceb362012-06-12 20:19:24 +0200[diff] [blame]2705 return -ENODEV;
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2706
2707 /* Map DMA controller registers to virtual memory */
Linus Walleijf7ceb362012-06-12 20:19:24 +0200[diff] [blame]2708 if (devm_request_mem_region(&pdev->dev,
2709 io->start,
2710 resource_size(io),
2711 pdev->dev.driver->name) == NULL)
2712 return -ENOMEM;
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2713
Linus Walleij24dbcd82013-01-04 13:38:18 +0100[diff] [blame]2714 pdata = &coh901318_platform,
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2715
Linus Walleijf7ceb362012-06-12 20:19:24 +0200[diff] [blame]2716 base = devm_kzalloc(&pdev->dev,
2717 ALIGN(sizeof(struct coh901318_base), 4) +
2718 pdata->max_channels *
2719 sizeof(struct coh901318_chan),
2720 GFP_KERNEL);
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2721 if (!base)
Linus Walleijf7ceb362012-06-12 20:19:24 +0200[diff] [blame]2722 return -ENOMEM;
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2723
2724 base->chans = ((void *)base) + ALIGN(sizeof(struct coh901318_base), 4);
2725
Linus Walleijf7ceb362012-06-12 20:19:24 +0200[diff] [blame]2726 base->virtbase = devm_ioremap(&pdev->dev, io->start, resource_size(io));
2727 if (!base->virtbase)
2728 return -ENOMEM;
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2729
2730 base->dev = &pdev->dev;
2731 base->platform = pdata;
2732 spin_lock_init(&base->pm.lock);
2733 base->pm.started_channels = 0;
2734
2735 COH901318_DEBUGFS_ASSIGN(debugfs_dma_base, base);
2736
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2737 irq = platform_get_irq(pdev, 0);
2738 if (irq < 0)
Linus Walleijf7ceb362012-06-12 20:19:24 +0200[diff] [blame]2739 return irq;
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2740
Linus Walleijf7ceb362012-06-12 20:19:24 +0200[diff] [blame]2741 err = devm_request_irq(&pdev->dev, irq, dma_irq_handler, IRQF_DISABLED,
2742 "coh901318", base);
2743 if (err)
2744 return err;
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2745
2746 err = coh901318_pool_create(&base->pool, &pdev->dev,
2747 sizeof(struct coh901318_lli),
2748 32);
2749 if (err)
Linus Walleijf7ceb362012-06-12 20:19:24 +0200[diff] [blame]2750 return err;
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2751
2752 /* init channels for device transfers */
2753 coh901318_base_init(&base->dma_slave, base->platform->chans_slave,
2754 base);
2755
2756 dma_cap_zero(base->dma_slave.cap_mask);
2757 dma_cap_set(DMA_SLAVE, base->dma_slave.cap_mask);
2758
2759 base->dma_slave.device_alloc_chan_resources = coh901318_alloc_chan_resources;
2760 base->dma_slave.device_free_chan_resources = coh901318_free_chan_resources;
2761 base->dma_slave.device_prep_slave_sg = coh901318_prep_slave_sg;
Linus Walleij07934482010-03-26 16:50:49 -0700[diff] [blame]2762 base->dma_slave.device_tx_status = coh901318_tx_status;
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2763 base->dma_slave.device_issue_pending = coh901318_issue_pending;
Linus Walleijc3635c72010-03-26 16:44:01 -0700[diff] [blame]2764 base->dma_slave.device_control = coh901318_control;
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2765 base->dma_slave.dev = &pdev->dev;
2766
2767 err = dma_async_device_register(&base->dma_slave);
2768
2769 if (err)
2770 goto err_register_slave;
2771
2772 /* init channels for memcpy */
2773 coh901318_base_init(&base->dma_memcpy, base->platform->chans_memcpy,
2774 base);
2775
2776 dma_cap_zero(base->dma_memcpy.cap_mask);
2777 dma_cap_set(DMA_MEMCPY, base->dma_memcpy.cap_mask);
2778
2779 base->dma_memcpy.device_alloc_chan_resources = coh901318_alloc_chan_resources;
2780 base->dma_memcpy.device_free_chan_resources = coh901318_free_chan_resources;
2781 base->dma_memcpy.device_prep_dma_memcpy = coh901318_prep_memcpy;
Linus Walleij07934482010-03-26 16:50:49 -0700[diff] [blame]2782 base->dma_memcpy.device_tx_status = coh901318_tx_status;
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2783 base->dma_memcpy.device_issue_pending = coh901318_issue_pending;
Linus Walleijc3635c72010-03-26 16:44:01 -0700[diff] [blame]2784 base->dma_memcpy.device_control = coh901318_control;
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2785 base->dma_memcpy.dev = &pdev->dev;
Linus Walleij516fd432010-03-02 20:12:46 +0100[diff] [blame]2786 /*
2787 * This controller can only access address at even 32bit boundaries,
2788 * i.e. 2^2
2789 */
2790 base->dma_memcpy.copy_align = 2;
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2791 err = dma_async_device_register(&base->dma_memcpy);
2792
2793 if (err)
2794 goto err_register_memcpy;
2795
Linus Walleijf7ceb362012-06-12 20:19:24 +0200[diff] [blame]2796 platform_set_drvdata(pdev, base);
Linus Walleij848ad122010-03-02 14:17:15 -0700[diff] [blame]2797 dev_info(&pdev->dev, "Initialized COH901318 DMA on virtual base 0x%08x\n",
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2798 (u32) base->virtbase);
2799
2800 return err;
2801
2802 err_register_memcpy:
2803 dma_async_device_unregister(&base->dma_slave);
2804 err_register_slave:
2805 coh901318_pool_destroy(&base->pool);
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2806 return err;
2807}
2808
2809static int __exit coh901318_remove(struct platform_device *pdev)
2810{
2811 struct coh901318_base *base = platform_get_drvdata(pdev);
2812
2813 dma_async_device_unregister(&base->dma_memcpy);
2814 dma_async_device_unregister(&base->dma_slave);
2815 coh901318_pool_destroy(&base->pool);
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2816 return 0;
2817}
2818
2819
2820static struct platform_driver coh901318_driver = {
2821 .remove = __exit_p(coh901318_remove),
2822 .driver = {
2823 .name = "coh901318",
2824 },
2825};
2826
2827int __init coh901318_init(void)
2828{
2829 return platform_driver_probe(&coh901318_driver, coh901318_probe);
2830}
Linus Walleija0eb2212011-05-18 14:18:57 +0200[diff] [blame]2831subsys_initcall(coh901318_init);
Linus Walleij61f135b2009-11-19 19:49:17 +0100[diff] [blame]2832
2833void __exit coh901318_exit(void)
2834{
2835 platform_driver_unregister(&coh901318_driver);
2836}
2837module_exit(coh901318_exit);
2838
2839MODULE_LICENSE("GPL");
2840MODULE_AUTHOR("Per Friden");