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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * sata_nv.c - NVIDIA nForce SATA
3 *
4 * Copyright 2004 NVIDIA Corp. All rights reserved.
5 * Copyright 2004 Andrew Chew
6 *
Linus Torvalds1da177e2005-04-16 15:20:36 -07007 *
Jeff Garzikaa7e16d2005-08-29 15:12:56 -04008 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2, or (at your option)
11 * any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; see the file COPYING. If not, write to
20 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
Linus Torvalds1da177e2005-04-16 15:20:36 -070021 *
Jeff Garzikaf36d7f2005-08-28 20:18:39 -040022 *
23 * libata documentation is available via 'make {ps|pdf}docs',
24 * as Documentation/DocBook/libata.*
25 *
26 * No hardware documentation available outside of NVIDIA.
27 * This driver programs the NVIDIA SATA controller in a similar
28 * fashion as with other PCI IDE BMDMA controllers, with a few
29 * NV-specific details such as register offsets, SATA phy location,
30 * hotplug info, etc.
31 *
Robert Hancockfbbb2622006-10-27 19:08:41 -070032 * CK804/MCP04 controllers support an alternate programming interface
33 * similar to the ADMA specification (with some modifications).
34 * This allows the use of NCQ. Non-DMA-mapped ATA commands are still
35 * sent through the legacy interface.
36 *
Linus Torvalds1da177e2005-04-16 15:20:36 -070037 */
38
Linus Torvalds1da177e2005-04-16 15:20:36 -070039#include <linux/kernel.h>
40#include <linux/module.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090041#include <linux/gfp.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070042#include <linux/pci.h>
43#include <linux/init.h>
44#include <linux/blkdev.h>
45#include <linux/delay.h>
46#include <linux/interrupt.h>
Jeff Garzika9524a72005-10-30 14:39:11 -050047#include <linux/device.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070048#include <scsi/scsi_host.h>
Robert Hancockfbbb2622006-10-27 19:08:41 -070049#include <scsi/scsi_device.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070050#include <linux/libata.h>
51
52#define DRV_NAME "sata_nv"
Jeff Garzik2a3103c2007-08-31 04:54:06 -040053#define DRV_VERSION "3.5"
Robert Hancockfbbb2622006-10-27 19:08:41 -070054
55#define NV_ADMA_DMA_BOUNDARY 0xffffffffUL
Linus Torvalds1da177e2005-04-16 15:20:36 -070056
Jeff Garzik10ad05d2006-03-22 23:50:50 -050057enum {
Tejun Heo0d5ff562007-02-01 15:06:36 +090058 NV_MMIO_BAR = 5,
59
Jeff Garzik10ad05d2006-03-22 23:50:50 -050060 NV_PORTS = 2,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +010061 NV_PIO_MASK = ATA_PIO4,
62 NV_MWDMA_MASK = ATA_MWDMA2,
63 NV_UDMA_MASK = ATA_UDMA6,
Jeff Garzik10ad05d2006-03-22 23:50:50 -050064 NV_PORT0_SCR_REG_OFFSET = 0x00,
65 NV_PORT1_SCR_REG_OFFSET = 0x40,
Linus Torvalds1da177e2005-04-16 15:20:36 -070066
Tejun Heo27e4b272006-06-17 15:49:55 +090067 /* INT_STATUS/ENABLE */
Jeff Garzik10ad05d2006-03-22 23:50:50 -050068 NV_INT_STATUS = 0x10,
Jeff Garzik10ad05d2006-03-22 23:50:50 -050069 NV_INT_ENABLE = 0x11,
Tejun Heo27e4b272006-06-17 15:49:55 +090070 NV_INT_STATUS_CK804 = 0x440,
Jeff Garzik10ad05d2006-03-22 23:50:50 -050071 NV_INT_ENABLE_CK804 = 0x441,
Linus Torvalds1da177e2005-04-16 15:20:36 -070072
Tejun Heo27e4b272006-06-17 15:49:55 +090073 /* INT_STATUS/ENABLE bits */
74 NV_INT_DEV = 0x01,
75 NV_INT_PM = 0x02,
76 NV_INT_ADDED = 0x04,
77 NV_INT_REMOVED = 0x08,
78
79 NV_INT_PORT_SHIFT = 4, /* each port occupies 4 bits */
80
Tejun Heo39f87582006-06-17 15:49:56 +090081 NV_INT_ALL = 0x0f,
Tejun Heo5a44eff2006-06-17 15:49:56 +090082 NV_INT_MASK = NV_INT_DEV |
83 NV_INT_ADDED | NV_INT_REMOVED,
Tejun Heo39f87582006-06-17 15:49:56 +090084
Tejun Heo27e4b272006-06-17 15:49:55 +090085 /* INT_CONFIG */
Jeff Garzik10ad05d2006-03-22 23:50:50 -050086 NV_INT_CONFIG = 0x12,
87 NV_INT_CONFIG_METHD = 0x01, // 0 = INT, 1 = SMI
Linus Torvalds1da177e2005-04-16 15:20:36 -070088
Jeff Garzik10ad05d2006-03-22 23:50:50 -050089 // For PCI config register 20
90 NV_MCP_SATA_CFG_20 = 0x50,
91 NV_MCP_SATA_CFG_20_SATA_SPACE_EN = 0x04,
Robert Hancockfbbb2622006-10-27 19:08:41 -070092 NV_MCP_SATA_CFG_20_PORT0_EN = (1 << 17),
93 NV_MCP_SATA_CFG_20_PORT1_EN = (1 << 16),
94 NV_MCP_SATA_CFG_20_PORT0_PWB_EN = (1 << 14),
95 NV_MCP_SATA_CFG_20_PORT1_PWB_EN = (1 << 12),
96
97 NV_ADMA_MAX_CPBS = 32,
98 NV_ADMA_CPB_SZ = 128,
99 NV_ADMA_APRD_SZ = 16,
100 NV_ADMA_SGTBL_LEN = (1024 - NV_ADMA_CPB_SZ) /
101 NV_ADMA_APRD_SZ,
102 NV_ADMA_SGTBL_TOTAL_LEN = NV_ADMA_SGTBL_LEN + 5,
103 NV_ADMA_SGTBL_SZ = NV_ADMA_SGTBL_LEN * NV_ADMA_APRD_SZ,
104 NV_ADMA_PORT_PRIV_DMA_SZ = NV_ADMA_MAX_CPBS *
105 (NV_ADMA_CPB_SZ + NV_ADMA_SGTBL_SZ),
106
107 /* BAR5 offset to ADMA general registers */
108 NV_ADMA_GEN = 0x400,
109 NV_ADMA_GEN_CTL = 0x00,
110 NV_ADMA_NOTIFIER_CLEAR = 0x30,
111
112 /* BAR5 offset to ADMA ports */
113 NV_ADMA_PORT = 0x480,
114
115 /* size of ADMA port register space */
116 NV_ADMA_PORT_SIZE = 0x100,
117
118 /* ADMA port registers */
119 NV_ADMA_CTL = 0x40,
120 NV_ADMA_CPB_COUNT = 0x42,
121 NV_ADMA_NEXT_CPB_IDX = 0x43,
122 NV_ADMA_STAT = 0x44,
123 NV_ADMA_CPB_BASE_LOW = 0x48,
124 NV_ADMA_CPB_BASE_HIGH = 0x4C,
125 NV_ADMA_APPEND = 0x50,
126 NV_ADMA_NOTIFIER = 0x68,
127 NV_ADMA_NOTIFIER_ERROR = 0x6C,
128
129 /* NV_ADMA_CTL register bits */
130 NV_ADMA_CTL_HOTPLUG_IEN = (1 << 0),
131 NV_ADMA_CTL_CHANNEL_RESET = (1 << 5),
132 NV_ADMA_CTL_GO = (1 << 7),
133 NV_ADMA_CTL_AIEN = (1 << 8),
134 NV_ADMA_CTL_READ_NON_COHERENT = (1 << 11),
135 NV_ADMA_CTL_WRITE_NON_COHERENT = (1 << 12),
136
137 /* CPB response flag bits */
138 NV_CPB_RESP_DONE = (1 << 0),
139 NV_CPB_RESP_ATA_ERR = (1 << 3),
140 NV_CPB_RESP_CMD_ERR = (1 << 4),
141 NV_CPB_RESP_CPB_ERR = (1 << 7),
142
143 /* CPB control flag bits */
144 NV_CPB_CTL_CPB_VALID = (1 << 0),
145 NV_CPB_CTL_QUEUE = (1 << 1),
146 NV_CPB_CTL_APRD_VALID = (1 << 2),
147 NV_CPB_CTL_IEN = (1 << 3),
148 NV_CPB_CTL_FPDMA = (1 << 4),
149
150 /* APRD flags */
151 NV_APRD_WRITE = (1 << 1),
152 NV_APRD_END = (1 << 2),
153 NV_APRD_CONT = (1 << 3),
154
155 /* NV_ADMA_STAT flags */
156 NV_ADMA_STAT_TIMEOUT = (1 << 0),
157 NV_ADMA_STAT_HOTUNPLUG = (1 << 1),
158 NV_ADMA_STAT_HOTPLUG = (1 << 2),
159 NV_ADMA_STAT_CPBERR = (1 << 4),
160 NV_ADMA_STAT_SERROR = (1 << 5),
161 NV_ADMA_STAT_CMD_COMPLETE = (1 << 6),
162 NV_ADMA_STAT_IDLE = (1 << 8),
163 NV_ADMA_STAT_LEGACY = (1 << 9),
164 NV_ADMA_STAT_STOPPED = (1 << 10),
165 NV_ADMA_STAT_DONE = (1 << 12),
166 NV_ADMA_STAT_ERR = NV_ADMA_STAT_CPBERR |
Jeff Garzik2dcb4072007-10-19 06:42:56 -0400167 NV_ADMA_STAT_TIMEOUT,
Robert Hancockfbbb2622006-10-27 19:08:41 -0700168
169 /* port flags */
170 NV_ADMA_PORT_REGISTER_MODE = (1 << 0),
Robert Hancock2dec7552006-11-26 14:20:19 -0600171 NV_ADMA_ATAPI_SETUP_COMPLETE = (1 << 1),
Robert Hancockfbbb2622006-10-27 19:08:41 -0700172
Kuan Luof140f0f2007-10-15 15:16:53 -0400173 /* MCP55 reg offset */
174 NV_CTL_MCP55 = 0x400,
175 NV_INT_STATUS_MCP55 = 0x440,
176 NV_INT_ENABLE_MCP55 = 0x444,
177 NV_NCQ_REG_MCP55 = 0x448,
178
179 /* MCP55 */
180 NV_INT_ALL_MCP55 = 0xffff,
181 NV_INT_PORT_SHIFT_MCP55 = 16, /* each port occupies 16 bits */
182 NV_INT_MASK_MCP55 = NV_INT_ALL_MCP55 & 0xfffd,
183
184 /* SWNCQ ENABLE BITS*/
185 NV_CTL_PRI_SWNCQ = 0x02,
186 NV_CTL_SEC_SWNCQ = 0x04,
187
188 /* SW NCQ status bits*/
189 NV_SWNCQ_IRQ_DEV = (1 << 0),
190 NV_SWNCQ_IRQ_PM = (1 << 1),
191 NV_SWNCQ_IRQ_ADDED = (1 << 2),
192 NV_SWNCQ_IRQ_REMOVED = (1 << 3),
193
194 NV_SWNCQ_IRQ_BACKOUT = (1 << 4),
195 NV_SWNCQ_IRQ_SDBFIS = (1 << 5),
196 NV_SWNCQ_IRQ_DHREGFIS = (1 << 6),
197 NV_SWNCQ_IRQ_DMASETUP = (1 << 7),
198
199 NV_SWNCQ_IRQ_HOTPLUG = NV_SWNCQ_IRQ_ADDED |
200 NV_SWNCQ_IRQ_REMOVED,
201
Jeff Garzik10ad05d2006-03-22 23:50:50 -0500202};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700203
Robert Hancockfbbb2622006-10-27 19:08:41 -0700204/* ADMA Physical Region Descriptor - one SG segment */
205struct nv_adma_prd {
206 __le64 addr;
207 __le32 len;
208 u8 flags;
209 u8 packet_len;
210 __le16 reserved;
211};
212
213enum nv_adma_regbits {
214 CMDEND = (1 << 15), /* end of command list */
215 WNB = (1 << 14), /* wait-not-BSY */
216 IGN = (1 << 13), /* ignore this entry */
217 CS1n = (1 << (4 + 8)), /* std. PATA signals follow... */
218 DA2 = (1 << (2 + 8)),
219 DA1 = (1 << (1 + 8)),
220 DA0 = (1 << (0 + 8)),
221};
222
223/* ADMA Command Parameter Block
224 The first 5 SG segments are stored inside the Command Parameter Block itself.
225 If there are more than 5 segments the remainder are stored in a separate
226 memory area indicated by next_aprd. */
227struct nv_adma_cpb {
228 u8 resp_flags; /* 0 */
229 u8 reserved1; /* 1 */
230 u8 ctl_flags; /* 2 */
231 /* len is length of taskfile in 64 bit words */
Jeff Garzik2dcb4072007-10-19 06:42:56 -0400232 u8 len; /* 3 */
Robert Hancockfbbb2622006-10-27 19:08:41 -0700233 u8 tag; /* 4 */
234 u8 next_cpb_idx; /* 5 */
235 __le16 reserved2; /* 6-7 */
236 __le16 tf[12]; /* 8-31 */
237 struct nv_adma_prd aprd[5]; /* 32-111 */
238 __le64 next_aprd; /* 112-119 */
239 __le64 reserved3; /* 120-127 */
240};
241
242
243struct nv_adma_port_priv {
244 struct nv_adma_cpb *cpb;
245 dma_addr_t cpb_dma;
246 struct nv_adma_prd *aprd;
247 dma_addr_t aprd_dma;
Jeff Garzik2dcb4072007-10-19 06:42:56 -0400248 void __iomem *ctl_block;
249 void __iomem *gen_block;
250 void __iomem *notifier_clear_block;
Robert Hancock8959d302008-02-04 19:39:02 -0600251 u64 adma_dma_mask;
Robert Hancockfbbb2622006-10-27 19:08:41 -0700252 u8 flags;
Robert Hancock5e5c74a2007-02-19 18:42:30 -0600253 int last_issue_ncq;
Robert Hancockfbbb2622006-10-27 19:08:41 -0700254};
255
Robert Hancockcdf56bc2007-01-03 18:13:57 -0600256struct nv_host_priv {
257 unsigned long type;
258};
259
Kuan Luof140f0f2007-10-15 15:16:53 -0400260struct defer_queue {
261 u32 defer_bits;
262 unsigned int head;
263 unsigned int tail;
264 unsigned int tag[ATA_MAX_QUEUE];
265};
266
267enum ncq_saw_flag_list {
268 ncq_saw_d2h = (1U << 0),
269 ncq_saw_dmas = (1U << 1),
270 ncq_saw_sdb = (1U << 2),
271 ncq_saw_backout = (1U << 3),
272};
273
274struct nv_swncq_port_priv {
Tejun Heof60d7012010-05-10 21:41:41 +0200275 struct ata_bmdma_prd *prd; /* our SG list */
Kuan Luof140f0f2007-10-15 15:16:53 -0400276 dma_addr_t prd_dma; /* and its DMA mapping */
277 void __iomem *sactive_block;
278 void __iomem *irq_block;
279 void __iomem *tag_block;
280 u32 qc_active;
281
282 unsigned int last_issue_tag;
283
284 /* fifo circular queue to store deferral command */
285 struct defer_queue defer_queue;
286
287 /* for NCQ interrupt analysis */
288 u32 dhfis_bits;
289 u32 dmafis_bits;
290 u32 sdbfis_bits;
291
292 unsigned int ncq_flags;
293};
294
295
Jeff Garzik5796d1c2007-10-26 00:03:37 -0400296#define NV_ADMA_CHECK_INTR(GCTL, PORT) ((GCTL) & (1 << (19 + (12 * (PORT)))))
Robert Hancockfbbb2622006-10-27 19:08:41 -0700297
Jeff Garzik2dcb4072007-10-19 06:42:56 -0400298static int nv_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
Tejun Heo438ac6d2007-03-02 17:31:26 +0900299#ifdef CONFIG_PM
Robert Hancockcdf56bc2007-01-03 18:13:57 -0600300static int nv_pci_device_resume(struct pci_dev *pdev);
Tejun Heo438ac6d2007-03-02 17:31:26 +0900301#endif
Jeff Garzikcca39742006-08-24 03:19:22 -0400302static void nv_ck804_host_stop(struct ata_host *host);
David Howells7d12e782006-10-05 14:55:46 +0100303static irqreturn_t nv_generic_interrupt(int irq, void *dev_instance);
304static irqreturn_t nv_nf2_interrupt(int irq, void *dev_instance);
305static irqreturn_t nv_ck804_interrupt(int irq, void *dev_instance);
Tejun Heo82ef04f2008-07-31 17:02:40 +0900306static int nv_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
307static int nv_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700308
Tejun Heo7f4774b2009-06-10 16:29:07 +0900309static int nv_hardreset(struct ata_link *link, unsigned int *class,
310 unsigned long deadline);
Tejun Heo39f87582006-06-17 15:49:56 +0900311static void nv_nf2_freeze(struct ata_port *ap);
312static void nv_nf2_thaw(struct ata_port *ap);
313static void nv_ck804_freeze(struct ata_port *ap);
314static void nv_ck804_thaw(struct ata_port *ap);
Robert Hancockfbbb2622006-10-27 19:08:41 -0700315static int nv_adma_slave_config(struct scsi_device *sdev);
Robert Hancock2dec7552006-11-26 14:20:19 -0600316static int nv_adma_check_atapi_dma(struct ata_queued_cmd *qc);
Robert Hancockfbbb2622006-10-27 19:08:41 -0700317static void nv_adma_qc_prep(struct ata_queued_cmd *qc);
318static unsigned int nv_adma_qc_issue(struct ata_queued_cmd *qc);
319static irqreturn_t nv_adma_interrupt(int irq, void *dev_instance);
320static void nv_adma_irq_clear(struct ata_port *ap);
321static int nv_adma_port_start(struct ata_port *ap);
322static void nv_adma_port_stop(struct ata_port *ap);
Tejun Heo438ac6d2007-03-02 17:31:26 +0900323#ifdef CONFIG_PM
Robert Hancockcdf56bc2007-01-03 18:13:57 -0600324static int nv_adma_port_suspend(struct ata_port *ap, pm_message_t mesg);
325static int nv_adma_port_resume(struct ata_port *ap);
Tejun Heo438ac6d2007-03-02 17:31:26 +0900326#endif
Robert Hancock53014e22007-05-05 15:36:36 -0600327static void nv_adma_freeze(struct ata_port *ap);
328static void nv_adma_thaw(struct ata_port *ap);
Robert Hancockfbbb2622006-10-27 19:08:41 -0700329static void nv_adma_error_handler(struct ata_port *ap);
330static void nv_adma_host_stop(struct ata_host *host);
Robert Hancockf5ecac22007-02-20 21:49:10 -0600331static void nv_adma_post_internal_cmd(struct ata_queued_cmd *qc);
Robert Hancockf2fb3442007-03-26 21:43:36 -0800332static void nv_adma_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
Tejun Heo39f87582006-06-17 15:49:56 +0900333
Kuan Luof140f0f2007-10-15 15:16:53 -0400334static void nv_mcp55_thaw(struct ata_port *ap);
335static void nv_mcp55_freeze(struct ata_port *ap);
336static void nv_swncq_error_handler(struct ata_port *ap);
337static int nv_swncq_slave_config(struct scsi_device *sdev);
338static int nv_swncq_port_start(struct ata_port *ap);
339static void nv_swncq_qc_prep(struct ata_queued_cmd *qc);
340static void nv_swncq_fill_sg(struct ata_queued_cmd *qc);
341static unsigned int nv_swncq_qc_issue(struct ata_queued_cmd *qc);
342static void nv_swncq_irq_clear(struct ata_port *ap, u16 fis);
343static irqreturn_t nv_swncq_interrupt(int irq, void *dev_instance);
344#ifdef CONFIG_PM
345static int nv_swncq_port_suspend(struct ata_port *ap, pm_message_t mesg);
346static int nv_swncq_port_resume(struct ata_port *ap);
347#endif
348
Linus Torvalds1da177e2005-04-16 15:20:36 -0700349enum nv_host_type
350{
351 GENERIC,
352 NFORCE2,
Tejun Heo27e4b272006-06-17 15:49:55 +0900353 NFORCE3 = NFORCE2, /* NF2 == NF3 as far as sata_nv is concerned */
Robert Hancockfbbb2622006-10-27 19:08:41 -0700354 CK804,
Kuan Luof140f0f2007-10-15 15:16:53 -0400355 ADMA,
Tejun Heo2d775702009-01-25 11:29:38 +0900356 MCP5x,
Kuan Luof140f0f2007-10-15 15:16:53 -0400357 SWNCQ,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700358};
359
Jeff Garzik3b7d6972005-11-10 11:04:11 -0500360static const struct pci_device_id nv_pci_tbl[] = {
Jeff Garzik54bb3a942006-09-27 22:20:11 -0400361 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_SATA), NFORCE2 },
362 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA), NFORCE3 },
363 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA2), NFORCE3 },
364 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA), CK804 },
365 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA2), CK804 },
366 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA), CK804 },
367 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA2), CK804 },
Tejun Heo2d775702009-01-25 11:29:38 +0900368 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA), MCP5x },
369 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA2), MCP5x },
370 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA), MCP5x },
371 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA2), MCP5x },
Kuan Luoe2e031e2007-10-25 02:14:17 -0400372 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA), GENERIC },
373 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA2), GENERIC },
374 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA3), GENERIC },
Jeff Garzik2d2744f2006-09-28 20:21:59 -0400375
376 { } /* terminate list */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700377};
378
Linus Torvalds1da177e2005-04-16 15:20:36 -0700379static struct pci_driver nv_pci_driver = {
380 .name = DRV_NAME,
381 .id_table = nv_pci_tbl,
382 .probe = nv_init_one,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900383#ifdef CONFIG_PM
Robert Hancockcdf56bc2007-01-03 18:13:57 -0600384 .suspend = ata_pci_device_suspend,
385 .resume = nv_pci_device_resume,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900386#endif
Tejun Heo1daf9ce2007-05-17 13:13:57 +0200387 .remove = ata_pci_remove_one,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700388};
389
Jeff Garzik193515d2005-11-07 00:59:37 -0500390static struct scsi_host_template nv_sht = {
Tejun Heo68d1d072008-03-25 12:22:49 +0900391 ATA_BMDMA_SHT(DRV_NAME),
Linus Torvalds1da177e2005-04-16 15:20:36 -0700392};
393
Robert Hancockfbbb2622006-10-27 19:08:41 -0700394static struct scsi_host_template nv_adma_sht = {
Tejun Heo68d1d072008-03-25 12:22:49 +0900395 ATA_NCQ_SHT(DRV_NAME),
Robert Hancockfbbb2622006-10-27 19:08:41 -0700396 .can_queue = NV_ADMA_MAX_CPBS,
Robert Hancockfbbb2622006-10-27 19:08:41 -0700397 .sg_tablesize = NV_ADMA_SGTBL_TOTAL_LEN,
Robert Hancockfbbb2622006-10-27 19:08:41 -0700398 .dma_boundary = NV_ADMA_DMA_BOUNDARY,
399 .slave_configure = nv_adma_slave_config,
Robert Hancockfbbb2622006-10-27 19:08:41 -0700400};
401
Kuan Luof140f0f2007-10-15 15:16:53 -0400402static struct scsi_host_template nv_swncq_sht = {
Tejun Heo68d1d072008-03-25 12:22:49 +0900403 ATA_NCQ_SHT(DRV_NAME),
Kuan Luof140f0f2007-10-15 15:16:53 -0400404 .can_queue = ATA_MAX_QUEUE,
Kuan Luof140f0f2007-10-15 15:16:53 -0400405 .sg_tablesize = LIBATA_MAX_PRD,
Kuan Luof140f0f2007-10-15 15:16:53 -0400406 .dma_boundary = ATA_DMA_BOUNDARY,
407 .slave_configure = nv_swncq_slave_config,
Kuan Luof140f0f2007-10-15 15:16:53 -0400408};
409
Tejun Heo7f4774b2009-06-10 16:29:07 +0900410/*
411 * NV SATA controllers have various different problems with hardreset
412 * protocol depending on the specific controller and device.
413 *
414 * GENERIC:
415 *
416 * bko11195 reports that link doesn't come online after hardreset on
417 * generic nv's and there have been several other similar reports on
418 * linux-ide.
419 *
420 * bko12351#c23 reports that warmplug on MCP61 doesn't work with
421 * softreset.
422 *
423 * NF2/3:
424 *
425 * bko3352 reports nf2/3 controllers can't determine device signature
426 * reliably after hardreset. The following thread reports detection
427 * failure on cold boot with the standard debouncing timing.
428 *
429 * http://thread.gmane.org/gmane.linux.ide/34098
430 *
431 * bko12176 reports that hardreset fails to bring up the link during
432 * boot on nf2.
433 *
434 * CK804:
435 *
436 * For initial probing after boot and hot plugging, hardreset mostly
437 * works fine on CK804 but curiously, reprobing on the initial port
438 * by rescanning or rmmod/insmod fails to acquire the initial D2H Reg
439 * FIS in somewhat undeterministic way.
440 *
441 * SWNCQ:
442 *
443 * bko12351 reports that when SWNCQ is enabled, for hotplug to work,
444 * hardreset should be used and hardreset can't report proper
445 * signature, which suggests that mcp5x is closer to nf2 as long as
446 * reset quirkiness is concerned.
447 *
448 * bko12703 reports that boot probing fails for intel SSD with
449 * hardreset. Link fails to come online. Softreset works fine.
450 *
451 * The failures are varied but the following patterns seem true for
452 * all flavors.
453 *
454 * - Softreset during boot always works.
455 *
456 * - Hardreset during boot sometimes fails to bring up the link on
457 * certain comibnations and device signature acquisition is
458 * unreliable.
459 *
460 * - Hardreset is often necessary after hotplug.
461 *
462 * So, preferring softreset for boot probing and error handling (as
463 * hardreset might bring down the link) but using hardreset for
464 * post-boot probing should work around the above issues in most
465 * cases. Define nv_hardreset() which only kicks in for post-boot
466 * probing and use it for all variants.
467 */
468static struct ata_port_operations nv_generic_ops = {
Tejun Heo029cfd62008-03-25 12:22:49 +0900469 .inherits = &ata_bmdma_port_ops,
Alan Coxc96f1732009-03-24 10:23:46 +0000470 .lost_interrupt = ATA_OP_NULL,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700471 .scr_read = nv_scr_read,
472 .scr_write = nv_scr_write,
Tejun Heo7f4774b2009-06-10 16:29:07 +0900473 .hardreset = nv_hardreset,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700474};
475
Tejun Heo029cfd62008-03-25 12:22:49 +0900476static struct ata_port_operations nv_nf2_ops = {
Tejun Heo7dac7452009-02-12 10:34:32 +0900477 .inherits = &nv_generic_ops,
Tejun Heo39f87582006-06-17 15:49:56 +0900478 .freeze = nv_nf2_freeze,
479 .thaw = nv_nf2_thaw,
Tejun Heoada364e2006-06-17 15:49:56 +0900480};
481
Tejun Heo029cfd62008-03-25 12:22:49 +0900482static struct ata_port_operations nv_ck804_ops = {
Tejun Heo7f4774b2009-06-10 16:29:07 +0900483 .inherits = &nv_generic_ops,
Tejun Heo39f87582006-06-17 15:49:56 +0900484 .freeze = nv_ck804_freeze,
485 .thaw = nv_ck804_thaw,
Tejun Heoada364e2006-06-17 15:49:56 +0900486 .host_stop = nv_ck804_host_stop,
487};
488
Tejun Heo029cfd62008-03-25 12:22:49 +0900489static struct ata_port_operations nv_adma_ops = {
Tejun Heo3c324282008-11-03 12:37:49 +0900490 .inherits = &nv_ck804_ops,
Tejun Heo029cfd62008-03-25 12:22:49 +0900491
Robert Hancock2dec7552006-11-26 14:20:19 -0600492 .check_atapi_dma = nv_adma_check_atapi_dma,
Tejun Heo5682ed32008-04-07 22:47:16 +0900493 .sff_tf_read = nv_adma_tf_read,
Tejun Heo31cc23b2007-09-23 13:14:12 +0900494 .qc_defer = ata_std_qc_defer,
Robert Hancockfbbb2622006-10-27 19:08:41 -0700495 .qc_prep = nv_adma_qc_prep,
496 .qc_issue = nv_adma_qc_issue,
Tejun Heo5682ed32008-04-07 22:47:16 +0900497 .sff_irq_clear = nv_adma_irq_clear,
Tejun Heo029cfd62008-03-25 12:22:49 +0900498
Robert Hancock53014e22007-05-05 15:36:36 -0600499 .freeze = nv_adma_freeze,
500 .thaw = nv_adma_thaw,
Robert Hancockfbbb2622006-10-27 19:08:41 -0700501 .error_handler = nv_adma_error_handler,
Robert Hancockf5ecac22007-02-20 21:49:10 -0600502 .post_internal_cmd = nv_adma_post_internal_cmd,
Tejun Heo029cfd62008-03-25 12:22:49 +0900503
Robert Hancockfbbb2622006-10-27 19:08:41 -0700504 .port_start = nv_adma_port_start,
505 .port_stop = nv_adma_port_stop,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900506#ifdef CONFIG_PM
Robert Hancockcdf56bc2007-01-03 18:13:57 -0600507 .port_suspend = nv_adma_port_suspend,
508 .port_resume = nv_adma_port_resume,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900509#endif
Robert Hancockfbbb2622006-10-27 19:08:41 -0700510 .host_stop = nv_adma_host_stop,
511};
512
Tejun Heo029cfd62008-03-25 12:22:49 +0900513static struct ata_port_operations nv_swncq_ops = {
Tejun Heo7f4774b2009-06-10 16:29:07 +0900514 .inherits = &nv_generic_ops,
Tejun Heo029cfd62008-03-25 12:22:49 +0900515
Kuan Luof140f0f2007-10-15 15:16:53 -0400516 .qc_defer = ata_std_qc_defer,
517 .qc_prep = nv_swncq_qc_prep,
518 .qc_issue = nv_swncq_qc_issue,
Tejun Heo029cfd62008-03-25 12:22:49 +0900519
Kuan Luof140f0f2007-10-15 15:16:53 -0400520 .freeze = nv_mcp55_freeze,
521 .thaw = nv_mcp55_thaw,
522 .error_handler = nv_swncq_error_handler,
Tejun Heo029cfd62008-03-25 12:22:49 +0900523
Kuan Luof140f0f2007-10-15 15:16:53 -0400524#ifdef CONFIG_PM
525 .port_suspend = nv_swncq_port_suspend,
526 .port_resume = nv_swncq_port_resume,
527#endif
528 .port_start = nv_swncq_port_start,
529};
530
Tejun Heo95947192008-03-25 12:22:49 +0900531struct nv_pi_priv {
532 irq_handler_t irq_handler;
533 struct scsi_host_template *sht;
534};
535
536#define NV_PI_PRIV(_irq_handler, _sht) \
537 &(struct nv_pi_priv){ .irq_handler = _irq_handler, .sht = _sht }
538
Tejun Heo1626aeb2007-05-04 12:43:58 +0200539static const struct ata_port_info nv_port_info[] = {
Tejun Heoada364e2006-06-17 15:49:56 +0900540 /* generic */
541 {
Tejun Heo0c887582007-08-06 18:36:23 +0900542 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY,
Tejun Heoada364e2006-06-17 15:49:56 +0900543 .pio_mask = NV_PIO_MASK,
544 .mwdma_mask = NV_MWDMA_MASK,
545 .udma_mask = NV_UDMA_MASK,
546 .port_ops = &nv_generic_ops,
Tejun Heo95947192008-03-25 12:22:49 +0900547 .private_data = NV_PI_PRIV(nv_generic_interrupt, &nv_sht),
Tejun Heoada364e2006-06-17 15:49:56 +0900548 },
549 /* nforce2/3 */
550 {
Tejun Heo0c887582007-08-06 18:36:23 +0900551 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY,
Tejun Heoada364e2006-06-17 15:49:56 +0900552 .pio_mask = NV_PIO_MASK,
553 .mwdma_mask = NV_MWDMA_MASK,
554 .udma_mask = NV_UDMA_MASK,
555 .port_ops = &nv_nf2_ops,
Tejun Heo95947192008-03-25 12:22:49 +0900556 .private_data = NV_PI_PRIV(nv_nf2_interrupt, &nv_sht),
Tejun Heoada364e2006-06-17 15:49:56 +0900557 },
558 /* ck804 */
559 {
Tejun Heo0c887582007-08-06 18:36:23 +0900560 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY,
Tejun Heoada364e2006-06-17 15:49:56 +0900561 .pio_mask = NV_PIO_MASK,
562 .mwdma_mask = NV_MWDMA_MASK,
563 .udma_mask = NV_UDMA_MASK,
564 .port_ops = &nv_ck804_ops,
Tejun Heo95947192008-03-25 12:22:49 +0900565 .private_data = NV_PI_PRIV(nv_ck804_interrupt, &nv_sht),
Tejun Heoada364e2006-06-17 15:49:56 +0900566 },
Robert Hancockfbbb2622006-10-27 19:08:41 -0700567 /* ADMA */
568 {
Robert Hancockfbbb2622006-10-27 19:08:41 -0700569 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
570 ATA_FLAG_MMIO | ATA_FLAG_NCQ,
571 .pio_mask = NV_PIO_MASK,
572 .mwdma_mask = NV_MWDMA_MASK,
573 .udma_mask = NV_UDMA_MASK,
574 .port_ops = &nv_adma_ops,
Tejun Heo95947192008-03-25 12:22:49 +0900575 .private_data = NV_PI_PRIV(nv_adma_interrupt, &nv_adma_sht),
Robert Hancockfbbb2622006-10-27 19:08:41 -0700576 },
Tejun Heo2d775702009-01-25 11:29:38 +0900577 /* MCP5x */
578 {
579 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY,
580 .pio_mask = NV_PIO_MASK,
581 .mwdma_mask = NV_MWDMA_MASK,
582 .udma_mask = NV_UDMA_MASK,
Tejun Heo7f4774b2009-06-10 16:29:07 +0900583 .port_ops = &nv_generic_ops,
Tejun Heo2d775702009-01-25 11:29:38 +0900584 .private_data = NV_PI_PRIV(nv_generic_interrupt, &nv_sht),
585 },
Kuan Luof140f0f2007-10-15 15:16:53 -0400586 /* SWNCQ */
587 {
Kuan Luof140f0f2007-10-15 15:16:53 -0400588 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
589 ATA_FLAG_NCQ,
Kuan Luof140f0f2007-10-15 15:16:53 -0400590 .pio_mask = NV_PIO_MASK,
591 .mwdma_mask = NV_MWDMA_MASK,
592 .udma_mask = NV_UDMA_MASK,
593 .port_ops = &nv_swncq_ops,
Tejun Heo95947192008-03-25 12:22:49 +0900594 .private_data = NV_PI_PRIV(nv_swncq_interrupt, &nv_swncq_sht),
Kuan Luof140f0f2007-10-15 15:16:53 -0400595 },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700596};
597
598MODULE_AUTHOR("NVIDIA");
599MODULE_DESCRIPTION("low-level driver for NVIDIA nForce SATA controller");
600MODULE_LICENSE("GPL");
601MODULE_DEVICE_TABLE(pci, nv_pci_tbl);
602MODULE_VERSION(DRV_VERSION);
603
Jeff Garzik06993d22008-04-04 03:34:45 -0400604static int adma_enabled;
Zoltan Boszormenyid21279f2008-03-28 14:33:46 -0700605static int swncq_enabled = 1;
Tony Vroon51c89492009-08-06 00:50:09 +0100606static int msi_enabled;
Robert Hancockfbbb2622006-10-27 19:08:41 -0700607
Robert Hancock2dec7552006-11-26 14:20:19 -0600608static void nv_adma_register_mode(struct ata_port *ap)
609{
Robert Hancock2dec7552006-11-26 14:20:19 -0600610 struct nv_adma_port_priv *pp = ap->private_data;
Robert Hancockcdf56bc2007-01-03 18:13:57 -0600611 void __iomem *mmio = pp->ctl_block;
Robert Hancocka2cfe812007-02-05 16:26:03 -0800612 u16 tmp, status;
613 int count = 0;
Robert Hancock2dec7552006-11-26 14:20:19 -0600614
615 if (pp->flags & NV_ADMA_PORT_REGISTER_MODE)
616 return;
617
Robert Hancocka2cfe812007-02-05 16:26:03 -0800618 status = readw(mmio + NV_ADMA_STAT);
Jeff Garzik2dcb4072007-10-19 06:42:56 -0400619 while (!(status & NV_ADMA_STAT_IDLE) && count < 20) {
Robert Hancocka2cfe812007-02-05 16:26:03 -0800620 ndelay(50);
621 status = readw(mmio + NV_ADMA_STAT);
622 count++;
623 }
Jeff Garzik2dcb4072007-10-19 06:42:56 -0400624 if (count == 20)
Robert Hancocka2cfe812007-02-05 16:26:03 -0800625 ata_port_printk(ap, KERN_WARNING,
626 "timeout waiting for ADMA IDLE, stat=0x%hx\n",
627 status);
628
Robert Hancock2dec7552006-11-26 14:20:19 -0600629 tmp = readw(mmio + NV_ADMA_CTL);
630 writew(tmp & ~NV_ADMA_CTL_GO, mmio + NV_ADMA_CTL);
631
Robert Hancocka2cfe812007-02-05 16:26:03 -0800632 count = 0;
633 status = readw(mmio + NV_ADMA_STAT);
Jeff Garzik2dcb4072007-10-19 06:42:56 -0400634 while (!(status & NV_ADMA_STAT_LEGACY) && count < 20) {
Robert Hancocka2cfe812007-02-05 16:26:03 -0800635 ndelay(50);
636 status = readw(mmio + NV_ADMA_STAT);
637 count++;
638 }
Jeff Garzik2dcb4072007-10-19 06:42:56 -0400639 if (count == 20)
Robert Hancocka2cfe812007-02-05 16:26:03 -0800640 ata_port_printk(ap, KERN_WARNING,
641 "timeout waiting for ADMA LEGACY, stat=0x%hx\n",
642 status);
643
Robert Hancock2dec7552006-11-26 14:20:19 -0600644 pp->flags |= NV_ADMA_PORT_REGISTER_MODE;
645}
646
647static void nv_adma_mode(struct ata_port *ap)
648{
Robert Hancock2dec7552006-11-26 14:20:19 -0600649 struct nv_adma_port_priv *pp = ap->private_data;
Robert Hancockcdf56bc2007-01-03 18:13:57 -0600650 void __iomem *mmio = pp->ctl_block;
Robert Hancocka2cfe812007-02-05 16:26:03 -0800651 u16 tmp, status;
652 int count = 0;
Robert Hancock2dec7552006-11-26 14:20:19 -0600653
654 if (!(pp->flags & NV_ADMA_PORT_REGISTER_MODE))
655 return;
Jeff Garzikf20b16f2006-12-11 11:14:06 -0500656
Robert Hancock2dec7552006-11-26 14:20:19 -0600657 WARN_ON(pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE);
658
659 tmp = readw(mmio + NV_ADMA_CTL);
660 writew(tmp | NV_ADMA_CTL_GO, mmio + NV_ADMA_CTL);
661
Robert Hancocka2cfe812007-02-05 16:26:03 -0800662 status = readw(mmio + NV_ADMA_STAT);
Jeff Garzik2dcb4072007-10-19 06:42:56 -0400663 while (((status & NV_ADMA_STAT_LEGACY) ||
Robert Hancocka2cfe812007-02-05 16:26:03 -0800664 !(status & NV_ADMA_STAT_IDLE)) && count < 20) {
665 ndelay(50);
666 status = readw(mmio + NV_ADMA_STAT);
667 count++;
668 }
Jeff Garzik2dcb4072007-10-19 06:42:56 -0400669 if (count == 20)
Robert Hancocka2cfe812007-02-05 16:26:03 -0800670 ata_port_printk(ap, KERN_WARNING,
671 "timeout waiting for ADMA LEGACY clear and IDLE, stat=0x%hx\n",
672 status);
673
Robert Hancock2dec7552006-11-26 14:20:19 -0600674 pp->flags &= ~NV_ADMA_PORT_REGISTER_MODE;
675}
676
Robert Hancockfbbb2622006-10-27 19:08:41 -0700677static int nv_adma_slave_config(struct scsi_device *sdev)
678{
679 struct ata_port *ap = ata_shost_to_port(sdev->host);
Robert Hancock2dec7552006-11-26 14:20:19 -0600680 struct nv_adma_port_priv *pp = ap->private_data;
Robert Hancock8959d302008-02-04 19:39:02 -0600681 struct nv_adma_port_priv *port0, *port1;
682 struct scsi_device *sdev0, *sdev1;
Robert Hancock2dec7552006-11-26 14:20:19 -0600683 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
Robert Hancock8959d302008-02-04 19:39:02 -0600684 unsigned long segment_boundary, flags;
Robert Hancockfbbb2622006-10-27 19:08:41 -0700685 unsigned short sg_tablesize;
686 int rc;
Robert Hancock2dec7552006-11-26 14:20:19 -0600687 int adma_enable;
688 u32 current_reg, new_reg, config_mask;
Robert Hancockfbbb2622006-10-27 19:08:41 -0700689
690 rc = ata_scsi_slave_config(sdev);
691
692 if (sdev->id >= ATA_MAX_DEVICES || sdev->channel || sdev->lun)
693 /* Not a proper libata device, ignore */
694 return rc;
695
Robert Hancock8959d302008-02-04 19:39:02 -0600696 spin_lock_irqsave(ap->lock, flags);
697
Tejun Heo9af5c9c2007-08-06 18:36:22 +0900698 if (ap->link.device[sdev->id].class == ATA_DEV_ATAPI) {
Robert Hancockfbbb2622006-10-27 19:08:41 -0700699 /*
700 * NVIDIA reports that ADMA mode does not support ATAPI commands.
701 * Therefore ATAPI commands are sent through the legacy interface.
702 * However, the legacy interface only supports 32-bit DMA.
703 * Restrict DMA parameters as required by the legacy interface
704 * when an ATAPI device is connected.
705 */
Robert Hancockfbbb2622006-10-27 19:08:41 -0700706 segment_boundary = ATA_DMA_BOUNDARY;
707 /* Subtract 1 since an extra entry may be needed for padding, see
708 libata-scsi.c */
709 sg_tablesize = LIBATA_MAX_PRD - 1;
Jeff Garzikf20b16f2006-12-11 11:14:06 -0500710
Robert Hancock2dec7552006-11-26 14:20:19 -0600711 /* Since the legacy DMA engine is in use, we need to disable ADMA
712 on the port. */
713 adma_enable = 0;
714 nv_adma_register_mode(ap);
Jeff Garzik2dcb4072007-10-19 06:42:56 -0400715 } else {
Robert Hancockfbbb2622006-10-27 19:08:41 -0700716 segment_boundary = NV_ADMA_DMA_BOUNDARY;
717 sg_tablesize = NV_ADMA_SGTBL_TOTAL_LEN;
Robert Hancock2dec7552006-11-26 14:20:19 -0600718 adma_enable = 1;
Robert Hancockfbbb2622006-10-27 19:08:41 -0700719 }
Jeff Garzikf20b16f2006-12-11 11:14:06 -0500720
Robert Hancock2dec7552006-11-26 14:20:19 -0600721 pci_read_config_dword(pdev, NV_MCP_SATA_CFG_20, &current_reg);
Robert Hancockfbbb2622006-10-27 19:08:41 -0700722
Jeff Garzik2dcb4072007-10-19 06:42:56 -0400723 if (ap->port_no == 1)
Robert Hancock2dec7552006-11-26 14:20:19 -0600724 config_mask = NV_MCP_SATA_CFG_20_PORT1_EN |
725 NV_MCP_SATA_CFG_20_PORT1_PWB_EN;
726 else
727 config_mask = NV_MCP_SATA_CFG_20_PORT0_EN |
728 NV_MCP_SATA_CFG_20_PORT0_PWB_EN;
Jeff Garzikf20b16f2006-12-11 11:14:06 -0500729
Jeff Garzik2dcb4072007-10-19 06:42:56 -0400730 if (adma_enable) {
Robert Hancock2dec7552006-11-26 14:20:19 -0600731 new_reg = current_reg | config_mask;
732 pp->flags &= ~NV_ADMA_ATAPI_SETUP_COMPLETE;
Jeff Garzik2dcb4072007-10-19 06:42:56 -0400733 } else {
Robert Hancock2dec7552006-11-26 14:20:19 -0600734 new_reg = current_reg & ~config_mask;
735 pp->flags |= NV_ADMA_ATAPI_SETUP_COMPLETE;
736 }
Jeff Garzikf20b16f2006-12-11 11:14:06 -0500737
Jeff Garzik2dcb4072007-10-19 06:42:56 -0400738 if (current_reg != new_reg)
Robert Hancock2dec7552006-11-26 14:20:19 -0600739 pci_write_config_dword(pdev, NV_MCP_SATA_CFG_20, new_reg);
Jeff Garzikf20b16f2006-12-11 11:14:06 -0500740
Robert Hancock8959d302008-02-04 19:39:02 -0600741 port0 = ap->host->ports[0]->private_data;
742 port1 = ap->host->ports[1]->private_data;
743 sdev0 = ap->host->ports[0]->link.device[0].sdev;
744 sdev1 = ap->host->ports[1]->link.device[0].sdev;
745 if ((port0->flags & NV_ADMA_ATAPI_SETUP_COMPLETE) ||
746 (port1->flags & NV_ADMA_ATAPI_SETUP_COMPLETE)) {
747 /** We have to set the DMA mask to 32-bit if either port is in
748 ATAPI mode, since they are on the same PCI device which is
749 used for DMA mapping. If we set the mask we also need to set
750 the bounce limit on both ports to ensure that the block
751 layer doesn't feed addresses that cause DMA mapping to
752 choke. If either SCSI device is not allocated yet, it's OK
753 since that port will discover its correct setting when it
754 does get allocated.
755 Note: Setting 32-bit mask should not fail. */
756 if (sdev0)
757 blk_queue_bounce_limit(sdev0->request_queue,
758 ATA_DMA_MASK);
759 if (sdev1)
760 blk_queue_bounce_limit(sdev1->request_queue,
761 ATA_DMA_MASK);
762
763 pci_set_dma_mask(pdev, ATA_DMA_MASK);
764 } else {
765 /** This shouldn't fail as it was set to this value before */
766 pci_set_dma_mask(pdev, pp->adma_dma_mask);
767 if (sdev0)
768 blk_queue_bounce_limit(sdev0->request_queue,
769 pp->adma_dma_mask);
770 if (sdev1)
771 blk_queue_bounce_limit(sdev1->request_queue,
772 pp->adma_dma_mask);
773 }
774
Robert Hancockfbbb2622006-10-27 19:08:41 -0700775 blk_queue_segment_boundary(sdev->request_queue, segment_boundary);
Martin K. Petersen8a783622010-02-26 00:20:39 -0500776 blk_queue_max_segments(sdev->request_queue, sg_tablesize);
Robert Hancockfbbb2622006-10-27 19:08:41 -0700777 ata_port_printk(ap, KERN_INFO,
Robert Hancock8959d302008-02-04 19:39:02 -0600778 "DMA mask 0x%llX, segment boundary 0x%lX, hw segs %hu\n",
779 (unsigned long long)*ap->host->dev->dma_mask,
780 segment_boundary, sg_tablesize);
781
782 spin_unlock_irqrestore(ap->lock, flags);
783
Robert Hancockfbbb2622006-10-27 19:08:41 -0700784 return rc;
785}
786
Robert Hancock2dec7552006-11-26 14:20:19 -0600787static int nv_adma_check_atapi_dma(struct ata_queued_cmd *qc)
788{
789 struct nv_adma_port_priv *pp = qc->ap->private_data;
790 return !(pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE);
791}
792
Robert Hancockf2fb3442007-03-26 21:43:36 -0800793static void nv_adma_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
794{
Robert Hancock3f3debd2007-11-25 16:59:36 -0600795 /* Other than when internal or pass-through commands are executed,
796 the only time this function will be called in ADMA mode will be
797 if a command fails. In the failure case we don't care about going
798 into register mode with ADMA commands pending, as the commands will
799 all shortly be aborted anyway. We assume that NCQ commands are not
800 issued via passthrough, which is the only way that switching into
801 ADMA mode could abort outstanding commands. */
Robert Hancockf2fb3442007-03-26 21:43:36 -0800802 nv_adma_register_mode(ap);
803
Tejun Heo9363c382008-04-07 22:47:16 +0900804 ata_sff_tf_read(ap, tf);
Robert Hancockf2fb3442007-03-26 21:43:36 -0800805}
806
Robert Hancock2dec7552006-11-26 14:20:19 -0600807static unsigned int nv_adma_tf_to_cpb(struct ata_taskfile *tf, __le16 *cpb)
Robert Hancockfbbb2622006-10-27 19:08:41 -0700808{
809 unsigned int idx = 0;
810
Jeff Garzik2dcb4072007-10-19 06:42:56 -0400811 if (tf->flags & ATA_TFLAG_ISADDR) {
Robert Hancockac3d6b82007-02-19 19:02:46 -0600812 if (tf->flags & ATA_TFLAG_LBA48) {
813 cpb[idx++] = cpu_to_le16((ATA_REG_ERR << 8) | tf->hob_feature | WNB);
814 cpb[idx++] = cpu_to_le16((ATA_REG_NSECT << 8) | tf->hob_nsect);
815 cpb[idx++] = cpu_to_le16((ATA_REG_LBAL << 8) | tf->hob_lbal);
816 cpb[idx++] = cpu_to_le16((ATA_REG_LBAM << 8) | tf->hob_lbam);
817 cpb[idx++] = cpu_to_le16((ATA_REG_LBAH << 8) | tf->hob_lbah);
818 cpb[idx++] = cpu_to_le16((ATA_REG_ERR << 8) | tf->feature);
819 } else
820 cpb[idx++] = cpu_to_le16((ATA_REG_ERR << 8) | tf->feature | WNB);
Jeff Garzika84471f2007-02-26 05:51:33 -0500821
Robert Hancockac3d6b82007-02-19 19:02:46 -0600822 cpb[idx++] = cpu_to_le16((ATA_REG_NSECT << 8) | tf->nsect);
823 cpb[idx++] = cpu_to_le16((ATA_REG_LBAL << 8) | tf->lbal);
824 cpb[idx++] = cpu_to_le16((ATA_REG_LBAM << 8) | tf->lbam);
825 cpb[idx++] = cpu_to_le16((ATA_REG_LBAH << 8) | tf->lbah);
Robert Hancockfbbb2622006-10-27 19:08:41 -0700826 }
Jeff Garzika84471f2007-02-26 05:51:33 -0500827
Jeff Garzik2dcb4072007-10-19 06:42:56 -0400828 if (tf->flags & ATA_TFLAG_DEVICE)
Robert Hancockac3d6b82007-02-19 19:02:46 -0600829 cpb[idx++] = cpu_to_le16((ATA_REG_DEVICE << 8) | tf->device);
Robert Hancockfbbb2622006-10-27 19:08:41 -0700830
831 cpb[idx++] = cpu_to_le16((ATA_REG_CMD << 8) | tf->command | CMDEND);
Jeff Garzika84471f2007-02-26 05:51:33 -0500832
Jeff Garzik2dcb4072007-10-19 06:42:56 -0400833 while (idx < 12)
Robert Hancockac3d6b82007-02-19 19:02:46 -0600834 cpb[idx++] = cpu_to_le16(IGN);
Robert Hancockfbbb2622006-10-27 19:08:41 -0700835
836 return idx;
837}
838
Robert Hancock5bd28a42007-02-05 16:26:01 -0800839static int nv_adma_check_cpb(struct ata_port *ap, int cpb_num, int force_err)
Robert Hancockfbbb2622006-10-27 19:08:41 -0700840{
841 struct nv_adma_port_priv *pp = ap->private_data;
Robert Hancock2dec7552006-11-26 14:20:19 -0600842 u8 flags = pp->cpb[cpb_num].resp_flags;
Robert Hancockfbbb2622006-10-27 19:08:41 -0700843
844 VPRINTK("CPB %d, flags=0x%x\n", cpb_num, flags);
845
Robert Hancock5bd28a42007-02-05 16:26:01 -0800846 if (unlikely((force_err ||
847 flags & (NV_CPB_RESP_ATA_ERR |
848 NV_CPB_RESP_CMD_ERR |
849 NV_CPB_RESP_CPB_ERR)))) {
Tejun Heo9af5c9c2007-08-06 18:36:22 +0900850 struct ata_eh_info *ehi = &ap->link.eh_info;
Robert Hancock5bd28a42007-02-05 16:26:01 -0800851 int freeze = 0;
852
853 ata_ehi_clear_desc(ehi);
Jeff Garzik2dcb4072007-10-19 06:42:56 -0400854 __ata_ehi_push_desc(ehi, "CPB resp_flags 0x%x: ", flags);
Robert Hancock5bd28a42007-02-05 16:26:01 -0800855 if (flags & NV_CPB_RESP_ATA_ERR) {
Tejun Heob64bbc32007-07-16 14:29:39 +0900856 ata_ehi_push_desc(ehi, "ATA error");
Robert Hancock5bd28a42007-02-05 16:26:01 -0800857 ehi->err_mask |= AC_ERR_DEV;
858 } else if (flags & NV_CPB_RESP_CMD_ERR) {
Tejun Heob64bbc32007-07-16 14:29:39 +0900859 ata_ehi_push_desc(ehi, "CMD error");
Robert Hancock5bd28a42007-02-05 16:26:01 -0800860 ehi->err_mask |= AC_ERR_DEV;
861 } else if (flags & NV_CPB_RESP_CPB_ERR) {
Tejun Heob64bbc32007-07-16 14:29:39 +0900862 ata_ehi_push_desc(ehi, "CPB error");
Robert Hancock5bd28a42007-02-05 16:26:01 -0800863 ehi->err_mask |= AC_ERR_SYSTEM;
864 freeze = 1;
865 } else {
866 /* notifier error, but no error in CPB flags? */
Tejun Heob64bbc32007-07-16 14:29:39 +0900867 ata_ehi_push_desc(ehi, "unknown");
Robert Hancock5bd28a42007-02-05 16:26:01 -0800868 ehi->err_mask |= AC_ERR_OTHER;
869 freeze = 1;
870 }
871 /* Kill all commands. EH will determine what actually failed. */
872 if (freeze)
873 ata_port_freeze(ap);
874 else
875 ata_port_abort(ap);
876 return 1;
877 }
878
Robert Hancockf2fb3442007-03-26 21:43:36 -0800879 if (likely(flags & NV_CPB_RESP_DONE)) {
Robert Hancockfbbb2622006-10-27 19:08:41 -0700880 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, cpb_num);
Robert Hancock5bd28a42007-02-05 16:26:01 -0800881 VPRINTK("CPB flags done, flags=0x%x\n", flags);
882 if (likely(qc)) {
Jeff Garzik2dcb4072007-10-19 06:42:56 -0400883 DPRINTK("Completing qc from tag %d\n", cpb_num);
Robert Hancockfbbb2622006-10-27 19:08:41 -0700884 ata_qc_complete(qc);
Robert Hancock2a54cf72007-02-21 23:53:03 -0600885 } else {
Tejun Heo9af5c9c2007-08-06 18:36:22 +0900886 struct ata_eh_info *ehi = &ap->link.eh_info;
Robert Hancock2a54cf72007-02-21 23:53:03 -0600887 /* Notifier bits set without a command may indicate the drive
888 is misbehaving. Raise host state machine violation on this
889 condition. */
Jeff Garzik5796d1c2007-10-26 00:03:37 -0400890 ata_port_printk(ap, KERN_ERR,
891 "notifier for tag %d with no cmd?\n",
892 cpb_num);
Robert Hancock2a54cf72007-02-21 23:53:03 -0600893 ehi->err_mask |= AC_ERR_HSM;
Tejun Heocf480622008-01-24 00:05:14 +0900894 ehi->action |= ATA_EH_RESET;
Robert Hancock2a54cf72007-02-21 23:53:03 -0600895 ata_port_freeze(ap);
896 return 1;
Robert Hancockfbbb2622006-10-27 19:08:41 -0700897 }
898 }
Robert Hancock5bd28a42007-02-05 16:26:01 -0800899 return 0;
Robert Hancockfbbb2622006-10-27 19:08:41 -0700900}
901
Robert Hancock2dec7552006-11-26 14:20:19 -0600902static int nv_host_intr(struct ata_port *ap, u8 irq_stat)
903{
Tejun Heo9af5c9c2007-08-06 18:36:22 +0900904 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag);
Robert Hancock2dec7552006-11-26 14:20:19 -0600905
906 /* freeze if hotplugged */
907 if (unlikely(irq_stat & (NV_INT_ADDED | NV_INT_REMOVED))) {
908 ata_port_freeze(ap);
909 return 1;
910 }
911
912 /* bail out if not our interrupt */
913 if (!(irq_stat & NV_INT_DEV))
914 return 0;
915
916 /* DEV interrupt w/ no active qc? */
917 if (unlikely(!qc || (qc->tf.flags & ATA_TFLAG_POLLING))) {
Tejun Heo9363c382008-04-07 22:47:16 +0900918 ata_sff_check_status(ap);
Robert Hancock2dec7552006-11-26 14:20:19 -0600919 return 1;
920 }
921
922 /* handle interrupt */
Tejun Heoc3b28892010-05-19 22:10:21 +0200923 return ata_bmdma_port_intr(ap, qc);
Robert Hancock2dec7552006-11-26 14:20:19 -0600924}
925
Robert Hancockfbbb2622006-10-27 19:08:41 -0700926static irqreturn_t nv_adma_interrupt(int irq, void *dev_instance)
927{
928 struct ata_host *host = dev_instance;
929 int i, handled = 0;
Robert Hancock2dec7552006-11-26 14:20:19 -0600930 u32 notifier_clears[2];
Robert Hancockfbbb2622006-10-27 19:08:41 -0700931
932 spin_lock(&host->lock);
933
934 for (i = 0; i < host->n_ports; i++) {
935 struct ata_port *ap = host->ports[i];
Tejun Heo3e4ec342010-05-10 21:41:30 +0200936 struct nv_adma_port_priv *pp = ap->private_data;
937 void __iomem *mmio = pp->ctl_block;
938 u16 status;
939 u32 gen_ctl;
940 u32 notifier, notifier_error;
941
Robert Hancock2dec7552006-11-26 14:20:19 -0600942 notifier_clears[i] = 0;
Robert Hancockfbbb2622006-10-27 19:08:41 -0700943
Tejun Heo3e4ec342010-05-10 21:41:30 +0200944 /* if ADMA is disabled, use standard ata interrupt handler */
945 if (pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE) {
946 u8 irq_stat = readb(host->iomap[NV_MMIO_BAR] + NV_INT_STATUS_CK804)
947 >> (NV_INT_PORT_SHIFT * i);
948 handled += nv_host_intr(ap, irq_stat);
949 continue;
950 }
Jeff Garzika617c092007-05-21 20:14:23 -0400951
Tejun Heo3e4ec342010-05-10 21:41:30 +0200952 /* if in ATA register mode, check for standard interrupts */
953 if (pp->flags & NV_ADMA_PORT_REGISTER_MODE) {
954 u8 irq_stat = readb(host->iomap[NV_MMIO_BAR] + NV_INT_STATUS_CK804)
955 >> (NV_INT_PORT_SHIFT * i);
956 if (ata_tag_valid(ap->link.active_tag))
957 /** NV_INT_DEV indication seems unreliable
958 at times at least in ADMA mode. Force it
959 on always when a command is active, to
960 prevent losing interrupts. */
961 irq_stat |= NV_INT_DEV;
962 handled += nv_host_intr(ap, irq_stat);
963 }
Robert Hancockfbbb2622006-10-27 19:08:41 -0700964
Tejun Heo3e4ec342010-05-10 21:41:30 +0200965 notifier = readl(mmio + NV_ADMA_NOTIFIER);
966 notifier_error = readl(mmio + NV_ADMA_NOTIFIER_ERROR);
967 notifier_clears[i] = notifier | notifier_error;
968
969 gen_ctl = readl(pp->gen_block + NV_ADMA_GEN_CTL);
970
971 if (!NV_ADMA_CHECK_INTR(gen_ctl, ap->port_no) && !notifier &&
972 !notifier_error)
973 /* Nothing to do */
974 continue;
975
976 status = readw(mmio + NV_ADMA_STAT);
977
978 /*
979 * Clear status. Ensure the controller sees the
980 * clearing before we start looking at any of the CPB
981 * statuses, so that any CPB completions after this
982 * point in the handler will raise another interrupt.
983 */
984 writew(status, mmio + NV_ADMA_STAT);
985 readw(mmio + NV_ADMA_STAT); /* flush posted write */
986 rmb();
987
988 handled++; /* irq handled if we got here */
989
990 /* freeze if hotplugged or controller error */
991 if (unlikely(status & (NV_ADMA_STAT_HOTPLUG |
992 NV_ADMA_STAT_HOTUNPLUG |
993 NV_ADMA_STAT_TIMEOUT |
994 NV_ADMA_STAT_SERROR))) {
995 struct ata_eh_info *ehi = &ap->link.eh_info;
996
997 ata_ehi_clear_desc(ehi);
998 __ata_ehi_push_desc(ehi, "ADMA status 0x%08x: ", status);
999 if (status & NV_ADMA_STAT_TIMEOUT) {
1000 ehi->err_mask |= AC_ERR_SYSTEM;
1001 ata_ehi_push_desc(ehi, "timeout");
1002 } else if (status & NV_ADMA_STAT_HOTPLUG) {
1003 ata_ehi_hotplugged(ehi);
1004 ata_ehi_push_desc(ehi, "hotplug");
1005 } else if (status & NV_ADMA_STAT_HOTUNPLUG) {
1006 ata_ehi_hotplugged(ehi);
1007 ata_ehi_push_desc(ehi, "hot unplug");
1008 } else if (status & NV_ADMA_STAT_SERROR) {
1009 /* let EH analyze SError and figure out cause */
1010 ata_ehi_push_desc(ehi, "SError");
1011 } else
1012 ata_ehi_push_desc(ehi, "unknown");
1013 ata_port_freeze(ap);
1014 continue;
1015 }
1016
1017 if (status & (NV_ADMA_STAT_DONE |
1018 NV_ADMA_STAT_CPBERR |
1019 NV_ADMA_STAT_CMD_COMPLETE)) {
1020 u32 check_commands = notifier_clears[i];
Tejun Heo752e3862010-06-25 15:02:59 +02001021 int pos, rc;
Tejun Heo3e4ec342010-05-10 21:41:30 +02001022
1023 if (status & NV_ADMA_STAT_CPBERR) {
1024 /* check all active commands */
Jeff Garzik2dcb4072007-10-19 06:42:56 -04001025 if (ata_tag_valid(ap->link.active_tag))
Tejun Heo3e4ec342010-05-10 21:41:30 +02001026 check_commands = 1 <<
1027 ap->link.active_tag;
1028 else
1029 check_commands = ap->link.sactive;
Robert Hancockfbbb2622006-10-27 19:08:41 -07001030 }
1031
Tejun Heo3e4ec342010-05-10 21:41:30 +02001032 /* check CPBs for completed commands */
Tejun Heo752e3862010-06-25 15:02:59 +02001033 while ((pos = ffs(check_commands))) {
Tejun Heo3e4ec342010-05-10 21:41:30 +02001034 pos--;
Tejun Heo752e3862010-06-25 15:02:59 +02001035 rc = nv_adma_check_cpb(ap, pos,
Jeff Garzik5796d1c2007-10-26 00:03:37 -04001036 notifier_error & (1 << pos));
Tejun Heo752e3862010-06-25 15:02:59 +02001037 if (unlikely(rc))
1038 check_commands = 0;
Tejun Heo3e4ec342010-05-10 21:41:30 +02001039 check_commands &= ~(1 << pos);
Robert Hancockfbbb2622006-10-27 19:08:41 -07001040 }
Robert Hancockfbbb2622006-10-27 19:08:41 -07001041 }
1042 }
Jeff Garzikf20b16f2006-12-11 11:14:06 -05001043
Jeff Garzikb4479162007-10-25 20:47:30 -04001044 if (notifier_clears[0] || notifier_clears[1]) {
Robert Hancock2dec7552006-11-26 14:20:19 -06001045 /* Note: Both notifier clear registers must be written
1046 if either is set, even if one is zero, according to NVIDIA. */
Robert Hancockcdf56bc2007-01-03 18:13:57 -06001047 struct nv_adma_port_priv *pp = host->ports[0]->private_data;
1048 writel(notifier_clears[0], pp->notifier_clear_block);
1049 pp = host->ports[1]->private_data;
1050 writel(notifier_clears[1], pp->notifier_clear_block);
Robert Hancock2dec7552006-11-26 14:20:19 -06001051 }
Robert Hancockfbbb2622006-10-27 19:08:41 -07001052
1053 spin_unlock(&host->lock);
1054
1055 return IRQ_RETVAL(handled);
1056}
1057
Robert Hancock53014e22007-05-05 15:36:36 -06001058static void nv_adma_freeze(struct ata_port *ap)
1059{
1060 struct nv_adma_port_priv *pp = ap->private_data;
1061 void __iomem *mmio = pp->ctl_block;
1062 u16 tmp;
1063
1064 nv_ck804_freeze(ap);
1065
1066 if (pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE)
1067 return;
1068
1069 /* clear any outstanding CK804 notifications */
Jeff Garzik2dcb4072007-10-19 06:42:56 -04001070 writeb(NV_INT_ALL << (ap->port_no * NV_INT_PORT_SHIFT),
Robert Hancock53014e22007-05-05 15:36:36 -06001071 ap->host->iomap[NV_MMIO_BAR] + NV_INT_STATUS_CK804);
1072
1073 /* Disable interrupt */
1074 tmp = readw(mmio + NV_ADMA_CTL);
Jeff Garzik2dcb4072007-10-19 06:42:56 -04001075 writew(tmp & ~(NV_ADMA_CTL_AIEN | NV_ADMA_CTL_HOTPLUG_IEN),
Robert Hancock53014e22007-05-05 15:36:36 -06001076 mmio + NV_ADMA_CTL);
Jeff Garzik5796d1c2007-10-26 00:03:37 -04001077 readw(mmio + NV_ADMA_CTL); /* flush posted write */
Robert Hancock53014e22007-05-05 15:36:36 -06001078}
1079
1080static void nv_adma_thaw(struct ata_port *ap)
1081{
1082 struct nv_adma_port_priv *pp = ap->private_data;
1083 void __iomem *mmio = pp->ctl_block;
1084 u16 tmp;
1085
1086 nv_ck804_thaw(ap);
1087
1088 if (pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE)
1089 return;
1090
1091 /* Enable interrupt */
1092 tmp = readw(mmio + NV_ADMA_CTL);
Jeff Garzik2dcb4072007-10-19 06:42:56 -04001093 writew(tmp | (NV_ADMA_CTL_AIEN | NV_ADMA_CTL_HOTPLUG_IEN),
Robert Hancock53014e22007-05-05 15:36:36 -06001094 mmio + NV_ADMA_CTL);
Jeff Garzik5796d1c2007-10-26 00:03:37 -04001095 readw(mmio + NV_ADMA_CTL); /* flush posted write */
Robert Hancock53014e22007-05-05 15:36:36 -06001096}
1097
Robert Hancockfbbb2622006-10-27 19:08:41 -07001098static void nv_adma_irq_clear(struct ata_port *ap)
1099{
Robert Hancockcdf56bc2007-01-03 18:13:57 -06001100 struct nv_adma_port_priv *pp = ap->private_data;
1101 void __iomem *mmio = pp->ctl_block;
Robert Hancock53014e22007-05-05 15:36:36 -06001102 u32 notifier_clears[2];
1103
1104 if (pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE) {
Tejun Heo37f65b82010-05-19 22:10:20 +02001105 ata_bmdma_irq_clear(ap);
Robert Hancock53014e22007-05-05 15:36:36 -06001106 return;
1107 }
1108
1109 /* clear any outstanding CK804 notifications */
Jeff Garzik2dcb4072007-10-19 06:42:56 -04001110 writeb(NV_INT_ALL << (ap->port_no * NV_INT_PORT_SHIFT),
Robert Hancock53014e22007-05-05 15:36:36 -06001111 ap->host->iomap[NV_MMIO_BAR] + NV_INT_STATUS_CK804);
Robert Hancockfbbb2622006-10-27 19:08:41 -07001112
1113 /* clear ADMA status */
Robert Hancock53014e22007-05-05 15:36:36 -06001114 writew(0xffff, mmio + NV_ADMA_STAT);
Jeff Garzika617c092007-05-21 20:14:23 -04001115
Robert Hancock53014e22007-05-05 15:36:36 -06001116 /* clear notifiers - note both ports need to be written with
1117 something even though we are only clearing on one */
1118 if (ap->port_no == 0) {
1119 notifier_clears[0] = 0xFFFFFFFF;
1120 notifier_clears[1] = 0;
1121 } else {
1122 notifier_clears[0] = 0;
1123 notifier_clears[1] = 0xFFFFFFFF;
1124 }
1125 pp = ap->host->ports[0]->private_data;
1126 writel(notifier_clears[0], pp->notifier_clear_block);
1127 pp = ap->host->ports[1]->private_data;
1128 writel(notifier_clears[1], pp->notifier_clear_block);
Robert Hancockfbbb2622006-10-27 19:08:41 -07001129}
1130
Robert Hancockf5ecac22007-02-20 21:49:10 -06001131static void nv_adma_post_internal_cmd(struct ata_queued_cmd *qc)
Robert Hancockfbbb2622006-10-27 19:08:41 -07001132{
Robert Hancockf5ecac22007-02-20 21:49:10 -06001133 struct nv_adma_port_priv *pp = qc->ap->private_data;
Robert Hancockfbbb2622006-10-27 19:08:41 -07001134
Jeff Garzikb4479162007-10-25 20:47:30 -04001135 if (pp->flags & NV_ADMA_PORT_REGISTER_MODE)
Tejun Heofe06e5f2010-05-10 21:41:39 +02001136 ata_bmdma_post_internal_cmd(qc);
Robert Hancockfbbb2622006-10-27 19:08:41 -07001137}
1138
1139static int nv_adma_port_start(struct ata_port *ap)
1140{
1141 struct device *dev = ap->host->dev;
1142 struct nv_adma_port_priv *pp;
1143 int rc;
1144 void *mem;
1145 dma_addr_t mem_dma;
Robert Hancockcdf56bc2007-01-03 18:13:57 -06001146 void __iomem *mmio;
Robert Hancock8959d302008-02-04 19:39:02 -06001147 struct pci_dev *pdev = to_pci_dev(dev);
Robert Hancockfbbb2622006-10-27 19:08:41 -07001148 u16 tmp;
1149
1150 VPRINTK("ENTER\n");
1151
Robert Hancock8959d302008-02-04 19:39:02 -06001152 /* Ensure DMA mask is set to 32-bit before allocating legacy PRD and
1153 pad buffers */
1154 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1155 if (rc)
1156 return rc;
1157 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1158 if (rc)
1159 return rc;
1160
Tejun Heoc7087652010-05-10 21:41:34 +02001161 /* we might fallback to bmdma, allocate bmdma resources */
1162 rc = ata_bmdma_port_start(ap);
Robert Hancockfbbb2622006-10-27 19:08:41 -07001163 if (rc)
1164 return rc;
1165
Tejun Heo24dc5f32007-01-20 16:00:28 +09001166 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
1167 if (!pp)
1168 return -ENOMEM;
Robert Hancockfbbb2622006-10-27 19:08:41 -07001169
Tejun Heo0d5ff562007-02-01 15:06:36 +09001170 mmio = ap->host->iomap[NV_MMIO_BAR] + NV_ADMA_PORT +
Robert Hancockcdf56bc2007-01-03 18:13:57 -06001171 ap->port_no * NV_ADMA_PORT_SIZE;
1172 pp->ctl_block = mmio;
Tejun Heo0d5ff562007-02-01 15:06:36 +09001173 pp->gen_block = ap->host->iomap[NV_MMIO_BAR] + NV_ADMA_GEN;
Robert Hancockcdf56bc2007-01-03 18:13:57 -06001174 pp->notifier_clear_block = pp->gen_block +
1175 NV_ADMA_NOTIFIER_CLEAR + (4 * ap->port_no);
1176
Robert Hancock8959d302008-02-04 19:39:02 -06001177 /* Now that the legacy PRD and padding buffer are allocated we can
1178 safely raise the DMA mask to allocate the CPB/APRD table.
1179 These are allowed to fail since we store the value that ends up
1180 being used to set as the bounce limit in slave_config later if
1181 needed. */
1182 pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
1183 pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
1184 pp->adma_dma_mask = *dev->dma_mask;
1185
Tejun Heo24dc5f32007-01-20 16:00:28 +09001186 mem = dmam_alloc_coherent(dev, NV_ADMA_PORT_PRIV_DMA_SZ,
1187 &mem_dma, GFP_KERNEL);
1188 if (!mem)
1189 return -ENOMEM;
Robert Hancockfbbb2622006-10-27 19:08:41 -07001190 memset(mem, 0, NV_ADMA_PORT_PRIV_DMA_SZ);
1191
1192 /*
1193 * First item in chunk of DMA memory:
1194 * 128-byte command parameter block (CPB)
1195 * one for each command tag
1196 */
1197 pp->cpb = mem;
1198 pp->cpb_dma = mem_dma;
1199
1200 writel(mem_dma & 0xFFFFFFFF, mmio + NV_ADMA_CPB_BASE_LOW);
Jeff Garzik5796d1c2007-10-26 00:03:37 -04001201 writel((mem_dma >> 16) >> 16, mmio + NV_ADMA_CPB_BASE_HIGH);
Robert Hancockfbbb2622006-10-27 19:08:41 -07001202
1203 mem += NV_ADMA_MAX_CPBS * NV_ADMA_CPB_SZ;
1204 mem_dma += NV_ADMA_MAX_CPBS * NV_ADMA_CPB_SZ;
1205
1206 /*
1207 * Second item: block of ADMA_SGTBL_LEN s/g entries
1208 */
1209 pp->aprd = mem;
1210 pp->aprd_dma = mem_dma;
1211
1212 ap->private_data = pp;
1213
1214 /* clear any outstanding interrupt conditions */
1215 writew(0xffff, mmio + NV_ADMA_STAT);
1216
1217 /* initialize port variables */
1218 pp->flags = NV_ADMA_PORT_REGISTER_MODE;
1219
1220 /* clear CPB fetch count */
1221 writew(0, mmio + NV_ADMA_CPB_COUNT);
1222
Robert Hancockcdf56bc2007-01-03 18:13:57 -06001223 /* clear GO for register mode, enable interrupt */
Robert Hancockfbbb2622006-10-27 19:08:41 -07001224 tmp = readw(mmio + NV_ADMA_CTL);
Jeff Garzik5796d1c2007-10-26 00:03:37 -04001225 writew((tmp & ~NV_ADMA_CTL_GO) | NV_ADMA_CTL_AIEN |
1226 NV_ADMA_CTL_HOTPLUG_IEN, mmio + NV_ADMA_CTL);
Robert Hancockfbbb2622006-10-27 19:08:41 -07001227
1228 tmp = readw(mmio + NV_ADMA_CTL);
1229 writew(tmp | NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);
Jeff Garzik5796d1c2007-10-26 00:03:37 -04001230 readw(mmio + NV_ADMA_CTL); /* flush posted write */
Robert Hancockfbbb2622006-10-27 19:08:41 -07001231 udelay(1);
1232 writew(tmp & ~NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);
Jeff Garzik5796d1c2007-10-26 00:03:37 -04001233 readw(mmio + NV_ADMA_CTL); /* flush posted write */
Robert Hancockfbbb2622006-10-27 19:08:41 -07001234
1235 return 0;
Robert Hancockfbbb2622006-10-27 19:08:41 -07001236}
1237
1238static void nv_adma_port_stop(struct ata_port *ap)
1239{
Robert Hancockfbbb2622006-10-27 19:08:41 -07001240 struct nv_adma_port_priv *pp = ap->private_data;
Robert Hancockcdf56bc2007-01-03 18:13:57 -06001241 void __iomem *mmio = pp->ctl_block;
Robert Hancockfbbb2622006-10-27 19:08:41 -07001242
1243 VPRINTK("ENTER\n");
Robert Hancockfbbb2622006-10-27 19:08:41 -07001244 writew(0, mmio + NV_ADMA_CTL);
Robert Hancockfbbb2622006-10-27 19:08:41 -07001245}
1246
Tejun Heo438ac6d2007-03-02 17:31:26 +09001247#ifdef CONFIG_PM
Robert Hancockcdf56bc2007-01-03 18:13:57 -06001248static int nv_adma_port_suspend(struct ata_port *ap, pm_message_t mesg)
1249{
1250 struct nv_adma_port_priv *pp = ap->private_data;
1251 void __iomem *mmio = pp->ctl_block;
1252
1253 /* Go to register mode - clears GO */
1254 nv_adma_register_mode(ap);
1255
1256 /* clear CPB fetch count */
1257 writew(0, mmio + NV_ADMA_CPB_COUNT);
1258
1259 /* disable interrupt, shut down port */
1260 writew(0, mmio + NV_ADMA_CTL);
1261
1262 return 0;
1263}
1264
1265static int nv_adma_port_resume(struct ata_port *ap)
1266{
1267 struct nv_adma_port_priv *pp = ap->private_data;
1268 void __iomem *mmio = pp->ctl_block;
1269 u16 tmp;
1270
1271 /* set CPB block location */
1272 writel(pp->cpb_dma & 0xFFFFFFFF, mmio + NV_ADMA_CPB_BASE_LOW);
Jeff Garzik5796d1c2007-10-26 00:03:37 -04001273 writel((pp->cpb_dma >> 16) >> 16, mmio + NV_ADMA_CPB_BASE_HIGH);
Robert Hancockcdf56bc2007-01-03 18:13:57 -06001274
1275 /* clear any outstanding interrupt conditions */
1276 writew(0xffff, mmio + NV_ADMA_STAT);
1277
1278 /* initialize port variables */
1279 pp->flags |= NV_ADMA_PORT_REGISTER_MODE;
1280
1281 /* clear CPB fetch count */
1282 writew(0, mmio + NV_ADMA_CPB_COUNT);
1283
1284 /* clear GO for register mode, enable interrupt */
1285 tmp = readw(mmio + NV_ADMA_CTL);
Jeff Garzik5796d1c2007-10-26 00:03:37 -04001286 writew((tmp & ~NV_ADMA_CTL_GO) | NV_ADMA_CTL_AIEN |
1287 NV_ADMA_CTL_HOTPLUG_IEN, mmio + NV_ADMA_CTL);
Robert Hancockcdf56bc2007-01-03 18:13:57 -06001288
1289 tmp = readw(mmio + NV_ADMA_CTL);
1290 writew(tmp | NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);
Jeff Garzik5796d1c2007-10-26 00:03:37 -04001291 readw(mmio + NV_ADMA_CTL); /* flush posted write */
Robert Hancockcdf56bc2007-01-03 18:13:57 -06001292 udelay(1);
1293 writew(tmp & ~NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);
Jeff Garzik5796d1c2007-10-26 00:03:37 -04001294 readw(mmio + NV_ADMA_CTL); /* flush posted write */
Robert Hancockcdf56bc2007-01-03 18:13:57 -06001295
1296 return 0;
1297}
Tejun Heo438ac6d2007-03-02 17:31:26 +09001298#endif
Robert Hancockfbbb2622006-10-27 19:08:41 -07001299
Tejun Heo9a829cc2007-04-17 23:44:08 +09001300static void nv_adma_setup_port(struct ata_port *ap)
Robert Hancockfbbb2622006-10-27 19:08:41 -07001301{
Tejun Heo9a829cc2007-04-17 23:44:08 +09001302 void __iomem *mmio = ap->host->iomap[NV_MMIO_BAR];
1303 struct ata_ioports *ioport = &ap->ioaddr;
Robert Hancockfbbb2622006-10-27 19:08:41 -07001304
1305 VPRINTK("ENTER\n");
1306
Tejun Heo9a829cc2007-04-17 23:44:08 +09001307 mmio += NV_ADMA_PORT + ap->port_no * NV_ADMA_PORT_SIZE;
Robert Hancockfbbb2622006-10-27 19:08:41 -07001308
Tejun Heo0d5ff562007-02-01 15:06:36 +09001309 ioport->cmd_addr = mmio;
1310 ioport->data_addr = mmio + (ATA_REG_DATA * 4);
Robert Hancockfbbb2622006-10-27 19:08:41 -07001311 ioport->error_addr =
Tejun Heo0d5ff562007-02-01 15:06:36 +09001312 ioport->feature_addr = mmio + (ATA_REG_ERR * 4);
1313 ioport->nsect_addr = mmio + (ATA_REG_NSECT * 4);
1314 ioport->lbal_addr = mmio + (ATA_REG_LBAL * 4);
1315 ioport->lbam_addr = mmio + (ATA_REG_LBAM * 4);
1316 ioport->lbah_addr = mmio + (ATA_REG_LBAH * 4);
1317 ioport->device_addr = mmio + (ATA_REG_DEVICE * 4);
Robert Hancockfbbb2622006-10-27 19:08:41 -07001318 ioport->status_addr =
Tejun Heo0d5ff562007-02-01 15:06:36 +09001319 ioport->command_addr = mmio + (ATA_REG_STATUS * 4);
Robert Hancockfbbb2622006-10-27 19:08:41 -07001320 ioport->altstatus_addr =
Tejun Heo0d5ff562007-02-01 15:06:36 +09001321 ioport->ctl_addr = mmio + 0x20;
Robert Hancockfbbb2622006-10-27 19:08:41 -07001322}
1323
Tejun Heo9a829cc2007-04-17 23:44:08 +09001324static int nv_adma_host_init(struct ata_host *host)
Robert Hancockfbbb2622006-10-27 19:08:41 -07001325{
Tejun Heo9a829cc2007-04-17 23:44:08 +09001326 struct pci_dev *pdev = to_pci_dev(host->dev);
Robert Hancockfbbb2622006-10-27 19:08:41 -07001327 unsigned int i;
1328 u32 tmp32;
1329
1330 VPRINTK("ENTER\n");
1331
1332 /* enable ADMA on the ports */
1333 pci_read_config_dword(pdev, NV_MCP_SATA_CFG_20, &tmp32);
1334 tmp32 |= NV_MCP_SATA_CFG_20_PORT0_EN |
1335 NV_MCP_SATA_CFG_20_PORT0_PWB_EN |
1336 NV_MCP_SATA_CFG_20_PORT1_EN |
1337 NV_MCP_SATA_CFG_20_PORT1_PWB_EN;
1338
1339 pci_write_config_dword(pdev, NV_MCP_SATA_CFG_20, tmp32);
1340
Tejun Heo9a829cc2007-04-17 23:44:08 +09001341 for (i = 0; i < host->n_ports; i++)
1342 nv_adma_setup_port(host->ports[i]);
Robert Hancockfbbb2622006-10-27 19:08:41 -07001343
Robert Hancockfbbb2622006-10-27 19:08:41 -07001344 return 0;
1345}
1346
1347static void nv_adma_fill_aprd(struct ata_queued_cmd *qc,
1348 struct scatterlist *sg,
1349 int idx,
1350 struct nv_adma_prd *aprd)
1351{
Robert Hancock41949ed2007-02-19 19:02:27 -06001352 u8 flags = 0;
Robert Hancockfbbb2622006-10-27 19:08:41 -07001353 if (qc->tf.flags & ATA_TFLAG_WRITE)
1354 flags |= NV_APRD_WRITE;
1355 if (idx == qc->n_elem - 1)
1356 flags |= NV_APRD_END;
1357 else if (idx != 4)
1358 flags |= NV_APRD_CONT;
1359
1360 aprd->addr = cpu_to_le64(((u64)sg_dma_address(sg)));
1361 aprd->len = cpu_to_le32(((u32)sg_dma_len(sg))); /* len in bytes */
Robert Hancock2dec7552006-11-26 14:20:19 -06001362 aprd->flags = flags;
Robert Hancock41949ed2007-02-19 19:02:27 -06001363 aprd->packet_len = 0;
Robert Hancockfbbb2622006-10-27 19:08:41 -07001364}
1365
1366static void nv_adma_fill_sg(struct ata_queued_cmd *qc, struct nv_adma_cpb *cpb)
1367{
1368 struct nv_adma_port_priv *pp = qc->ap->private_data;
Robert Hancockfbbb2622006-10-27 19:08:41 -07001369 struct nv_adma_prd *aprd;
1370 struct scatterlist *sg;
Tejun Heoff2aeb12007-12-05 16:43:11 +09001371 unsigned int si;
Robert Hancockfbbb2622006-10-27 19:08:41 -07001372
1373 VPRINTK("ENTER\n");
1374
Tejun Heoff2aeb12007-12-05 16:43:11 +09001375 for_each_sg(qc->sg, sg, qc->n_elem, si) {
1376 aprd = (si < 5) ? &cpb->aprd[si] :
1377 &pp->aprd[NV_ADMA_SGTBL_LEN * qc->tag + (si-5)];
1378 nv_adma_fill_aprd(qc, sg, si, aprd);
Robert Hancockfbbb2622006-10-27 19:08:41 -07001379 }
Tejun Heoff2aeb12007-12-05 16:43:11 +09001380 if (si > 5)
Robert Hancockfbbb2622006-10-27 19:08:41 -07001381 cpb->next_aprd = cpu_to_le64(((u64)(pp->aprd_dma + NV_ADMA_SGTBL_SZ * qc->tag)));
Robert Hancock41949ed2007-02-19 19:02:27 -06001382 else
1383 cpb->next_aprd = cpu_to_le64(0);
Robert Hancockfbbb2622006-10-27 19:08:41 -07001384}
1385
Robert Hancock382a6652007-02-05 16:26:02 -08001386static int nv_adma_use_reg_mode(struct ata_queued_cmd *qc)
1387{
1388 struct nv_adma_port_priv *pp = qc->ap->private_data;
1389
1390 /* ADMA engine can only be used for non-ATAPI DMA commands,
Robert Hancock3f3debd2007-11-25 16:59:36 -06001391 or interrupt-driven no-data commands. */
Jeff Garzikb4479162007-10-25 20:47:30 -04001392 if ((pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE) ||
Robert Hancock3f3debd2007-11-25 16:59:36 -06001393 (qc->tf.flags & ATA_TFLAG_POLLING))
Robert Hancock382a6652007-02-05 16:26:02 -08001394 return 1;
1395
Jeff Garzikb4479162007-10-25 20:47:30 -04001396 if ((qc->flags & ATA_QCFLAG_DMAMAP) ||
Robert Hancock382a6652007-02-05 16:26:02 -08001397 (qc->tf.protocol == ATA_PROT_NODATA))
1398 return 0;
1399
1400 return 1;
1401}
1402
Robert Hancockfbbb2622006-10-27 19:08:41 -07001403static void nv_adma_qc_prep(struct ata_queued_cmd *qc)
1404{
1405 struct nv_adma_port_priv *pp = qc->ap->private_data;
1406 struct nv_adma_cpb *cpb = &pp->cpb[qc->tag];
1407 u8 ctl_flags = NV_CPB_CTL_CPB_VALID |
Robert Hancockfbbb2622006-10-27 19:08:41 -07001408 NV_CPB_CTL_IEN;
1409
Robert Hancock382a6652007-02-05 16:26:02 -08001410 if (nv_adma_use_reg_mode(qc)) {
Robert Hancock3f3debd2007-11-25 16:59:36 -06001411 BUG_ON(!(pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE) &&
1412 (qc->flags & ATA_QCFLAG_DMAMAP));
Robert Hancock2dec7552006-11-26 14:20:19 -06001413 nv_adma_register_mode(qc->ap);
Tejun Heof47451c2010-05-10 21:41:40 +02001414 ata_bmdma_qc_prep(qc);
Robert Hancockfbbb2622006-10-27 19:08:41 -07001415 return;
1416 }
1417
Robert Hancock41949ed2007-02-19 19:02:27 -06001418 cpb->resp_flags = NV_CPB_RESP_DONE;
1419 wmb();
1420 cpb->ctl_flags = 0;
1421 wmb();
Robert Hancockfbbb2622006-10-27 19:08:41 -07001422
1423 cpb->len = 3;
1424 cpb->tag = qc->tag;
1425 cpb->next_cpb_idx = 0;
1426
1427 /* turn on NCQ flags for NCQ commands */
1428 if (qc->tf.protocol == ATA_PROT_NCQ)
1429 ctl_flags |= NV_CPB_CTL_QUEUE | NV_CPB_CTL_FPDMA;
1430
Robert Hancockcdf56bc2007-01-03 18:13:57 -06001431 VPRINTK("qc->flags = 0x%lx\n", qc->flags);
1432
Robert Hancockfbbb2622006-10-27 19:08:41 -07001433 nv_adma_tf_to_cpb(&qc->tf, cpb->tf);
1434
Jeff Garzikb4479162007-10-25 20:47:30 -04001435 if (qc->flags & ATA_QCFLAG_DMAMAP) {
Robert Hancock382a6652007-02-05 16:26:02 -08001436 nv_adma_fill_sg(qc, cpb);
1437 ctl_flags |= NV_CPB_CTL_APRD_VALID;
1438 } else
1439 memset(&cpb->aprd[0], 0, sizeof(struct nv_adma_prd) * 5);
Robert Hancockfbbb2622006-10-27 19:08:41 -07001440
Jeff Garzik5796d1c2007-10-26 00:03:37 -04001441 /* Be paranoid and don't let the device see NV_CPB_CTL_CPB_VALID
1442 until we are finished filling in all of the contents */
Robert Hancockfbbb2622006-10-27 19:08:41 -07001443 wmb();
1444 cpb->ctl_flags = ctl_flags;
Robert Hancock41949ed2007-02-19 19:02:27 -06001445 wmb();
1446 cpb->resp_flags = 0;
Robert Hancockfbbb2622006-10-27 19:08:41 -07001447}
1448
1449static unsigned int nv_adma_qc_issue(struct ata_queued_cmd *qc)
1450{
Robert Hancock2dec7552006-11-26 14:20:19 -06001451 struct nv_adma_port_priv *pp = qc->ap->private_data;
Robert Hancockcdf56bc2007-01-03 18:13:57 -06001452 void __iomem *mmio = pp->ctl_block;
Robert Hancock5e5c74a2007-02-19 18:42:30 -06001453 int curr_ncq = (qc->tf.protocol == ATA_PROT_NCQ);
Robert Hancockfbbb2622006-10-27 19:08:41 -07001454
1455 VPRINTK("ENTER\n");
1456
Robert Hancock3f3debd2007-11-25 16:59:36 -06001457 /* We can't handle result taskfile with NCQ commands, since
1458 retrieving the taskfile switches us out of ADMA mode and would abort
1459 existing commands. */
1460 if (unlikely(qc->tf.protocol == ATA_PROT_NCQ &&
1461 (qc->flags & ATA_QCFLAG_RESULT_TF))) {
1462 ata_dev_printk(qc->dev, KERN_ERR,
1463 "NCQ w/ RESULT_TF not allowed\n");
1464 return AC_ERR_SYSTEM;
1465 }
1466
Robert Hancock382a6652007-02-05 16:26:02 -08001467 if (nv_adma_use_reg_mode(qc)) {
Robert Hancockfbbb2622006-10-27 19:08:41 -07001468 /* use ATA register mode */
Robert Hancock382a6652007-02-05 16:26:02 -08001469 VPRINTK("using ATA register mode: 0x%lx\n", qc->flags);
Robert Hancock3f3debd2007-11-25 16:59:36 -06001470 BUG_ON(!(pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE) &&
1471 (qc->flags & ATA_QCFLAG_DMAMAP));
Robert Hancockfbbb2622006-10-27 19:08:41 -07001472 nv_adma_register_mode(qc->ap);
Tejun Heo360ff782010-05-10 21:41:42 +02001473 return ata_bmdma_qc_issue(qc);
Robert Hancockfbbb2622006-10-27 19:08:41 -07001474 } else
1475 nv_adma_mode(qc->ap);
1476
1477 /* write append register, command tag in lower 8 bits
1478 and (number of cpbs to append -1) in top 8 bits */
1479 wmb();
Robert Hancock5e5c74a2007-02-19 18:42:30 -06001480
Jeff Garzikb4479162007-10-25 20:47:30 -04001481 if (curr_ncq != pp->last_issue_ncq) {
Jeff Garzik5796d1c2007-10-26 00:03:37 -04001482 /* Seems to need some delay before switching between NCQ and
1483 non-NCQ commands, else we get command timeouts and such. */
Robert Hancock5e5c74a2007-02-19 18:42:30 -06001484 udelay(20);
1485 pp->last_issue_ncq = curr_ncq;
1486 }
1487
Robert Hancockfbbb2622006-10-27 19:08:41 -07001488 writew(qc->tag, mmio + NV_ADMA_APPEND);
1489
Jeff Garzik5796d1c2007-10-26 00:03:37 -04001490 DPRINTK("Issued tag %u\n", qc->tag);
Robert Hancockfbbb2622006-10-27 19:08:41 -07001491
1492 return 0;
1493}
1494
David Howells7d12e782006-10-05 14:55:46 +01001495static irqreturn_t nv_generic_interrupt(int irq, void *dev_instance)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001496{
Jeff Garzikcca39742006-08-24 03:19:22 -04001497 struct ata_host *host = dev_instance;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001498 unsigned int i;
1499 unsigned int handled = 0;
1500 unsigned long flags;
1501
Jeff Garzikcca39742006-08-24 03:19:22 -04001502 spin_lock_irqsave(&host->lock, flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001503
Jeff Garzikcca39742006-08-24 03:19:22 -04001504 for (i = 0; i < host->n_ports; i++) {
Tejun Heo3e4ec342010-05-10 21:41:30 +02001505 struct ata_port *ap = host->ports[i];
1506 struct ata_queued_cmd *qc;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001507
Tejun Heo3e4ec342010-05-10 21:41:30 +02001508 qc = ata_qc_from_tag(ap, ap->link.active_tag);
1509 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) {
Tejun Heoc3b28892010-05-19 22:10:21 +02001510 handled += ata_bmdma_port_intr(ap, qc);
Tejun Heo3e4ec342010-05-10 21:41:30 +02001511 } else {
1512 /*
1513 * No request pending? Clear interrupt status
1514 * anyway, in case there's one pending.
1515 */
1516 ap->ops->sff_check_status(ap);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001517 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001518 }
1519
Jeff Garzikcca39742006-08-24 03:19:22 -04001520 spin_unlock_irqrestore(&host->lock, flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001521
1522 return IRQ_RETVAL(handled);
1523}
1524
Jeff Garzikcca39742006-08-24 03:19:22 -04001525static irqreturn_t nv_do_interrupt(struct ata_host *host, u8 irq_stat)
Tejun Heoada364e2006-06-17 15:49:56 +09001526{
1527 int i, handled = 0;
1528
Jeff Garzikcca39742006-08-24 03:19:22 -04001529 for (i = 0; i < host->n_ports; i++) {
Tejun Heo3e4ec342010-05-10 21:41:30 +02001530 handled += nv_host_intr(host->ports[i], irq_stat);
Tejun Heoada364e2006-06-17 15:49:56 +09001531 irq_stat >>= NV_INT_PORT_SHIFT;
1532 }
1533
1534 return IRQ_RETVAL(handled);
1535}
1536
David Howells7d12e782006-10-05 14:55:46 +01001537static irqreturn_t nv_nf2_interrupt(int irq, void *dev_instance)
Tejun Heoada364e2006-06-17 15:49:56 +09001538{
Jeff Garzikcca39742006-08-24 03:19:22 -04001539 struct ata_host *host = dev_instance;
Tejun Heoada364e2006-06-17 15:49:56 +09001540 u8 irq_stat;
1541 irqreturn_t ret;
1542
Jeff Garzikcca39742006-08-24 03:19:22 -04001543 spin_lock(&host->lock);
Tejun Heo0d5ff562007-02-01 15:06:36 +09001544 irq_stat = ioread8(host->ports[0]->ioaddr.scr_addr + NV_INT_STATUS);
Jeff Garzikcca39742006-08-24 03:19:22 -04001545 ret = nv_do_interrupt(host, irq_stat);
1546 spin_unlock(&host->lock);
Tejun Heoada364e2006-06-17 15:49:56 +09001547
1548 return ret;
1549}
1550
David Howells7d12e782006-10-05 14:55:46 +01001551static irqreturn_t nv_ck804_interrupt(int irq, void *dev_instance)
Tejun Heoada364e2006-06-17 15:49:56 +09001552{
Jeff Garzikcca39742006-08-24 03:19:22 -04001553 struct ata_host *host = dev_instance;
Tejun Heoada364e2006-06-17 15:49:56 +09001554 u8 irq_stat;
1555 irqreturn_t ret;
1556
Jeff Garzikcca39742006-08-24 03:19:22 -04001557 spin_lock(&host->lock);
Tejun Heo0d5ff562007-02-01 15:06:36 +09001558 irq_stat = readb(host->iomap[NV_MMIO_BAR] + NV_INT_STATUS_CK804);
Jeff Garzikcca39742006-08-24 03:19:22 -04001559 ret = nv_do_interrupt(host, irq_stat);
1560 spin_unlock(&host->lock);
Tejun Heoada364e2006-06-17 15:49:56 +09001561
1562 return ret;
1563}
1564
Tejun Heo82ef04f2008-07-31 17:02:40 +09001565static int nv_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001566{
Linus Torvalds1da177e2005-04-16 15:20:36 -07001567 if (sc_reg > SCR_CONTROL)
Tejun Heoda3dbb12007-07-16 14:29:40 +09001568 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001569
Tejun Heo82ef04f2008-07-31 17:02:40 +09001570 *val = ioread32(link->ap->ioaddr.scr_addr + (sc_reg * 4));
Tejun Heoda3dbb12007-07-16 14:29:40 +09001571 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001572}
1573
Tejun Heo82ef04f2008-07-31 17:02:40 +09001574static int nv_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001575{
Linus Torvalds1da177e2005-04-16 15:20:36 -07001576 if (sc_reg > SCR_CONTROL)
Tejun Heoda3dbb12007-07-16 14:29:40 +09001577 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001578
Tejun Heo82ef04f2008-07-31 17:02:40 +09001579 iowrite32(val, link->ap->ioaddr.scr_addr + (sc_reg * 4));
Tejun Heoda3dbb12007-07-16 14:29:40 +09001580 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001581}
1582
Tejun Heo7f4774b2009-06-10 16:29:07 +09001583static int nv_hardreset(struct ata_link *link, unsigned int *class,
1584 unsigned long deadline)
Tejun Heoe8caa3c2009-01-25 11:25:22 +09001585{
Tejun Heo7f4774b2009-06-10 16:29:07 +09001586 struct ata_eh_context *ehc = &link->eh_context;
Tejun Heoe8caa3c2009-01-25 11:25:22 +09001587
Tejun Heo7f4774b2009-06-10 16:29:07 +09001588 /* Do hardreset iff it's post-boot probing, please read the
1589 * comment above port ops for details.
1590 */
1591 if (!(link->ap->pflags & ATA_PFLAG_LOADING) &&
1592 !ata_dev_enabled(link->device))
1593 sata_link_hardreset(link, sata_deb_timing_hotplug, deadline,
1594 NULL, NULL);
Tejun Heo6489e322009-10-14 11:18:28 +09001595 else {
1596 const unsigned long *timing = sata_ehc_deb_timing(ehc);
1597 int rc;
1598
1599 if (!(ehc->i.flags & ATA_EHI_QUIET))
1600 ata_link_printk(link, KERN_INFO, "nv: skipping "
1601 "hardreset on occupied port\n");
1602
1603 /* make sure the link is online */
1604 rc = sata_link_resume(link, timing, deadline);
1605 /* whine about phy resume failure but proceed */
1606 if (rc && rc != -EOPNOTSUPP)
1607 ata_link_printk(link, KERN_WARNING, "failed to resume "
1608 "link (errno=%d)\n", rc);
1609 }
Tejun Heo7f4774b2009-06-10 16:29:07 +09001610
1611 /* device signature acquisition is unreliable */
1612 return -EAGAIN;
Tejun Heoe8caa3c2009-01-25 11:25:22 +09001613}
1614
Tejun Heo39f87582006-06-17 15:49:56 +09001615static void nv_nf2_freeze(struct ata_port *ap)
1616{
Tejun Heo0d5ff562007-02-01 15:06:36 +09001617 void __iomem *scr_addr = ap->host->ports[0]->ioaddr.scr_addr;
Tejun Heo39f87582006-06-17 15:49:56 +09001618 int shift = ap->port_no * NV_INT_PORT_SHIFT;
1619 u8 mask;
1620
Tejun Heo0d5ff562007-02-01 15:06:36 +09001621 mask = ioread8(scr_addr + NV_INT_ENABLE);
Tejun Heo39f87582006-06-17 15:49:56 +09001622 mask &= ~(NV_INT_ALL << shift);
Tejun Heo0d5ff562007-02-01 15:06:36 +09001623 iowrite8(mask, scr_addr + NV_INT_ENABLE);
Tejun Heo39f87582006-06-17 15:49:56 +09001624}
1625
1626static void nv_nf2_thaw(struct ata_port *ap)
1627{
Tejun Heo0d5ff562007-02-01 15:06:36 +09001628 void __iomem *scr_addr = ap->host->ports[0]->ioaddr.scr_addr;
Tejun Heo39f87582006-06-17 15:49:56 +09001629 int shift = ap->port_no * NV_INT_PORT_SHIFT;
1630 u8 mask;
1631
Tejun Heo0d5ff562007-02-01 15:06:36 +09001632 iowrite8(NV_INT_ALL << shift, scr_addr + NV_INT_STATUS);
Tejun Heo39f87582006-06-17 15:49:56 +09001633
Tejun Heo0d5ff562007-02-01 15:06:36 +09001634 mask = ioread8(scr_addr + NV_INT_ENABLE);
Tejun Heo39f87582006-06-17 15:49:56 +09001635 mask |= (NV_INT_MASK << shift);
Tejun Heo0d5ff562007-02-01 15:06:36 +09001636 iowrite8(mask, scr_addr + NV_INT_ENABLE);
Tejun Heo39f87582006-06-17 15:49:56 +09001637}
1638
1639static void nv_ck804_freeze(struct ata_port *ap)
1640{
Tejun Heo0d5ff562007-02-01 15:06:36 +09001641 void __iomem *mmio_base = ap->host->iomap[NV_MMIO_BAR];
Tejun Heo39f87582006-06-17 15:49:56 +09001642 int shift = ap->port_no * NV_INT_PORT_SHIFT;
1643 u8 mask;
1644
1645 mask = readb(mmio_base + NV_INT_ENABLE_CK804);
1646 mask &= ~(NV_INT_ALL << shift);
1647 writeb(mask, mmio_base + NV_INT_ENABLE_CK804);
1648}
1649
1650static void nv_ck804_thaw(struct ata_port *ap)
1651{
Tejun Heo0d5ff562007-02-01 15:06:36 +09001652 void __iomem *mmio_base = ap->host->iomap[NV_MMIO_BAR];
Tejun Heo39f87582006-06-17 15:49:56 +09001653 int shift = ap->port_no * NV_INT_PORT_SHIFT;
1654 u8 mask;
1655
1656 writeb(NV_INT_ALL << shift, mmio_base + NV_INT_STATUS_CK804);
1657
1658 mask = readb(mmio_base + NV_INT_ENABLE_CK804);
1659 mask |= (NV_INT_MASK << shift);
1660 writeb(mask, mmio_base + NV_INT_ENABLE_CK804);
1661}
1662
Kuan Luof140f0f2007-10-15 15:16:53 -04001663static void nv_mcp55_freeze(struct ata_port *ap)
1664{
1665 void __iomem *mmio_base = ap->host->iomap[NV_MMIO_BAR];
1666 int shift = ap->port_no * NV_INT_PORT_SHIFT_MCP55;
1667 u32 mask;
1668
1669 writel(NV_INT_ALL_MCP55 << shift, mmio_base + NV_INT_STATUS_MCP55);
1670
1671 mask = readl(mmio_base + NV_INT_ENABLE_MCP55);
1672 mask &= ~(NV_INT_ALL_MCP55 << shift);
1673 writel(mask, mmio_base + NV_INT_ENABLE_MCP55);
Kuan Luof140f0f2007-10-15 15:16:53 -04001674}
1675
1676static void nv_mcp55_thaw(struct ata_port *ap)
1677{
1678 void __iomem *mmio_base = ap->host->iomap[NV_MMIO_BAR];
1679 int shift = ap->port_no * NV_INT_PORT_SHIFT_MCP55;
1680 u32 mask;
1681
1682 writel(NV_INT_ALL_MCP55 << shift, mmio_base + NV_INT_STATUS_MCP55);
1683
1684 mask = readl(mmio_base + NV_INT_ENABLE_MCP55);
1685 mask |= (NV_INT_MASK_MCP55 << shift);
1686 writel(mask, mmio_base + NV_INT_ENABLE_MCP55);
Kuan Luof140f0f2007-10-15 15:16:53 -04001687}
1688
Robert Hancockfbbb2622006-10-27 19:08:41 -07001689static void nv_adma_error_handler(struct ata_port *ap)
1690{
1691 struct nv_adma_port_priv *pp = ap->private_data;
Jeff Garzikb4479162007-10-25 20:47:30 -04001692 if (!(pp->flags & NV_ADMA_PORT_REGISTER_MODE)) {
Robert Hancockcdf56bc2007-01-03 18:13:57 -06001693 void __iomem *mmio = pp->ctl_block;
Robert Hancockfbbb2622006-10-27 19:08:41 -07001694 int i;
1695 u16 tmp;
Jeff Garzika84471f2007-02-26 05:51:33 -05001696
Jeff Garzikb4479162007-10-25 20:47:30 -04001697 if (ata_tag_valid(ap->link.active_tag) || ap->link.sactive) {
Robert Hancock2cb27852007-02-11 18:34:44 -06001698 u32 notifier = readl(mmio + NV_ADMA_NOTIFIER);
1699 u32 notifier_error = readl(mmio + NV_ADMA_NOTIFIER_ERROR);
1700 u32 gen_ctl = readl(pp->gen_block + NV_ADMA_GEN_CTL);
1701 u32 status = readw(mmio + NV_ADMA_STAT);
Robert Hancock08af7412007-02-19 19:01:59 -06001702 u8 cpb_count = readb(mmio + NV_ADMA_CPB_COUNT);
1703 u8 next_cpb_idx = readb(mmio + NV_ADMA_NEXT_CPB_IDX);
Robert Hancock2cb27852007-02-11 18:34:44 -06001704
Jeff Garzik5796d1c2007-10-26 00:03:37 -04001705 ata_port_printk(ap, KERN_ERR,
1706 "EH in ADMA mode, notifier 0x%X "
Robert Hancock08af7412007-02-19 19:01:59 -06001707 "notifier_error 0x%X gen_ctl 0x%X status 0x%X "
1708 "next cpb count 0x%X next cpb idx 0x%x\n",
1709 notifier, notifier_error, gen_ctl, status,
1710 cpb_count, next_cpb_idx);
Robert Hancock2cb27852007-02-11 18:34:44 -06001711
Jeff Garzikb4479162007-10-25 20:47:30 -04001712 for (i = 0; i < NV_ADMA_MAX_CPBS; i++) {
Robert Hancock2cb27852007-02-11 18:34:44 -06001713 struct nv_adma_cpb *cpb = &pp->cpb[i];
Jeff Garzikb4479162007-10-25 20:47:30 -04001714 if ((ata_tag_valid(ap->link.active_tag) && i == ap->link.active_tag) ||
Jeff Garzik5796d1c2007-10-26 00:03:37 -04001715 ap->link.sactive & (1 << i))
Robert Hancock2cb27852007-02-11 18:34:44 -06001716 ata_port_printk(ap, KERN_ERR,
1717 "CPB %d: ctl_flags 0x%x, resp_flags 0x%x\n",
1718 i, cpb->ctl_flags, cpb->resp_flags);
1719 }
1720 }
Robert Hancockfbbb2622006-10-27 19:08:41 -07001721
Robert Hancockfbbb2622006-10-27 19:08:41 -07001722 /* Push us back into port register mode for error handling. */
1723 nv_adma_register_mode(ap);
1724
Jeff Garzik5796d1c2007-10-26 00:03:37 -04001725 /* Mark all of the CPBs as invalid to prevent them from
1726 being executed */
Jeff Garzikb4479162007-10-25 20:47:30 -04001727 for (i = 0; i < NV_ADMA_MAX_CPBS; i++)
Robert Hancockfbbb2622006-10-27 19:08:41 -07001728 pp->cpb[i].ctl_flags &= ~NV_CPB_CTL_CPB_VALID;
1729
1730 /* clear CPB fetch count */
1731 writew(0, mmio + NV_ADMA_CPB_COUNT);
1732
1733 /* Reset channel */
1734 tmp = readw(mmio + NV_ADMA_CTL);
1735 writew(tmp | NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);
Jeff Garzikb4479162007-10-25 20:47:30 -04001736 readw(mmio + NV_ADMA_CTL); /* flush posted write */
Robert Hancockfbbb2622006-10-27 19:08:41 -07001737 udelay(1);
1738 writew(tmp & ~NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);
Jeff Garzikb4479162007-10-25 20:47:30 -04001739 readw(mmio + NV_ADMA_CTL); /* flush posted write */
Robert Hancockfbbb2622006-10-27 19:08:41 -07001740 }
1741
Tejun Heofe06e5f2010-05-10 21:41:39 +02001742 ata_bmdma_error_handler(ap);
Robert Hancockfbbb2622006-10-27 19:08:41 -07001743}
1744
Kuan Luof140f0f2007-10-15 15:16:53 -04001745static void nv_swncq_qc_to_dq(struct ata_port *ap, struct ata_queued_cmd *qc)
1746{
1747 struct nv_swncq_port_priv *pp = ap->private_data;
1748 struct defer_queue *dq = &pp->defer_queue;
1749
1750 /* queue is full */
1751 WARN_ON(dq->tail - dq->head == ATA_MAX_QUEUE);
1752 dq->defer_bits |= (1 << qc->tag);
1753 dq->tag[dq->tail++ & (ATA_MAX_QUEUE - 1)] = qc->tag;
1754}
1755
1756static struct ata_queued_cmd *nv_swncq_qc_from_dq(struct ata_port *ap)
1757{
1758 struct nv_swncq_port_priv *pp = ap->private_data;
1759 struct defer_queue *dq = &pp->defer_queue;
1760 unsigned int tag;
1761
1762 if (dq->head == dq->tail) /* null queue */
1763 return NULL;
1764
1765 tag = dq->tag[dq->head & (ATA_MAX_QUEUE - 1)];
1766 dq->tag[dq->head++ & (ATA_MAX_QUEUE - 1)] = ATA_TAG_POISON;
1767 WARN_ON(!(dq->defer_bits & (1 << tag)));
1768 dq->defer_bits &= ~(1 << tag);
1769
1770 return ata_qc_from_tag(ap, tag);
1771}
1772
1773static void nv_swncq_fis_reinit(struct ata_port *ap)
1774{
1775 struct nv_swncq_port_priv *pp = ap->private_data;
1776
1777 pp->dhfis_bits = 0;
1778 pp->dmafis_bits = 0;
1779 pp->sdbfis_bits = 0;
1780 pp->ncq_flags = 0;
1781}
1782
1783static void nv_swncq_pp_reinit(struct ata_port *ap)
1784{
1785 struct nv_swncq_port_priv *pp = ap->private_data;
1786 struct defer_queue *dq = &pp->defer_queue;
1787
1788 dq->head = 0;
1789 dq->tail = 0;
1790 dq->defer_bits = 0;
1791 pp->qc_active = 0;
1792 pp->last_issue_tag = ATA_TAG_POISON;
1793 nv_swncq_fis_reinit(ap);
1794}
1795
1796static void nv_swncq_irq_clear(struct ata_port *ap, u16 fis)
1797{
1798 struct nv_swncq_port_priv *pp = ap->private_data;
1799
1800 writew(fis, pp->irq_block);
1801}
1802
1803static void __ata_bmdma_stop(struct ata_port *ap)
1804{
1805 struct ata_queued_cmd qc;
1806
1807 qc.ap = ap;
1808 ata_bmdma_stop(&qc);
1809}
1810
1811static void nv_swncq_ncq_stop(struct ata_port *ap)
1812{
1813 struct nv_swncq_port_priv *pp = ap->private_data;
1814 unsigned int i;
1815 u32 sactive;
1816 u32 done_mask;
1817
1818 ata_port_printk(ap, KERN_ERR,
1819 "EH in SWNCQ mode,QC:qc_active 0x%X sactive 0x%X\n",
1820 ap->qc_active, ap->link.sactive);
1821 ata_port_printk(ap, KERN_ERR,
1822 "SWNCQ:qc_active 0x%X defer_bits 0x%X last_issue_tag 0x%x\n "
1823 "dhfis 0x%X dmafis 0x%X sdbfis 0x%X\n",
1824 pp->qc_active, pp->defer_queue.defer_bits, pp->last_issue_tag,
1825 pp->dhfis_bits, pp->dmafis_bits, pp->sdbfis_bits);
1826
1827 ata_port_printk(ap, KERN_ERR, "ATA_REG 0x%X ERR_REG 0x%X\n",
Tejun Heo5682ed32008-04-07 22:47:16 +09001828 ap->ops->sff_check_status(ap),
Kuan Luof140f0f2007-10-15 15:16:53 -04001829 ioread8(ap->ioaddr.error_addr));
1830
1831 sactive = readl(pp->sactive_block);
1832 done_mask = pp->qc_active ^ sactive;
1833
1834 ata_port_printk(ap, KERN_ERR, "tag : dhfis dmafis sdbfis sacitve\n");
1835 for (i = 0; i < ATA_MAX_QUEUE; i++) {
1836 u8 err = 0;
1837 if (pp->qc_active & (1 << i))
1838 err = 0;
1839 else if (done_mask & (1 << i))
1840 err = 1;
1841 else
1842 continue;
1843
1844 ata_port_printk(ap, KERN_ERR,
1845 "tag 0x%x: %01x %01x %01x %01x %s\n", i,
1846 (pp->dhfis_bits >> i) & 0x1,
1847 (pp->dmafis_bits >> i) & 0x1,
1848 (pp->sdbfis_bits >> i) & 0x1,
1849 (sactive >> i) & 0x1,
1850 (err ? "error! tag doesn't exit" : " "));
1851 }
1852
1853 nv_swncq_pp_reinit(ap);
Tejun Heo5682ed32008-04-07 22:47:16 +09001854 ap->ops->sff_irq_clear(ap);
Kuan Luof140f0f2007-10-15 15:16:53 -04001855 __ata_bmdma_stop(ap);
1856 nv_swncq_irq_clear(ap, 0xffff);
1857}
1858
1859static void nv_swncq_error_handler(struct ata_port *ap)
1860{
1861 struct ata_eh_context *ehc = &ap->link.eh_context;
1862
1863 if (ap->link.sactive) {
1864 nv_swncq_ncq_stop(ap);
Tejun Heocf480622008-01-24 00:05:14 +09001865 ehc->i.action |= ATA_EH_RESET;
Kuan Luof140f0f2007-10-15 15:16:53 -04001866 }
1867
Tejun Heofe06e5f2010-05-10 21:41:39 +02001868 ata_bmdma_error_handler(ap);
Kuan Luof140f0f2007-10-15 15:16:53 -04001869}
1870
1871#ifdef CONFIG_PM
1872static int nv_swncq_port_suspend(struct ata_port *ap, pm_message_t mesg)
1873{
1874 void __iomem *mmio = ap->host->iomap[NV_MMIO_BAR];
1875 u32 tmp;
1876
1877 /* clear irq */
1878 writel(~0, mmio + NV_INT_STATUS_MCP55);
1879
1880 /* disable irq */
1881 writel(0, mmio + NV_INT_ENABLE_MCP55);
1882
1883 /* disable swncq */
1884 tmp = readl(mmio + NV_CTL_MCP55);
1885 tmp &= ~(NV_CTL_PRI_SWNCQ | NV_CTL_SEC_SWNCQ);
1886 writel(tmp, mmio + NV_CTL_MCP55);
1887
1888 return 0;
1889}
1890
1891static int nv_swncq_port_resume(struct ata_port *ap)
1892{
1893 void __iomem *mmio = ap->host->iomap[NV_MMIO_BAR];
1894 u32 tmp;
1895
1896 /* clear irq */
1897 writel(~0, mmio + NV_INT_STATUS_MCP55);
1898
1899 /* enable irq */
1900 writel(0x00fd00fd, mmio + NV_INT_ENABLE_MCP55);
1901
1902 /* enable swncq */
1903 tmp = readl(mmio + NV_CTL_MCP55);
1904 writel(tmp | NV_CTL_PRI_SWNCQ | NV_CTL_SEC_SWNCQ, mmio + NV_CTL_MCP55);
1905
1906 return 0;
1907}
1908#endif
1909
1910static void nv_swncq_host_init(struct ata_host *host)
1911{
1912 u32 tmp;
1913 void __iomem *mmio = host->iomap[NV_MMIO_BAR];
1914 struct pci_dev *pdev = to_pci_dev(host->dev);
1915 u8 regval;
1916
1917 /* disable ECO 398 */
1918 pci_read_config_byte(pdev, 0x7f, &regval);
1919 regval &= ~(1 << 7);
1920 pci_write_config_byte(pdev, 0x7f, regval);
1921
1922 /* enable swncq */
1923 tmp = readl(mmio + NV_CTL_MCP55);
1924 VPRINTK("HOST_CTL:0x%X\n", tmp);
1925 writel(tmp | NV_CTL_PRI_SWNCQ | NV_CTL_SEC_SWNCQ, mmio + NV_CTL_MCP55);
1926
1927 /* enable irq intr */
1928 tmp = readl(mmio + NV_INT_ENABLE_MCP55);
1929 VPRINTK("HOST_ENABLE:0x%X\n", tmp);
1930 writel(tmp | 0x00fd00fd, mmio + NV_INT_ENABLE_MCP55);
1931
1932 /* clear port irq */
1933 writel(~0x0, mmio + NV_INT_STATUS_MCP55);
1934}
1935
1936static int nv_swncq_slave_config(struct scsi_device *sdev)
1937{
1938 struct ata_port *ap = ata_shost_to_port(sdev->host);
1939 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
1940 struct ata_device *dev;
1941 int rc;
1942 u8 rev;
1943 u8 check_maxtor = 0;
1944 unsigned char model_num[ATA_ID_PROD_LEN + 1];
1945
1946 rc = ata_scsi_slave_config(sdev);
1947 if (sdev->id >= ATA_MAX_DEVICES || sdev->channel || sdev->lun)
1948 /* Not a proper libata device, ignore */
1949 return rc;
1950
1951 dev = &ap->link.device[sdev->id];
1952 if (!(ap->flags & ATA_FLAG_NCQ) || dev->class == ATA_DEV_ATAPI)
1953 return rc;
1954
1955 /* if MCP51 and Maxtor, then disable ncq */
1956 if (pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA ||
1957 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA2)
1958 check_maxtor = 1;
1959
1960 /* if MCP55 and rev <= a2 and Maxtor, then disable ncq */
1961 if (pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA ||
1962 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA2) {
1963 pci_read_config_byte(pdev, 0x8, &rev);
1964 if (rev <= 0xa2)
1965 check_maxtor = 1;
1966 }
1967
1968 if (!check_maxtor)
1969 return rc;
1970
1971 ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num));
1972
1973 if (strncmp(model_num, "Maxtor", 6) == 0) {
Mike Christiee881a172009-10-15 17:46:39 -07001974 ata_scsi_change_queue_depth(sdev, 1, SCSI_QDEPTH_DEFAULT);
Kuan Luof140f0f2007-10-15 15:16:53 -04001975 ata_dev_printk(dev, KERN_NOTICE,
1976 "Disabling SWNCQ mode (depth %x)\n", sdev->queue_depth);
1977 }
1978
1979 return rc;
1980}
1981
1982static int nv_swncq_port_start(struct ata_port *ap)
1983{
1984 struct device *dev = ap->host->dev;
1985 void __iomem *mmio = ap->host->iomap[NV_MMIO_BAR];
1986 struct nv_swncq_port_priv *pp;
1987 int rc;
1988
Tejun Heoc7087652010-05-10 21:41:34 +02001989 /* we might fallback to bmdma, allocate bmdma resources */
1990 rc = ata_bmdma_port_start(ap);
Kuan Luof140f0f2007-10-15 15:16:53 -04001991 if (rc)
1992 return rc;
1993
1994 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
1995 if (!pp)
1996 return -ENOMEM;
1997
1998 pp->prd = dmam_alloc_coherent(dev, ATA_PRD_TBL_SZ * ATA_MAX_QUEUE,
1999 &pp->prd_dma, GFP_KERNEL);
2000 if (!pp->prd)
2001 return -ENOMEM;
2002 memset(pp->prd, 0, ATA_PRD_TBL_SZ * ATA_MAX_QUEUE);
2003
2004 ap->private_data = pp;
2005 pp->sactive_block = ap->ioaddr.scr_addr + 4 * SCR_ACTIVE;
2006 pp->irq_block = mmio + NV_INT_STATUS_MCP55 + ap->port_no * 2;
2007 pp->tag_block = mmio + NV_NCQ_REG_MCP55 + ap->port_no * 2;
2008
2009 return 0;
2010}
2011
2012static void nv_swncq_qc_prep(struct ata_queued_cmd *qc)
2013{
2014 if (qc->tf.protocol != ATA_PROT_NCQ) {
Tejun Heof47451c2010-05-10 21:41:40 +02002015 ata_bmdma_qc_prep(qc);
Kuan Luof140f0f2007-10-15 15:16:53 -04002016 return;
2017 }
2018
2019 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
2020 return;
2021
2022 nv_swncq_fill_sg(qc);
2023}
2024
2025static void nv_swncq_fill_sg(struct ata_queued_cmd *qc)
2026{
2027 struct ata_port *ap = qc->ap;
2028 struct scatterlist *sg;
Kuan Luof140f0f2007-10-15 15:16:53 -04002029 struct nv_swncq_port_priv *pp = ap->private_data;
Tejun Heof60d7012010-05-10 21:41:41 +02002030 struct ata_bmdma_prd *prd;
Tejun Heoff2aeb12007-12-05 16:43:11 +09002031 unsigned int si, idx;
Kuan Luof140f0f2007-10-15 15:16:53 -04002032
2033 prd = pp->prd + ATA_MAX_PRD * qc->tag;
2034
2035 idx = 0;
Tejun Heoff2aeb12007-12-05 16:43:11 +09002036 for_each_sg(qc->sg, sg, qc->n_elem, si) {
Kuan Luof140f0f2007-10-15 15:16:53 -04002037 u32 addr, offset;
2038 u32 sg_len, len;
2039
2040 addr = (u32)sg_dma_address(sg);
2041 sg_len = sg_dma_len(sg);
2042
2043 while (sg_len) {
2044 offset = addr & 0xffff;
2045 len = sg_len;
2046 if ((offset + sg_len) > 0x10000)
2047 len = 0x10000 - offset;
2048
2049 prd[idx].addr = cpu_to_le32(addr);
2050 prd[idx].flags_len = cpu_to_le32(len & 0xffff);
2051
2052 idx++;
2053 sg_len -= len;
2054 addr += len;
2055 }
2056 }
2057
Tejun Heoff2aeb12007-12-05 16:43:11 +09002058 prd[idx - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT);
Kuan Luof140f0f2007-10-15 15:16:53 -04002059}
2060
2061static unsigned int nv_swncq_issue_atacmd(struct ata_port *ap,
2062 struct ata_queued_cmd *qc)
2063{
2064 struct nv_swncq_port_priv *pp = ap->private_data;
2065
2066 if (qc == NULL)
2067 return 0;
2068
2069 DPRINTK("Enter\n");
2070
2071 writel((1 << qc->tag), pp->sactive_block);
2072 pp->last_issue_tag = qc->tag;
2073 pp->dhfis_bits &= ~(1 << qc->tag);
2074 pp->dmafis_bits &= ~(1 << qc->tag);
2075 pp->qc_active |= (0x1 << qc->tag);
2076
Tejun Heo5682ed32008-04-07 22:47:16 +09002077 ap->ops->sff_tf_load(ap, &qc->tf); /* load tf registers */
2078 ap->ops->sff_exec_command(ap, &qc->tf);
Kuan Luof140f0f2007-10-15 15:16:53 -04002079
2080 DPRINTK("Issued tag %u\n", qc->tag);
2081
2082 return 0;
2083}
2084
2085static unsigned int nv_swncq_qc_issue(struct ata_queued_cmd *qc)
2086{
2087 struct ata_port *ap = qc->ap;
2088 struct nv_swncq_port_priv *pp = ap->private_data;
2089
2090 if (qc->tf.protocol != ATA_PROT_NCQ)
Tejun Heo360ff782010-05-10 21:41:42 +02002091 return ata_bmdma_qc_issue(qc);
Kuan Luof140f0f2007-10-15 15:16:53 -04002092
2093 DPRINTK("Enter\n");
2094
2095 if (!pp->qc_active)
2096 nv_swncq_issue_atacmd(ap, qc);
2097 else
2098 nv_swncq_qc_to_dq(ap, qc); /* add qc to defer queue */
2099
2100 return 0;
2101}
2102
2103static void nv_swncq_hotplug(struct ata_port *ap, u32 fis)
2104{
2105 u32 serror;
2106 struct ata_eh_info *ehi = &ap->link.eh_info;
2107
2108 ata_ehi_clear_desc(ehi);
2109
2110 /* AHCI needs SError cleared; otherwise, it might lock up */
2111 sata_scr_read(&ap->link, SCR_ERROR, &serror);
2112 sata_scr_write(&ap->link, SCR_ERROR, serror);
2113
2114 /* analyze @irq_stat */
2115 if (fis & NV_SWNCQ_IRQ_ADDED)
2116 ata_ehi_push_desc(ehi, "hot plug");
2117 else if (fis & NV_SWNCQ_IRQ_REMOVED)
2118 ata_ehi_push_desc(ehi, "hot unplug");
2119
2120 ata_ehi_hotplugged(ehi);
2121
2122 /* okay, let's hand over to EH */
2123 ehi->serror |= serror;
2124
2125 ata_port_freeze(ap);
2126}
2127
2128static int nv_swncq_sdbfis(struct ata_port *ap)
2129{
2130 struct ata_queued_cmd *qc;
2131 struct nv_swncq_port_priv *pp = ap->private_data;
2132 struct ata_eh_info *ehi = &ap->link.eh_info;
2133 u32 sactive;
Kuan Luof140f0f2007-10-15 15:16:53 -04002134 u32 done_mask;
2135 int i;
2136 u8 host_stat;
2137 u8 lack_dhfis = 0;
2138
2139 host_stat = ap->ops->bmdma_status(ap);
2140 if (unlikely(host_stat & ATA_DMA_ERR)) {
2141 /* error when transfering data to/from memory */
2142 ata_ehi_clear_desc(ehi);
2143 ata_ehi_push_desc(ehi, "BMDMA stat 0x%x", host_stat);
2144 ehi->err_mask |= AC_ERR_HOST_BUS;
Tejun Heocf480622008-01-24 00:05:14 +09002145 ehi->action |= ATA_EH_RESET;
Kuan Luof140f0f2007-10-15 15:16:53 -04002146 return -EINVAL;
2147 }
2148
Tejun Heo5682ed32008-04-07 22:47:16 +09002149 ap->ops->sff_irq_clear(ap);
Kuan Luof140f0f2007-10-15 15:16:53 -04002150 __ata_bmdma_stop(ap);
2151
2152 sactive = readl(pp->sactive_block);
2153 done_mask = pp->qc_active ^ sactive;
2154
2155 if (unlikely(done_mask & sactive)) {
2156 ata_ehi_clear_desc(ehi);
2157 ata_ehi_push_desc(ehi, "illegal SWNCQ:qc_active transition"
2158 "(%08x->%08x)", pp->qc_active, sactive);
2159 ehi->err_mask |= AC_ERR_HSM;
Tejun Heocf480622008-01-24 00:05:14 +09002160 ehi->action |= ATA_EH_RESET;
Kuan Luof140f0f2007-10-15 15:16:53 -04002161 return -EINVAL;
2162 }
2163 for (i = 0; i < ATA_MAX_QUEUE; i++) {
2164 if (!(done_mask & (1 << i)))
2165 continue;
2166
2167 qc = ata_qc_from_tag(ap, i);
2168 if (qc) {
2169 ata_qc_complete(qc);
2170 pp->qc_active &= ~(1 << i);
2171 pp->dhfis_bits &= ~(1 << i);
2172 pp->dmafis_bits &= ~(1 << i);
2173 pp->sdbfis_bits |= (1 << i);
Kuan Luof140f0f2007-10-15 15:16:53 -04002174 }
2175 }
2176
2177 if (!ap->qc_active) {
2178 DPRINTK("over\n");
2179 nv_swncq_pp_reinit(ap);
Tejun Heo752e3862010-06-25 15:02:59 +02002180 return 0;
Kuan Luof140f0f2007-10-15 15:16:53 -04002181 }
2182
2183 if (pp->qc_active & pp->dhfis_bits)
Tejun Heo752e3862010-06-25 15:02:59 +02002184 return 0;
Kuan Luof140f0f2007-10-15 15:16:53 -04002185
2186 if ((pp->ncq_flags & ncq_saw_backout) ||
2187 (pp->qc_active ^ pp->dhfis_bits))
Tejun Heo752e3862010-06-25 15:02:59 +02002188 /* if the controller can't get a device to host register FIS,
Kuan Luof140f0f2007-10-15 15:16:53 -04002189 * The driver needs to reissue the new command.
2190 */
2191 lack_dhfis = 1;
2192
2193 DPRINTK("id 0x%x QC: qc_active 0x%x,"
2194 "SWNCQ:qc_active 0x%X defer_bits %X "
2195 "dhfis 0x%X dmafis 0x%X last_issue_tag %x\n",
2196 ap->print_id, ap->qc_active, pp->qc_active,
2197 pp->defer_queue.defer_bits, pp->dhfis_bits,
2198 pp->dmafis_bits, pp->last_issue_tag);
2199
2200 nv_swncq_fis_reinit(ap);
2201
2202 if (lack_dhfis) {
2203 qc = ata_qc_from_tag(ap, pp->last_issue_tag);
2204 nv_swncq_issue_atacmd(ap, qc);
Tejun Heo752e3862010-06-25 15:02:59 +02002205 return 0;
Kuan Luof140f0f2007-10-15 15:16:53 -04002206 }
2207
2208 if (pp->defer_queue.defer_bits) {
2209 /* send deferral queue command */
2210 qc = nv_swncq_qc_from_dq(ap);
2211 WARN_ON(qc == NULL);
2212 nv_swncq_issue_atacmd(ap, qc);
2213 }
2214
Tejun Heo752e3862010-06-25 15:02:59 +02002215 return 0;
Kuan Luof140f0f2007-10-15 15:16:53 -04002216}
2217
2218static inline u32 nv_swncq_tag(struct ata_port *ap)
2219{
2220 struct nv_swncq_port_priv *pp = ap->private_data;
2221 u32 tag;
2222
2223 tag = readb(pp->tag_block) >> 2;
2224 return (tag & 0x1f);
2225}
2226
Tejun Heo752e3862010-06-25 15:02:59 +02002227static void nv_swncq_dmafis(struct ata_port *ap)
Kuan Luof140f0f2007-10-15 15:16:53 -04002228{
2229 struct ata_queued_cmd *qc;
2230 unsigned int rw;
2231 u8 dmactl;
2232 u32 tag;
2233 struct nv_swncq_port_priv *pp = ap->private_data;
2234
2235 __ata_bmdma_stop(ap);
2236 tag = nv_swncq_tag(ap);
2237
2238 DPRINTK("dma setup tag 0x%x\n", tag);
2239 qc = ata_qc_from_tag(ap, tag);
2240
2241 if (unlikely(!qc))
Tejun Heo752e3862010-06-25 15:02:59 +02002242 return;
Kuan Luof140f0f2007-10-15 15:16:53 -04002243
2244 rw = qc->tf.flags & ATA_TFLAG_WRITE;
2245
2246 /* load PRD table addr. */
2247 iowrite32(pp->prd_dma + ATA_PRD_TBL_SZ * qc->tag,
2248 ap->ioaddr.bmdma_addr + ATA_DMA_TABLE_OFS);
2249
2250 /* specify data direction, triple-check start bit is clear */
2251 dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
2252 dmactl &= ~ATA_DMA_WR;
2253 if (!rw)
2254 dmactl |= ATA_DMA_WR;
2255
2256 iowrite8(dmactl | ATA_DMA_START, ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
Kuan Luof140f0f2007-10-15 15:16:53 -04002257}
2258
2259static void nv_swncq_host_interrupt(struct ata_port *ap, u16 fis)
2260{
2261 struct nv_swncq_port_priv *pp = ap->private_data;
2262 struct ata_queued_cmd *qc;
2263 struct ata_eh_info *ehi = &ap->link.eh_info;
2264 u32 serror;
2265 u8 ata_stat;
Kuan Luof140f0f2007-10-15 15:16:53 -04002266
Tejun Heo5682ed32008-04-07 22:47:16 +09002267 ata_stat = ap->ops->sff_check_status(ap);
Kuan Luof140f0f2007-10-15 15:16:53 -04002268 nv_swncq_irq_clear(ap, fis);
2269 if (!fis)
2270 return;
2271
2272 if (ap->pflags & ATA_PFLAG_FROZEN)
2273 return;
2274
2275 if (fis & NV_SWNCQ_IRQ_HOTPLUG) {
2276 nv_swncq_hotplug(ap, fis);
2277 return;
2278 }
2279
2280 if (!pp->qc_active)
2281 return;
2282
Tejun Heo82ef04f2008-07-31 17:02:40 +09002283 if (ap->ops->scr_read(&ap->link, SCR_ERROR, &serror))
Kuan Luof140f0f2007-10-15 15:16:53 -04002284 return;
Tejun Heo82ef04f2008-07-31 17:02:40 +09002285 ap->ops->scr_write(&ap->link, SCR_ERROR, serror);
Kuan Luof140f0f2007-10-15 15:16:53 -04002286
2287 if (ata_stat & ATA_ERR) {
2288 ata_ehi_clear_desc(ehi);
2289 ata_ehi_push_desc(ehi, "Ata error. fis:0x%X", fis);
2290 ehi->err_mask |= AC_ERR_DEV;
2291 ehi->serror |= serror;
Tejun Heocf480622008-01-24 00:05:14 +09002292 ehi->action |= ATA_EH_RESET;
Kuan Luof140f0f2007-10-15 15:16:53 -04002293 ata_port_freeze(ap);
2294 return;
2295 }
2296
2297 if (fis & NV_SWNCQ_IRQ_BACKOUT) {
2298 /* If the IRQ is backout, driver must issue
2299 * the new command again some time later.
2300 */
2301 pp->ncq_flags |= ncq_saw_backout;
2302 }
2303
2304 if (fis & NV_SWNCQ_IRQ_SDBFIS) {
2305 pp->ncq_flags |= ncq_saw_sdb;
2306 DPRINTK("id 0x%x SWNCQ: qc_active 0x%X "
2307 "dhfis 0x%X dmafis 0x%X sactive 0x%X\n",
2308 ap->print_id, pp->qc_active, pp->dhfis_bits,
2309 pp->dmafis_bits, readl(pp->sactive_block));
Tejun Heo752e3862010-06-25 15:02:59 +02002310 if (nv_swncq_sdbfis(ap) < 0)
Kuan Luof140f0f2007-10-15 15:16:53 -04002311 goto irq_error;
2312 }
2313
2314 if (fis & NV_SWNCQ_IRQ_DHREGFIS) {
2315 /* The interrupt indicates the new command
2316 * was transmitted correctly to the drive.
2317 */
2318 pp->dhfis_bits |= (0x1 << pp->last_issue_tag);
2319 pp->ncq_flags |= ncq_saw_d2h;
2320 if (pp->ncq_flags & (ncq_saw_sdb | ncq_saw_backout)) {
2321 ata_ehi_push_desc(ehi, "illegal fis transaction");
2322 ehi->err_mask |= AC_ERR_HSM;
Tejun Heocf480622008-01-24 00:05:14 +09002323 ehi->action |= ATA_EH_RESET;
Kuan Luof140f0f2007-10-15 15:16:53 -04002324 goto irq_error;
2325 }
2326
2327 if (!(fis & NV_SWNCQ_IRQ_DMASETUP) &&
2328 !(pp->ncq_flags & ncq_saw_dmas)) {
Tejun Heo5682ed32008-04-07 22:47:16 +09002329 ata_stat = ap->ops->sff_check_status(ap);
Kuan Luof140f0f2007-10-15 15:16:53 -04002330 if (ata_stat & ATA_BUSY)
2331 goto irq_exit;
2332
2333 if (pp->defer_queue.defer_bits) {
2334 DPRINTK("send next command\n");
2335 qc = nv_swncq_qc_from_dq(ap);
2336 nv_swncq_issue_atacmd(ap, qc);
2337 }
2338 }
2339 }
2340
2341 if (fis & NV_SWNCQ_IRQ_DMASETUP) {
2342 /* program the dma controller with appropriate PRD buffers
2343 * and start the DMA transfer for requested command.
2344 */
2345 pp->dmafis_bits |= (0x1 << nv_swncq_tag(ap));
2346 pp->ncq_flags |= ncq_saw_dmas;
Tejun Heo752e3862010-06-25 15:02:59 +02002347 nv_swncq_dmafis(ap);
Kuan Luof140f0f2007-10-15 15:16:53 -04002348 }
2349
2350irq_exit:
2351 return;
2352irq_error:
2353 ata_ehi_push_desc(ehi, "fis:0x%x", fis);
2354 ata_port_freeze(ap);
2355 return;
2356}
2357
2358static irqreturn_t nv_swncq_interrupt(int irq, void *dev_instance)
2359{
2360 struct ata_host *host = dev_instance;
2361 unsigned int i;
2362 unsigned int handled = 0;
2363 unsigned long flags;
2364 u32 irq_stat;
2365
2366 spin_lock_irqsave(&host->lock, flags);
2367
2368 irq_stat = readl(host->iomap[NV_MMIO_BAR] + NV_INT_STATUS_MCP55);
2369
2370 for (i = 0; i < host->n_ports; i++) {
2371 struct ata_port *ap = host->ports[i];
2372
Tejun Heo3e4ec342010-05-10 21:41:30 +02002373 if (ap->link.sactive) {
2374 nv_swncq_host_interrupt(ap, (u16)irq_stat);
2375 handled = 1;
2376 } else {
2377 if (irq_stat) /* reserve Hotplug */
2378 nv_swncq_irq_clear(ap, 0xfff0);
Kuan Luof140f0f2007-10-15 15:16:53 -04002379
Tejun Heo3e4ec342010-05-10 21:41:30 +02002380 handled += nv_host_intr(ap, (u8)irq_stat);
Kuan Luof140f0f2007-10-15 15:16:53 -04002381 }
2382 irq_stat >>= NV_INT_PORT_SHIFT_MCP55;
2383 }
2384
2385 spin_unlock_irqrestore(&host->lock, flags);
2386
2387 return IRQ_RETVAL(handled);
2388}
2389
Jeff Garzik5796d1c2007-10-26 00:03:37 -04002390static int nv_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002391{
Jeff Garzik5796d1c2007-10-26 00:03:37 -04002392 static int printed_version;
Tejun Heo1626aeb2007-05-04 12:43:58 +02002393 const struct ata_port_info *ppi[] = { NULL, NULL };
Tejun Heo95947192008-03-25 12:22:49 +09002394 struct nv_pi_priv *ipriv;
Tejun Heo9a829cc2007-04-17 23:44:08 +09002395 struct ata_host *host;
Robert Hancockcdf56bc2007-01-03 18:13:57 -06002396 struct nv_host_priv *hpriv;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002397 int rc;
2398 u32 bar;
Tejun Heo0d5ff562007-02-01 15:06:36 +09002399 void __iomem *base;
Robert Hancockfbbb2622006-10-27 19:08:41 -07002400 unsigned long type = ent->driver_data;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002401
2402 // Make sure this is a SATA controller by counting the number of bars
2403 // (NVIDIA SATA controllers will always have six bars). Otherwise,
2404 // it's an IDE controller and we ignore it.
Jeff Garzik5796d1c2007-10-26 00:03:37 -04002405 for (bar = 0; bar < 6; bar++)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002406 if (pci_resource_start(pdev, bar) == 0)
2407 return -ENODEV;
2408
Robert Hancockcdf56bc2007-01-03 18:13:57 -06002409 if (!printed_version++)
Jeff Garzika9524a72005-10-30 14:39:11 -05002410 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07002411
Tejun Heo24dc5f32007-01-20 16:00:28 +09002412 rc = pcim_enable_device(pdev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002413 if (rc)
Tejun Heo24dc5f32007-01-20 16:00:28 +09002414 return rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002415
Tejun Heo9a829cc2007-04-17 23:44:08 +09002416 /* determine type and allocate host */
Kuan Luof140f0f2007-10-15 15:16:53 -04002417 if (type == CK804 && adma_enabled) {
Robert Hancockfbbb2622006-10-27 19:08:41 -07002418 dev_printk(KERN_NOTICE, &pdev->dev, "Using ADMA mode\n");
2419 type = ADMA;
Tejun Heo2d775702009-01-25 11:29:38 +09002420 } else if (type == MCP5x && swncq_enabled) {
2421 dev_printk(KERN_NOTICE, &pdev->dev, "Using SWNCQ mode\n");
2422 type = SWNCQ;
Jeff Garzik360737a2007-10-29 06:49:24 -04002423 }
2424
Tejun Heo1626aeb2007-05-04 12:43:58 +02002425 ppi[0] = &nv_port_info[type];
Tejun Heo95947192008-03-25 12:22:49 +09002426 ipriv = ppi[0]->private_data;
Tejun Heo1c5afdf2010-05-19 22:10:22 +02002427 rc = ata_pci_bmdma_prepare_host(pdev, ppi, &host);
Tejun Heo9a829cc2007-04-17 23:44:08 +09002428 if (rc)
2429 return rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002430
Tejun Heo24dc5f32007-01-20 16:00:28 +09002431 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
Robert Hancockcdf56bc2007-01-03 18:13:57 -06002432 if (!hpriv)
Tejun Heo24dc5f32007-01-20 16:00:28 +09002433 return -ENOMEM;
Robert Hancockcdf56bc2007-01-03 18:13:57 -06002434 hpriv->type = type;
Tejun Heo9a829cc2007-04-17 23:44:08 +09002435 host->private_data = hpriv;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002436
Tejun Heo9a829cc2007-04-17 23:44:08 +09002437 /* request and iomap NV_MMIO_BAR */
2438 rc = pcim_iomap_regions(pdev, 1 << NV_MMIO_BAR, DRV_NAME);
2439 if (rc)
2440 return rc;
2441
2442 /* configure SCR access */
2443 base = host->iomap[NV_MMIO_BAR];
2444 host->ports[0]->ioaddr.scr_addr = base + NV_PORT0_SCR_REG_OFFSET;
2445 host->ports[1]->ioaddr.scr_addr = base + NV_PORT1_SCR_REG_OFFSET;
Jeff Garzik02cbd922006-03-22 23:59:46 -05002446
Tejun Heoada364e2006-06-17 15:49:56 +09002447 /* enable SATA space for CK804 */
Robert Hancockfbbb2622006-10-27 19:08:41 -07002448 if (type >= CK804) {
Tejun Heoada364e2006-06-17 15:49:56 +09002449 u8 regval;
2450
2451 pci_read_config_byte(pdev, NV_MCP_SATA_CFG_20, &regval);
2452 regval |= NV_MCP_SATA_CFG_20_SATA_SPACE_EN;
2453 pci_write_config_byte(pdev, NV_MCP_SATA_CFG_20, regval);
2454 }
2455
Tejun Heo9a829cc2007-04-17 23:44:08 +09002456 /* init ADMA */
Robert Hancockfbbb2622006-10-27 19:08:41 -07002457 if (type == ADMA) {
Tejun Heo9a829cc2007-04-17 23:44:08 +09002458 rc = nv_adma_host_init(host);
Robert Hancockfbbb2622006-10-27 19:08:41 -07002459 if (rc)
Tejun Heo24dc5f32007-01-20 16:00:28 +09002460 return rc;
Jeff Garzik360737a2007-10-29 06:49:24 -04002461 } else if (type == SWNCQ)
Kuan Luof140f0f2007-10-15 15:16:53 -04002462 nv_swncq_host_init(host);
Robert Hancockfbbb2622006-10-27 19:08:41 -07002463
Tony Vroon51c89492009-08-06 00:50:09 +01002464 if (msi_enabled) {
2465 dev_printk(KERN_NOTICE, &pdev->dev, "Using MSI\n");
2466 pci_enable_msi(pdev);
2467 }
2468
Tejun Heo9a829cc2007-04-17 23:44:08 +09002469 pci_set_master(pdev);
Tejun Heo95cc2c72010-05-14 11:48:50 +02002470 return ata_pci_sff_activate_host(host, ipriv->irq_handler, ipriv->sht);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002471}
2472
Tejun Heo438ac6d2007-03-02 17:31:26 +09002473#ifdef CONFIG_PM
Robert Hancockcdf56bc2007-01-03 18:13:57 -06002474static int nv_pci_device_resume(struct pci_dev *pdev)
2475{
2476 struct ata_host *host = dev_get_drvdata(&pdev->dev);
2477 struct nv_host_priv *hpriv = host->private_data;
Robert Hancockce053fa2007-02-05 16:26:04 -08002478 int rc;
Robert Hancockcdf56bc2007-01-03 18:13:57 -06002479
Robert Hancockce053fa2007-02-05 16:26:04 -08002480 rc = ata_pci_device_do_resume(pdev);
Jeff Garzikb4479162007-10-25 20:47:30 -04002481 if (rc)
Robert Hancockce053fa2007-02-05 16:26:04 -08002482 return rc;
Robert Hancockcdf56bc2007-01-03 18:13:57 -06002483
2484 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
Jeff Garzikb4479162007-10-25 20:47:30 -04002485 if (hpriv->type >= CK804) {
Robert Hancockcdf56bc2007-01-03 18:13:57 -06002486 u8 regval;
2487
2488 pci_read_config_byte(pdev, NV_MCP_SATA_CFG_20, &regval);
2489 regval |= NV_MCP_SATA_CFG_20_SATA_SPACE_EN;
2490 pci_write_config_byte(pdev, NV_MCP_SATA_CFG_20, regval);
2491 }
Jeff Garzikb4479162007-10-25 20:47:30 -04002492 if (hpriv->type == ADMA) {
Robert Hancockcdf56bc2007-01-03 18:13:57 -06002493 u32 tmp32;
2494 struct nv_adma_port_priv *pp;
2495 /* enable/disable ADMA on the ports appropriately */
2496 pci_read_config_dword(pdev, NV_MCP_SATA_CFG_20, &tmp32);
2497
2498 pp = host->ports[0]->private_data;
Jeff Garzikb4479162007-10-25 20:47:30 -04002499 if (pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE)
Robert Hancockcdf56bc2007-01-03 18:13:57 -06002500 tmp32 &= ~(NV_MCP_SATA_CFG_20_PORT0_EN |
Jeff Garzik5796d1c2007-10-26 00:03:37 -04002501 NV_MCP_SATA_CFG_20_PORT0_PWB_EN);
Robert Hancockcdf56bc2007-01-03 18:13:57 -06002502 else
2503 tmp32 |= (NV_MCP_SATA_CFG_20_PORT0_EN |
Jeff Garzik5796d1c2007-10-26 00:03:37 -04002504 NV_MCP_SATA_CFG_20_PORT0_PWB_EN);
Robert Hancockcdf56bc2007-01-03 18:13:57 -06002505 pp = host->ports[1]->private_data;
Jeff Garzikb4479162007-10-25 20:47:30 -04002506 if (pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE)
Robert Hancockcdf56bc2007-01-03 18:13:57 -06002507 tmp32 &= ~(NV_MCP_SATA_CFG_20_PORT1_EN |
Jeff Garzik5796d1c2007-10-26 00:03:37 -04002508 NV_MCP_SATA_CFG_20_PORT1_PWB_EN);
Robert Hancockcdf56bc2007-01-03 18:13:57 -06002509 else
2510 tmp32 |= (NV_MCP_SATA_CFG_20_PORT1_EN |
Jeff Garzik5796d1c2007-10-26 00:03:37 -04002511 NV_MCP_SATA_CFG_20_PORT1_PWB_EN);
Robert Hancockcdf56bc2007-01-03 18:13:57 -06002512
2513 pci_write_config_dword(pdev, NV_MCP_SATA_CFG_20, tmp32);
2514 }
2515 }
2516
2517 ata_host_resume(host);
2518
2519 return 0;
2520}
Tejun Heo438ac6d2007-03-02 17:31:26 +09002521#endif
Robert Hancockcdf56bc2007-01-03 18:13:57 -06002522
Jeff Garzikcca39742006-08-24 03:19:22 -04002523static void nv_ck804_host_stop(struct ata_host *host)
Tejun Heoada364e2006-06-17 15:49:56 +09002524{
Jeff Garzikcca39742006-08-24 03:19:22 -04002525 struct pci_dev *pdev = to_pci_dev(host->dev);
Tejun Heoada364e2006-06-17 15:49:56 +09002526 u8 regval;
2527
2528 /* disable SATA space for CK804 */
2529 pci_read_config_byte(pdev, NV_MCP_SATA_CFG_20, &regval);
2530 regval &= ~NV_MCP_SATA_CFG_20_SATA_SPACE_EN;
2531 pci_write_config_byte(pdev, NV_MCP_SATA_CFG_20, regval);
Tejun Heoada364e2006-06-17 15:49:56 +09002532}
2533
Robert Hancockfbbb2622006-10-27 19:08:41 -07002534static void nv_adma_host_stop(struct ata_host *host)
2535{
2536 struct pci_dev *pdev = to_pci_dev(host->dev);
Robert Hancockfbbb2622006-10-27 19:08:41 -07002537 u32 tmp32;
2538
Robert Hancockfbbb2622006-10-27 19:08:41 -07002539 /* disable ADMA on the ports */
2540 pci_read_config_dword(pdev, NV_MCP_SATA_CFG_20, &tmp32);
2541 tmp32 &= ~(NV_MCP_SATA_CFG_20_PORT0_EN |
2542 NV_MCP_SATA_CFG_20_PORT0_PWB_EN |
2543 NV_MCP_SATA_CFG_20_PORT1_EN |
2544 NV_MCP_SATA_CFG_20_PORT1_PWB_EN);
2545
2546 pci_write_config_dword(pdev, NV_MCP_SATA_CFG_20, tmp32);
2547
2548 nv_ck804_host_stop(host);
2549}
2550
Linus Torvalds1da177e2005-04-16 15:20:36 -07002551static int __init nv_init(void)
2552{
Pavel Roskinb7887192006-08-10 18:13:18 +09002553 return pci_register_driver(&nv_pci_driver);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002554}
2555
2556static void __exit nv_exit(void)
2557{
2558 pci_unregister_driver(&nv_pci_driver);
2559}
2560
2561module_init(nv_init);
2562module_exit(nv_exit);
Robert Hancockfbbb2622006-10-27 19:08:41 -07002563module_param_named(adma, adma_enabled, bool, 0444);
Brandon Ehle55f784c2009-03-01 00:02:49 -08002564MODULE_PARM_DESC(adma, "Enable use of ADMA (Default: false)");
Kuan Luof140f0f2007-10-15 15:16:53 -04002565module_param_named(swncq, swncq_enabled, bool, 0444);
Zoltan Boszormenyid21279f2008-03-28 14:33:46 -07002566MODULE_PARM_DESC(swncq, "Enable use of SWNCQ (Default: true)");
Tony Vroon51c89492009-08-06 00:50:09 +01002567module_param_named(msi, msi_enabled, bool, 0444);
2568MODULE_PARM_DESC(msi, "Enable use of MSI (Default: false)");
Kuan Luof140f0f2007-10-15 15:16:53 -04002569