blob: 91d294e74ac8a68ee8185352643ab41b28b3f32c [file] [log] [blame]
Daniel Vetter02e792f2009-09-15 22:57:34 +02001/*
2 * Copyright © 2009
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Daniel Vetter <daniel@ffwll.ch>
25 *
26 * Derived from Xorg ddx, xf86-video-intel, src/i830_video.c
27 */
Andrew Mortone1679762010-08-24 16:35:52 -070028
29#include <linux/seq_file.h>
Daniel Vetter02e792f2009-09-15 22:57:34 +020030#include "drmP.h"
31#include "drm.h"
32#include "i915_drm.h"
33#include "i915_drv.h"
34#include "i915_reg.h"
35#include "intel_drv.h"
36
37/* Limits for overlay size. According to intel doc, the real limits are:
38 * Y width: 4095, UV width (planar): 2047, Y height: 2047,
39 * UV width (planar): * 1023. But the xorg thinks 2048 for height and width. Use
40 * the mininum of both. */
41#define IMAGE_MAX_WIDTH 2048
42#define IMAGE_MAX_HEIGHT 2046 /* 2 * 1023 */
43/* on 830 and 845 these large limits result in the card hanging */
44#define IMAGE_MAX_WIDTH_LEGACY 1024
45#define IMAGE_MAX_HEIGHT_LEGACY 1088
46
47/* overlay register definitions */
48/* OCMD register */
49#define OCMD_TILED_SURFACE (0x1<<19)
50#define OCMD_MIRROR_MASK (0x3<<17)
51#define OCMD_MIRROR_MODE (0x3<<17)
52#define OCMD_MIRROR_HORIZONTAL (0x1<<17)
53#define OCMD_MIRROR_VERTICAL (0x2<<17)
54#define OCMD_MIRROR_BOTH (0x3<<17)
55#define OCMD_BYTEORDER_MASK (0x3<<14) /* zero for YUYV or FOURCC YUY2 */
56#define OCMD_UV_SWAP (0x1<<14) /* YVYU */
57#define OCMD_Y_SWAP (0x2<<14) /* UYVY or FOURCC UYVY */
58#define OCMD_Y_AND_UV_SWAP (0x3<<14) /* VYUY */
59#define OCMD_SOURCE_FORMAT_MASK (0xf<<10)
60#define OCMD_RGB_888 (0x1<<10) /* not in i965 Intel docs */
61#define OCMD_RGB_555 (0x2<<10) /* not in i965 Intel docs */
62#define OCMD_RGB_565 (0x3<<10) /* not in i965 Intel docs */
63#define OCMD_YUV_422_PACKED (0x8<<10)
64#define OCMD_YUV_411_PACKED (0x9<<10) /* not in i965 Intel docs */
65#define OCMD_YUV_420_PLANAR (0xc<<10)
66#define OCMD_YUV_422_PLANAR (0xd<<10)
67#define OCMD_YUV_410_PLANAR (0xe<<10) /* also 411 */
68#define OCMD_TVSYNCFLIP_PARITY (0x1<<9)
69#define OCMD_TVSYNCFLIP_ENABLE (0x1<<7)
Chris Wilsond7961362010-07-13 13:52:17 +010070#define OCMD_BUF_TYPE_MASK (0x1<<5)
Daniel Vetter02e792f2009-09-15 22:57:34 +020071#define OCMD_BUF_TYPE_FRAME (0x0<<5)
72#define OCMD_BUF_TYPE_FIELD (0x1<<5)
73#define OCMD_TEST_MODE (0x1<<4)
74#define OCMD_BUFFER_SELECT (0x3<<2)
75#define OCMD_BUFFER0 (0x0<<2)
76#define OCMD_BUFFER1 (0x1<<2)
77#define OCMD_FIELD_SELECT (0x1<<2)
78#define OCMD_FIELD0 (0x0<<1)
79#define OCMD_FIELD1 (0x1<<1)
80#define OCMD_ENABLE (0x1<<0)
81
82/* OCONFIG register */
83#define OCONF_PIPE_MASK (0x1<<18)
84#define OCONF_PIPE_A (0x0<<18)
85#define OCONF_PIPE_B (0x1<<18)
86#define OCONF_GAMMA2_ENABLE (0x1<<16)
87#define OCONF_CSC_MODE_BT601 (0x0<<5)
88#define OCONF_CSC_MODE_BT709 (0x1<<5)
89#define OCONF_CSC_BYPASS (0x1<<4)
90#define OCONF_CC_OUT_8BIT (0x1<<3)
91#define OCONF_TEST_MODE (0x1<<2)
92#define OCONF_THREE_LINE_BUFFER (0x1<<0)
93#define OCONF_TWO_LINE_BUFFER (0x0<<0)
94
95/* DCLRKM (dst-key) register */
96#define DST_KEY_ENABLE (0x1<<31)
97#define CLK_RGB24_MASK 0x0
98#define CLK_RGB16_MASK 0x070307
99#define CLK_RGB15_MASK 0x070707
100#define CLK_RGB8I_MASK 0xffffff
101
102#define RGB16_TO_COLORKEY(c) \
103 (((c & 0xF800) << 8) | ((c & 0x07E0) << 5) | ((c & 0x001F) << 3))
104#define RGB15_TO_COLORKEY(c) \
105 (((c & 0x7c00) << 9) | ((c & 0x03E0) << 6) | ((c & 0x001F) << 3))
106
107/* overlay flip addr flag */
108#define OFC_UPDATE 0x1
109
110/* polyphase filter coefficients */
111#define N_HORIZ_Y_TAPS 5
112#define N_VERT_Y_TAPS 3
113#define N_HORIZ_UV_TAPS 3
114#define N_VERT_UV_TAPS 3
115#define N_PHASES 17
116#define MAX_TAPS 5
117
118/* memory bufferd overlay registers */
119struct overlay_registers {
Akshay Joshi0206e352011-08-16 15:34:10 -0400120 u32 OBUF_0Y;
121 u32 OBUF_1Y;
122 u32 OBUF_0U;
123 u32 OBUF_0V;
124 u32 OBUF_1U;
125 u32 OBUF_1V;
126 u32 OSTRIDE;
127 u32 YRGB_VPH;
128 u32 UV_VPH;
129 u32 HORZ_PH;
130 u32 INIT_PHS;
131 u32 DWINPOS;
132 u32 DWINSZ;
133 u32 SWIDTH;
134 u32 SWIDTHSW;
135 u32 SHEIGHT;
136 u32 YRGBSCALE;
137 u32 UVSCALE;
138 u32 OCLRC0;
139 u32 OCLRC1;
140 u32 DCLRKV;
141 u32 DCLRKM;
142 u32 SCLRKVH;
143 u32 SCLRKVL;
144 u32 SCLRKEN;
145 u32 OCONFIG;
146 u32 OCMD;
147 u32 RESERVED1; /* 0x6C */
148 u32 OSTART_0Y;
149 u32 OSTART_1Y;
150 u32 OSTART_0U;
151 u32 OSTART_0V;
152 u32 OSTART_1U;
153 u32 OSTART_1V;
154 u32 OTILEOFF_0Y;
155 u32 OTILEOFF_1Y;
156 u32 OTILEOFF_0U;
157 u32 OTILEOFF_0V;
158 u32 OTILEOFF_1U;
159 u32 OTILEOFF_1V;
160 u32 FASTHSCALE; /* 0xA0 */
161 u32 UVSCALEV; /* 0xA4 */
162 u32 RESERVEDC[(0x200 - 0xA8) / 4]; /* 0xA8 - 0x1FC */
163 u16 Y_VCOEFS[N_VERT_Y_TAPS * N_PHASES]; /* 0x200 */
164 u16 RESERVEDD[0x100 / 2 - N_VERT_Y_TAPS * N_PHASES];
165 u16 Y_HCOEFS[N_HORIZ_Y_TAPS * N_PHASES]; /* 0x300 */
166 u16 RESERVEDE[0x200 / 2 - N_HORIZ_Y_TAPS * N_PHASES];
167 u16 UV_VCOEFS[N_VERT_UV_TAPS * N_PHASES]; /* 0x500 */
168 u16 RESERVEDF[0x100 / 2 - N_VERT_UV_TAPS * N_PHASES];
169 u16 UV_HCOEFS[N_HORIZ_UV_TAPS * N_PHASES]; /* 0x600 */
170 u16 RESERVEDG[0x100 / 2 - N_HORIZ_UV_TAPS * N_PHASES];
Daniel Vetter02e792f2009-09-15 22:57:34 +0200171};
172
Chris Wilson23f09ce2010-08-12 13:53:37 +0100173struct intel_overlay {
174 struct drm_device *dev;
175 struct intel_crtc *crtc;
176 struct drm_i915_gem_object *vid_bo;
177 struct drm_i915_gem_object *old_vid_bo;
178 int active;
179 int pfit_active;
180 u32 pfit_vscale_ratio; /* shifted-point number, (1<<12) == 1.0 */
181 u32 color_key;
182 u32 brightness, contrast, saturation;
183 u32 old_xscale, old_yscale;
184 /* register access */
185 u32 flip_addr;
186 struct drm_i915_gem_object *reg_bo;
187 /* flip handling */
188 uint32_t last_flip_req;
Chris Wilsonb303cf92010-08-12 14:03:48 +0100189 void (*flip_tail)(struct intel_overlay *);
Chris Wilson23f09ce2010-08-12 13:53:37 +0100190};
Daniel Vetter02e792f2009-09-15 22:57:34 +0200191
Chris Wilson8d74f652010-08-12 10:35:26 +0100192static struct overlay_registers *
Chris Wilson8d74f652010-08-12 10:35:26 +0100193intel_overlay_map_regs(struct intel_overlay *overlay)
Daniel Vetter02e792f2009-09-15 22:57:34 +0200194{
Akshay Joshi0206e352011-08-16 15:34:10 -0400195 drm_i915_private_t *dev_priv = overlay->dev->dev_private;
Daniel Vetter02e792f2009-09-15 22:57:34 +0200196 struct overlay_registers *regs;
197
Chris Wilson9bb2ff72010-08-12 12:02:11 +0100198 if (OVERLAY_NEEDS_PHYSICAL(overlay->dev))
Daniel Vetter02e792f2009-09-15 22:57:34 +0200199 regs = overlay->reg_bo->phys_obj->handle->vaddr;
Chris Wilson9bb2ff72010-08-12 12:02:11 +0100200 else
Chris Wilson8d74f652010-08-12 10:35:26 +0100201 regs = io_mapping_map_wc(dev_priv->mm.gtt_mapping,
202 overlay->reg_bo->gtt_offset);
Daniel Vetter02e792f2009-09-15 22:57:34 +0200203
Chris Wilson9bb2ff72010-08-12 12:02:11 +0100204 return regs;
Daniel Vetter02e792f2009-09-15 22:57:34 +0200205}
206
Chris Wilson9bb2ff72010-08-12 12:02:11 +0100207static void intel_overlay_unmap_regs(struct intel_overlay *overlay,
208 struct overlay_registers *regs)
Daniel Vetter02e792f2009-09-15 22:57:34 +0200209{
Chris Wilson8d74f652010-08-12 10:35:26 +0100210 if (!OVERLAY_NEEDS_PHYSICAL(overlay->dev))
Chris Wilson9bb2ff72010-08-12 12:02:11 +0100211 io_mapping_unmap(regs);
Daniel Vetter02e792f2009-09-15 22:57:34 +0200212}
Daniel Vetter02e792f2009-09-15 22:57:34 +0200213
Chris Wilsonb6c028e2010-08-12 11:55:08 +0100214static int intel_overlay_do_wait_request(struct intel_overlay *overlay,
Chris Wilson8dc5d142010-08-12 12:36:12 +0100215 struct drm_i915_gem_request *request,
Chris Wilsonb303cf92010-08-12 14:03:48 +0100216 void (*tail)(struct intel_overlay *))
Chris Wilsonb6c028e2010-08-12 11:55:08 +0100217{
218 struct drm_device *dev = overlay->dev;
219 drm_i915_private_t *dev_priv = dev->dev_private;
220 int ret;
Daniel Vetter02e792f2009-09-15 22:57:34 +0200221
Chris Wilsonb303cf92010-08-12 14:03:48 +0100222 BUG_ON(overlay->last_flip_req);
Chris Wilsondb53a302011-02-03 11:57:46 +0000223 ret = i915_add_request(LP_RING(dev_priv), NULL, request);
Chris Wilson3cce4692010-10-27 16:11:02 +0100224 if (ret) {
225 kfree(request);
226 return ret;
227 }
228 overlay->last_flip_req = request->seqno;
Chris Wilsonb303cf92010-08-12 14:03:48 +0100229 overlay->flip_tail = tail;
Ben Widawskyb93f9cf2012-01-25 15:39:34 -0800230 ret = i915_wait_request(LP_RING(dev_priv), overlay->last_flip_req,
231 true);
Chris Wilsonb6c028e2010-08-12 11:55:08 +0100232 if (ret)
233 return ret;
234
Chris Wilsonb6c028e2010-08-12 11:55:08 +0100235 overlay->last_flip_req = 0;
236 return 0;
237}
238
Chris Wilson106dada2010-07-16 17:13:01 +0100239/* Workaround for i830 bug where pipe a must be enable to change control regs */
240static int
241i830_activate_pipe_a(struct drm_device *dev)
242{
243 drm_i915_private_t *dev_priv = dev->dev_private;
244 struct intel_crtc *crtc;
245 struct drm_crtc_helper_funcs *crtc_funcs;
246 struct drm_display_mode vesa_640x480 = {
247 DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
248 752, 800, 0, 480, 489, 492, 525, 0,
249 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC)
250 }, *mode;
251
252 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[0]);
253 if (crtc->dpms_mode == DRM_MODE_DPMS_ON)
254 return 0;
255
256 /* most i8xx have pipe a forced on, so don't trust dpms mode */
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800257 if (I915_READ(_PIPEACONF) & PIPECONF_ENABLE)
Chris Wilson106dada2010-07-16 17:13:01 +0100258 return 0;
259
260 crtc_funcs = crtc->base.helper_private;
261 if (crtc_funcs->dpms == NULL)
262 return 0;
263
264 DRM_DEBUG_DRIVER("Enabling pipe A in order to enable overlay\n");
265
266 mode = drm_mode_duplicate(dev, &vesa_640x480);
Daniel Vetterca9bfa72012-01-28 14:49:20 +0100267 drm_mode_set_crtcinfo(mode, 0);
Akshay Joshi0206e352011-08-16 15:34:10 -0400268 if (!drm_crtc_helper_set_mode(&crtc->base, mode,
Chris Wilson106dada2010-07-16 17:13:01 +0100269 crtc->base.x, crtc->base.y,
270 crtc->base.fb))
271 return 0;
272
273 crtc_funcs->dpms(&crtc->base, DRM_MODE_DPMS_ON);
274 return 1;
275}
276
277static void
278i830_deactivate_pipe_a(struct drm_device *dev)
279{
280 drm_i915_private_t *dev_priv = dev->dev_private;
281 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[0];
282 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
283
284 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
Daniel Vetter02e792f2009-09-15 22:57:34 +0200285}
286
287/* overlay needs to be disable in OCMD reg */
288static int intel_overlay_on(struct intel_overlay *overlay)
289{
290 struct drm_device *dev = overlay->dev;
Chris Wilsone1f99ce2010-10-27 12:45:26 +0100291 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilson8dc5d142010-08-12 12:36:12 +0100292 struct drm_i915_gem_request *request;
Chris Wilson106dada2010-07-16 17:13:01 +0100293 int pipe_a_quirk = 0;
Daniel Vetter02e792f2009-09-15 22:57:34 +0200294 int ret;
Daniel Vetter02e792f2009-09-15 22:57:34 +0200295
296 BUG_ON(overlay->active);
Daniel Vetter03f77ea2009-09-15 22:57:37 +0200297 overlay->active = 1;
Daniel Vetter03f77ea2009-09-15 22:57:37 +0200298
Chris Wilson106dada2010-07-16 17:13:01 +0100299 if (IS_I830(dev)) {
300 pipe_a_quirk = i830_activate_pipe_a(dev);
301 if (pipe_a_quirk < 0)
302 return pipe_a_quirk;
303 }
304
Chris Wilson8dc5d142010-08-12 12:36:12 +0100305 request = kzalloc(sizeof(*request), GFP_KERNEL);
Chris Wilson106dada2010-07-16 17:13:01 +0100306 if (request == NULL) {
307 ret = -ENOMEM;
308 goto out;
309 }
Daniel Vetter02e792f2009-09-15 22:57:34 +0200310
Chris Wilsone1f99ce2010-10-27 12:45:26 +0100311 ret = BEGIN_LP_RING(4);
312 if (ret) {
313 kfree(request);
314 goto out;
315 }
316
Daniel Vetter02e792f2009-09-15 22:57:34 +0200317 OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_ON);
318 OUT_RING(overlay->flip_addr | OFC_UPDATE);
319 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
320 OUT_RING(MI_NOOP);
321 ADVANCE_LP_RING();
322
Chris Wilsonce453d82011-02-21 14:43:56 +0000323 ret = intel_overlay_do_wait_request(overlay, request, NULL);
Chris Wilson106dada2010-07-16 17:13:01 +0100324out:
325 if (pipe_a_quirk)
326 i830_deactivate_pipe_a(dev);
Daniel Vetter02e792f2009-09-15 22:57:34 +0200327
Chris Wilson106dada2010-07-16 17:13:01 +0100328 return ret;
Daniel Vetter02e792f2009-09-15 22:57:34 +0200329}
330
331/* overlay needs to be enabled in OCMD reg */
Chris Wilson8dc5d142010-08-12 12:36:12 +0100332static int intel_overlay_continue(struct intel_overlay *overlay,
333 bool load_polyphase_filter)
Daniel Vetter02e792f2009-09-15 22:57:34 +0200334{
335 struct drm_device *dev = overlay->dev;
Akshay Joshi0206e352011-08-16 15:34:10 -0400336 drm_i915_private_t *dev_priv = dev->dev_private;
Chris Wilson8dc5d142010-08-12 12:36:12 +0100337 struct drm_i915_gem_request *request;
Daniel Vetter02e792f2009-09-15 22:57:34 +0200338 u32 flip_addr = overlay->flip_addr;
339 u32 tmp;
Chris Wilsone1f99ce2010-10-27 12:45:26 +0100340 int ret;
Daniel Vetter02e792f2009-09-15 22:57:34 +0200341
342 BUG_ON(!overlay->active);
343
Chris Wilson8dc5d142010-08-12 12:36:12 +0100344 request = kzalloc(sizeof(*request), GFP_KERNEL);
345 if (request == NULL)
346 return -ENOMEM;
347
Daniel Vetter02e792f2009-09-15 22:57:34 +0200348 if (load_polyphase_filter)
349 flip_addr |= OFC_UPDATE;
350
351 /* check for underruns */
352 tmp = I915_READ(DOVSTA);
353 if (tmp & (1 << 17))
354 DRM_DEBUG("overlay underrun, DOVSTA: %x\n", tmp);
355
Chris Wilsone1f99ce2010-10-27 12:45:26 +0100356 ret = BEGIN_LP_RING(2);
357 if (ret) {
358 kfree(request);
359 return ret;
360 }
Daniel Vetter02e792f2009-09-15 22:57:34 +0200361 OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE);
362 OUT_RING(flip_addr);
Akshay Joshi0206e352011-08-16 15:34:10 -0400363 ADVANCE_LP_RING();
Daniel Vetter5a5a0c62009-09-15 22:57:36 +0200364
Chris Wilsondb53a302011-02-03 11:57:46 +0000365 ret = i915_add_request(LP_RING(dev_priv), NULL, request);
Chris Wilson3cce4692010-10-27 16:11:02 +0100366 if (ret) {
367 kfree(request);
368 return ret;
369 }
370
371 overlay->last_flip_req = request->seqno;
Daniel Vetter03f77ea2009-09-15 22:57:37 +0200372 return 0;
Daniel Vetter02e792f2009-09-15 22:57:34 +0200373}
374
Chris Wilsonb303cf92010-08-12 14:03:48 +0100375static void intel_overlay_release_old_vid_tail(struct intel_overlay *overlay)
Daniel Vetter02e792f2009-09-15 22:57:34 +0200376{
Chris Wilson05394f32010-11-08 19:18:58 +0000377 struct drm_i915_gem_object *obj = overlay->old_vid_bo;
Daniel Vetter02e792f2009-09-15 22:57:34 +0200378
Chris Wilsonb303cf92010-08-12 14:03:48 +0100379 i915_gem_object_unpin(obj);
Chris Wilson05394f32010-11-08 19:18:58 +0000380 drm_gem_object_unreference(&obj->base);
Daniel Vetter02e792f2009-09-15 22:57:34 +0200381
Chris Wilsonb303cf92010-08-12 14:03:48 +0100382 overlay->old_vid_bo = NULL;
Daniel Vetter02e792f2009-09-15 22:57:34 +0200383}
384
Daniel Vetter12ca45f2037-04-25 10:08:26 +0200385static void intel_overlay_off_tail(struct intel_overlay *overlay)
386{
Chris Wilson05394f32010-11-08 19:18:58 +0000387 struct drm_i915_gem_object *obj = overlay->vid_bo;
Daniel Vetter12ca45f2037-04-25 10:08:26 +0200388
389 /* never have the overlay hw on without showing a frame */
390 BUG_ON(!overlay->vid_bo);
Daniel Vetter12ca45f2037-04-25 10:08:26 +0200391
392 i915_gem_object_unpin(obj);
Chris Wilson05394f32010-11-08 19:18:58 +0000393 drm_gem_object_unreference(&obj->base);
Daniel Vetter12ca45f2037-04-25 10:08:26 +0200394 overlay->vid_bo = NULL;
395
396 overlay->crtc->overlay = NULL;
397 overlay->crtc = NULL;
398 overlay->active = 0;
399}
400
Daniel Vetter02e792f2009-09-15 22:57:34 +0200401/* overlay needs to be disabled in OCMD reg */
Chris Wilsonce453d82011-02-21 14:43:56 +0000402static int intel_overlay_off(struct intel_overlay *overlay)
Daniel Vetter03f77ea2009-09-15 22:57:37 +0200403{
404 struct drm_device *dev = overlay->dev;
Chris Wilsone1f99ce2010-10-27 12:45:26 +0100405 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilson8dc5d142010-08-12 12:36:12 +0100406 u32 flip_addr = overlay->flip_addr;
407 struct drm_i915_gem_request *request;
Chris Wilsone1f99ce2010-10-27 12:45:26 +0100408 int ret;
Daniel Vetter02e792f2009-09-15 22:57:34 +0200409
410 BUG_ON(!overlay->active);
411
Chris Wilson8dc5d142010-08-12 12:36:12 +0100412 request = kzalloc(sizeof(*request), GFP_KERNEL);
413 if (request == NULL)
414 return -ENOMEM;
415
Daniel Vetter02e792f2009-09-15 22:57:34 +0200416 /* According to intel docs the overlay hw may hang (when switching
417 * off) without loading the filter coeffs. It is however unclear whether
418 * this applies to the disabling of the overlay or to the switching off
419 * of the hw. Do it in both cases */
420 flip_addr |= OFC_UPDATE;
421
Chris Wilsone1f99ce2010-10-27 12:45:26 +0100422 ret = BEGIN_LP_RING(6);
423 if (ret) {
424 kfree(request);
425 return ret;
426 }
Daniel Vetter02e792f2009-09-15 22:57:34 +0200427 /* wait for overlay to go idle */
Daniel Vetter02e792f2009-09-15 22:57:34 +0200428 OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE);
429 OUT_RING(flip_addr);
Chris Wilson722506f2010-08-12 09:28:50 +0100430 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
Chris Wilson722506f2010-08-12 09:28:50 +0100431 /* turn overlay off */
Chris Wilson722506f2010-08-12 09:28:50 +0100432 OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_OFF);
433 OUT_RING(flip_addr);
434 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
Chris Wilson722506f2010-08-12 09:28:50 +0100435 ADVANCE_LP_RING();
436
Chris Wilsonce453d82011-02-21 14:43:56 +0000437 return intel_overlay_do_wait_request(overlay, request,
Chris Wilsonb303cf92010-08-12 14:03:48 +0100438 intel_overlay_off_tail);
Daniel Vetter02e792f2009-09-15 22:57:34 +0200439}
440
Daniel Vetter03f77ea2009-09-15 22:57:37 +0200441/* recover from an interruption due to a signal
442 * We have to be careful not to repeat work forever an make forward progess. */
Chris Wilsonce453d82011-02-21 14:43:56 +0000443static int intel_overlay_recover_from_interrupt(struct intel_overlay *overlay)
Daniel Vetter03f77ea2009-09-15 22:57:37 +0200444{
445 struct drm_device *dev = overlay->dev;
Zou Nan hai852835f2010-05-21 09:08:56 +0800446 drm_i915_private_t *dev_priv = dev->dev_private;
Daniel Vetter03f77ea2009-09-15 22:57:37 +0200447 int ret;
Daniel Vetter03f77ea2009-09-15 22:57:37 +0200448
Chris Wilsonb303cf92010-08-12 14:03:48 +0100449 if (overlay->last_flip_req == 0)
450 return 0;
Daniel Vetter03f77ea2009-09-15 22:57:37 +0200451
Ben Widawskyb93f9cf2012-01-25 15:39:34 -0800452 ret = i915_wait_request(LP_RING(dev_priv), overlay->last_flip_req,
453 true);
Chris Wilsonb6c028e2010-08-12 11:55:08 +0100454 if (ret)
Daniel Vetter03f77ea2009-09-15 22:57:37 +0200455 return ret;
456
Chris Wilsonb303cf92010-08-12 14:03:48 +0100457 if (overlay->flip_tail)
458 overlay->flip_tail(overlay);
Daniel Vetter03f77ea2009-09-15 22:57:37 +0200459
Daniel Vetter03f77ea2009-09-15 22:57:37 +0200460 overlay->last_flip_req = 0;
461 return 0;
462}
463
Daniel Vetter5a5a0c62009-09-15 22:57:36 +0200464/* Wait for pending overlay flip and release old frame.
465 * Needs to be called before the overlay register are changed
Chris Wilson8d74f652010-08-12 10:35:26 +0100466 * via intel_overlay_(un)map_regs
467 */
Daniel Vetter02e792f2009-09-15 22:57:34 +0200468static int intel_overlay_release_old_vid(struct intel_overlay *overlay)
469{
Chris Wilson5cd68c92010-08-12 12:21:54 +0100470 struct drm_device *dev = overlay->dev;
471 drm_i915_private_t *dev_priv = dev->dev_private;
Daniel Vetter02e792f2009-09-15 22:57:34 +0200472 int ret;
Daniel Vetter02e792f2009-09-15 22:57:34 +0200473
Chris Wilson5cd68c92010-08-12 12:21:54 +0100474 /* Only wait if there is actually an old frame to release to
475 * guarantee forward progress.
476 */
Daniel Vetter03f77ea2009-09-15 22:57:37 +0200477 if (!overlay->old_vid_bo)
478 return 0;
479
Chris Wilson5cd68c92010-08-12 12:21:54 +0100480 if (I915_READ(ISR) & I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT) {
Chris Wilson8dc5d142010-08-12 12:36:12 +0100481 struct drm_i915_gem_request *request;
Daniel Vetter02e792f2009-09-15 22:57:34 +0200482
Chris Wilson5cd68c92010-08-12 12:21:54 +0100483 /* synchronous slowpath */
Chris Wilson8dc5d142010-08-12 12:36:12 +0100484 request = kzalloc(sizeof(*request), GFP_KERNEL);
485 if (request == NULL)
486 return -ENOMEM;
Daniel Vetter02e792f2009-09-15 22:57:34 +0200487
Chris Wilsone1f99ce2010-10-27 12:45:26 +0100488 ret = BEGIN_LP_RING(2);
489 if (ret) {
490 kfree(request);
491 return ret;
492 }
493
Chris Wilson5cd68c92010-08-12 12:21:54 +0100494 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
495 OUT_RING(MI_NOOP);
496 ADVANCE_LP_RING();
Daniel Vetter02e792f2009-09-15 22:57:34 +0200497
Chris Wilsonce453d82011-02-21 14:43:56 +0000498 ret = intel_overlay_do_wait_request(overlay, request,
Chris Wilsonb303cf92010-08-12 14:03:48 +0100499 intel_overlay_release_old_vid_tail);
Chris Wilson5cd68c92010-08-12 12:21:54 +0100500 if (ret)
501 return ret;
502 }
Daniel Vetter02e792f2009-09-15 22:57:34 +0200503
Chris Wilson5cd68c92010-08-12 12:21:54 +0100504 intel_overlay_release_old_vid_tail(overlay);
Daniel Vetter02e792f2009-09-15 22:57:34 +0200505 return 0;
506}
507
508struct put_image_params {
509 int format;
510 short dst_x;
511 short dst_y;
512 short dst_w;
513 short dst_h;
514 short src_w;
515 short src_scan_h;
516 short src_scan_w;
517 short src_h;
518 short stride_Y;
519 short stride_UV;
520 int offset_Y;
521 int offset_U;
522 int offset_V;
523};
524
525static int packed_depth_bytes(u32 format)
526{
527 switch (format & I915_OVERLAY_DEPTH_MASK) {
Chris Wilson722506f2010-08-12 09:28:50 +0100528 case I915_OVERLAY_YUV422:
529 return 4;
530 case I915_OVERLAY_YUV411:
531 /* return 6; not implemented */
532 default:
533 return -EINVAL;
Daniel Vetter02e792f2009-09-15 22:57:34 +0200534 }
535}
536
537static int packed_width_bytes(u32 format, short width)
538{
539 switch (format & I915_OVERLAY_DEPTH_MASK) {
Chris Wilson722506f2010-08-12 09:28:50 +0100540 case I915_OVERLAY_YUV422:
541 return width << 1;
542 default:
543 return -EINVAL;
Daniel Vetter02e792f2009-09-15 22:57:34 +0200544 }
545}
546
547static int uv_hsubsampling(u32 format)
548{
549 switch (format & I915_OVERLAY_DEPTH_MASK) {
Chris Wilson722506f2010-08-12 09:28:50 +0100550 case I915_OVERLAY_YUV422:
551 case I915_OVERLAY_YUV420:
552 return 2;
553 case I915_OVERLAY_YUV411:
554 case I915_OVERLAY_YUV410:
555 return 4;
556 default:
557 return -EINVAL;
Daniel Vetter02e792f2009-09-15 22:57:34 +0200558 }
559}
560
561static int uv_vsubsampling(u32 format)
562{
563 switch (format & I915_OVERLAY_DEPTH_MASK) {
Chris Wilson722506f2010-08-12 09:28:50 +0100564 case I915_OVERLAY_YUV420:
565 case I915_OVERLAY_YUV410:
566 return 2;
567 case I915_OVERLAY_YUV422:
568 case I915_OVERLAY_YUV411:
569 return 1;
570 default:
571 return -EINVAL;
Daniel Vetter02e792f2009-09-15 22:57:34 +0200572 }
573}
574
575static u32 calc_swidthsw(struct drm_device *dev, u32 offset, u32 width)
576{
577 u32 mask, shift, ret;
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100578 if (IS_GEN2(dev)) {
Daniel Vetter02e792f2009-09-15 22:57:34 +0200579 mask = 0x1f;
580 shift = 5;
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100581 } else {
582 mask = 0x3f;
583 shift = 6;
Daniel Vetter02e792f2009-09-15 22:57:34 +0200584 }
585 ret = ((offset + width + mask) >> shift) - (offset >> shift);
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100586 if (!IS_GEN2(dev))
Daniel Vetter02e792f2009-09-15 22:57:34 +0200587 ret <<= 1;
Akshay Joshi0206e352011-08-16 15:34:10 -0400588 ret -= 1;
Daniel Vetter02e792f2009-09-15 22:57:34 +0200589 return ret << 2;
590}
591
592static const u16 y_static_hcoeffs[N_HORIZ_Y_TAPS * N_PHASES] = {
593 0x3000, 0xb4a0, 0x1930, 0x1920, 0xb4a0,
594 0x3000, 0xb500, 0x19d0, 0x1880, 0xb440,
595 0x3000, 0xb540, 0x1a88, 0x2f80, 0xb3e0,
596 0x3000, 0xb580, 0x1b30, 0x2e20, 0xb380,
597 0x3000, 0xb5c0, 0x1bd8, 0x2cc0, 0xb320,
598 0x3020, 0xb5e0, 0x1c60, 0x2b80, 0xb2c0,
599 0x3020, 0xb5e0, 0x1cf8, 0x2a20, 0xb260,
600 0x3020, 0xb5e0, 0x1d80, 0x28e0, 0xb200,
601 0x3020, 0xb5c0, 0x1e08, 0x3f40, 0xb1c0,
602 0x3020, 0xb580, 0x1e78, 0x3ce0, 0xb160,
603 0x3040, 0xb520, 0x1ed8, 0x3aa0, 0xb120,
604 0x3040, 0xb4a0, 0x1f30, 0x3880, 0xb0e0,
605 0x3040, 0xb400, 0x1f78, 0x3680, 0xb0a0,
606 0x3020, 0xb340, 0x1fb8, 0x34a0, 0xb060,
607 0x3020, 0xb240, 0x1fe0, 0x32e0, 0xb040,
608 0x3020, 0xb140, 0x1ff8, 0x3160, 0xb020,
Chris Wilson722506f2010-08-12 09:28:50 +0100609 0xb000, 0x3000, 0x0800, 0x3000, 0xb000
610};
611
Daniel Vetter02e792f2009-09-15 22:57:34 +0200612static const u16 uv_static_hcoeffs[N_HORIZ_UV_TAPS * N_PHASES] = {
613 0x3000, 0x1800, 0x1800, 0xb000, 0x18d0, 0x2e60,
614 0xb000, 0x1990, 0x2ce0, 0xb020, 0x1a68, 0x2b40,
615 0xb040, 0x1b20, 0x29e0, 0xb060, 0x1bd8, 0x2880,
616 0xb080, 0x1c88, 0x3e60, 0xb0a0, 0x1d28, 0x3c00,
617 0xb0c0, 0x1db8, 0x39e0, 0xb0e0, 0x1e40, 0x37e0,
618 0xb100, 0x1eb8, 0x3620, 0xb100, 0x1f18, 0x34a0,
619 0xb100, 0x1f68, 0x3360, 0xb0e0, 0x1fa8, 0x3240,
620 0xb0c0, 0x1fe0, 0x3140, 0xb060, 0x1ff0, 0x30a0,
Chris Wilson722506f2010-08-12 09:28:50 +0100621 0x3000, 0x0800, 0x3000
622};
Daniel Vetter02e792f2009-09-15 22:57:34 +0200623
624static void update_polyphase_filter(struct overlay_registers *regs)
625{
626 memcpy(regs->Y_HCOEFS, y_static_hcoeffs, sizeof(y_static_hcoeffs));
627 memcpy(regs->UV_HCOEFS, uv_static_hcoeffs, sizeof(uv_static_hcoeffs));
628}
629
630static bool update_scaling_factors(struct intel_overlay *overlay,
631 struct overlay_registers *regs,
632 struct put_image_params *params)
633{
634 /* fixed point with a 12 bit shift */
635 u32 xscale, yscale, xscale_UV, yscale_UV;
636#define FP_SHIFT 12
637#define FRACT_MASK 0xfff
638 bool scale_changed = false;
639 int uv_hscale = uv_hsubsampling(params->format);
640 int uv_vscale = uv_vsubsampling(params->format);
641
642 if (params->dst_w > 1)
643 xscale = ((params->src_scan_w - 1) << FP_SHIFT)
644 /(params->dst_w);
645 else
646 xscale = 1 << FP_SHIFT;
647
648 if (params->dst_h > 1)
649 yscale = ((params->src_scan_h - 1) << FP_SHIFT)
650 /(params->dst_h);
651 else
652 yscale = 1 << FP_SHIFT;
653
654 /*if (params->format & I915_OVERLAY_YUV_PLANAR) {*/
Chris Wilson722506f2010-08-12 09:28:50 +0100655 xscale_UV = xscale/uv_hscale;
656 yscale_UV = yscale/uv_vscale;
657 /* make the Y scale to UV scale ratio an exact multiply */
658 xscale = xscale_UV * uv_hscale;
659 yscale = yscale_UV * uv_vscale;
Daniel Vetter02e792f2009-09-15 22:57:34 +0200660 /*} else {
Chris Wilson722506f2010-08-12 09:28:50 +0100661 xscale_UV = 0;
662 yscale_UV = 0;
663 }*/
Daniel Vetter02e792f2009-09-15 22:57:34 +0200664
665 if (xscale != overlay->old_xscale || yscale != overlay->old_yscale)
666 scale_changed = true;
667 overlay->old_xscale = xscale;
668 overlay->old_yscale = yscale;
669
Chris Wilson722506f2010-08-12 09:28:50 +0100670 regs->YRGBSCALE = (((yscale & FRACT_MASK) << 20) |
671 ((xscale >> FP_SHIFT) << 16) |
672 ((xscale & FRACT_MASK) << 3));
673
674 regs->UVSCALE = (((yscale_UV & FRACT_MASK) << 20) |
675 ((xscale_UV >> FP_SHIFT) << 16) |
676 ((xscale_UV & FRACT_MASK) << 3));
677
678 regs->UVSCALEV = ((((yscale >> FP_SHIFT) << 16) |
679 ((yscale_UV >> FP_SHIFT) << 0)));
Daniel Vetter02e792f2009-09-15 22:57:34 +0200680
681 if (scale_changed)
682 update_polyphase_filter(regs);
683
684 return scale_changed;
685}
686
687static void update_colorkey(struct intel_overlay *overlay,
688 struct overlay_registers *regs)
689{
690 u32 key = overlay->color_key;
Chris Wilson6ba3ddd2010-08-12 09:30:58 +0100691
Daniel Vetter02e792f2009-09-15 22:57:34 +0200692 switch (overlay->crtc->base.fb->bits_per_pixel) {
Chris Wilson722506f2010-08-12 09:28:50 +0100693 case 8:
694 regs->DCLRKV = 0;
695 regs->DCLRKM = CLK_RGB8I_MASK | DST_KEY_ENABLE;
Chris Wilson6ba3ddd2010-08-12 09:30:58 +0100696 break;
697
Chris Wilson722506f2010-08-12 09:28:50 +0100698 case 16:
699 if (overlay->crtc->base.fb->depth == 15) {
700 regs->DCLRKV = RGB15_TO_COLORKEY(key);
701 regs->DCLRKM = CLK_RGB15_MASK | DST_KEY_ENABLE;
702 } else {
703 regs->DCLRKV = RGB16_TO_COLORKEY(key);
704 regs->DCLRKM = CLK_RGB16_MASK | DST_KEY_ENABLE;
705 }
Chris Wilson6ba3ddd2010-08-12 09:30:58 +0100706 break;
707
Chris Wilson722506f2010-08-12 09:28:50 +0100708 case 24:
709 case 32:
710 regs->DCLRKV = key;
711 regs->DCLRKM = CLK_RGB24_MASK | DST_KEY_ENABLE;
Chris Wilson6ba3ddd2010-08-12 09:30:58 +0100712 break;
Daniel Vetter02e792f2009-09-15 22:57:34 +0200713 }
714}
715
716static u32 overlay_cmd_reg(struct put_image_params *params)
717{
718 u32 cmd = OCMD_ENABLE | OCMD_BUF_TYPE_FRAME | OCMD_BUFFER0;
719
720 if (params->format & I915_OVERLAY_YUV_PLANAR) {
721 switch (params->format & I915_OVERLAY_DEPTH_MASK) {
Chris Wilson722506f2010-08-12 09:28:50 +0100722 case I915_OVERLAY_YUV422:
723 cmd |= OCMD_YUV_422_PLANAR;
724 break;
725 case I915_OVERLAY_YUV420:
726 cmd |= OCMD_YUV_420_PLANAR;
727 break;
728 case I915_OVERLAY_YUV411:
729 case I915_OVERLAY_YUV410:
730 cmd |= OCMD_YUV_410_PLANAR;
731 break;
Daniel Vetter02e792f2009-09-15 22:57:34 +0200732 }
733 } else { /* YUV packed */
734 switch (params->format & I915_OVERLAY_DEPTH_MASK) {
Chris Wilson722506f2010-08-12 09:28:50 +0100735 case I915_OVERLAY_YUV422:
736 cmd |= OCMD_YUV_422_PACKED;
737 break;
738 case I915_OVERLAY_YUV411:
739 cmd |= OCMD_YUV_411_PACKED;
740 break;
Daniel Vetter02e792f2009-09-15 22:57:34 +0200741 }
742
743 switch (params->format & I915_OVERLAY_SWAP_MASK) {
Chris Wilson722506f2010-08-12 09:28:50 +0100744 case I915_OVERLAY_NO_SWAP:
745 break;
746 case I915_OVERLAY_UV_SWAP:
747 cmd |= OCMD_UV_SWAP;
748 break;
749 case I915_OVERLAY_Y_SWAP:
750 cmd |= OCMD_Y_SWAP;
751 break;
752 case I915_OVERLAY_Y_AND_UV_SWAP:
753 cmd |= OCMD_Y_AND_UV_SWAP;
754 break;
Daniel Vetter02e792f2009-09-15 22:57:34 +0200755 }
756 }
757
758 return cmd;
759}
760
Chris Wilson5fe82c52010-08-12 12:38:21 +0100761static int intel_overlay_do_put_image(struct intel_overlay *overlay,
Chris Wilson05394f32010-11-08 19:18:58 +0000762 struct drm_i915_gem_object *new_bo,
Chris Wilson5fe82c52010-08-12 12:38:21 +0100763 struct put_image_params *params)
Daniel Vetter02e792f2009-09-15 22:57:34 +0200764{
765 int ret, tmp_width;
766 struct overlay_registers *regs;
767 bool scale_changed = false;
Daniel Vetter02e792f2009-09-15 22:57:34 +0200768 struct drm_device *dev = overlay->dev;
769
770 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
771 BUG_ON(!mutex_is_locked(&dev->mode_config.mutex));
772 BUG_ON(!overlay);
773
Daniel Vetter02e792f2009-09-15 22:57:34 +0200774 ret = intel_overlay_release_old_vid(overlay);
775 if (ret != 0)
776 return ret;
777
Chris Wilson2da3b9b2011-04-14 09:41:17 +0100778 ret = i915_gem_object_pin_to_display_plane(new_bo, 0, NULL);
Daniel Vetter02e792f2009-09-15 22:57:34 +0200779 if (ret != 0)
780 return ret;
781
Chris Wilsond9e86c02010-11-10 16:40:20 +0000782 ret = i915_gem_object_put_fence(new_bo);
783 if (ret)
784 goto out_unpin;
785
Daniel Vetter02e792f2009-09-15 22:57:34 +0200786 if (!overlay->active) {
Chris Wilson8d74f652010-08-12 10:35:26 +0100787 regs = intel_overlay_map_regs(overlay);
Daniel Vetter02e792f2009-09-15 22:57:34 +0200788 if (!regs) {
789 ret = -ENOMEM;
790 goto out_unpin;
791 }
792 regs->OCONFIG = OCONF_CC_OUT_8BIT;
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100793 if (IS_GEN4(overlay->dev))
Daniel Vetter02e792f2009-09-15 22:57:34 +0200794 regs->OCONFIG |= OCONF_CSC_MODE_BT709;
795 regs->OCONFIG |= overlay->crtc->pipe == 0 ?
796 OCONF_PIPE_A : OCONF_PIPE_B;
Chris Wilson9bb2ff72010-08-12 12:02:11 +0100797 intel_overlay_unmap_regs(overlay, regs);
Daniel Vetter02e792f2009-09-15 22:57:34 +0200798
799 ret = intel_overlay_on(overlay);
800 if (ret != 0)
801 goto out_unpin;
802 }
803
Chris Wilson8d74f652010-08-12 10:35:26 +0100804 regs = intel_overlay_map_regs(overlay);
Daniel Vetter02e792f2009-09-15 22:57:34 +0200805 if (!regs) {
806 ret = -ENOMEM;
807 goto out_unpin;
808 }
809
810 regs->DWINPOS = (params->dst_y << 16) | params->dst_x;
811 regs->DWINSZ = (params->dst_h << 16) | params->dst_w;
812
813 if (params->format & I915_OVERLAY_YUV_PACKED)
814 tmp_width = packed_width_bytes(params->format, params->src_w);
815 else
816 tmp_width = params->src_w;
817
818 regs->SWIDTH = params->src_w;
819 regs->SWIDTHSW = calc_swidthsw(overlay->dev,
Chris Wilson722506f2010-08-12 09:28:50 +0100820 params->offset_Y, tmp_width);
Daniel Vetter02e792f2009-09-15 22:57:34 +0200821 regs->SHEIGHT = params->src_h;
Akshay Joshi0206e352011-08-16 15:34:10 -0400822 regs->OBUF_0Y = new_bo->gtt_offset + params->offset_Y;
Daniel Vetter02e792f2009-09-15 22:57:34 +0200823 regs->OSTRIDE = params->stride_Y;
824
825 if (params->format & I915_OVERLAY_YUV_PLANAR) {
826 int uv_hscale = uv_hsubsampling(params->format);
827 int uv_vscale = uv_vsubsampling(params->format);
828 u32 tmp_U, tmp_V;
829 regs->SWIDTH |= (params->src_w/uv_hscale) << 16;
830 tmp_U = calc_swidthsw(overlay->dev, params->offset_U,
Chris Wilson722506f2010-08-12 09:28:50 +0100831 params->src_w/uv_hscale);
Daniel Vetter02e792f2009-09-15 22:57:34 +0200832 tmp_V = calc_swidthsw(overlay->dev, params->offset_V,
Chris Wilson722506f2010-08-12 09:28:50 +0100833 params->src_w/uv_hscale);
Daniel Vetter02e792f2009-09-15 22:57:34 +0200834 regs->SWIDTHSW |= max_t(u32, tmp_U, tmp_V) << 16;
835 regs->SHEIGHT |= (params->src_h/uv_vscale) << 16;
Chris Wilson05394f32010-11-08 19:18:58 +0000836 regs->OBUF_0U = new_bo->gtt_offset + params->offset_U;
837 regs->OBUF_0V = new_bo->gtt_offset + params->offset_V;
Daniel Vetter02e792f2009-09-15 22:57:34 +0200838 regs->OSTRIDE |= params->stride_UV << 16;
839 }
840
841 scale_changed = update_scaling_factors(overlay, regs, params);
842
843 update_colorkey(overlay, regs);
844
845 regs->OCMD = overlay_cmd_reg(params);
846
Chris Wilson9bb2ff72010-08-12 12:02:11 +0100847 intel_overlay_unmap_regs(overlay, regs);
Daniel Vetter02e792f2009-09-15 22:57:34 +0200848
Chris Wilson8dc5d142010-08-12 12:36:12 +0100849 ret = intel_overlay_continue(overlay, scale_changed);
850 if (ret)
851 goto out_unpin;
Daniel Vetter02e792f2009-09-15 22:57:34 +0200852
853 overlay->old_vid_bo = overlay->vid_bo;
Chris Wilson05394f32010-11-08 19:18:58 +0000854 overlay->vid_bo = new_bo;
Daniel Vetter02e792f2009-09-15 22:57:34 +0200855
856 return 0;
857
858out_unpin:
859 i915_gem_object_unpin(new_bo);
860 return ret;
861}
862
Chris Wilsonce453d82011-02-21 14:43:56 +0000863int intel_overlay_switch_off(struct intel_overlay *overlay)
Daniel Vetter02e792f2009-09-15 22:57:34 +0200864{
Daniel Vetter02e792f2009-09-15 22:57:34 +0200865 struct overlay_registers *regs;
Daniel Vetter02e792f2009-09-15 22:57:34 +0200866 struct drm_device *dev = overlay->dev;
Chris Wilson5dcdbcb2010-08-12 13:50:28 +0100867 int ret;
Daniel Vetter02e792f2009-09-15 22:57:34 +0200868
869 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
870 BUG_ON(!mutex_is_locked(&dev->mode_config.mutex));
871
Chris Wilsonce453d82011-02-21 14:43:56 +0000872 ret = intel_overlay_recover_from_interrupt(overlay);
Chris Wilsonb303cf92010-08-12 14:03:48 +0100873 if (ret != 0)
874 return ret;
Daniel Vetter9bedb972009-11-30 15:55:49 +0100875
Daniel Vetter02e792f2009-09-15 22:57:34 +0200876 if (!overlay->active)
877 return 0;
878
Daniel Vetter02e792f2009-09-15 22:57:34 +0200879 ret = intel_overlay_release_old_vid(overlay);
880 if (ret != 0)
881 return ret;
882
Chris Wilson8d74f652010-08-12 10:35:26 +0100883 regs = intel_overlay_map_regs(overlay);
Daniel Vetter02e792f2009-09-15 22:57:34 +0200884 regs->OCMD = 0;
Chris Wilson9bb2ff72010-08-12 12:02:11 +0100885 intel_overlay_unmap_regs(overlay, regs);
Daniel Vetter02e792f2009-09-15 22:57:34 +0200886
Chris Wilsonce453d82011-02-21 14:43:56 +0000887 ret = intel_overlay_off(overlay);
Daniel Vetter03f77ea2009-09-15 22:57:37 +0200888 if (ret != 0)
889 return ret;
890
Daniel Vetter12ca45f2037-04-25 10:08:26 +0200891 intel_overlay_off_tail(overlay);
Daniel Vetter02e792f2009-09-15 22:57:34 +0200892 return 0;
893}
894
895static int check_overlay_possible_on_crtc(struct intel_overlay *overlay,
896 struct intel_crtc *crtc)
897{
Chris Wilson722506f2010-08-12 09:28:50 +0100898 drm_i915_private_t *dev_priv = overlay->dev->dev_private;
Daniel Vetter02e792f2009-09-15 22:57:34 +0200899
Chris Wilsonf7abfe82010-09-13 14:19:16 +0100900 if (!crtc->active)
Daniel Vetter02e792f2009-09-15 22:57:34 +0200901 return -EINVAL;
902
Daniel Vetter02e792f2009-09-15 22:57:34 +0200903 /* can't use the overlay with double wide pipe */
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100904 if (INTEL_INFO(overlay->dev)->gen < 4 &&
Chris Wilsonf7abfe82010-09-13 14:19:16 +0100905 (I915_READ(PIPECONF(crtc->pipe)) & (PIPECONF_DOUBLE_WIDE | PIPECONF_ENABLE)) != PIPECONF_ENABLE)
Daniel Vetter02e792f2009-09-15 22:57:34 +0200906 return -EINVAL;
907
908 return 0;
909}
910
911static void update_pfit_vscale_ratio(struct intel_overlay *overlay)
912{
913 struct drm_device *dev = overlay->dev;
Chris Wilson722506f2010-08-12 09:28:50 +0100914 drm_i915_private_t *dev_priv = dev->dev_private;
Daniel Vetter02e792f2009-09-15 22:57:34 +0200915 u32 pfit_control = I915_READ(PFIT_CONTROL);
Chris Wilson446d2182010-08-12 11:15:58 +0100916 u32 ratio;
Daniel Vetter02e792f2009-09-15 22:57:34 +0200917
918 /* XXX: This is not the same logic as in the xorg driver, but more in
Chris Wilson446d2182010-08-12 11:15:58 +0100919 * line with the intel documentation for the i965
920 */
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100921 if (INTEL_INFO(dev)->gen >= 4) {
Akshay Joshi0206e352011-08-16 15:34:10 -0400922 /* on i965 use the PGM reg to read out the autoscaler values */
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100923 ratio = I915_READ(PFIT_PGM_RATIOS) >> PFIT_VERT_SCALE_SHIFT_965;
924 } else {
Chris Wilson446d2182010-08-12 11:15:58 +0100925 if (pfit_control & VERT_AUTO_SCALE)
926 ratio = I915_READ(PFIT_AUTO_RATIOS);
Daniel Vetter02e792f2009-09-15 22:57:34 +0200927 else
Chris Wilson446d2182010-08-12 11:15:58 +0100928 ratio = I915_READ(PFIT_PGM_RATIOS);
929 ratio >>= PFIT_VERT_SCALE_SHIFT;
Daniel Vetter02e792f2009-09-15 22:57:34 +0200930 }
931
932 overlay->pfit_vscale_ratio = ratio;
933}
934
935static int check_overlay_dst(struct intel_overlay *overlay,
936 struct drm_intel_overlay_put_image *rec)
937{
938 struct drm_display_mode *mode = &overlay->crtc->base.mode;
939
Daniel Vetter75c13992012-01-28 23:48:46 +0100940 if (rec->dst_x < mode->hdisplay &&
941 rec->dst_x + rec->dst_width <= mode->hdisplay &&
942 rec->dst_y < mode->vdisplay &&
943 rec->dst_y + rec->dst_height <= mode->vdisplay)
Daniel Vetter02e792f2009-09-15 22:57:34 +0200944 return 0;
945 else
946 return -EINVAL;
947}
948
949static int check_overlay_scaling(struct put_image_params *rec)
950{
951 u32 tmp;
952
953 /* downscaling limit is 8.0 */
954 tmp = ((rec->src_scan_h << 16) / rec->dst_h) >> 16;
955 if (tmp > 7)
956 return -EINVAL;
957 tmp = ((rec->src_scan_w << 16) / rec->dst_w) >> 16;
958 if (tmp > 7)
959 return -EINVAL;
960
961 return 0;
962}
963
964static int check_overlay_src(struct drm_device *dev,
965 struct drm_intel_overlay_put_image *rec,
Chris Wilson05394f32010-11-08 19:18:58 +0000966 struct drm_i915_gem_object *new_bo)
Daniel Vetter02e792f2009-09-15 22:57:34 +0200967{
Daniel Vetter02e792f2009-09-15 22:57:34 +0200968 int uv_hscale = uv_hsubsampling(rec->flags);
969 int uv_vscale = uv_vsubsampling(rec->flags);
Dan Carpenter8f28f542010-10-27 23:17:25 +0200970 u32 stride_mask;
971 int depth;
972 u32 tmp;
Daniel Vetter02e792f2009-09-15 22:57:34 +0200973
974 /* check src dimensions */
975 if (IS_845G(dev) || IS_I830(dev)) {
Chris Wilson722506f2010-08-12 09:28:50 +0100976 if (rec->src_height > IMAGE_MAX_HEIGHT_LEGACY ||
Chris Wilson9f7c3f42010-08-12 11:29:34 +0100977 rec->src_width > IMAGE_MAX_WIDTH_LEGACY)
Daniel Vetter02e792f2009-09-15 22:57:34 +0200978 return -EINVAL;
979 } else {
Chris Wilson722506f2010-08-12 09:28:50 +0100980 if (rec->src_height > IMAGE_MAX_HEIGHT ||
Chris Wilson9f7c3f42010-08-12 11:29:34 +0100981 rec->src_width > IMAGE_MAX_WIDTH)
Daniel Vetter02e792f2009-09-15 22:57:34 +0200982 return -EINVAL;
983 }
Chris Wilson9f7c3f42010-08-12 11:29:34 +0100984
Daniel Vetter02e792f2009-09-15 22:57:34 +0200985 /* better safe than sorry, use 4 as the maximal subsampling ratio */
Chris Wilson722506f2010-08-12 09:28:50 +0100986 if (rec->src_height < N_VERT_Y_TAPS*4 ||
Chris Wilson9f7c3f42010-08-12 11:29:34 +0100987 rec->src_width < N_HORIZ_Y_TAPS*4)
Daniel Vetter02e792f2009-09-15 22:57:34 +0200988 return -EINVAL;
989
Chris Wilsona1efd142010-07-12 19:35:38 +0100990 /* check alignment constraints */
Daniel Vetter02e792f2009-09-15 22:57:34 +0200991 switch (rec->flags & I915_OVERLAY_TYPE_MASK) {
Chris Wilson722506f2010-08-12 09:28:50 +0100992 case I915_OVERLAY_RGB:
993 /* not implemented */
994 return -EINVAL;
Chris Wilson9f7c3f42010-08-12 11:29:34 +0100995
Chris Wilson722506f2010-08-12 09:28:50 +0100996 case I915_OVERLAY_YUV_PACKED:
Chris Wilson722506f2010-08-12 09:28:50 +0100997 if (uv_vscale != 1)
Daniel Vetter02e792f2009-09-15 22:57:34 +0200998 return -EINVAL;
Chris Wilson9f7c3f42010-08-12 11:29:34 +0100999
1000 depth = packed_depth_bytes(rec->flags);
Chris Wilson722506f2010-08-12 09:28:50 +01001001 if (depth < 0)
1002 return depth;
Chris Wilson9f7c3f42010-08-12 11:29:34 +01001003
Chris Wilson722506f2010-08-12 09:28:50 +01001004 /* ignore UV planes */
1005 rec->stride_UV = 0;
1006 rec->offset_U = 0;
1007 rec->offset_V = 0;
1008 /* check pixel alignment */
1009 if (rec->offset_Y % depth)
Daniel Vetter02e792f2009-09-15 22:57:34 +02001010 return -EINVAL;
Chris Wilson722506f2010-08-12 09:28:50 +01001011 break;
Chris Wilson9f7c3f42010-08-12 11:29:34 +01001012
Chris Wilson722506f2010-08-12 09:28:50 +01001013 case I915_OVERLAY_YUV_PLANAR:
1014 if (uv_vscale < 0 || uv_hscale < 0)
1015 return -EINVAL;
1016 /* no offset restrictions for planar formats */
1017 break;
Chris Wilson9f7c3f42010-08-12 11:29:34 +01001018
Chris Wilson722506f2010-08-12 09:28:50 +01001019 default:
1020 return -EINVAL;
Daniel Vetter02e792f2009-09-15 22:57:34 +02001021 }
1022
1023 if (rec->src_width % uv_hscale)
1024 return -EINVAL;
1025
1026 /* stride checking */
Chris Wilsona1efd142010-07-12 19:35:38 +01001027 if (IS_I830(dev) || IS_845G(dev))
1028 stride_mask = 255;
1029 else
1030 stride_mask = 63;
Daniel Vetter02e792f2009-09-15 22:57:34 +02001031
1032 if (rec->stride_Y & stride_mask || rec->stride_UV & stride_mask)
1033 return -EINVAL;
Chris Wilsona6c45cf2010-09-17 00:32:17 +01001034 if (IS_GEN4(dev) && rec->stride_Y < 512)
Daniel Vetter02e792f2009-09-15 22:57:34 +02001035 return -EINVAL;
1036
1037 tmp = (rec->flags & I915_OVERLAY_TYPE_MASK) == I915_OVERLAY_YUV_PLANAR ?
Chris Wilson9f7c3f42010-08-12 11:29:34 +01001038 4096 : 8192;
1039 if (rec->stride_Y > tmp || rec->stride_UV > 2*1024)
Daniel Vetter02e792f2009-09-15 22:57:34 +02001040 return -EINVAL;
1041
1042 /* check buffer dimensions */
1043 switch (rec->flags & I915_OVERLAY_TYPE_MASK) {
Chris Wilson722506f2010-08-12 09:28:50 +01001044 case I915_OVERLAY_RGB:
1045 case I915_OVERLAY_YUV_PACKED:
1046 /* always 4 Y values per depth pixels */
1047 if (packed_width_bytes(rec->flags, rec->src_width) > rec->stride_Y)
1048 return -EINVAL;
Daniel Vetter02e792f2009-09-15 22:57:34 +02001049
Chris Wilson722506f2010-08-12 09:28:50 +01001050 tmp = rec->stride_Y*rec->src_height;
Chris Wilson05394f32010-11-08 19:18:58 +00001051 if (rec->offset_Y + tmp > new_bo->base.size)
Chris Wilson722506f2010-08-12 09:28:50 +01001052 return -EINVAL;
1053 break;
Daniel Vetter02e792f2009-09-15 22:57:34 +02001054
Chris Wilson722506f2010-08-12 09:28:50 +01001055 case I915_OVERLAY_YUV_PLANAR:
1056 if (rec->src_width > rec->stride_Y)
1057 return -EINVAL;
1058 if (rec->src_width/uv_hscale > rec->stride_UV)
1059 return -EINVAL;
1060
Chris Wilson9f7c3f42010-08-12 11:29:34 +01001061 tmp = rec->stride_Y * rec->src_height;
Chris Wilson05394f32010-11-08 19:18:58 +00001062 if (rec->offset_Y + tmp > new_bo->base.size)
Chris Wilson722506f2010-08-12 09:28:50 +01001063 return -EINVAL;
Chris Wilson9f7c3f42010-08-12 11:29:34 +01001064
1065 tmp = rec->stride_UV * (rec->src_height / uv_vscale);
Chris Wilson05394f32010-11-08 19:18:58 +00001066 if (rec->offset_U + tmp > new_bo->base.size ||
1067 rec->offset_V + tmp > new_bo->base.size)
Chris Wilson722506f2010-08-12 09:28:50 +01001068 return -EINVAL;
1069 break;
Daniel Vetter02e792f2009-09-15 22:57:34 +02001070 }
1071
1072 return 0;
1073}
1074
Chris Wilsone9e331a2010-09-13 01:16:10 +01001075/**
1076 * Return the pipe currently connected to the panel fitter,
1077 * or -1 if the panel fitter is not present or not in use
1078 */
1079static int intel_panel_fitter_pipe(struct drm_device *dev)
1080{
1081 struct drm_i915_private *dev_priv = dev->dev_private;
1082 u32 pfit_control;
1083
1084 /* i830 doesn't have a panel fitter */
1085 if (IS_I830(dev))
1086 return -1;
1087
1088 pfit_control = I915_READ(PFIT_CONTROL);
1089
1090 /* See if the panel fitter is in use */
1091 if ((pfit_control & PFIT_ENABLE) == 0)
1092 return -1;
1093
1094 /* 965 can place panel fitter on either pipe */
Chris Wilsona6c45cf2010-09-17 00:32:17 +01001095 if (IS_GEN4(dev))
Chris Wilsone9e331a2010-09-13 01:16:10 +01001096 return (pfit_control >> 29) & 0x3;
1097
1098 /* older chips can only use pipe 1 */
1099 return 1;
1100}
1101
Daniel Vetter02e792f2009-09-15 22:57:34 +02001102int intel_overlay_put_image(struct drm_device *dev, void *data,
Akshay Joshi0206e352011-08-16 15:34:10 -04001103 struct drm_file *file_priv)
Daniel Vetter02e792f2009-09-15 22:57:34 +02001104{
1105 struct drm_intel_overlay_put_image *put_image_rec = data;
1106 drm_i915_private_t *dev_priv = dev->dev_private;
1107 struct intel_overlay *overlay;
1108 struct drm_mode_object *drmmode_obj;
1109 struct intel_crtc *crtc;
Chris Wilson05394f32010-11-08 19:18:58 +00001110 struct drm_i915_gem_object *new_bo;
Daniel Vetter02e792f2009-09-15 22:57:34 +02001111 struct put_image_params *params;
1112 int ret;
1113
1114 if (!dev_priv) {
1115 DRM_ERROR("called with no initialization\n");
1116 return -EINVAL;
1117 }
1118
1119 overlay = dev_priv->overlay;
1120 if (!overlay) {
1121 DRM_DEBUG("userspace bug: no overlay\n");
1122 return -ENODEV;
1123 }
1124
1125 if (!(put_image_rec->flags & I915_OVERLAY_ENABLE)) {
1126 mutex_lock(&dev->mode_config.mutex);
1127 mutex_lock(&dev->struct_mutex);
1128
Chris Wilsonce453d82011-02-21 14:43:56 +00001129 ret = intel_overlay_switch_off(overlay);
Daniel Vetter02e792f2009-09-15 22:57:34 +02001130
1131 mutex_unlock(&dev->struct_mutex);
1132 mutex_unlock(&dev->mode_config.mutex);
1133
1134 return ret;
1135 }
1136
1137 params = kmalloc(sizeof(struct put_image_params), GFP_KERNEL);
1138 if (!params)
1139 return -ENOMEM;
1140
1141 drmmode_obj = drm_mode_object_find(dev, put_image_rec->crtc_id,
Chris Wilson722506f2010-08-12 09:28:50 +01001142 DRM_MODE_OBJECT_CRTC);
Dan Carpenter915a4282010-03-06 14:05:39 +03001143 if (!drmmode_obj) {
1144 ret = -ENOENT;
1145 goto out_free;
1146 }
Daniel Vetter02e792f2009-09-15 22:57:34 +02001147 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
1148
Chris Wilson05394f32010-11-08 19:18:58 +00001149 new_bo = to_intel_bo(drm_gem_object_lookup(dev, file_priv,
1150 put_image_rec->bo_handle));
Chris Wilsonc8725222011-02-19 11:31:06 +00001151 if (&new_bo->base == NULL) {
Dan Carpenter915a4282010-03-06 14:05:39 +03001152 ret = -ENOENT;
1153 goto out_free;
1154 }
Daniel Vetter02e792f2009-09-15 22:57:34 +02001155
1156 mutex_lock(&dev->mode_config.mutex);
1157 mutex_lock(&dev->struct_mutex);
1158
Chris Wilsond9e86c02010-11-10 16:40:20 +00001159 if (new_bo->tiling_mode) {
1160 DRM_ERROR("buffer used for overlay image can not be tiled\n");
1161 ret = -EINVAL;
1162 goto out_unlock;
1163 }
1164
Chris Wilsonce453d82011-02-21 14:43:56 +00001165 ret = intel_overlay_recover_from_interrupt(overlay);
Chris Wilsonb303cf92010-08-12 14:03:48 +01001166 if (ret != 0)
1167 goto out_unlock;
Daniel Vetter03f77ea2009-09-15 22:57:37 +02001168
Daniel Vetter02e792f2009-09-15 22:57:34 +02001169 if (overlay->crtc != crtc) {
1170 struct drm_display_mode *mode = &crtc->base.mode;
Chris Wilsonce453d82011-02-21 14:43:56 +00001171 ret = intel_overlay_switch_off(overlay);
Daniel Vetter02e792f2009-09-15 22:57:34 +02001172 if (ret != 0)
1173 goto out_unlock;
1174
1175 ret = check_overlay_possible_on_crtc(overlay, crtc);
1176 if (ret != 0)
1177 goto out_unlock;
1178
1179 overlay->crtc = crtc;
1180 crtc->overlay = overlay;
1181
Chris Wilsone9e331a2010-09-13 01:16:10 +01001182 /* line too wide, i.e. one-line-mode */
1183 if (mode->hdisplay > 1024 &&
1184 intel_panel_fitter_pipe(dev) == crtc->pipe) {
Daniel Vetter02e792f2009-09-15 22:57:34 +02001185 overlay->pfit_active = 1;
1186 update_pfit_vscale_ratio(overlay);
1187 } else
1188 overlay->pfit_active = 0;
1189 }
1190
1191 ret = check_overlay_dst(overlay, put_image_rec);
1192 if (ret != 0)
1193 goto out_unlock;
1194
1195 if (overlay->pfit_active) {
1196 params->dst_y = ((((u32)put_image_rec->dst_y) << 12) /
Chris Wilson722506f2010-08-12 09:28:50 +01001197 overlay->pfit_vscale_ratio);
Daniel Vetter02e792f2009-09-15 22:57:34 +02001198 /* shifting right rounds downwards, so add 1 */
1199 params->dst_h = ((((u32)put_image_rec->dst_height) << 12) /
Chris Wilson722506f2010-08-12 09:28:50 +01001200 overlay->pfit_vscale_ratio) + 1;
Daniel Vetter02e792f2009-09-15 22:57:34 +02001201 } else {
1202 params->dst_y = put_image_rec->dst_y;
1203 params->dst_h = put_image_rec->dst_height;
1204 }
1205 params->dst_x = put_image_rec->dst_x;
1206 params->dst_w = put_image_rec->dst_width;
1207
1208 params->src_w = put_image_rec->src_width;
1209 params->src_h = put_image_rec->src_height;
1210 params->src_scan_w = put_image_rec->src_scan_width;
1211 params->src_scan_h = put_image_rec->src_scan_height;
Chris Wilson722506f2010-08-12 09:28:50 +01001212 if (params->src_scan_h > params->src_h ||
1213 params->src_scan_w > params->src_w) {
Daniel Vetter02e792f2009-09-15 22:57:34 +02001214 ret = -EINVAL;
1215 goto out_unlock;
1216 }
1217
1218 ret = check_overlay_src(dev, put_image_rec, new_bo);
1219 if (ret != 0)
1220 goto out_unlock;
1221 params->format = put_image_rec->flags & ~I915_OVERLAY_FLAGS_MASK;
1222 params->stride_Y = put_image_rec->stride_Y;
1223 params->stride_UV = put_image_rec->stride_UV;
1224 params->offset_Y = put_image_rec->offset_Y;
1225 params->offset_U = put_image_rec->offset_U;
1226 params->offset_V = put_image_rec->offset_V;
1227
1228 /* Check scaling after src size to prevent a divide-by-zero. */
1229 ret = check_overlay_scaling(params);
1230 if (ret != 0)
1231 goto out_unlock;
1232
1233 ret = intel_overlay_do_put_image(overlay, new_bo, params);
1234 if (ret != 0)
1235 goto out_unlock;
1236
1237 mutex_unlock(&dev->struct_mutex);
1238 mutex_unlock(&dev->mode_config.mutex);
1239
1240 kfree(params);
1241
1242 return 0;
1243
1244out_unlock:
1245 mutex_unlock(&dev->struct_mutex);
1246 mutex_unlock(&dev->mode_config.mutex);
Chris Wilson05394f32010-11-08 19:18:58 +00001247 drm_gem_object_unreference_unlocked(&new_bo->base);
Dan Carpenter915a4282010-03-06 14:05:39 +03001248out_free:
Daniel Vetter02e792f2009-09-15 22:57:34 +02001249 kfree(params);
1250
1251 return ret;
1252}
1253
1254static void update_reg_attrs(struct intel_overlay *overlay,
1255 struct overlay_registers *regs)
1256{
1257 regs->OCLRC0 = (overlay->contrast << 18) | (overlay->brightness & 0xff);
1258 regs->OCLRC1 = overlay->saturation;
1259}
1260
1261static bool check_gamma_bounds(u32 gamma1, u32 gamma2)
1262{
1263 int i;
1264
1265 if (gamma1 & 0xff000000 || gamma2 & 0xff000000)
1266 return false;
1267
1268 for (i = 0; i < 3; i++) {
Chris Wilson722506f2010-08-12 09:28:50 +01001269 if (((gamma1 >> i*8) & 0xff) >= ((gamma2 >> i*8) & 0xff))
Daniel Vetter02e792f2009-09-15 22:57:34 +02001270 return false;
1271 }
1272
1273 return true;
1274}
1275
1276static bool check_gamma5_errata(u32 gamma5)
1277{
1278 int i;
1279
1280 for (i = 0; i < 3; i++) {
1281 if (((gamma5 >> i*8) & 0xff) == 0x80)
1282 return false;
1283 }
1284
1285 return true;
1286}
1287
1288static int check_gamma(struct drm_intel_overlay_attrs *attrs)
1289{
Chris Wilson722506f2010-08-12 09:28:50 +01001290 if (!check_gamma_bounds(0, attrs->gamma0) ||
1291 !check_gamma_bounds(attrs->gamma0, attrs->gamma1) ||
1292 !check_gamma_bounds(attrs->gamma1, attrs->gamma2) ||
1293 !check_gamma_bounds(attrs->gamma2, attrs->gamma3) ||
1294 !check_gamma_bounds(attrs->gamma3, attrs->gamma4) ||
1295 !check_gamma_bounds(attrs->gamma4, attrs->gamma5) ||
1296 !check_gamma_bounds(attrs->gamma5, 0x00ffffff))
Daniel Vetter02e792f2009-09-15 22:57:34 +02001297 return -EINVAL;
Chris Wilson722506f2010-08-12 09:28:50 +01001298
Daniel Vetter02e792f2009-09-15 22:57:34 +02001299 if (!check_gamma5_errata(attrs->gamma5))
1300 return -EINVAL;
Chris Wilson722506f2010-08-12 09:28:50 +01001301
Daniel Vetter02e792f2009-09-15 22:57:34 +02001302 return 0;
1303}
1304
1305int intel_overlay_attrs(struct drm_device *dev, void *data,
Akshay Joshi0206e352011-08-16 15:34:10 -04001306 struct drm_file *file_priv)
Daniel Vetter02e792f2009-09-15 22:57:34 +02001307{
1308 struct drm_intel_overlay_attrs *attrs = data;
Akshay Joshi0206e352011-08-16 15:34:10 -04001309 drm_i915_private_t *dev_priv = dev->dev_private;
Daniel Vetter02e792f2009-09-15 22:57:34 +02001310 struct intel_overlay *overlay;
1311 struct overlay_registers *regs;
1312 int ret;
1313
1314 if (!dev_priv) {
1315 DRM_ERROR("called with no initialization\n");
1316 return -EINVAL;
1317 }
1318
1319 overlay = dev_priv->overlay;
1320 if (!overlay) {
1321 DRM_DEBUG("userspace bug: no overlay\n");
1322 return -ENODEV;
1323 }
1324
1325 mutex_lock(&dev->mode_config.mutex);
1326 mutex_lock(&dev->struct_mutex);
1327
Chris Wilson60fc3322010-08-12 10:44:45 +01001328 ret = -EINVAL;
Daniel Vetter02e792f2009-09-15 22:57:34 +02001329 if (!(attrs->flags & I915_OVERLAY_UPDATE_ATTRS)) {
Chris Wilson60fc3322010-08-12 10:44:45 +01001330 attrs->color_key = overlay->color_key;
Daniel Vetter02e792f2009-09-15 22:57:34 +02001331 attrs->brightness = overlay->brightness;
Chris Wilson60fc3322010-08-12 10:44:45 +01001332 attrs->contrast = overlay->contrast;
Daniel Vetter02e792f2009-09-15 22:57:34 +02001333 attrs->saturation = overlay->saturation;
1334
Chris Wilsona6c45cf2010-09-17 00:32:17 +01001335 if (!IS_GEN2(dev)) {
Daniel Vetter02e792f2009-09-15 22:57:34 +02001336 attrs->gamma0 = I915_READ(OGAMC0);
1337 attrs->gamma1 = I915_READ(OGAMC1);
1338 attrs->gamma2 = I915_READ(OGAMC2);
1339 attrs->gamma3 = I915_READ(OGAMC3);
1340 attrs->gamma4 = I915_READ(OGAMC4);
1341 attrs->gamma5 = I915_READ(OGAMC5);
1342 }
Daniel Vetter02e792f2009-09-15 22:57:34 +02001343 } else {
Chris Wilson60fc3322010-08-12 10:44:45 +01001344 if (attrs->brightness < -128 || attrs->brightness > 127)
Daniel Vetter02e792f2009-09-15 22:57:34 +02001345 goto out_unlock;
Chris Wilson60fc3322010-08-12 10:44:45 +01001346 if (attrs->contrast > 255)
Daniel Vetter02e792f2009-09-15 22:57:34 +02001347 goto out_unlock;
Chris Wilson60fc3322010-08-12 10:44:45 +01001348 if (attrs->saturation > 1023)
Daniel Vetter02e792f2009-09-15 22:57:34 +02001349 goto out_unlock;
Daniel Vetter02e792f2009-09-15 22:57:34 +02001350
Chris Wilson60fc3322010-08-12 10:44:45 +01001351 overlay->color_key = attrs->color_key;
1352 overlay->brightness = attrs->brightness;
1353 overlay->contrast = attrs->contrast;
1354 overlay->saturation = attrs->saturation;
Daniel Vetter02e792f2009-09-15 22:57:34 +02001355
Chris Wilson8d74f652010-08-12 10:35:26 +01001356 regs = intel_overlay_map_regs(overlay);
Daniel Vetter02e792f2009-09-15 22:57:34 +02001357 if (!regs) {
1358 ret = -ENOMEM;
1359 goto out_unlock;
1360 }
1361
1362 update_reg_attrs(overlay, regs);
1363
Chris Wilson9bb2ff72010-08-12 12:02:11 +01001364 intel_overlay_unmap_regs(overlay, regs);
Daniel Vetter02e792f2009-09-15 22:57:34 +02001365
1366 if (attrs->flags & I915_OVERLAY_UPDATE_GAMMA) {
Chris Wilsona6c45cf2010-09-17 00:32:17 +01001367 if (IS_GEN2(dev))
Daniel Vetter02e792f2009-09-15 22:57:34 +02001368 goto out_unlock;
Daniel Vetter02e792f2009-09-15 22:57:34 +02001369
1370 if (overlay->active) {
1371 ret = -EBUSY;
1372 goto out_unlock;
1373 }
1374
1375 ret = check_gamma(attrs);
Chris Wilson60fc3322010-08-12 10:44:45 +01001376 if (ret)
Daniel Vetter02e792f2009-09-15 22:57:34 +02001377 goto out_unlock;
1378
1379 I915_WRITE(OGAMC0, attrs->gamma0);
1380 I915_WRITE(OGAMC1, attrs->gamma1);
1381 I915_WRITE(OGAMC2, attrs->gamma2);
1382 I915_WRITE(OGAMC3, attrs->gamma3);
1383 I915_WRITE(OGAMC4, attrs->gamma4);
1384 I915_WRITE(OGAMC5, attrs->gamma5);
1385 }
Daniel Vetter02e792f2009-09-15 22:57:34 +02001386 }
1387
Chris Wilson60fc3322010-08-12 10:44:45 +01001388 ret = 0;
Daniel Vetter02e792f2009-09-15 22:57:34 +02001389out_unlock:
1390 mutex_unlock(&dev->struct_mutex);
1391 mutex_unlock(&dev->mode_config.mutex);
1392
1393 return ret;
1394}
1395
1396void intel_setup_overlay(struct drm_device *dev)
1397{
Akshay Joshi0206e352011-08-16 15:34:10 -04001398 drm_i915_private_t *dev_priv = dev->dev_private;
Daniel Vetter02e792f2009-09-15 22:57:34 +02001399 struct intel_overlay *overlay;
Chris Wilson05394f32010-11-08 19:18:58 +00001400 struct drm_i915_gem_object *reg_bo;
Daniel Vetter02e792f2009-09-15 22:57:34 +02001401 struct overlay_registers *regs;
1402 int ret;
1403
Chris Wilson315781482010-08-12 09:42:51 +01001404 if (!HAS_OVERLAY(dev))
Daniel Vetter02e792f2009-09-15 22:57:34 +02001405 return;
1406
1407 overlay = kzalloc(sizeof(struct intel_overlay), GFP_KERNEL);
1408 if (!overlay)
1409 return;
Chris Wilson79d24272011-06-28 11:27:47 +01001410
1411 mutex_lock(&dev->struct_mutex);
1412 if (WARN_ON(dev_priv->overlay))
1413 goto out_free;
1414
Daniel Vetter02e792f2009-09-15 22:57:34 +02001415 overlay->dev = dev;
1416
Daniel Vetterac52bc52010-04-09 19:05:06 +00001417 reg_bo = i915_gem_alloc_object(dev, PAGE_SIZE);
Daniel Vetter02e792f2009-09-15 22:57:34 +02001418 if (!reg_bo)
1419 goto out_free;
Chris Wilson05394f32010-11-08 19:18:58 +00001420 overlay->reg_bo = reg_bo;
Daniel Vetter02e792f2009-09-15 22:57:34 +02001421
Chris Wilson315781482010-08-12 09:42:51 +01001422 if (OVERLAY_NEEDS_PHYSICAL(dev)) {
1423 ret = i915_gem_attach_phys_object(dev, reg_bo,
1424 I915_GEM_PHYS_OVERLAY_REGS,
Chris Wilsona2930122010-08-12 10:47:56 +01001425 PAGE_SIZE);
Akshay Joshi0206e352011-08-16 15:34:10 -04001426 if (ret) {
1427 DRM_ERROR("failed to attach phys overlay regs\n");
1428 goto out_free_bo;
1429 }
Chris Wilson05394f32010-11-08 19:18:58 +00001430 overlay->flip_addr = reg_bo->phys_obj->handle->busaddr;
Chris Wilson315781482010-08-12 09:42:51 +01001431 } else {
Daniel Vetter75e9e912010-11-04 17:11:09 +01001432 ret = i915_gem_object_pin(reg_bo, PAGE_SIZE, true);
Daniel Vetter02e792f2009-09-15 22:57:34 +02001433 if (ret) {
Akshay Joshi0206e352011-08-16 15:34:10 -04001434 DRM_ERROR("failed to pin overlay register bo\n");
1435 goto out_free_bo;
1436 }
Chris Wilson05394f32010-11-08 19:18:58 +00001437 overlay->flip_addr = reg_bo->gtt_offset;
Chris Wilson0ddc1282010-08-12 09:35:00 +01001438
1439 ret = i915_gem_object_set_to_gtt_domain(reg_bo, true);
1440 if (ret) {
Akshay Joshi0206e352011-08-16 15:34:10 -04001441 DRM_ERROR("failed to move overlay register bo into the GTT\n");
1442 goto out_unpin_bo;
1443 }
Daniel Vetter02e792f2009-09-15 22:57:34 +02001444 }
1445
1446 /* init all values */
1447 overlay->color_key = 0x0101fe;
1448 overlay->brightness = -19;
1449 overlay->contrast = 75;
1450 overlay->saturation = 146;
1451
Chris Wilson8d74f652010-08-12 10:35:26 +01001452 regs = intel_overlay_map_regs(overlay);
Daniel Vetter02e792f2009-09-15 22:57:34 +02001453 if (!regs)
Chris Wilson79d24272011-06-28 11:27:47 +01001454 goto out_unpin_bo;
Daniel Vetter02e792f2009-09-15 22:57:34 +02001455
1456 memset(regs, 0, sizeof(struct overlay_registers));
1457 update_polyphase_filter(regs);
Daniel Vetter02e792f2009-09-15 22:57:34 +02001458 update_reg_attrs(overlay, regs);
1459
Chris Wilson9bb2ff72010-08-12 12:02:11 +01001460 intel_overlay_unmap_regs(overlay, regs);
Daniel Vetter02e792f2009-09-15 22:57:34 +02001461
1462 dev_priv->overlay = overlay;
Chris Wilson79d24272011-06-28 11:27:47 +01001463 mutex_unlock(&dev->struct_mutex);
Daniel Vetter02e792f2009-09-15 22:57:34 +02001464 DRM_INFO("initialized overlay support\n");
1465 return;
1466
Chris Wilson0ddc1282010-08-12 09:35:00 +01001467out_unpin_bo:
Chris Wilson79d24272011-06-28 11:27:47 +01001468 if (!OVERLAY_NEEDS_PHYSICAL(dev))
1469 i915_gem_object_unpin(reg_bo);
Daniel Vetter02e792f2009-09-15 22:57:34 +02001470out_free_bo:
Chris Wilson05394f32010-11-08 19:18:58 +00001471 drm_gem_object_unreference(&reg_bo->base);
Daniel Vetter02e792f2009-09-15 22:57:34 +02001472out_free:
Chris Wilson79d24272011-06-28 11:27:47 +01001473 mutex_unlock(&dev->struct_mutex);
Daniel Vetter02e792f2009-09-15 22:57:34 +02001474 kfree(overlay);
1475 return;
1476}
1477
1478void intel_cleanup_overlay(struct drm_device *dev)
1479{
Chris Wilson722506f2010-08-12 09:28:50 +01001480 drm_i915_private_t *dev_priv = dev->dev_private;
Daniel Vetter02e792f2009-09-15 22:57:34 +02001481
Chris Wilson62cf4e62010-08-12 10:50:36 +01001482 if (!dev_priv->overlay)
1483 return;
Daniel Vetter02e792f2009-09-15 22:57:34 +02001484
Chris Wilson62cf4e62010-08-12 10:50:36 +01001485 /* The bo's should be free'd by the generic code already.
1486 * Furthermore modesetting teardown happens beforehand so the
1487 * hardware should be off already */
1488 BUG_ON(dev_priv->overlay->active);
1489
1490 drm_gem_object_unreference_unlocked(&dev_priv->overlay->reg_bo->base);
1491 kfree(dev_priv->overlay);
Daniel Vetter02e792f2009-09-15 22:57:34 +02001492}
Chris Wilson6ef3d422010-08-04 20:26:07 +01001493
Chris Wilson3bd3c932010-08-19 08:19:30 +01001494#ifdef CONFIG_DEBUG_FS
1495#include <linux/seq_file.h>
1496
Chris Wilson6ef3d422010-08-04 20:26:07 +01001497struct intel_overlay_error_state {
1498 struct overlay_registers regs;
1499 unsigned long base;
1500 u32 dovsta;
1501 u32 isr;
1502};
1503
Chris Wilson3bd3c932010-08-19 08:19:30 +01001504static struct overlay_registers *
Linus Torvaldsc48c43e2010-10-26 18:57:59 -07001505intel_overlay_map_regs_atomic(struct intel_overlay *overlay)
Chris Wilson3bd3c932010-08-19 08:19:30 +01001506{
Linus Torvaldsc48c43e2010-10-26 18:57:59 -07001507 drm_i915_private_t *dev_priv = overlay->dev->dev_private;
Chris Wilson3bd3c932010-08-19 08:19:30 +01001508 struct overlay_registers *regs;
1509
1510 if (OVERLAY_NEEDS_PHYSICAL(overlay->dev))
1511 regs = overlay->reg_bo->phys_obj->handle->vaddr;
1512 else
1513 regs = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
Linus Torvaldsc48c43e2010-10-26 18:57:59 -07001514 overlay->reg_bo->gtt_offset);
Chris Wilson3bd3c932010-08-19 08:19:30 +01001515
1516 return regs;
1517}
1518
1519static void intel_overlay_unmap_regs_atomic(struct intel_overlay *overlay,
Chris Wilson3bd3c932010-08-19 08:19:30 +01001520 struct overlay_registers *regs)
1521{
1522 if (!OVERLAY_NEEDS_PHYSICAL(overlay->dev))
Linus Torvaldsc48c43e2010-10-26 18:57:59 -07001523 io_mapping_unmap_atomic(regs);
Chris Wilson3bd3c932010-08-19 08:19:30 +01001524}
1525
1526
Chris Wilson6ef3d422010-08-04 20:26:07 +01001527struct intel_overlay_error_state *
1528intel_overlay_capture_error_state(struct drm_device *dev)
1529{
Akshay Joshi0206e352011-08-16 15:34:10 -04001530 drm_i915_private_t *dev_priv = dev->dev_private;
Chris Wilson6ef3d422010-08-04 20:26:07 +01001531 struct intel_overlay *overlay = dev_priv->overlay;
1532 struct intel_overlay_error_state *error;
1533 struct overlay_registers __iomem *regs;
1534
1535 if (!overlay || !overlay->active)
1536 return NULL;
1537
1538 error = kmalloc(sizeof(*error), GFP_ATOMIC);
1539 if (error == NULL)
1540 return NULL;
1541
1542 error->dovsta = I915_READ(DOVSTA);
1543 error->isr = I915_READ(ISR);
Chris Wilson315781482010-08-12 09:42:51 +01001544 if (OVERLAY_NEEDS_PHYSICAL(overlay->dev))
Chris Wilson6ef3d422010-08-04 20:26:07 +01001545 error->base = (long) overlay->reg_bo->phys_obj->handle->vaddr;
Chris Wilson315781482010-08-12 09:42:51 +01001546 else
1547 error->base = (long) overlay->reg_bo->gtt_offset;
Chris Wilson6ef3d422010-08-04 20:26:07 +01001548
1549 regs = intel_overlay_map_regs_atomic(overlay);
1550 if (!regs)
1551 goto err;
1552
1553 memcpy_fromio(&error->regs, regs, sizeof(struct overlay_registers));
Linus Torvaldsc48c43e2010-10-26 18:57:59 -07001554 intel_overlay_unmap_regs_atomic(overlay, regs);
Chris Wilson6ef3d422010-08-04 20:26:07 +01001555
1556 return error;
1557
1558err:
1559 kfree(error);
1560 return NULL;
1561}
1562
1563void
1564intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error)
1565{
1566 seq_printf(m, "Overlay, status: 0x%08x, interrupt: 0x%08x\n",
1567 error->dovsta, error->isr);
1568 seq_printf(m, " Register file at 0x%08lx:\n",
1569 error->base);
1570
1571#define P(x) seq_printf(m, " " #x ": 0x%08x\n", error->regs.x)
1572 P(OBUF_0Y);
1573 P(OBUF_1Y);
1574 P(OBUF_0U);
1575 P(OBUF_0V);
1576 P(OBUF_1U);
1577 P(OBUF_1V);
1578 P(OSTRIDE);
1579 P(YRGB_VPH);
1580 P(UV_VPH);
1581 P(HORZ_PH);
1582 P(INIT_PHS);
1583 P(DWINPOS);
1584 P(DWINSZ);
1585 P(SWIDTH);
1586 P(SWIDTHSW);
1587 P(SHEIGHT);
1588 P(YRGBSCALE);
1589 P(UVSCALE);
1590 P(OCLRC0);
1591 P(OCLRC1);
1592 P(DCLRKV);
1593 P(DCLRKM);
1594 P(SCLRKVH);
1595 P(SCLRKVL);
1596 P(SCLRKEN);
1597 P(OCONFIG);
1598 P(OCMD);
1599 P(OSTART_0Y);
1600 P(OSTART_1Y);
1601 P(OSTART_0U);
1602 P(OSTART_0V);
1603 P(OSTART_1U);
1604 P(OSTART_1V);
1605 P(OTILEOFF_0Y);
1606 P(OTILEOFF_1Y);
1607 P(OTILEOFF_0U);
1608 P(OTILEOFF_0V);
1609 P(OTILEOFF_1U);
1610 P(OTILEOFF_1V);
1611 P(FASTHSCALE);
1612 P(UVSCALEV);
1613#undef P
1614}
Chris Wilson3bd3c932010-08-19 08:19:30 +01001615#endif