blob: 12e92f2cc3a78067870f8d420c25ca2ec2834d28 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
2 */
Dave Airlie0d6aa602006-01-02 20:14:23 +11003/*
Linus Torvalds1da177e2005-04-16 15:20:36 -07004 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
Dave Airliebc54fd12005-06-23 22:46:46 +10006 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
Dave Airlie0d6aa602006-01-02 20:14:23 +110027 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070028
29#include "drmP.h"
30#include "drm.h"
Jesse Barnes79e53942008-11-07 14:24:08 -080031#include "drm_crtc_helper.h"
Dave Airlie785b93e2009-08-28 15:46:53 +100032#include "drm_fb_helper.h"
Jesse Barnes79e53942008-11-07 14:24:08 -080033#include "intel_drv.h"
Linus Torvalds1da177e2005-04-16 15:20:36 -070034#include "i915_drm.h"
35#include "i915_drv.h"
Chris Wilson1c5d22f2009-08-25 11:15:50 +010036#include "i915_trace.h"
Dave Airlie28d52042009-09-21 14:33:58 +100037#include <linux/vgaarb.h>
Zhenyu Wangc48044112009-12-17 14:48:43 +080038#include <linux/acpi.h>
39#include <linux/pnp.h>
Dave Airlie6a9ee8a2010-02-01 15:38:10 +100040#include <linux/vga_switcheroo.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090041#include <linux/slab.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070042
Keith Packard398c9cb2008-07-30 13:03:43 -070043/**
44 * Sets up the hardware status page for devices that need a physical address
45 * in the register.
46 */
Eric Anholt3043c602008-10-02 12:24:47 -070047static int i915_init_phys_hws(struct drm_device *dev)
Keith Packard398c9cb2008-07-30 13:03:43 -070048{
49 drm_i915_private_t *dev_priv = dev->dev_private;
50 /* Program Hardware Status Page */
51 dev_priv->status_page_dmah =
Zhenyu Wange6be8d92010-01-05 11:25:05 +080052 drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE);
Keith Packard398c9cb2008-07-30 13:03:43 -070053
54 if (!dev_priv->status_page_dmah) {
55 DRM_ERROR("Can not allocate hardware status page\n");
56 return -ENOMEM;
57 }
Zou Nan hai8187a2b2010-05-21 09:08:55 +080058 dev_priv->render_ring.status_page.page_addr
59 = dev_priv->status_page_dmah->vaddr;
Keith Packard398c9cb2008-07-30 13:03:43 -070060 dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
61
Zou Nan hai8187a2b2010-05-21 09:08:55 +080062 memset(dev_priv->render_ring.status_page.page_addr, 0, PAGE_SIZE);
Keith Packard398c9cb2008-07-30 13:03:43 -070063
Zhenyu Wang9b974cc2010-01-05 11:25:06 +080064 if (IS_I965G(dev))
65 dev_priv->dma_status_page |= (dev_priv->dma_status_page >> 28) &
66 0xf0;
67
Keith Packard398c9cb2008-07-30 13:03:43 -070068 I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
Zhao Yakui8a4c47f2009-07-20 13:48:04 +080069 DRM_DEBUG_DRIVER("Enabled hardware status page\n");
Keith Packard398c9cb2008-07-30 13:03:43 -070070 return 0;
71}
72
73/**
74 * Frees the hardware status page, whether it's a physical address or a virtual
75 * address set up by the X Server.
76 */
Eric Anholt3043c602008-10-02 12:24:47 -070077static void i915_free_hws(struct drm_device *dev)
Keith Packard398c9cb2008-07-30 13:03:43 -070078{
79 drm_i915_private_t *dev_priv = dev->dev_private;
80 if (dev_priv->status_page_dmah) {
81 drm_pci_free(dev, dev_priv->status_page_dmah);
82 dev_priv->status_page_dmah = NULL;
83 }
84
Zou Nan hai852835f2010-05-21 09:08:56 +080085 if (dev_priv->render_ring.status_page.gfx_addr) {
86 dev_priv->render_ring.status_page.gfx_addr = 0;
Keith Packard398c9cb2008-07-30 13:03:43 -070087 dev_priv->status_gfx_addr = 0;
88 drm_core_ioremapfree(&dev_priv->hws_map, dev);
89 }
90
91 /* Need to rewrite hardware status page */
92 I915_WRITE(HWS_PGA, 0x1ffff000);
93}
94
Dave Airlie84b1fd12007-07-11 15:53:27 +100095void i915_kernel_lost_context(struct drm_device * dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -070096{
97 drm_i915_private_t *dev_priv = dev->dev_private;
Dave Airlie7c1c2872008-11-28 14:22:24 +100098 struct drm_i915_master_private *master_priv;
Zou Nan hai8187a2b2010-05-21 09:08:55 +080099 struct intel_ring_buffer *ring = &dev_priv->render_ring;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700100
Jesse Barnes79e53942008-11-07 14:24:08 -0800101 /*
102 * We should never lose context on the ring with modesetting
103 * as we don't expose it to userspace
104 */
105 if (drm_core_check_feature(dev, DRIVER_MODESET))
106 return;
107
Jesse Barnes585fb112008-07-29 11:54:06 -0700108 ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
109 ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700110 ring->space = ring->head - (ring->tail + 8);
111 if (ring->space < 0)
Zou Nan hai8187a2b2010-05-21 09:08:55 +0800112 ring->space += ring->size;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700113
Dave Airlie7c1c2872008-11-28 14:22:24 +1000114 if (!dev->primary->master)
115 return;
116
117 master_priv = dev->primary->master->driver_priv;
118 if (ring->head == ring->tail && master_priv->sarea_priv)
119 master_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700120}
121
Dave Airlie84b1fd12007-07-11 15:53:27 +1000122static int i915_dma_cleanup(struct drm_device * dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700123{
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000124 drm_i915_private_t *dev_priv = dev->dev_private;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700125 /* Make sure interrupts are disabled here because the uninstall ioctl
126 * may not have been called from userspace and after dev_private
127 * is freed, it's too late.
128 */
Eric Anholted4cb412008-07-29 12:10:39 -0700129 if (dev->irq_enabled)
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000130 drm_irq_uninstall(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700131
Zou Nan hai8187a2b2010-05-21 09:08:55 +0800132 intel_cleanup_ring_buffer(dev, &dev_priv->render_ring);
Zou Nan haid1b851f2010-05-21 09:08:57 +0800133 if (HAS_BSD(dev))
134 intel_cleanup_ring_buffer(dev, &dev_priv->bsd_ring);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700135
Keith Packard398c9cb2008-07-30 13:03:43 -0700136 /* Clear the HWS virtual address at teardown */
137 if (I915_NEED_GFX_HWS(dev))
138 i915_free_hws(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700139
140 return 0;
141}
142
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000143static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700144{
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000145 drm_i915_private_t *dev_priv = dev->dev_private;
Dave Airlie7c1c2872008-11-28 14:22:24 +1000146 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700147
Dave Airlie3a03ac12009-01-11 09:03:49 +1000148 master_priv->sarea = drm_getsarea(dev);
149 if (master_priv->sarea) {
150 master_priv->sarea_priv = (drm_i915_sarea_t *)
151 ((u8 *)master_priv->sarea->handle + init->sarea_priv_offset);
152 } else {
Zhao Yakui8a4c47f2009-07-20 13:48:04 +0800153 DRM_DEBUG_DRIVER("sarea not found assuming DRI2 userspace\n");
Dave Airlie3a03ac12009-01-11 09:03:49 +1000154 }
155
Eric Anholt673a3942008-07-30 12:06:12 -0700156 if (init->ring_size != 0) {
Zou Nan hai8187a2b2010-05-21 09:08:55 +0800157 if (dev_priv->render_ring.gem_object != NULL) {
Eric Anholt673a3942008-07-30 12:06:12 -0700158 i915_dma_cleanup(dev);
159 DRM_ERROR("Client tried to initialize ringbuffer in "
160 "GEM mode\n");
161 return -EINVAL;
162 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700163
Zou Nan hai8187a2b2010-05-21 09:08:55 +0800164 dev_priv->render_ring.size = init->ring_size;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700165
Eric Anholtd3301d82010-05-21 13:55:54 -0700166 dev_priv->render_ring.map.offset = init->ring_start;
167 dev_priv->render_ring.map.size = init->ring_size;
168 dev_priv->render_ring.map.type = 0;
169 dev_priv->render_ring.map.flags = 0;
170 dev_priv->render_ring.map.mtrr = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700171
Eric Anholtd3301d82010-05-21 13:55:54 -0700172 drm_core_ioremap_wc(&dev_priv->render_ring.map, dev);
Eric Anholt673a3942008-07-30 12:06:12 -0700173
Eric Anholtd3301d82010-05-21 13:55:54 -0700174 if (dev_priv->render_ring.map.handle == NULL) {
Eric Anholt673a3942008-07-30 12:06:12 -0700175 i915_dma_cleanup(dev);
176 DRM_ERROR("can not ioremap virtual address for"
177 " ring buffer\n");
178 return -ENOMEM;
179 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700180 }
181
Eric Anholtd3301d82010-05-21 13:55:54 -0700182 dev_priv->render_ring.virtual_start = dev_priv->render_ring.map.handle;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700183
=?utf-8?q?Michel_D=C3=A4nzer?=a6b54f32006-10-24 23:37:43 +1000184 dev_priv->cpp = init->cpp;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700185 dev_priv->back_offset = init->back_offset;
186 dev_priv->front_offset = init->front_offset;
187 dev_priv->current_page = 0;
Dave Airlie7c1c2872008-11-28 14:22:24 +1000188 if (master_priv->sarea_priv)
189 master_priv->sarea_priv->pf_current_page = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700190
Linus Torvalds1da177e2005-04-16 15:20:36 -0700191 /* Allow hardware batchbuffers unless told otherwise.
192 */
193 dev_priv->allow_batchbuffer = 1;
194
Linus Torvalds1da177e2005-04-16 15:20:36 -0700195 return 0;
196}
197
Dave Airlie84b1fd12007-07-11 15:53:27 +1000198static int i915_dma_resume(struct drm_device * dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700199{
200 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
201
Zou Nan hai8187a2b2010-05-21 09:08:55 +0800202 struct intel_ring_buffer *ring;
Zhao Yakui8a4c47f2009-07-20 13:48:04 +0800203 DRM_DEBUG_DRIVER("%s\n", __func__);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700204
Zou Nan hai8187a2b2010-05-21 09:08:55 +0800205 ring = &dev_priv->render_ring;
206
207 if (ring->map.handle == NULL) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700208 DRM_ERROR("can not ioremap virtual address for"
209 " ring buffer\n");
Eric Anholt20caafa2007-08-25 19:22:43 +1000210 return -ENOMEM;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700211 }
212
213 /* Program Hardware Status Page */
Zou Nan hai8187a2b2010-05-21 09:08:55 +0800214 if (!ring->status_page.page_addr) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700215 DRM_ERROR("Can not find hardware status page\n");
Eric Anholt20caafa2007-08-25 19:22:43 +1000216 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700217 }
Zhao Yakui8a4c47f2009-07-20 13:48:04 +0800218 DRM_DEBUG_DRIVER("hw status page @ %p\n",
Zou Nan hai8187a2b2010-05-21 09:08:55 +0800219 ring->status_page.page_addr);
220 if (ring->status_page.gfx_addr != 0)
221 ring->setup_status_page(dev, ring);
Wang Zhenyudc7a9312007-06-10 15:58:19 +1000222 else
Jesse Barnes585fb112008-07-29 11:54:06 -0700223 I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
Zou Nan hai8187a2b2010-05-21 09:08:55 +0800224
Zhao Yakui8a4c47f2009-07-20 13:48:04 +0800225 DRM_DEBUG_DRIVER("Enabled hardware status page\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700226
227 return 0;
228}
229
Eric Anholtc153f452007-09-03 12:06:45 +1000230static int i915_dma_init(struct drm_device *dev, void *data,
231 struct drm_file *file_priv)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700232{
Eric Anholtc153f452007-09-03 12:06:45 +1000233 drm_i915_init_t *init = data;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700234 int retcode = 0;
235
Eric Anholtc153f452007-09-03 12:06:45 +1000236 switch (init->func) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700237 case I915_INIT_DMA:
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000238 retcode = i915_initialize(dev, init);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700239 break;
240 case I915_CLEANUP_DMA:
241 retcode = i915_dma_cleanup(dev);
242 break;
243 case I915_RESUME_DMA:
Dave Airlie0d6aa602006-01-02 20:14:23 +1100244 retcode = i915_dma_resume(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700245 break;
246 default:
Eric Anholt20caafa2007-08-25 19:22:43 +1000247 retcode = -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700248 break;
249 }
250
251 return retcode;
252}
253
254/* Implement basically the same security restrictions as hardware does
255 * for MI_BATCH_NON_SECURE. These can be made stricter at any time.
256 *
257 * Most of the calculations below involve calculating the size of a
258 * particular instruction. It's important to get the size right as
259 * that tells us where the next instruction to check is. Any illegal
260 * instruction detected will be given a size of zero, which is a
261 * signal to abort the rest of the buffer.
262 */
263static int do_validate_cmd(int cmd)
264{
265 switch (((cmd >> 29) & 0x7)) {
266 case 0x0:
267 switch ((cmd >> 23) & 0x3f) {
268 case 0x0:
269 return 1; /* MI_NOOP */
270 case 0x4:
271 return 1; /* MI_FLUSH */
272 default:
273 return 0; /* disallow everything else */
274 }
275 break;
276 case 0x1:
277 return 0; /* reserved */
278 case 0x2:
279 return (cmd & 0xff) + 2; /* 2d commands */
280 case 0x3:
281 if (((cmd >> 24) & 0x1f) <= 0x18)
282 return 1;
283
284 switch ((cmd >> 24) & 0x1f) {
285 case 0x1c:
286 return 1;
287 case 0x1d:
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000288 switch ((cmd >> 16) & 0xff) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700289 case 0x3:
290 return (cmd & 0x1f) + 2;
291 case 0x4:
292 return (cmd & 0xf) + 2;
293 default:
294 return (cmd & 0xffff) + 2;
295 }
296 case 0x1e:
297 if (cmd & (1 << 23))
298 return (cmd & 0xffff) + 1;
299 else
300 return 1;
301 case 0x1f:
302 if ((cmd & (1 << 23)) == 0) /* inline vertices */
303 return (cmd & 0x1ffff) + 2;
304 else if (cmd & (1 << 17)) /* indirect random */
305 if ((cmd & 0xffff) == 0)
306 return 0; /* unknown length, too hard */
307 else
308 return (((cmd & 0xffff) + 1) / 2) + 1;
309 else
310 return 2; /* indirect sequential */
311 default:
312 return 0;
313 }
314 default:
315 return 0;
316 }
317
318 return 0;
319}
320
321static int validate_cmd(int cmd)
322{
323 int ret = do_validate_cmd(cmd);
324
Dave Airliebc5f4522007-11-05 12:50:58 +1000325/* printk("validate_cmd( %x ): %d\n", cmd, ret); */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700326
327 return ret;
328}
329
Eric Anholt201361a2009-03-11 12:30:04 -0700330static int i915_emit_cmds(struct drm_device * dev, int *buffer, int dwords)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700331{
332 drm_i915_private_t *dev_priv = dev->dev_private;
333 int i;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700334
Zou Nan hai8187a2b2010-05-21 09:08:55 +0800335 if ((dwords+1) * sizeof(int) >= dev_priv->render_ring.size - 8)
Eric Anholt20caafa2007-08-25 19:22:43 +1000336 return -EINVAL;
Dave Airliede227f52006-01-25 15:31:43 +1100337
Alan Hourihanec29b6692006-08-12 16:29:24 +1000338 BEGIN_LP_RING((dwords+1)&~1);
Dave Airliede227f52006-01-25 15:31:43 +1100339
Linus Torvalds1da177e2005-04-16 15:20:36 -0700340 for (i = 0; i < dwords;) {
341 int cmd, sz;
342
Eric Anholt201361a2009-03-11 12:30:04 -0700343 cmd = buffer[i];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700344
Linus Torvalds1da177e2005-04-16 15:20:36 -0700345 if ((sz = validate_cmd(cmd)) == 0 || i + sz > dwords)
Eric Anholt20caafa2007-08-25 19:22:43 +1000346 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700347
Linus Torvalds1da177e2005-04-16 15:20:36 -0700348 OUT_RING(cmd);
349
350 while (++i, --sz) {
Eric Anholt201361a2009-03-11 12:30:04 -0700351 OUT_RING(buffer[i]);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700352 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700353 }
354
Dave Airliede227f52006-01-25 15:31:43 +1100355 if (dwords & 1)
356 OUT_RING(0);
357
358 ADVANCE_LP_RING();
359
Linus Torvalds1da177e2005-04-16 15:20:36 -0700360 return 0;
361}
362
Eric Anholt673a3942008-07-30 12:06:12 -0700363int
364i915_emit_box(struct drm_device *dev,
Eric Anholt201361a2009-03-11 12:30:04 -0700365 struct drm_clip_rect *boxes,
Eric Anholt673a3942008-07-30 12:06:12 -0700366 int i, int DR1, int DR4)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700367{
Eric Anholt201361a2009-03-11 12:30:04 -0700368 struct drm_clip_rect box = boxes[i];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700369
Linus Torvalds1da177e2005-04-16 15:20:36 -0700370 if (box.y2 <= box.y1 || box.x2 <= box.x1 || box.y2 <= 0 || box.x2 <= 0) {
371 DRM_ERROR("Bad box %d,%d..%d,%d\n",
372 box.x1, box.y1, box.x2, box.y2);
Eric Anholt20caafa2007-08-25 19:22:43 +1000373 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700374 }
375
Alan Hourihanec29b6692006-08-12 16:29:24 +1000376 if (IS_I965G(dev)) {
377 BEGIN_LP_RING(4);
378 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
379 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
Andrew Morton78eca432006-08-16 09:15:51 +1000380 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
Alan Hourihanec29b6692006-08-12 16:29:24 +1000381 OUT_RING(DR4);
382 ADVANCE_LP_RING();
383 } else {
384 BEGIN_LP_RING(6);
385 OUT_RING(GFX_OP_DRAWRECT_INFO);
386 OUT_RING(DR1);
387 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
388 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
389 OUT_RING(DR4);
390 OUT_RING(0);
391 ADVANCE_LP_RING();
392 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700393
394 return 0;
395}
396
Alan Hourihanec29b6692006-08-12 16:29:24 +1000397/* XXX: Emitting the counter should really be moved to part of the IRQ
398 * emit. For now, do it in both places:
399 */
400
Dave Airlie84b1fd12007-07-11 15:53:27 +1000401static void i915_emit_breadcrumb(struct drm_device *dev)
Dave Airliede227f52006-01-25 15:31:43 +1100402{
403 drm_i915_private_t *dev_priv = dev->dev_private;
Dave Airlie7c1c2872008-11-28 14:22:24 +1000404 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
Dave Airliede227f52006-01-25 15:31:43 +1100405
Kristian Høgsbergc99b0582008-08-20 11:20:13 -0400406 dev_priv->counter++;
Dave Airlieaf6061a2008-05-07 12:15:39 +1000407 if (dev_priv->counter > 0x7FFFFFFFUL)
Kristian Høgsbergc99b0582008-08-20 11:20:13 -0400408 dev_priv->counter = 0;
Dave Airlie7c1c2872008-11-28 14:22:24 +1000409 if (master_priv->sarea_priv)
410 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
Dave Airliede227f52006-01-25 15:31:43 +1100411
412 BEGIN_LP_RING(4);
Jesse Barnes585fb112008-07-29 11:54:06 -0700413 OUT_RING(MI_STORE_DWORD_INDEX);
Keith Packard0baf8232008-11-08 11:44:14 +1000414 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
Dave Airliede227f52006-01-25 15:31:43 +1100415 OUT_RING(dev_priv->counter);
416 OUT_RING(0);
417 ADVANCE_LP_RING();
418}
419
Dave Airlie84b1fd12007-07-11 15:53:27 +1000420static int i915_dispatch_cmdbuffer(struct drm_device * dev,
Eric Anholt201361a2009-03-11 12:30:04 -0700421 drm_i915_cmdbuffer_t *cmd,
422 struct drm_clip_rect *cliprects,
423 void *cmdbuf)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700424{
425 int nbox = cmd->num_cliprects;
426 int i = 0, count, ret;
427
428 if (cmd->sz & 0x3) {
429 DRM_ERROR("alignment");
Eric Anholt20caafa2007-08-25 19:22:43 +1000430 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700431 }
432
433 i915_kernel_lost_context(dev);
434
435 count = nbox ? nbox : 1;
436
437 for (i = 0; i < count; i++) {
438 if (i < nbox) {
Eric Anholt201361a2009-03-11 12:30:04 -0700439 ret = i915_emit_box(dev, cliprects, i,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700440 cmd->DR1, cmd->DR4);
441 if (ret)
442 return ret;
443 }
444
Eric Anholt201361a2009-03-11 12:30:04 -0700445 ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700446 if (ret)
447 return ret;
448 }
449
Dave Airliede227f52006-01-25 15:31:43 +1100450 i915_emit_breadcrumb(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700451 return 0;
452}
453
Dave Airlie84b1fd12007-07-11 15:53:27 +1000454static int i915_dispatch_batchbuffer(struct drm_device * dev,
Eric Anholt201361a2009-03-11 12:30:04 -0700455 drm_i915_batchbuffer_t * batch,
456 struct drm_clip_rect *cliprects)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700457{
Linus Torvalds1da177e2005-04-16 15:20:36 -0700458 int nbox = batch->num_cliprects;
459 int i = 0, count;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700460
461 if ((batch->start | batch->used) & 0x7) {
462 DRM_ERROR("alignment");
Eric Anholt20caafa2007-08-25 19:22:43 +1000463 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700464 }
465
466 i915_kernel_lost_context(dev);
467
468 count = nbox ? nbox : 1;
469
470 for (i = 0; i < count; i++) {
471 if (i < nbox) {
Eric Anholt201361a2009-03-11 12:30:04 -0700472 int ret = i915_emit_box(dev, cliprects, i,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700473 batch->DR1, batch->DR4);
474 if (ret)
475 return ret;
476 }
477
Keith Packard0790d5e2008-07-30 12:28:47 -0700478 if (!IS_I830(dev) && !IS_845G(dev)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700479 BEGIN_LP_RING(2);
Dave Airlie21f16282007-08-07 09:09:51 +1000480 if (IS_I965G(dev)) {
481 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
482 OUT_RING(batch->start);
483 } else {
484 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
485 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
486 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700487 ADVANCE_LP_RING();
488 } else {
489 BEGIN_LP_RING(4);
490 OUT_RING(MI_BATCH_BUFFER);
491 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
492 OUT_RING(batch->start + batch->used - 4);
493 OUT_RING(0);
494 ADVANCE_LP_RING();
495 }
496 }
497
Dave Airliede227f52006-01-25 15:31:43 +1100498 i915_emit_breadcrumb(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700499
500 return 0;
501}
502
Dave Airlieaf6061a2008-05-07 12:15:39 +1000503static int i915_dispatch_flip(struct drm_device * dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700504{
505 drm_i915_private_t *dev_priv = dev->dev_private;
Dave Airlie7c1c2872008-11-28 14:22:24 +1000506 struct drm_i915_master_private *master_priv =
507 dev->primary->master->driver_priv;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700508
Dave Airlie7c1c2872008-11-28 14:22:24 +1000509 if (!master_priv->sarea_priv)
Kristian Høgsbergc99b0582008-08-20 11:20:13 -0400510 return -EINVAL;
511
Zhao Yakui8a4c47f2009-07-20 13:48:04 +0800512 DRM_DEBUG_DRIVER("%s: page=%d pfCurrentPage=%d\n",
yakui_zhaobe25ed92009-06-02 14:13:55 +0800513 __func__,
514 dev_priv->current_page,
515 master_priv->sarea_priv->pf_current_page);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700516
Dave Airlieaf6061a2008-05-07 12:15:39 +1000517 i915_kernel_lost_context(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700518
Dave Airlieaf6061a2008-05-07 12:15:39 +1000519 BEGIN_LP_RING(2);
Jesse Barnes585fb112008-07-29 11:54:06 -0700520 OUT_RING(MI_FLUSH | MI_READ_FLUSH);
Dave Airlieaf6061a2008-05-07 12:15:39 +1000521 OUT_RING(0);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700522 ADVANCE_LP_RING();
523
Dave Airlieaf6061a2008-05-07 12:15:39 +1000524 BEGIN_LP_RING(6);
525 OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
526 OUT_RING(0);
527 if (dev_priv->current_page == 0) {
528 OUT_RING(dev_priv->back_offset);
529 dev_priv->current_page = 1;
530 } else {
531 OUT_RING(dev_priv->front_offset);
532 dev_priv->current_page = 0;
533 }
534 OUT_RING(0);
535 ADVANCE_LP_RING();
Jesse Barnesac741ab2008-04-22 16:03:07 +1000536
Dave Airlieaf6061a2008-05-07 12:15:39 +1000537 BEGIN_LP_RING(2);
538 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
539 OUT_RING(0);
540 ADVANCE_LP_RING();
Jesse Barnesac741ab2008-04-22 16:03:07 +1000541
Dave Airlie7c1c2872008-11-28 14:22:24 +1000542 master_priv->sarea_priv->last_enqueue = dev_priv->counter++;
Jesse Barnesac741ab2008-04-22 16:03:07 +1000543
Dave Airlieaf6061a2008-05-07 12:15:39 +1000544 BEGIN_LP_RING(4);
Jesse Barnes585fb112008-07-29 11:54:06 -0700545 OUT_RING(MI_STORE_DWORD_INDEX);
Keith Packard0baf8232008-11-08 11:44:14 +1000546 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
Dave Airlieaf6061a2008-05-07 12:15:39 +1000547 OUT_RING(dev_priv->counter);
548 OUT_RING(0);
549 ADVANCE_LP_RING();
Jesse Barnesac741ab2008-04-22 16:03:07 +1000550
Dave Airlie7c1c2872008-11-28 14:22:24 +1000551 master_priv->sarea_priv->pf_current_page = dev_priv->current_page;
Dave Airlieaf6061a2008-05-07 12:15:39 +1000552 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700553}
554
Dave Airlie84b1fd12007-07-11 15:53:27 +1000555static int i915_quiescent(struct drm_device * dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700556{
557 drm_i915_private_t *dev_priv = dev->dev_private;
558
559 i915_kernel_lost_context(dev);
Zou Nan hai8187a2b2010-05-21 09:08:55 +0800560 return intel_wait_ring_buffer(dev, &dev_priv->render_ring,
561 dev_priv->render_ring.size - 8);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700562}
563
Eric Anholtc153f452007-09-03 12:06:45 +1000564static int i915_flush_ioctl(struct drm_device *dev, void *data,
565 struct drm_file *file_priv)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700566{
Eric Anholt546b0972008-09-01 16:45:29 -0700567 int ret;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700568
Eric Anholt546b0972008-09-01 16:45:29 -0700569 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
570
571 mutex_lock(&dev->struct_mutex);
572 ret = i915_quiescent(dev);
573 mutex_unlock(&dev->struct_mutex);
574
575 return ret;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700576}
577
Eric Anholtc153f452007-09-03 12:06:45 +1000578static int i915_batchbuffer(struct drm_device *dev, void *data,
579 struct drm_file *file_priv)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700580{
Linus Torvalds1da177e2005-04-16 15:20:36 -0700581 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
Dave Airlie7c1c2872008-11-28 14:22:24 +1000582 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700583 drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
Dave Airlie7c1c2872008-11-28 14:22:24 +1000584 master_priv->sarea_priv;
Eric Anholtc153f452007-09-03 12:06:45 +1000585 drm_i915_batchbuffer_t *batch = data;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700586 int ret;
Eric Anholt201361a2009-03-11 12:30:04 -0700587 struct drm_clip_rect *cliprects = NULL;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700588
589 if (!dev_priv->allow_batchbuffer) {
590 DRM_ERROR("Batchbuffer ioctl disabled\n");
Eric Anholt20caafa2007-08-25 19:22:43 +1000591 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700592 }
593
Zhao Yakui8a4c47f2009-07-20 13:48:04 +0800594 DRM_DEBUG_DRIVER("i915 batchbuffer, start %x used %d cliprects %d\n",
yakui_zhaobe25ed92009-06-02 14:13:55 +0800595 batch->start, batch->used, batch->num_cliprects);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700596
Eric Anholt546b0972008-09-01 16:45:29 -0700597 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700598
Eric Anholt201361a2009-03-11 12:30:04 -0700599 if (batch->num_cliprects < 0)
600 return -EINVAL;
601
602 if (batch->num_cliprects) {
Eric Anholt9a298b22009-03-24 12:23:04 -0700603 cliprects = kcalloc(batch->num_cliprects,
604 sizeof(struct drm_clip_rect),
605 GFP_KERNEL);
Eric Anholt201361a2009-03-11 12:30:04 -0700606 if (cliprects == NULL)
607 return -ENOMEM;
608
609 ret = copy_from_user(cliprects, batch->cliprects,
610 batch->num_cliprects *
611 sizeof(struct drm_clip_rect));
612 if (ret != 0)
613 goto fail_free;
614 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700615
Eric Anholt546b0972008-09-01 16:45:29 -0700616 mutex_lock(&dev->struct_mutex);
Eric Anholt201361a2009-03-11 12:30:04 -0700617 ret = i915_dispatch_batchbuffer(dev, batch, cliprects);
Eric Anholt546b0972008-09-01 16:45:29 -0700618 mutex_unlock(&dev->struct_mutex);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700619
Kristian Høgsbergc99b0582008-08-20 11:20:13 -0400620 if (sarea_priv)
Keith Packard0baf8232008-11-08 11:44:14 +1000621 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
Eric Anholt201361a2009-03-11 12:30:04 -0700622
623fail_free:
Eric Anholt9a298b22009-03-24 12:23:04 -0700624 kfree(cliprects);
Eric Anholt201361a2009-03-11 12:30:04 -0700625
Linus Torvalds1da177e2005-04-16 15:20:36 -0700626 return ret;
627}
628
Eric Anholtc153f452007-09-03 12:06:45 +1000629static int i915_cmdbuffer(struct drm_device *dev, void *data,
630 struct drm_file *file_priv)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700631{
Linus Torvalds1da177e2005-04-16 15:20:36 -0700632 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
Dave Airlie7c1c2872008-11-28 14:22:24 +1000633 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700634 drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
Dave Airlie7c1c2872008-11-28 14:22:24 +1000635 master_priv->sarea_priv;
Eric Anholtc153f452007-09-03 12:06:45 +1000636 drm_i915_cmdbuffer_t *cmdbuf = data;
Eric Anholt201361a2009-03-11 12:30:04 -0700637 struct drm_clip_rect *cliprects = NULL;
638 void *batch_data;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700639 int ret;
640
Zhao Yakui8a4c47f2009-07-20 13:48:04 +0800641 DRM_DEBUG_DRIVER("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
yakui_zhaobe25ed92009-06-02 14:13:55 +0800642 cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700643
Eric Anholt546b0972008-09-01 16:45:29 -0700644 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700645
Eric Anholt201361a2009-03-11 12:30:04 -0700646 if (cmdbuf->num_cliprects < 0)
647 return -EINVAL;
648
Eric Anholt9a298b22009-03-24 12:23:04 -0700649 batch_data = kmalloc(cmdbuf->sz, GFP_KERNEL);
Eric Anholt201361a2009-03-11 12:30:04 -0700650 if (batch_data == NULL)
651 return -ENOMEM;
652
653 ret = copy_from_user(batch_data, cmdbuf->buf, cmdbuf->sz);
654 if (ret != 0)
655 goto fail_batch_free;
656
657 if (cmdbuf->num_cliprects) {
Eric Anholt9a298b22009-03-24 12:23:04 -0700658 cliprects = kcalloc(cmdbuf->num_cliprects,
659 sizeof(struct drm_clip_rect), GFP_KERNEL);
Owain Ainswortha40e8d32010-02-09 14:25:55 +0000660 if (cliprects == NULL) {
661 ret = -ENOMEM;
Eric Anholt201361a2009-03-11 12:30:04 -0700662 goto fail_batch_free;
Owain Ainswortha40e8d32010-02-09 14:25:55 +0000663 }
Eric Anholt201361a2009-03-11 12:30:04 -0700664
665 ret = copy_from_user(cliprects, cmdbuf->cliprects,
666 cmdbuf->num_cliprects *
667 sizeof(struct drm_clip_rect));
668 if (ret != 0)
669 goto fail_clip_free;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700670 }
671
Eric Anholt546b0972008-09-01 16:45:29 -0700672 mutex_lock(&dev->struct_mutex);
Eric Anholt201361a2009-03-11 12:30:04 -0700673 ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data);
Eric Anholt546b0972008-09-01 16:45:29 -0700674 mutex_unlock(&dev->struct_mutex);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700675 if (ret) {
676 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
Chris Wright355d7f32009-04-17 01:18:55 +0000677 goto fail_clip_free;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700678 }
679
Kristian Høgsbergc99b0582008-08-20 11:20:13 -0400680 if (sarea_priv)
Keith Packard0baf8232008-11-08 11:44:14 +1000681 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
Eric Anholt201361a2009-03-11 12:30:04 -0700682
Eric Anholt201361a2009-03-11 12:30:04 -0700683fail_clip_free:
Eric Anholt9a298b22009-03-24 12:23:04 -0700684 kfree(cliprects);
Chris Wright355d7f32009-04-17 01:18:55 +0000685fail_batch_free:
Eric Anholt9a298b22009-03-24 12:23:04 -0700686 kfree(batch_data);
Eric Anholt201361a2009-03-11 12:30:04 -0700687
688 return ret;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700689}
690
Eric Anholtc153f452007-09-03 12:06:45 +1000691static int i915_flip_bufs(struct drm_device *dev, void *data,
692 struct drm_file *file_priv)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700693{
Eric Anholt546b0972008-09-01 16:45:29 -0700694 int ret;
695
Zhao Yakui8a4c47f2009-07-20 13:48:04 +0800696 DRM_DEBUG_DRIVER("%s\n", __func__);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700697
Eric Anholt546b0972008-09-01 16:45:29 -0700698 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700699
Eric Anholt546b0972008-09-01 16:45:29 -0700700 mutex_lock(&dev->struct_mutex);
701 ret = i915_dispatch_flip(dev);
702 mutex_unlock(&dev->struct_mutex);
703
704 return ret;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700705}
706
Eric Anholtc153f452007-09-03 12:06:45 +1000707static int i915_getparam(struct drm_device *dev, void *data,
708 struct drm_file *file_priv)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700709{
Linus Torvalds1da177e2005-04-16 15:20:36 -0700710 drm_i915_private_t *dev_priv = dev->dev_private;
Eric Anholtc153f452007-09-03 12:06:45 +1000711 drm_i915_getparam_t *param = data;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700712 int value;
713
714 if (!dev_priv) {
Márton Németh3e684ea2008-01-24 15:58:57 +1000715 DRM_ERROR("called with no initialization\n");
Eric Anholt20caafa2007-08-25 19:22:43 +1000716 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700717 }
718
Eric Anholtc153f452007-09-03 12:06:45 +1000719 switch (param->param) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700720 case I915_PARAM_IRQ_ACTIVE:
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700721 value = dev->pdev->irq ? 1 : 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700722 break;
723 case I915_PARAM_ALLOW_BATCHBUFFER:
724 value = dev_priv->allow_batchbuffer ? 1 : 0;
725 break;
Dave Airlie0d6aa602006-01-02 20:14:23 +1100726 case I915_PARAM_LAST_DISPATCH:
727 value = READ_BREADCRUMB(dev_priv);
728 break;
Kristian Høgsberged4c9c42008-08-20 11:08:52 -0400729 case I915_PARAM_CHIPSET_ID:
730 value = dev->pci_device;
731 break;
Eric Anholt673a3942008-07-30 12:06:12 -0700732 case I915_PARAM_HAS_GEM:
Dave Airlieac5c4e72008-12-19 15:38:34 +1000733 value = dev_priv->has_gem;
Eric Anholt673a3942008-07-30 12:06:12 -0700734 break;
Jesse Barnes0f973f22009-01-26 17:10:45 -0800735 case I915_PARAM_NUM_FENCES_AVAIL:
736 value = dev_priv->num_fence_regs - dev_priv->fence_reg_start;
737 break;
Daniel Vetter02e792f2009-09-15 22:57:34 +0200738 case I915_PARAM_HAS_OVERLAY:
739 value = dev_priv->overlay ? 1 : 0;
740 break;
Jesse Barnese9560f72009-11-19 10:49:07 -0800741 case I915_PARAM_HAS_PAGEFLIPPING:
742 value = 1;
743 break;
Jesse Barnes76446ca2009-12-17 22:05:42 -0500744 case I915_PARAM_HAS_EXECBUF2:
745 /* depends on GEM */
746 value = dev_priv->has_gem;
747 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700748 default:
Zhao Yakui8a4c47f2009-07-20 13:48:04 +0800749 DRM_DEBUG_DRIVER("Unknown parameter %d\n",
Jesse Barnes76446ca2009-12-17 22:05:42 -0500750 param->param);
Eric Anholt20caafa2007-08-25 19:22:43 +1000751 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700752 }
753
Eric Anholtc153f452007-09-03 12:06:45 +1000754 if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700755 DRM_ERROR("DRM_COPY_TO_USER failed\n");
Eric Anholt20caafa2007-08-25 19:22:43 +1000756 return -EFAULT;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700757 }
758
759 return 0;
760}
761
Eric Anholtc153f452007-09-03 12:06:45 +1000762static int i915_setparam(struct drm_device *dev, void *data,
763 struct drm_file *file_priv)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700764{
Linus Torvalds1da177e2005-04-16 15:20:36 -0700765 drm_i915_private_t *dev_priv = dev->dev_private;
Eric Anholtc153f452007-09-03 12:06:45 +1000766 drm_i915_setparam_t *param = data;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700767
768 if (!dev_priv) {
Márton Németh3e684ea2008-01-24 15:58:57 +1000769 DRM_ERROR("called with no initialization\n");
Eric Anholt20caafa2007-08-25 19:22:43 +1000770 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700771 }
772
Eric Anholtc153f452007-09-03 12:06:45 +1000773 switch (param->param) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700774 case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700775 break;
776 case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
Eric Anholtc153f452007-09-03 12:06:45 +1000777 dev_priv->tex_lru_log_granularity = param->value;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700778 break;
779 case I915_SETPARAM_ALLOW_BATCHBUFFER:
Eric Anholtc153f452007-09-03 12:06:45 +1000780 dev_priv->allow_batchbuffer = param->value;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700781 break;
Jesse Barnes0f973f22009-01-26 17:10:45 -0800782 case I915_SETPARAM_NUM_USED_FENCES:
783 if (param->value > dev_priv->num_fence_regs ||
784 param->value < 0)
785 return -EINVAL;
786 /* Userspace can use first N regs */
787 dev_priv->fence_reg_start = param->value;
788 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700789 default:
Zhao Yakui8a4c47f2009-07-20 13:48:04 +0800790 DRM_DEBUG_DRIVER("unknown parameter %d\n",
yakui_zhaobe25ed92009-06-02 14:13:55 +0800791 param->param);
Eric Anholt20caafa2007-08-25 19:22:43 +1000792 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700793 }
794
795 return 0;
796}
797
Eric Anholtc153f452007-09-03 12:06:45 +1000798static int i915_set_status_page(struct drm_device *dev, void *data,
799 struct drm_file *file_priv)
Wang Zhenyudc7a9312007-06-10 15:58:19 +1000800{
Wang Zhenyudc7a9312007-06-10 15:58:19 +1000801 drm_i915_private_t *dev_priv = dev->dev_private;
Eric Anholtc153f452007-09-03 12:06:45 +1000802 drm_i915_hws_addr_t *hws = data;
Zou Nan hai8187a2b2010-05-21 09:08:55 +0800803 struct intel_ring_buffer *ring = &dev_priv->render_ring;
Wang Zhenyudc7a9312007-06-10 15:58:19 +1000804
Zhenyu Wangb39d50e2008-02-19 20:59:09 +1000805 if (!I915_NEED_GFX_HWS(dev))
806 return -EINVAL;
807
Wang Zhenyudc7a9312007-06-10 15:58:19 +1000808 if (!dev_priv) {
Márton Németh3e684ea2008-01-24 15:58:57 +1000809 DRM_ERROR("called with no initialization\n");
Eric Anholt20caafa2007-08-25 19:22:43 +1000810 return -EINVAL;
Wang Zhenyudc7a9312007-06-10 15:58:19 +1000811 }
Wang Zhenyudc7a9312007-06-10 15:58:19 +1000812
Jesse Barnes79e53942008-11-07 14:24:08 -0800813 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
814 WARN(1, "tried to set status page when mode setting active\n");
815 return 0;
816 }
817
Zhao Yakui8a4c47f2009-07-20 13:48:04 +0800818 DRM_DEBUG_DRIVER("set status page addr 0x%08x\n", (u32)hws->addr);
Wang Zhenyudc7a9312007-06-10 15:58:19 +1000819
Zou Nan hai8187a2b2010-05-21 09:08:55 +0800820 ring->status_page.gfx_addr = hws->addr & (0x1ffff<<12);
Eric Anholtc153f452007-09-03 12:06:45 +1000821
Eric Anholt8b409582007-11-22 16:40:37 +1000822 dev_priv->hws_map.offset = dev->agp->base + hws->addr;
Wang Zhenyudc7a9312007-06-10 15:58:19 +1000823 dev_priv->hws_map.size = 4*1024;
824 dev_priv->hws_map.type = 0;
825 dev_priv->hws_map.flags = 0;
826 dev_priv->hws_map.mtrr = 0;
827
Dave Airliedd0910b2009-02-25 14:49:21 +1000828 drm_core_ioremap_wc(&dev_priv->hws_map, dev);
Wang Zhenyudc7a9312007-06-10 15:58:19 +1000829 if (dev_priv->hws_map.handle == NULL) {
Wang Zhenyudc7a9312007-06-10 15:58:19 +1000830 i915_dma_cleanup(dev);
831 dev_priv->status_gfx_addr = 0;
832 DRM_ERROR("can not ioremap virtual address for"
833 " G33 hw status page\n");
Eric Anholt20caafa2007-08-25 19:22:43 +1000834 return -ENOMEM;
Wang Zhenyudc7a9312007-06-10 15:58:19 +1000835 }
Zou Nan hai8187a2b2010-05-21 09:08:55 +0800836 ring->status_page.page_addr = dev_priv->hws_map.handle;
837 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
838 I915_WRITE(HWS_PGA, ring->status_page.gfx_addr);
Wang Zhenyudc7a9312007-06-10 15:58:19 +1000839
Zhao Yakui8a4c47f2009-07-20 13:48:04 +0800840 DRM_DEBUG_DRIVER("load hws HWS_PGA with gfx mem 0x%x\n",
Zou Nan hai852835f2010-05-21 09:08:56 +0800841 dev_priv->status_gfx_addr);
Zhao Yakui8a4c47f2009-07-20 13:48:04 +0800842 DRM_DEBUG_DRIVER("load hws at %p\n",
Zou Nan hai852835f2010-05-21 09:08:56 +0800843 dev_priv->hw_status_page);
Wang Zhenyudc7a9312007-06-10 15:58:19 +1000844 return 0;
845}
846
Dave Airlieec2a4c32009-08-04 11:43:41 +1000847static int i915_get_bridge_dev(struct drm_device *dev)
848{
849 struct drm_i915_private *dev_priv = dev->dev_private;
850
851 dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0,0));
852 if (!dev_priv->bridge_dev) {
853 DRM_ERROR("bridge device not found\n");
854 return -1;
855 }
856 return 0;
857}
858
Zhenyu Wangc48044112009-12-17 14:48:43 +0800859#define MCHBAR_I915 0x44
860#define MCHBAR_I965 0x48
861#define MCHBAR_SIZE (4*4096)
862
863#define DEVEN_REG 0x54
864#define DEVEN_MCHBAR_EN (1 << 28)
865
866/* Allocate space for the MCH regs if needed, return nonzero on error */
867static int
868intel_alloc_mchbar_resource(struct drm_device *dev)
869{
870 drm_i915_private_t *dev_priv = dev->dev_private;
871 int reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915;
872 u32 temp_lo, temp_hi = 0;
873 u64 mchbar_addr;
874 int ret = 0;
875
876 if (IS_I965G(dev))
877 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
878 pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
879 mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
880
881 /* If ACPI doesn't have it, assume we need to allocate it ourselves */
882#ifdef CONFIG_PNP
883 if (mchbar_addr &&
884 pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE)) {
885 ret = 0;
886 goto out;
887 }
888#endif
889
890 /* Get some space for it */
891 ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus, &dev_priv->mch_res,
892 MCHBAR_SIZE, MCHBAR_SIZE,
893 PCIBIOS_MIN_MEM,
894 0, pcibios_align_resource,
895 dev_priv->bridge_dev);
896 if (ret) {
897 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
898 dev_priv->mch_res.start = 0;
899 goto out;
900 }
901
902 if (IS_I965G(dev))
903 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
904 upper_32_bits(dev_priv->mch_res.start));
905
906 pci_write_config_dword(dev_priv->bridge_dev, reg,
907 lower_32_bits(dev_priv->mch_res.start));
908out:
909 return ret;
910}
911
912/* Setup MCHBAR if possible, return true if we should disable it again */
913static void
914intel_setup_mchbar(struct drm_device *dev)
915{
916 drm_i915_private_t *dev_priv = dev->dev_private;
917 int mchbar_reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915;
918 u32 temp;
919 bool enabled;
920
921 dev_priv->mchbar_need_disable = false;
922
923 if (IS_I915G(dev) || IS_I915GM(dev)) {
924 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
925 enabled = !!(temp & DEVEN_MCHBAR_EN);
926 } else {
927 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
928 enabled = temp & 1;
929 }
930
931 /* If it's already enabled, don't have to do anything */
932 if (enabled)
933 return;
934
935 if (intel_alloc_mchbar_resource(dev))
936 return;
937
938 dev_priv->mchbar_need_disable = true;
939
940 /* Space is allocated or reserved, so enable it. */
941 if (IS_I915G(dev) || IS_I915GM(dev)) {
942 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG,
943 temp | DEVEN_MCHBAR_EN);
944 } else {
945 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
946 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
947 }
948}
949
950static void
951intel_teardown_mchbar(struct drm_device *dev)
952{
953 drm_i915_private_t *dev_priv = dev->dev_private;
954 int mchbar_reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915;
955 u32 temp;
956
957 if (dev_priv->mchbar_need_disable) {
958 if (IS_I915G(dev) || IS_I915GM(dev)) {
959 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
960 temp &= ~DEVEN_MCHBAR_EN;
961 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp);
962 } else {
963 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
964 temp &= ~1;
965 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp);
966 }
967 }
968
969 if (dev_priv->mch_res.start)
970 release_resource(&dev_priv->mch_res);
971}
972
Jesse Barnes79e53942008-11-07 14:24:08 -0800973/**
974 * i915_probe_agp - get AGP bootup configuration
975 * @pdev: PCI device
976 * @aperture_size: returns AGP aperture configured size
977 * @preallocated_size: returns size of BIOS preallocated AGP space
978 *
979 * Since Intel integrated graphics are UMA, the BIOS has to set aside
980 * some RAM for the framebuffer at early boot. This code figures out
981 * how much was set aside so we can use it for our own purposes.
982 */
Eric Anholt2a34f5e62009-07-02 09:30:50 -0700983static int i915_probe_agp(struct drm_device *dev, uint32_t *aperture_size,
Jesse Barnes80824002009-09-10 15:28:06 -0700984 uint32_t *preallocated_size,
985 uint32_t *start)
Jesse Barnes79e53942008-11-07 14:24:08 -0800986{
Dave Airlieec2a4c32009-08-04 11:43:41 +1000987 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes79e53942008-11-07 14:24:08 -0800988 u16 tmp = 0;
989 unsigned long overhead;
Eric Anholt241fa852009-01-02 18:05:51 -0800990 unsigned long stolen;
Jesse Barnes79e53942008-11-07 14:24:08 -0800991
Jesse Barnes79e53942008-11-07 14:24:08 -0800992 /* Get the fb aperture size and "stolen" memory amount. */
Dave Airlieec2a4c32009-08-04 11:43:41 +1000993 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &tmp);
Jesse Barnes79e53942008-11-07 14:24:08 -0800994
995 *aperture_size = 1024 * 1024;
996 *preallocated_size = 1024 * 1024;
997
Eric Anholt60fd99e2008-12-03 22:50:02 -0800998 switch (dev->pdev->device) {
Jesse Barnes79e53942008-11-07 14:24:08 -0800999 case PCI_DEVICE_ID_INTEL_82830_CGC:
1000 case PCI_DEVICE_ID_INTEL_82845G_IG:
1001 case PCI_DEVICE_ID_INTEL_82855GM_IG:
1002 case PCI_DEVICE_ID_INTEL_82865_IG:
1003 if ((tmp & INTEL_GMCH_MEM_MASK) == INTEL_GMCH_MEM_64M)
1004 *aperture_size *= 64;
1005 else
1006 *aperture_size *= 128;
1007 break;
1008 default:
1009 /* 9xx supports large sizes, just look at the length */
Eric Anholt60fd99e2008-12-03 22:50:02 -08001010 *aperture_size = pci_resource_len(dev->pdev, 2);
Jesse Barnes79e53942008-11-07 14:24:08 -08001011 break;
1012 }
1013
1014 /*
1015 * Some of the preallocated space is taken by the GTT
1016 * and popup. GTT is 1K per MB of aperture size, and popup is 4K.
1017 */
Eric Anholtbad720f2009-10-22 16:11:14 -07001018 if (IS_G4X(dev) || IS_PINEVIEW(dev) || IS_IRONLAKE(dev) || IS_GEN6(dev))
Eric Anholt60fd99e2008-12-03 22:50:02 -08001019 overhead = 4096;
1020 else
1021 overhead = (*aperture_size / 1024) + 4096;
1022
Zhenyu Wang14bc4902009-11-11 01:25:25 +08001023 if (IS_GEN6(dev)) {
1024 /* SNB has memory control reg at 0x50.w */
1025 pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &tmp);
1026
1027 switch (tmp & SNB_GMCH_GMS_STOLEN_MASK) {
1028 case INTEL_855_GMCH_GMS_DISABLED:
Eric Anholtbad720f2009-10-22 16:11:14 -07001029 DRM_ERROR("video memory is disabled\n");
1030 return -1;
Zhenyu Wang14bc4902009-11-11 01:25:25 +08001031 case SNB_GMCH_GMS_STOLEN_32M:
1032 stolen = 32 * 1024 * 1024;
1033 break;
1034 case SNB_GMCH_GMS_STOLEN_64M:
1035 stolen = 64 * 1024 * 1024;
1036 break;
1037 case SNB_GMCH_GMS_STOLEN_96M:
1038 stolen = 96 * 1024 * 1024;
1039 break;
1040 case SNB_GMCH_GMS_STOLEN_128M:
1041 stolen = 128 * 1024 * 1024;
1042 break;
1043 case SNB_GMCH_GMS_STOLEN_160M:
1044 stolen = 160 * 1024 * 1024;
1045 break;
1046 case SNB_GMCH_GMS_STOLEN_192M:
1047 stolen = 192 * 1024 * 1024;
1048 break;
1049 case SNB_GMCH_GMS_STOLEN_224M:
1050 stolen = 224 * 1024 * 1024;
1051 break;
1052 case SNB_GMCH_GMS_STOLEN_256M:
1053 stolen = 256 * 1024 * 1024;
1054 break;
1055 case SNB_GMCH_GMS_STOLEN_288M:
1056 stolen = 288 * 1024 * 1024;
1057 break;
1058 case SNB_GMCH_GMS_STOLEN_320M:
1059 stolen = 320 * 1024 * 1024;
1060 break;
1061 case SNB_GMCH_GMS_STOLEN_352M:
1062 stolen = 352 * 1024 * 1024;
1063 break;
1064 case SNB_GMCH_GMS_STOLEN_384M:
1065 stolen = 384 * 1024 * 1024;
1066 break;
1067 case SNB_GMCH_GMS_STOLEN_416M:
1068 stolen = 416 * 1024 * 1024;
1069 break;
1070 case SNB_GMCH_GMS_STOLEN_448M:
1071 stolen = 448 * 1024 * 1024;
1072 break;
1073 case SNB_GMCH_GMS_STOLEN_480M:
1074 stolen = 480 * 1024 * 1024;
1075 break;
1076 case SNB_GMCH_GMS_STOLEN_512M:
1077 stolen = 512 * 1024 * 1024;
1078 break;
1079 default:
1080 DRM_ERROR("unexpected GMCH_GMS value: 0x%02x\n",
1081 tmp & SNB_GMCH_GMS_STOLEN_MASK);
1082 return -1;
Eric Anholtbad720f2009-10-22 16:11:14 -07001083 }
Zhenyu Wang14bc4902009-11-11 01:25:25 +08001084 } else {
1085 switch (tmp & INTEL_GMCH_GMS_MASK) {
1086 case INTEL_855_GMCH_GMS_DISABLED:
1087 DRM_ERROR("video memory is disabled\n");
1088 return -1;
1089 case INTEL_855_GMCH_GMS_STOLEN_1M:
1090 stolen = 1 * 1024 * 1024;
1091 break;
1092 case INTEL_855_GMCH_GMS_STOLEN_4M:
1093 stolen = 4 * 1024 * 1024;
1094 break;
1095 case INTEL_855_GMCH_GMS_STOLEN_8M:
1096 stolen = 8 * 1024 * 1024;
1097 break;
1098 case INTEL_855_GMCH_GMS_STOLEN_16M:
1099 stolen = 16 * 1024 * 1024;
1100 break;
1101 case INTEL_855_GMCH_GMS_STOLEN_32M:
1102 stolen = 32 * 1024 * 1024;
1103 break;
1104 case INTEL_915G_GMCH_GMS_STOLEN_48M:
1105 stolen = 48 * 1024 * 1024;
1106 break;
1107 case INTEL_915G_GMCH_GMS_STOLEN_64M:
1108 stolen = 64 * 1024 * 1024;
1109 break;
1110 case INTEL_GMCH_GMS_STOLEN_128M:
1111 stolen = 128 * 1024 * 1024;
1112 break;
1113 case INTEL_GMCH_GMS_STOLEN_256M:
1114 stolen = 256 * 1024 * 1024;
1115 break;
1116 case INTEL_GMCH_GMS_STOLEN_96M:
1117 stolen = 96 * 1024 * 1024;
1118 break;
1119 case INTEL_GMCH_GMS_STOLEN_160M:
1120 stolen = 160 * 1024 * 1024;
1121 break;
1122 case INTEL_GMCH_GMS_STOLEN_224M:
1123 stolen = 224 * 1024 * 1024;
1124 break;
1125 case INTEL_GMCH_GMS_STOLEN_352M:
1126 stolen = 352 * 1024 * 1024;
1127 break;
1128 default:
1129 DRM_ERROR("unexpected GMCH_GMS value: 0x%02x\n",
1130 tmp & INTEL_GMCH_GMS_MASK);
1131 return -1;
1132 }
Jesse Barnes79e53942008-11-07 14:24:08 -08001133 }
Zhenyu Wang14bc4902009-11-11 01:25:25 +08001134
Eric Anholt241fa852009-01-02 18:05:51 -08001135 *preallocated_size = stolen - overhead;
Jesse Barnes80824002009-09-10 15:28:06 -07001136 *start = overhead;
Jesse Barnes79e53942008-11-07 14:24:08 -08001137
1138 return 0;
1139}
1140
Jesse Barnes80824002009-09-10 15:28:06 -07001141#define PTE_ADDRESS_MASK 0xfffff000
1142#define PTE_ADDRESS_MASK_HIGH 0x000000f0 /* i915+ */
1143#define PTE_MAPPING_TYPE_UNCACHED (0 << 1)
1144#define PTE_MAPPING_TYPE_DCACHE (1 << 1) /* i830 only */
1145#define PTE_MAPPING_TYPE_CACHED (3 << 1)
1146#define PTE_MAPPING_TYPE_MASK (3 << 1)
1147#define PTE_VALID (1 << 0)
1148
1149/**
1150 * i915_gtt_to_phys - take a GTT address and turn it into a physical one
1151 * @dev: drm device
1152 * @gtt_addr: address to translate
1153 *
1154 * Some chip functions require allocations from stolen space but need the
1155 * physical address of the memory in question. We use this routine
1156 * to get a physical address suitable for register programming from a given
1157 * GTT address.
1158 */
1159static unsigned long i915_gtt_to_phys(struct drm_device *dev,
1160 unsigned long gtt_addr)
1161{
1162 unsigned long *gtt;
1163 unsigned long entry, phys;
1164 int gtt_bar = IS_I9XX(dev) ? 0 : 1;
1165 int gtt_offset, gtt_size;
1166
1167 if (IS_I965G(dev)) {
Eric Anholtbad720f2009-10-22 16:11:14 -07001168 if (IS_G4X(dev) || IS_IRONLAKE(dev) || IS_GEN6(dev)) {
Jesse Barnes80824002009-09-10 15:28:06 -07001169 gtt_offset = 2*1024*1024;
1170 gtt_size = 2*1024*1024;
1171 } else {
1172 gtt_offset = 512*1024;
1173 gtt_size = 512*1024;
1174 }
1175 } else {
1176 gtt_bar = 3;
1177 gtt_offset = 0;
1178 gtt_size = pci_resource_len(dev->pdev, gtt_bar);
1179 }
1180
1181 gtt = ioremap_wc(pci_resource_start(dev->pdev, gtt_bar) + gtt_offset,
1182 gtt_size);
1183 if (!gtt) {
1184 DRM_ERROR("ioremap of GTT failed\n");
1185 return 0;
1186 }
1187
1188 entry = *(volatile u32 *)(gtt + (gtt_addr / 1024));
1189
Zhao Yakui44d98a62009-10-09 11:39:40 +08001190 DRM_DEBUG_DRIVER("GTT addr: 0x%08lx, PTE: 0x%08lx\n", gtt_addr, entry);
Jesse Barnes80824002009-09-10 15:28:06 -07001191
1192 /* Mask out these reserved bits on this hardware. */
1193 if (!IS_I9XX(dev) || IS_I915G(dev) || IS_I915GM(dev) ||
1194 IS_I945G(dev) || IS_I945GM(dev)) {
1195 entry &= ~PTE_ADDRESS_MASK_HIGH;
1196 }
1197
1198 /* If it's not a mapping type we know, then bail. */
1199 if ((entry & PTE_MAPPING_TYPE_MASK) != PTE_MAPPING_TYPE_UNCACHED &&
1200 (entry & PTE_MAPPING_TYPE_MASK) != PTE_MAPPING_TYPE_CACHED) {
1201 iounmap(gtt);
1202 return 0;
1203 }
1204
1205 if (!(entry & PTE_VALID)) {
1206 DRM_ERROR("bad GTT entry in stolen space\n");
1207 iounmap(gtt);
1208 return 0;
1209 }
1210
1211 iounmap(gtt);
1212
1213 phys =(entry & PTE_ADDRESS_MASK) |
1214 ((uint64_t)(entry & PTE_ADDRESS_MASK_HIGH) << (32 - 4));
1215
Zhao Yakui44d98a62009-10-09 11:39:40 +08001216 DRM_DEBUG_DRIVER("GTT addr: 0x%08lx, phys addr: 0x%08lx\n", gtt_addr, phys);
Jesse Barnes80824002009-09-10 15:28:06 -07001217
1218 return phys;
1219}
1220
1221static void i915_warn_stolen(struct drm_device *dev)
1222{
1223 DRM_ERROR("not enough stolen space for compressed buffer, disabling\n");
1224 DRM_ERROR("hint: you may be able to increase stolen memory size in the BIOS to avoid this\n");
1225}
1226
1227static void i915_setup_compression(struct drm_device *dev, int size)
1228{
1229 struct drm_i915_private *dev_priv = dev->dev_private;
1230 struct drm_mm_node *compressed_fb, *compressed_llb;
Andrew Morton29bd0ae2009-11-17 14:08:52 -08001231 unsigned long cfb_base;
1232 unsigned long ll_base = 0;
Jesse Barnes80824002009-09-10 15:28:06 -07001233
1234 /* Leave 1M for line length buffer & misc. */
1235 compressed_fb = drm_mm_search_free(&dev_priv->vram, size, 4096, 0);
1236 if (!compressed_fb) {
Jesse Barnesb5e50c32010-02-05 12:42:41 -08001237 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
Jesse Barnes80824002009-09-10 15:28:06 -07001238 i915_warn_stolen(dev);
1239 return;
1240 }
1241
1242 compressed_fb = drm_mm_get_block(compressed_fb, size, 4096);
1243 if (!compressed_fb) {
1244 i915_warn_stolen(dev);
Jesse Barnesb5e50c32010-02-05 12:42:41 -08001245 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
Jesse Barnes80824002009-09-10 15:28:06 -07001246 return;
1247 }
1248
Jesse Barnes74dff282009-09-14 15:39:40 -07001249 cfb_base = i915_gtt_to_phys(dev, compressed_fb->start);
1250 if (!cfb_base) {
1251 DRM_ERROR("failed to get stolen phys addr, disabling FBC\n");
1252 drm_mm_put_block(compressed_fb);
Jesse Barnes80824002009-09-10 15:28:06 -07001253 }
1254
Jesse Barnes74dff282009-09-14 15:39:40 -07001255 if (!IS_GM45(dev)) {
1256 compressed_llb = drm_mm_search_free(&dev_priv->vram, 4096,
1257 4096, 0);
1258 if (!compressed_llb) {
1259 i915_warn_stolen(dev);
1260 return;
1261 }
1262
1263 compressed_llb = drm_mm_get_block(compressed_llb, 4096, 4096);
1264 if (!compressed_llb) {
1265 i915_warn_stolen(dev);
1266 return;
1267 }
1268
1269 ll_base = i915_gtt_to_phys(dev, compressed_llb->start);
1270 if (!ll_base) {
1271 DRM_ERROR("failed to get stolen phys addr, disabling FBC\n");
1272 drm_mm_put_block(compressed_fb);
1273 drm_mm_put_block(compressed_llb);
1274 }
Jesse Barnes80824002009-09-10 15:28:06 -07001275 }
1276
1277 dev_priv->cfb_size = size;
1278
Adam Jacksonee5382a2010-04-23 11:17:39 -04001279 intel_disable_fbc(dev);
Jesse Barnes20bf3772010-04-21 11:39:22 -07001280 dev_priv->compressed_fb = compressed_fb;
1281
Jesse Barnes74dff282009-09-14 15:39:40 -07001282 if (IS_GM45(dev)) {
Jesse Barnes74dff282009-09-14 15:39:40 -07001283 I915_WRITE(DPFC_CB_BASE, compressed_fb->start);
1284 } else {
Jesse Barnes74dff282009-09-14 15:39:40 -07001285 I915_WRITE(FBC_CFB_BASE, cfb_base);
1286 I915_WRITE(FBC_LL_BASE, ll_base);
Jesse Barnes20bf3772010-04-21 11:39:22 -07001287 dev_priv->compressed_llb = compressed_llb;
Jesse Barnes80824002009-09-10 15:28:06 -07001288 }
1289
Jesse Barnes80824002009-09-10 15:28:06 -07001290 DRM_DEBUG("FBC base 0x%08lx, ll base 0x%08lx, size %dM\n", cfb_base,
1291 ll_base, size >> 20);
Jesse Barnes80824002009-09-10 15:28:06 -07001292}
1293
Jesse Barnes20bf3772010-04-21 11:39:22 -07001294static void i915_cleanup_compression(struct drm_device *dev)
1295{
1296 struct drm_i915_private *dev_priv = dev->dev_private;
1297
1298 drm_mm_put_block(dev_priv->compressed_fb);
1299 if (!IS_GM45(dev))
1300 drm_mm_put_block(dev_priv->compressed_llb);
1301}
1302
Dave Airlie28d52042009-09-21 14:33:58 +10001303/* true = enable decode, false = disable decoder */
1304static unsigned int i915_vga_set_decode(void *cookie, bool state)
1305{
1306 struct drm_device *dev = cookie;
1307
1308 intel_modeset_vga_set_state(dev, state);
1309 if (state)
1310 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
1311 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1312 else
1313 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1314}
1315
Dave Airlie6a9ee8a2010-02-01 15:38:10 +10001316static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1317{
1318 struct drm_device *dev = pci_get_drvdata(pdev);
1319 pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
1320 if (state == VGA_SWITCHEROO_ON) {
1321 printk(KERN_INFO "i915: switched off\n");
1322 /* i915 resume handler doesn't set to D0 */
1323 pci_set_power_state(dev->pdev, PCI_D0);
1324 i915_resume(dev);
1325 } else {
1326 printk(KERN_ERR "i915: switched off\n");
1327 i915_suspend(dev, pmm);
1328 }
1329}
1330
1331static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
1332{
1333 struct drm_device *dev = pci_get_drvdata(pdev);
1334 bool can_switch;
1335
1336 spin_lock(&dev->count_lock);
1337 can_switch = (dev->open_count == 0);
1338 spin_unlock(&dev->count_lock);
1339 return can_switch;
1340}
1341
Eric Anholt2a34f5e62009-07-02 09:30:50 -07001342static int i915_load_modeset_init(struct drm_device *dev,
Jesse Barnes80824002009-09-10 15:28:06 -07001343 unsigned long prealloc_start,
Eric Anholt2a34f5e62009-07-02 09:30:50 -07001344 unsigned long prealloc_size,
1345 unsigned long agp_size)
Jesse Barnes79e53942008-11-07 14:24:08 -08001346{
1347 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes79e53942008-11-07 14:24:08 -08001348 int fb_bar = IS_I9XX(dev) ? 2 : 0;
1349 int ret = 0;
1350
1351 dev->mode_config.fb_base = drm_get_resource_start(dev, fb_bar) &
1352 0xff000000;
1353
Jesse Barnes79e53942008-11-07 14:24:08 -08001354 /* Basic memrange allocator for stolen space (aka vram) */
1355 drm_mm_init(&dev_priv->vram, 0, prealloc_size);
Jesse Barnes80824002009-09-10 15:28:06 -07001356 DRM_INFO("set up %ldM of stolen space\n", prealloc_size / (1024*1024));
Jesse Barnes79e53942008-11-07 14:24:08 -08001357
Ben Gamari11ed50e2009-09-14 17:48:45 -04001358 /* We're off and running w/KMS */
1359 dev_priv->mm.suspended = 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08001360
Eric Anholt13f4c432009-05-12 15:27:36 -07001361 /* Let GEM Manage from end of prealloc space to end of aperture.
1362 *
1363 * However, leave one page at the end still bound to the scratch page.
1364 * There are a number of places where the hardware apparently
1365 * prefetches past the end of the object, and we've seen multiple
1366 * hangs with the GPU head pointer stuck in a batchbuffer bound
1367 * at the last page of the aperture. One page should be enough to
1368 * keep any prefetching inside of the aperture.
1369 */
1370 i915_gem_do_init(dev, prealloc_size, agp_size - 4096);
Jesse Barnes79e53942008-11-07 14:24:08 -08001371
Ben Gamari11ed50e2009-09-14 17:48:45 -04001372 mutex_lock(&dev->struct_mutex);
Jesse Barnes79e53942008-11-07 14:24:08 -08001373 ret = i915_gem_init_ringbuffer(dev);
Ben Gamari11ed50e2009-09-14 17:48:45 -04001374 mutex_unlock(&dev->struct_mutex);
Jesse Barnes79e53942008-11-07 14:24:08 -08001375 if (ret)
Dave Airlieb8da7de2009-06-02 16:50:35 +10001376 goto out;
Jesse Barnes79e53942008-11-07 14:24:08 -08001377
Jesse Barnes80824002009-09-10 15:28:06 -07001378 /* Try to set up FBC with a reasonable compressed buffer size */
Shaohua Li9216d442009-10-10 15:20:55 +08001379 if (I915_HAS_FBC(dev) && i915_powersave) {
Jesse Barnes80824002009-09-10 15:28:06 -07001380 int cfb_size;
1381
1382 /* Try to get an 8M buffer... */
1383 if (prealloc_size > (9*1024*1024))
1384 cfb_size = 8*1024*1024;
1385 else /* fall back to 7/8 of the stolen space */
1386 cfb_size = prealloc_size * 7 / 8;
1387 i915_setup_compression(dev, cfb_size);
1388 }
1389
Jesse Barnes79e53942008-11-07 14:24:08 -08001390 /* Allow hardware batchbuffers unless told otherwise.
1391 */
1392 dev_priv->allow_batchbuffer = 1;
1393
1394 ret = intel_init_bios(dev);
1395 if (ret)
1396 DRM_INFO("failed to find VBIOS tables\n");
1397
Dave Airlie28d52042009-09-21 14:33:58 +10001398 /* if we have > 1 VGA cards, then disable the radeon VGA resources */
1399 ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
1400 if (ret)
1401 goto destroy_ringbuffer;
1402
Dave Airlie6a9ee8a2010-02-01 15:38:10 +10001403 ret = vga_switcheroo_register_client(dev->pdev,
1404 i915_switcheroo_set_state,
1405 i915_switcheroo_can_switch);
1406 if (ret)
1407 goto destroy_ringbuffer;
1408
Jesse Barnesb01f2c32009-12-11 11:07:17 -08001409 intel_modeset_init(dev);
1410
Jesse Barnes79e53942008-11-07 14:24:08 -08001411 ret = drm_irq_install(dev);
1412 if (ret)
1413 goto destroy_ringbuffer;
1414
Jesse Barnes79e53942008-11-07 14:24:08 -08001415 /* Always safe in the mode setting case. */
1416 /* FIXME: do pre/post-mode set stuff in core KMS code */
1417 dev->vblank_disable_allowed = 1;
1418
1419 /*
1420 * Initialize the hardware status page IRQ location.
1421 */
1422
1423 I915_WRITE(INSTPM, (1 << 5) | (1 << 21));
1424
Dave Airlie38651672010-03-30 05:34:13 +00001425 intel_fbdev_init(dev);
Dave Airlieeb1f8e42010-05-07 06:42:51 +00001426 drm_kms_helper_poll_init(dev);
Jesse Barnes79e53942008-11-07 14:24:08 -08001427 return 0;
1428
Jesse Barnes79e53942008-11-07 14:24:08 -08001429destroy_ringbuffer:
Eric Anholt21099532009-11-09 14:57:34 -08001430 mutex_lock(&dev->struct_mutex);
Jesse Barnes79e53942008-11-07 14:24:08 -08001431 i915_gem_cleanup_ringbuffer(dev);
Eric Anholt21099532009-11-09 14:57:34 -08001432 mutex_unlock(&dev->struct_mutex);
Jesse Barnes79e53942008-11-07 14:24:08 -08001433out:
1434 return ret;
1435}
1436
Dave Airlie7c1c2872008-11-28 14:22:24 +10001437int i915_master_create(struct drm_device *dev, struct drm_master *master)
1438{
1439 struct drm_i915_master_private *master_priv;
1440
Eric Anholt9a298b22009-03-24 12:23:04 -07001441 master_priv = kzalloc(sizeof(*master_priv), GFP_KERNEL);
Dave Airlie7c1c2872008-11-28 14:22:24 +10001442 if (!master_priv)
1443 return -ENOMEM;
1444
1445 master->driver_priv = master_priv;
1446 return 0;
1447}
1448
1449void i915_master_destroy(struct drm_device *dev, struct drm_master *master)
1450{
1451 struct drm_i915_master_private *master_priv = master->driver_priv;
1452
1453 if (!master_priv)
1454 return;
1455
Eric Anholt9a298b22009-03-24 12:23:04 -07001456 kfree(master_priv);
Dave Airlie7c1c2872008-11-28 14:22:24 +10001457
1458 master->driver_priv = NULL;
1459}
1460
Jesse Barnes7648fa92010-05-20 14:28:11 -07001461static void i915_pineview_get_mem_freq(struct drm_device *dev)
Shaohua Li7662c8b2009-06-26 11:23:55 +08001462{
1463 drm_i915_private_t *dev_priv = dev->dev_private;
1464 u32 tmp;
1465
Shaohua Li7662c8b2009-06-26 11:23:55 +08001466 tmp = I915_READ(CLKCFG);
1467
1468 switch (tmp & CLKCFG_FSB_MASK) {
1469 case CLKCFG_FSB_533:
1470 dev_priv->fsb_freq = 533; /* 133*4 */
1471 break;
1472 case CLKCFG_FSB_800:
1473 dev_priv->fsb_freq = 800; /* 200*4 */
1474 break;
1475 case CLKCFG_FSB_667:
1476 dev_priv->fsb_freq = 667; /* 167*4 */
1477 break;
1478 case CLKCFG_FSB_400:
1479 dev_priv->fsb_freq = 400; /* 100*4 */
1480 break;
1481 }
1482
1483 switch (tmp & CLKCFG_MEM_MASK) {
1484 case CLKCFG_MEM_533:
1485 dev_priv->mem_freq = 533;
1486 break;
1487 case CLKCFG_MEM_667:
1488 dev_priv->mem_freq = 667;
1489 break;
1490 case CLKCFG_MEM_800:
1491 dev_priv->mem_freq = 800;
1492 break;
1493 }
1494}
1495
Jesse Barnes7648fa92010-05-20 14:28:11 -07001496static void i915_ironlake_get_mem_freq(struct drm_device *dev)
1497{
1498 drm_i915_private_t *dev_priv = dev->dev_private;
1499 u16 ddrpll, csipll;
1500
1501 ddrpll = I915_READ16(DDRMPLL1);
1502 csipll = I915_READ16(CSIPLL0);
1503
1504 switch (ddrpll & 0xff) {
1505 case 0xc:
1506 dev_priv->mem_freq = 800;
1507 break;
1508 case 0x10:
1509 dev_priv->mem_freq = 1066;
1510 break;
1511 case 0x14:
1512 dev_priv->mem_freq = 1333;
1513 break;
1514 case 0x18:
1515 dev_priv->mem_freq = 1600;
1516 break;
1517 default:
1518 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
1519 ddrpll & 0xff);
1520 dev_priv->mem_freq = 0;
1521 break;
1522 }
1523
1524 dev_priv->r_t = dev_priv->mem_freq;
1525
1526 switch (csipll & 0x3ff) {
1527 case 0x00c:
1528 dev_priv->fsb_freq = 3200;
1529 break;
1530 case 0x00e:
1531 dev_priv->fsb_freq = 3733;
1532 break;
1533 case 0x010:
1534 dev_priv->fsb_freq = 4266;
1535 break;
1536 case 0x012:
1537 dev_priv->fsb_freq = 4800;
1538 break;
1539 case 0x014:
1540 dev_priv->fsb_freq = 5333;
1541 break;
1542 case 0x016:
1543 dev_priv->fsb_freq = 5866;
1544 break;
1545 case 0x018:
1546 dev_priv->fsb_freq = 6400;
1547 break;
1548 default:
1549 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
1550 csipll & 0x3ff);
1551 dev_priv->fsb_freq = 0;
1552 break;
1553 }
1554
1555 if (dev_priv->fsb_freq == 3200) {
1556 dev_priv->c_m = 0;
1557 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
1558 dev_priv->c_m = 1;
1559 } else {
1560 dev_priv->c_m = 2;
1561 }
1562}
1563
1564struct v_table {
1565 u8 vid;
1566 unsigned long vd; /* in .1 mil */
1567 unsigned long vm; /* in .1 mil */
1568 u8 pvid;
1569};
1570
1571static struct v_table v_table[] = {
1572 { 0, 16125, 15000, 0x7f, },
1573 { 1, 16000, 14875, 0x7e, },
1574 { 2, 15875, 14750, 0x7d, },
1575 { 3, 15750, 14625, 0x7c, },
1576 { 4, 15625, 14500, 0x7b, },
1577 { 5, 15500, 14375, 0x7a, },
1578 { 6, 15375, 14250, 0x79, },
1579 { 7, 15250, 14125, 0x78, },
1580 { 8, 15125, 14000, 0x77, },
1581 { 9, 15000, 13875, 0x76, },
1582 { 10, 14875, 13750, 0x75, },
1583 { 11, 14750, 13625, 0x74, },
1584 { 12, 14625, 13500, 0x73, },
1585 { 13, 14500, 13375, 0x72, },
1586 { 14, 14375, 13250, 0x71, },
1587 { 15, 14250, 13125, 0x70, },
1588 { 16, 14125, 13000, 0x6f, },
1589 { 17, 14000, 12875, 0x6e, },
1590 { 18, 13875, 12750, 0x6d, },
1591 { 19, 13750, 12625, 0x6c, },
1592 { 20, 13625, 12500, 0x6b, },
1593 { 21, 13500, 12375, 0x6a, },
1594 { 22, 13375, 12250, 0x69, },
1595 { 23, 13250, 12125, 0x68, },
1596 { 24, 13125, 12000, 0x67, },
1597 { 25, 13000, 11875, 0x66, },
1598 { 26, 12875, 11750, 0x65, },
1599 { 27, 12750, 11625, 0x64, },
1600 { 28, 12625, 11500, 0x63, },
1601 { 29, 12500, 11375, 0x62, },
1602 { 30, 12375, 11250, 0x61, },
1603 { 31, 12250, 11125, 0x60, },
1604 { 32, 12125, 11000, 0x5f, },
1605 { 33, 12000, 10875, 0x5e, },
1606 { 34, 11875, 10750, 0x5d, },
1607 { 35, 11750, 10625, 0x5c, },
1608 { 36, 11625, 10500, 0x5b, },
1609 { 37, 11500, 10375, 0x5a, },
1610 { 38, 11375, 10250, 0x59, },
1611 { 39, 11250, 10125, 0x58, },
1612 { 40, 11125, 10000, 0x57, },
1613 { 41, 11000, 9875, 0x56, },
1614 { 42, 10875, 9750, 0x55, },
1615 { 43, 10750, 9625, 0x54, },
1616 { 44, 10625, 9500, 0x53, },
1617 { 45, 10500, 9375, 0x52, },
1618 { 46, 10375, 9250, 0x51, },
1619 { 47, 10250, 9125, 0x50, },
1620 { 48, 10125, 9000, 0x4f, },
1621 { 49, 10000, 8875, 0x4e, },
1622 { 50, 9875, 8750, 0x4d, },
1623 { 51, 9750, 8625, 0x4c, },
1624 { 52, 9625, 8500, 0x4b, },
1625 { 53, 9500, 8375, 0x4a, },
1626 { 54, 9375, 8250, 0x49, },
1627 { 55, 9250, 8125, 0x48, },
1628 { 56, 9125, 8000, 0x47, },
1629 { 57, 9000, 7875, 0x46, },
1630 { 58, 8875, 7750, 0x45, },
1631 { 59, 8750, 7625, 0x44, },
1632 { 60, 8625, 7500, 0x43, },
1633 { 61, 8500, 7375, 0x42, },
1634 { 62, 8375, 7250, 0x41, },
1635 { 63, 8250, 7125, 0x40, },
1636 { 64, 8125, 7000, 0x3f, },
1637 { 65, 8000, 6875, 0x3e, },
1638 { 66, 7875, 6750, 0x3d, },
1639 { 67, 7750, 6625, 0x3c, },
1640 { 68, 7625, 6500, 0x3b, },
1641 { 69, 7500, 6375, 0x3a, },
1642 { 70, 7375, 6250, 0x39, },
1643 { 71, 7250, 6125, 0x38, },
1644 { 72, 7125, 6000, 0x37, },
1645 { 73, 7000, 5875, 0x36, },
1646 { 74, 6875, 5750, 0x35, },
1647 { 75, 6750, 5625, 0x34, },
1648 { 76, 6625, 5500, 0x33, },
1649 { 77, 6500, 5375, 0x32, },
1650 { 78, 6375, 5250, 0x31, },
1651 { 79, 6250, 5125, 0x30, },
1652 { 80, 6125, 5000, 0x2f, },
1653 { 81, 6000, 4875, 0x2e, },
1654 { 82, 5875, 4750, 0x2d, },
1655 { 83, 5750, 4625, 0x2c, },
1656 { 84, 5625, 4500, 0x2b, },
1657 { 85, 5500, 4375, 0x2a, },
1658 { 86, 5375, 4250, 0x29, },
1659 { 87, 5250, 4125, 0x28, },
1660 { 88, 5125, 4000, 0x27, },
1661 { 89, 5000, 3875, 0x26, },
1662 { 90, 4875, 3750, 0x25, },
1663 { 91, 4750, 3625, 0x24, },
1664 { 92, 4625, 3500, 0x23, },
1665 { 93, 4500, 3375, 0x22, },
1666 { 94, 4375, 3250, 0x21, },
1667 { 95, 4250, 3125, 0x20, },
1668 { 96, 4125, 3000, 0x1f, },
1669 { 97, 4125, 3000, 0x1e, },
1670 { 98, 4125, 3000, 0x1d, },
1671 { 99, 4125, 3000, 0x1c, },
1672 { 100, 4125, 3000, 0x1b, },
1673 { 101, 4125, 3000, 0x1a, },
1674 { 102, 4125, 3000, 0x19, },
1675 { 103, 4125, 3000, 0x18, },
1676 { 104, 4125, 3000, 0x17, },
1677 { 105, 4125, 3000, 0x16, },
1678 { 106, 4125, 3000, 0x15, },
1679 { 107, 4125, 3000, 0x14, },
1680 { 108, 4125, 3000, 0x13, },
1681 { 109, 4125, 3000, 0x12, },
1682 { 110, 4125, 3000, 0x11, },
1683 { 111, 4125, 3000, 0x10, },
1684 { 112, 4125, 3000, 0x0f, },
1685 { 113, 4125, 3000, 0x0e, },
1686 { 114, 4125, 3000, 0x0d, },
1687 { 115, 4125, 3000, 0x0c, },
1688 { 116, 4125, 3000, 0x0b, },
1689 { 117, 4125, 3000, 0x0a, },
1690 { 118, 4125, 3000, 0x09, },
1691 { 119, 4125, 3000, 0x08, },
1692 { 120, 1125, 0, 0x07, },
1693 { 121, 1000, 0, 0x06, },
1694 { 122, 875, 0, 0x05, },
1695 { 123, 750, 0, 0x04, },
1696 { 124, 625, 0, 0x03, },
1697 { 125, 500, 0, 0x02, },
1698 { 126, 375, 0, 0x01, },
1699 { 127, 0, 0, 0x00, },
1700};
1701
1702struct cparams {
1703 int i;
1704 int t;
1705 int m;
1706 int c;
1707};
1708
1709static struct cparams cparams[] = {
1710 { 1, 1333, 301, 28664 },
1711 { 1, 1066, 294, 24460 },
1712 { 1, 800, 294, 25192 },
1713 { 0, 1333, 276, 27605 },
1714 { 0, 1066, 276, 27605 },
1715 { 0, 800, 231, 23784 },
1716};
1717
1718unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
1719{
1720 u64 total_count, diff, ret;
1721 u32 count1, count2, count3, m = 0, c = 0;
1722 unsigned long now = jiffies_to_msecs(jiffies), diff1;
1723 int i;
1724
1725 diff1 = now - dev_priv->last_time1;
1726
1727 count1 = I915_READ(DMIEC);
1728 count2 = I915_READ(DDREC);
1729 count3 = I915_READ(CSIEC);
1730
1731 total_count = count1 + count2 + count3;
1732
1733 /* FIXME: handle per-counter overflow */
1734 if (total_count < dev_priv->last_count1) {
1735 diff = ~0UL - dev_priv->last_count1;
1736 diff += total_count;
1737 } else {
1738 diff = total_count - dev_priv->last_count1;
1739 }
1740
1741 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
1742 if (cparams[i].i == dev_priv->c_m &&
1743 cparams[i].t == dev_priv->r_t) {
1744 m = cparams[i].m;
1745 c = cparams[i].c;
1746 break;
1747 }
1748 }
1749
1750 div_u64(diff, diff1);
1751 ret = ((m * diff) + c);
1752 div_u64(ret, 10);
1753
1754 dev_priv->last_count1 = total_count;
1755 dev_priv->last_time1 = now;
1756
1757 return ret;
1758}
1759
1760unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
1761{
1762 unsigned long m, x, b;
1763 u32 tsfs;
1764
1765 tsfs = I915_READ(TSFS);
1766
1767 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
1768 x = I915_READ8(TR1);
1769
1770 b = tsfs & TSFS_INTR_MASK;
1771
1772 return ((m * x) / 127) - b;
1773}
1774
1775static unsigned long pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
1776{
1777 unsigned long val = 0;
1778 int i;
1779
1780 for (i = 0; i < ARRAY_SIZE(v_table); i++) {
1781 if (v_table[i].pvid == pxvid) {
1782 if (IS_MOBILE(dev_priv->dev))
1783 val = v_table[i].vm;
1784 else
1785 val = v_table[i].vd;
1786 }
1787 }
1788
1789 return val;
1790}
1791
1792void i915_update_gfx_val(struct drm_i915_private *dev_priv)
1793{
1794 struct timespec now, diff1;
1795 u64 diff;
1796 unsigned long diffms;
1797 u32 count;
1798
1799 getrawmonotonic(&now);
1800 diff1 = timespec_sub(now, dev_priv->last_time2);
1801
1802 /* Don't divide by 0 */
1803 diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
1804 if (!diffms)
1805 return;
1806
1807 count = I915_READ(GFXEC);
1808
1809 if (count < dev_priv->last_count2) {
1810 diff = ~0UL - dev_priv->last_count2;
1811 diff += count;
1812 } else {
1813 diff = count - dev_priv->last_count2;
1814 }
1815
1816 dev_priv->last_count2 = count;
1817 dev_priv->last_time2 = now;
1818
1819 /* More magic constants... */
1820 diff = diff * 1181;
1821 div_u64(diff, diffms * 10);
1822 dev_priv->gfx_power = diff;
1823}
1824
1825unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
1826{
1827 unsigned long t, corr, state1, corr2, state2;
1828 u32 pxvid, ext_v;
1829
1830 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->cur_delay * 4));
1831 pxvid = (pxvid >> 24) & 0x7f;
1832 ext_v = pvid_to_extvid(dev_priv, pxvid);
1833
1834 state1 = ext_v;
1835
1836 t = i915_mch_val(dev_priv);
1837
1838 /* Revel in the empirically derived constants */
1839
1840 /* Correction factor in 1/100000 units */
1841 if (t > 80)
1842 corr = ((t * 2349) + 135940);
1843 else if (t >= 50)
1844 corr = ((t * 964) + 29317);
1845 else /* < 50 */
1846 corr = ((t * 301) + 1004);
1847
1848 corr = corr * ((150142 * state1) / 10000 - 78642);
1849 corr /= 100000;
1850 corr2 = (corr * dev_priv->corr);
1851
1852 state2 = (corr2 * state1) / 10000;
1853 state2 /= 100; /* convert to mW */
1854
1855 i915_update_gfx_val(dev_priv);
1856
1857 return dev_priv->gfx_power + state2;
1858}
1859
1860/* Global for IPS driver to get at the current i915 device */
1861static struct drm_i915_private *i915_mch_dev;
1862/*
1863 * Lock protecting IPS related data structures
1864 * - i915_mch_dev
1865 * - dev_priv->max_delay
1866 * - dev_priv->min_delay
1867 * - dev_priv->fmax
1868 * - dev_priv->gpu_busy
1869 */
1870DEFINE_SPINLOCK(mchdev_lock);
1871
1872/**
1873 * i915_read_mch_val - return value for IPS use
1874 *
1875 * Calculate and return a value for the IPS driver to use when deciding whether
1876 * we have thermal and power headroom to increase CPU or GPU power budget.
1877 */
1878unsigned long i915_read_mch_val(void)
1879{
1880 struct drm_i915_private *dev_priv;
1881 unsigned long chipset_val, graphics_val, ret = 0;
1882
1883 spin_lock(&mchdev_lock);
1884 if (!i915_mch_dev)
1885 goto out_unlock;
1886 dev_priv = i915_mch_dev;
1887
1888 chipset_val = i915_chipset_val(dev_priv);
1889 graphics_val = i915_gfx_val(dev_priv);
1890
1891 ret = chipset_val + graphics_val;
1892
1893out_unlock:
1894 spin_unlock(&mchdev_lock);
1895
1896 return ret;
1897}
1898EXPORT_SYMBOL_GPL(i915_read_mch_val);
1899
1900/**
1901 * i915_gpu_raise - raise GPU frequency limit
1902 *
1903 * Raise the limit; IPS indicates we have thermal headroom.
1904 */
1905bool i915_gpu_raise(void)
1906{
1907 struct drm_i915_private *dev_priv;
1908 bool ret = true;
1909
1910 spin_lock(&mchdev_lock);
1911 if (!i915_mch_dev) {
1912 ret = false;
1913 goto out_unlock;
1914 }
1915 dev_priv = i915_mch_dev;
1916
1917 if (dev_priv->max_delay > dev_priv->fmax)
1918 dev_priv->max_delay--;
1919
1920out_unlock:
1921 spin_unlock(&mchdev_lock);
1922
1923 return ret;
1924}
1925EXPORT_SYMBOL_GPL(i915_gpu_raise);
1926
1927/**
1928 * i915_gpu_lower - lower GPU frequency limit
1929 *
1930 * IPS indicates we're close to a thermal limit, so throttle back the GPU
1931 * frequency maximum.
1932 */
1933bool i915_gpu_lower(void)
1934{
1935 struct drm_i915_private *dev_priv;
1936 bool ret = true;
1937
1938 spin_lock(&mchdev_lock);
1939 if (!i915_mch_dev) {
1940 ret = false;
1941 goto out_unlock;
1942 }
1943 dev_priv = i915_mch_dev;
1944
1945 if (dev_priv->max_delay < dev_priv->min_delay)
1946 dev_priv->max_delay++;
1947
1948out_unlock:
1949 spin_unlock(&mchdev_lock);
1950
1951 return ret;
1952}
1953EXPORT_SYMBOL_GPL(i915_gpu_lower);
1954
1955/**
1956 * i915_gpu_busy - indicate GPU business to IPS
1957 *
1958 * Tell the IPS driver whether or not the GPU is busy.
1959 */
1960bool i915_gpu_busy(void)
1961{
1962 struct drm_i915_private *dev_priv;
1963 bool ret = false;
1964
1965 spin_lock(&mchdev_lock);
1966 if (!i915_mch_dev)
1967 goto out_unlock;
1968 dev_priv = i915_mch_dev;
1969
1970 ret = dev_priv->busy;
1971
1972out_unlock:
1973 spin_unlock(&mchdev_lock);
1974
1975 return ret;
1976}
1977EXPORT_SYMBOL_GPL(i915_gpu_busy);
1978
1979/**
1980 * i915_gpu_turbo_disable - disable graphics turbo
1981 *
1982 * Disable graphics turbo by resetting the max frequency and setting the
1983 * current frequency to the default.
1984 */
1985bool i915_gpu_turbo_disable(void)
1986{
1987 struct drm_i915_private *dev_priv;
1988 bool ret = true;
1989
1990 spin_lock(&mchdev_lock);
1991 if (!i915_mch_dev) {
1992 ret = false;
1993 goto out_unlock;
1994 }
1995 dev_priv = i915_mch_dev;
1996
1997 dev_priv->max_delay = dev_priv->fstart;
1998
1999 if (!ironlake_set_drps(dev_priv->dev, dev_priv->fstart))
2000 ret = false;
2001
2002out_unlock:
2003 spin_unlock(&mchdev_lock);
2004
2005 return ret;
2006}
2007EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
2008
Jesse Barnes79e53942008-11-07 14:24:08 -08002009/**
2010 * i915_driver_load - setup chip and create an initial config
2011 * @dev: DRM device
2012 * @flags: startup flags
2013 *
2014 * The driver load routine has to do several things:
2015 * - drive output discovery via intel_modeset_init()
2016 * - initialize the memory manager
2017 * - allocate initial config memory
2018 * - setup the DRM framebuffer with the allocated memory
2019 */
Dave Airlie84b1fd12007-07-11 15:53:27 +10002020int i915_driver_load(struct drm_device *dev, unsigned long flags)
Dave Airlie22eae942005-11-10 22:16:34 +11002021{
Luca Tettamantiea059a12010-04-08 21:41:59 +02002022 struct drm_i915_private *dev_priv;
Benjamin Herrenschmidtd883f7f2009-02-02 16:55:45 +11002023 resource_size_t base, size;
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -05002024 int ret = 0, mmio_bar;
Jesse Barnes80824002009-09-10 15:28:06 -07002025 uint32_t agp_size, prealloc_size, prealloc_start;
Dave Airlie22eae942005-11-10 22:16:34 +11002026 /* i915 has 4 more counters */
2027 dev->counters += 4;
2028 dev->types[6] = _DRM_STAT_IRQ;
2029 dev->types[7] = _DRM_STAT_PRIMARY;
2030 dev->types[8] = _DRM_STAT_SECONDARY;
2031 dev->types[9] = _DRM_STAT_DMA;
2032
Eric Anholt9a298b22009-03-24 12:23:04 -07002033 dev_priv = kzalloc(sizeof(drm_i915_private_t), GFP_KERNEL);
Jesse Barnesba8bbcf2007-11-22 14:14:14 +10002034 if (dev_priv == NULL)
2035 return -ENOMEM;
2036
Jesse Barnesba8bbcf2007-11-22 14:14:14 +10002037 dev->dev_private = (void *)dev_priv;
Eric Anholt673a3942008-07-30 12:06:12 -07002038 dev_priv->dev = dev;
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -05002039 dev_priv->info = (struct intel_device_info *) flags;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +10002040
2041 /* Add register map (needed for suspend/resume) */
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -05002042 mmio_bar = IS_I9XX(dev) ? 0 : 1;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +10002043 base = drm_get_resource_start(dev, mmio_bar);
2044 size = drm_get_resource_len(dev, mmio_bar);
2045
Dave Airlieec2a4c32009-08-04 11:43:41 +10002046 if (i915_get_bridge_dev(dev)) {
2047 ret = -EIO;
2048 goto free_priv;
2049 }
2050
Eric Anholt3043c602008-10-02 12:24:47 -07002051 dev_priv->regs = ioremap(base, size);
Jesse Barnes79e53942008-11-07 14:24:08 -08002052 if (!dev_priv->regs) {
2053 DRM_ERROR("failed to map registers\n");
2054 ret = -EIO;
Dave Airlieec2a4c32009-08-04 11:43:41 +10002055 goto put_bridge;
Jesse Barnes79e53942008-11-07 14:24:08 -08002056 }
Eric Anholted4cb412008-07-29 12:10:39 -07002057
Eric Anholtab657db12009-01-23 12:57:47 -08002058 dev_priv->mm.gtt_mapping =
2059 io_mapping_create_wc(dev->agp->base,
2060 dev->agp->agp_info.aper_size * 1024*1024);
Venkatesh Pallipadi66441072009-02-24 17:35:11 -08002061 if (dev_priv->mm.gtt_mapping == NULL) {
2062 ret = -EIO;
2063 goto out_rmmap;
2064 }
2065
Eric Anholtab657db12009-01-23 12:57:47 -08002066 /* Set up a WC MTRR for non-PAT systems. This is more common than
2067 * one would think, because the kernel disables PAT on first
2068 * generation Core chips because WC PAT gets overridden by a UC
2069 * MTRR if present. Even if a UC MTRR isn't present.
2070 */
2071 dev_priv->mm.gtt_mtrr = mtrr_add(dev->agp->base,
2072 dev->agp->agp_info.aper_size *
2073 1024 * 1024,
2074 MTRR_TYPE_WRCOMB, 1);
2075 if (dev_priv->mm.gtt_mtrr < 0) {
Eric Anholt040aefa2009-03-10 12:31:12 -07002076 DRM_INFO("MTRR allocation failed. Graphics "
Eric Anholtab657db12009-01-23 12:57:47 -08002077 "performance may suffer.\n");
2078 }
2079
Jesse Barnes80824002009-09-10 15:28:06 -07002080 ret = i915_probe_agp(dev, &agp_size, &prealloc_size, &prealloc_start);
Eric Anholt2a34f5e62009-07-02 09:30:50 -07002081 if (ret)
2082 goto out_iomapfree;
2083
Chris Wilsonaed5f1d2009-10-14 13:40:04 +01002084 dev_priv->wq = create_singlethread_workqueue("i915");
Eric Anholt9c9fe1f2009-08-03 16:09:16 -07002085 if (dev_priv->wq == NULL) {
2086 DRM_ERROR("Failed to create our workqueue.\n");
2087 ret = -ENOMEM;
2088 goto out_iomapfree;
2089 }
2090
Dave Airlieac5c4e72008-12-19 15:38:34 +10002091 /* enable GEM by default */
2092 dev_priv->has_gem = 1;
Dave Airlieac5c4e72008-12-19 15:38:34 +10002093
Eric Anholt2a34f5e62009-07-02 09:30:50 -07002094 if (prealloc_size > agp_size * 3 / 4) {
2095 DRM_ERROR("Detected broken video BIOS with %d/%dkB of video "
2096 "memory stolen.\n",
2097 prealloc_size / 1024, agp_size / 1024);
2098 DRM_ERROR("Disabling GEM. (try reducing stolen memory or "
2099 "updating the BIOS to fix).\n");
2100 dev_priv->has_gem = 0;
2101 }
2102
Chris Wilson79a78dd2010-05-17 09:23:54 +01002103 if (dev_priv->has_gem == 0 &&
2104 drm_core_check_feature(dev, DRIVER_MODESET)) {
2105 DRM_ERROR("kernel modesetting requires GEM, disabling driver.\n");
2106 ret = -ENODEV;
2107 goto out_iomapfree;
2108 }
2109
Jesse Barnes9880b7a2009-02-06 10:22:41 -08002110 dev->driver->get_vblank_counter = i915_get_vblank_counter;
Jesse Barnes42c27982009-05-05 13:13:16 -07002111 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
Eric Anholtbad720f2009-10-22 16:11:14 -07002112 if (IS_G4X(dev) || IS_IRONLAKE(dev) || IS_GEN6(dev)) {
Jesse Barnes42c27982009-05-05 13:13:16 -07002113 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
Jesse Barnes9880b7a2009-02-06 10:22:41 -08002114 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
Jesse Barnes42c27982009-05-05 13:13:16 -07002115 }
Jesse Barnes9880b7a2009-02-06 10:22:41 -08002116
Zhenyu Wangc48044112009-12-17 14:48:43 +08002117 /* Try to make sure MCHBAR is enabled before poking at it */
2118 intel_setup_mchbar(dev);
2119
Eric Anholt673a3942008-07-30 12:06:12 -07002120 i915_gem_load(dev);
2121
Keith Packard398c9cb2008-07-30 13:03:43 -07002122 /* Init HWS */
2123 if (!I915_NEED_GFX_HWS(dev)) {
2124 ret = i915_init_phys_hws(dev);
2125 if (ret != 0)
Eric Anholt9c9fe1f2009-08-03 16:09:16 -07002126 goto out_workqueue_free;
Keith Packard398c9cb2008-07-30 13:03:43 -07002127 }
Eric Anholted4cb412008-07-29 12:10:39 -07002128
Jesse Barnes7648fa92010-05-20 14:28:11 -07002129 if (IS_PINEVIEW(dev))
2130 i915_pineview_get_mem_freq(dev);
2131 else if (IS_IRONLAKE(dev))
2132 i915_ironlake_get_mem_freq(dev);
Shaohua Li7662c8b2009-06-26 11:23:55 +08002133
Eric Anholted4cb412008-07-29 12:10:39 -07002134 /* On the 945G/GM, the chipset reports the MSI capability on the
2135 * integrated graphics even though the support isn't actually there
2136 * according to the published specs. It doesn't appear to function
2137 * correctly in testing on 945G.
2138 * This may be a side effect of MSI having been made available for PEG
2139 * and the registers being closely associated.
Keith Packardd1ed6292008-10-17 00:44:42 -07002140 *
2141 * According to chipset errata, on the 965GM, MSI interrupts may
Keith Packardb60678a2008-12-08 11:12:28 -08002142 * be lost or delayed, but we use them anyways to avoid
2143 * stuck interrupts on some machines.
Eric Anholted4cb412008-07-29 12:10:39 -07002144 */
Keith Packardb60678a2008-12-08 11:12:28 -08002145 if (!IS_I945G(dev) && !IS_I945GM(dev))
Eric Anholtd3e74d02008-11-03 14:46:17 -08002146 pci_enable_msi(dev->pdev);
Eric Anholted4cb412008-07-29 12:10:39 -07002147
2148 spin_lock_init(&dev_priv->user_irq_lock);
Jesse Barnes63eeaf32009-06-18 16:56:52 -07002149 spin_lock_init(&dev_priv->error_lock);
Chris Wilson9d34e5d2009-09-24 05:26:06 +01002150 dev_priv->trace_irq_seqno = 0;
Eric Anholted4cb412008-07-29 12:10:39 -07002151
Keith Packard52440212008-11-18 09:30:25 -08002152 ret = drm_vblank_init(dev, I915_NUM_PIPE);
2153
2154 if (ret) {
2155 (void) i915_driver_unload(dev);
2156 return ret;
2157 }
2158
Ben Gamari11ed50e2009-09-14 17:48:45 -04002159 /* Start out suspended */
2160 dev_priv->mm.suspended = 1;
2161
Zhenyu Wang3bad0782010-04-07 16:15:53 +08002162 intel_detect_pch(dev);
2163
Jesse Barnes79e53942008-11-07 14:24:08 -08002164 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
Jesse Barnes80824002009-09-10 15:28:06 -07002165 ret = i915_load_modeset_init(dev, prealloc_start,
2166 prealloc_size, agp_size);
Jesse Barnes79e53942008-11-07 14:24:08 -08002167 if (ret < 0) {
2168 DRM_ERROR("failed to init modeset\n");
Eric Anholt9c9fe1f2009-08-03 16:09:16 -07002169 goto out_workqueue_free;
Jesse Barnes79e53942008-11-07 14:24:08 -08002170 }
2171 }
2172
Matthew Garrett74a365b2009-03-19 21:35:39 +00002173 /* Must be done after probing outputs */
Zhao Yakui01c66882009-10-28 05:10:00 +00002174 intel_opregion_init(dev, 0);
Matthew Garrett74a365b2009-03-19 21:35:39 +00002175
Ben Gamarif65d9422009-09-14 17:48:44 -04002176 setup_timer(&dev_priv->hangcheck_timer, i915_hangcheck_elapsed,
2177 (unsigned long) dev);
Jesse Barnes7648fa92010-05-20 14:28:11 -07002178
2179 spin_lock(&mchdev_lock);
2180 i915_mch_dev = dev_priv;
2181 dev_priv->mchdev_lock = &mchdev_lock;
2182 spin_unlock(&mchdev_lock);
2183
Jesse Barnes79e53942008-11-07 14:24:08 -08002184 return 0;
2185
Eric Anholt9c9fe1f2009-08-03 16:09:16 -07002186out_workqueue_free:
2187 destroy_workqueue(dev_priv->wq);
Venkatesh Pallipadi66441072009-02-24 17:35:11 -08002188out_iomapfree:
2189 io_mapping_free(dev_priv->mm.gtt_mapping);
Jesse Barnes79e53942008-11-07 14:24:08 -08002190out_rmmap:
2191 iounmap(dev_priv->regs);
Dave Airlieec2a4c32009-08-04 11:43:41 +10002192put_bridge:
2193 pci_dev_put(dev_priv->bridge_dev);
Jesse Barnes79e53942008-11-07 14:24:08 -08002194free_priv:
Eric Anholt9a298b22009-03-24 12:23:04 -07002195 kfree(dev_priv);
Jesse Barnesba8bbcf2007-11-22 14:14:14 +10002196 return ret;
2197}
2198
2199int i915_driver_unload(struct drm_device *dev)
2200{
2201 struct drm_i915_private *dev_priv = dev->dev_private;
2202
Chris Wilson9df30792010-02-18 10:24:56 +00002203 i915_destroy_error_state(dev);
2204
Jesse Barnes7648fa92010-05-20 14:28:11 -07002205 spin_lock(&mchdev_lock);
2206 i915_mch_dev = NULL;
2207 spin_unlock(&mchdev_lock);
2208
Eric Anholt9c9fe1f2009-08-03 16:09:16 -07002209 destroy_workqueue(dev_priv->wq);
Ben Gamarif65d9422009-09-14 17:48:44 -04002210 del_timer_sync(&dev_priv->hangcheck_timer);
Eric Anholt9c9fe1f2009-08-03 16:09:16 -07002211
Eric Anholtab657db12009-01-23 12:57:47 -08002212 io_mapping_free(dev_priv->mm.gtt_mapping);
2213 if (dev_priv->mm.gtt_mtrr >= 0) {
2214 mtrr_del(dev_priv->mm.gtt_mtrr, dev->agp->base,
2215 dev->agp->agp_info.aper_size * 1024 * 1024);
2216 dev_priv->mm.gtt_mtrr = -1;
2217 }
2218
Jesse Barnes79e53942008-11-07 14:24:08 -08002219 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
Jesse Barnes3d8620c2010-03-26 11:07:21 -07002220 intel_modeset_cleanup(dev);
2221
Zhao Yakui6363ee62009-11-24 09:48:44 +08002222 /*
2223 * free the memory space allocated for the child device
2224 * config parsed from VBT
2225 */
2226 if (dev_priv->child_dev && dev_priv->child_dev_num) {
2227 kfree(dev_priv->child_dev);
2228 dev_priv->child_dev = NULL;
2229 dev_priv->child_dev_num = 0;
2230 }
Jesse Barnes79e53942008-11-07 14:24:08 -08002231 drm_irq_uninstall(dev);
Dave Airlie6a9ee8a2010-02-01 15:38:10 +10002232 vga_switcheroo_unregister_client(dev->pdev);
Dave Airlie28d52042009-09-21 14:33:58 +10002233 vga_client_register(dev->pdev, NULL, NULL, NULL);
Jesse Barnes79e53942008-11-07 14:24:08 -08002234 }
2235
Eric Anholted4cb412008-07-29 12:10:39 -07002236 if (dev->pdev->msi_enabled)
2237 pci_disable_msi(dev->pdev);
2238
Eric Anholt3043c602008-10-02 12:24:47 -07002239 if (dev_priv->regs != NULL)
2240 iounmap(dev_priv->regs);
Jesse Barnesba8bbcf2007-11-22 14:14:14 +10002241
Zhao Yakui01c66882009-10-28 05:10:00 +00002242 intel_opregion_free(dev, 0);
Matthew Garrett8ee1c3d2008-08-05 19:37:25 +01002243
Jesse Barnes79e53942008-11-07 14:24:08 -08002244 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
Dave Airlie71acb5e2008-12-30 20:31:46 +10002245 i915_gem_free_all_phys_object(dev);
2246
Jesse Barnes79e53942008-11-07 14:24:08 -08002247 mutex_lock(&dev->struct_mutex);
2248 i915_gem_cleanup_ringbuffer(dev);
2249 mutex_unlock(&dev->struct_mutex);
Jesse Barnes20bf3772010-04-21 11:39:22 -07002250 if (I915_HAS_FBC(dev) && i915_powersave)
2251 i915_cleanup_compression(dev);
Jesse Barnes79e53942008-11-07 14:24:08 -08002252 drm_mm_takedown(&dev_priv->vram);
2253 i915_gem_lastclose(dev);
Daniel Vetter02e792f2009-09-15 22:57:34 +02002254
2255 intel_cleanup_overlay(dev);
Jesse Barnes79e53942008-11-07 14:24:08 -08002256 }
2257
Zhenyu Wangc48044112009-12-17 14:48:43 +08002258 intel_teardown_mchbar(dev);
2259
Dave Airlieec2a4c32009-08-04 11:43:41 +10002260 pci_dev_put(dev_priv->bridge_dev);
Eric Anholt9a298b22009-03-24 12:23:04 -07002261 kfree(dev->dev_private);
Jesse Barnesba8bbcf2007-11-22 14:14:14 +10002262
Dave Airlie22eae942005-11-10 22:16:34 +11002263 return 0;
2264}
2265
Eric Anholt673a3942008-07-30 12:06:12 -07002266int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv)
2267{
2268 struct drm_i915_file_private *i915_file_priv;
2269
Zhao Yakui8a4c47f2009-07-20 13:48:04 +08002270 DRM_DEBUG_DRIVER("\n");
Eric Anholt673a3942008-07-30 12:06:12 -07002271 i915_file_priv = (struct drm_i915_file_private *)
Eric Anholt9a298b22009-03-24 12:23:04 -07002272 kmalloc(sizeof(*i915_file_priv), GFP_KERNEL);
Eric Anholt673a3942008-07-30 12:06:12 -07002273
2274 if (!i915_file_priv)
2275 return -ENOMEM;
2276
2277 file_priv->driver_priv = i915_file_priv;
2278
Eric Anholtb9624422009-06-03 07:27:35 +00002279 INIT_LIST_HEAD(&i915_file_priv->mm.request_list);
Eric Anholt673a3942008-07-30 12:06:12 -07002280
2281 return 0;
2282}
2283
Jesse Barnes79e53942008-11-07 14:24:08 -08002284/**
2285 * i915_driver_lastclose - clean up after all DRM clients have exited
2286 * @dev: DRM device
2287 *
2288 * Take care of cleaning up after all DRM clients have exited. In the
2289 * mode setting case, we want to restore the kernel's initial mode (just
2290 * in case the last client left us in a bad state).
2291 *
2292 * Additionally, in the non-mode setting case, we'll tear down the AGP
2293 * and DMA structures, since the kernel won't be using them, and clea
2294 * up any GEM state.
2295 */
Dave Airlie84b1fd12007-07-11 15:53:27 +10002296void i915_driver_lastclose(struct drm_device * dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002297{
Jesse Barnesba8bbcf2007-11-22 14:14:14 +10002298 drm_i915_private_t *dev_priv = dev->dev_private;
2299
Jesse Barnes79e53942008-11-07 14:24:08 -08002300 if (!dev_priv || drm_core_check_feature(dev, DRIVER_MODESET)) {
Dave Airlie785b93e2009-08-28 15:46:53 +10002301 drm_fb_helper_restore();
Dave Airlie6a9ee8a2010-02-01 15:38:10 +10002302 vga_switcheroo_process_delayed_switch();
Dave Airlie144a75f2008-03-30 07:53:58 +10002303 return;
Jesse Barnes79e53942008-11-07 14:24:08 -08002304 }
Dave Airlie144a75f2008-03-30 07:53:58 +10002305
Eric Anholt673a3942008-07-30 12:06:12 -07002306 i915_gem_lastclose(dev);
2307
Jesse Barnesba8bbcf2007-11-22 14:14:14 +10002308 if (dev_priv->agp_heap)
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002309 i915_mem_takedown(&(dev_priv->agp_heap));
Jesse Barnesba8bbcf2007-11-22 14:14:14 +10002310
Dave Airlieb5e89ed2005-09-25 14:28:13 +10002311 i915_dma_cleanup(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002312}
2313
Eric Anholt6c340ea2007-08-25 20:23:09 +10002314void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002315{
Jesse Barnesba8bbcf2007-11-22 14:14:14 +10002316 drm_i915_private_t *dev_priv = dev->dev_private;
Eric Anholtb9624422009-06-03 07:27:35 +00002317 i915_gem_release(dev, file_priv);
Jesse Barnes79e53942008-11-07 14:24:08 -08002318 if (!drm_core_check_feature(dev, DRIVER_MODESET))
2319 i915_mem_release(dev, file_priv, dev_priv->agp_heap);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002320}
2321
Eric Anholt673a3942008-07-30 12:06:12 -07002322void i915_driver_postclose(struct drm_device *dev, struct drm_file *file_priv)
2323{
2324 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
2325
Eric Anholt9a298b22009-03-24 12:23:04 -07002326 kfree(i915_file_priv);
Eric Anholt673a3942008-07-30 12:06:12 -07002327}
2328
Eric Anholtc153f452007-09-03 12:06:45 +10002329struct drm_ioctl_desc i915_ioctls[] = {
2330 DRM_IOCTL_DEF(DRM_I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2331 DRM_IOCTL_DEF(DRM_I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
2332 DRM_IOCTL_DEF(DRM_I915_FLIP, i915_flip_bufs, DRM_AUTH),
2333 DRM_IOCTL_DEF(DRM_I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
2334 DRM_IOCTL_DEF(DRM_I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
2335 DRM_IOCTL_DEF(DRM_I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
2336 DRM_IOCTL_DEF(DRM_I915_GETPARAM, i915_getparam, DRM_AUTH),
2337 DRM_IOCTL_DEF(DRM_I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2338 DRM_IOCTL_DEF(DRM_I915_ALLOC, i915_mem_alloc, DRM_AUTH),
2339 DRM_IOCTL_DEF(DRM_I915_FREE, i915_mem_free, DRM_AUTH),
2340 DRM_IOCTL_DEF(DRM_I915_INIT_HEAP, i915_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2341 DRM_IOCTL_DEF(DRM_I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
2342 DRM_IOCTL_DEF(DRM_I915_DESTROY_HEAP, i915_mem_destroy_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
2343 DRM_IOCTL_DEF(DRM_I915_SET_VBLANK_PIPE, i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
2344 DRM_IOCTL_DEF(DRM_I915_GET_VBLANK_PIPE, i915_vblank_pipe_get, DRM_AUTH ),
2345 DRM_IOCTL_DEF(DRM_I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
Matthias Hopf4b408932008-10-18 07:18:05 +10002346 DRM_IOCTL_DEF(DRM_I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
Eric Anholtf05dd2f2010-02-26 13:32:11 -08002347 DRM_IOCTL_DEF(DRM_I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2348 DRM_IOCTL_DEF(DRM_I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH|DRM_UNLOCKED),
2349 DRM_IOCTL_DEF(DRM_I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_UNLOCKED),
2350 DRM_IOCTL_DEF(DRM_I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
2351 DRM_IOCTL_DEF(DRM_I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
2352 DRM_IOCTL_DEF(DRM_I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED),
2353 DRM_IOCTL_DEF(DRM_I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_UNLOCKED),
2354 DRM_IOCTL_DEF(DRM_I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2355 DRM_IOCTL_DEF(DRM_I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2356 DRM_IOCTL_DEF(DRM_I915_GEM_CREATE, i915_gem_create_ioctl, DRM_UNLOCKED),
2357 DRM_IOCTL_DEF(DRM_I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED),
2358 DRM_IOCTL_DEF(DRM_I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED),
2359 DRM_IOCTL_DEF(DRM_I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_UNLOCKED),
2360 DRM_IOCTL_DEF(DRM_I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED),
2361 DRM_IOCTL_DEF(DRM_I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED),
2362 DRM_IOCTL_DEF(DRM_I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED),
2363 DRM_IOCTL_DEF(DRM_I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_UNLOCKED),
2364 DRM_IOCTL_DEF(DRM_I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_UNLOCKED),
2365 DRM_IOCTL_DEF(DRM_I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED),
2366 DRM_IOCTL_DEF(DRM_I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED),
2367 DRM_IOCTL_DEF(DRM_I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED),
2368 DRM_IOCTL_DEF(DRM_I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
2369 DRM_IOCTL_DEF(DRM_I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
Dave Airliec94f7022005-07-07 21:03:38 +10002370};
2371
2372int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
Dave Airliecda17382005-07-10 17:31:26 +10002373
2374/**
2375 * Determine if the device really is AGP or not.
2376 *
2377 * All Intel graphics chipsets are treated as AGP, even if they are really
2378 * PCI-e.
2379 *
2380 * \param dev The device to be tested.
2381 *
2382 * \returns
2383 * A value of 1 is always retured to indictate every i9x5 is AGP.
2384 */
Dave Airlie84b1fd12007-07-11 15:53:27 +10002385int i915_driver_device_is_agp(struct drm_device * dev)
Dave Airliecda17382005-07-10 17:31:26 +10002386{
2387 return 1;
2388}