Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved. |
Jack Morgenstein | 51a379d | 2008-07-25 10:32:52 -0700 | [diff] [blame] | 3 | * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved. |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 4 | * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved. |
| 5 | * |
| 6 | * This software is available to you under a choice of one of two |
| 7 | * licenses. You may choose to be licensed under the terms of the GNU |
| 8 | * General Public License (GPL) Version 2, available from the file |
| 9 | * COPYING in the main directory of this source tree, or the |
| 10 | * OpenIB.org BSD license below: |
| 11 | * |
| 12 | * Redistribution and use in source and binary forms, with or |
| 13 | * without modification, are permitted provided that the following |
| 14 | * conditions are met: |
| 15 | * |
| 16 | * - Redistributions of source code must retain the above |
| 17 | * copyright notice, this list of conditions and the following |
| 18 | * disclaimer. |
| 19 | * |
| 20 | * - Redistributions in binary form must reproduce the above |
| 21 | * copyright notice, this list of conditions and the following |
| 22 | * disclaimer in the documentation and/or other materials |
| 23 | * provided with the distribution. |
| 24 | * |
| 25 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
| 26 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| 27 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
| 28 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS |
| 29 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN |
| 30 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN |
| 31 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
| 32 | * SOFTWARE. |
| 33 | */ |
| 34 | |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 35 | #include <linux/etherdevice.h> |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 36 | #include <linux/mlx4/cmd.h> |
Paul Gortmaker | 9d9779e | 2011-07-03 15:21:01 -0400 | [diff] [blame] | 37 | #include <linux/module.h> |
Eli Cohen | c57e20dcf | 2009-09-24 11:03:03 -0700 | [diff] [blame] | 38 | #include <linux/cache.h> |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 39 | |
| 40 | #include "fw.h" |
| 41 | #include "icm.h" |
| 42 | |
Roland Dreier | fe40900 | 2007-06-07 23:24:36 -0700 | [diff] [blame] | 43 | enum { |
Roland Dreier | 5ae2a7a | 2007-06-18 08:15:02 -0700 | [diff] [blame] | 44 | MLX4_COMMAND_INTERFACE_MIN_REV = 2, |
| 45 | MLX4_COMMAND_INTERFACE_MAX_REV = 3, |
| 46 | MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS = 3, |
Roland Dreier | fe40900 | 2007-06-07 23:24:36 -0700 | [diff] [blame] | 47 | }; |
| 48 | |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 49 | extern void __buggy_use_of_MLX4_GET(void); |
| 50 | extern void __buggy_use_of_MLX4_PUT(void); |
| 51 | |
Rusty Russell | eb93992 | 2011-12-19 14:08:01 +0000 | [diff] [blame] | 52 | static bool enable_qos; |
Jack Morgenstein | 51f5f0e | 2008-07-22 14:19:37 -0700 | [diff] [blame] | 53 | module_param(enable_qos, bool, 0444); |
| 54 | MODULE_PARM_DESC(enable_qos, "Enable Quality of Service support in the HCA (default: off)"); |
| 55 | |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 56 | #define MLX4_GET(dest, source, offset) \ |
| 57 | do { \ |
| 58 | void *__p = (char *) (source) + (offset); \ |
| 59 | switch (sizeof (dest)) { \ |
| 60 | case 1: (dest) = *(u8 *) __p; break; \ |
| 61 | case 2: (dest) = be16_to_cpup(__p); break; \ |
| 62 | case 4: (dest) = be32_to_cpup(__p); break; \ |
| 63 | case 8: (dest) = be64_to_cpup(__p); break; \ |
| 64 | default: __buggy_use_of_MLX4_GET(); \ |
| 65 | } \ |
| 66 | } while (0) |
| 67 | |
| 68 | #define MLX4_PUT(dest, source, offset) \ |
| 69 | do { \ |
| 70 | void *__d = ((char *) (dest) + (offset)); \ |
| 71 | switch (sizeof(source)) { \ |
| 72 | case 1: *(u8 *) __d = (source); break; \ |
| 73 | case 2: *(__be16 *) __d = cpu_to_be16(source); break; \ |
| 74 | case 4: *(__be32 *) __d = cpu_to_be32(source); break; \ |
| 75 | case 8: *(__be64 *) __d = cpu_to_be64(source); break; \ |
| 76 | default: __buggy_use_of_MLX4_PUT(); \ |
| 77 | } \ |
| 78 | } while (0) |
| 79 | |
Or Gerlitz | 52eafc6 | 2011-06-15 14:41:42 +0000 | [diff] [blame] | 80 | static void dump_dev_cap_flags(struct mlx4_dev *dev, u64 flags) |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 81 | { |
| 82 | static const char *fname[] = { |
| 83 | [ 0] = "RC transport", |
| 84 | [ 1] = "UC transport", |
| 85 | [ 2] = "UD transport", |
Roland Dreier | ea98054 | 2007-10-09 19:59:13 -0700 | [diff] [blame] | 86 | [ 3] = "XRC transport", |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 87 | [ 4] = "reliable multicast", |
| 88 | [ 5] = "FCoIB support", |
| 89 | [ 6] = "SRQ support", |
| 90 | [ 7] = "IPoIB checksum offload", |
| 91 | [ 8] = "P_Key violation counter", |
| 92 | [ 9] = "Q_Key violation counter", |
| 93 | [10] = "VMM", |
Or Gerlitz | 4d531aa | 2013-04-07 03:44:06 +0000 | [diff] [blame] | 94 | [12] = "Dual Port Different Protocol (DPDP) support", |
Eli Cohen | 417608c | 2009-11-12 11:19:44 -0800 | [diff] [blame] | 95 | [15] = "Big LSO headers", |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 96 | [16] = "MW support", |
| 97 | [17] = "APM support", |
| 98 | [18] = "Atomic ops support", |
| 99 | [19] = "Raw multicast support", |
| 100 | [20] = "Address vector port checking support", |
| 101 | [21] = "UD multicast support", |
| 102 | [24] = "Demand paging support", |
Eli Cohen | 96dfa68 | 2010-10-20 21:57:02 -0700 | [diff] [blame] | 103 | [25] = "Router support", |
Or Gerlitz | ccf8632 | 2011-07-07 19:19:29 +0000 | [diff] [blame] | 104 | [30] = "IBoE support", |
| 105 | [32] = "Unicast loopback support", |
Yevgeny Petrilin | f3a9d1f | 2011-10-18 01:50:42 +0000 | [diff] [blame] | 106 | [34] = "FCS header control", |
Or Gerlitz | ccf8632 | 2011-07-07 19:19:29 +0000 | [diff] [blame] | 107 | [38] = "Wake On LAN support", |
| 108 | [40] = "UDP RSS support", |
| 109 | [41] = "Unicast VEP steering support", |
Or Gerlitz | f2a3f6a | 2011-06-15 14:47:14 +0000 | [diff] [blame] | 110 | [42] = "Multicast VEP steering support", |
| 111 | [48] = "Counters support", |
Or Gerlitz | 540b3a3 | 2013-04-07 03:44:07 +0000 | [diff] [blame] | 112 | [53] = "Port ETS Scheduler support", |
Or Gerlitz | 4d531aa | 2013-04-07 03:44:06 +0000 | [diff] [blame] | 113 | [55] = "Port link type sensing support", |
Jack Morgenstein | 00f5ce9 | 2012-06-19 11:21:40 +0300 | [diff] [blame] | 114 | [59] = "Port management change event support", |
Or Gerlitz | 08ff323 | 2012-10-21 14:59:24 +0000 | [diff] [blame] | 115 | [61] = "64 byte EQE support", |
| 116 | [62] = "64 byte CQE support", |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 117 | }; |
| 118 | int i; |
| 119 | |
| 120 | mlx4_dbg(dev, "DEV_CAP flags:\n"); |
Roland Dreier | 23c15c2 | 2007-05-19 08:51:57 -0700 | [diff] [blame] | 121 | for (i = 0; i < ARRAY_SIZE(fname); ++i) |
Or Gerlitz | 52eafc6 | 2011-06-15 14:41:42 +0000 | [diff] [blame] | 122 | if (fname[i] && (flags & (1LL << i))) |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 123 | mlx4_dbg(dev, " %s\n", fname[i]); |
| 124 | } |
| 125 | |
Shlomo Pongratz | b3416f4 | 2012-04-29 17:04:25 +0300 | [diff] [blame] | 126 | static void dump_dev_cap_flags2(struct mlx4_dev *dev, u64 flags) |
| 127 | { |
| 128 | static const char * const fname[] = { |
| 129 | [0] = "RSS support", |
| 130 | [1] = "RSS Toeplitz Hash Function support", |
Hadar Hen Zion | 0ff1fb6 | 2012-07-05 04:03:46 +0000 | [diff] [blame] | 131 | [2] = "RSS XOR Hash Function support", |
Or Gerlitz | 56cb456 | 2014-03-12 17:16:30 +0200 | [diff] [blame] | 132 | [3] = "Device managed flow steering support", |
Eugenia Emantayev | d998735 | 2013-04-23 06:06:47 +0000 | [diff] [blame] | 133 | [4] = "Automatic MAC reassignment support", |
Or Gerlitz | 4e8cf5b | 2013-05-08 22:22:34 +0000 | [diff] [blame] | 134 | [5] = "Time stamping support", |
| 135 | [6] = "VST (control vlan insertion/stripping) support", |
Jack Morgenstein | b01978c | 2013-06-27 19:05:21 +0300 | [diff] [blame] | 136 | [7] = "FSM (MAC anti-spoofing) support", |
Or Gerlitz | 7ffdf72 | 2013-12-23 16:09:43 +0200 | [diff] [blame] | 137 | [8] = "Dynamic QP updates support", |
Or Gerlitz | 56cb456 | 2014-03-12 17:16:30 +0200 | [diff] [blame] | 138 | [9] = "Device managed flow steering IPoIB support", |
Jack Morgenstein | 114840c | 2014-06-01 11:53:50 +0300 | [diff] [blame] | 139 | [10] = "TCP/IP offloads/flow-steering for VXLAN support", |
Ido Shamay | 77507aa | 2014-09-18 11:50:59 +0300 | [diff] [blame^] | 140 | [11] = "MAD DEMUX (Secure-Host) support", |
| 141 | [12] = "Large cache line (>64B) CQE stride support", |
| 142 | [13] = "Large cache line (>64B) EQE stride support" |
Shlomo Pongratz | b3416f4 | 2012-04-29 17:04:25 +0300 | [diff] [blame] | 143 | }; |
| 144 | int i; |
| 145 | |
| 146 | for (i = 0; i < ARRAY_SIZE(fname); ++i) |
| 147 | if (fname[i] && (flags & (1LL << i))) |
| 148 | mlx4_dbg(dev, " %s\n", fname[i]); |
| 149 | } |
| 150 | |
Vladimir Sokolovsky | 2d92865 | 2008-07-14 23:48:53 -0700 | [diff] [blame] | 151 | int mlx4_MOD_STAT_CFG(struct mlx4_dev *dev, struct mlx4_mod_stat_cfg *cfg) |
| 152 | { |
| 153 | struct mlx4_cmd_mailbox *mailbox; |
| 154 | u32 *inbox; |
| 155 | int err = 0; |
| 156 | |
| 157 | #define MOD_STAT_CFG_IN_SIZE 0x100 |
| 158 | |
| 159 | #define MOD_STAT_CFG_PG_SZ_M_OFFSET 0x002 |
| 160 | #define MOD_STAT_CFG_PG_SZ_OFFSET 0x003 |
| 161 | |
| 162 | mailbox = mlx4_alloc_cmd_mailbox(dev); |
| 163 | if (IS_ERR(mailbox)) |
| 164 | return PTR_ERR(mailbox); |
| 165 | inbox = mailbox->buf; |
| 166 | |
Vladimir Sokolovsky | 2d92865 | 2008-07-14 23:48:53 -0700 | [diff] [blame] | 167 | MLX4_PUT(inbox, cfg->log_pg_sz, MOD_STAT_CFG_PG_SZ_OFFSET); |
| 168 | MLX4_PUT(inbox, cfg->log_pg_sz_m, MOD_STAT_CFG_PG_SZ_M_OFFSET); |
| 169 | |
| 170 | err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_MOD_STAT_CFG, |
Jack Morgenstein | f9baff5 | 2011-12-13 04:10:51 +0000 | [diff] [blame] | 171 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); |
Vladimir Sokolovsky | 2d92865 | 2008-07-14 23:48:53 -0700 | [diff] [blame] | 172 | |
| 173 | mlx4_free_cmd_mailbox(dev, mailbox); |
| 174 | return err; |
| 175 | } |
| 176 | |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 177 | int mlx4_QUERY_FUNC_CAP_wrapper(struct mlx4_dev *dev, int slave, |
| 178 | struct mlx4_vhcr *vhcr, |
| 179 | struct mlx4_cmd_mailbox *inbox, |
| 180 | struct mlx4_cmd_mailbox *outbox, |
| 181 | struct mlx4_cmd_info *cmd) |
| 182 | { |
Jack Morgenstein | 5a0d0a6 | 2013-11-03 10:03:23 +0200 | [diff] [blame] | 183 | struct mlx4_priv *priv = mlx4_priv(dev); |
Jack Morgenstein | 99ec41d | 2014-05-29 16:31:03 +0300 | [diff] [blame] | 184 | u8 field, port; |
| 185 | u32 size, proxy_qp, qkey; |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 186 | int err = 0; |
| 187 | |
| 188 | #define QUERY_FUNC_CAP_FLAGS_OFFSET 0x0 |
| 189 | #define QUERY_FUNC_CAP_NUM_PORTS_OFFSET 0x1 |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 190 | #define QUERY_FUNC_CAP_PF_BHVR_OFFSET 0x4 |
Jack Morgenstein | 105c320 | 2012-06-19 11:21:43 +0300 | [diff] [blame] | 191 | #define QUERY_FUNC_CAP_FMR_OFFSET 0x8 |
Jack Morgenstein | eb456a6 | 2013-11-03 10:03:24 +0200 | [diff] [blame] | 192 | #define QUERY_FUNC_CAP_QP_QUOTA_OFFSET_DEP 0x10 |
| 193 | #define QUERY_FUNC_CAP_CQ_QUOTA_OFFSET_DEP 0x14 |
| 194 | #define QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET_DEP 0x18 |
| 195 | #define QUERY_FUNC_CAP_MPT_QUOTA_OFFSET_DEP 0x20 |
| 196 | #define QUERY_FUNC_CAP_MTT_QUOTA_OFFSET_DEP 0x24 |
| 197 | #define QUERY_FUNC_CAP_MCG_QUOTA_OFFSET_DEP 0x28 |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 198 | #define QUERY_FUNC_CAP_MAX_EQ_OFFSET 0x2c |
Roland Dreier | 69612b9 | 2012-09-23 09:18:24 -0700 | [diff] [blame] | 199 | #define QUERY_FUNC_CAP_RESERVED_EQ_OFFSET 0x30 |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 200 | |
Jack Morgenstein | eb456a6 | 2013-11-03 10:03:24 +0200 | [diff] [blame] | 201 | #define QUERY_FUNC_CAP_QP_QUOTA_OFFSET 0x50 |
| 202 | #define QUERY_FUNC_CAP_CQ_QUOTA_OFFSET 0x54 |
| 203 | #define QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET 0x58 |
| 204 | #define QUERY_FUNC_CAP_MPT_QUOTA_OFFSET 0x60 |
| 205 | #define QUERY_FUNC_CAP_MTT_QUOTA_OFFSET 0x64 |
| 206 | #define QUERY_FUNC_CAP_MCG_QUOTA_OFFSET 0x68 |
| 207 | |
Jack Morgenstein | 105c320 | 2012-06-19 11:21:43 +0300 | [diff] [blame] | 208 | #define QUERY_FUNC_CAP_FMR_FLAG 0x80 |
| 209 | #define QUERY_FUNC_CAP_FLAG_RDMA 0x40 |
| 210 | #define QUERY_FUNC_CAP_FLAG_ETH 0x80 |
Jack Morgenstein | eb456a6 | 2013-11-03 10:03:24 +0200 | [diff] [blame] | 211 | #define QUERY_FUNC_CAP_FLAG_QUOTAS 0x10 |
Jack Morgenstein | 105c320 | 2012-06-19 11:21:43 +0300 | [diff] [blame] | 212 | |
| 213 | /* when opcode modifier = 1 */ |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 214 | #define QUERY_FUNC_CAP_PHYS_PORT_OFFSET 0x3 |
Jack Morgenstein | 99ec41d | 2014-05-29 16:31:03 +0300 | [diff] [blame] | 215 | #define QUERY_FUNC_CAP_PRIV_VF_QKEY_OFFSET 0x4 |
Hadar Hen Zion | 73e74ab | 2013-12-19 21:20:10 +0200 | [diff] [blame] | 216 | #define QUERY_FUNC_CAP_FLAGS0_OFFSET 0x8 |
| 217 | #define QUERY_FUNC_CAP_FLAGS1_OFFSET 0xc |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 218 | |
Jack Morgenstein | 47605df | 2012-08-03 08:40:57 +0000 | [diff] [blame] | 219 | #define QUERY_FUNC_CAP_QP0_TUNNEL 0x10 |
| 220 | #define QUERY_FUNC_CAP_QP0_PROXY 0x14 |
| 221 | #define QUERY_FUNC_CAP_QP1_TUNNEL 0x18 |
| 222 | #define QUERY_FUNC_CAP_QP1_PROXY 0x1c |
Hadar Hen Zion | 8e1a28e | 2013-12-19 21:20:12 +0200 | [diff] [blame] | 223 | #define QUERY_FUNC_CAP_PHYS_PORT_ID 0x28 |
Jack Morgenstein | 47605df | 2012-08-03 08:40:57 +0000 | [diff] [blame] | 224 | |
Hadar Hen Zion | 73e74ab | 2013-12-19 21:20:10 +0200 | [diff] [blame] | 225 | #define QUERY_FUNC_CAP_FLAGS1_FORCE_MAC 0x40 |
| 226 | #define QUERY_FUNC_CAP_FLAGS1_FORCE_VLAN 0x80 |
Hadar Hen Zion | eb17711 | 2013-12-19 21:20:11 +0200 | [diff] [blame] | 227 | #define QUERY_FUNC_CAP_FLAGS1_NIC_INFO 0x10 |
Jack Morgenstein | 99ec41d | 2014-05-29 16:31:03 +0300 | [diff] [blame] | 228 | #define QUERY_FUNC_CAP_VF_ENABLE_QP0 0x08 |
Jack Morgenstein | 105c320 | 2012-06-19 11:21:43 +0300 | [diff] [blame] | 229 | |
Hadar Hen Zion | 73e74ab | 2013-12-19 21:20:10 +0200 | [diff] [blame] | 230 | #define QUERY_FUNC_CAP_FLAGS0_FORCE_PHY_WQE_GID 0x80 |
Jack Morgenstein | 105c320 | 2012-06-19 11:21:43 +0300 | [diff] [blame] | 231 | |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 232 | if (vhcr->op_modifier == 1) { |
Matan Barak | 449fc48 | 2014-03-19 18:11:52 +0200 | [diff] [blame] | 233 | struct mlx4_active_ports actv_ports = |
| 234 | mlx4_get_active_ports(dev, slave); |
| 235 | int converted_port = mlx4_slave_convert_port( |
| 236 | dev, slave, vhcr->in_modifier); |
| 237 | |
| 238 | if (converted_port < 0) |
| 239 | return -EINVAL; |
| 240 | |
| 241 | vhcr->in_modifier = converted_port; |
Matan Barak | 449fc48 | 2014-03-19 18:11:52 +0200 | [diff] [blame] | 242 | /* phys-port = logical-port */ |
| 243 | field = vhcr->in_modifier - |
| 244 | find_first_bit(actv_ports.ports, dev->caps.num_ports); |
Jack Morgenstein | 47605df | 2012-08-03 08:40:57 +0000 | [diff] [blame] | 245 | MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_PHYS_PORT_OFFSET); |
| 246 | |
Jack Morgenstein | 99ec41d | 2014-05-29 16:31:03 +0300 | [diff] [blame] | 247 | port = vhcr->in_modifier; |
| 248 | proxy_qp = dev->phys_caps.base_proxy_sqpn + 8 * slave + port - 1; |
| 249 | |
| 250 | /* Set nic_info bit to mark new fields support */ |
| 251 | field = QUERY_FUNC_CAP_FLAGS1_NIC_INFO; |
| 252 | |
| 253 | if (mlx4_vf_smi_enabled(dev, slave, port) && |
| 254 | !mlx4_get_parav_qkey(dev, proxy_qp, &qkey)) { |
| 255 | field |= QUERY_FUNC_CAP_VF_ENABLE_QP0; |
| 256 | MLX4_PUT(outbox->buf, qkey, |
| 257 | QUERY_FUNC_CAP_PRIV_VF_QKEY_OFFSET); |
| 258 | } |
| 259 | MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FLAGS1_OFFSET); |
| 260 | |
Jack Morgenstein | 47605df | 2012-08-03 08:40:57 +0000 | [diff] [blame] | 261 | /* size is now the QP number */ |
Jack Morgenstein | 99ec41d | 2014-05-29 16:31:03 +0300 | [diff] [blame] | 262 | size = dev->phys_caps.base_tunnel_sqpn + 8 * slave + port - 1; |
Jack Morgenstein | 47605df | 2012-08-03 08:40:57 +0000 | [diff] [blame] | 263 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP0_TUNNEL); |
| 264 | |
| 265 | size += 2; |
| 266 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP1_TUNNEL); |
| 267 | |
Jack Morgenstein | 99ec41d | 2014-05-29 16:31:03 +0300 | [diff] [blame] | 268 | MLX4_PUT(outbox->buf, proxy_qp, QUERY_FUNC_CAP_QP0_PROXY); |
| 269 | proxy_qp += 2; |
| 270 | MLX4_PUT(outbox->buf, proxy_qp, QUERY_FUNC_CAP_QP1_PROXY); |
Jack Morgenstein | 47605df | 2012-08-03 08:40:57 +0000 | [diff] [blame] | 271 | |
Hadar Hen Zion | 8e1a28e | 2013-12-19 21:20:12 +0200 | [diff] [blame] | 272 | MLX4_PUT(outbox->buf, dev->caps.phys_port_id[vhcr->in_modifier], |
| 273 | QUERY_FUNC_CAP_PHYS_PORT_ID); |
| 274 | |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 275 | } else if (vhcr->op_modifier == 0) { |
Matan Barak | 449fc48 | 2014-03-19 18:11:52 +0200 | [diff] [blame] | 276 | struct mlx4_active_ports actv_ports = |
| 277 | mlx4_get_active_ports(dev, slave); |
Jack Morgenstein | eb456a6 | 2013-11-03 10:03:24 +0200 | [diff] [blame] | 278 | /* enable rdma and ethernet interfaces, and new quota locations */ |
| 279 | field = (QUERY_FUNC_CAP_FLAG_ETH | QUERY_FUNC_CAP_FLAG_RDMA | |
| 280 | QUERY_FUNC_CAP_FLAG_QUOTAS); |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 281 | MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FLAGS_OFFSET); |
| 282 | |
Matan Barak | 449fc48 | 2014-03-19 18:11:52 +0200 | [diff] [blame] | 283 | field = min( |
| 284 | bitmap_weight(actv_ports.ports, dev->caps.num_ports), |
| 285 | dev->caps.num_ports); |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 286 | MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_NUM_PORTS_OFFSET); |
| 287 | |
Or Gerlitz | 08ff323 | 2012-10-21 14:59:24 +0000 | [diff] [blame] | 288 | size = dev->caps.function_caps; /* set PF behaviours */ |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 289 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_PF_BHVR_OFFSET); |
| 290 | |
Jack Morgenstein | 105c320 | 2012-06-19 11:21:43 +0300 | [diff] [blame] | 291 | field = 0; /* protected FMR support not available as yet */ |
| 292 | MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FMR_OFFSET); |
| 293 | |
Jack Morgenstein | 5a0d0a6 | 2013-11-03 10:03:23 +0200 | [diff] [blame] | 294 | size = priv->mfunc.master.res_tracker.res_alloc[RES_QP].quota[slave]; |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 295 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP_QUOTA_OFFSET); |
Jack Morgenstein | eb456a6 | 2013-11-03 10:03:24 +0200 | [diff] [blame] | 296 | size = dev->caps.num_qps; |
| 297 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP_QUOTA_OFFSET_DEP); |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 298 | |
Jack Morgenstein | 5a0d0a6 | 2013-11-03 10:03:23 +0200 | [diff] [blame] | 299 | size = priv->mfunc.master.res_tracker.res_alloc[RES_SRQ].quota[slave]; |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 300 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET); |
Jack Morgenstein | eb456a6 | 2013-11-03 10:03:24 +0200 | [diff] [blame] | 301 | size = dev->caps.num_srqs; |
| 302 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET_DEP); |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 303 | |
Jack Morgenstein | 5a0d0a6 | 2013-11-03 10:03:23 +0200 | [diff] [blame] | 304 | size = priv->mfunc.master.res_tracker.res_alloc[RES_CQ].quota[slave]; |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 305 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET); |
Jack Morgenstein | eb456a6 | 2013-11-03 10:03:24 +0200 | [diff] [blame] | 306 | size = dev->caps.num_cqs; |
| 307 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET_DEP); |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 308 | |
| 309 | size = dev->caps.num_eqs; |
| 310 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MAX_EQ_OFFSET); |
| 311 | |
| 312 | size = dev->caps.reserved_eqs; |
| 313 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET); |
| 314 | |
Jack Morgenstein | 5a0d0a6 | 2013-11-03 10:03:23 +0200 | [diff] [blame] | 315 | size = priv->mfunc.master.res_tracker.res_alloc[RES_MPT].quota[slave]; |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 316 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET); |
Jack Morgenstein | eb456a6 | 2013-11-03 10:03:24 +0200 | [diff] [blame] | 317 | size = dev->caps.num_mpts; |
| 318 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET_DEP); |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 319 | |
Jack Morgenstein | 5a0d0a6 | 2013-11-03 10:03:23 +0200 | [diff] [blame] | 320 | size = priv->mfunc.master.res_tracker.res_alloc[RES_MTT].quota[slave]; |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 321 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET); |
Jack Morgenstein | eb456a6 | 2013-11-03 10:03:24 +0200 | [diff] [blame] | 322 | size = dev->caps.num_mtts; |
| 323 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET_DEP); |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 324 | |
| 325 | size = dev->caps.num_mgms + dev->caps.num_amgms; |
| 326 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET); |
Jack Morgenstein | eb456a6 | 2013-11-03 10:03:24 +0200 | [diff] [blame] | 327 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET_DEP); |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 328 | |
| 329 | } else |
| 330 | err = -EINVAL; |
| 331 | |
| 332 | return err; |
| 333 | } |
| 334 | |
Jack Morgenstein | 47605df | 2012-08-03 08:40:57 +0000 | [diff] [blame] | 335 | int mlx4_QUERY_FUNC_CAP(struct mlx4_dev *dev, u32 gen_or_port, |
| 336 | struct mlx4_func_cap *func_cap) |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 337 | { |
| 338 | struct mlx4_cmd_mailbox *mailbox; |
| 339 | u32 *outbox; |
Jack Morgenstein | 47605df | 2012-08-03 08:40:57 +0000 | [diff] [blame] | 340 | u8 field, op_modifier; |
Jack Morgenstein | 99ec41d | 2014-05-29 16:31:03 +0300 | [diff] [blame] | 341 | u32 size, qkey; |
Jack Morgenstein | eb456a6 | 2013-11-03 10:03:24 +0200 | [diff] [blame] | 342 | int err = 0, quotas = 0; |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 343 | |
Jack Morgenstein | 47605df | 2012-08-03 08:40:57 +0000 | [diff] [blame] | 344 | op_modifier = !!gen_or_port; /* 0 = general, 1 = logical port */ |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 345 | |
| 346 | mailbox = mlx4_alloc_cmd_mailbox(dev); |
| 347 | if (IS_ERR(mailbox)) |
| 348 | return PTR_ERR(mailbox); |
| 349 | |
Jack Morgenstein | 47605df | 2012-08-03 08:40:57 +0000 | [diff] [blame] | 350 | err = mlx4_cmd_box(dev, 0, mailbox->dma, gen_or_port, op_modifier, |
| 351 | MLX4_CMD_QUERY_FUNC_CAP, |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 352 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED); |
| 353 | if (err) |
| 354 | goto out; |
| 355 | |
| 356 | outbox = mailbox->buf; |
| 357 | |
Jack Morgenstein | 47605df | 2012-08-03 08:40:57 +0000 | [diff] [blame] | 358 | if (!op_modifier) { |
| 359 | MLX4_GET(field, outbox, QUERY_FUNC_CAP_FLAGS_OFFSET); |
| 360 | if (!(field & (QUERY_FUNC_CAP_FLAG_ETH | QUERY_FUNC_CAP_FLAG_RDMA))) { |
| 361 | mlx4_err(dev, "The host supports neither eth nor rdma interfaces\n"); |
| 362 | err = -EPROTONOSUPPORT; |
| 363 | goto out; |
| 364 | } |
| 365 | func_cap->flags = field; |
Jack Morgenstein | eb456a6 | 2013-11-03 10:03:24 +0200 | [diff] [blame] | 366 | quotas = !!(func_cap->flags & QUERY_FUNC_CAP_FLAG_QUOTAS); |
Jack Morgenstein | 47605df | 2012-08-03 08:40:57 +0000 | [diff] [blame] | 367 | |
| 368 | MLX4_GET(field, outbox, QUERY_FUNC_CAP_NUM_PORTS_OFFSET); |
| 369 | func_cap->num_ports = field; |
| 370 | |
| 371 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_PF_BHVR_OFFSET); |
| 372 | func_cap->pf_context_behaviour = size; |
| 373 | |
Jack Morgenstein | eb456a6 | 2013-11-03 10:03:24 +0200 | [diff] [blame] | 374 | if (quotas) { |
| 375 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP_QUOTA_OFFSET); |
| 376 | func_cap->qp_quota = size & 0xFFFFFF; |
Jack Morgenstein | 47605df | 2012-08-03 08:40:57 +0000 | [diff] [blame] | 377 | |
Jack Morgenstein | eb456a6 | 2013-11-03 10:03:24 +0200 | [diff] [blame] | 378 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET); |
| 379 | func_cap->srq_quota = size & 0xFFFFFF; |
Jack Morgenstein | 47605df | 2012-08-03 08:40:57 +0000 | [diff] [blame] | 380 | |
Jack Morgenstein | eb456a6 | 2013-11-03 10:03:24 +0200 | [diff] [blame] | 381 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET); |
| 382 | func_cap->cq_quota = size & 0xFFFFFF; |
Jack Morgenstein | 47605df | 2012-08-03 08:40:57 +0000 | [diff] [blame] | 383 | |
Jack Morgenstein | eb456a6 | 2013-11-03 10:03:24 +0200 | [diff] [blame] | 384 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET); |
| 385 | func_cap->mpt_quota = size & 0xFFFFFF; |
| 386 | |
| 387 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET); |
| 388 | func_cap->mtt_quota = size & 0xFFFFFF; |
| 389 | |
| 390 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET); |
| 391 | func_cap->mcg_quota = size & 0xFFFFFF; |
| 392 | |
| 393 | } else { |
| 394 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP_QUOTA_OFFSET_DEP); |
| 395 | func_cap->qp_quota = size & 0xFFFFFF; |
| 396 | |
| 397 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET_DEP); |
| 398 | func_cap->srq_quota = size & 0xFFFFFF; |
| 399 | |
| 400 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET_DEP); |
| 401 | func_cap->cq_quota = size & 0xFFFFFF; |
| 402 | |
| 403 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET_DEP); |
| 404 | func_cap->mpt_quota = size & 0xFFFFFF; |
| 405 | |
| 406 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET_DEP); |
| 407 | func_cap->mtt_quota = size & 0xFFFFFF; |
| 408 | |
| 409 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET_DEP); |
| 410 | func_cap->mcg_quota = size & 0xFFFFFF; |
| 411 | } |
Jack Morgenstein | 47605df | 2012-08-03 08:40:57 +0000 | [diff] [blame] | 412 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_MAX_EQ_OFFSET); |
| 413 | func_cap->max_eq = size & 0xFFFFFF; |
| 414 | |
| 415 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET); |
| 416 | func_cap->reserved_eq = size & 0xFFFFFF; |
| 417 | |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 418 | goto out; |
| 419 | } |
| 420 | |
Jack Morgenstein | 47605df | 2012-08-03 08:40:57 +0000 | [diff] [blame] | 421 | /* logical port query */ |
| 422 | if (gen_or_port > dev->caps.num_ports) { |
| 423 | err = -EINVAL; |
| 424 | goto out; |
| 425 | } |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 426 | |
Hadar Hen Zion | eb17711 | 2013-12-19 21:20:11 +0200 | [diff] [blame] | 427 | MLX4_GET(func_cap->flags1, outbox, QUERY_FUNC_CAP_FLAGS1_OFFSET); |
Jack Morgenstein | 47605df | 2012-08-03 08:40:57 +0000 | [diff] [blame] | 428 | if (dev->caps.port_type[gen_or_port] == MLX4_PORT_TYPE_ETH) { |
Jack Morgenstein | bc82878 | 2014-05-29 16:31:00 +0300 | [diff] [blame] | 429 | if (func_cap->flags1 & QUERY_FUNC_CAP_FLAGS1_FORCE_VLAN) { |
Jack Morgenstein | 47605df | 2012-08-03 08:40:57 +0000 | [diff] [blame] | 430 | mlx4_err(dev, "VLAN is enforced on this port\n"); |
| 431 | err = -EPROTONOSUPPORT; |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 432 | goto out; |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 433 | } |
| 434 | |
Hadar Hen Zion | eb17711 | 2013-12-19 21:20:11 +0200 | [diff] [blame] | 435 | if (func_cap->flags1 & QUERY_FUNC_CAP_FLAGS1_FORCE_MAC) { |
Jack Morgenstein | 47605df | 2012-08-03 08:40:57 +0000 | [diff] [blame] | 436 | mlx4_err(dev, "Force mac is enabled on this port\n"); |
| 437 | err = -EPROTONOSUPPORT; |
| 438 | goto out; |
| 439 | } |
| 440 | } else if (dev->caps.port_type[gen_or_port] == MLX4_PORT_TYPE_IB) { |
Hadar Hen Zion | 73e74ab | 2013-12-19 21:20:10 +0200 | [diff] [blame] | 441 | MLX4_GET(field, outbox, QUERY_FUNC_CAP_FLAGS0_OFFSET); |
| 442 | if (field & QUERY_FUNC_CAP_FLAGS0_FORCE_PHY_WQE_GID) { |
Joe Perches | 1a91de2 | 2014-05-07 12:52:57 -0700 | [diff] [blame] | 443 | mlx4_err(dev, "phy_wqe_gid is enforced on this ib port\n"); |
Jack Morgenstein | 47605df | 2012-08-03 08:40:57 +0000 | [diff] [blame] | 444 | err = -EPROTONOSUPPORT; |
| 445 | goto out; |
| 446 | } |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 447 | } |
| 448 | |
Jack Morgenstein | 47605df | 2012-08-03 08:40:57 +0000 | [diff] [blame] | 449 | MLX4_GET(field, outbox, QUERY_FUNC_CAP_PHYS_PORT_OFFSET); |
| 450 | func_cap->physical_port = field; |
| 451 | if (func_cap->physical_port != gen_or_port) { |
| 452 | err = -ENOSYS; |
| 453 | goto out; |
| 454 | } |
| 455 | |
Jack Morgenstein | 99ec41d | 2014-05-29 16:31:03 +0300 | [diff] [blame] | 456 | if (func_cap->flags1 & QUERY_FUNC_CAP_VF_ENABLE_QP0) { |
| 457 | MLX4_GET(qkey, outbox, QUERY_FUNC_CAP_PRIV_VF_QKEY_OFFSET); |
| 458 | func_cap->qp0_qkey = qkey; |
| 459 | } else { |
| 460 | func_cap->qp0_qkey = 0; |
| 461 | } |
| 462 | |
Jack Morgenstein | 47605df | 2012-08-03 08:40:57 +0000 | [diff] [blame] | 463 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP0_TUNNEL); |
| 464 | func_cap->qp0_tunnel_qpn = size & 0xFFFFFF; |
| 465 | |
| 466 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP0_PROXY); |
| 467 | func_cap->qp0_proxy_qpn = size & 0xFFFFFF; |
| 468 | |
| 469 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP1_TUNNEL); |
| 470 | func_cap->qp1_tunnel_qpn = size & 0xFFFFFF; |
| 471 | |
| 472 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP1_PROXY); |
| 473 | func_cap->qp1_proxy_qpn = size & 0xFFFFFF; |
| 474 | |
Hadar Hen Zion | 8e1a28e | 2013-12-19 21:20:12 +0200 | [diff] [blame] | 475 | if (func_cap->flags1 & QUERY_FUNC_CAP_FLAGS1_NIC_INFO) |
| 476 | MLX4_GET(func_cap->phys_port_id, outbox, |
| 477 | QUERY_FUNC_CAP_PHYS_PORT_ID); |
| 478 | |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 479 | /* All other resources are allocated by the master, but we still report |
| 480 | * 'num' and 'reserved' capabilities as follows: |
| 481 | * - num remains the maximum resource index |
| 482 | * - 'num - reserved' is the total available objects of a resource, but |
| 483 | * resource indices may be less than 'reserved' |
| 484 | * TODO: set per-resource quotas */ |
| 485 | |
| 486 | out: |
| 487 | mlx4_free_cmd_mailbox(dev, mailbox); |
| 488 | |
| 489 | return err; |
| 490 | } |
| 491 | |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 492 | int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap) |
| 493 | { |
| 494 | struct mlx4_cmd_mailbox *mailbox; |
| 495 | u32 *outbox; |
| 496 | u8 field; |
Or Gerlitz | ccf8632 | 2011-07-07 19:19:29 +0000 | [diff] [blame] | 497 | u32 field32, flags, ext_flags; |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 498 | u16 size; |
| 499 | u16 stat_rate; |
| 500 | int err; |
Roland Dreier | 5ae2a7a | 2007-06-18 08:15:02 -0700 | [diff] [blame] | 501 | int i; |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 502 | |
| 503 | #define QUERY_DEV_CAP_OUT_SIZE 0x100 |
| 504 | #define QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET 0x10 |
| 505 | #define QUERY_DEV_CAP_MAX_QP_SZ_OFFSET 0x11 |
| 506 | #define QUERY_DEV_CAP_RSVD_QP_OFFSET 0x12 |
| 507 | #define QUERY_DEV_CAP_MAX_QP_OFFSET 0x13 |
| 508 | #define QUERY_DEV_CAP_RSVD_SRQ_OFFSET 0x14 |
| 509 | #define QUERY_DEV_CAP_MAX_SRQ_OFFSET 0x15 |
| 510 | #define QUERY_DEV_CAP_RSVD_EEC_OFFSET 0x16 |
| 511 | #define QUERY_DEV_CAP_MAX_EEC_OFFSET 0x17 |
| 512 | #define QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET 0x19 |
| 513 | #define QUERY_DEV_CAP_RSVD_CQ_OFFSET 0x1a |
| 514 | #define QUERY_DEV_CAP_MAX_CQ_OFFSET 0x1b |
| 515 | #define QUERY_DEV_CAP_MAX_MPT_OFFSET 0x1d |
| 516 | #define QUERY_DEV_CAP_RSVD_EQ_OFFSET 0x1e |
| 517 | #define QUERY_DEV_CAP_MAX_EQ_OFFSET 0x1f |
| 518 | #define QUERY_DEV_CAP_RSVD_MTT_OFFSET 0x20 |
| 519 | #define QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET 0x21 |
| 520 | #define QUERY_DEV_CAP_RSVD_MRW_OFFSET 0x22 |
| 521 | #define QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET 0x23 |
| 522 | #define QUERY_DEV_CAP_MAX_AV_OFFSET 0x27 |
| 523 | #define QUERY_DEV_CAP_MAX_REQ_QP_OFFSET 0x29 |
| 524 | #define QUERY_DEV_CAP_MAX_RES_QP_OFFSET 0x2b |
Eli Cohen | b832be1 | 2008-04-16 21:09:27 -0700 | [diff] [blame] | 525 | #define QUERY_DEV_CAP_MAX_GSO_OFFSET 0x2d |
Shlomo Pongratz | b3416f4 | 2012-04-29 17:04:25 +0300 | [diff] [blame] | 526 | #define QUERY_DEV_CAP_RSS_OFFSET 0x2e |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 527 | #define QUERY_DEV_CAP_MAX_RDMA_OFFSET 0x2f |
| 528 | #define QUERY_DEV_CAP_RSZ_SRQ_OFFSET 0x33 |
| 529 | #define QUERY_DEV_CAP_ACK_DELAY_OFFSET 0x35 |
| 530 | #define QUERY_DEV_CAP_MTU_WIDTH_OFFSET 0x36 |
| 531 | #define QUERY_DEV_CAP_VL_PORT_OFFSET 0x37 |
Dotan Barak | 149983af | 2007-06-26 15:55:28 +0300 | [diff] [blame] | 532 | #define QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET 0x38 |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 533 | #define QUERY_DEV_CAP_MAX_GID_OFFSET 0x3b |
| 534 | #define QUERY_DEV_CAP_RATE_SUPPORT_OFFSET 0x3c |
Eugenia Emantayev | d998735 | 2013-04-23 06:06:47 +0000 | [diff] [blame] | 535 | #define QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET 0x3e |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 536 | #define QUERY_DEV_CAP_MAX_PKEY_OFFSET 0x3f |
Or Gerlitz | ccf8632 | 2011-07-07 19:19:29 +0000 | [diff] [blame] | 537 | #define QUERY_DEV_CAP_EXT_FLAGS_OFFSET 0x40 |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 538 | #define QUERY_DEV_CAP_FLAGS_OFFSET 0x44 |
| 539 | #define QUERY_DEV_CAP_RSVD_UAR_OFFSET 0x48 |
| 540 | #define QUERY_DEV_CAP_UAR_SZ_OFFSET 0x49 |
| 541 | #define QUERY_DEV_CAP_PAGE_SZ_OFFSET 0x4b |
| 542 | #define QUERY_DEV_CAP_BF_OFFSET 0x4c |
| 543 | #define QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET 0x4d |
| 544 | #define QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET 0x4e |
| 545 | #define QUERY_DEV_CAP_LOG_MAX_BF_PAGES_OFFSET 0x4f |
| 546 | #define QUERY_DEV_CAP_MAX_SG_SQ_OFFSET 0x51 |
| 547 | #define QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET 0x52 |
| 548 | #define QUERY_DEV_CAP_MAX_SG_RQ_OFFSET 0x55 |
| 549 | #define QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET 0x56 |
| 550 | #define QUERY_DEV_CAP_MAX_QP_MCG_OFFSET 0x61 |
| 551 | #define QUERY_DEV_CAP_RSVD_MCG_OFFSET 0x62 |
| 552 | #define QUERY_DEV_CAP_MAX_MCG_OFFSET 0x63 |
| 553 | #define QUERY_DEV_CAP_RSVD_PD_OFFSET 0x64 |
| 554 | #define QUERY_DEV_CAP_MAX_PD_OFFSET 0x65 |
Linus Torvalds | f470f8d | 2011-11-01 10:51:38 -0700 | [diff] [blame] | 555 | #define QUERY_DEV_CAP_RSVD_XRC_OFFSET 0x66 |
| 556 | #define QUERY_DEV_CAP_MAX_XRC_OFFSET 0x67 |
Or Gerlitz | f2a3f6a | 2011-06-15 14:47:14 +0000 | [diff] [blame] | 557 | #define QUERY_DEV_CAP_MAX_COUNTERS_OFFSET 0x68 |
Rony Efraim | 3f7fb02 | 2013-04-25 05:22:28 +0000 | [diff] [blame] | 558 | #define QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET 0x70 |
Matan Barak | 4de6580 | 2013-11-07 15:25:14 +0200 | [diff] [blame] | 559 | #define QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET 0x74 |
Hadar Hen Zion | 0ff1fb6 | 2012-07-05 04:03:46 +0000 | [diff] [blame] | 560 | #define QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET 0x76 |
| 561 | #define QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET 0x77 |
Ido Shamay | 77507aa | 2014-09-18 11:50:59 +0300 | [diff] [blame^] | 562 | #define QUERY_DEV_CAP_CQ_EQ_CACHE_LINE_STRIDE 0x7a |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 563 | #define QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET 0x80 |
| 564 | #define QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET 0x82 |
| 565 | #define QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET 0x84 |
| 566 | #define QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET 0x86 |
| 567 | #define QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET 0x88 |
| 568 | #define QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET 0x8a |
| 569 | #define QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET 0x8c |
| 570 | #define QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET 0x8e |
| 571 | #define QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET 0x90 |
| 572 | #define QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET 0x92 |
Roland Dreier | 95d04f0 | 2008-07-23 08:12:26 -0700 | [diff] [blame] | 573 | #define QUERY_DEV_CAP_BMME_FLAGS_OFFSET 0x94 |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 574 | #define QUERY_DEV_CAP_RSVD_LKEY_OFFSET 0x98 |
| 575 | #define QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET 0xa0 |
Matan Barak | 955154f | 2013-01-30 23:07:10 +0000 | [diff] [blame] | 576 | #define QUERY_DEV_CAP_FW_REASSIGN_MAC 0x9d |
Or Gerlitz | 7ffdf72 | 2013-12-23 16:09:43 +0200 | [diff] [blame] | 577 | #define QUERY_DEV_CAP_VXLAN 0x9e |
Jack Morgenstein | 114840c | 2014-06-01 11:53:50 +0300 | [diff] [blame] | 578 | #define QUERY_DEV_CAP_MAD_DEMUX_OFFSET 0xb0 |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 579 | |
Shlomo Pongratz | b3416f4 | 2012-04-29 17:04:25 +0300 | [diff] [blame] | 580 | dev_cap->flags2 = 0; |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 581 | mailbox = mlx4_alloc_cmd_mailbox(dev); |
| 582 | if (IS_ERR(mailbox)) |
| 583 | return PTR_ERR(mailbox); |
| 584 | outbox = mailbox->buf; |
| 585 | |
| 586 | err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP, |
Jack Morgenstein | 401453a | 2012-05-30 09:14:55 +0000 | [diff] [blame] | 587 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 588 | if (err) |
| 589 | goto out; |
| 590 | |
| 591 | MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_QP_OFFSET); |
| 592 | dev_cap->reserved_qps = 1 << (field & 0xf); |
| 593 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_OFFSET); |
| 594 | dev_cap->max_qps = 1 << (field & 0x1f); |
| 595 | MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_SRQ_OFFSET); |
| 596 | dev_cap->reserved_srqs = 1 << (field >> 4); |
| 597 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_OFFSET); |
| 598 | dev_cap->max_srqs = 1 << (field & 0x1f); |
| 599 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET); |
| 600 | dev_cap->max_cq_sz = 1 << field; |
| 601 | MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_CQ_OFFSET); |
| 602 | dev_cap->reserved_cqs = 1 << (field & 0xf); |
| 603 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_OFFSET); |
| 604 | dev_cap->max_cqs = 1 << (field & 0x1f); |
| 605 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MPT_OFFSET); |
| 606 | dev_cap->max_mpts = 1 << (field & 0x3f); |
| 607 | MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_EQ_OFFSET); |
Yevgeny Petrilin | be504b0 | 2009-11-12 15:51:16 -0800 | [diff] [blame] | 608 | dev_cap->reserved_eqs = field & 0xf; |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 609 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_EQ_OFFSET); |
Jack Morgenstein | 5920869 | 2007-12-10 05:25:23 +0200 | [diff] [blame] | 610 | dev_cap->max_eqs = 1 << (field & 0xf); |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 611 | MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MTT_OFFSET); |
| 612 | dev_cap->reserved_mtts = 1 << (field >> 4); |
| 613 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET); |
| 614 | dev_cap->max_mrw_sz = 1 << field; |
| 615 | MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MRW_OFFSET); |
| 616 | dev_cap->reserved_mrws = 1 << (field & 0xf); |
| 617 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET); |
| 618 | dev_cap->max_mtt_seg = 1 << (field & 0x3f); |
| 619 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_REQ_QP_OFFSET); |
| 620 | dev_cap->max_requester_per_qp = 1 << (field & 0x3f); |
| 621 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RES_QP_OFFSET); |
| 622 | dev_cap->max_responder_per_qp = 1 << (field & 0x3f); |
Eli Cohen | b832be1 | 2008-04-16 21:09:27 -0700 | [diff] [blame] | 623 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GSO_OFFSET); |
| 624 | field &= 0x1f; |
| 625 | if (!field) |
| 626 | dev_cap->max_gso_sz = 0; |
| 627 | else |
| 628 | dev_cap->max_gso_sz = 1 << field; |
| 629 | |
Shlomo Pongratz | b3416f4 | 2012-04-29 17:04:25 +0300 | [diff] [blame] | 630 | MLX4_GET(field, outbox, QUERY_DEV_CAP_RSS_OFFSET); |
| 631 | if (field & 0x20) |
| 632 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS_XOR; |
| 633 | if (field & 0x10) |
| 634 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS_TOP; |
| 635 | field &= 0xf; |
| 636 | if (field) { |
| 637 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS; |
| 638 | dev_cap->max_rss_tbl_sz = 1 << field; |
| 639 | } else |
| 640 | dev_cap->max_rss_tbl_sz = 0; |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 641 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RDMA_OFFSET); |
| 642 | dev_cap->max_rdma_global = 1 << (field & 0x3f); |
| 643 | MLX4_GET(field, outbox, QUERY_DEV_CAP_ACK_DELAY_OFFSET); |
| 644 | dev_cap->local_ca_ack_delay = field & 0x1f; |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 645 | MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET); |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 646 | dev_cap->num_ports = field & 0xf; |
Dotan Barak | 149983af | 2007-06-26 15:55:28 +0300 | [diff] [blame] | 647 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET); |
| 648 | dev_cap->max_msg_sz = 1 << (field & 0x1f); |
Hadar Hen Zion | 0ff1fb6 | 2012-07-05 04:03:46 +0000 | [diff] [blame] | 649 | MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET); |
| 650 | if (field & 0x80) |
| 651 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FS_EN; |
| 652 | dev_cap->fs_log_max_ucast_qp_range_size = field & 0x1f; |
Matan Barak | 4de6580 | 2013-11-07 15:25:14 +0200 | [diff] [blame] | 653 | MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET); |
| 654 | if (field & 0x80) |
| 655 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_DMFS_IPOIB; |
Hadar Hen Zion | 0ff1fb6 | 2012-07-05 04:03:46 +0000 | [diff] [blame] | 656 | MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET); |
| 657 | dev_cap->fs_max_num_qp_per_entry = field; |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 658 | MLX4_GET(stat_rate, outbox, QUERY_DEV_CAP_RATE_SUPPORT_OFFSET); |
| 659 | dev_cap->stat_rate_support = stat_rate; |
Eugenia Emantayev | d998735 | 2013-04-23 06:06:47 +0000 | [diff] [blame] | 660 | MLX4_GET(field, outbox, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET); |
| 661 | if (field & 0x80) |
| 662 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_TS; |
Or Gerlitz | ccf8632 | 2011-07-07 19:19:29 +0000 | [diff] [blame] | 663 | MLX4_GET(ext_flags, outbox, QUERY_DEV_CAP_EXT_FLAGS_OFFSET); |
Or Gerlitz | 52eafc6 | 2011-06-15 14:41:42 +0000 | [diff] [blame] | 664 | MLX4_GET(flags, outbox, QUERY_DEV_CAP_FLAGS_OFFSET); |
Or Gerlitz | ccf8632 | 2011-07-07 19:19:29 +0000 | [diff] [blame] | 665 | dev_cap->flags = flags | (u64)ext_flags << 32; |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 666 | MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_UAR_OFFSET); |
| 667 | dev_cap->reserved_uars = field >> 4; |
| 668 | MLX4_GET(field, outbox, QUERY_DEV_CAP_UAR_SZ_OFFSET); |
| 669 | dev_cap->uar_size = 1 << ((field & 0x3f) + 20); |
| 670 | MLX4_GET(field, outbox, QUERY_DEV_CAP_PAGE_SZ_OFFSET); |
| 671 | dev_cap->min_page_sz = 1 << field; |
| 672 | |
| 673 | MLX4_GET(field, outbox, QUERY_DEV_CAP_BF_OFFSET); |
| 674 | if (field & 0x80) { |
| 675 | MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET); |
| 676 | dev_cap->bf_reg_size = 1 << (field & 0x1f); |
| 677 | MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET); |
Roland Dreier | f5a4953 | 2011-01-10 17:42:05 -0800 | [diff] [blame] | 678 | if ((1 << (field & 0x3f)) > (PAGE_SIZE / dev_cap->bf_reg_size)) |
Eli Cohen | 58d74bb | 2010-11-10 12:52:37 +0000 | [diff] [blame] | 679 | field = 3; |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 680 | dev_cap->bf_regs_per_page = 1 << (field & 0x3f); |
| 681 | mlx4_dbg(dev, "BlueFlame available (reg size %d, regs/page %d)\n", |
| 682 | dev_cap->bf_reg_size, dev_cap->bf_regs_per_page); |
| 683 | } else { |
| 684 | dev_cap->bf_reg_size = 0; |
| 685 | mlx4_dbg(dev, "BlueFlame not available\n"); |
| 686 | } |
| 687 | |
| 688 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_SQ_OFFSET); |
| 689 | dev_cap->max_sq_sg = field; |
| 690 | MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET); |
| 691 | dev_cap->max_sq_desc_sz = size; |
| 692 | |
| 693 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_MCG_OFFSET); |
| 694 | dev_cap->max_qp_per_mcg = 1 << field; |
| 695 | MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MCG_OFFSET); |
| 696 | dev_cap->reserved_mgms = field & 0xf; |
| 697 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MCG_OFFSET); |
| 698 | dev_cap->max_mcgs = 1 << field; |
| 699 | MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_PD_OFFSET); |
| 700 | dev_cap->reserved_pds = field >> 4; |
| 701 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PD_OFFSET); |
| 702 | dev_cap->max_pds = 1 << (field & 0x3f); |
Linus Torvalds | f470f8d | 2011-11-01 10:51:38 -0700 | [diff] [blame] | 703 | MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_XRC_OFFSET); |
| 704 | dev_cap->reserved_xrcds = field >> 4; |
Dotan Barak | 426dd00 | 2012-08-23 14:09:04 +0000 | [diff] [blame] | 705 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_XRC_OFFSET); |
Linus Torvalds | f470f8d | 2011-11-01 10:51:38 -0700 | [diff] [blame] | 706 | dev_cap->max_xrcds = 1 << (field & 0x1f); |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 707 | |
| 708 | MLX4_GET(size, outbox, QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET); |
| 709 | dev_cap->rdmarc_entry_sz = size; |
| 710 | MLX4_GET(size, outbox, QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET); |
| 711 | dev_cap->qpc_entry_sz = size; |
| 712 | MLX4_GET(size, outbox, QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET); |
| 713 | dev_cap->aux_entry_sz = size; |
| 714 | MLX4_GET(size, outbox, QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET); |
| 715 | dev_cap->altc_entry_sz = size; |
| 716 | MLX4_GET(size, outbox, QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET); |
| 717 | dev_cap->eqc_entry_sz = size; |
| 718 | MLX4_GET(size, outbox, QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET); |
| 719 | dev_cap->cqc_entry_sz = size; |
| 720 | MLX4_GET(size, outbox, QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET); |
| 721 | dev_cap->srq_entry_sz = size; |
| 722 | MLX4_GET(size, outbox, QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET); |
| 723 | dev_cap->cmpt_entry_sz = size; |
| 724 | MLX4_GET(size, outbox, QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET); |
| 725 | dev_cap->mtt_entry_sz = size; |
| 726 | MLX4_GET(size, outbox, QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET); |
| 727 | dev_cap->dmpt_entry_sz = size; |
| 728 | |
| 729 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET); |
| 730 | dev_cap->max_srq_sz = 1 << field; |
| 731 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_SZ_OFFSET); |
| 732 | dev_cap->max_qp_sz = 1 << field; |
| 733 | MLX4_GET(field, outbox, QUERY_DEV_CAP_RSZ_SRQ_OFFSET); |
| 734 | dev_cap->resize_srq = field & 1; |
| 735 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_RQ_OFFSET); |
| 736 | dev_cap->max_rq_sg = field; |
| 737 | MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET); |
| 738 | dev_cap->max_rq_desc_sz = size; |
Ido Shamay | 77507aa | 2014-09-18 11:50:59 +0300 | [diff] [blame^] | 739 | MLX4_GET(field, outbox, QUERY_DEV_CAP_CQ_EQ_CACHE_LINE_STRIDE); |
| 740 | if (field & (1 << 6)) |
| 741 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_CQE_STRIDE; |
| 742 | if (field & (1 << 7)) |
| 743 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_EQE_STRIDE; |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 744 | |
| 745 | MLX4_GET(dev_cap->bmme_flags, outbox, |
| 746 | QUERY_DEV_CAP_BMME_FLAGS_OFFSET); |
| 747 | MLX4_GET(dev_cap->reserved_lkey, outbox, |
| 748 | QUERY_DEV_CAP_RSVD_LKEY_OFFSET); |
Matan Barak | 955154f | 2013-01-30 23:07:10 +0000 | [diff] [blame] | 749 | MLX4_GET(field, outbox, QUERY_DEV_CAP_FW_REASSIGN_MAC); |
| 750 | if (field & 1<<6) |
Or Gerlitz | 5930e8d | 2013-10-15 16:55:22 +0200 | [diff] [blame] | 751 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN; |
Or Gerlitz | 7ffdf72 | 2013-12-23 16:09:43 +0200 | [diff] [blame] | 752 | MLX4_GET(field, outbox, QUERY_DEV_CAP_VXLAN); |
| 753 | if (field & 1<<3) |
| 754 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS; |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 755 | MLX4_GET(dev_cap->max_icm_sz, outbox, |
| 756 | QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET); |
Or Gerlitz | f2a3f6a | 2011-06-15 14:47:14 +0000 | [diff] [blame] | 757 | if (dev_cap->flags & MLX4_DEV_CAP_FLAG_COUNTERS) |
| 758 | MLX4_GET(dev_cap->max_counters, outbox, |
| 759 | QUERY_DEV_CAP_MAX_COUNTERS_OFFSET); |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 760 | |
Jack Morgenstein | 114840c | 2014-06-01 11:53:50 +0300 | [diff] [blame] | 761 | MLX4_GET(field32, outbox, |
| 762 | QUERY_DEV_CAP_MAD_DEMUX_OFFSET); |
| 763 | if (field32 & (1 << 0)) |
| 764 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_MAD_DEMUX; |
| 765 | |
Rony Efraim | 3f7fb02 | 2013-04-25 05:22:28 +0000 | [diff] [blame] | 766 | MLX4_GET(field32, outbox, QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET); |
Jack Morgenstein | b01978c | 2013-06-27 19:05:21 +0300 | [diff] [blame] | 767 | if (field32 & (1 << 16)) |
| 768 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_UPDATE_QP; |
Rony Efraim | 3f7fb02 | 2013-04-25 05:22:28 +0000 | [diff] [blame] | 769 | if (field32 & (1 << 26)) |
| 770 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_VLAN_CONTROL; |
Rony Efraim | e6b6a23 | 2013-04-25 05:22:29 +0000 | [diff] [blame] | 771 | if (field32 & (1 << 20)) |
| 772 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FSM; |
Rony Efraim | 3f7fb02 | 2013-04-25 05:22:28 +0000 | [diff] [blame] | 773 | |
Roland Dreier | 5ae2a7a | 2007-06-18 08:15:02 -0700 | [diff] [blame] | 774 | if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) { |
| 775 | for (i = 1; i <= dev_cap->num_ports; ++i) { |
| 776 | MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET); |
| 777 | dev_cap->max_vl[i] = field >> 4; |
| 778 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MTU_WIDTH_OFFSET); |
Yevgeny Petrilin | b79acb4 | 2008-10-22 10:56:48 -0700 | [diff] [blame] | 779 | dev_cap->ib_mtu[i] = field >> 4; |
Roland Dreier | 5ae2a7a | 2007-06-18 08:15:02 -0700 | [diff] [blame] | 780 | dev_cap->max_port_width[i] = field & 0xf; |
| 781 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GID_OFFSET); |
| 782 | dev_cap->max_gids[i] = 1 << (field & 0xf); |
| 783 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PKEY_OFFSET); |
| 784 | dev_cap->max_pkeys[i] = 1 << (field & 0xf); |
| 785 | } |
| 786 | } else { |
Yevgeny Petrilin | 7ff93f8 | 2008-10-22 15:38:42 -0700 | [diff] [blame] | 787 | #define QUERY_PORT_SUPPORTED_TYPE_OFFSET 0x00 |
Roland Dreier | 5ae2a7a | 2007-06-18 08:15:02 -0700 | [diff] [blame] | 788 | #define QUERY_PORT_MTU_OFFSET 0x01 |
Yevgeny Petrilin | b79acb4 | 2008-10-22 10:56:48 -0700 | [diff] [blame] | 789 | #define QUERY_PORT_ETH_MTU_OFFSET 0x02 |
Roland Dreier | 5ae2a7a | 2007-06-18 08:15:02 -0700 | [diff] [blame] | 790 | #define QUERY_PORT_WIDTH_OFFSET 0x06 |
| 791 | #define QUERY_PORT_MAX_GID_PKEY_OFFSET 0x07 |
Yevgeny Petrilin | 93fc9e1 | 2008-10-22 10:25:29 -0700 | [diff] [blame] | 792 | #define QUERY_PORT_MAX_MACVLAN_OFFSET 0x0a |
Roland Dreier | 5ae2a7a | 2007-06-18 08:15:02 -0700 | [diff] [blame] | 793 | #define QUERY_PORT_MAX_VL_OFFSET 0x0b |
Yevgeny Petrilin | e65b959 | 2008-10-26 17:13:24 +0200 | [diff] [blame] | 794 | #define QUERY_PORT_MAC_OFFSET 0x10 |
Yevgeny Petrilin | 7699517 | 2010-08-24 03:46:23 +0000 | [diff] [blame] | 795 | #define QUERY_PORT_TRANS_VENDOR_OFFSET 0x18 |
| 796 | #define QUERY_PORT_WAVELENGTH_OFFSET 0x1c |
| 797 | #define QUERY_PORT_TRANS_CODE_OFFSET 0x20 |
Roland Dreier | 5ae2a7a | 2007-06-18 08:15:02 -0700 | [diff] [blame] | 798 | |
| 799 | for (i = 1; i <= dev_cap->num_ports; ++i) { |
| 800 | err = mlx4_cmd_box(dev, 0, mailbox->dma, i, 0, MLX4_CMD_QUERY_PORT, |
Jack Morgenstein | 401453a | 2012-05-30 09:14:55 +0000 | [diff] [blame] | 801 | MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); |
Roland Dreier | 5ae2a7a | 2007-06-18 08:15:02 -0700 | [diff] [blame] | 802 | if (err) |
| 803 | goto out; |
| 804 | |
Yevgeny Petrilin | 7ff93f8 | 2008-10-22 15:38:42 -0700 | [diff] [blame] | 805 | MLX4_GET(field, outbox, QUERY_PORT_SUPPORTED_TYPE_OFFSET); |
| 806 | dev_cap->supported_port_types[i] = field & 3; |
Yevgeny Petrilin | 8d0fc7b | 2011-12-19 04:00:34 +0000 | [diff] [blame] | 807 | dev_cap->suggested_type[i] = (field >> 3) & 1; |
| 808 | dev_cap->default_sense[i] = (field >> 4) & 1; |
Roland Dreier | 5ae2a7a | 2007-06-18 08:15:02 -0700 | [diff] [blame] | 809 | MLX4_GET(field, outbox, QUERY_PORT_MTU_OFFSET); |
Yevgeny Petrilin | b79acb4 | 2008-10-22 10:56:48 -0700 | [diff] [blame] | 810 | dev_cap->ib_mtu[i] = field & 0xf; |
Roland Dreier | 5ae2a7a | 2007-06-18 08:15:02 -0700 | [diff] [blame] | 811 | MLX4_GET(field, outbox, QUERY_PORT_WIDTH_OFFSET); |
| 812 | dev_cap->max_port_width[i] = field & 0xf; |
| 813 | MLX4_GET(field, outbox, QUERY_PORT_MAX_GID_PKEY_OFFSET); |
| 814 | dev_cap->max_gids[i] = 1 << (field >> 4); |
| 815 | dev_cap->max_pkeys[i] = 1 << (field & 0xf); |
| 816 | MLX4_GET(field, outbox, QUERY_PORT_MAX_VL_OFFSET); |
| 817 | dev_cap->max_vl[i] = field & 0xf; |
Yevgeny Petrilin | 93fc9e1 | 2008-10-22 10:25:29 -0700 | [diff] [blame] | 818 | MLX4_GET(field, outbox, QUERY_PORT_MAX_MACVLAN_OFFSET); |
| 819 | dev_cap->log_max_macs[i] = field & 0xf; |
| 820 | dev_cap->log_max_vlans[i] = field >> 4; |
Yevgeny Petrilin | b79acb4 | 2008-10-22 10:56:48 -0700 | [diff] [blame] | 821 | MLX4_GET(dev_cap->eth_mtu[i], outbox, QUERY_PORT_ETH_MTU_OFFSET); |
| 822 | MLX4_GET(dev_cap->def_mac[i], outbox, QUERY_PORT_MAC_OFFSET); |
Yevgeny Petrilin | 7699517 | 2010-08-24 03:46:23 +0000 | [diff] [blame] | 823 | MLX4_GET(field32, outbox, QUERY_PORT_TRANS_VENDOR_OFFSET); |
| 824 | dev_cap->trans_type[i] = field32 >> 24; |
| 825 | dev_cap->vendor_oui[i] = field32 & 0xffffff; |
| 826 | MLX4_GET(dev_cap->wavelength[i], outbox, QUERY_PORT_WAVELENGTH_OFFSET); |
| 827 | MLX4_GET(dev_cap->trans_code[i], outbox, QUERY_PORT_TRANS_CODE_OFFSET); |
Roland Dreier | 5ae2a7a | 2007-06-18 08:15:02 -0700 | [diff] [blame] | 828 | } |
| 829 | } |
| 830 | |
Roland Dreier | 95d04f0 | 2008-07-23 08:12:26 -0700 | [diff] [blame] | 831 | mlx4_dbg(dev, "Base MM extensions: flags %08x, rsvd L_Key %08x\n", |
| 832 | dev_cap->bmme_flags, dev_cap->reserved_lkey); |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 833 | |
| 834 | /* |
| 835 | * Each UAR has 4 EQ doorbells; so if a UAR is reserved, then |
| 836 | * we can't use any EQs whose doorbell falls on that page, |
| 837 | * even if the EQ itself isn't reserved. |
| 838 | */ |
| 839 | dev_cap->reserved_eqs = max(dev_cap->reserved_uars * 4, |
| 840 | dev_cap->reserved_eqs); |
| 841 | |
| 842 | mlx4_dbg(dev, "Max ICM size %lld MB\n", |
| 843 | (unsigned long long) dev_cap->max_icm_sz >> 20); |
| 844 | mlx4_dbg(dev, "Max QPs: %d, reserved QPs: %d, entry size: %d\n", |
| 845 | dev_cap->max_qps, dev_cap->reserved_qps, dev_cap->qpc_entry_sz); |
| 846 | mlx4_dbg(dev, "Max SRQs: %d, reserved SRQs: %d, entry size: %d\n", |
| 847 | dev_cap->max_srqs, dev_cap->reserved_srqs, dev_cap->srq_entry_sz); |
| 848 | mlx4_dbg(dev, "Max CQs: %d, reserved CQs: %d, entry size: %d\n", |
| 849 | dev_cap->max_cqs, dev_cap->reserved_cqs, dev_cap->cqc_entry_sz); |
| 850 | mlx4_dbg(dev, "Max EQs: %d, reserved EQs: %d, entry size: %d\n", |
| 851 | dev_cap->max_eqs, dev_cap->reserved_eqs, dev_cap->eqc_entry_sz); |
| 852 | mlx4_dbg(dev, "reserved MPTs: %d, reserved MTTs: %d\n", |
| 853 | dev_cap->reserved_mrws, dev_cap->reserved_mtts); |
| 854 | mlx4_dbg(dev, "Max PDs: %d, reserved PDs: %d, reserved UARs: %d\n", |
| 855 | dev_cap->max_pds, dev_cap->reserved_pds, dev_cap->reserved_uars); |
| 856 | mlx4_dbg(dev, "Max QP/MCG: %d, reserved MGMs: %d\n", |
| 857 | dev_cap->max_pds, dev_cap->reserved_mgms); |
| 858 | mlx4_dbg(dev, "Max CQEs: %d, max WQEs: %d, max SRQ WQEs: %d\n", |
| 859 | dev_cap->max_cq_sz, dev_cap->max_qp_sz, dev_cap->max_srq_sz); |
| 860 | mlx4_dbg(dev, "Local CA ACK delay: %d, max MTU: %d, port width cap: %d\n", |
Yevgeny Petrilin | b79acb4 | 2008-10-22 10:56:48 -0700 | [diff] [blame] | 861 | dev_cap->local_ca_ack_delay, 128 << dev_cap->ib_mtu[1], |
Roland Dreier | 5ae2a7a | 2007-06-18 08:15:02 -0700 | [diff] [blame] | 862 | dev_cap->max_port_width[1]); |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 863 | mlx4_dbg(dev, "Max SQ desc size: %d, max SQ S/G: %d\n", |
| 864 | dev_cap->max_sq_desc_sz, dev_cap->max_sq_sg); |
| 865 | mlx4_dbg(dev, "Max RQ desc size: %d, max RQ S/G: %d\n", |
| 866 | dev_cap->max_rq_desc_sz, dev_cap->max_rq_sg); |
Eli Cohen | b832be1 | 2008-04-16 21:09:27 -0700 | [diff] [blame] | 867 | mlx4_dbg(dev, "Max GSO size: %d\n", dev_cap->max_gso_sz); |
Or Gerlitz | f2a3f6a | 2011-06-15 14:47:14 +0000 | [diff] [blame] | 868 | mlx4_dbg(dev, "Max counters: %d\n", dev_cap->max_counters); |
Shlomo Pongratz | b3416f4 | 2012-04-29 17:04:25 +0300 | [diff] [blame] | 869 | mlx4_dbg(dev, "Max RSS Table size: %d\n", dev_cap->max_rss_tbl_sz); |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 870 | |
| 871 | dump_dev_cap_flags(dev, dev_cap->flags); |
Shlomo Pongratz | b3416f4 | 2012-04-29 17:04:25 +0300 | [diff] [blame] | 872 | dump_dev_cap_flags2(dev, dev_cap->flags2); |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 873 | |
| 874 | out: |
| 875 | mlx4_free_cmd_mailbox(dev, mailbox); |
| 876 | return err; |
| 877 | } |
| 878 | |
Jack Morgenstein | b91cb3e | 2012-05-30 09:14:53 +0000 | [diff] [blame] | 879 | int mlx4_QUERY_DEV_CAP_wrapper(struct mlx4_dev *dev, int slave, |
| 880 | struct mlx4_vhcr *vhcr, |
| 881 | struct mlx4_cmd_mailbox *inbox, |
| 882 | struct mlx4_cmd_mailbox *outbox, |
| 883 | struct mlx4_cmd_info *cmd) |
| 884 | { |
Jack Morgenstein | 2a4fae1 | 2012-08-03 08:40:50 +0000 | [diff] [blame] | 885 | u64 flags; |
Jack Morgenstein | b91cb3e | 2012-05-30 09:14:53 +0000 | [diff] [blame] | 886 | int err = 0; |
| 887 | u8 field; |
Shani Michaeli | cc1ade9 | 2013-02-06 16:19:10 +0000 | [diff] [blame] | 888 | u32 bmme_flags; |
Matan Barak | 449fc48 | 2014-03-19 18:11:52 +0200 | [diff] [blame] | 889 | int real_port; |
| 890 | int slave_port; |
| 891 | int first_port; |
| 892 | struct mlx4_active_ports actv_ports; |
Jack Morgenstein | b91cb3e | 2012-05-30 09:14:53 +0000 | [diff] [blame] | 893 | |
| 894 | err = mlx4_cmd_box(dev, 0, outbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP, |
| 895 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); |
| 896 | if (err) |
| 897 | return err; |
| 898 | |
Shani Michaeli | cc1ade9 | 2013-02-06 16:19:10 +0000 | [diff] [blame] | 899 | /* add port mng change event capability and disable mw type 1 |
| 900 | * unconditionally to slaves |
| 901 | */ |
Jack Morgenstein | 2a4fae1 | 2012-08-03 08:40:50 +0000 | [diff] [blame] | 902 | MLX4_GET(flags, outbox->buf, QUERY_DEV_CAP_EXT_FLAGS_OFFSET); |
| 903 | flags |= MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV; |
Shani Michaeli | cc1ade9 | 2013-02-06 16:19:10 +0000 | [diff] [blame] | 904 | flags &= ~MLX4_DEV_CAP_FLAG_MEM_WINDOW; |
Matan Barak | 449fc48 | 2014-03-19 18:11:52 +0200 | [diff] [blame] | 905 | actv_ports = mlx4_get_active_ports(dev, slave); |
| 906 | first_port = find_first_bit(actv_ports.ports, dev->caps.num_ports); |
| 907 | for (slave_port = 0, real_port = first_port; |
| 908 | real_port < first_port + |
| 909 | bitmap_weight(actv_ports.ports, dev->caps.num_ports); |
| 910 | ++real_port, ++slave_port) { |
| 911 | if (flags & (MLX4_DEV_CAP_FLAG_WOL_PORT1 << real_port)) |
| 912 | flags |= MLX4_DEV_CAP_FLAG_WOL_PORT1 << slave_port; |
| 913 | else |
| 914 | flags &= ~(MLX4_DEV_CAP_FLAG_WOL_PORT1 << slave_port); |
| 915 | } |
| 916 | for (; slave_port < dev->caps.num_ports; ++slave_port) |
| 917 | flags &= ~(MLX4_DEV_CAP_FLAG_WOL_PORT1 << slave_port); |
Jack Morgenstein | 2a4fae1 | 2012-08-03 08:40:50 +0000 | [diff] [blame] | 918 | MLX4_PUT(outbox->buf, flags, QUERY_DEV_CAP_EXT_FLAGS_OFFSET); |
| 919 | |
Matan Barak | 449fc48 | 2014-03-19 18:11:52 +0200 | [diff] [blame] | 920 | MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_VL_PORT_OFFSET); |
| 921 | field &= ~0x0F; |
| 922 | field |= bitmap_weight(actv_ports.ports, dev->caps.num_ports) & 0x0F; |
| 923 | MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_VL_PORT_OFFSET); |
| 924 | |
Amir Vadai | 30b40c3 | 2013-04-25 05:22:23 +0000 | [diff] [blame] | 925 | /* For guests, disable timestamp */ |
| 926 | MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET); |
| 927 | field &= 0x7f; |
| 928 | MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET); |
| 929 | |
Or Gerlitz | 7ffdf72 | 2013-12-23 16:09:43 +0200 | [diff] [blame] | 930 | /* For guests, disable vxlan tunneling */ |
Amir Vadai | 57352ef | 2014-03-06 18:28:16 +0200 | [diff] [blame] | 931 | MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_VXLAN); |
Or Gerlitz | 7ffdf72 | 2013-12-23 16:09:43 +0200 | [diff] [blame] | 932 | field &= 0xf7; |
| 933 | MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_VXLAN); |
| 934 | |
Jack Morgenstein | b91cb3e | 2012-05-30 09:14:53 +0000 | [diff] [blame] | 935 | /* For guests, report Blueflame disabled */ |
| 936 | MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_BF_OFFSET); |
| 937 | field &= 0x7f; |
| 938 | MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_BF_OFFSET); |
| 939 | |
Shani Michaeli | cc1ade9 | 2013-02-06 16:19:10 +0000 | [diff] [blame] | 940 | /* For guests, disable mw type 2 */ |
Amir Vadai | 57352ef | 2014-03-06 18:28:16 +0200 | [diff] [blame] | 941 | MLX4_GET(bmme_flags, outbox->buf, QUERY_DEV_CAP_BMME_FLAGS_OFFSET); |
Shani Michaeli | cc1ade9 | 2013-02-06 16:19:10 +0000 | [diff] [blame] | 942 | bmme_flags &= ~MLX4_BMME_FLAG_TYPE_2_WIN; |
| 943 | MLX4_PUT(outbox->buf, bmme_flags, QUERY_DEV_CAP_BMME_FLAGS_OFFSET); |
| 944 | |
Jack Morgenstein | 0081c8f | 2013-03-07 03:46:53 +0000 | [diff] [blame] | 945 | /* turn off device-managed steering capability if not enabled */ |
| 946 | if (dev->caps.steering_mode != MLX4_STEERING_MODE_DEVICE_MANAGED) { |
| 947 | MLX4_GET(field, outbox->buf, |
| 948 | QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET); |
| 949 | field &= 0x7f; |
| 950 | MLX4_PUT(outbox->buf, field, |
| 951 | QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET); |
| 952 | } |
Matan Barak | 4de6580 | 2013-11-07 15:25:14 +0200 | [diff] [blame] | 953 | |
| 954 | /* turn off ipoib managed steering for guests */ |
Amir Vadai | 57352ef | 2014-03-06 18:28:16 +0200 | [diff] [blame] | 955 | MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET); |
Matan Barak | 4de6580 | 2013-11-07 15:25:14 +0200 | [diff] [blame] | 956 | field &= ~0x80; |
| 957 | MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET); |
| 958 | |
Jack Morgenstein | b91cb3e | 2012-05-30 09:14:53 +0000 | [diff] [blame] | 959 | return 0; |
| 960 | } |
| 961 | |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 962 | int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave, |
| 963 | struct mlx4_vhcr *vhcr, |
| 964 | struct mlx4_cmd_mailbox *inbox, |
| 965 | struct mlx4_cmd_mailbox *outbox, |
| 966 | struct mlx4_cmd_info *cmd) |
| 967 | { |
Rony Efraim | 0eb62b9 | 2013-04-25 05:22:26 +0000 | [diff] [blame] | 968 | struct mlx4_priv *priv = mlx4_priv(dev); |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 969 | u64 def_mac; |
| 970 | u8 port_type; |
Jack Morgenstein | 6634961 | 2012-06-19 11:21:44 +0300 | [diff] [blame] | 971 | u16 short_field; |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 972 | int err; |
Rony Efraim | 948e306 | 2013-06-13 13:19:11 +0300 | [diff] [blame] | 973 | int admin_link_state; |
Matan Barak | 449fc48 | 2014-03-19 18:11:52 +0200 | [diff] [blame] | 974 | int port = mlx4_slave_convert_port(dev, slave, |
| 975 | vhcr->in_modifier & 0xFF); |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 976 | |
Jack Morgenstein | 105c320 | 2012-06-19 11:21:43 +0300 | [diff] [blame] | 977 | #define MLX4_VF_PORT_NO_LINK_SENSE_MASK 0xE0 |
Rony Efraim | 948e306 | 2013-06-13 13:19:11 +0300 | [diff] [blame] | 978 | #define MLX4_PORT_LINK_UP_MASK 0x80 |
Jack Morgenstein | 6634961 | 2012-06-19 11:21:44 +0300 | [diff] [blame] | 979 | #define QUERY_PORT_CUR_MAX_PKEY_OFFSET 0x0c |
| 980 | #define QUERY_PORT_CUR_MAX_GID_OFFSET 0x0e |
Yevgeny Petrilin | 95f56e7 | 2011-12-29 07:42:39 +0000 | [diff] [blame] | 981 | |
Matan Barak | 449fc48 | 2014-03-19 18:11:52 +0200 | [diff] [blame] | 982 | if (port < 0) |
| 983 | return -EINVAL; |
| 984 | |
| 985 | vhcr->in_modifier = (vhcr->in_modifier & ~0xFF) | |
| 986 | (port & 0xFF); |
| 987 | |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 988 | err = mlx4_cmd_box(dev, 0, outbox->dma, vhcr->in_modifier, 0, |
| 989 | MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B, |
| 990 | MLX4_CMD_NATIVE); |
| 991 | |
| 992 | if (!err && dev->caps.function != slave) { |
Or Gerlitz | 0508ad6 | 2013-08-01 19:55:00 +0300 | [diff] [blame] | 993 | def_mac = priv->mfunc.master.vf_oper[slave].vport[vhcr->in_modifier].state.mac; |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 994 | MLX4_PUT(outbox->buf, def_mac, QUERY_PORT_MAC_OFFSET); |
| 995 | |
| 996 | /* get port type - currently only eth is enabled */ |
| 997 | MLX4_GET(port_type, outbox->buf, |
| 998 | QUERY_PORT_SUPPORTED_TYPE_OFFSET); |
| 999 | |
Jack Morgenstein | 105c320 | 2012-06-19 11:21:43 +0300 | [diff] [blame] | 1000 | /* No link sensing allowed */ |
| 1001 | port_type &= MLX4_VF_PORT_NO_LINK_SENSE_MASK; |
| 1002 | /* set port type to currently operating port type */ |
| 1003 | port_type |= (dev->caps.port_type[vhcr->in_modifier] & 0x3); |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 1004 | |
Rony Efraim | 948e306 | 2013-06-13 13:19:11 +0300 | [diff] [blame] | 1005 | admin_link_state = priv->mfunc.master.vf_oper[slave].vport[vhcr->in_modifier].state.link_state; |
| 1006 | if (IFLA_VF_LINK_STATE_ENABLE == admin_link_state) |
| 1007 | port_type |= MLX4_PORT_LINK_UP_MASK; |
| 1008 | else if (IFLA_VF_LINK_STATE_DISABLE == admin_link_state) |
| 1009 | port_type &= ~MLX4_PORT_LINK_UP_MASK; |
| 1010 | |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 1011 | MLX4_PUT(outbox->buf, port_type, |
| 1012 | QUERY_PORT_SUPPORTED_TYPE_OFFSET); |
Jack Morgenstein | 6634961 | 2012-06-19 11:21:44 +0300 | [diff] [blame] | 1013 | |
Jack Morgenstein | b6ffaef | 2014-03-12 12:00:39 +0200 | [diff] [blame] | 1014 | if (dev->caps.port_type[vhcr->in_modifier] == MLX4_PORT_TYPE_ETH) |
Matan Barak | 449fc48 | 2014-03-19 18:11:52 +0200 | [diff] [blame] | 1015 | short_field = mlx4_get_slave_num_gids(dev, slave, port); |
Jack Morgenstein | b6ffaef | 2014-03-12 12:00:39 +0200 | [diff] [blame] | 1016 | else |
| 1017 | short_field = 1; /* slave max gids */ |
Jack Morgenstein | 6634961 | 2012-06-19 11:21:44 +0300 | [diff] [blame] | 1018 | MLX4_PUT(outbox->buf, short_field, |
| 1019 | QUERY_PORT_CUR_MAX_GID_OFFSET); |
| 1020 | |
| 1021 | short_field = dev->caps.pkey_table_len[vhcr->in_modifier]; |
| 1022 | MLX4_PUT(outbox->buf, short_field, |
| 1023 | QUERY_PORT_CUR_MAX_PKEY_OFFSET); |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 1024 | } |
| 1025 | |
| 1026 | return err; |
| 1027 | } |
| 1028 | |
Jack Morgenstein | 6634961 | 2012-06-19 11:21:44 +0300 | [diff] [blame] | 1029 | int mlx4_get_slave_pkey_gid_tbl_len(struct mlx4_dev *dev, u8 port, |
| 1030 | int *gid_tbl_len, int *pkey_tbl_len) |
| 1031 | { |
| 1032 | struct mlx4_cmd_mailbox *mailbox; |
| 1033 | u32 *outbox; |
| 1034 | u16 field; |
| 1035 | int err; |
| 1036 | |
| 1037 | mailbox = mlx4_alloc_cmd_mailbox(dev); |
| 1038 | if (IS_ERR(mailbox)) |
| 1039 | return PTR_ERR(mailbox); |
| 1040 | |
| 1041 | err = mlx4_cmd_box(dev, 0, mailbox->dma, port, 0, |
| 1042 | MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B, |
| 1043 | MLX4_CMD_WRAPPED); |
| 1044 | if (err) |
| 1045 | goto out; |
| 1046 | |
| 1047 | outbox = mailbox->buf; |
| 1048 | |
| 1049 | MLX4_GET(field, outbox, QUERY_PORT_CUR_MAX_GID_OFFSET); |
| 1050 | *gid_tbl_len = field; |
| 1051 | |
| 1052 | MLX4_GET(field, outbox, QUERY_PORT_CUR_MAX_PKEY_OFFSET); |
| 1053 | *pkey_tbl_len = field; |
| 1054 | |
| 1055 | out: |
| 1056 | mlx4_free_cmd_mailbox(dev, mailbox); |
| 1057 | return err; |
| 1058 | } |
| 1059 | EXPORT_SYMBOL(mlx4_get_slave_pkey_gid_tbl_len); |
| 1060 | |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1061 | int mlx4_map_cmd(struct mlx4_dev *dev, u16 op, struct mlx4_icm *icm, u64 virt) |
| 1062 | { |
| 1063 | struct mlx4_cmd_mailbox *mailbox; |
| 1064 | struct mlx4_icm_iter iter; |
| 1065 | __be64 *pages; |
| 1066 | int lg; |
| 1067 | int nent = 0; |
| 1068 | int i; |
| 1069 | int err = 0; |
| 1070 | int ts = 0, tc = 0; |
| 1071 | |
| 1072 | mailbox = mlx4_alloc_cmd_mailbox(dev); |
| 1073 | if (IS_ERR(mailbox)) |
| 1074 | return PTR_ERR(mailbox); |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1075 | pages = mailbox->buf; |
| 1076 | |
| 1077 | for (mlx4_icm_first(icm, &iter); |
| 1078 | !mlx4_icm_last(&iter); |
| 1079 | mlx4_icm_next(&iter)) { |
| 1080 | /* |
| 1081 | * We have to pass pages that are aligned to their |
| 1082 | * size, so find the least significant 1 in the |
| 1083 | * address or size and use that as our log2 size. |
| 1084 | */ |
| 1085 | lg = ffs(mlx4_icm_addr(&iter) | mlx4_icm_size(&iter)) - 1; |
| 1086 | if (lg < MLX4_ICM_PAGE_SHIFT) { |
Joe Perches | 1a91de2 | 2014-05-07 12:52:57 -0700 | [diff] [blame] | 1087 | mlx4_warn(dev, "Got FW area not aligned to %d (%llx/%lx)\n", |
| 1088 | MLX4_ICM_PAGE_SIZE, |
| 1089 | (unsigned long long) mlx4_icm_addr(&iter), |
| 1090 | mlx4_icm_size(&iter)); |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1091 | err = -EINVAL; |
| 1092 | goto out; |
| 1093 | } |
| 1094 | |
| 1095 | for (i = 0; i < mlx4_icm_size(&iter) >> lg; ++i) { |
| 1096 | if (virt != -1) { |
| 1097 | pages[nent * 2] = cpu_to_be64(virt); |
| 1098 | virt += 1 << lg; |
| 1099 | } |
| 1100 | |
| 1101 | pages[nent * 2 + 1] = |
| 1102 | cpu_to_be64((mlx4_icm_addr(&iter) + (i << lg)) | |
| 1103 | (lg - MLX4_ICM_PAGE_SHIFT)); |
| 1104 | ts += 1 << (lg - 10); |
| 1105 | ++tc; |
| 1106 | |
| 1107 | if (++nent == MLX4_MAILBOX_SIZE / 16) { |
| 1108 | err = mlx4_cmd(dev, mailbox->dma, nent, 0, op, |
Jack Morgenstein | f9baff5 | 2011-12-13 04:10:51 +0000 | [diff] [blame] | 1109 | MLX4_CMD_TIME_CLASS_B, |
| 1110 | MLX4_CMD_NATIVE); |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1111 | if (err) |
| 1112 | goto out; |
| 1113 | nent = 0; |
| 1114 | } |
| 1115 | } |
| 1116 | } |
| 1117 | |
| 1118 | if (nent) |
Jack Morgenstein | f9baff5 | 2011-12-13 04:10:51 +0000 | [diff] [blame] | 1119 | err = mlx4_cmd(dev, mailbox->dma, nent, 0, op, |
| 1120 | MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1121 | if (err) |
| 1122 | goto out; |
| 1123 | |
| 1124 | switch (op) { |
| 1125 | case MLX4_CMD_MAP_FA: |
Joe Perches | 1a91de2 | 2014-05-07 12:52:57 -0700 | [diff] [blame] | 1126 | mlx4_dbg(dev, "Mapped %d chunks/%d KB for FW\n", tc, ts); |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1127 | break; |
| 1128 | case MLX4_CMD_MAP_ICM_AUX: |
Joe Perches | 1a91de2 | 2014-05-07 12:52:57 -0700 | [diff] [blame] | 1129 | mlx4_dbg(dev, "Mapped %d chunks/%d KB for ICM aux\n", tc, ts); |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1130 | break; |
| 1131 | case MLX4_CMD_MAP_ICM: |
Joe Perches | 1a91de2 | 2014-05-07 12:52:57 -0700 | [diff] [blame] | 1132 | mlx4_dbg(dev, "Mapped %d chunks/%d KB at %llx for ICM\n", |
| 1133 | tc, ts, (unsigned long long) virt - (ts << 10)); |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1134 | break; |
| 1135 | } |
| 1136 | |
| 1137 | out: |
| 1138 | mlx4_free_cmd_mailbox(dev, mailbox); |
| 1139 | return err; |
| 1140 | } |
| 1141 | |
| 1142 | int mlx4_MAP_FA(struct mlx4_dev *dev, struct mlx4_icm *icm) |
| 1143 | { |
| 1144 | return mlx4_map_cmd(dev, MLX4_CMD_MAP_FA, icm, -1); |
| 1145 | } |
| 1146 | |
| 1147 | int mlx4_UNMAP_FA(struct mlx4_dev *dev) |
| 1148 | { |
Jack Morgenstein | f9baff5 | 2011-12-13 04:10:51 +0000 | [diff] [blame] | 1149 | return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_UNMAP_FA, |
| 1150 | MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1151 | } |
| 1152 | |
| 1153 | |
| 1154 | int mlx4_RUN_FW(struct mlx4_dev *dev) |
| 1155 | { |
Jack Morgenstein | f9baff5 | 2011-12-13 04:10:51 +0000 | [diff] [blame] | 1156 | return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_RUN_FW, |
| 1157 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1158 | } |
| 1159 | |
| 1160 | int mlx4_QUERY_FW(struct mlx4_dev *dev) |
| 1161 | { |
| 1162 | struct mlx4_fw *fw = &mlx4_priv(dev)->fw; |
| 1163 | struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd; |
| 1164 | struct mlx4_cmd_mailbox *mailbox; |
| 1165 | u32 *outbox; |
| 1166 | int err = 0; |
| 1167 | u64 fw_ver; |
Roland Dreier | fe40900 | 2007-06-07 23:24:36 -0700 | [diff] [blame] | 1168 | u16 cmd_if_rev; |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1169 | u8 lg; |
| 1170 | |
| 1171 | #define QUERY_FW_OUT_SIZE 0x100 |
| 1172 | #define QUERY_FW_VER_OFFSET 0x00 |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 1173 | #define QUERY_FW_PPF_ID 0x09 |
Roland Dreier | fe40900 | 2007-06-07 23:24:36 -0700 | [diff] [blame] | 1174 | #define QUERY_FW_CMD_IF_REV_OFFSET 0x0a |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1175 | #define QUERY_FW_MAX_CMD_OFFSET 0x0f |
| 1176 | #define QUERY_FW_ERR_START_OFFSET 0x30 |
| 1177 | #define QUERY_FW_ERR_SIZE_OFFSET 0x38 |
| 1178 | #define QUERY_FW_ERR_BAR_OFFSET 0x3c |
| 1179 | |
| 1180 | #define QUERY_FW_SIZE_OFFSET 0x00 |
| 1181 | #define QUERY_FW_CLR_INT_BASE_OFFSET 0x20 |
| 1182 | #define QUERY_FW_CLR_INT_BAR_OFFSET 0x28 |
| 1183 | |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 1184 | #define QUERY_FW_COMM_BASE_OFFSET 0x40 |
| 1185 | #define QUERY_FW_COMM_BAR_OFFSET 0x48 |
| 1186 | |
Eugenia Emantayev | ddd8a6c | 2013-04-23 06:06:48 +0000 | [diff] [blame] | 1187 | #define QUERY_FW_CLOCK_OFFSET 0x50 |
| 1188 | #define QUERY_FW_CLOCK_BAR 0x58 |
| 1189 | |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1190 | mailbox = mlx4_alloc_cmd_mailbox(dev); |
| 1191 | if (IS_ERR(mailbox)) |
| 1192 | return PTR_ERR(mailbox); |
| 1193 | outbox = mailbox->buf; |
| 1194 | |
| 1195 | err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_FW, |
Jack Morgenstein | f9baff5 | 2011-12-13 04:10:51 +0000 | [diff] [blame] | 1196 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1197 | if (err) |
| 1198 | goto out; |
| 1199 | |
| 1200 | MLX4_GET(fw_ver, outbox, QUERY_FW_VER_OFFSET); |
| 1201 | /* |
Roland Dreier | 3e1db33 | 2007-06-03 19:47:10 -0700 | [diff] [blame] | 1202 | * FW subminor version is at more significant bits than minor |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1203 | * version, so swap here. |
| 1204 | */ |
| 1205 | dev->caps.fw_ver = (fw_ver & 0xffff00000000ull) | |
| 1206 | ((fw_ver & 0xffff0000ull) >> 16) | |
| 1207 | ((fw_ver & 0x0000ffffull) << 16); |
| 1208 | |
Jack Morgenstein | 752a50c | 2012-06-19 11:21:33 +0300 | [diff] [blame] | 1209 | MLX4_GET(lg, outbox, QUERY_FW_PPF_ID); |
| 1210 | dev->caps.function = lg; |
| 1211 | |
Jack Morgenstein | b91cb3e | 2012-05-30 09:14:53 +0000 | [diff] [blame] | 1212 | if (mlx4_is_slave(dev)) |
| 1213 | goto out; |
| 1214 | |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 1215 | |
Roland Dreier | fe40900 | 2007-06-07 23:24:36 -0700 | [diff] [blame] | 1216 | MLX4_GET(cmd_if_rev, outbox, QUERY_FW_CMD_IF_REV_OFFSET); |
Roland Dreier | 5ae2a7a | 2007-06-18 08:15:02 -0700 | [diff] [blame] | 1217 | if (cmd_if_rev < MLX4_COMMAND_INTERFACE_MIN_REV || |
| 1218 | cmd_if_rev > MLX4_COMMAND_INTERFACE_MAX_REV) { |
Joe Perches | 1a91de2 | 2014-05-07 12:52:57 -0700 | [diff] [blame] | 1219 | mlx4_err(dev, "Installed FW has unsupported command interface revision %d\n", |
Roland Dreier | fe40900 | 2007-06-07 23:24:36 -0700 | [diff] [blame] | 1220 | cmd_if_rev); |
| 1221 | mlx4_err(dev, "(Installed FW version is %d.%d.%03d)\n", |
| 1222 | (int) (dev->caps.fw_ver >> 32), |
| 1223 | (int) (dev->caps.fw_ver >> 16) & 0xffff, |
| 1224 | (int) dev->caps.fw_ver & 0xffff); |
Joe Perches | 1a91de2 | 2014-05-07 12:52:57 -0700 | [diff] [blame] | 1225 | mlx4_err(dev, "This driver version supports only revisions %d to %d\n", |
Roland Dreier | 5ae2a7a | 2007-06-18 08:15:02 -0700 | [diff] [blame] | 1226 | MLX4_COMMAND_INTERFACE_MIN_REV, MLX4_COMMAND_INTERFACE_MAX_REV); |
Roland Dreier | fe40900 | 2007-06-07 23:24:36 -0700 | [diff] [blame] | 1227 | err = -ENODEV; |
| 1228 | goto out; |
| 1229 | } |
| 1230 | |
Roland Dreier | 5ae2a7a | 2007-06-18 08:15:02 -0700 | [diff] [blame] | 1231 | if (cmd_if_rev < MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS) |
| 1232 | dev->flags |= MLX4_FLAG_OLD_PORT_CMDS; |
| 1233 | |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1234 | MLX4_GET(lg, outbox, QUERY_FW_MAX_CMD_OFFSET); |
| 1235 | cmd->max_cmds = 1 << lg; |
| 1236 | |
Roland Dreier | fe40900 | 2007-06-07 23:24:36 -0700 | [diff] [blame] | 1237 | mlx4_dbg(dev, "FW version %d.%d.%03d (cmd intf rev %d), max commands %d\n", |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1238 | (int) (dev->caps.fw_ver >> 32), |
| 1239 | (int) (dev->caps.fw_ver >> 16) & 0xffff, |
| 1240 | (int) dev->caps.fw_ver & 0xffff, |
Roland Dreier | fe40900 | 2007-06-07 23:24:36 -0700 | [diff] [blame] | 1241 | cmd_if_rev, cmd->max_cmds); |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1242 | |
| 1243 | MLX4_GET(fw->catas_offset, outbox, QUERY_FW_ERR_START_OFFSET); |
| 1244 | MLX4_GET(fw->catas_size, outbox, QUERY_FW_ERR_SIZE_OFFSET); |
| 1245 | MLX4_GET(fw->catas_bar, outbox, QUERY_FW_ERR_BAR_OFFSET); |
| 1246 | fw->catas_bar = (fw->catas_bar >> 6) * 2; |
| 1247 | |
| 1248 | mlx4_dbg(dev, "Catastrophic error buffer at 0x%llx, size 0x%x, BAR %d\n", |
| 1249 | (unsigned long long) fw->catas_offset, fw->catas_size, fw->catas_bar); |
| 1250 | |
| 1251 | MLX4_GET(fw->fw_pages, outbox, QUERY_FW_SIZE_OFFSET); |
| 1252 | MLX4_GET(fw->clr_int_base, outbox, QUERY_FW_CLR_INT_BASE_OFFSET); |
| 1253 | MLX4_GET(fw->clr_int_bar, outbox, QUERY_FW_CLR_INT_BAR_OFFSET); |
| 1254 | fw->clr_int_bar = (fw->clr_int_bar >> 6) * 2; |
| 1255 | |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 1256 | MLX4_GET(fw->comm_base, outbox, QUERY_FW_COMM_BASE_OFFSET); |
| 1257 | MLX4_GET(fw->comm_bar, outbox, QUERY_FW_COMM_BAR_OFFSET); |
| 1258 | fw->comm_bar = (fw->comm_bar >> 6) * 2; |
| 1259 | mlx4_dbg(dev, "Communication vector bar:%d offset:0x%llx\n", |
| 1260 | fw->comm_bar, fw->comm_base); |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1261 | mlx4_dbg(dev, "FW size %d KB\n", fw->fw_pages >> 2); |
| 1262 | |
Eugenia Emantayev | ddd8a6c | 2013-04-23 06:06:48 +0000 | [diff] [blame] | 1263 | MLX4_GET(fw->clock_offset, outbox, QUERY_FW_CLOCK_OFFSET); |
| 1264 | MLX4_GET(fw->clock_bar, outbox, QUERY_FW_CLOCK_BAR); |
| 1265 | fw->clock_bar = (fw->clock_bar >> 6) * 2; |
| 1266 | mlx4_dbg(dev, "Internal clock bar:%d offset:0x%llx\n", |
| 1267 | fw->clock_bar, fw->clock_offset); |
| 1268 | |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1269 | /* |
| 1270 | * Round up number of system pages needed in case |
| 1271 | * MLX4_ICM_PAGE_SIZE < PAGE_SIZE. |
| 1272 | */ |
| 1273 | fw->fw_pages = |
| 1274 | ALIGN(fw->fw_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >> |
| 1275 | (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT); |
| 1276 | |
| 1277 | mlx4_dbg(dev, "Clear int @ %llx, BAR %d\n", |
| 1278 | (unsigned long long) fw->clr_int_base, fw->clr_int_bar); |
| 1279 | |
| 1280 | out: |
| 1281 | mlx4_free_cmd_mailbox(dev, mailbox); |
| 1282 | return err; |
| 1283 | } |
| 1284 | |
Jack Morgenstein | b91cb3e | 2012-05-30 09:14:53 +0000 | [diff] [blame] | 1285 | int mlx4_QUERY_FW_wrapper(struct mlx4_dev *dev, int slave, |
| 1286 | struct mlx4_vhcr *vhcr, |
| 1287 | struct mlx4_cmd_mailbox *inbox, |
| 1288 | struct mlx4_cmd_mailbox *outbox, |
| 1289 | struct mlx4_cmd_info *cmd) |
| 1290 | { |
| 1291 | u8 *outbuf; |
| 1292 | int err; |
| 1293 | |
| 1294 | outbuf = outbox->buf; |
| 1295 | err = mlx4_cmd_box(dev, 0, outbox->dma, 0, 0, MLX4_CMD_QUERY_FW, |
| 1296 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); |
| 1297 | if (err) |
| 1298 | return err; |
| 1299 | |
Jack Morgenstein | 752a50c | 2012-06-19 11:21:33 +0300 | [diff] [blame] | 1300 | /* for slaves, set pci PPF ID to invalid and zero out everything |
| 1301 | * else except FW version */ |
Jack Morgenstein | b91cb3e | 2012-05-30 09:14:53 +0000 | [diff] [blame] | 1302 | outbuf[0] = outbuf[1] = 0; |
| 1303 | memset(&outbuf[8], 0, QUERY_FW_OUT_SIZE - 8); |
Jack Morgenstein | 752a50c | 2012-06-19 11:21:33 +0300 | [diff] [blame] | 1304 | outbuf[QUERY_FW_PPF_ID] = MLX4_INVALID_SLAVE_ID; |
| 1305 | |
Jack Morgenstein | b91cb3e | 2012-05-30 09:14:53 +0000 | [diff] [blame] | 1306 | return 0; |
| 1307 | } |
| 1308 | |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1309 | static void get_board_id(void *vsd, char *board_id) |
| 1310 | { |
| 1311 | int i; |
| 1312 | |
| 1313 | #define VSD_OFFSET_SIG1 0x00 |
| 1314 | #define VSD_OFFSET_SIG2 0xde |
| 1315 | #define VSD_OFFSET_MLX_BOARD_ID 0xd0 |
| 1316 | #define VSD_OFFSET_TS_BOARD_ID 0x20 |
| 1317 | |
| 1318 | #define VSD_SIGNATURE_TOPSPIN 0x5ad |
| 1319 | |
| 1320 | memset(board_id, 0, MLX4_BOARD_ID_LEN); |
| 1321 | |
| 1322 | if (be16_to_cpup(vsd + VSD_OFFSET_SIG1) == VSD_SIGNATURE_TOPSPIN && |
| 1323 | be16_to_cpup(vsd + VSD_OFFSET_SIG2) == VSD_SIGNATURE_TOPSPIN) { |
| 1324 | strlcpy(board_id, vsd + VSD_OFFSET_TS_BOARD_ID, MLX4_BOARD_ID_LEN); |
| 1325 | } else { |
| 1326 | /* |
| 1327 | * The board ID is a string but the firmware byte |
| 1328 | * swaps each 4-byte word before passing it back to |
| 1329 | * us. Therefore we need to swab it before printing. |
| 1330 | */ |
| 1331 | for (i = 0; i < 4; ++i) |
| 1332 | ((u32 *) board_id)[i] = |
| 1333 | swab32(*(u32 *) (vsd + VSD_OFFSET_MLX_BOARD_ID + i * 4)); |
| 1334 | } |
| 1335 | } |
| 1336 | |
| 1337 | int mlx4_QUERY_ADAPTER(struct mlx4_dev *dev, struct mlx4_adapter *adapter) |
| 1338 | { |
| 1339 | struct mlx4_cmd_mailbox *mailbox; |
| 1340 | u32 *outbox; |
| 1341 | int err; |
| 1342 | |
| 1343 | #define QUERY_ADAPTER_OUT_SIZE 0x100 |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1344 | #define QUERY_ADAPTER_INTA_PIN_OFFSET 0x10 |
| 1345 | #define QUERY_ADAPTER_VSD_OFFSET 0x20 |
| 1346 | |
| 1347 | mailbox = mlx4_alloc_cmd_mailbox(dev); |
| 1348 | if (IS_ERR(mailbox)) |
| 1349 | return PTR_ERR(mailbox); |
| 1350 | outbox = mailbox->buf; |
| 1351 | |
| 1352 | err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_ADAPTER, |
Jack Morgenstein | f9baff5 | 2011-12-13 04:10:51 +0000 | [diff] [blame] | 1353 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1354 | if (err) |
| 1355 | goto out; |
| 1356 | |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1357 | MLX4_GET(adapter->inta_pin, outbox, QUERY_ADAPTER_INTA_PIN_OFFSET); |
| 1358 | |
| 1359 | get_board_id(outbox + QUERY_ADAPTER_VSD_OFFSET / 4, |
| 1360 | adapter->board_id); |
| 1361 | |
| 1362 | out: |
| 1363 | mlx4_free_cmd_mailbox(dev, mailbox); |
| 1364 | return err; |
| 1365 | } |
| 1366 | |
| 1367 | int mlx4_INIT_HCA(struct mlx4_dev *dev, struct mlx4_init_hca_param *param) |
| 1368 | { |
| 1369 | struct mlx4_cmd_mailbox *mailbox; |
| 1370 | __be32 *inbox; |
| 1371 | int err; |
| 1372 | |
| 1373 | #define INIT_HCA_IN_SIZE 0x200 |
| 1374 | #define INIT_HCA_VERSION_OFFSET 0x000 |
| 1375 | #define INIT_HCA_VERSION 2 |
Or Gerlitz | 7ffdf72 | 2013-12-23 16:09:43 +0200 | [diff] [blame] | 1376 | #define INIT_HCA_VXLAN_OFFSET 0x0c |
Eli Cohen | c57e20dcf | 2009-09-24 11:03:03 -0700 | [diff] [blame] | 1377 | #define INIT_HCA_CACHELINE_SZ_OFFSET 0x0e |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1378 | #define INIT_HCA_FLAGS_OFFSET 0x014 |
| 1379 | #define INIT_HCA_QPC_OFFSET 0x020 |
| 1380 | #define INIT_HCA_QPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x10) |
| 1381 | #define INIT_HCA_LOG_QP_OFFSET (INIT_HCA_QPC_OFFSET + 0x17) |
| 1382 | #define INIT_HCA_SRQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x28) |
| 1383 | #define INIT_HCA_LOG_SRQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x2f) |
| 1384 | #define INIT_HCA_CQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x30) |
| 1385 | #define INIT_HCA_LOG_CQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x37) |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 1386 | #define INIT_HCA_EQE_CQE_OFFSETS (INIT_HCA_QPC_OFFSET + 0x38) |
Ido Shamay | 77507aa | 2014-09-18 11:50:59 +0300 | [diff] [blame^] | 1387 | #define INIT_HCA_EQE_CQE_STRIDE_OFFSET (INIT_HCA_QPC_OFFSET + 0x3b) |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1388 | #define INIT_HCA_ALTC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x40) |
| 1389 | #define INIT_HCA_AUXC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x50) |
| 1390 | #define INIT_HCA_EQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x60) |
| 1391 | #define INIT_HCA_LOG_EQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x67) |
| 1392 | #define INIT_HCA_RDMARC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x70) |
| 1393 | #define INIT_HCA_LOG_RD_OFFSET (INIT_HCA_QPC_OFFSET + 0x77) |
| 1394 | #define INIT_HCA_MCAST_OFFSET 0x0c0 |
| 1395 | #define INIT_HCA_MC_BASE_OFFSET (INIT_HCA_MCAST_OFFSET + 0x00) |
| 1396 | #define INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x12) |
| 1397 | #define INIT_HCA_LOG_MC_HASH_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x16) |
Yevgeny Petrilin | 1679200 | 2011-03-22 22:38:31 +0000 | [diff] [blame] | 1398 | #define INIT_HCA_UC_STEERING_OFFSET (INIT_HCA_MCAST_OFFSET + 0x18) |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1399 | #define INIT_HCA_LOG_MC_TABLE_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x1b) |
Hadar Hen Zion | 0ff1fb6 | 2012-07-05 04:03:46 +0000 | [diff] [blame] | 1400 | #define INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN 0x6 |
| 1401 | #define INIT_HCA_FS_PARAM_OFFSET 0x1d0 |
| 1402 | #define INIT_HCA_FS_BASE_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x00) |
| 1403 | #define INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x12) |
| 1404 | #define INIT_HCA_FS_LOG_TABLE_SZ_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x1b) |
| 1405 | #define INIT_HCA_FS_ETH_BITS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x21) |
| 1406 | #define INIT_HCA_FS_ETH_NUM_ADDRS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x22) |
| 1407 | #define INIT_HCA_FS_IB_BITS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x25) |
| 1408 | #define INIT_HCA_FS_IB_NUM_ADDRS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x26) |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1409 | #define INIT_HCA_TPT_OFFSET 0x0f0 |
| 1410 | #define INIT_HCA_DMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x00) |
Shani Michaeli | e448834 | 2013-02-06 16:19:11 +0000 | [diff] [blame] | 1411 | #define INIT_HCA_TPT_MW_OFFSET (INIT_HCA_TPT_OFFSET + 0x08) |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1412 | #define INIT_HCA_LOG_MPT_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x0b) |
| 1413 | #define INIT_HCA_MTT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x10) |
| 1414 | #define INIT_HCA_CMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x18) |
| 1415 | #define INIT_HCA_UAR_OFFSET 0x120 |
| 1416 | #define INIT_HCA_LOG_UAR_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0a) |
| 1417 | #define INIT_HCA_UAR_PAGE_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0b) |
| 1418 | |
| 1419 | mailbox = mlx4_alloc_cmd_mailbox(dev); |
| 1420 | if (IS_ERR(mailbox)) |
| 1421 | return PTR_ERR(mailbox); |
| 1422 | inbox = mailbox->buf; |
| 1423 | |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1424 | *((u8 *) mailbox->buf + INIT_HCA_VERSION_OFFSET) = INIT_HCA_VERSION; |
| 1425 | |
Eli Cohen | c57e20dcf | 2009-09-24 11:03:03 -0700 | [diff] [blame] | 1426 | *((u8 *) mailbox->buf + INIT_HCA_CACHELINE_SZ_OFFSET) = |
| 1427 | (ilog2(cache_line_size()) - 4) << 5; |
| 1428 | |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1429 | #if defined(__LITTLE_ENDIAN) |
| 1430 | *(inbox + INIT_HCA_FLAGS_OFFSET / 4) &= ~cpu_to_be32(1 << 1); |
| 1431 | #elif defined(__BIG_ENDIAN) |
| 1432 | *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 1); |
| 1433 | #else |
| 1434 | #error Host endianness not defined |
| 1435 | #endif |
| 1436 | /* Check port for UD address vector: */ |
| 1437 | *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1); |
| 1438 | |
Eli Cohen | 8ff095e | 2008-04-16 21:01:10 -0700 | [diff] [blame] | 1439 | /* Enable IPoIB checksumming if we can: */ |
| 1440 | if (dev->caps.flags & MLX4_DEV_CAP_FLAG_IPOIB_CSUM) |
| 1441 | *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 3); |
| 1442 | |
Jack Morgenstein | 51f5f0e | 2008-07-22 14:19:37 -0700 | [diff] [blame] | 1443 | /* Enable QoS support if module parameter set */ |
| 1444 | if (enable_qos) |
| 1445 | *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 2); |
| 1446 | |
Or Gerlitz | f2a3f6a | 2011-06-15 14:47:14 +0000 | [diff] [blame] | 1447 | /* enable counters */ |
| 1448 | if (dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS) |
| 1449 | *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 4); |
| 1450 | |
Or Gerlitz | 08ff323 | 2012-10-21 14:59:24 +0000 | [diff] [blame] | 1451 | /* CX3 is capable of extending CQEs/EQEs from 32 to 64 bytes */ |
| 1452 | if (dev->caps.flags & MLX4_DEV_CAP_FLAG_64B_EQE) { |
| 1453 | *(inbox + INIT_HCA_EQE_CQE_OFFSETS / 4) |= cpu_to_be32(1 << 29); |
| 1454 | dev->caps.eqe_size = 64; |
| 1455 | dev->caps.eqe_factor = 1; |
| 1456 | } else { |
| 1457 | dev->caps.eqe_size = 32; |
| 1458 | dev->caps.eqe_factor = 0; |
| 1459 | } |
| 1460 | |
| 1461 | if (dev->caps.flags & MLX4_DEV_CAP_FLAG_64B_CQE) { |
| 1462 | *(inbox + INIT_HCA_EQE_CQE_OFFSETS / 4) |= cpu_to_be32(1 << 30); |
| 1463 | dev->caps.cqe_size = 64; |
Ido Shamay | 77507aa | 2014-09-18 11:50:59 +0300 | [diff] [blame^] | 1464 | dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE; |
Or Gerlitz | 08ff323 | 2012-10-21 14:59:24 +0000 | [diff] [blame] | 1465 | } else { |
| 1466 | dev->caps.cqe_size = 32; |
| 1467 | } |
| 1468 | |
Ido Shamay | 77507aa | 2014-09-18 11:50:59 +0300 | [diff] [blame^] | 1469 | /* CX3 is capable of extending CQEs\EQEs to strides larger than 64B */ |
| 1470 | if ((dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_EQE_STRIDE) && |
| 1471 | (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_CQE_STRIDE)) { |
| 1472 | dev->caps.eqe_size = cache_line_size(); |
| 1473 | dev->caps.cqe_size = cache_line_size(); |
| 1474 | dev->caps.eqe_factor = 0; |
| 1475 | MLX4_PUT(inbox, (u8)((ilog2(dev->caps.eqe_size) - 5) << 4 | |
| 1476 | (ilog2(dev->caps.eqe_size) - 5)), |
| 1477 | INIT_HCA_EQE_CQE_STRIDE_OFFSET); |
| 1478 | |
| 1479 | /* User still need to know to support CQE > 32B */ |
| 1480 | dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE; |
| 1481 | } |
| 1482 | |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1483 | /* QPC/EEC/CQC/EQC/RDMARC attributes */ |
| 1484 | |
| 1485 | MLX4_PUT(inbox, param->qpc_base, INIT_HCA_QPC_BASE_OFFSET); |
| 1486 | MLX4_PUT(inbox, param->log_num_qps, INIT_HCA_LOG_QP_OFFSET); |
| 1487 | MLX4_PUT(inbox, param->srqc_base, INIT_HCA_SRQC_BASE_OFFSET); |
| 1488 | MLX4_PUT(inbox, param->log_num_srqs, INIT_HCA_LOG_SRQ_OFFSET); |
| 1489 | MLX4_PUT(inbox, param->cqc_base, INIT_HCA_CQC_BASE_OFFSET); |
| 1490 | MLX4_PUT(inbox, param->log_num_cqs, INIT_HCA_LOG_CQ_OFFSET); |
| 1491 | MLX4_PUT(inbox, param->altc_base, INIT_HCA_ALTC_BASE_OFFSET); |
| 1492 | MLX4_PUT(inbox, param->auxc_base, INIT_HCA_AUXC_BASE_OFFSET); |
| 1493 | MLX4_PUT(inbox, param->eqc_base, INIT_HCA_EQC_BASE_OFFSET); |
| 1494 | MLX4_PUT(inbox, param->log_num_eqs, INIT_HCA_LOG_EQ_OFFSET); |
| 1495 | MLX4_PUT(inbox, param->rdmarc_base, INIT_HCA_RDMARC_BASE_OFFSET); |
| 1496 | MLX4_PUT(inbox, param->log_rd_per_qp, INIT_HCA_LOG_RD_OFFSET); |
| 1497 | |
Hadar Hen Zion | 0ff1fb6 | 2012-07-05 04:03:46 +0000 | [diff] [blame] | 1498 | /* steering attributes */ |
| 1499 | if (dev->caps.steering_mode == |
| 1500 | MLX4_STEERING_MODE_DEVICE_MANAGED) { |
| 1501 | *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= |
| 1502 | cpu_to_be32(1 << |
| 1503 | INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN); |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1504 | |
Hadar Hen Zion | 0ff1fb6 | 2012-07-05 04:03:46 +0000 | [diff] [blame] | 1505 | MLX4_PUT(inbox, param->mc_base, INIT_HCA_FS_BASE_OFFSET); |
| 1506 | MLX4_PUT(inbox, param->log_mc_entry_sz, |
| 1507 | INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET); |
| 1508 | MLX4_PUT(inbox, param->log_mc_table_sz, |
| 1509 | INIT_HCA_FS_LOG_TABLE_SZ_OFFSET); |
| 1510 | /* Enable Ethernet flow steering |
| 1511 | * with udp unicast and tcp unicast |
| 1512 | */ |
Hadar Hen Zion | 23537b7 | 2013-01-30 23:07:09 +0000 | [diff] [blame] | 1513 | MLX4_PUT(inbox, (u8) (MLX4_FS_UDP_UC_EN | MLX4_FS_TCP_UC_EN), |
Hadar Hen Zion | 0ff1fb6 | 2012-07-05 04:03:46 +0000 | [diff] [blame] | 1514 | INIT_HCA_FS_ETH_BITS_OFFSET); |
| 1515 | MLX4_PUT(inbox, (u16) MLX4_FS_NUM_OF_L2_ADDR, |
| 1516 | INIT_HCA_FS_ETH_NUM_ADDRS_OFFSET); |
| 1517 | /* Enable IPoIB flow steering |
| 1518 | * with udp unicast and tcp unicast |
| 1519 | */ |
Hadar Hen Zion | 23537b7 | 2013-01-30 23:07:09 +0000 | [diff] [blame] | 1520 | MLX4_PUT(inbox, (u8) (MLX4_FS_UDP_UC_EN | MLX4_FS_TCP_UC_EN), |
Hadar Hen Zion | 0ff1fb6 | 2012-07-05 04:03:46 +0000 | [diff] [blame] | 1521 | INIT_HCA_FS_IB_BITS_OFFSET); |
| 1522 | MLX4_PUT(inbox, (u16) MLX4_FS_NUM_OF_L2_ADDR, |
| 1523 | INIT_HCA_FS_IB_NUM_ADDRS_OFFSET); |
| 1524 | } else { |
| 1525 | MLX4_PUT(inbox, param->mc_base, INIT_HCA_MC_BASE_OFFSET); |
| 1526 | MLX4_PUT(inbox, param->log_mc_entry_sz, |
| 1527 | INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET); |
| 1528 | MLX4_PUT(inbox, param->log_mc_hash_sz, |
| 1529 | INIT_HCA_LOG_MC_HASH_SZ_OFFSET); |
| 1530 | MLX4_PUT(inbox, param->log_mc_table_sz, |
| 1531 | INIT_HCA_LOG_MC_TABLE_SZ_OFFSET); |
| 1532 | if (dev->caps.steering_mode == MLX4_STEERING_MODE_B0) |
| 1533 | MLX4_PUT(inbox, (u8) (1 << 3), |
| 1534 | INIT_HCA_UC_STEERING_OFFSET); |
| 1535 | } |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1536 | |
| 1537 | /* TPT attributes */ |
| 1538 | |
| 1539 | MLX4_PUT(inbox, param->dmpt_base, INIT_HCA_DMPT_BASE_OFFSET); |
Shani Michaeli | e448834 | 2013-02-06 16:19:11 +0000 | [diff] [blame] | 1540 | MLX4_PUT(inbox, param->mw_enabled, INIT_HCA_TPT_MW_OFFSET); |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1541 | MLX4_PUT(inbox, param->log_mpt_sz, INIT_HCA_LOG_MPT_SZ_OFFSET); |
| 1542 | MLX4_PUT(inbox, param->mtt_base, INIT_HCA_MTT_BASE_OFFSET); |
| 1543 | MLX4_PUT(inbox, param->cmpt_base, INIT_HCA_CMPT_BASE_OFFSET); |
| 1544 | |
| 1545 | /* UAR attributes */ |
| 1546 | |
Jack Morgenstein | ab9c17a | 2011-12-13 04:18:30 +0000 | [diff] [blame] | 1547 | MLX4_PUT(inbox, param->uar_page_sz, INIT_HCA_UAR_PAGE_SZ_OFFSET); |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1548 | MLX4_PUT(inbox, param->log_uar_sz, INIT_HCA_LOG_UAR_SZ_OFFSET); |
| 1549 | |
Or Gerlitz | 7ffdf72 | 2013-12-23 16:09:43 +0200 | [diff] [blame] | 1550 | /* set parser VXLAN attributes */ |
| 1551 | if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS) { |
| 1552 | u8 parser_params = 0; |
| 1553 | MLX4_PUT(inbox, parser_params, INIT_HCA_VXLAN_OFFSET); |
| 1554 | } |
| 1555 | |
Jack Morgenstein | f9baff5 | 2011-12-13 04:10:51 +0000 | [diff] [blame] | 1556 | err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_INIT_HCA, 10000, |
| 1557 | MLX4_CMD_NATIVE); |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1558 | |
| 1559 | if (err) |
| 1560 | mlx4_err(dev, "INIT_HCA returns %d\n", err); |
| 1561 | |
| 1562 | mlx4_free_cmd_mailbox(dev, mailbox); |
| 1563 | return err; |
| 1564 | } |
| 1565 | |
Jack Morgenstein | ab9c17a | 2011-12-13 04:18:30 +0000 | [diff] [blame] | 1566 | int mlx4_QUERY_HCA(struct mlx4_dev *dev, |
| 1567 | struct mlx4_init_hca_param *param) |
| 1568 | { |
| 1569 | struct mlx4_cmd_mailbox *mailbox; |
| 1570 | __be32 *outbox; |
Jack Morgenstein | 7b8157b | 2012-12-06 17:11:59 +0000 | [diff] [blame] | 1571 | u32 dword_field; |
Jack Morgenstein | ab9c17a | 2011-12-13 04:18:30 +0000 | [diff] [blame] | 1572 | int err; |
Or Gerlitz | 08ff323 | 2012-10-21 14:59:24 +0000 | [diff] [blame] | 1573 | u8 byte_field; |
Jack Morgenstein | ab9c17a | 2011-12-13 04:18:30 +0000 | [diff] [blame] | 1574 | |
| 1575 | #define QUERY_HCA_GLOBAL_CAPS_OFFSET 0x04 |
Eugenia Emantayev | ddd8a6c | 2013-04-23 06:06:48 +0000 | [diff] [blame] | 1576 | #define QUERY_HCA_CORE_CLOCK_OFFSET 0x0c |
Jack Morgenstein | ab9c17a | 2011-12-13 04:18:30 +0000 | [diff] [blame] | 1577 | |
| 1578 | mailbox = mlx4_alloc_cmd_mailbox(dev); |
| 1579 | if (IS_ERR(mailbox)) |
| 1580 | return PTR_ERR(mailbox); |
| 1581 | outbox = mailbox->buf; |
| 1582 | |
| 1583 | err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, |
| 1584 | MLX4_CMD_QUERY_HCA, |
| 1585 | MLX4_CMD_TIME_CLASS_B, |
| 1586 | !mlx4_is_slave(dev)); |
| 1587 | if (err) |
| 1588 | goto out; |
| 1589 | |
| 1590 | MLX4_GET(param->global_caps, outbox, QUERY_HCA_GLOBAL_CAPS_OFFSET); |
Eugenia Emantayev | ddd8a6c | 2013-04-23 06:06:48 +0000 | [diff] [blame] | 1591 | MLX4_GET(param->hca_core_clock, outbox, QUERY_HCA_CORE_CLOCK_OFFSET); |
Jack Morgenstein | ab9c17a | 2011-12-13 04:18:30 +0000 | [diff] [blame] | 1592 | |
| 1593 | /* QPC/EEC/CQC/EQC/RDMARC attributes */ |
| 1594 | |
| 1595 | MLX4_GET(param->qpc_base, outbox, INIT_HCA_QPC_BASE_OFFSET); |
| 1596 | MLX4_GET(param->log_num_qps, outbox, INIT_HCA_LOG_QP_OFFSET); |
| 1597 | MLX4_GET(param->srqc_base, outbox, INIT_HCA_SRQC_BASE_OFFSET); |
| 1598 | MLX4_GET(param->log_num_srqs, outbox, INIT_HCA_LOG_SRQ_OFFSET); |
| 1599 | MLX4_GET(param->cqc_base, outbox, INIT_HCA_CQC_BASE_OFFSET); |
| 1600 | MLX4_GET(param->log_num_cqs, outbox, INIT_HCA_LOG_CQ_OFFSET); |
| 1601 | MLX4_GET(param->altc_base, outbox, INIT_HCA_ALTC_BASE_OFFSET); |
| 1602 | MLX4_GET(param->auxc_base, outbox, INIT_HCA_AUXC_BASE_OFFSET); |
| 1603 | MLX4_GET(param->eqc_base, outbox, INIT_HCA_EQC_BASE_OFFSET); |
| 1604 | MLX4_GET(param->log_num_eqs, outbox, INIT_HCA_LOG_EQ_OFFSET); |
| 1605 | MLX4_GET(param->rdmarc_base, outbox, INIT_HCA_RDMARC_BASE_OFFSET); |
| 1606 | MLX4_GET(param->log_rd_per_qp, outbox, INIT_HCA_LOG_RD_OFFSET); |
| 1607 | |
Jack Morgenstein | 7b8157b | 2012-12-06 17:11:59 +0000 | [diff] [blame] | 1608 | MLX4_GET(dword_field, outbox, INIT_HCA_FLAGS_OFFSET); |
| 1609 | if (dword_field & (1 << INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN)) { |
| 1610 | param->steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED; |
| 1611 | } else { |
| 1612 | MLX4_GET(byte_field, outbox, INIT_HCA_UC_STEERING_OFFSET); |
| 1613 | if (byte_field & 0x8) |
| 1614 | param->steering_mode = MLX4_STEERING_MODE_B0; |
| 1615 | else |
| 1616 | param->steering_mode = MLX4_STEERING_MODE_A0; |
| 1617 | } |
Hadar Hen Zion | 0ff1fb6 | 2012-07-05 04:03:46 +0000 | [diff] [blame] | 1618 | /* steering attributes */ |
Jack Morgenstein | 7b8157b | 2012-12-06 17:11:59 +0000 | [diff] [blame] | 1619 | if (param->steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) { |
Hadar Hen Zion | 0ff1fb6 | 2012-07-05 04:03:46 +0000 | [diff] [blame] | 1620 | MLX4_GET(param->mc_base, outbox, INIT_HCA_FS_BASE_OFFSET); |
| 1621 | MLX4_GET(param->log_mc_entry_sz, outbox, |
| 1622 | INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET); |
| 1623 | MLX4_GET(param->log_mc_table_sz, outbox, |
| 1624 | INIT_HCA_FS_LOG_TABLE_SZ_OFFSET); |
| 1625 | } else { |
| 1626 | MLX4_GET(param->mc_base, outbox, INIT_HCA_MC_BASE_OFFSET); |
| 1627 | MLX4_GET(param->log_mc_entry_sz, outbox, |
| 1628 | INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET); |
| 1629 | MLX4_GET(param->log_mc_hash_sz, outbox, |
| 1630 | INIT_HCA_LOG_MC_HASH_SZ_OFFSET); |
| 1631 | MLX4_GET(param->log_mc_table_sz, outbox, |
| 1632 | INIT_HCA_LOG_MC_TABLE_SZ_OFFSET); |
| 1633 | } |
Jack Morgenstein | ab9c17a | 2011-12-13 04:18:30 +0000 | [diff] [blame] | 1634 | |
Or Gerlitz | 08ff323 | 2012-10-21 14:59:24 +0000 | [diff] [blame] | 1635 | /* CX3 is capable of extending CQEs/EQEs from 32 to 64 bytes */ |
| 1636 | MLX4_GET(byte_field, outbox, INIT_HCA_EQE_CQE_OFFSETS); |
| 1637 | if (byte_field & 0x20) /* 64-bytes eqe enabled */ |
| 1638 | param->dev_cap_enabled |= MLX4_DEV_CAP_64B_EQE_ENABLED; |
| 1639 | if (byte_field & 0x40) /* 64-bytes cqe enabled */ |
| 1640 | param->dev_cap_enabled |= MLX4_DEV_CAP_64B_CQE_ENABLED; |
| 1641 | |
Ido Shamay | 77507aa | 2014-09-18 11:50:59 +0300 | [diff] [blame^] | 1642 | /* CX3 is capable of extending CQEs\EQEs to strides larger than 64B */ |
| 1643 | MLX4_GET(byte_field, outbox, INIT_HCA_EQE_CQE_STRIDE_OFFSET); |
| 1644 | if (byte_field) { |
| 1645 | param->dev_cap_enabled |= MLX4_DEV_CAP_64B_EQE_ENABLED; |
| 1646 | param->dev_cap_enabled |= MLX4_DEV_CAP_64B_CQE_ENABLED; |
| 1647 | param->cqe_size = 1 << ((byte_field & |
| 1648 | MLX4_CQE_SIZE_MASK_STRIDE) + 5); |
| 1649 | param->eqe_size = 1 << (((byte_field & |
| 1650 | MLX4_EQE_SIZE_MASK_STRIDE) >> 4) + 5); |
| 1651 | } |
| 1652 | |
Jack Morgenstein | ab9c17a | 2011-12-13 04:18:30 +0000 | [diff] [blame] | 1653 | /* TPT attributes */ |
| 1654 | |
| 1655 | MLX4_GET(param->dmpt_base, outbox, INIT_HCA_DMPT_BASE_OFFSET); |
Shani Michaeli | e448834 | 2013-02-06 16:19:11 +0000 | [diff] [blame] | 1656 | MLX4_GET(param->mw_enabled, outbox, INIT_HCA_TPT_MW_OFFSET); |
Jack Morgenstein | ab9c17a | 2011-12-13 04:18:30 +0000 | [diff] [blame] | 1657 | MLX4_GET(param->log_mpt_sz, outbox, INIT_HCA_LOG_MPT_SZ_OFFSET); |
| 1658 | MLX4_GET(param->mtt_base, outbox, INIT_HCA_MTT_BASE_OFFSET); |
| 1659 | MLX4_GET(param->cmpt_base, outbox, INIT_HCA_CMPT_BASE_OFFSET); |
| 1660 | |
| 1661 | /* UAR attributes */ |
| 1662 | |
| 1663 | MLX4_GET(param->uar_page_sz, outbox, INIT_HCA_UAR_PAGE_SZ_OFFSET); |
| 1664 | MLX4_GET(param->log_uar_sz, outbox, INIT_HCA_LOG_UAR_SZ_OFFSET); |
| 1665 | |
| 1666 | out: |
| 1667 | mlx4_free_cmd_mailbox(dev, mailbox); |
| 1668 | |
| 1669 | return err; |
| 1670 | } |
| 1671 | |
Jack Morgenstein | 980e900 | 2012-08-03 08:40:53 +0000 | [diff] [blame] | 1672 | /* for IB-type ports only in SRIOV mode. Checks that both proxy QP0 |
| 1673 | * and real QP0 are active, so that the paravirtualized QP0 is ready |
| 1674 | * to operate */ |
| 1675 | static int check_qp0_state(struct mlx4_dev *dev, int function, int port) |
| 1676 | { |
| 1677 | struct mlx4_priv *priv = mlx4_priv(dev); |
| 1678 | /* irrelevant if not infiniband */ |
| 1679 | if (priv->mfunc.master.qp0_state[port].proxy_qp0_active && |
| 1680 | priv->mfunc.master.qp0_state[port].qp0_active) |
| 1681 | return 1; |
| 1682 | return 0; |
| 1683 | } |
| 1684 | |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 1685 | int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave, |
| 1686 | struct mlx4_vhcr *vhcr, |
| 1687 | struct mlx4_cmd_mailbox *inbox, |
| 1688 | struct mlx4_cmd_mailbox *outbox, |
| 1689 | struct mlx4_cmd_info *cmd) |
| 1690 | { |
| 1691 | struct mlx4_priv *priv = mlx4_priv(dev); |
Matan Barak | 449fc48 | 2014-03-19 18:11:52 +0200 | [diff] [blame] | 1692 | int port = mlx4_slave_convert_port(dev, slave, vhcr->in_modifier); |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 1693 | int err; |
| 1694 | |
Matan Barak | 449fc48 | 2014-03-19 18:11:52 +0200 | [diff] [blame] | 1695 | if (port < 0) |
| 1696 | return -EINVAL; |
| 1697 | |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 1698 | if (priv->mfunc.master.slave_state[slave].init_port_mask & (1 << port)) |
| 1699 | return 0; |
| 1700 | |
Jack Morgenstein | 980e900 | 2012-08-03 08:40:53 +0000 | [diff] [blame] | 1701 | if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB) { |
| 1702 | /* Enable port only if it was previously disabled */ |
| 1703 | if (!priv->mfunc.master.init_port_ref[port]) { |
| 1704 | err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT, |
| 1705 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); |
| 1706 | if (err) |
| 1707 | return err; |
| 1708 | } |
| 1709 | priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port); |
| 1710 | } else { |
| 1711 | if (slave == mlx4_master_func_num(dev)) { |
| 1712 | if (check_qp0_state(dev, slave, port) && |
| 1713 | !priv->mfunc.master.qp0_state[port].port_active) { |
| 1714 | err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT, |
| 1715 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); |
| 1716 | if (err) |
| 1717 | return err; |
| 1718 | priv->mfunc.master.qp0_state[port].port_active = 1; |
| 1719 | priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port); |
| 1720 | } |
| 1721 | } else |
| 1722 | priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port); |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 1723 | } |
| 1724 | ++priv->mfunc.master.init_port_ref[port]; |
| 1725 | return 0; |
| 1726 | } |
| 1727 | |
Roland Dreier | 5ae2a7a | 2007-06-18 08:15:02 -0700 | [diff] [blame] | 1728 | int mlx4_INIT_PORT(struct mlx4_dev *dev, int port) |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1729 | { |
| 1730 | struct mlx4_cmd_mailbox *mailbox; |
| 1731 | u32 *inbox; |
| 1732 | int err; |
| 1733 | u32 flags; |
Roland Dreier | 5ae2a7a | 2007-06-18 08:15:02 -0700 | [diff] [blame] | 1734 | u16 field; |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1735 | |
Roland Dreier | 5ae2a7a | 2007-06-18 08:15:02 -0700 | [diff] [blame] | 1736 | if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) { |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1737 | #define INIT_PORT_IN_SIZE 256 |
| 1738 | #define INIT_PORT_FLAGS_OFFSET 0x00 |
| 1739 | #define INIT_PORT_FLAG_SIG (1 << 18) |
| 1740 | #define INIT_PORT_FLAG_NG (1 << 17) |
| 1741 | #define INIT_PORT_FLAG_G0 (1 << 16) |
| 1742 | #define INIT_PORT_VL_SHIFT 4 |
| 1743 | #define INIT_PORT_PORT_WIDTH_SHIFT 8 |
| 1744 | #define INIT_PORT_MTU_OFFSET 0x04 |
| 1745 | #define INIT_PORT_MAX_GID_OFFSET 0x06 |
| 1746 | #define INIT_PORT_MAX_PKEY_OFFSET 0x0a |
| 1747 | #define INIT_PORT_GUID0_OFFSET 0x10 |
| 1748 | #define INIT_PORT_NODE_GUID_OFFSET 0x18 |
| 1749 | #define INIT_PORT_SI_GUID_OFFSET 0x20 |
| 1750 | |
Roland Dreier | 5ae2a7a | 2007-06-18 08:15:02 -0700 | [diff] [blame] | 1751 | mailbox = mlx4_alloc_cmd_mailbox(dev); |
| 1752 | if (IS_ERR(mailbox)) |
| 1753 | return PTR_ERR(mailbox); |
| 1754 | inbox = mailbox->buf; |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1755 | |
Roland Dreier | 5ae2a7a | 2007-06-18 08:15:02 -0700 | [diff] [blame] | 1756 | flags = 0; |
| 1757 | flags |= (dev->caps.vl_cap[port] & 0xf) << INIT_PORT_VL_SHIFT; |
| 1758 | flags |= (dev->caps.port_width_cap[port] & 0xf) << INIT_PORT_PORT_WIDTH_SHIFT; |
| 1759 | MLX4_PUT(inbox, flags, INIT_PORT_FLAGS_OFFSET); |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1760 | |
Yevgeny Petrilin | b79acb4 | 2008-10-22 10:56:48 -0700 | [diff] [blame] | 1761 | field = 128 << dev->caps.ib_mtu_cap[port]; |
Roland Dreier | 5ae2a7a | 2007-06-18 08:15:02 -0700 | [diff] [blame] | 1762 | MLX4_PUT(inbox, field, INIT_PORT_MTU_OFFSET); |
| 1763 | field = dev->caps.gid_table_len[port]; |
| 1764 | MLX4_PUT(inbox, field, INIT_PORT_MAX_GID_OFFSET); |
| 1765 | field = dev->caps.pkey_table_len[port]; |
| 1766 | MLX4_PUT(inbox, field, INIT_PORT_MAX_PKEY_OFFSET); |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1767 | |
Roland Dreier | 5ae2a7a | 2007-06-18 08:15:02 -0700 | [diff] [blame] | 1768 | err = mlx4_cmd(dev, mailbox->dma, port, 0, MLX4_CMD_INIT_PORT, |
Jack Morgenstein | f9baff5 | 2011-12-13 04:10:51 +0000 | [diff] [blame] | 1769 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1770 | |
Roland Dreier | 5ae2a7a | 2007-06-18 08:15:02 -0700 | [diff] [blame] | 1771 | mlx4_free_cmd_mailbox(dev, mailbox); |
| 1772 | } else |
| 1773 | err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT, |
Jack Morgenstein | f9baff5 | 2011-12-13 04:10:51 +0000 | [diff] [blame] | 1774 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED); |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1775 | |
| 1776 | return err; |
| 1777 | } |
| 1778 | EXPORT_SYMBOL_GPL(mlx4_INIT_PORT); |
| 1779 | |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 1780 | int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave, |
| 1781 | struct mlx4_vhcr *vhcr, |
| 1782 | struct mlx4_cmd_mailbox *inbox, |
| 1783 | struct mlx4_cmd_mailbox *outbox, |
| 1784 | struct mlx4_cmd_info *cmd) |
| 1785 | { |
| 1786 | struct mlx4_priv *priv = mlx4_priv(dev); |
Matan Barak | 449fc48 | 2014-03-19 18:11:52 +0200 | [diff] [blame] | 1787 | int port = mlx4_slave_convert_port(dev, slave, vhcr->in_modifier); |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 1788 | int err; |
| 1789 | |
Matan Barak | 449fc48 | 2014-03-19 18:11:52 +0200 | [diff] [blame] | 1790 | if (port < 0) |
| 1791 | return -EINVAL; |
| 1792 | |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 1793 | if (!(priv->mfunc.master.slave_state[slave].init_port_mask & |
| 1794 | (1 << port))) |
| 1795 | return 0; |
| 1796 | |
Jack Morgenstein | 980e900 | 2012-08-03 08:40:53 +0000 | [diff] [blame] | 1797 | if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB) { |
| 1798 | if (priv->mfunc.master.init_port_ref[port] == 1) { |
| 1799 | err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, |
| 1800 | 1000, MLX4_CMD_NATIVE); |
| 1801 | if (err) |
| 1802 | return err; |
| 1803 | } |
| 1804 | priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port); |
| 1805 | } else { |
| 1806 | /* infiniband port */ |
| 1807 | if (slave == mlx4_master_func_num(dev)) { |
| 1808 | if (!priv->mfunc.master.qp0_state[port].qp0_active && |
| 1809 | priv->mfunc.master.qp0_state[port].port_active) { |
| 1810 | err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, |
| 1811 | 1000, MLX4_CMD_NATIVE); |
| 1812 | if (err) |
| 1813 | return err; |
| 1814 | priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port); |
| 1815 | priv->mfunc.master.qp0_state[port].port_active = 0; |
| 1816 | } |
| 1817 | } else |
| 1818 | priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port); |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 1819 | } |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 1820 | --priv->mfunc.master.init_port_ref[port]; |
| 1821 | return 0; |
| 1822 | } |
| 1823 | |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1824 | int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port) |
| 1825 | { |
Jack Morgenstein | f9baff5 | 2011-12-13 04:10:51 +0000 | [diff] [blame] | 1826 | return mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, 1000, |
| 1827 | MLX4_CMD_WRAPPED); |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1828 | } |
| 1829 | EXPORT_SYMBOL_GPL(mlx4_CLOSE_PORT); |
| 1830 | |
| 1831 | int mlx4_CLOSE_HCA(struct mlx4_dev *dev, int panic) |
| 1832 | { |
Jack Morgenstein | f9baff5 | 2011-12-13 04:10:51 +0000 | [diff] [blame] | 1833 | return mlx4_cmd(dev, 0, 0, panic, MLX4_CMD_CLOSE_HCA, 1000, |
| 1834 | MLX4_CMD_NATIVE); |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1835 | } |
| 1836 | |
Or Gerlitz | d18f141 | 2014-03-27 14:02:03 +0200 | [diff] [blame] | 1837 | struct mlx4_config_dev { |
| 1838 | __be32 update_flags; |
| 1839 | __be32 rsdv1[3]; |
| 1840 | __be16 vxlan_udp_dport; |
| 1841 | __be16 rsvd2; |
| 1842 | }; |
| 1843 | |
| 1844 | #define MLX4_VXLAN_UDP_DPORT (1 << 0) |
| 1845 | |
| 1846 | static int mlx4_CONFIG_DEV(struct mlx4_dev *dev, struct mlx4_config_dev *config_dev) |
| 1847 | { |
| 1848 | int err; |
| 1849 | struct mlx4_cmd_mailbox *mailbox; |
| 1850 | |
| 1851 | mailbox = mlx4_alloc_cmd_mailbox(dev); |
| 1852 | if (IS_ERR(mailbox)) |
| 1853 | return PTR_ERR(mailbox); |
| 1854 | |
| 1855 | memcpy(mailbox->buf, config_dev, sizeof(*config_dev)); |
| 1856 | |
| 1857 | err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_CONFIG_DEV, |
| 1858 | MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); |
| 1859 | |
| 1860 | mlx4_free_cmd_mailbox(dev, mailbox); |
| 1861 | return err; |
| 1862 | } |
| 1863 | |
| 1864 | int mlx4_config_vxlan_port(struct mlx4_dev *dev, __be16 udp_port) |
| 1865 | { |
| 1866 | struct mlx4_config_dev config_dev; |
| 1867 | |
| 1868 | memset(&config_dev, 0, sizeof(config_dev)); |
| 1869 | config_dev.update_flags = cpu_to_be32(MLX4_VXLAN_UDP_DPORT); |
| 1870 | config_dev.vxlan_udp_dport = udp_port; |
| 1871 | |
| 1872 | return mlx4_CONFIG_DEV(dev, &config_dev); |
| 1873 | } |
| 1874 | EXPORT_SYMBOL_GPL(mlx4_config_vxlan_port); |
| 1875 | |
| 1876 | |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1877 | int mlx4_SET_ICM_SIZE(struct mlx4_dev *dev, u64 icm_size, u64 *aux_pages) |
| 1878 | { |
| 1879 | int ret = mlx4_cmd_imm(dev, icm_size, aux_pages, 0, 0, |
| 1880 | MLX4_CMD_SET_ICM_SIZE, |
Jack Morgenstein | f9baff5 | 2011-12-13 04:10:51 +0000 | [diff] [blame] | 1881 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1882 | if (ret) |
| 1883 | return ret; |
| 1884 | |
| 1885 | /* |
| 1886 | * Round up number of system pages needed in case |
| 1887 | * MLX4_ICM_PAGE_SIZE < PAGE_SIZE. |
| 1888 | */ |
| 1889 | *aux_pages = ALIGN(*aux_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >> |
| 1890 | (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT); |
| 1891 | |
| 1892 | return 0; |
| 1893 | } |
| 1894 | |
| 1895 | int mlx4_NOP(struct mlx4_dev *dev) |
| 1896 | { |
| 1897 | /* Input modifier of 0x1f means "finish as soon as possible." */ |
Jack Morgenstein | f9baff5 | 2011-12-13 04:10:51 +0000 | [diff] [blame] | 1898 | return mlx4_cmd(dev, 0, 0x1f, 0, MLX4_CMD_NOP, 100, MLX4_CMD_NATIVE); |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1899 | } |
Yevgeny Petrilin | 14c07b1 | 2011-03-22 22:37:59 +0000 | [diff] [blame] | 1900 | |
Hadar Hen Zion | 8e1a28e | 2013-12-19 21:20:12 +0200 | [diff] [blame] | 1901 | int mlx4_get_phys_port_id(struct mlx4_dev *dev) |
| 1902 | { |
| 1903 | u8 port; |
| 1904 | u32 *outbox; |
| 1905 | struct mlx4_cmd_mailbox *mailbox; |
| 1906 | u32 in_mod; |
| 1907 | u32 guid_hi, guid_lo; |
| 1908 | int err, ret = 0; |
| 1909 | #define MOD_STAT_CFG_PORT_OFFSET 8 |
| 1910 | #define MOD_STAT_CFG_GUID_H 0X14 |
| 1911 | #define MOD_STAT_CFG_GUID_L 0X1c |
| 1912 | |
| 1913 | mailbox = mlx4_alloc_cmd_mailbox(dev); |
| 1914 | if (IS_ERR(mailbox)) |
| 1915 | return PTR_ERR(mailbox); |
| 1916 | outbox = mailbox->buf; |
| 1917 | |
| 1918 | for (port = 1; port <= dev->caps.num_ports; port++) { |
| 1919 | in_mod = port << MOD_STAT_CFG_PORT_OFFSET; |
| 1920 | err = mlx4_cmd_box(dev, 0, mailbox->dma, in_mod, 0x2, |
| 1921 | MLX4_CMD_MOD_STAT_CFG, MLX4_CMD_TIME_CLASS_A, |
| 1922 | MLX4_CMD_NATIVE); |
| 1923 | if (err) { |
| 1924 | mlx4_err(dev, "Fail to get port %d uplink guid\n", |
| 1925 | port); |
| 1926 | ret = err; |
| 1927 | } else { |
| 1928 | MLX4_GET(guid_hi, outbox, MOD_STAT_CFG_GUID_H); |
| 1929 | MLX4_GET(guid_lo, outbox, MOD_STAT_CFG_GUID_L); |
| 1930 | dev->caps.phys_port_id[port] = (u64)guid_lo | |
| 1931 | (u64)guid_hi << 32; |
| 1932 | } |
| 1933 | } |
| 1934 | mlx4_free_cmd_mailbox(dev, mailbox); |
| 1935 | return ret; |
| 1936 | } |
| 1937 | |
Yevgeny Petrilin | 14c07b1 | 2011-03-22 22:37:59 +0000 | [diff] [blame] | 1938 | #define MLX4_WOL_SETUP_MODE (5 << 28) |
| 1939 | int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port) |
| 1940 | { |
| 1941 | u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8; |
| 1942 | |
| 1943 | return mlx4_cmd_imm(dev, 0, config, in_mod, 0x3, |
Jack Morgenstein | f9baff5 | 2011-12-13 04:10:51 +0000 | [diff] [blame] | 1944 | MLX4_CMD_MOD_STAT_CFG, MLX4_CMD_TIME_CLASS_A, |
| 1945 | MLX4_CMD_NATIVE); |
Yevgeny Petrilin | 14c07b1 | 2011-03-22 22:37:59 +0000 | [diff] [blame] | 1946 | } |
| 1947 | EXPORT_SYMBOL_GPL(mlx4_wol_read); |
| 1948 | |
| 1949 | int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port) |
| 1950 | { |
| 1951 | u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8; |
| 1952 | |
| 1953 | return mlx4_cmd(dev, config, in_mod, 0x1, MLX4_CMD_MOD_STAT_CFG, |
Jack Morgenstein | f9baff5 | 2011-12-13 04:10:51 +0000 | [diff] [blame] | 1954 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); |
Yevgeny Petrilin | 14c07b1 | 2011-03-22 22:37:59 +0000 | [diff] [blame] | 1955 | } |
| 1956 | EXPORT_SYMBOL_GPL(mlx4_wol_write); |
Yevgeny Petrilin | fe6f700 | 2013-07-28 18:54:21 +0300 | [diff] [blame] | 1957 | |
| 1958 | enum { |
| 1959 | ADD_TO_MCG = 0x26, |
| 1960 | }; |
| 1961 | |
| 1962 | |
| 1963 | void mlx4_opreq_action(struct work_struct *work) |
| 1964 | { |
| 1965 | struct mlx4_priv *priv = container_of(work, struct mlx4_priv, |
| 1966 | opreq_task); |
| 1967 | struct mlx4_dev *dev = &priv->dev; |
| 1968 | int num_tasks = atomic_read(&priv->opreq_count); |
| 1969 | struct mlx4_cmd_mailbox *mailbox; |
| 1970 | struct mlx4_mgm *mgm; |
| 1971 | u32 *outbox; |
| 1972 | u32 modifier; |
| 1973 | u16 token; |
Yevgeny Petrilin | fe6f700 | 2013-07-28 18:54:21 +0300 | [diff] [blame] | 1974 | u16 type; |
| 1975 | int err; |
| 1976 | u32 num_qps; |
| 1977 | struct mlx4_qp qp; |
| 1978 | int i; |
| 1979 | u8 rem_mcg; |
| 1980 | u8 prot; |
| 1981 | |
| 1982 | #define GET_OP_REQ_MODIFIER_OFFSET 0x08 |
| 1983 | #define GET_OP_REQ_TOKEN_OFFSET 0x14 |
| 1984 | #define GET_OP_REQ_TYPE_OFFSET 0x1a |
| 1985 | #define GET_OP_REQ_DATA_OFFSET 0x20 |
| 1986 | |
| 1987 | mailbox = mlx4_alloc_cmd_mailbox(dev); |
| 1988 | if (IS_ERR(mailbox)) { |
| 1989 | mlx4_err(dev, "Failed to allocate mailbox for GET_OP_REQ\n"); |
| 1990 | return; |
| 1991 | } |
| 1992 | outbox = mailbox->buf; |
| 1993 | |
| 1994 | while (num_tasks) { |
| 1995 | err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, |
| 1996 | MLX4_CMD_GET_OP_REQ, MLX4_CMD_TIME_CLASS_A, |
| 1997 | MLX4_CMD_NATIVE); |
| 1998 | if (err) { |
Masanari Iida | 6d3be30 | 2013-09-30 23:19:09 +0900 | [diff] [blame] | 1999 | mlx4_err(dev, "Failed to retrieve required operation: %d\n", |
Yevgeny Petrilin | fe6f700 | 2013-07-28 18:54:21 +0300 | [diff] [blame] | 2000 | err); |
| 2001 | return; |
| 2002 | } |
| 2003 | MLX4_GET(modifier, outbox, GET_OP_REQ_MODIFIER_OFFSET); |
| 2004 | MLX4_GET(token, outbox, GET_OP_REQ_TOKEN_OFFSET); |
| 2005 | MLX4_GET(type, outbox, GET_OP_REQ_TYPE_OFFSET); |
Yevgeny Petrilin | fe6f700 | 2013-07-28 18:54:21 +0300 | [diff] [blame] | 2006 | type &= 0xfff; |
| 2007 | |
| 2008 | switch (type) { |
| 2009 | case ADD_TO_MCG: |
| 2010 | if (dev->caps.steering_mode == |
| 2011 | MLX4_STEERING_MODE_DEVICE_MANAGED) { |
| 2012 | mlx4_warn(dev, "ADD MCG operation is not supported in DEVICE_MANAGED steering mode\n"); |
| 2013 | err = EPERM; |
| 2014 | break; |
| 2015 | } |
| 2016 | mgm = (struct mlx4_mgm *)((u8 *)(outbox) + |
| 2017 | GET_OP_REQ_DATA_OFFSET); |
| 2018 | num_qps = be32_to_cpu(mgm->members_count) & |
| 2019 | MGM_QPN_MASK; |
| 2020 | rem_mcg = ((u8 *)(&mgm->members_count))[0] & 1; |
| 2021 | prot = ((u8 *)(&mgm->members_count))[0] >> 6; |
| 2022 | |
| 2023 | for (i = 0; i < num_qps; i++) { |
| 2024 | qp.qpn = be32_to_cpu(mgm->qp[i]); |
| 2025 | if (rem_mcg) |
| 2026 | err = mlx4_multicast_detach(dev, &qp, |
| 2027 | mgm->gid, |
| 2028 | prot, 0); |
| 2029 | else |
| 2030 | err = mlx4_multicast_attach(dev, &qp, |
| 2031 | mgm->gid, |
| 2032 | mgm->gid[5] |
| 2033 | , 0, prot, |
| 2034 | NULL); |
| 2035 | if (err) |
| 2036 | break; |
| 2037 | } |
| 2038 | break; |
| 2039 | default: |
| 2040 | mlx4_warn(dev, "Bad type for required operation\n"); |
| 2041 | err = EINVAL; |
| 2042 | break; |
| 2043 | } |
Eyal Perry | 28d222b | 2014-03-02 10:25:03 +0200 | [diff] [blame] | 2044 | err = mlx4_cmd(dev, 0, ((u32) err | |
| 2045 | (__force u32)cpu_to_be32(token) << 16), |
Yevgeny Petrilin | fe6f700 | 2013-07-28 18:54:21 +0300 | [diff] [blame] | 2046 | 1, MLX4_CMD_GET_OP_REQ, MLX4_CMD_TIME_CLASS_A, |
| 2047 | MLX4_CMD_NATIVE); |
| 2048 | if (err) { |
| 2049 | mlx4_err(dev, "Failed to acknowledge required request: %d\n", |
| 2050 | err); |
| 2051 | goto out; |
| 2052 | } |
| 2053 | memset(outbox, 0, 0xffc); |
| 2054 | num_tasks = atomic_dec_return(&priv->opreq_count); |
| 2055 | } |
| 2056 | |
| 2057 | out: |
| 2058 | mlx4_free_cmd_mailbox(dev, mailbox); |
| 2059 | } |
Jack Morgenstein | 114840c | 2014-06-01 11:53:50 +0300 | [diff] [blame] | 2060 | |
| 2061 | static int mlx4_check_smp_firewall_active(struct mlx4_dev *dev, |
| 2062 | struct mlx4_cmd_mailbox *mailbox) |
| 2063 | { |
| 2064 | #define MLX4_CMD_MAD_DEMUX_SET_ATTR_OFFSET 0x10 |
| 2065 | #define MLX4_CMD_MAD_DEMUX_GETRESP_ATTR_OFFSET 0x20 |
| 2066 | #define MLX4_CMD_MAD_DEMUX_TRAP_ATTR_OFFSET 0x40 |
| 2067 | #define MLX4_CMD_MAD_DEMUX_TRAP_REPRESS_ATTR_OFFSET 0x70 |
| 2068 | |
| 2069 | u32 set_attr_mask, getresp_attr_mask; |
| 2070 | u32 trap_attr_mask, traprepress_attr_mask; |
| 2071 | |
| 2072 | MLX4_GET(set_attr_mask, mailbox->buf, |
| 2073 | MLX4_CMD_MAD_DEMUX_SET_ATTR_OFFSET); |
| 2074 | mlx4_dbg(dev, "SMP firewall set_attribute_mask = 0x%x\n", |
| 2075 | set_attr_mask); |
| 2076 | |
| 2077 | MLX4_GET(getresp_attr_mask, mailbox->buf, |
| 2078 | MLX4_CMD_MAD_DEMUX_GETRESP_ATTR_OFFSET); |
| 2079 | mlx4_dbg(dev, "SMP firewall getresp_attribute_mask = 0x%x\n", |
| 2080 | getresp_attr_mask); |
| 2081 | |
| 2082 | MLX4_GET(trap_attr_mask, mailbox->buf, |
| 2083 | MLX4_CMD_MAD_DEMUX_TRAP_ATTR_OFFSET); |
| 2084 | mlx4_dbg(dev, "SMP firewall trap_attribute_mask = 0x%x\n", |
| 2085 | trap_attr_mask); |
| 2086 | |
| 2087 | MLX4_GET(traprepress_attr_mask, mailbox->buf, |
| 2088 | MLX4_CMD_MAD_DEMUX_TRAP_REPRESS_ATTR_OFFSET); |
| 2089 | mlx4_dbg(dev, "SMP firewall traprepress_attribute_mask = 0x%x\n", |
| 2090 | traprepress_attr_mask); |
| 2091 | |
| 2092 | if (set_attr_mask && getresp_attr_mask && trap_attr_mask && |
| 2093 | traprepress_attr_mask) |
| 2094 | return 1; |
| 2095 | |
| 2096 | return 0; |
| 2097 | } |
| 2098 | |
| 2099 | int mlx4_config_mad_demux(struct mlx4_dev *dev) |
| 2100 | { |
| 2101 | struct mlx4_cmd_mailbox *mailbox; |
| 2102 | int secure_host_active; |
| 2103 | int err; |
| 2104 | |
| 2105 | /* Check if mad_demux is supported */ |
| 2106 | if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_MAD_DEMUX)) |
| 2107 | return 0; |
| 2108 | |
| 2109 | mailbox = mlx4_alloc_cmd_mailbox(dev); |
| 2110 | if (IS_ERR(mailbox)) { |
| 2111 | mlx4_warn(dev, "Failed to allocate mailbox for cmd MAD_DEMUX"); |
| 2112 | return -ENOMEM; |
| 2113 | } |
| 2114 | |
| 2115 | /* Query mad_demux to find out which MADs are handled by internal sma */ |
| 2116 | err = mlx4_cmd_box(dev, 0, mailbox->dma, 0x01 /* subn mgmt class */, |
| 2117 | MLX4_CMD_MAD_DEMUX_QUERY_RESTR, MLX4_CMD_MAD_DEMUX, |
| 2118 | MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); |
| 2119 | if (err) { |
| 2120 | mlx4_warn(dev, "MLX4_CMD_MAD_DEMUX: query restrictions failed (%d)\n", |
| 2121 | err); |
| 2122 | goto out; |
| 2123 | } |
| 2124 | |
| 2125 | secure_host_active = mlx4_check_smp_firewall_active(dev, mailbox); |
| 2126 | |
| 2127 | /* Config mad_demux to handle all MADs returned by the query above */ |
| 2128 | err = mlx4_cmd(dev, mailbox->dma, 0x01 /* subn mgmt class */, |
| 2129 | MLX4_CMD_MAD_DEMUX_CONFIG, MLX4_CMD_MAD_DEMUX, |
| 2130 | MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); |
| 2131 | if (err) { |
| 2132 | mlx4_warn(dev, "MLX4_CMD_MAD_DEMUX: configure failed (%d)\n", err); |
| 2133 | goto out; |
| 2134 | } |
| 2135 | |
| 2136 | if (secure_host_active) |
| 2137 | mlx4_warn(dev, "HCA operating in secure-host mode. SMP firewall activated.\n"); |
| 2138 | out: |
| 2139 | mlx4_free_cmd_mailbox(dev, mailbox); |
| 2140 | return err; |
| 2141 | } |