blob: 49bf3e2eb652316757e2781ef7e703171c868414 [file] [log] [blame]
David S. Millerecba38a2006-06-23 21:23:01 -07001/* sunqe.c: Sparc QuadEthernet 10baseT SBUS card driver.
Linus Torvalds1da177e2005-04-16 15:20:36 -07002 * Once again I am out to prove that every ethernet
3 * controller out there can be most efficiently programmed
4 * if you make it look like a LANCE.
5 *
David S. Miller8e912b32008-08-27 00:12:27 -07006 * Copyright (C) 1996, 1999, 2003, 2006, 2008 David S. Miller (davem@davemloft.net)
Linus Torvalds1da177e2005-04-16 15:20:36 -07007 */
8
Linus Torvalds1da177e2005-04-16 15:20:36 -07009#include <linux/module.h>
10#include <linux/kernel.h>
11#include <linux/types.h>
12#include <linux/errno.h>
13#include <linux/fcntl.h>
14#include <linux/interrupt.h>
15#include <linux/ioport.h>
16#include <linux/in.h>
17#include <linux/slab.h>
18#include <linux/string.h>
19#include <linux/delay.h>
20#include <linux/init.h>
21#include <linux/crc32.h>
22#include <linux/netdevice.h>
23#include <linux/etherdevice.h>
24#include <linux/skbuff.h>
25#include <linux/ethtool.h>
26#include <linux/bitops.h>
David S. Miller738f2b72008-08-27 18:09:11 -070027#include <linux/dma-mapping.h>
David S. Miller8e912b32008-08-27 00:12:27 -070028#include <linux/of.h>
29#include <linux/of_device.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070030
Linus Torvalds1da177e2005-04-16 15:20:36 -070031#include <asm/io.h>
32#include <asm/dma.h>
33#include <asm/byteorder.h>
34#include <asm/idprom.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070035#include <asm/openprom.h>
36#include <asm/oplib.h>
37#include <asm/auxio.h>
38#include <asm/pgtable.h>
39#include <asm/irq.h>
40
41#include "sunqe.h"
42
Tom 'spot' Callaway10158282005-04-24 20:35:20 -070043#define DRV_NAME "sunqe"
David S. Miller8e912b32008-08-27 00:12:27 -070044#define DRV_VERSION "4.1"
45#define DRV_RELDATE "August 27, 2008"
David S. Millerecba38a2006-06-23 21:23:01 -070046#define DRV_AUTHOR "David S. Miller (davem@davemloft.net)"
Tom 'spot' Callaway10158282005-04-24 20:35:20 -070047
48static char version[] =
49 DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE " " DRV_AUTHOR "\n";
50
51MODULE_VERSION(DRV_VERSION);
52MODULE_AUTHOR(DRV_AUTHOR);
53MODULE_DESCRIPTION("Sun QuadEthernet 10baseT SBUS card driver");
54MODULE_LICENSE("GPL");
55
Linus Torvalds1da177e2005-04-16 15:20:36 -070056static struct sunqec *root_qec_dev;
57
58static void qe_set_multicast(struct net_device *dev);
59
60#define QEC_RESET_TRIES 200
61
62static inline int qec_global_reset(void __iomem *gregs)
63{
64 int tries = QEC_RESET_TRIES;
65
66 sbus_writel(GLOB_CTRL_RESET, gregs + GLOB_CTRL);
67 while (--tries) {
68 u32 tmp = sbus_readl(gregs + GLOB_CTRL);
69 if (tmp & GLOB_CTRL_RESET) {
70 udelay(20);
71 continue;
72 }
73 break;
74 }
75 if (tries)
76 return 0;
77 printk(KERN_ERR "QuadEther: AIEEE cannot reset the QEC!\n");
78 return -1;
79}
80
81#define MACE_RESET_RETRIES 200
82#define QE_RESET_RETRIES 200
83
84static inline int qe_stop(struct sunqe *qep)
85{
86 void __iomem *cregs = qep->qcregs;
87 void __iomem *mregs = qep->mregs;
88 int tries;
89
90 /* Reset the MACE, then the QEC channel. */
91 sbus_writeb(MREGS_BCONFIG_RESET, mregs + MREGS_BCONFIG);
92 tries = MACE_RESET_RETRIES;
93 while (--tries) {
94 u8 tmp = sbus_readb(mregs + MREGS_BCONFIG);
95 if (tmp & MREGS_BCONFIG_RESET) {
96 udelay(20);
97 continue;
98 }
99 break;
100 }
101 if (!tries) {
102 printk(KERN_ERR "QuadEther: AIEEE cannot reset the MACE!\n");
103 return -1;
104 }
105
106 sbus_writel(CREG_CTRL_RESET, cregs + CREG_CTRL);
107 tries = QE_RESET_RETRIES;
108 while (--tries) {
109 u32 tmp = sbus_readl(cregs + CREG_CTRL);
110 if (tmp & CREG_CTRL_RESET) {
111 udelay(20);
112 continue;
113 }
114 break;
115 }
116 if (!tries) {
117 printk(KERN_ERR "QuadEther: Cannot reset QE channel!\n");
118 return -1;
119 }
120 return 0;
121}
122
123static void qe_init_rings(struct sunqe *qep)
124{
125 struct qe_init_block *qb = qep->qe_block;
126 struct sunqe_buffers *qbufs = qep->buffers;
127 __u32 qbufs_dvma = qep->buffers_dvma;
128 int i;
129
130 qep->rx_new = qep->rx_old = qep->tx_new = qep->tx_old = 0;
131 memset(qb, 0, sizeof(struct qe_init_block));
132 memset(qbufs, 0, sizeof(struct sunqe_buffers));
133 for (i = 0; i < RX_RING_SIZE; i++) {
134 qb->qe_rxd[i].rx_addr = qbufs_dvma + qebuf_offset(rx_buf, i);
135 qb->qe_rxd[i].rx_flags =
136 (RXD_OWN | ((RXD_PKT_SZ) & RXD_LENGTH));
137 }
138}
139
140static int qe_init(struct sunqe *qep, int from_irq)
141{
142 struct sunqec *qecp = qep->parent;
143 void __iomem *cregs = qep->qcregs;
144 void __iomem *mregs = qep->mregs;
145 void __iomem *gregs = qecp->gregs;
146 unsigned char *e = &qep->dev->dev_addr[0];
147 u32 tmp;
148 int i;
149
150 /* Shut it up. */
151 if (qe_stop(qep))
152 return -EAGAIN;
153
154 /* Setup initial rx/tx init block pointers. */
155 sbus_writel(qep->qblock_dvma + qib_offset(qe_rxd, 0), cregs + CREG_RXDS);
156 sbus_writel(qep->qblock_dvma + qib_offset(qe_txd, 0), cregs + CREG_TXDS);
157
158 /* Enable/mask the various irq's. */
159 sbus_writel(0, cregs + CREG_RIMASK);
160 sbus_writel(1, cregs + CREG_TIMASK);
161
162 sbus_writel(0, cregs + CREG_QMASK);
163 sbus_writel(CREG_MMASK_RXCOLL, cregs + CREG_MMASK);
164
165 /* Setup the FIFO pointers into QEC local memory. */
166 tmp = qep->channel * sbus_readl(gregs + GLOB_MSIZE);
167 sbus_writel(tmp, cregs + CREG_RXRBUFPTR);
168 sbus_writel(tmp, cregs + CREG_RXWBUFPTR);
169
170 tmp = sbus_readl(cregs + CREG_RXRBUFPTR) +
171 sbus_readl(gregs + GLOB_RSIZE);
172 sbus_writel(tmp, cregs + CREG_TXRBUFPTR);
173 sbus_writel(tmp, cregs + CREG_TXWBUFPTR);
174
175 /* Clear the channel collision counter. */
176 sbus_writel(0, cregs + CREG_CCNT);
177
178 /* For 10baseT, inter frame space nor throttle seems to be necessary. */
179 sbus_writel(0, cregs + CREG_PIPG);
180
181 /* Now dork with the AMD MACE. */
182 sbus_writeb(MREGS_PHYCONFIG_AUTO, mregs + MREGS_PHYCONFIG);
183 sbus_writeb(MREGS_TXFCNTL_AUTOPAD, mregs + MREGS_TXFCNTL);
184 sbus_writeb(0, mregs + MREGS_RXFCNTL);
185
186 /* The QEC dma's the rx'd packets from local memory out to main memory,
187 * and therefore it interrupts when the packet reception is "complete".
188 * So don't listen for the MACE talking about it.
189 */
190 sbus_writeb(MREGS_IMASK_COLL | MREGS_IMASK_RXIRQ, mregs + MREGS_IMASK);
191 sbus_writeb(MREGS_BCONFIG_BSWAP | MREGS_BCONFIG_64TS, mregs + MREGS_BCONFIG);
192 sbus_writeb((MREGS_FCONFIG_TXF16 | MREGS_FCONFIG_RXF32 |
193 MREGS_FCONFIG_RFWU | MREGS_FCONFIG_TFWU),
194 mregs + MREGS_FCONFIG);
195
196 /* Only usable interface on QuadEther is twisted pair. */
197 sbus_writeb(MREGS_PLSCONFIG_TP, mregs + MREGS_PLSCONFIG);
198
199 /* Tell MACE we are changing the ether address. */
200 sbus_writeb(MREGS_IACONFIG_ACHNGE | MREGS_IACONFIG_PARESET,
201 mregs + MREGS_IACONFIG);
202 while ((sbus_readb(mregs + MREGS_IACONFIG) & MREGS_IACONFIG_ACHNGE) != 0)
203 barrier();
204 sbus_writeb(e[0], mregs + MREGS_ETHADDR);
205 sbus_writeb(e[1], mregs + MREGS_ETHADDR);
206 sbus_writeb(e[2], mregs + MREGS_ETHADDR);
207 sbus_writeb(e[3], mregs + MREGS_ETHADDR);
208 sbus_writeb(e[4], mregs + MREGS_ETHADDR);
209 sbus_writeb(e[5], mregs + MREGS_ETHADDR);
210
211 /* Clear out the address filter. */
212 sbus_writeb(MREGS_IACONFIG_ACHNGE | MREGS_IACONFIG_LARESET,
213 mregs + MREGS_IACONFIG);
214 while ((sbus_readb(mregs + MREGS_IACONFIG) & MREGS_IACONFIG_ACHNGE) != 0)
215 barrier();
216 for (i = 0; i < 8; i++)
217 sbus_writeb(0, mregs + MREGS_FILTER);
218
219 /* Address changes are now complete. */
220 sbus_writeb(0, mregs + MREGS_IACONFIG);
221
222 qe_init_rings(qep);
223
224 /* Wait a little bit for the link to come up... */
225 mdelay(5);
226 if (!(sbus_readb(mregs + MREGS_PHYCONFIG) & MREGS_PHYCONFIG_LTESTDIS)) {
227 int tries = 50;
228
Roel Kluin46578a692009-02-02 21:39:02 -0800229 while (--tries) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700230 u8 tmp;
231
232 mdelay(5);
233 barrier();
234 tmp = sbus_readb(mregs + MREGS_PHYCONFIG);
235 if ((tmp & MREGS_PHYCONFIG_LSTAT) != 0)
236 break;
237 }
238 if (tries == 0)
239 printk(KERN_NOTICE "%s: Warning, link state is down.\n", qep->dev->name);
240 }
241
242 /* Missed packet counter is cleared on a read. */
243 sbus_readb(mregs + MREGS_MPCNT);
244
245 /* Reload multicast information, this will enable the receiver
246 * and transmitter.
247 */
248 qe_set_multicast(qep->dev);
249
250 /* QEC should now start to show interrupts. */
251 return 0;
252}
253
254/* Grrr, certain error conditions completely lock up the AMD MACE,
255 * so when we get these we _must_ reset the chip.
256 */
257static int qe_is_bolixed(struct sunqe *qep, u32 qe_status)
258{
259 struct net_device *dev = qep->dev;
260 int mace_hwbug_workaround = 0;
261
262 if (qe_status & CREG_STAT_EDEFER) {
263 printk(KERN_ERR "%s: Excessive transmit defers.\n", dev->name);
Jeff Garzik09f75cd2007-10-03 17:41:50 -0700264 dev->stats.tx_errors++;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700265 }
266
267 if (qe_status & CREG_STAT_CLOSS) {
268 printk(KERN_ERR "%s: Carrier lost, link down?\n", dev->name);
Jeff Garzik09f75cd2007-10-03 17:41:50 -0700269 dev->stats.tx_errors++;
270 dev->stats.tx_carrier_errors++;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700271 }
272
273 if (qe_status & CREG_STAT_ERETRIES) {
274 printk(KERN_ERR "%s: Excessive transmit retries (more than 16).\n", dev->name);
Jeff Garzik09f75cd2007-10-03 17:41:50 -0700275 dev->stats.tx_errors++;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700276 mace_hwbug_workaround = 1;
277 }
278
279 if (qe_status & CREG_STAT_LCOLL) {
280 printk(KERN_ERR "%s: Late transmit collision.\n", dev->name);
Jeff Garzik09f75cd2007-10-03 17:41:50 -0700281 dev->stats.tx_errors++;
282 dev->stats.collisions++;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700283 mace_hwbug_workaround = 1;
284 }
285
286 if (qe_status & CREG_STAT_FUFLOW) {
287 printk(KERN_ERR "%s: Transmit fifo underflow, driver bug.\n", dev->name);
Jeff Garzik09f75cd2007-10-03 17:41:50 -0700288 dev->stats.tx_errors++;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700289 mace_hwbug_workaround = 1;
290 }
291
292 if (qe_status & CREG_STAT_JERROR) {
293 printk(KERN_ERR "%s: Jabber error.\n", dev->name);
294 }
295
296 if (qe_status & CREG_STAT_BERROR) {
297 printk(KERN_ERR "%s: Babble error.\n", dev->name);
298 }
299
300 if (qe_status & CREG_STAT_CCOFLOW) {
Jeff Garzik09f75cd2007-10-03 17:41:50 -0700301 dev->stats.tx_errors += 256;
302 dev->stats.collisions += 256;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700303 }
304
305 if (qe_status & CREG_STAT_TXDERROR) {
306 printk(KERN_ERR "%s: Transmit descriptor is bogus, driver bug.\n", dev->name);
Jeff Garzik09f75cd2007-10-03 17:41:50 -0700307 dev->stats.tx_errors++;
308 dev->stats.tx_aborted_errors++;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700309 mace_hwbug_workaround = 1;
310 }
311
312 if (qe_status & CREG_STAT_TXLERR) {
313 printk(KERN_ERR "%s: Transmit late error.\n", dev->name);
Jeff Garzik09f75cd2007-10-03 17:41:50 -0700314 dev->stats.tx_errors++;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700315 mace_hwbug_workaround = 1;
316 }
317
318 if (qe_status & CREG_STAT_TXPERR) {
319 printk(KERN_ERR "%s: Transmit DMA parity error.\n", dev->name);
Jeff Garzik09f75cd2007-10-03 17:41:50 -0700320 dev->stats.tx_errors++;
321 dev->stats.tx_aborted_errors++;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700322 mace_hwbug_workaround = 1;
323 }
324
325 if (qe_status & CREG_STAT_TXSERR) {
326 printk(KERN_ERR "%s: Transmit DMA sbus error ack.\n", dev->name);
Jeff Garzik09f75cd2007-10-03 17:41:50 -0700327 dev->stats.tx_errors++;
328 dev->stats.tx_aborted_errors++;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700329 mace_hwbug_workaround = 1;
330 }
331
332 if (qe_status & CREG_STAT_RCCOFLOW) {
Jeff Garzik09f75cd2007-10-03 17:41:50 -0700333 dev->stats.rx_errors += 256;
334 dev->stats.collisions += 256;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700335 }
336
337 if (qe_status & CREG_STAT_RUOFLOW) {
Jeff Garzik09f75cd2007-10-03 17:41:50 -0700338 dev->stats.rx_errors += 256;
339 dev->stats.rx_over_errors += 256;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700340 }
341
342 if (qe_status & CREG_STAT_MCOFLOW) {
Jeff Garzik09f75cd2007-10-03 17:41:50 -0700343 dev->stats.rx_errors += 256;
344 dev->stats.rx_missed_errors += 256;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700345 }
346
347 if (qe_status & CREG_STAT_RXFOFLOW) {
348 printk(KERN_ERR "%s: Receive fifo overflow.\n", dev->name);
Jeff Garzik09f75cd2007-10-03 17:41:50 -0700349 dev->stats.rx_errors++;
350 dev->stats.rx_over_errors++;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700351 }
352
353 if (qe_status & CREG_STAT_RLCOLL) {
354 printk(KERN_ERR "%s: Late receive collision.\n", dev->name);
Jeff Garzik09f75cd2007-10-03 17:41:50 -0700355 dev->stats.rx_errors++;
356 dev->stats.collisions++;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700357 }
358
359 if (qe_status & CREG_STAT_FCOFLOW) {
Jeff Garzik09f75cd2007-10-03 17:41:50 -0700360 dev->stats.rx_errors += 256;
361 dev->stats.rx_frame_errors += 256;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700362 }
363
364 if (qe_status & CREG_STAT_CECOFLOW) {
Jeff Garzik09f75cd2007-10-03 17:41:50 -0700365 dev->stats.rx_errors += 256;
366 dev->stats.rx_crc_errors += 256;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700367 }
368
369 if (qe_status & CREG_STAT_RXDROP) {
370 printk(KERN_ERR "%s: Receive packet dropped.\n", dev->name);
Jeff Garzik09f75cd2007-10-03 17:41:50 -0700371 dev->stats.rx_errors++;
372 dev->stats.rx_dropped++;
373 dev->stats.rx_missed_errors++;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700374 }
375
376 if (qe_status & CREG_STAT_RXSMALL) {
377 printk(KERN_ERR "%s: Receive buffer too small, driver bug.\n", dev->name);
Jeff Garzik09f75cd2007-10-03 17:41:50 -0700378 dev->stats.rx_errors++;
379 dev->stats.rx_length_errors++;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700380 }
381
382 if (qe_status & CREG_STAT_RXLERR) {
383 printk(KERN_ERR "%s: Receive late error.\n", dev->name);
Jeff Garzik09f75cd2007-10-03 17:41:50 -0700384 dev->stats.rx_errors++;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700385 mace_hwbug_workaround = 1;
386 }
387
388 if (qe_status & CREG_STAT_RXPERR) {
389 printk(KERN_ERR "%s: Receive DMA parity error.\n", dev->name);
Jeff Garzik09f75cd2007-10-03 17:41:50 -0700390 dev->stats.rx_errors++;
391 dev->stats.rx_missed_errors++;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700392 mace_hwbug_workaround = 1;
393 }
394
395 if (qe_status & CREG_STAT_RXSERR) {
396 printk(KERN_ERR "%s: Receive DMA sbus error ack.\n", dev->name);
Jeff Garzik09f75cd2007-10-03 17:41:50 -0700397 dev->stats.rx_errors++;
398 dev->stats.rx_missed_errors++;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700399 mace_hwbug_workaround = 1;
400 }
401
402 if (mace_hwbug_workaround)
403 qe_init(qep, 1);
404 return mace_hwbug_workaround;
405}
406
407/* Per-QE receive interrupt service routine. Just like on the happy meal
408 * we receive directly into skb's with a small packet copy water mark.
409 */
410static void qe_rx(struct sunqe *qep)
411{
412 struct qe_rxd *rxbase = &qep->qe_block->qe_rxd[0];
Jeff Garzik09f75cd2007-10-03 17:41:50 -0700413 struct net_device *dev = qep->dev;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700414 struct qe_rxd *this;
415 struct sunqe_buffers *qbufs = qep->buffers;
416 __u32 qbufs_dvma = qep->buffers_dvma;
417 int elem = qep->rx_new, drops = 0;
418 u32 flags;
419
420 this = &rxbase[elem];
421 while (!((flags = this->rx_flags) & RXD_OWN)) {
422 struct sk_buff *skb;
423 unsigned char *this_qbuf =
424 &qbufs->rx_buf[elem & (RX_RING_SIZE - 1)][0];
425 __u32 this_qbuf_dvma = qbufs_dvma +
426 qebuf_offset(rx_buf, (elem & (RX_RING_SIZE - 1)));
427 struct qe_rxd *end_rxd =
428 &rxbase[(elem+RX_RING_SIZE)&(RX_RING_MAXSIZE-1)];
429 int len = (flags & RXD_LENGTH) - 4; /* QE adds ether FCS size to len */
430
431 /* Check for errors. */
432 if (len < ETH_ZLEN) {
Jeff Garzik09f75cd2007-10-03 17:41:50 -0700433 dev->stats.rx_errors++;
434 dev->stats.rx_length_errors++;
435 dev->stats.rx_dropped++;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700436 } else {
Pradeep A. Dalvidae2e9f2012-02-06 11:16:13 +0000437 skb = netdev_alloc_skb(dev, len + 2);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700438 if (skb == NULL) {
439 drops++;
Jeff Garzik09f75cd2007-10-03 17:41:50 -0700440 dev->stats.rx_dropped++;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700441 } else {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700442 skb_reserve(skb, 2);
443 skb_put(skb, len);
Joe Perches64699332012-06-04 12:44:16 +0000444 skb_copy_to_linear_data(skb, this_qbuf,
David S. Miller8c7b7fa2007-07-10 22:08:12 -0700445 len);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700446 skb->protocol = eth_type_trans(skb, qep->dev);
447 netif_rx(skb);
Jeff Garzik09f75cd2007-10-03 17:41:50 -0700448 dev->stats.rx_packets++;
449 dev->stats.rx_bytes += len;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700450 }
451 }
452 end_rxd->rx_addr = this_qbuf_dvma;
453 end_rxd->rx_flags = (RXD_OWN | ((RXD_PKT_SZ) & RXD_LENGTH));
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400454
Linus Torvalds1da177e2005-04-16 15:20:36 -0700455 elem = NEXT_RX(elem);
456 this = &rxbase[elem];
457 }
458 qep->rx_new = elem;
459 if (drops)
460 printk(KERN_NOTICE "%s: Memory squeeze, deferring packet.\n", qep->dev->name);
461}
462
463static void qe_tx_reclaim(struct sunqe *qep);
464
465/* Interrupts for all QE's get filtered out via the QEC master controller,
466 * so we just run through each qe and check to see who is signaling
467 * and thus needs to be serviced.
468 */
David Howells7d12e782006-10-05 14:55:46 +0100469static irqreturn_t qec_interrupt(int irq, void *dev_id)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700470{
Jeff Garzikc31f28e2006-10-06 14:56:04 -0400471 struct sunqec *qecp = dev_id;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700472 u32 qec_status;
473 int channel = 0;
474
475 /* Latch the status now. */
476 qec_status = sbus_readl(qecp->gregs + GLOB_STAT);
477 while (channel < 4) {
478 if (qec_status & 0xf) {
479 struct sunqe *qep = qecp->qes[channel];
480 u32 qe_status;
481
482 qe_status = sbus_readl(qep->qcregs + CREG_STAT);
483 if (qe_status & CREG_STAT_ERRORS) {
484 if (qe_is_bolixed(qep, qe_status))
485 goto next;
486 }
487 if (qe_status & CREG_STAT_RXIRQ)
488 qe_rx(qep);
489 if (netif_queue_stopped(qep->dev) &&
490 (qe_status & CREG_STAT_TXIRQ)) {
491 spin_lock(&qep->lock);
492 qe_tx_reclaim(qep);
493 if (TX_BUFFS_AVAIL(qep) > 0) {
494 /* Wake net queue and return to
495 * lazy tx reclaim.
496 */
497 netif_wake_queue(qep->dev);
498 sbus_writel(1, qep->qcregs + CREG_TIMASK);
499 }
500 spin_unlock(&qep->lock);
501 }
502 next:
503 ;
504 }
505 qec_status >>= 4;
506 channel++;
507 }
508
509 return IRQ_HANDLED;
510}
511
512static int qe_open(struct net_device *dev)
513{
Wang Chen8f15ea42008-11-12 23:38:36 -0800514 struct sunqe *qep = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700515
516 qep->mconfig = (MREGS_MCONFIG_TXENAB |
517 MREGS_MCONFIG_RXENAB |
518 MREGS_MCONFIG_MBAENAB);
519 return qe_init(qep, 0);
520}
521
522static int qe_close(struct net_device *dev)
523{
Wang Chen8f15ea42008-11-12 23:38:36 -0800524 struct sunqe *qep = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700525
526 qe_stop(qep);
527 return 0;
528}
529
530/* Reclaim TX'd frames from the ring. This must always run under
531 * the IRQ protected qep->lock.
532 */
533static void qe_tx_reclaim(struct sunqe *qep)
534{
535 struct qe_txd *txbase = &qep->qe_block->qe_txd[0];
536 int elem = qep->tx_old;
537
538 while (elem != qep->tx_new) {
539 u32 flags = txbase[elem].tx_flags;
540
541 if (flags & TXD_OWN)
542 break;
543 elem = NEXT_TX(elem);
544 }
545 qep->tx_old = elem;
546}
547
548static void qe_tx_timeout(struct net_device *dev)
549{
Wang Chen8f15ea42008-11-12 23:38:36 -0800550 struct sunqe *qep = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700551 int tx_full;
552
553 spin_lock_irq(&qep->lock);
554
555 /* Try to reclaim, if that frees up some tx
556 * entries, we're fine.
557 */
558 qe_tx_reclaim(qep);
559 tx_full = TX_BUFFS_AVAIL(qep) <= 0;
560
561 spin_unlock_irq(&qep->lock);
562
563 if (! tx_full)
564 goto out;
565
566 printk(KERN_ERR "%s: transmit timed out, resetting\n", dev->name);
567 qe_init(qep, 1);
568
569out:
570 netif_wake_queue(dev);
571}
572
573/* Get a packet queued to go onto the wire. */
574static int qe_start_xmit(struct sk_buff *skb, struct net_device *dev)
575{
Wang Chen8f15ea42008-11-12 23:38:36 -0800576 struct sunqe *qep = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700577 struct sunqe_buffers *qbufs = qep->buffers;
578 __u32 txbuf_dvma, qbufs_dvma = qep->buffers_dvma;
579 unsigned char *txbuf;
580 int len, entry;
581
582 spin_lock_irq(&qep->lock);
583
584 qe_tx_reclaim(qep);
585
586 len = skb->len;
587 entry = qep->tx_new;
588
589 txbuf = &qbufs->tx_buf[entry & (TX_RING_SIZE - 1)][0];
590 txbuf_dvma = qbufs_dvma +
591 qebuf_offset(tx_buf, (entry & (TX_RING_SIZE - 1)));
592
593 /* Avoid a race... */
594 qep->qe_block->qe_txd[entry].tx_flags = TXD_UPDATE;
595
Arnaldo Carvalho de Melod626f622007-03-27 18:55:52 -0300596 skb_copy_from_linear_data(skb, txbuf, len);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700597
598 qep->qe_block->qe_txd[entry].tx_addr = txbuf_dvma;
599 qep->qe_block->qe_txd[entry].tx_flags =
600 (TXD_OWN | TXD_SOP | TXD_EOP | (len & TXD_LENGTH));
601 qep->tx_new = NEXT_TX(entry);
602
603 /* Get it going. */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700604 sbus_writel(CREG_CTRL_TWAKEUP, qep->qcregs + CREG_CTRL);
605
Jeff Garzik09f75cd2007-10-03 17:41:50 -0700606 dev->stats.tx_packets++;
607 dev->stats.tx_bytes += len;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700608
609 if (TX_BUFFS_AVAIL(qep) <= 0) {
610 /* Halt the net queue and enable tx interrupts.
611 * When the tx queue empties the tx irq handler
612 * will wake up the queue and return us back to
613 * the lazy tx reclaim scheme.
614 */
615 netif_stop_queue(dev);
616 sbus_writel(0, qep->qcregs + CREG_TIMASK);
617 }
618 spin_unlock_irq(&qep->lock);
619
620 dev_kfree_skb(skb);
621
Patrick McHardy6ed10652009-06-23 06:03:08 +0000622 return NETDEV_TX_OK;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700623}
624
Linus Torvalds1da177e2005-04-16 15:20:36 -0700625static void qe_set_multicast(struct net_device *dev)
626{
Wang Chen8f15ea42008-11-12 23:38:36 -0800627 struct sunqe *qep = netdev_priv(dev);
Jiri Pirko22bedad32010-04-01 21:22:57 +0000628 struct netdev_hw_addr *ha;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700629 u8 new_mconfig = qep->mconfig;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700630 int i;
631 u32 crc;
632
633 /* Lock out others. */
634 netif_stop_queue(dev);
635
Jiri Pirko4cd24ea2010-02-08 04:30:35 +0000636 if ((dev->flags & IFF_ALLMULTI) || (netdev_mc_count(dev) > 64)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700637 sbus_writeb(MREGS_IACONFIG_ACHNGE | MREGS_IACONFIG_LARESET,
638 qep->mregs + MREGS_IACONFIG);
639 while ((sbus_readb(qep->mregs + MREGS_IACONFIG) & MREGS_IACONFIG_ACHNGE) != 0)
640 barrier();
641 for (i = 0; i < 8; i++)
642 sbus_writeb(0xff, qep->mregs + MREGS_FILTER);
643 sbus_writeb(0, qep->mregs + MREGS_IACONFIG);
644 } else if (dev->flags & IFF_PROMISC) {
645 new_mconfig |= MREGS_MCONFIG_PROMISC;
646 } else {
647 u16 hash_table[4];
648 u8 *hbytes = (unsigned char *) &hash_table[0];
649
Jiri Pirko55085902010-02-18 00:42:54 +0000650 memset(hash_table, 0, sizeof(hash_table));
Jiri Pirko22bedad32010-04-01 21:22:57 +0000651 netdev_for_each_mc_addr(ha, dev) {
Tobias Klauser498d8e22011-07-07 22:06:26 +0000652 crc = ether_crc_le(6, ha->addr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700653 crc >>= 26;
654 hash_table[crc >> 4] |= 1 << (crc & 0xf);
655 }
656 /* Program the qe with the new filter value. */
657 sbus_writeb(MREGS_IACONFIG_ACHNGE | MREGS_IACONFIG_LARESET,
658 qep->mregs + MREGS_IACONFIG);
659 while ((sbus_readb(qep->mregs + MREGS_IACONFIG) & MREGS_IACONFIG_ACHNGE) != 0)
660 barrier();
661 for (i = 0; i < 8; i++) {
662 u8 tmp = *hbytes++;
663 sbus_writeb(tmp, qep->mregs + MREGS_FILTER);
664 }
665 sbus_writeb(0, qep->mregs + MREGS_IACONFIG);
666 }
667
668 /* Any change of the logical address filter, the physical address,
669 * or enabling/disabling promiscuous mode causes the MACE to disable
670 * the receiver. So we must re-enable them here or else the MACE
671 * refuses to listen to anything on the network. Sheesh, took
672 * me a day or two to find this bug.
673 */
674 qep->mconfig = new_mconfig;
675 sbus_writeb(qep->mconfig, qep->mregs + MREGS_MCONFIG);
676
677 /* Let us get going again. */
678 netif_wake_queue(dev);
679}
680
681/* Ethtool support... */
682static void qe_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
683{
David S. Miller8e912b32008-08-27 00:12:27 -0700684 const struct linux_prom_registers *regs;
Wang Chen8f15ea42008-11-12 23:38:36 -0800685 struct sunqe *qep = netdev_priv(dev);
Grant Likely2dc11582010-08-06 09:25:50 -0600686 struct platform_device *op;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700687
Jiri Pirko7826d432013-01-06 00:44:26 +0000688 strlcpy(info->driver, "sunqe", sizeof(info->driver));
689 strlcpy(info->version, "3.0", sizeof(info->version));
David S. Miller8e912b32008-08-27 00:12:27 -0700690
691 op = qep->op;
Grant Likely61c7a082010-04-13 16:12:29 -0700692 regs = of_get_property(op->dev.of_node, "reg", NULL);
David S. Miller8e912b32008-08-27 00:12:27 -0700693 if (regs)
Jiri Pirko7826d432013-01-06 00:44:26 +0000694 snprintf(info->bus_info, sizeof(info->bus_info), "SBUS:%d",
695 regs->which_io);
David S. Miller8e912b32008-08-27 00:12:27 -0700696
Linus Torvalds1da177e2005-04-16 15:20:36 -0700697}
698
699static u32 qe_get_link(struct net_device *dev)
700{
Wang Chen8f15ea42008-11-12 23:38:36 -0800701 struct sunqe *qep = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700702 void __iomem *mregs = qep->mregs;
703 u8 phyconfig;
704
705 spin_lock_irq(&qep->lock);
706 phyconfig = sbus_readb(mregs + MREGS_PHYCONFIG);
707 spin_unlock_irq(&qep->lock);
708
Eric Dumazet807540b2010-09-23 05:40:09 +0000709 return phyconfig & MREGS_PHYCONFIG_LSTAT;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700710}
711
Jeff Garzik7282d492006-09-13 14:30:00 -0400712static const struct ethtool_ops qe_ethtool_ops = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700713 .get_drvinfo = qe_get_drvinfo,
714 .get_link = qe_get_link,
715};
716
717/* This is only called once at boot time for each card probed. */
Grant Likely2dc11582010-08-06 09:25:50 -0600718static void qec_init_once(struct sunqec *qecp, struct platform_device *op)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700719{
720 u8 bsizes = qecp->qec_bursts;
721
David S. Miller63237ee2008-08-26 23:33:42 -0700722 if (sbus_can_burst64() && (bsizes & DMA_BURST64)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700723 sbus_writel(GLOB_CTRL_B64, qecp->gregs + GLOB_CTRL);
724 } else if (bsizes & DMA_BURST32) {
725 sbus_writel(GLOB_CTRL_B32, qecp->gregs + GLOB_CTRL);
726 } else {
727 sbus_writel(GLOB_CTRL_B16, qecp->gregs + GLOB_CTRL);
728 }
729
730 /* Packetsize only used in 100baseT BigMAC configurations,
731 * set it to zero just to be on the safe side.
732 */
733 sbus_writel(GLOB_PSIZE_2048, qecp->gregs + GLOB_PSIZE);
734
735 /* Set the local memsize register, divided up to one piece per QE channel. */
David S. Miller8e912b32008-08-27 00:12:27 -0700736 sbus_writel((resource_size(&op->resource[1]) >> 2),
Linus Torvalds1da177e2005-04-16 15:20:36 -0700737 qecp->gregs + GLOB_MSIZE);
738
739 /* Divide up the local QEC memory amongst the 4 QE receiver and
740 * transmitter FIFOs. Basically it is (total / 2 / num_channels).
741 */
David S. Miller8e912b32008-08-27 00:12:27 -0700742 sbus_writel((resource_size(&op->resource[1]) >> 2) >> 1,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700743 qecp->gregs + GLOB_TSIZE);
David S. Miller8e912b32008-08-27 00:12:27 -0700744 sbus_writel((resource_size(&op->resource[1]) >> 2) >> 1,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700745 qecp->gregs + GLOB_RSIZE);
746}
747
Bill Pembertonf73d12b2012-12-03 09:24:02 -0500748static u8 qec_get_burst(struct device_node *dp)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700749{
Linus Torvalds1da177e2005-04-16 15:20:36 -0700750 u8 bsizes, bsizes_more;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700751
David S. Millerecba38a2006-06-23 21:23:01 -0700752 /* Find and set the burst sizes for the QEC, since it
753 * does the actual dma for all 4 channels.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700754 */
David S. Millerecba38a2006-06-23 21:23:01 -0700755 bsizes = of_getintprop_default(dp, "burst-sizes", 0xff);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700756 bsizes &= 0xff;
David S. Millerecba38a2006-06-23 21:23:01 -0700757 bsizes_more = of_getintprop_default(dp->parent, "burst-sizes", 0xff);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700758
759 if (bsizes_more != 0xff)
760 bsizes &= bsizes_more;
761 if (bsizes == 0xff || (bsizes & DMA_BURST16) == 0 ||
David S. Millerecba38a2006-06-23 21:23:01 -0700762 (bsizes & DMA_BURST32)==0)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700763 bsizes = (DMA_BURST32 - 1);
764
David S. Millerecba38a2006-06-23 21:23:01 -0700765 return bsizes;
766}
Linus Torvalds1da177e2005-04-16 15:20:36 -0700767
Bill Pembertonf73d12b2012-12-03 09:24:02 -0500768static struct sunqec *get_qec(struct platform_device *child)
David S. Millerecba38a2006-06-23 21:23:01 -0700769{
Grant Likely2dc11582010-08-06 09:25:50 -0600770 struct platform_device *op = to_platform_device(child->dev.parent);
David S. Millerecba38a2006-06-23 21:23:01 -0700771 struct sunqec *qecp;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700772
David S. Miller8e912b32008-08-27 00:12:27 -0700773 qecp = dev_get_drvdata(&op->dev);
David S. Millerecba38a2006-06-23 21:23:01 -0700774 if (!qecp) {
775 qecp = kzalloc(sizeof(struct sunqec), GFP_KERNEL);
776 if (qecp) {
777 u32 ctrl;
778
David S. Miller8e912b32008-08-27 00:12:27 -0700779 qecp->op = op;
780 qecp->gregs = of_ioremap(&op->resource[0], 0,
781 GLOB_REG_SIZE,
782 "QEC Global Registers");
David S. Millerecba38a2006-06-23 21:23:01 -0700783 if (!qecp->gregs)
784 goto fail;
785
786 /* Make sure the QEC is in MACE mode. */
787 ctrl = sbus_readl(qecp->gregs + GLOB_CTRL);
788 ctrl &= 0xf0000000;
789 if (ctrl != GLOB_CTRL_MMODE) {
790 printk(KERN_ERR "qec: Not in MACE mode!\n");
791 goto fail;
792 }
793
794 if (qec_global_reset(qecp->gregs))
795 goto fail;
796
Grant Likely61c7a082010-04-13 16:12:29 -0700797 qecp->qec_bursts = qec_get_burst(op->dev.of_node);
David S. Millerecba38a2006-06-23 21:23:01 -0700798
David S. Miller8e912b32008-08-27 00:12:27 -0700799 qec_init_once(qecp, op);
David S. Millerecba38a2006-06-23 21:23:01 -0700800
Grant Likely1636f8a2010-06-18 11:09:58 -0600801 if (request_irq(op->archdata.irqs[0], qec_interrupt,
Thomas Gleixner1fb9df52006-07-01 19:29:39 -0700802 IRQF_SHARED, "qec", (void *) qecp)) {
David S. Millerecba38a2006-06-23 21:23:01 -0700803 printk(KERN_ERR "qec: Can't register irq.\n");
804 goto fail;
805 }
806
David S. Miller8e912b32008-08-27 00:12:27 -0700807 dev_set_drvdata(&op->dev, qecp);
808
David S. Millerecba38a2006-06-23 21:23:01 -0700809 qecp->next_module = root_qec_dev;
810 root_qec_dev = qecp;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700811 }
David S. Millerecba38a2006-06-23 21:23:01 -0700812 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700813
David S. Millerecba38a2006-06-23 21:23:01 -0700814 return qecp;
815
816fail:
817 if (qecp->gregs)
David S. Miller8e912b32008-08-27 00:12:27 -0700818 of_iounmap(&op->resource[0], qecp->gregs, GLOB_REG_SIZE);
David S. Millerecba38a2006-06-23 21:23:01 -0700819 kfree(qecp);
820 return NULL;
821}
822
David S. Millerecd41372009-03-23 13:33:37 -0700823static const struct net_device_ops qec_ops = {
824 .ndo_open = qe_open,
825 .ndo_stop = qe_close,
826 .ndo_start_xmit = qe_start_xmit,
Jiri Pirkoafc4b132011-08-16 06:29:01 +0000827 .ndo_set_rx_mode = qe_set_multicast,
David S. Millerecd41372009-03-23 13:33:37 -0700828 .ndo_tx_timeout = qe_tx_timeout,
David S. Millerdac46962009-03-23 14:29:24 -0700829 .ndo_change_mtu = eth_change_mtu,
830 .ndo_set_mac_address = eth_mac_addr,
831 .ndo_validate_addr = eth_validate_addr,
David S. Millerecd41372009-03-23 13:33:37 -0700832};
833
Bill Pembertonf73d12b2012-12-03 09:24:02 -0500834static int qec_ether_init(struct platform_device *op)
David S. Millerecba38a2006-06-23 21:23:01 -0700835{
836 static unsigned version_printed;
837 struct net_device *dev;
David S. Millerecba38a2006-06-23 21:23:01 -0700838 struct sunqec *qecp;
David S. Miller8e912b32008-08-27 00:12:27 -0700839 struct sunqe *qe;
David S. Millerecba38a2006-06-23 21:23:01 -0700840 int i, res;
841
842 if (version_printed++ == 0)
843 printk(KERN_INFO "%s", version);
844
845 dev = alloc_etherdev(sizeof(struct sunqe));
846 if (!dev)
847 return -ENOMEM;
848
Marcel van Niesd0dc1122007-04-21 15:31:58 -0700849 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
850
David S. Millerecba38a2006-06-23 21:23:01 -0700851 qe = netdev_priv(dev);
852
David S. Miller8e912b32008-08-27 00:12:27 -0700853 res = -ENODEV;
854
Grant Likely61c7a082010-04-13 16:12:29 -0700855 i = of_getintprop_default(op->dev.of_node, "channel#", -1);
David S. Miller8e912b32008-08-27 00:12:27 -0700856 if (i == -1)
857 goto fail;
David S. Millerecba38a2006-06-23 21:23:01 -0700858 qe->channel = i;
859 spin_lock_init(&qe->lock);
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400860
David S. Miller8e912b32008-08-27 00:12:27 -0700861 qecp = get_qec(op);
David S. Millerecba38a2006-06-23 21:23:01 -0700862 if (!qecp)
863 goto fail;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700864
David S. Millerecba38a2006-06-23 21:23:01 -0700865 qecp->qes[qe->channel] = qe;
866 qe->dev = dev;
867 qe->parent = qecp;
David S. Miller8e912b32008-08-27 00:12:27 -0700868 qe->op = op;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700869
David S. Millerecba38a2006-06-23 21:23:01 -0700870 res = -ENOMEM;
David S. Miller8e912b32008-08-27 00:12:27 -0700871 qe->qcregs = of_ioremap(&op->resource[0], 0,
872 CREG_REG_SIZE, "QEC Channel Registers");
David S. Millerecba38a2006-06-23 21:23:01 -0700873 if (!qe->qcregs) {
874 printk(KERN_ERR "qe: Cannot map channel registers.\n");
875 goto fail;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700876 }
877
David S. Miller8e912b32008-08-27 00:12:27 -0700878 qe->mregs = of_ioremap(&op->resource[1], 0,
879 MREGS_REG_SIZE, "QE MACE Registers");
David S. Millerecba38a2006-06-23 21:23:01 -0700880 if (!qe->mregs) {
881 printk(KERN_ERR "qe: Cannot map MACE registers.\n");
882 goto fail;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700883 }
884
David S. Miller8e912b32008-08-27 00:12:27 -0700885 qe->qe_block = dma_alloc_coherent(&op->dev, PAGE_SIZE,
David S. Miller738f2b72008-08-27 18:09:11 -0700886 &qe->qblock_dvma, GFP_ATOMIC);
David S. Miller8e912b32008-08-27 00:12:27 -0700887 qe->buffers = dma_alloc_coherent(&op->dev, sizeof(struct sunqe_buffers),
David S. Miller738f2b72008-08-27 18:09:11 -0700888 &qe->buffers_dvma, GFP_ATOMIC);
David S. Millerecba38a2006-06-23 21:23:01 -0700889 if (qe->qe_block == NULL || qe->qblock_dvma == 0 ||
890 qe->buffers == NULL || qe->buffers_dvma == 0)
891 goto fail;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700892
David S. Millerecba38a2006-06-23 21:23:01 -0700893 /* Stop this QE. */
894 qe_stop(qe);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700895
David S. Miller8e912b32008-08-27 00:12:27 -0700896 SET_NETDEV_DEV(dev, &op->dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700897
David S. Millerecba38a2006-06-23 21:23:01 -0700898 dev->watchdog_timeo = 5*HZ;
Grant Likely1636f8a2010-06-18 11:09:58 -0600899 dev->irq = op->archdata.irqs[0];
David S. Millerecba38a2006-06-23 21:23:01 -0700900 dev->dma = 0;
901 dev->ethtool_ops = &qe_ethtool_ops;
David S. Millerecd41372009-03-23 13:33:37 -0700902 dev->netdev_ops = &qec_ops;
David S. Millerecba38a2006-06-23 21:23:01 -0700903
904 res = register_netdev(dev);
905 if (res)
906 goto fail;
907
David S. Miller8e912b32008-08-27 00:12:27 -0700908 dev_set_drvdata(&op->dev, qe);
David S. Millerecba38a2006-06-23 21:23:01 -0700909
Danny Kukawkad5589502012-02-24 03:45:57 +0000910 printk(KERN_INFO "%s: qe channel[%d] %pM\n", dev->name, qe->channel,
911 dev->dev_addr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700912 return 0;
913
David S. Millerecba38a2006-06-23 21:23:01 -0700914fail:
915 if (qe->qcregs)
David S. Miller8e912b32008-08-27 00:12:27 -0700916 of_iounmap(&op->resource[0], qe->qcregs, CREG_REG_SIZE);
David S. Millerecba38a2006-06-23 21:23:01 -0700917 if (qe->mregs)
David S. Miller8e912b32008-08-27 00:12:27 -0700918 of_iounmap(&op->resource[1], qe->mregs, MREGS_REG_SIZE);
David S. Millerecba38a2006-06-23 21:23:01 -0700919 if (qe->qe_block)
David S. Miller8e912b32008-08-27 00:12:27 -0700920 dma_free_coherent(&op->dev, PAGE_SIZE,
921 qe->qe_block, qe->qblock_dvma);
David S. Millerecba38a2006-06-23 21:23:01 -0700922 if (qe->buffers)
David S. Miller8e912b32008-08-27 00:12:27 -0700923 dma_free_coherent(&op->dev,
David S. Miller738f2b72008-08-27 18:09:11 -0700924 sizeof(struct sunqe_buffers),
925 qe->buffers,
926 qe->buffers_dvma);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700927
David S. Millerecba38a2006-06-23 21:23:01 -0700928 free_netdev(dev);
929
Linus Torvalds1da177e2005-04-16 15:20:36 -0700930 return res;
931}
932
Bill Pembertonf73d12b2012-12-03 09:24:02 -0500933static int qec_sbus_probe(struct platform_device *op)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700934{
David S. Miller8e912b32008-08-27 00:12:27 -0700935 return qec_ether_init(op);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700936}
937
Bill Pembertonf73d12b2012-12-03 09:24:02 -0500938static int qec_sbus_remove(struct platform_device *op)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700939{
David S. Miller8e912b32008-08-27 00:12:27 -0700940 struct sunqe *qp = dev_get_drvdata(&op->dev);
David S. Millerecba38a2006-06-23 21:23:01 -0700941 struct net_device *net_dev = qp->dev;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700942
Marcel van Niesd0dc1122007-04-21 15:31:58 -0700943 unregister_netdev(net_dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700944
David S. Miller8e912b32008-08-27 00:12:27 -0700945 of_iounmap(&op->resource[0], qp->qcregs, CREG_REG_SIZE);
946 of_iounmap(&op->resource[1], qp->mregs, MREGS_REG_SIZE);
947 dma_free_coherent(&op->dev, PAGE_SIZE,
948 qp->qe_block, qp->qblock_dvma);
949 dma_free_coherent(&op->dev, sizeof(struct sunqe_buffers),
950 qp->buffers, qp->buffers_dvma);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700951
David S. Millerecba38a2006-06-23 21:23:01 -0700952 free_netdev(net_dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700953
David S. Miller8e912b32008-08-27 00:12:27 -0700954 dev_set_drvdata(&op->dev, NULL);
David S. Millerecba38a2006-06-23 21:23:01 -0700955
Linus Torvalds1da177e2005-04-16 15:20:36 -0700956 return 0;
957}
958
David S. Millerfd098312008-08-31 01:23:17 -0700959static const struct of_device_id qec_sbus_match[] = {
David S. Millerecba38a2006-06-23 21:23:01 -0700960 {
961 .name = "qe",
962 },
963 {},
964};
965
966MODULE_DEVICE_TABLE(of, qec_sbus_match);
967
Grant Likely74888762011-02-22 21:05:51 -0700968static struct platform_driver qec_sbus_driver = {
Grant Likely40182942010-04-13 16:13:02 -0700969 .driver = {
970 .name = "qec",
971 .owner = THIS_MODULE,
972 .of_match_table = qec_sbus_match,
973 },
David S. Millerecba38a2006-06-23 21:23:01 -0700974 .probe = qec_sbus_probe,
Bill Pembertonf73d12b2012-12-03 09:24:02 -0500975 .remove = qec_sbus_remove,
David S. Millerecba38a2006-06-23 21:23:01 -0700976};
977
978static int __init qec_init(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700979{
Grant Likely74888762011-02-22 21:05:51 -0700980 return platform_driver_register(&qec_sbus_driver);
David S. Millerecba38a2006-06-23 21:23:01 -0700981}
982
983static void __exit qec_exit(void)
984{
Grant Likely74888762011-02-22 21:05:51 -0700985 platform_driver_unregister(&qec_sbus_driver);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700986
987 while (root_qec_dev) {
David S. Millerecba38a2006-06-23 21:23:01 -0700988 struct sunqec *next = root_qec_dev->next_module;
Grant Likely2dc11582010-08-06 09:25:50 -0600989 struct platform_device *op = root_qec_dev->op;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700990
Grant Likely1636f8a2010-06-18 11:09:58 -0600991 free_irq(op->archdata.irqs[0], (void *) root_qec_dev);
David S. Miller8e912b32008-08-27 00:12:27 -0700992 of_iounmap(&op->resource[0], root_qec_dev->gregs,
993 GLOB_REG_SIZE);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700994 kfree(root_qec_dev);
David S. Millerecba38a2006-06-23 21:23:01 -0700995
996 root_qec_dev = next;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700997 }
998}
999
David S. Millerecba38a2006-06-23 21:23:01 -07001000module_init(qec_init);
1001module_exit(qec_exit);