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Nicolas Ferredc78baa2009-07-03 19:24:33 +02001/*
2 * Driver for the Atmel AHB DMA Controller (aka HDMA or DMAC on AT91 systems)
3 *
4 * Copyright (C) 2008 Atmel Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 *
Nicolas Ferre9102d872012-06-12 10:44:55 +020012 * This supports the Atmel AHB DMA Controller found in several Atmel SoCs.
13 * The only Atmel DMA Controller that is not covered by this driver is the one
14 * found on AT91SAM9263.
Nicolas Ferredc78baa2009-07-03 19:24:33 +020015 */
16
Ludovic Desroches62971b22013-06-13 10:39:39 +020017#include <dt-bindings/dma/at91.h>
Nicolas Ferredc78baa2009-07-03 19:24:33 +020018#include <linux/clk.h>
19#include <linux/dmaengine.h>
20#include <linux/dma-mapping.h>
21#include <linux/dmapool.h>
22#include <linux/interrupt.h>
23#include <linux/module.h>
24#include <linux/platform_device.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090025#include <linux/slab.h>
Nicolas Ferrec5115952011-10-17 14:56:41 +020026#include <linux/of.h>
27#include <linux/of_device.h>
Ludovic Desrochesbbe89c82013-04-19 09:11:18 +000028#include <linux/of_dma.h>
Nicolas Ferredc78baa2009-07-03 19:24:33 +020029
30#include "at_hdmac_regs.h"
Russell King - ARM Linuxd2ebfb32012-03-06 22:34:26 +000031#include "dmaengine.h"
Nicolas Ferredc78baa2009-07-03 19:24:33 +020032
33/*
34 * Glossary
35 * --------
36 *
37 * at_hdmac : Name of the ATmel AHB DMA Controller
38 * at_dma_ / atdma : ATmel DMA controller entity related
39 * atc_ / atchan : ATmel DMA Channel entity related
40 */
41
42#define ATC_DEFAULT_CFG (ATC_FIFOCFG_HALFFIFO)
Nicolas Ferreae14d4b2011-04-30 16:57:49 +020043#define ATC_DEFAULT_CTRLB (ATC_SIF(AT_DMA_MEM_IF) \
44 |ATC_DIF(AT_DMA_MEM_IF))
Ludovic Desroches816070e2015-01-06 17:36:26 +010045#define ATC_DMA_BUSWIDTHS\
46 (BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) |\
47 BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |\
48 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |\
49 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES))
Nicolas Ferredc78baa2009-07-03 19:24:33 +020050
Cyrille Pitchen93dce3a2015-06-18 13:25:41 +020051#define ATC_MAX_DSCR_TRIALS 10
52
Nicolas Ferredc78baa2009-07-03 19:24:33 +020053/*
54 * Initial number of descriptors to allocate for each channel. This could
55 * be increased during dma usage.
56 */
57static unsigned int init_nr_desc_per_channel = 64;
58module_param(init_nr_desc_per_channel, uint, 0644);
59MODULE_PARM_DESC(init_nr_desc_per_channel,
60 "initial descriptors per channel (default: 64)");
61
62
63/* prototypes */
64static dma_cookie_t atc_tx_submit(struct dma_async_tx_descriptor *tx);
Elen Songd48de6f2013-05-10 11:01:46 +080065static void atc_issue_pending(struct dma_chan *chan);
Nicolas Ferredc78baa2009-07-03 19:24:33 +020066
67
68/*----------------------------------------------------------------------*/
69
Torsten Fleischer265567f2015-02-23 17:54:11 +010070static inline unsigned int atc_get_xfer_width(dma_addr_t src, dma_addr_t dst,
71 size_t len)
72{
73 unsigned int width;
74
75 if (!((src | dst | len) & 3))
76 width = 2;
77 else if (!((src | dst | len) & 1))
78 width = 1;
79 else
80 width = 0;
81
82 return width;
83}
84
Nicolas Ferredc78baa2009-07-03 19:24:33 +020085static struct at_desc *atc_first_active(struct at_dma_chan *atchan)
86{
87 return list_first_entry(&atchan->active_list,
88 struct at_desc, desc_node);
89}
90
91static struct at_desc *atc_first_queued(struct at_dma_chan *atchan)
92{
93 return list_first_entry(&atchan->queue,
94 struct at_desc, desc_node);
95}
96
97/**
Uwe Kleine-König421f91d2010-06-11 12:17:00 +020098 * atc_alloc_descriptor - allocate and return an initialized descriptor
Nicolas Ferredc78baa2009-07-03 19:24:33 +020099 * @chan: the channel to allocate descriptors for
100 * @gfp_flags: GFP allocation flags
101 *
102 * Note: The ack-bit is positioned in the descriptor flag at creation time
103 * to make initial allocation more convenient. This bit will be cleared
104 * and control will be given to client at usage time (during
105 * preparation functions).
106 */
107static struct at_desc *atc_alloc_descriptor(struct dma_chan *chan,
108 gfp_t gfp_flags)
109{
110 struct at_desc *desc = NULL;
111 struct at_dma *atdma = to_at_dma(chan->device);
112 dma_addr_t phys;
113
114 desc = dma_pool_alloc(atdma->dma_desc_pool, gfp_flags, &phys);
115 if (desc) {
116 memset(desc, 0, sizeof(struct at_desc));
Dan Williams285a3c72009-09-08 17:53:03 -0700117 INIT_LIST_HEAD(&desc->tx_list);
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200118 dma_async_tx_descriptor_init(&desc->txd, chan);
119 /* txd.flags will be overwritten in prep functions */
120 desc->txd.flags = DMA_CTRL_ACK;
121 desc->txd.tx_submit = atc_tx_submit;
122 desc->txd.phys = phys;
123 }
124
125 return desc;
126}
127
128/**
André Goddard Rosaaf901ca2009-11-14 13:09:05 -0200129 * atc_desc_get - get an unused descriptor from free_list
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200130 * @atchan: channel we want a new descriptor for
131 */
132static struct at_desc *atc_desc_get(struct at_dma_chan *atchan)
133{
134 struct at_desc *desc, *_desc;
135 struct at_desc *ret = NULL;
Nicolas Ferred8cb04b2011-07-27 12:21:28 +0000136 unsigned long flags;
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200137 unsigned int i = 0;
138 LIST_HEAD(tmp_list);
139
Nicolas Ferred8cb04b2011-07-27 12:21:28 +0000140 spin_lock_irqsave(&atchan->lock, flags);
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200141 list_for_each_entry_safe(desc, _desc, &atchan->free_list, desc_node) {
142 i++;
143 if (async_tx_test_ack(&desc->txd)) {
144 list_del(&desc->desc_node);
145 ret = desc;
146 break;
147 }
148 dev_dbg(chan2dev(&atchan->chan_common),
149 "desc %p not ACKed\n", desc);
150 }
Nicolas Ferred8cb04b2011-07-27 12:21:28 +0000151 spin_unlock_irqrestore(&atchan->lock, flags);
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200152 dev_vdbg(chan2dev(&atchan->chan_common),
153 "scanned %u descriptors on freelist\n", i);
154
155 /* no more descriptor available in initial pool: create one more */
156 if (!ret) {
157 ret = atc_alloc_descriptor(&atchan->chan_common, GFP_ATOMIC);
158 if (ret) {
Nicolas Ferred8cb04b2011-07-27 12:21:28 +0000159 spin_lock_irqsave(&atchan->lock, flags);
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200160 atchan->descs_allocated++;
Nicolas Ferred8cb04b2011-07-27 12:21:28 +0000161 spin_unlock_irqrestore(&atchan->lock, flags);
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200162 } else {
163 dev_err(chan2dev(&atchan->chan_common),
164 "not enough descriptors available\n");
165 }
166 }
167
168 return ret;
169}
170
171/**
172 * atc_desc_put - move a descriptor, including any children, to the free list
173 * @atchan: channel we work on
174 * @desc: descriptor, at the head of a chain, to move to free list
175 */
176static void atc_desc_put(struct at_dma_chan *atchan, struct at_desc *desc)
177{
178 if (desc) {
179 struct at_desc *child;
Nicolas Ferred8cb04b2011-07-27 12:21:28 +0000180 unsigned long flags;
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200181
Nicolas Ferred8cb04b2011-07-27 12:21:28 +0000182 spin_lock_irqsave(&atchan->lock, flags);
Dan Williams285a3c72009-09-08 17:53:03 -0700183 list_for_each_entry(child, &desc->tx_list, desc_node)
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200184 dev_vdbg(chan2dev(&atchan->chan_common),
185 "moving child desc %p to freelist\n",
186 child);
Dan Williams285a3c72009-09-08 17:53:03 -0700187 list_splice_init(&desc->tx_list, &atchan->free_list);
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200188 dev_vdbg(chan2dev(&atchan->chan_common),
189 "moving desc %p to freelist\n", desc);
190 list_add(&desc->desc_node, &atchan->free_list);
Nicolas Ferred8cb04b2011-07-27 12:21:28 +0000191 spin_unlock_irqrestore(&atchan->lock, flags);
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200192 }
193}
194
195/**
Masanari Iidad73111c2012-08-04 23:37:53 +0900196 * atc_desc_chain - build chain adding a descriptor
197 * @first: address of first descriptor of the chain
198 * @prev: address of previous descriptor of the chain
Nicolas Ferre53830cc2011-04-30 16:57:46 +0200199 * @desc: descriptor to queue
200 *
201 * Called from prep_* functions
202 */
203static void atc_desc_chain(struct at_desc **first, struct at_desc **prev,
204 struct at_desc *desc)
205{
206 if (!(*first)) {
207 *first = desc;
208 } else {
209 /* inform the HW lli about chaining */
210 (*prev)->lli.dscr = desc->txd.phys;
211 /* insert the link descriptor to the LD ring */
212 list_add_tail(&desc->desc_node,
213 &(*first)->tx_list);
214 }
215 *prev = desc;
216}
217
218/**
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200219 * atc_dostart - starts the DMA engine for real
220 * @atchan: the channel we want to start
221 * @first: first descriptor in the list we want to begin with
222 *
223 * Called with atchan->lock held and bh disabled
224 */
225static void atc_dostart(struct at_dma_chan *atchan, struct at_desc *first)
226{
227 struct at_dma *atdma = to_at_dma(atchan->chan_common.device);
228
229 /* ASSERT: channel is idle */
230 if (atc_chan_is_enabled(atchan)) {
231 dev_err(chan2dev(&atchan->chan_common),
232 "BUG: Attempted to start non-idle channel\n");
233 dev_err(chan2dev(&atchan->chan_common),
234 " channel: s0x%x d0x%x ctrl0x%x:0x%x l0x%x\n",
235 channel_readl(atchan, SADDR),
236 channel_readl(atchan, DADDR),
237 channel_readl(atchan, CTRLA),
238 channel_readl(atchan, CTRLB),
239 channel_readl(atchan, DSCR));
240
241 /* The tasklet will hopefully advance the queue... */
242 return;
243 }
244
245 vdbg_dump_regs(atchan);
246
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200247 channel_writel(atchan, SADDR, 0);
248 channel_writel(atchan, DADDR, 0);
249 channel_writel(atchan, CTRLA, 0);
250 channel_writel(atchan, CTRLB, 0);
251 channel_writel(atchan, DSCR, first->txd.phys);
Maxime Ripard5abecfa2015-05-27 16:01:53 +0200252 channel_writel(atchan, SPIP, ATC_SPIP_HOLE(first->src_hole) |
253 ATC_SPIP_BOUNDARY(first->boundary));
254 channel_writel(atchan, DPIP, ATC_DPIP_HOLE(first->dst_hole) |
255 ATC_DPIP_BOUNDARY(first->boundary));
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200256 dma_writel(atdma, CHER, atchan->mask);
257
258 vdbg_dump_regs(atchan);
259}
260
Elen Songd48de6f2013-05-10 11:01:46 +0800261/*
Torsten Fleischerbdf6c792015-02-23 17:54:10 +0100262 * atc_get_desc_by_cookie - get the descriptor of a cookie
263 * @atchan: the DMA channel
264 * @cookie: the cookie to get the descriptor for
Elen Songd48de6f2013-05-10 11:01:46 +0800265 */
Torsten Fleischerbdf6c792015-02-23 17:54:10 +0100266static struct at_desc *atc_get_desc_by_cookie(struct at_dma_chan *atchan,
267 dma_cookie_t cookie)
Elen Songd48de6f2013-05-10 11:01:46 +0800268{
Torsten Fleischerbdf6c792015-02-23 17:54:10 +0100269 struct at_desc *desc, *_desc;
270
271 list_for_each_entry_safe(desc, _desc, &atchan->queue, desc_node) {
272 if (desc->txd.cookie == cookie)
273 return desc;
274 }
Elen Songd48de6f2013-05-10 11:01:46 +0800275
276 list_for_each_entry_safe(desc, _desc, &atchan->active_list, desc_node) {
Torsten Fleischerbdf6c792015-02-23 17:54:10 +0100277 if (desc->txd.cookie == cookie)
278 return desc;
Elen Songd48de6f2013-05-10 11:01:46 +0800279 }
280
Torsten Fleischerbdf6c792015-02-23 17:54:10 +0100281 return NULL;
Elen Songd48de6f2013-05-10 11:01:46 +0800282}
283
Torsten Fleischerbdf6c792015-02-23 17:54:10 +0100284/**
285 * atc_calc_bytes_left - calculates the number of bytes left according to the
286 * value read from CTRLA.
287 *
288 * @current_len: the number of bytes left before reading CTRLA
289 * @ctrla: the value of CTRLA
Elen Songd48de6f2013-05-10 11:01:46 +0800290 */
Cyrille Pitchen93dce3a2015-06-18 13:25:41 +0200291static inline int atc_calc_bytes_left(int current_len, u32 ctrla)
Torsten Fleischerbdf6c792015-02-23 17:54:10 +0100292{
Cyrille Pitchen93dce3a2015-06-18 13:25:41 +0200293 u32 btsize = (ctrla & ATC_BTSIZE_MAX);
294 u32 src_width = ATC_REG_TO_SRC_WIDTH(ctrla);
Torsten Fleischerbdf6c792015-02-23 17:54:10 +0100295
Cyrille Pitchen93dce3a2015-06-18 13:25:41 +0200296 /*
297 * According to the datasheet, when reading the Control A Register
298 * (ctrla), the Buffer Transfer Size (btsize) bitfield refers to the
299 * number of transfers completed on the Source Interface.
300 * So btsize is always a number of source width transfers.
301 */
302 return current_len - (btsize << src_width);
Torsten Fleischerbdf6c792015-02-23 17:54:10 +0100303}
304
305/**
306 * atc_get_bytes_left - get the number of bytes residue for a cookie
307 * @chan: DMA channel
308 * @cookie: transaction identifier to check status of
309 */
310static int atc_get_bytes_left(struct dma_chan *chan, dma_cookie_t cookie)
Elen Songd48de6f2013-05-10 11:01:46 +0800311{
312 struct at_dma_chan *atchan = to_at_dma_chan(chan);
Elen Songd48de6f2013-05-10 11:01:46 +0800313 struct at_desc *desc_first = atc_first_active(atchan);
Torsten Fleischerbdf6c792015-02-23 17:54:10 +0100314 struct at_desc *desc;
315 int ret;
Cyrille Pitchen93dce3a2015-06-18 13:25:41 +0200316 u32 ctrla, dscr, trials;
Elen Songd48de6f2013-05-10 11:01:46 +0800317
318 /*
Torsten Fleischerbdf6c792015-02-23 17:54:10 +0100319 * If the cookie doesn't match to the currently running transfer then
320 * we can return the total length of the associated DMA transfer,
321 * because it is still queued.
Elen Songd48de6f2013-05-10 11:01:46 +0800322 */
Torsten Fleischerbdf6c792015-02-23 17:54:10 +0100323 desc = atc_get_desc_by_cookie(atchan, cookie);
324 if (desc == NULL)
325 return -EINVAL;
326 else if (desc != desc_first)
327 return desc->total_len;
Elen Songd48de6f2013-05-10 11:01:46 +0800328
Torsten Fleischerbdf6c792015-02-23 17:54:10 +0100329 /* cookie matches to the currently running transfer */
330 ret = desc_first->total_len;
Alexandre Belloni6758dda2014-08-01 18:51:46 +0200331
Torsten Fleischerbdf6c792015-02-23 17:54:10 +0100332 if (desc_first->lli.dscr) {
333 /* hardware linked list transfer */
Alexandre Belloni6758dda2014-08-01 18:51:46 +0200334
Elen Songd48de6f2013-05-10 11:01:46 +0800335 /*
Torsten Fleischerbdf6c792015-02-23 17:54:10 +0100336 * Calculate the residue by removing the length of the child
337 * descriptors already transferred from the total length.
338 * To get the current child descriptor we can use the value of
339 * the channel's DSCR register and compare it against the value
340 * of the hardware linked list structure of each child
341 * descriptor.
Cyrille Pitchen93dce3a2015-06-18 13:25:41 +0200342 *
343 * The CTRLA register provides us with the amount of data
344 * already read from the source for the current child
345 * descriptor. So we can compute a more accurate residue by also
346 * removing the number of bytes corresponding to this amount of
347 * data.
348 *
349 * However, the DSCR and CTRLA registers cannot be read both
350 * atomically. Hence a race condition may occur: the first read
351 * register may refer to one child descriptor whereas the second
352 * read may refer to a later child descriptor in the list
353 * because of the DMA transfer progression inbetween the two
354 * reads.
355 *
356 * One solution could have been to pause the DMA transfer, read
357 * the DSCR and CTRLA then resume the DMA transfer. Nonetheless,
358 * this approach presents some drawbacks:
359 * - If the DMA transfer is paused, RX overruns or TX underruns
360 * are more likey to occur depending on the system latency.
361 * Taking the USART driver as an example, it uses a cyclic DMA
362 * transfer to read data from the Receive Holding Register
363 * (RHR) to avoid RX overruns since the RHR is not protected
364 * by any FIFO on most Atmel SoCs. So pausing the DMA transfer
365 * to compute the residue would break the USART driver design.
366 * - The atc_pause() function masks interrupts but we'd rather
367 * avoid to do so for system latency purpose.
368 *
369 * Then we'd rather use another solution: the DSCR is read a
370 * first time, the CTRLA is read in turn, next the DSCR is read
371 * a second time. If the two consecutive read values of the DSCR
372 * are the same then we assume both refers to the very same
373 * child descriptor as well as the CTRLA value read inbetween
374 * does. For cyclic tranfers, the assumption is that a full loop
375 * is "not so fast".
376 * If the two DSCR values are different, we read again the CTRLA
377 * then the DSCR till two consecutive read values from DSCR are
378 * equal or till the maxium trials is reach.
379 * This algorithm is very unlikely not to find a stable value for
380 * DSCR.
Elen Songd48de6f2013-05-10 11:01:46 +0800381 */
Elen Songd48de6f2013-05-10 11:01:46 +0800382
Torsten Fleischerbdf6c792015-02-23 17:54:10 +0100383 dscr = channel_readl(atchan, DSCR);
Cyrille Pitchen93dce3a2015-06-18 13:25:41 +0200384 rmb(); /* ensure DSCR is read before CTRLA */
385 ctrla = channel_readl(atchan, CTRLA);
386 for (trials = 0; trials < ATC_MAX_DSCR_TRIALS; ++trials) {
387 u32 new_dscr;
388
389 rmb(); /* ensure DSCR is read after CTRLA */
390 new_dscr = channel_readl(atchan, DSCR);
391
392 /*
393 * If the DSCR register value has not changed inside the
394 * DMA controller since the previous read, we assume
395 * that both the dscr and ctrla values refers to the
396 * very same descriptor.
397 */
398 if (likely(new_dscr == dscr))
399 break;
400
401 /*
402 * DSCR has changed inside the DMA controller, so the
403 * previouly read value of CTRLA may refer to an already
404 * processed descriptor hence could be outdated.
405 * We need to update ctrla to match the current
406 * descriptor.
407 */
408 dscr = new_dscr;
409 rmb(); /* ensure DSCR is read before CTRLA */
410 ctrla = channel_readl(atchan, CTRLA);
411 }
412 if (unlikely(trials >= ATC_MAX_DSCR_TRIALS))
413 return -ETIMEDOUT;
Torsten Fleischerbdf6c792015-02-23 17:54:10 +0100414
415 /* for the first descriptor we can be more accurate */
416 if (desc_first->lli.dscr == dscr)
Cyrille Pitchen93dce3a2015-06-18 13:25:41 +0200417 return atc_calc_bytes_left(ret, ctrla);
Torsten Fleischerbdf6c792015-02-23 17:54:10 +0100418
419 ret -= desc_first->len;
420 list_for_each_entry(desc, &desc_first->tx_list, desc_node) {
421 if (desc->lli.dscr == dscr)
422 break;
423
424 ret -= desc->len;
425 }
426
427 /*
Cyrille Pitchen93dce3a2015-06-18 13:25:41 +0200428 * For the current descriptor in the chain we can calculate
Torsten Fleischerbdf6c792015-02-23 17:54:10 +0100429 * the remaining bytes using the channel's register.
Torsten Fleischerbdf6c792015-02-23 17:54:10 +0100430 */
Cyrille Pitchen93dce3a2015-06-18 13:25:41 +0200431 ret = atc_calc_bytes_left(ret, ctrla);
Torsten Fleischerbdf6c792015-02-23 17:54:10 +0100432 } else {
433 /* single transfer */
Cyrille Pitchen93dce3a2015-06-18 13:25:41 +0200434 ctrla = channel_readl(atchan, CTRLA);
435 ret = atc_calc_bytes_left(ret, ctrla);
Torsten Fleischerbdf6c792015-02-23 17:54:10 +0100436 }
437
Elen Songd48de6f2013-05-10 11:01:46 +0800438 return ret;
439}
440
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200441/**
442 * atc_chain_complete - finish work for one transaction chain
443 * @atchan: channel we work on
444 * @desc: descriptor at the head of the chain we want do complete
445 *
446 * Called with atchan->lock held and bh disabled */
447static void
448atc_chain_complete(struct at_dma_chan *atchan, struct at_desc *desc)
449{
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200450 struct dma_async_tx_descriptor *txd = &desc->txd;
Maxime Ripard4d112422015-08-24 11:21:15 +0200451 struct at_dma *atdma = to_at_dma(atchan->chan_common.device);
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200452
453 dev_vdbg(chan2dev(&atchan->chan_common),
454 "descriptor %u complete\n", txd->cookie);
455
Vinod Kould4116052012-05-11 11:48:21 +0530456 /* mark the descriptor as complete for non cyclic cases only */
457 if (!atc_chan_is_cyclic(atchan))
458 dma_cookie_complete(txd);
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200459
Maxime Ripard4d112422015-08-24 11:21:15 +0200460 /* If the transfer was a memset, free our temporary buffer */
Maxime Ripardce2a6732015-10-22 11:40:59 +0200461 if (desc->memset_buffer) {
Maxime Ripard4d112422015-08-24 11:21:15 +0200462 dma_pool_free(atdma->memset_pool, desc->memset_vaddr,
463 desc->memset_paddr);
Maxime Ripardce2a6732015-10-22 11:40:59 +0200464 desc->memset_buffer = false;
Maxime Ripard4d112422015-08-24 11:21:15 +0200465 }
466
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200467 /* move children to free_list */
Dan Williams285a3c72009-09-08 17:53:03 -0700468 list_splice_init(&desc->tx_list, &atchan->free_list);
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200469 /* move myself to free_list */
470 list_move(&desc->desc_node, &atchan->free_list);
471
Dan Williamsd38a8c62013-10-18 19:35:23 +0200472 dma_descriptor_unmap(txd);
Nicolas Ferre53830cc2011-04-30 16:57:46 +0200473 /* for cyclic transfers,
474 * no need to replay callback function while stopping */
Nicolas Ferre3c477482011-07-25 21:09:23 +0000475 if (!atc_chan_is_cyclic(atchan)) {
Nicolas Ferre53830cc2011-04-30 16:57:46 +0200476 /*
477 * The API requires that no submissions are done from a
478 * callback, so we don't need to drop the lock here
479 */
Dave Jiangdff232d2016-07-20 13:10:37 -0700480 dmaengine_desc_get_callback_invoke(txd, NULL);
Nicolas Ferre53830cc2011-04-30 16:57:46 +0200481 }
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200482
483 dma_run_dependencies(txd);
484}
485
486/**
487 * atc_complete_all - finish work for all transactions
488 * @atchan: channel to complete transactions for
489 *
490 * Eventually submit queued descriptors if any
491 *
492 * Assume channel is idle while calling this function
493 * Called with atchan->lock held and bh disabled
494 */
495static void atc_complete_all(struct at_dma_chan *atchan)
496{
497 struct at_desc *desc, *_desc;
498 LIST_HEAD(list);
499
500 dev_vdbg(chan2dev(&atchan->chan_common), "complete all\n");
501
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200502 /*
503 * Submit queued descriptors ASAP, i.e. before we go through
504 * the completed ones.
505 */
506 if (!list_empty(&atchan->queue))
507 atc_dostart(atchan, atc_first_queued(atchan));
508 /* empty active_list now it is completed */
509 list_splice_init(&atchan->active_list, &list);
510 /* empty queue list by moving descriptors (if any) to active_list */
511 list_splice_init(&atchan->queue, &atchan->active_list);
512
513 list_for_each_entry_safe(desc, _desc, &list, desc_node)
514 atc_chain_complete(atchan, desc);
515}
516
517/**
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200518 * atc_advance_work - at the end of a transaction, move forward
519 * @atchan: channel where the transaction ended
520 *
521 * Called with atchan->lock held and bh disabled
522 */
523static void atc_advance_work(struct at_dma_chan *atchan)
524{
525 dev_vdbg(chan2dev(&atchan->chan_common), "advance_work\n");
526
Ludovic Desrochesd202f052013-04-18 09:52:59 +0200527 if (atc_chan_is_enabled(atchan))
528 return;
529
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200530 if (list_empty(&atchan->active_list) ||
531 list_is_singular(&atchan->active_list)) {
532 atc_complete_all(atchan);
533 } else {
534 atc_chain_complete(atchan, atc_first_active(atchan));
535 /* advance work */
536 atc_dostart(atchan, atc_first_active(atchan));
537 }
538}
539
540
541/**
542 * atc_handle_error - handle errors reported by DMA controller
543 * @atchan: channel where error occurs
544 *
545 * Called with atchan->lock held and bh disabled
546 */
547static void atc_handle_error(struct at_dma_chan *atchan)
548{
549 struct at_desc *bad_desc;
550 struct at_desc *child;
551
552 /*
553 * The descriptor currently at the head of the active list is
554 * broked. Since we don't have any way to report errors, we'll
555 * just have to scream loudly and try to carry on.
556 */
557 bad_desc = atc_first_active(atchan);
558 list_del_init(&bad_desc->desc_node);
559
560 /* As we are stopped, take advantage to push queued descriptors
561 * in active_list */
562 list_splice_init(&atchan->queue, atchan->active_list.prev);
563
564 /* Try to restart the controller */
565 if (!list_empty(&atchan->active_list))
566 atc_dostart(atchan, atc_first_active(atchan));
567
568 /*
569 * KERN_CRITICAL may seem harsh, but since this only happens
570 * when someone submits a bad physical address in a
571 * descriptor, we should consider ourselves lucky that the
572 * controller flagged an error instead of scribbling over
573 * random memory locations.
574 */
575 dev_crit(chan2dev(&atchan->chan_common),
576 "Bad descriptor submitted for DMA!\n");
577 dev_crit(chan2dev(&atchan->chan_common),
578 " cookie: %d\n", bad_desc->txd.cookie);
579 atc_dump_lli(atchan, &bad_desc->lli);
Dan Williams285a3c72009-09-08 17:53:03 -0700580 list_for_each_entry(child, &bad_desc->tx_list, desc_node)
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200581 atc_dump_lli(atchan, &child->lli);
582
583 /* Pretend the descriptor completed successfully */
584 atc_chain_complete(atchan, bad_desc);
585}
586
Nicolas Ferre53830cc2011-04-30 16:57:46 +0200587/**
588 * atc_handle_cyclic - at the end of a period, run callback function
589 * @atchan: channel used for cyclic operations
590 *
591 * Called with atchan->lock held and bh disabled
592 */
593static void atc_handle_cyclic(struct at_dma_chan *atchan)
594{
595 struct at_desc *first = atc_first_active(atchan);
596 struct dma_async_tx_descriptor *txd = &first->txd;
Nicolas Ferre53830cc2011-04-30 16:57:46 +0200597
598 dev_vdbg(chan2dev(&atchan->chan_common),
599 "new cyclic period llp 0x%08x\n",
600 channel_readl(atchan, DSCR));
601
Dave Jiangdff232d2016-07-20 13:10:37 -0700602 dmaengine_desc_get_callback_invoke(txd, NULL);
Nicolas Ferre53830cc2011-04-30 16:57:46 +0200603}
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200604
605/*-- IRQ & Tasklet ---------------------------------------------------*/
606
607static void atc_tasklet(unsigned long data)
608{
609 struct at_dma_chan *atchan = (struct at_dma_chan *)data;
Nicolas Ferred8cb04b2011-07-27 12:21:28 +0000610 unsigned long flags;
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200611
Nicolas Ferred8cb04b2011-07-27 12:21:28 +0000612 spin_lock_irqsave(&atchan->lock, flags);
Nicolas Ferre53830cc2011-04-30 16:57:46 +0200613 if (test_and_clear_bit(ATC_IS_ERROR, &atchan->status))
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200614 atc_handle_error(atchan);
Nicolas Ferre3c477482011-07-25 21:09:23 +0000615 else if (atc_chan_is_cyclic(atchan))
Nicolas Ferre53830cc2011-04-30 16:57:46 +0200616 atc_handle_cyclic(atchan);
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200617 else
618 atc_advance_work(atchan);
619
Nicolas Ferred8cb04b2011-07-27 12:21:28 +0000620 spin_unlock_irqrestore(&atchan->lock, flags);
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200621}
622
623static irqreturn_t at_dma_interrupt(int irq, void *dev_id)
624{
625 struct at_dma *atdma = (struct at_dma *)dev_id;
626 struct at_dma_chan *atchan;
627 int i;
628 u32 status, pending, imr;
629 int ret = IRQ_NONE;
630
631 do {
632 imr = dma_readl(atdma, EBCIMR);
633 status = dma_readl(atdma, EBCISR);
634 pending = status & imr;
635
636 if (!pending)
637 break;
638
639 dev_vdbg(atdma->dma_common.dev,
640 "interrupt: status = 0x%08x, 0x%08x, 0x%08x\n",
641 status, imr, pending);
642
643 for (i = 0; i < atdma->dma_common.chancnt; i++) {
644 atchan = &atdma->chan[i];
Nicolas Ferre9b3aa582011-04-30 16:57:45 +0200645 if (pending & (AT_DMA_BTC(i) | AT_DMA_ERR(i))) {
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200646 if (pending & AT_DMA_ERR(i)) {
647 /* Disable channel on AHB error */
Nicolas Ferre23b5e3a2011-05-06 19:56:52 +0200648 dma_writel(atdma, CHDR,
649 AT_DMA_RES(i) | atchan->mask);
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200650 /* Give information to tasklet */
Nicolas Ferre53830cc2011-04-30 16:57:46 +0200651 set_bit(ATC_IS_ERROR, &atchan->status);
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200652 }
653 tasklet_schedule(&atchan->tasklet);
654 ret = IRQ_HANDLED;
655 }
656 }
657
658 } while (pending);
659
660 return ret;
661}
662
663
664/*-- DMA Engine API --------------------------------------------------*/
665
666/**
667 * atc_tx_submit - set the prepared descriptor(s) to be executed by the engine
668 * @desc: descriptor at the head of the transaction chain
669 *
670 * Queue chain if DMA engine is working already
671 *
672 * Cookie increment and adding to active_list or queue must be atomic
673 */
674static dma_cookie_t atc_tx_submit(struct dma_async_tx_descriptor *tx)
675{
676 struct at_desc *desc = txd_to_at_desc(tx);
677 struct at_dma_chan *atchan = to_at_dma_chan(tx->chan);
678 dma_cookie_t cookie;
Nicolas Ferred8cb04b2011-07-27 12:21:28 +0000679 unsigned long flags;
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200680
Nicolas Ferred8cb04b2011-07-27 12:21:28 +0000681 spin_lock_irqsave(&atchan->lock, flags);
Russell King - ARM Linux884485e2012-03-06 22:34:46 +0000682 cookie = dma_cookie_assign(tx);
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200683
684 if (list_empty(&atchan->active_list)) {
685 dev_vdbg(chan2dev(tx->chan), "tx_submit: started %u\n",
686 desc->txd.cookie);
687 atc_dostart(atchan, desc);
688 list_add_tail(&desc->desc_node, &atchan->active_list);
689 } else {
690 dev_vdbg(chan2dev(tx->chan), "tx_submit: queued %u\n",
691 desc->txd.cookie);
692 list_add_tail(&desc->desc_node, &atchan->queue);
693 }
694
Nicolas Ferred8cb04b2011-07-27 12:21:28 +0000695 spin_unlock_irqrestore(&atchan->lock, flags);
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200696
697 return cookie;
698}
699
700/**
Maxime Ripard5abecfa2015-05-27 16:01:53 +0200701 * atc_prep_dma_interleaved - prepare memory to memory interleaved operation
702 * @chan: the channel to prepare operation on
703 * @xt: Interleaved transfer template
704 * @flags: tx descriptor status flags
705 */
706static struct dma_async_tx_descriptor *
707atc_prep_dma_interleaved(struct dma_chan *chan,
708 struct dma_interleaved_template *xt,
709 unsigned long flags)
710{
711 struct at_dma_chan *atchan = to_at_dma_chan(chan);
Gustavo A. R. Silva3250df92017-11-20 08:28:14 -0600712 struct data_chunk *first;
Maxime Ripard5abecfa2015-05-27 16:01:53 +0200713 struct at_desc *desc = NULL;
714 size_t xfer_count;
715 unsigned int dwidth;
716 u32 ctrla;
717 u32 ctrlb;
718 size_t len = 0;
719 int i;
720
Maninder Singh44833202015-06-26 16:04:48 +0530721 if (unlikely(!xt || xt->numf != 1 || !xt->frame_size))
722 return NULL;
723
Gustavo A. R. Silva3250df92017-11-20 08:28:14 -0600724 first = xt->sgl;
725
Maxime Ripard5abecfa2015-05-27 16:01:53 +0200726 dev_info(chan2dev(chan),
Arnd Bergmann2c5d7402015-11-12 15:18:22 +0100727 "%s: src=%pad, dest=%pad, numf=%d, frame_size=%d, flags=0x%lx\n",
728 __func__, &xt->src_start, &xt->dst_start, xt->numf,
Maxime Ripard5abecfa2015-05-27 16:01:53 +0200729 xt->frame_size, flags);
730
Maxime Ripard5abecfa2015-05-27 16:01:53 +0200731 /*
732 * The controller can only "skip" X bytes every Y bytes, so we
733 * need to make sure we are given a template that fit that
734 * description, ie a template with chunks that always have the
735 * same size, with the same ICGs.
736 */
737 for (i = 0; i < xt->frame_size; i++) {
738 struct data_chunk *chunk = xt->sgl + i;
739
740 if ((chunk->size != xt->sgl->size) ||
741 (dmaengine_get_dst_icg(xt, chunk) != dmaengine_get_dst_icg(xt, first)) ||
742 (dmaengine_get_src_icg(xt, chunk) != dmaengine_get_src_icg(xt, first))) {
743 dev_err(chan2dev(chan),
744 "%s: the controller can transfer only identical chunks\n",
745 __func__);
746 return NULL;
747 }
748
749 len += chunk->size;
750 }
751
752 dwidth = atc_get_xfer_width(xt->src_start,
753 xt->dst_start, len);
754
755 xfer_count = len >> dwidth;
756 if (xfer_count > ATC_BTSIZE_MAX) {
757 dev_err(chan2dev(chan), "%s: buffer is too big\n", __func__);
758 return NULL;
759 }
760
761 ctrla = ATC_SRC_WIDTH(dwidth) |
762 ATC_DST_WIDTH(dwidth);
763
764 ctrlb = ATC_DEFAULT_CTRLB | ATC_IEN
765 | ATC_SRC_ADDR_MODE_INCR
766 | ATC_DST_ADDR_MODE_INCR
767 | ATC_SRC_PIP
768 | ATC_DST_PIP
769 | ATC_FC_MEM2MEM;
770
771 /* create the transfer */
772 desc = atc_desc_get(atchan);
773 if (!desc) {
774 dev_err(chan2dev(chan),
775 "%s: couldn't allocate our descriptor\n", __func__);
776 return NULL;
777 }
778
779 desc->lli.saddr = xt->src_start;
780 desc->lli.daddr = xt->dst_start;
781 desc->lli.ctrla = ctrla | xfer_count;
782 desc->lli.ctrlb = ctrlb;
783
784 desc->boundary = first->size >> dwidth;
785 desc->dst_hole = (dmaengine_get_dst_icg(xt, first) >> dwidth) + 1;
786 desc->src_hole = (dmaengine_get_src_icg(xt, first) >> dwidth) + 1;
787
788 desc->txd.cookie = -EBUSY;
789 desc->total_len = desc->len = len;
Maxime Ripard5abecfa2015-05-27 16:01:53 +0200790
791 /* set end-of-link to the last link descriptor of list*/
792 set_desc_eol(desc);
793
794 desc->txd.flags = flags; /* client is in control of this ack */
795
796 return &desc->txd;
797}
798
799/**
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200800 * atc_prep_dma_memcpy - prepare a memcpy operation
801 * @chan: the channel to prepare operation on
802 * @dest: operation virtual destination address
803 * @src: operation virtual source address
804 * @len: operation length
805 * @flags: tx descriptor status flags
806 */
807static struct dma_async_tx_descriptor *
808atc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
809 size_t len, unsigned long flags)
810{
811 struct at_dma_chan *atchan = to_at_dma_chan(chan);
812 struct at_desc *desc = NULL;
813 struct at_desc *first = NULL;
814 struct at_desc *prev = NULL;
815 size_t xfer_count;
816 size_t offset;
817 unsigned int src_width;
818 unsigned int dst_width;
819 u32 ctrla;
820 u32 ctrlb;
821
Arnd Bergmann2c5d7402015-11-12 15:18:22 +0100822 dev_vdbg(chan2dev(chan), "prep_dma_memcpy: d%pad s%pad l0x%zx f0x%lx\n",
823 &dest, &src, len, flags);
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200824
825 if (unlikely(!len)) {
826 dev_dbg(chan2dev(chan), "prep_dma_memcpy: length is zero!\n");
827 return NULL;
828 }
829
Nicolas Ferre9b3aa582011-04-30 16:57:45 +0200830 ctrlb = ATC_DEFAULT_CTRLB | ATC_IEN
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200831 | ATC_SRC_ADDR_MODE_INCR
832 | ATC_DST_ADDR_MODE_INCR
833 | ATC_FC_MEM2MEM;
834
835 /*
836 * We can be a lot more clever here, but this should take care
837 * of the most common optimization.
838 */
Torsten Fleischer265567f2015-02-23 17:54:11 +0100839 src_width = dst_width = atc_get_xfer_width(src, dest, len);
840
841 ctrla = ATC_SRC_WIDTH(src_width) |
842 ATC_DST_WIDTH(dst_width);
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200843
844 for (offset = 0; offset < len; offset += xfer_count << src_width) {
845 xfer_count = min_t(size_t, (len - offset) >> src_width,
846 ATC_BTSIZE_MAX);
847
848 desc = atc_desc_get(atchan);
849 if (!desc)
850 goto err_desc_get;
851
852 desc->lli.saddr = src + offset;
853 desc->lli.daddr = dest + offset;
854 desc->lli.ctrla = ctrla | xfer_count;
855 desc->lli.ctrlb = ctrlb;
856
857 desc->txd.cookie = 0;
Torsten Fleischerbdf6c792015-02-23 17:54:10 +0100858 desc->len = xfer_count << src_width;
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200859
Nicolas Ferree257e152011-05-06 19:56:53 +0200860 atc_desc_chain(&first, &prev, desc);
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200861 }
862
863 /* First descriptor of the chain embedds additional information */
864 first->txd.cookie = -EBUSY;
Torsten Fleischerbdf6c792015-02-23 17:54:10 +0100865 first->total_len = len;
866
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200867 /* set end-of-link to the last link descriptor of list*/
868 set_desc_eol(desc);
869
Nicolas Ferre568f7f02011-01-12 15:39:09 +0100870 first->txd.flags = flags; /* client is in control of this ack */
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200871
872 return &first->txd;
873
874err_desc_get:
875 atc_desc_put(atchan, first);
876 return NULL;
877}
878
Maxime Ripardce2a6732015-10-22 11:40:59 +0200879static struct at_desc *atc_create_memset_desc(struct dma_chan *chan,
880 dma_addr_t psrc,
881 dma_addr_t pdst,
882 size_t len)
883{
884 struct at_dma_chan *atchan = to_at_dma_chan(chan);
885 struct at_desc *desc;
886 size_t xfer_count;
887
888 u32 ctrla = ATC_SRC_WIDTH(2) | ATC_DST_WIDTH(2);
889 u32 ctrlb = ATC_DEFAULT_CTRLB | ATC_IEN |
890 ATC_SRC_ADDR_MODE_FIXED |
891 ATC_DST_ADDR_MODE_INCR |
892 ATC_FC_MEM2MEM;
893
894 xfer_count = len >> 2;
895 if (xfer_count > ATC_BTSIZE_MAX) {
896 dev_err(chan2dev(chan), "%s: buffer is too big\n",
897 __func__);
898 return NULL;
899 }
900
901 desc = atc_desc_get(atchan);
902 if (!desc) {
903 dev_err(chan2dev(chan), "%s: can't get a descriptor\n",
904 __func__);
905 return NULL;
906 }
907
908 desc->lli.saddr = psrc;
909 desc->lli.daddr = pdst;
910 desc->lli.ctrla = ctrla | xfer_count;
911 desc->lli.ctrlb = ctrlb;
912
913 desc->txd.cookie = 0;
914 desc->len = len;
915
916 return desc;
917}
918
Maxime Ripard4d112422015-08-24 11:21:15 +0200919/**
920 * atc_prep_dma_memset - prepare a memcpy operation
921 * @chan: the channel to prepare operation on
922 * @dest: operation virtual destination address
923 * @value: value to set memory buffer to
924 * @len: operation length
925 * @flags: tx descriptor status flags
926 */
927static struct dma_async_tx_descriptor *
928atc_prep_dma_memset(struct dma_chan *chan, dma_addr_t dest, int value,
929 size_t len, unsigned long flags)
930{
Maxime Ripard4d112422015-08-24 11:21:15 +0200931 struct at_dma *atdma = to_at_dma(chan->device);
Maxime Ripardce2a6732015-10-22 11:40:59 +0200932 struct at_desc *desc;
933 void __iomem *vaddr;
934 dma_addr_t paddr;
Maxime Ripard4d112422015-08-24 11:21:15 +0200935
Arnd Bergmann2c5d7402015-11-12 15:18:22 +0100936 dev_vdbg(chan2dev(chan), "%s: d%pad v0x%x l0x%zx f0x%lx\n", __func__,
937 &dest, value, len, flags);
Maxime Ripard4d112422015-08-24 11:21:15 +0200938
939 if (unlikely(!len)) {
940 dev_dbg(chan2dev(chan), "%s: length is zero!\n", __func__);
941 return NULL;
942 }
943
944 if (!is_dma_fill_aligned(chan->device, dest, 0, len)) {
945 dev_dbg(chan2dev(chan), "%s: buffer is not aligned\n",
946 __func__);
947 return NULL;
948 }
949
Maxime Ripardce2a6732015-10-22 11:40:59 +0200950 vaddr = dma_pool_alloc(atdma->memset_pool, GFP_ATOMIC, &paddr);
951 if (!vaddr) {
Maxime Ripard4d112422015-08-24 11:21:15 +0200952 dev_err(chan2dev(chan), "%s: couldn't allocate buffer\n",
953 __func__);
Maxime Ripardce2a6732015-10-22 11:40:59 +0200954 return NULL;
955 }
956 *(u32*)vaddr = value;
957
958 desc = atc_create_memset_desc(chan, paddr, dest, len);
959 if (!desc) {
960 dev_err(chan2dev(chan), "%s: couldn't get a descriptor\n",
961 __func__);
962 goto err_free_buffer;
Maxime Ripard4d112422015-08-24 11:21:15 +0200963 }
964
Maxime Ripardce2a6732015-10-22 11:40:59 +0200965 desc->memset_paddr = paddr;
966 desc->memset_vaddr = vaddr;
967 desc->memset_buffer = true;
Maxime Ripard4d112422015-08-24 11:21:15 +0200968
969 desc->txd.cookie = -EBUSY;
Maxime Ripard4d112422015-08-24 11:21:15 +0200970 desc->total_len = len;
971
972 /* set end-of-link on the descriptor */
973 set_desc_eol(desc);
974
975 desc->txd.flags = flags;
976
977 return &desc->txd;
978
Maxime Ripardce2a6732015-10-22 11:40:59 +0200979err_free_buffer:
980 dma_pool_free(atdma->memset_pool, vaddr, paddr);
Maxime Ripard4d112422015-08-24 11:21:15 +0200981 return NULL;
982}
983
Maxime Ripard67d25f02015-10-22 11:41:00 +0200984static struct dma_async_tx_descriptor *
985atc_prep_dma_memset_sg(struct dma_chan *chan,
986 struct scatterlist *sgl,
987 unsigned int sg_len, int value,
988 unsigned long flags)
989{
990 struct at_dma_chan *atchan = to_at_dma_chan(chan);
991 struct at_dma *atdma = to_at_dma(chan->device);
992 struct at_desc *desc = NULL, *first = NULL, *prev = NULL;
993 struct scatterlist *sg;
994 void __iomem *vaddr;
995 dma_addr_t paddr;
996 size_t total_len = 0;
997 int i;
998
999 dev_vdbg(chan2dev(chan), "%s: v0x%x l0x%zx f0x%lx\n", __func__,
1000 value, sg_len, flags);
1001
1002 if (unlikely(!sgl || !sg_len)) {
1003 dev_dbg(chan2dev(chan), "%s: scatterlist is empty!\n",
1004 __func__);
1005 return NULL;
1006 }
1007
1008 vaddr = dma_pool_alloc(atdma->memset_pool, GFP_ATOMIC, &paddr);
1009 if (!vaddr) {
1010 dev_err(chan2dev(chan), "%s: couldn't allocate buffer\n",
1011 __func__);
1012 return NULL;
1013 }
1014 *(u32*)vaddr = value;
1015
1016 for_each_sg(sgl, sg, sg_len, i) {
1017 dma_addr_t dest = sg_dma_address(sg);
1018 size_t len = sg_dma_len(sg);
1019
Arnd Bergmann2c5d7402015-11-12 15:18:22 +01001020 dev_vdbg(chan2dev(chan), "%s: d%pad, l0x%zx\n",
1021 __func__, &dest, len);
Maxime Ripard67d25f02015-10-22 11:41:00 +02001022
1023 if (!is_dma_fill_aligned(chan->device, dest, 0, len)) {
1024 dev_err(chan2dev(chan), "%s: buffer is not aligned\n",
1025 __func__);
1026 goto err_put_desc;
1027 }
1028
1029 desc = atc_create_memset_desc(chan, paddr, dest, len);
1030 if (!desc)
1031 goto err_put_desc;
1032
1033 atc_desc_chain(&first, &prev, desc);
1034
1035 total_len += len;
1036 }
1037
1038 /*
1039 * Only set the buffer pointers on the last descriptor to
1040 * avoid free'ing while we have our transfer still going
1041 */
1042 desc->memset_paddr = paddr;
1043 desc->memset_vaddr = vaddr;
1044 desc->memset_buffer = true;
1045
1046 first->txd.cookie = -EBUSY;
1047 first->total_len = total_len;
1048
1049 /* set end-of-link on the descriptor */
1050 set_desc_eol(desc);
1051
1052 first->txd.flags = flags;
1053
1054 return &first->txd;
1055
1056err_put_desc:
1057 atc_desc_put(atchan, first);
1058 return NULL;
1059}
1060
Nicolas Ferre808347f2009-07-22 20:04:45 +02001061/**
1062 * atc_prep_slave_sg - prepare descriptors for a DMA_SLAVE transaction
1063 * @chan: DMA channel
1064 * @sgl: scatterlist to transfer to/from
1065 * @sg_len: number of entries in @scatterlist
1066 * @direction: DMA direction
1067 * @flags: tx descriptor status flags
Alexandre Bounine185ecb52012-03-08 15:35:13 -05001068 * @context: transaction context (ignored)
Nicolas Ferre808347f2009-07-22 20:04:45 +02001069 */
1070static struct dma_async_tx_descriptor *
1071atc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
Vinod Kouldb8196d2011-10-13 22:34:23 +05301072 unsigned int sg_len, enum dma_transfer_direction direction,
Alexandre Bounine185ecb52012-03-08 15:35:13 -05001073 unsigned long flags, void *context)
Nicolas Ferre808347f2009-07-22 20:04:45 +02001074{
1075 struct at_dma_chan *atchan = to_at_dma_chan(chan);
1076 struct at_dma_slave *atslave = chan->private;
Nicolas Ferrebeeaa102012-03-14 12:41:43 +01001077 struct dma_slave_config *sconfig = &atchan->dma_sconfig;
Nicolas Ferre808347f2009-07-22 20:04:45 +02001078 struct at_desc *first = NULL;
1079 struct at_desc *prev = NULL;
1080 u32 ctrla;
1081 u32 ctrlb;
1082 dma_addr_t reg;
1083 unsigned int reg_width;
1084 unsigned int mem_width;
1085 unsigned int i;
1086 struct scatterlist *sg;
1087 size_t total_len = 0;
1088
Nicolas Ferrecc52a102011-04-30 16:57:47 +02001089 dev_vdbg(chan2dev(chan), "prep_slave_sg (%d): %s f0x%lx\n",
1090 sg_len,
Vinod Kouldb8196d2011-10-13 22:34:23 +05301091 direction == DMA_MEM_TO_DEV ? "TO DEVICE" : "FROM DEVICE",
Nicolas Ferre808347f2009-07-22 20:04:45 +02001092 flags);
1093
1094 if (unlikely(!atslave || !sg_len)) {
Nicolas Ferrec618a9b2012-09-11 17:21:44 +02001095 dev_dbg(chan2dev(chan), "prep_slave_sg: sg length is zero!\n");
Nicolas Ferre808347f2009-07-22 20:04:45 +02001096 return NULL;
1097 }
1098
Nicolas Ferre1dd1ea82012-05-10 12:17:41 +02001099 ctrla = ATC_SCSIZE(sconfig->src_maxburst)
1100 | ATC_DCSIZE(sconfig->dst_maxburst);
Nicolas Ferreae14d4b2011-04-30 16:57:49 +02001101 ctrlb = ATC_IEN;
Nicolas Ferre808347f2009-07-22 20:04:45 +02001102
1103 switch (direction) {
Vinod Kouldb8196d2011-10-13 22:34:23 +05301104 case DMA_MEM_TO_DEV:
Nicolas Ferrebeeaa102012-03-14 12:41:43 +01001105 reg_width = convert_buswidth(sconfig->dst_addr_width);
Nicolas Ferre808347f2009-07-22 20:04:45 +02001106 ctrla |= ATC_DST_WIDTH(reg_width);
1107 ctrlb |= ATC_DST_ADDR_MODE_FIXED
1108 | ATC_SRC_ADDR_MODE_INCR
Nicolas Ferreae14d4b2011-04-30 16:57:49 +02001109 | ATC_FC_MEM2PER
Ludovic Desrochesbbe89c82013-04-19 09:11:18 +00001110 | ATC_SIF(atchan->mem_if) | ATC_DIF(atchan->per_if);
Nicolas Ferrebeeaa102012-03-14 12:41:43 +01001111 reg = sconfig->dst_addr;
Nicolas Ferre808347f2009-07-22 20:04:45 +02001112 for_each_sg(sgl, sg, sg_len, i) {
1113 struct at_desc *desc;
1114 u32 len;
1115 u32 mem;
1116
1117 desc = atc_desc_get(atchan);
1118 if (!desc)
1119 goto err_desc_get;
1120
Nicolas Ferre0f70e8c2010-12-15 18:50:16 +01001121 mem = sg_dma_address(sg);
Nicolas Ferre808347f2009-07-22 20:04:45 +02001122 len = sg_dma_len(sg);
Nicolas Ferrec4567972012-09-11 17:21:45 +02001123 if (unlikely(!len)) {
1124 dev_dbg(chan2dev(chan),
1125 "prep_slave_sg: sg(%d) data length is zero\n", i);
1126 goto err;
1127 }
Nicolas Ferre808347f2009-07-22 20:04:45 +02001128 mem_width = 2;
1129 if (unlikely(mem & 3 || len & 3))
1130 mem_width = 0;
1131
1132 desc->lli.saddr = mem;
1133 desc->lli.daddr = reg;
1134 desc->lli.ctrla = ctrla
1135 | ATC_SRC_WIDTH(mem_width)
1136 | len >> mem_width;
1137 desc->lli.ctrlb = ctrlb;
Torsten Fleischerbdf6c792015-02-23 17:54:10 +01001138 desc->len = len;
Nicolas Ferre808347f2009-07-22 20:04:45 +02001139
Nicolas Ferree257e152011-05-06 19:56:53 +02001140 atc_desc_chain(&first, &prev, desc);
Nicolas Ferre808347f2009-07-22 20:04:45 +02001141 total_len += len;
1142 }
1143 break;
Vinod Kouldb8196d2011-10-13 22:34:23 +05301144 case DMA_DEV_TO_MEM:
Nicolas Ferrebeeaa102012-03-14 12:41:43 +01001145 reg_width = convert_buswidth(sconfig->src_addr_width);
Nicolas Ferre808347f2009-07-22 20:04:45 +02001146 ctrla |= ATC_SRC_WIDTH(reg_width);
1147 ctrlb |= ATC_DST_ADDR_MODE_INCR
1148 | ATC_SRC_ADDR_MODE_FIXED
Nicolas Ferreae14d4b2011-04-30 16:57:49 +02001149 | ATC_FC_PER2MEM
Ludovic Desrochesbbe89c82013-04-19 09:11:18 +00001150 | ATC_SIF(atchan->per_if) | ATC_DIF(atchan->mem_if);
Nicolas Ferre808347f2009-07-22 20:04:45 +02001151
Nicolas Ferrebeeaa102012-03-14 12:41:43 +01001152 reg = sconfig->src_addr;
Nicolas Ferre808347f2009-07-22 20:04:45 +02001153 for_each_sg(sgl, sg, sg_len, i) {
1154 struct at_desc *desc;
1155 u32 len;
1156 u32 mem;
1157
1158 desc = atc_desc_get(atchan);
1159 if (!desc)
1160 goto err_desc_get;
1161
Nicolas Ferre0f70e8c2010-12-15 18:50:16 +01001162 mem = sg_dma_address(sg);
Nicolas Ferre808347f2009-07-22 20:04:45 +02001163 len = sg_dma_len(sg);
Nicolas Ferrec4567972012-09-11 17:21:45 +02001164 if (unlikely(!len)) {
1165 dev_dbg(chan2dev(chan),
1166 "prep_slave_sg: sg(%d) data length is zero\n", i);
1167 goto err;
1168 }
Nicolas Ferre808347f2009-07-22 20:04:45 +02001169 mem_width = 2;
1170 if (unlikely(mem & 3 || len & 3))
1171 mem_width = 0;
1172
1173 desc->lli.saddr = reg;
1174 desc->lli.daddr = mem;
1175 desc->lli.ctrla = ctrla
1176 | ATC_DST_WIDTH(mem_width)
Nicolas Ferre59a609d2010-12-13 13:48:41 +01001177 | len >> reg_width;
Nicolas Ferre808347f2009-07-22 20:04:45 +02001178 desc->lli.ctrlb = ctrlb;
Torsten Fleischerbdf6c792015-02-23 17:54:10 +01001179 desc->len = len;
Nicolas Ferre808347f2009-07-22 20:04:45 +02001180
Nicolas Ferree257e152011-05-06 19:56:53 +02001181 atc_desc_chain(&first, &prev, desc);
Nicolas Ferre808347f2009-07-22 20:04:45 +02001182 total_len += len;
1183 }
1184 break;
1185 default:
1186 return NULL;
1187 }
1188
1189 /* set end-of-link to the last link descriptor of list*/
1190 set_desc_eol(prev);
1191
1192 /* First descriptor of the chain embedds additional information */
1193 first->txd.cookie = -EBUSY;
Torsten Fleischerbdf6c792015-02-23 17:54:10 +01001194 first->total_len = total_len;
1195
Nicolas Ferre568f7f02011-01-12 15:39:09 +01001196 /* first link descriptor of list is responsible of flags */
1197 first->txd.flags = flags; /* client is in control of this ack */
Nicolas Ferre808347f2009-07-22 20:04:45 +02001198
1199 return &first->txd;
1200
1201err_desc_get:
1202 dev_err(chan2dev(chan), "not enough descriptors available\n");
Nicolas Ferrec4567972012-09-11 17:21:45 +02001203err:
Nicolas Ferre808347f2009-07-22 20:04:45 +02001204 atc_desc_put(atchan, first);
1205 return NULL;
1206}
1207
Nicolas Ferre53830cc2011-04-30 16:57:46 +02001208/**
Torsten Fleischer265567f2015-02-23 17:54:11 +01001209 * atc_prep_dma_sg - prepare memory to memory scather-gather operation
1210 * @chan: the channel to prepare operation on
1211 * @dst_sg: destination scatterlist
1212 * @dst_nents: number of destination scatterlist entries
1213 * @src_sg: source scatterlist
1214 * @src_nents: number of source scatterlist entries
1215 * @flags: tx descriptor status flags
1216 */
1217static struct dma_async_tx_descriptor *
1218atc_prep_dma_sg(struct dma_chan *chan,
1219 struct scatterlist *dst_sg, unsigned int dst_nents,
1220 struct scatterlist *src_sg, unsigned int src_nents,
1221 unsigned long flags)
1222{
1223 struct at_dma_chan *atchan = to_at_dma_chan(chan);
1224 struct at_desc *desc = NULL;
1225 struct at_desc *first = NULL;
1226 struct at_desc *prev = NULL;
1227 unsigned int src_width;
1228 unsigned int dst_width;
1229 size_t xfer_count;
1230 u32 ctrla;
1231 u32 ctrlb;
1232 size_t dst_len = 0, src_len = 0;
1233 dma_addr_t dst = 0, src = 0;
1234 size_t len = 0, total_len = 0;
1235
1236 if (unlikely(dst_nents == 0 || src_nents == 0))
1237 return NULL;
1238
1239 if (unlikely(dst_sg == NULL || src_sg == NULL))
1240 return NULL;
1241
1242 ctrlb = ATC_DEFAULT_CTRLB | ATC_IEN
1243 | ATC_SRC_ADDR_MODE_INCR
1244 | ATC_DST_ADDR_MODE_INCR
1245 | ATC_FC_MEM2MEM;
1246
1247 /*
1248 * loop until there is either no more source or no more destination
1249 * scatterlist entry
1250 */
1251 while (true) {
1252
1253 /* prepare the next transfer */
1254 if (dst_len == 0) {
1255
1256 /* no more destination scatterlist entries */
1257 if (!dst_sg || !dst_nents)
1258 break;
1259
1260 dst = sg_dma_address(dst_sg);
1261 dst_len = sg_dma_len(dst_sg);
1262
1263 dst_sg = sg_next(dst_sg);
1264 dst_nents--;
1265 }
1266
1267 if (src_len == 0) {
1268
1269 /* no more source scatterlist entries */
1270 if (!src_sg || !src_nents)
1271 break;
1272
1273 src = sg_dma_address(src_sg);
1274 src_len = sg_dma_len(src_sg);
1275
1276 src_sg = sg_next(src_sg);
1277 src_nents--;
1278 }
1279
1280 len = min_t(size_t, src_len, dst_len);
1281 if (len == 0)
1282 continue;
1283
1284 /* take care for the alignment */
1285 src_width = dst_width = atc_get_xfer_width(src, dst, len);
1286
1287 ctrla = ATC_SRC_WIDTH(src_width) |
1288 ATC_DST_WIDTH(dst_width);
1289
1290 /*
1291 * The number of transfers to set up refer to the source width
1292 * that depends on the alignment.
1293 */
1294 xfer_count = len >> src_width;
1295 if (xfer_count > ATC_BTSIZE_MAX) {
1296 xfer_count = ATC_BTSIZE_MAX;
1297 len = ATC_BTSIZE_MAX << src_width;
1298 }
1299
1300 /* create the transfer */
1301 desc = atc_desc_get(atchan);
1302 if (!desc)
1303 goto err_desc_get;
1304
1305 desc->lli.saddr = src;
1306 desc->lli.daddr = dst;
1307 desc->lli.ctrla = ctrla | xfer_count;
1308 desc->lli.ctrlb = ctrlb;
1309
1310 desc->txd.cookie = 0;
1311 desc->len = len;
1312
Torsten Fleischer265567f2015-02-23 17:54:11 +01001313 atc_desc_chain(&first, &prev, desc);
1314
1315 /* update the lengths and addresses for the next loop cycle */
1316 dst_len -= len;
1317 src_len -= len;
1318 dst += len;
1319 src += len;
1320
1321 total_len += len;
1322 }
1323
1324 /* First descriptor of the chain embedds additional information */
1325 first->txd.cookie = -EBUSY;
1326 first->total_len = total_len;
1327
1328 /* set end-of-link to the last link descriptor of list*/
1329 set_desc_eol(desc);
1330
1331 first->txd.flags = flags; /* client is in control of this ack */
1332
1333 return &first->txd;
1334
1335err_desc_get:
1336 atc_desc_put(atchan, first);
1337 return NULL;
1338}
1339
1340/**
Nicolas Ferre53830cc2011-04-30 16:57:46 +02001341 * atc_dma_cyclic_check_values
1342 * Check for too big/unaligned periods and unaligned DMA buffer
1343 */
1344static int
1345atc_dma_cyclic_check_values(unsigned int reg_width, dma_addr_t buf_addr,
Andy Shevchenko0e7264c2013-01-10 10:52:57 +02001346 size_t period_len)
Nicolas Ferre53830cc2011-04-30 16:57:46 +02001347{
1348 if (period_len > (ATC_BTSIZE_MAX << reg_width))
1349 goto err_out;
1350 if (unlikely(period_len & ((1 << reg_width) - 1)))
1351 goto err_out;
1352 if (unlikely(buf_addr & ((1 << reg_width) - 1)))
1353 goto err_out;
Nicolas Ferre53830cc2011-04-30 16:57:46 +02001354
1355 return 0;
1356
1357err_out:
1358 return -EINVAL;
1359}
1360
1361/**
Masanari Iidad73111c2012-08-04 23:37:53 +09001362 * atc_dma_cyclic_fill_desc - Fill one period descriptor
Nicolas Ferre53830cc2011-04-30 16:57:46 +02001363 */
1364static int
Nicolas Ferrebeeaa102012-03-14 12:41:43 +01001365atc_dma_cyclic_fill_desc(struct dma_chan *chan, struct at_desc *desc,
Nicolas Ferre53830cc2011-04-30 16:57:46 +02001366 unsigned int period_index, dma_addr_t buf_addr,
Nicolas Ferrebeeaa102012-03-14 12:41:43 +01001367 unsigned int reg_width, size_t period_len,
1368 enum dma_transfer_direction direction)
Nicolas Ferre53830cc2011-04-30 16:57:46 +02001369{
Nicolas Ferrebeeaa102012-03-14 12:41:43 +01001370 struct at_dma_chan *atchan = to_at_dma_chan(chan);
Nicolas Ferrebeeaa102012-03-14 12:41:43 +01001371 struct dma_slave_config *sconfig = &atchan->dma_sconfig;
1372 u32 ctrla;
Nicolas Ferre53830cc2011-04-30 16:57:46 +02001373
1374 /* prepare common CRTLA value */
Nicolas Ferre1dd1ea82012-05-10 12:17:41 +02001375 ctrla = ATC_SCSIZE(sconfig->src_maxburst)
1376 | ATC_DCSIZE(sconfig->dst_maxburst)
Nicolas Ferre53830cc2011-04-30 16:57:46 +02001377 | ATC_DST_WIDTH(reg_width)
1378 | ATC_SRC_WIDTH(reg_width)
1379 | period_len >> reg_width;
1380
1381 switch (direction) {
Vinod Kouldb8196d2011-10-13 22:34:23 +05301382 case DMA_MEM_TO_DEV:
Nicolas Ferre53830cc2011-04-30 16:57:46 +02001383 desc->lli.saddr = buf_addr + (period_len * period_index);
Nicolas Ferrebeeaa102012-03-14 12:41:43 +01001384 desc->lli.daddr = sconfig->dst_addr;
Nicolas Ferre53830cc2011-04-30 16:57:46 +02001385 desc->lli.ctrla = ctrla;
Nicolas Ferreae14d4b2011-04-30 16:57:49 +02001386 desc->lli.ctrlb = ATC_DST_ADDR_MODE_FIXED
Nicolas Ferre53830cc2011-04-30 16:57:46 +02001387 | ATC_SRC_ADDR_MODE_INCR
Nicolas Ferreae14d4b2011-04-30 16:57:49 +02001388 | ATC_FC_MEM2PER
Ludovic Desrochesbbe89c82013-04-19 09:11:18 +00001389 | ATC_SIF(atchan->mem_if)
1390 | ATC_DIF(atchan->per_if);
Torsten Fleischerbdf6c792015-02-23 17:54:10 +01001391 desc->len = period_len;
Nicolas Ferre53830cc2011-04-30 16:57:46 +02001392 break;
1393
Vinod Kouldb8196d2011-10-13 22:34:23 +05301394 case DMA_DEV_TO_MEM:
Nicolas Ferrebeeaa102012-03-14 12:41:43 +01001395 desc->lli.saddr = sconfig->src_addr;
Nicolas Ferre53830cc2011-04-30 16:57:46 +02001396 desc->lli.daddr = buf_addr + (period_len * period_index);
1397 desc->lli.ctrla = ctrla;
Nicolas Ferreae14d4b2011-04-30 16:57:49 +02001398 desc->lli.ctrlb = ATC_DST_ADDR_MODE_INCR
Nicolas Ferre53830cc2011-04-30 16:57:46 +02001399 | ATC_SRC_ADDR_MODE_FIXED
Nicolas Ferreae14d4b2011-04-30 16:57:49 +02001400 | ATC_FC_PER2MEM
Ludovic Desrochesbbe89c82013-04-19 09:11:18 +00001401 | ATC_SIF(atchan->per_if)
1402 | ATC_DIF(atchan->mem_if);
Torsten Fleischerbdf6c792015-02-23 17:54:10 +01001403 desc->len = period_len;
Nicolas Ferre53830cc2011-04-30 16:57:46 +02001404 break;
1405
1406 default:
1407 return -EINVAL;
1408 }
1409
1410 return 0;
1411}
1412
1413/**
1414 * atc_prep_dma_cyclic - prepare the cyclic DMA transfer
1415 * @chan: the DMA channel to prepare
1416 * @buf_addr: physical DMA address where the buffer starts
1417 * @buf_len: total number of bytes for the entire buffer
1418 * @period_len: number of bytes for each period
1419 * @direction: transfer direction, to or from device
Peter Ujfalusiec8b5e42012-09-14 15:05:47 +03001420 * @flags: tx descriptor status flags
Nicolas Ferre53830cc2011-04-30 16:57:46 +02001421 */
1422static struct dma_async_tx_descriptor *
1423atc_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
Alexandre Bounine185ecb52012-03-08 15:35:13 -05001424 size_t period_len, enum dma_transfer_direction direction,
Laurent Pinchart31c1e5a2014-08-01 12:20:10 +02001425 unsigned long flags)
Nicolas Ferre53830cc2011-04-30 16:57:46 +02001426{
1427 struct at_dma_chan *atchan = to_at_dma_chan(chan);
1428 struct at_dma_slave *atslave = chan->private;
Nicolas Ferrebeeaa102012-03-14 12:41:43 +01001429 struct dma_slave_config *sconfig = &atchan->dma_sconfig;
Nicolas Ferre53830cc2011-04-30 16:57:46 +02001430 struct at_desc *first = NULL;
1431 struct at_desc *prev = NULL;
1432 unsigned long was_cyclic;
Nicolas Ferrebeeaa102012-03-14 12:41:43 +01001433 unsigned int reg_width;
Nicolas Ferre53830cc2011-04-30 16:57:46 +02001434 unsigned int periods = buf_len / period_len;
1435 unsigned int i;
1436
Arnd Bergmann2c5d7402015-11-12 15:18:22 +01001437 dev_vdbg(chan2dev(chan), "prep_dma_cyclic: %s buf@%pad - %d (%d/%d)\n",
Vinod Kouldb8196d2011-10-13 22:34:23 +05301438 direction == DMA_MEM_TO_DEV ? "TO DEVICE" : "FROM DEVICE",
Arnd Bergmann2c5d7402015-11-12 15:18:22 +01001439 &buf_addr,
Nicolas Ferre53830cc2011-04-30 16:57:46 +02001440 periods, buf_len, period_len);
1441
1442 if (unlikely(!atslave || !buf_len || !period_len)) {
1443 dev_dbg(chan2dev(chan), "prep_dma_cyclic: length is zero!\n");
1444 return NULL;
1445 }
1446
1447 was_cyclic = test_and_set_bit(ATC_IS_CYCLIC, &atchan->status);
1448 if (was_cyclic) {
1449 dev_dbg(chan2dev(chan), "prep_dma_cyclic: channel in use!\n");
1450 return NULL;
1451 }
1452
Andy Shevchenko0e7264c2013-01-10 10:52:57 +02001453 if (unlikely(!is_slave_direction(direction)))
1454 goto err_out;
1455
Nicolas Ferrebeeaa102012-03-14 12:41:43 +01001456 if (sconfig->direction == DMA_MEM_TO_DEV)
1457 reg_width = convert_buswidth(sconfig->dst_addr_width);
1458 else
1459 reg_width = convert_buswidth(sconfig->src_addr_width);
1460
Nicolas Ferre53830cc2011-04-30 16:57:46 +02001461 /* Check for too big/unaligned periods and unaligned DMA buffer */
Andy Shevchenko0e7264c2013-01-10 10:52:57 +02001462 if (atc_dma_cyclic_check_values(reg_width, buf_addr, period_len))
Nicolas Ferre53830cc2011-04-30 16:57:46 +02001463 goto err_out;
1464
1465 /* build cyclic linked list */
1466 for (i = 0; i < periods; i++) {
1467 struct at_desc *desc;
1468
1469 desc = atc_desc_get(atchan);
1470 if (!desc)
1471 goto err_desc_get;
1472
Nicolas Ferrebeeaa102012-03-14 12:41:43 +01001473 if (atc_dma_cyclic_fill_desc(chan, desc, i, buf_addr,
1474 reg_width, period_len, direction))
Nicolas Ferre53830cc2011-04-30 16:57:46 +02001475 goto err_desc_get;
1476
1477 atc_desc_chain(&first, &prev, desc);
1478 }
1479
1480 /* lets make a cyclic list */
1481 prev->lli.dscr = first->txd.phys;
1482
1483 /* First descriptor of the chain embedds additional information */
1484 first->txd.cookie = -EBUSY;
Torsten Fleischerbdf6c792015-02-23 17:54:10 +01001485 first->total_len = buf_len;
Nicolas Ferre53830cc2011-04-30 16:57:46 +02001486
1487 return &first->txd;
1488
1489err_desc_get:
1490 dev_err(chan2dev(chan), "not enough descriptors available\n");
1491 atc_desc_put(atchan, first);
1492err_out:
1493 clear_bit(ATC_IS_CYCLIC, &atchan->status);
1494 return NULL;
1495}
1496
Maxime Ripard4facfe72014-11-17 14:42:06 +01001497static int atc_config(struct dma_chan *chan,
1498 struct dma_slave_config *sconfig)
Nicolas Ferrebeeaa102012-03-14 12:41:43 +01001499{
1500 struct at_dma_chan *atchan = to_at_dma_chan(chan);
1501
Maxime Ripard4facfe72014-11-17 14:42:06 +01001502 dev_vdbg(chan2dev(chan), "%s\n", __func__);
1503
Nicolas Ferrebeeaa102012-03-14 12:41:43 +01001504 /* Check if it is chan is configured for slave transfers */
1505 if (!chan->private)
1506 return -EINVAL;
1507
1508 memcpy(&atchan->dma_sconfig, sconfig, sizeof(*sconfig));
1509
1510 convert_burst(&atchan->dma_sconfig.src_maxburst);
1511 convert_burst(&atchan->dma_sconfig.dst_maxburst);
1512
1513 return 0;
1514}
1515
Maxime Ripard4facfe72014-11-17 14:42:06 +01001516static int atc_pause(struct dma_chan *chan)
Nicolas Ferre808347f2009-07-22 20:04:45 +02001517{
1518 struct at_dma_chan *atchan = to_at_dma_chan(chan);
1519 struct at_dma *atdma = to_at_dma(chan->device);
Nicolas Ferre23b5e3a2011-05-06 19:56:52 +02001520 int chan_id = atchan->chan_common.chan_id;
Nicolas Ferred8cb04b2011-07-27 12:21:28 +00001521 unsigned long flags;
Nicolas Ferre23b5e3a2011-05-06 19:56:52 +02001522
Nicolas Ferre808347f2009-07-22 20:04:45 +02001523 LIST_HEAD(list);
1524
Maxime Ripard4facfe72014-11-17 14:42:06 +01001525 dev_vdbg(chan2dev(chan), "%s\n", __func__);
Nicolas Ferre23b5e3a2011-05-06 19:56:52 +02001526
Maxime Ripard4facfe72014-11-17 14:42:06 +01001527 spin_lock_irqsave(&atchan->lock, flags);
Nicolas Ferre23b5e3a2011-05-06 19:56:52 +02001528
Maxime Ripard4facfe72014-11-17 14:42:06 +01001529 dma_writel(atdma, CHER, AT_DMA_SUSP(chan_id));
1530 set_bit(ATC_IS_PAUSED, &atchan->status);
Nicolas Ferre23b5e3a2011-05-06 19:56:52 +02001531
Maxime Ripard4facfe72014-11-17 14:42:06 +01001532 spin_unlock_irqrestore(&atchan->lock, flags);
Nicolas Ferre23b5e3a2011-05-06 19:56:52 +02001533
Maxime Ripard4facfe72014-11-17 14:42:06 +01001534 return 0;
1535}
Nicolas Ferre23b5e3a2011-05-06 19:56:52 +02001536
Maxime Ripard4facfe72014-11-17 14:42:06 +01001537static int atc_resume(struct dma_chan *chan)
1538{
1539 struct at_dma_chan *atchan = to_at_dma_chan(chan);
1540 struct at_dma *atdma = to_at_dma(chan->device);
1541 int chan_id = atchan->chan_common.chan_id;
1542 unsigned long flags;
Nicolas Ferre23b5e3a2011-05-06 19:56:52 +02001543
Maxime Ripard4facfe72014-11-17 14:42:06 +01001544 LIST_HEAD(list);
Nicolas Ferre23b5e3a2011-05-06 19:56:52 +02001545
Maxime Ripard4facfe72014-11-17 14:42:06 +01001546 dev_vdbg(chan2dev(chan), "%s\n", __func__);
Nicolas Ferre23b5e3a2011-05-06 19:56:52 +02001547
Maxime Ripard4facfe72014-11-17 14:42:06 +01001548 if (!atc_chan_is_paused(atchan))
1549 return 0;
Nicolas Ferre23b5e3a2011-05-06 19:56:52 +02001550
Maxime Ripard4facfe72014-11-17 14:42:06 +01001551 spin_lock_irqsave(&atchan->lock, flags);
Nicolas Ferre23b5e3a2011-05-06 19:56:52 +02001552
Maxime Ripard4facfe72014-11-17 14:42:06 +01001553 dma_writel(atdma, CHDR, AT_DMA_RES(chan_id));
1554 clear_bit(ATC_IS_PAUSED, &atchan->status);
Nicolas Ferre23b5e3a2011-05-06 19:56:52 +02001555
Maxime Ripard4facfe72014-11-17 14:42:06 +01001556 spin_unlock_irqrestore(&atchan->lock, flags);
Nicolas Ferre23b5e3a2011-05-06 19:56:52 +02001557
Maxime Ripard4facfe72014-11-17 14:42:06 +01001558 return 0;
1559}
1560
1561static int atc_terminate_all(struct dma_chan *chan)
1562{
1563 struct at_dma_chan *atchan = to_at_dma_chan(chan);
1564 struct at_dma *atdma = to_at_dma(chan->device);
1565 int chan_id = atchan->chan_common.chan_id;
1566 struct at_desc *desc, *_desc;
1567 unsigned long flags;
1568
1569 LIST_HEAD(list);
1570
1571 dev_vdbg(chan2dev(chan), "%s\n", __func__);
1572
1573 /*
1574 * This is only called when something went wrong elsewhere, so
1575 * we don't really care about the data. Just disable the
1576 * channel. We still have to poll the channel enable bit due
1577 * to AHB/HSB limitations.
1578 */
1579 spin_lock_irqsave(&atchan->lock, flags);
1580
1581 /* disabling channel: must also remove suspend state */
1582 dma_writel(atdma, CHDR, AT_DMA_RES(chan_id) | atchan->mask);
1583
1584 /* confirm that this channel is disabled */
1585 while (dma_readl(atdma, CHSR) & atchan->mask)
1586 cpu_relax();
1587
1588 /* active_list entries will end up before queued entries */
1589 list_splice_init(&atchan->queue, &list);
1590 list_splice_init(&atchan->active_list, &list);
1591
1592 /* Flush all pending and queued descriptors */
1593 list_for_each_entry_safe(desc, _desc, &list, desc_node)
1594 atc_chain_complete(atchan, desc);
1595
1596 clear_bit(ATC_IS_PAUSED, &atchan->status);
1597 /* if channel dedicated to cyclic operations, free it */
1598 clear_bit(ATC_IS_CYCLIC, &atchan->status);
1599
1600 spin_unlock_irqrestore(&atchan->lock, flags);
Yong Wangb0ebeb92010-08-05 10:40:08 +08001601
Linus Walleijc3635c72010-03-26 16:44:01 -07001602 return 0;
Nicolas Ferre808347f2009-07-22 20:04:45 +02001603}
1604
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001605/**
Linus Walleij07934482010-03-26 16:50:49 -07001606 * atc_tx_status - poll for transaction completion
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001607 * @chan: DMA channel
1608 * @cookie: transaction identifier to check status of
Linus Walleij07934482010-03-26 16:50:49 -07001609 * @txstate: if not %NULL updated with transaction state
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001610 *
Linus Walleij07934482010-03-26 16:50:49 -07001611 * If @txstate is passed in, upon return it reflect the driver
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001612 * internal state and can be used with dma_async_is_complete() to check
1613 * the status of multiple cookies without re-checking hardware state.
1614 */
1615static enum dma_status
Linus Walleij07934482010-03-26 16:50:49 -07001616atc_tx_status(struct dma_chan *chan,
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001617 dma_cookie_t cookie,
Linus Walleij07934482010-03-26 16:50:49 -07001618 struct dma_tx_state *txstate)
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001619{
1620 struct at_dma_chan *atchan = to_at_dma_chan(chan);
Nicolas Ferred8cb04b2011-07-27 12:21:28 +00001621 unsigned long flags;
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001622 enum dma_status ret;
Elen Songd48de6f2013-05-10 11:01:46 +08001623 int bytes = 0;
1624
1625 ret = dma_cookie_status(chan, cookie, txstate);
Vinod Koul6d203d12013-10-16 13:34:35 +05301626 if (ret == DMA_COMPLETE)
Elen Songd48de6f2013-05-10 11:01:46 +08001627 return ret;
1628 /*
1629 * There's no point calculating the residue if there's
1630 * no txstate to store the value.
1631 */
1632 if (!txstate)
1633 return DMA_ERROR;
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001634
Nicolas Ferred8cb04b2011-07-27 12:21:28 +00001635 spin_lock_irqsave(&atchan->lock, flags);
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001636
Elen Songd48de6f2013-05-10 11:01:46 +08001637 /* Get number of bytes left in the active transactions */
Torsten Fleischerbdf6c792015-02-23 17:54:10 +01001638 bytes = atc_get_bytes_left(chan, cookie);
Russell King - ARM Linux96a2af42012-03-06 22:35:27 +00001639
Nicolas Ferred8cb04b2011-07-27 12:21:28 +00001640 spin_unlock_irqrestore(&atchan->lock, flags);
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001641
Elen Songd48de6f2013-05-10 11:01:46 +08001642 if (unlikely(bytes < 0)) {
1643 dev_vdbg(chan2dev(chan), "get residual bytes error\n");
1644 return DMA_ERROR;
Nicolas Ferrec3dbc602013-06-07 17:26:14 +02001645 } else {
Elen Songd48de6f2013-05-10 11:01:46 +08001646 dma_set_residue(txstate, bytes);
Nicolas Ferrec3dbc602013-06-07 17:26:14 +02001647 }
Nicolas Ferre543aabc2011-05-06 19:56:51 +02001648
Elen Songd48de6f2013-05-10 11:01:46 +08001649 dev_vdbg(chan2dev(chan), "tx_status %d: cookie = %d residue = %d\n",
1650 ret, cookie, bytes);
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001651
1652 return ret;
1653}
1654
1655/**
1656 * atc_issue_pending - try to finish work
1657 * @chan: target DMA channel
1658 */
1659static void atc_issue_pending(struct dma_chan *chan)
1660{
1661 struct at_dma_chan *atchan = to_at_dma_chan(chan);
Nicolas Ferred8cb04b2011-07-27 12:21:28 +00001662 unsigned long flags;
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001663
1664 dev_vdbg(chan2dev(chan), "issue_pending\n");
1665
Nicolas Ferre53830cc2011-04-30 16:57:46 +02001666 /* Not needed for cyclic transfers */
Nicolas Ferre3c477482011-07-25 21:09:23 +00001667 if (atc_chan_is_cyclic(atchan))
Nicolas Ferre53830cc2011-04-30 16:57:46 +02001668 return;
1669
Nicolas Ferred8cb04b2011-07-27 12:21:28 +00001670 spin_lock_irqsave(&atchan->lock, flags);
Ludovic Desrochesd202f052013-04-18 09:52:59 +02001671 atc_advance_work(atchan);
Nicolas Ferred8cb04b2011-07-27 12:21:28 +00001672 spin_unlock_irqrestore(&atchan->lock, flags);
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001673}
1674
1675/**
1676 * atc_alloc_chan_resources - allocate resources for DMA channel
1677 * @chan: allocate descriptor resources for this channel
1678 * @client: current client requesting the channel be ready for requests
1679 *
1680 * return - the number of allocated descriptors
1681 */
1682static int atc_alloc_chan_resources(struct dma_chan *chan)
1683{
1684 struct at_dma_chan *atchan = to_at_dma_chan(chan);
1685 struct at_dma *atdma = to_at_dma(chan->device);
1686 struct at_desc *desc;
Nicolas Ferre808347f2009-07-22 20:04:45 +02001687 struct at_dma_slave *atslave;
Nicolas Ferred8cb04b2011-07-27 12:21:28 +00001688 unsigned long flags;
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001689 int i;
Nicolas Ferre808347f2009-07-22 20:04:45 +02001690 u32 cfg;
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001691 LIST_HEAD(tmp_list);
1692
1693 dev_vdbg(chan2dev(chan), "alloc_chan_resources\n");
1694
1695 /* ASSERT: channel is idle */
1696 if (atc_chan_is_enabled(atchan)) {
1697 dev_dbg(chan2dev(chan), "DMA channel not idle ?\n");
1698 return -EIO;
1699 }
1700
Nicolas Ferre808347f2009-07-22 20:04:45 +02001701 cfg = ATC_DEFAULT_CFG;
1702
1703 atslave = chan->private;
1704 if (atslave) {
1705 /*
1706 * We need controller-specific data to set up slave
1707 * transfers.
1708 */
1709 BUG_ON(!atslave->dma_dev || atslave->dma_dev != atdma->dma_common.dev);
1710
Nicolas Ferreea7e7902013-05-10 15:19:13 +02001711 /* if cfg configuration specified take it instead of default */
Nicolas Ferre808347f2009-07-22 20:04:45 +02001712 if (atslave->cfg)
1713 cfg = atslave->cfg;
1714 }
1715
1716 /* have we already been set up?
1717 * reconfigure channel but no need to reallocate descriptors */
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001718 if (!list_empty(&atchan->free_list))
1719 return atchan->descs_allocated;
1720
1721 /* Allocate initial pool of descriptors */
1722 for (i = 0; i < init_nr_desc_per_channel; i++) {
1723 desc = atc_alloc_descriptor(chan, GFP_KERNEL);
1724 if (!desc) {
1725 dev_err(atdma->dma_common.dev,
1726 "Only %d initial descriptors\n", i);
1727 break;
1728 }
1729 list_add_tail(&desc->desc_node, &tmp_list);
1730 }
1731
Nicolas Ferred8cb04b2011-07-27 12:21:28 +00001732 spin_lock_irqsave(&atchan->lock, flags);
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001733 atchan->descs_allocated = i;
1734 list_splice(&tmp_list, &atchan->free_list);
Russell King - ARM Linuxd3ee98cdc2012-03-06 22:35:47 +00001735 dma_cookie_init(chan);
Nicolas Ferred8cb04b2011-07-27 12:21:28 +00001736 spin_unlock_irqrestore(&atchan->lock, flags);
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001737
1738 /* channel parameters */
Nicolas Ferre808347f2009-07-22 20:04:45 +02001739 channel_writel(atchan, CFG, cfg);
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001740
1741 dev_dbg(chan2dev(chan),
1742 "alloc_chan_resources: allocated %d descriptors\n",
1743 atchan->descs_allocated);
1744
1745 return atchan->descs_allocated;
1746}
1747
1748/**
1749 * atc_free_chan_resources - free all channel resources
1750 * @chan: DMA channel
1751 */
1752static void atc_free_chan_resources(struct dma_chan *chan)
1753{
1754 struct at_dma_chan *atchan = to_at_dma_chan(chan);
1755 struct at_dma *atdma = to_at_dma(chan->device);
1756 struct at_desc *desc, *_desc;
1757 LIST_HEAD(list);
1758
1759 dev_dbg(chan2dev(chan), "free_chan_resources: (descs allocated=%u)\n",
1760 atchan->descs_allocated);
1761
1762 /* ASSERT: channel is idle */
1763 BUG_ON(!list_empty(&atchan->active_list));
1764 BUG_ON(!list_empty(&atchan->queue));
1765 BUG_ON(atc_chan_is_enabled(atchan));
1766
1767 list_for_each_entry_safe(desc, _desc, &atchan->free_list, desc_node) {
1768 dev_vdbg(chan2dev(chan), " freeing descriptor %p\n", desc);
1769 list_del(&desc->desc_node);
1770 /* free link descriptor */
1771 dma_pool_free(atdma->dma_desc_pool, desc, desc->txd.phys);
1772 }
1773 list_splice_init(&atchan->free_list, &list);
1774 atchan->descs_allocated = 0;
Nicolas Ferre53830cc2011-04-30 16:57:46 +02001775 atchan->status = 0;
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001776
1777 dev_vdbg(chan2dev(chan), "free_chan_resources: done\n");
1778}
1779
Ludovic Desrochesbbe89c82013-04-19 09:11:18 +00001780#ifdef CONFIG_OF
1781static bool at_dma_filter(struct dma_chan *chan, void *slave)
1782{
1783 struct at_dma_slave *atslave = slave;
1784
1785 if (atslave->dma_dev == chan->device->dev) {
1786 chan->private = atslave;
1787 return true;
1788 } else {
1789 return false;
1790 }
1791}
1792
1793static struct dma_chan *at_dma_xlate(struct of_phandle_args *dma_spec,
1794 struct of_dma *of_dma)
1795{
1796 struct dma_chan *chan;
1797 struct at_dma_chan *atchan;
1798 struct at_dma_slave *atslave;
1799 dma_cap_mask_t mask;
1800 unsigned int per_id;
1801 struct platform_device *dmac_pdev;
1802
1803 if (dma_spec->args_count != 2)
1804 return NULL;
1805
1806 dmac_pdev = of_find_device_by_node(dma_spec->np);
1807
1808 dma_cap_zero(mask);
1809 dma_cap_set(DMA_SLAVE, mask);
1810
1811 atslave = devm_kzalloc(&dmac_pdev->dev, sizeof(*atslave), GFP_KERNEL);
1812 if (!atslave)
1813 return NULL;
Ludovic Desroches62971b22013-06-13 10:39:39 +02001814
1815 atslave->cfg = ATC_DST_H2SEL_HW | ATC_SRC_H2SEL_HW;
Ludovic Desrochesbbe89c82013-04-19 09:11:18 +00001816 /*
1817 * We can fill both SRC_PER and DST_PER, one of these fields will be
1818 * ignored depending on DMA transfer direction.
1819 */
Ludovic Desroches62971b22013-06-13 10:39:39 +02001820 per_id = dma_spec->args[1] & AT91_DMA_CFG_PER_ID_MASK;
1821 atslave->cfg |= ATC_DST_PER_MSB(per_id) | ATC_DST_PER(per_id)
Nicolas Ferre6c227702013-05-10 15:19:15 +02001822 | ATC_SRC_PER_MSB(per_id) | ATC_SRC_PER(per_id);
Ludovic Desroches62971b22013-06-13 10:39:39 +02001823 /*
1824 * We have to translate the value we get from the device tree since
1825 * the half FIFO configuration value had to be 0 to keep backward
1826 * compatibility.
1827 */
1828 switch (dma_spec->args[1] & AT91_DMA_CFG_FIFOCFG_MASK) {
1829 case AT91_DMA_CFG_FIFOCFG_ALAP:
1830 atslave->cfg |= ATC_FIFOCFG_LARGESTBURST;
1831 break;
1832 case AT91_DMA_CFG_FIFOCFG_ASAP:
1833 atslave->cfg |= ATC_FIFOCFG_ENOUGHSPACE;
1834 break;
1835 case AT91_DMA_CFG_FIFOCFG_HALF:
1836 default:
1837 atslave->cfg |= ATC_FIFOCFG_HALFFIFO;
1838 }
Ludovic Desrochesbbe89c82013-04-19 09:11:18 +00001839 atslave->dma_dev = &dmac_pdev->dev;
1840
1841 chan = dma_request_channel(mask, at_dma_filter, atslave);
1842 if (!chan)
1843 return NULL;
1844
1845 atchan = to_at_dma_chan(chan);
1846 atchan->per_if = dma_spec->args[0] & 0xff;
1847 atchan->mem_if = (dma_spec->args[0] >> 16) & 0xff;
1848
1849 return chan;
1850}
1851#else
1852static struct dma_chan *at_dma_xlate(struct of_phandle_args *dma_spec,
1853 struct of_dma *of_dma)
1854{
1855 return NULL;
1856}
1857#endif
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001858
1859/*-- Module Management -----------------------------------------------*/
1860
Nicolas Ferre02f88be2011-11-22 11:55:54 +01001861/* cap_mask is a multi-u32 bitfield, fill it with proper C code. */
1862static struct at_dma_platform_data at91sam9rl_config = {
1863 .nr_channels = 2,
1864};
1865static struct at_dma_platform_data at91sam9g45_config = {
1866 .nr_channels = 8,
1867};
1868
Nicolas Ferrec5115952011-10-17 14:56:41 +02001869#if defined(CONFIG_OF)
1870static const struct of_device_id atmel_dma_dt_ids[] = {
1871 {
1872 .compatible = "atmel,at91sam9rl-dma",
Nicolas Ferre02f88be2011-11-22 11:55:54 +01001873 .data = &at91sam9rl_config,
Nicolas Ferrec5115952011-10-17 14:56:41 +02001874 }, {
1875 .compatible = "atmel,at91sam9g45-dma",
Nicolas Ferre02f88be2011-11-22 11:55:54 +01001876 .data = &at91sam9g45_config,
Nicolas Ferredcc81732011-11-22 11:55:53 +01001877 }, {
1878 /* sentinel */
1879 }
Nicolas Ferrec5115952011-10-17 14:56:41 +02001880};
1881
1882MODULE_DEVICE_TABLE(of, atmel_dma_dt_ids);
1883#endif
1884
Nicolas Ferre0ab88a02011-11-22 11:55:52 +01001885static const struct platform_device_id atdma_devtypes[] = {
Nicolas Ferre67348452011-10-17 14:56:40 +02001886 {
1887 .name = "at91sam9rl_dma",
Nicolas Ferre02f88be2011-11-22 11:55:54 +01001888 .driver_data = (unsigned long) &at91sam9rl_config,
Nicolas Ferre67348452011-10-17 14:56:40 +02001889 }, {
1890 .name = "at91sam9g45_dma",
Nicolas Ferre02f88be2011-11-22 11:55:54 +01001891 .driver_data = (unsigned long) &at91sam9g45_config,
Nicolas Ferre67348452011-10-17 14:56:40 +02001892 }, {
1893 /* sentinel */
1894 }
1895};
1896
Uwe Kleine-König7fd63cc2012-07-13 14:32:10 +02001897static inline const struct at_dma_platform_data * __init at_dma_get_driver_data(
Nicolas Ferre02f88be2011-11-22 11:55:54 +01001898 struct platform_device *pdev)
Nicolas Ferrec5115952011-10-17 14:56:41 +02001899{
1900 if (pdev->dev.of_node) {
1901 const struct of_device_id *match;
1902 match = of_match_node(atmel_dma_dt_ids, pdev->dev.of_node);
1903 if (match == NULL)
Nicolas Ferre02f88be2011-11-22 11:55:54 +01001904 return NULL;
1905 return match->data;
Nicolas Ferrec5115952011-10-17 14:56:41 +02001906 }
Nicolas Ferre02f88be2011-11-22 11:55:54 +01001907 return (struct at_dma_platform_data *)
1908 platform_get_device_id(pdev)->driver_data;
Nicolas Ferrec5115952011-10-17 14:56:41 +02001909}
1910
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001911/**
1912 * at_dma_off - disable DMA controller
1913 * @atdma: the Atmel HDAMC device
1914 */
1915static void at_dma_off(struct at_dma *atdma)
1916{
1917 dma_writel(atdma, EN, 0);
1918
1919 /* disable all interrupts */
1920 dma_writel(atdma, EBCIDR, -1L);
1921
1922 /* confirm that all channels are disabled */
1923 while (dma_readl(atdma, CHSR) & atdma->all_chan_mask)
1924 cpu_relax();
1925}
1926
1927static int __init at_dma_probe(struct platform_device *pdev)
1928{
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001929 struct resource *io;
1930 struct at_dma *atdma;
1931 size_t size;
1932 int irq;
1933 int err;
1934 int i;
Uwe Kleine-König7fd63cc2012-07-13 14:32:10 +02001935 const struct at_dma_platform_data *plat_dat;
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001936
Nicolas Ferre02f88be2011-11-22 11:55:54 +01001937 /* setup platform data for each SoC */
1938 dma_cap_set(DMA_MEMCPY, at91sam9rl_config.cap_mask);
Torsten Fleischer265567f2015-02-23 17:54:11 +01001939 dma_cap_set(DMA_SG, at91sam9rl_config.cap_mask);
Maxime Ripard5abecfa2015-05-27 16:01:53 +02001940 dma_cap_set(DMA_INTERLEAVE, at91sam9g45_config.cap_mask);
Nicolas Ferre02f88be2011-11-22 11:55:54 +01001941 dma_cap_set(DMA_MEMCPY, at91sam9g45_config.cap_mask);
Maxime Ripard4d112422015-08-24 11:21:15 +02001942 dma_cap_set(DMA_MEMSET, at91sam9g45_config.cap_mask);
Maxime Ripard67d25f02015-10-22 11:41:00 +02001943 dma_cap_set(DMA_MEMSET_SG, at91sam9g45_config.cap_mask);
Maxime Ripard4d112422015-08-24 11:21:15 +02001944 dma_cap_set(DMA_PRIVATE, at91sam9g45_config.cap_mask);
Nicolas Ferre02f88be2011-11-22 11:55:54 +01001945 dma_cap_set(DMA_SLAVE, at91sam9g45_config.cap_mask);
Torsten Fleischer265567f2015-02-23 17:54:11 +01001946 dma_cap_set(DMA_SG, at91sam9g45_config.cap_mask);
Nicolas Ferre67348452011-10-17 14:56:40 +02001947
1948 /* get DMA parameters from controller type */
Nicolas Ferre02f88be2011-11-22 11:55:54 +01001949 plat_dat = at_dma_get_driver_data(pdev);
1950 if (!plat_dat)
1951 return -ENODEV;
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001952
1953 io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1954 if (!io)
1955 return -EINVAL;
1956
1957 irq = platform_get_irq(pdev, 0);
1958 if (irq < 0)
1959 return irq;
1960
1961 size = sizeof(struct at_dma);
Nicolas Ferre02f88be2011-11-22 11:55:54 +01001962 size += plat_dat->nr_channels * sizeof(struct at_dma_chan);
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001963 atdma = kzalloc(size, GFP_KERNEL);
1964 if (!atdma)
1965 return -ENOMEM;
1966
Nicolas Ferre67348452011-10-17 14:56:40 +02001967 /* discover transaction capabilities */
Nicolas Ferre02f88be2011-11-22 11:55:54 +01001968 atdma->dma_common.cap_mask = plat_dat->cap_mask;
1969 atdma->all_chan_mask = (1 << plat_dat->nr_channels) - 1;
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001970
H Hartley Sweeten114df7d2011-06-01 15:16:09 -07001971 size = resource_size(io);
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001972 if (!request_mem_region(io->start, size, pdev->dev.driver->name)) {
1973 err = -EBUSY;
1974 goto err_kfree;
1975 }
1976
1977 atdma->regs = ioremap(io->start, size);
1978 if (!atdma->regs) {
1979 err = -ENOMEM;
1980 goto err_release_r;
1981 }
1982
1983 atdma->clk = clk_get(&pdev->dev, "dma_clk");
1984 if (IS_ERR(atdma->clk)) {
1985 err = PTR_ERR(atdma->clk);
1986 goto err_clk;
1987 }
Boris BREZILLONf784d9c2013-06-19 13:14:54 +02001988 err = clk_prepare_enable(atdma->clk);
1989 if (err)
1990 goto err_clk_prepare;
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001991
1992 /* force dma off, just in case */
1993 at_dma_off(atdma);
1994
1995 err = request_irq(irq, at_dma_interrupt, 0, "at_hdmac", atdma);
1996 if (err)
1997 goto err_irq;
1998
1999 platform_set_drvdata(pdev, atdma);
2000
2001 /* create a pool of consistent memory blocks for hardware descriptors */
2002 atdma->dma_desc_pool = dma_pool_create("at_hdmac_desc_pool",
2003 &pdev->dev, sizeof(struct at_desc),
2004 4 /* word alignment */, 0);
2005 if (!atdma->dma_desc_pool) {
2006 dev_err(&pdev->dev, "No memory for descriptors dma pool\n");
2007 err = -ENOMEM;
Maxime Ripard4d112422015-08-24 11:21:15 +02002008 goto err_desc_pool_create;
2009 }
2010
2011 /* create a pool of consistent memory blocks for memset blocks */
2012 atdma->memset_pool = dma_pool_create("at_hdmac_memset_pool",
2013 &pdev->dev, sizeof(int), 4, 0);
2014 if (!atdma->memset_pool) {
2015 dev_err(&pdev->dev, "No memory for memset dma pool\n");
2016 err = -ENOMEM;
2017 goto err_memset_pool_create;
Nicolas Ferredc78baa2009-07-03 19:24:33 +02002018 }
2019
2020 /* clear any pending interrupt */
2021 while (dma_readl(atdma, EBCISR))
2022 cpu_relax();
2023
2024 /* initialize channels related values */
2025 INIT_LIST_HEAD(&atdma->dma_common.channels);
Nicolas Ferre02f88be2011-11-22 11:55:54 +01002026 for (i = 0; i < plat_dat->nr_channels; i++) {
Nicolas Ferredc78baa2009-07-03 19:24:33 +02002027 struct at_dma_chan *atchan = &atdma->chan[i];
2028
Ludovic Desrochesbbe89c82013-04-19 09:11:18 +00002029 atchan->mem_if = AT_DMA_MEM_IF;
2030 atchan->per_if = AT_DMA_PER_IF;
Nicolas Ferredc78baa2009-07-03 19:24:33 +02002031 atchan->chan_common.device = &atdma->dma_common;
Russell King - ARM Linuxd3ee98cdc2012-03-06 22:35:47 +00002032 dma_cookie_init(&atchan->chan_common);
Nicolas Ferredc78baa2009-07-03 19:24:33 +02002033 list_add_tail(&atchan->chan_common.device_node,
2034 &atdma->dma_common.channels);
2035
2036 atchan->ch_regs = atdma->regs + ch_regs(i);
2037 spin_lock_init(&atchan->lock);
2038 atchan->mask = 1 << i;
2039
2040 INIT_LIST_HEAD(&atchan->active_list);
2041 INIT_LIST_HEAD(&atchan->queue);
2042 INIT_LIST_HEAD(&atchan->free_list);
2043
2044 tasklet_init(&atchan->tasklet, atc_tasklet,
2045 (unsigned long)atchan);
Nikolaus Vossbda3a472012-01-17 10:28:33 +01002046 atc_enable_chan_irq(atdma, i);
Nicolas Ferredc78baa2009-07-03 19:24:33 +02002047 }
2048
2049 /* set base routines */
2050 atdma->dma_common.device_alloc_chan_resources = atc_alloc_chan_resources;
2051 atdma->dma_common.device_free_chan_resources = atc_free_chan_resources;
Linus Walleij07934482010-03-26 16:50:49 -07002052 atdma->dma_common.device_tx_status = atc_tx_status;
Nicolas Ferredc78baa2009-07-03 19:24:33 +02002053 atdma->dma_common.device_issue_pending = atc_issue_pending;
2054 atdma->dma_common.dev = &pdev->dev;
2055
2056 /* set prep routines based on capability */
Maxime Ripard5abecfa2015-05-27 16:01:53 +02002057 if (dma_has_cap(DMA_INTERLEAVE, atdma->dma_common.cap_mask))
2058 atdma->dma_common.device_prep_interleaved_dma = atc_prep_dma_interleaved;
2059
Nicolas Ferredc78baa2009-07-03 19:24:33 +02002060 if (dma_has_cap(DMA_MEMCPY, atdma->dma_common.cap_mask))
2061 atdma->dma_common.device_prep_dma_memcpy = atc_prep_dma_memcpy;
2062
Maxime Ripard4d112422015-08-24 11:21:15 +02002063 if (dma_has_cap(DMA_MEMSET, atdma->dma_common.cap_mask)) {
2064 atdma->dma_common.device_prep_dma_memset = atc_prep_dma_memset;
Maxime Ripard67d25f02015-10-22 11:41:00 +02002065 atdma->dma_common.device_prep_dma_memset_sg = atc_prep_dma_memset_sg;
Maxime Ripard4d112422015-08-24 11:21:15 +02002066 atdma->dma_common.fill_align = DMAENGINE_ALIGN_4_BYTES;
2067 }
2068
Nicolas Ferred7db8082011-08-05 11:43:44 +00002069 if (dma_has_cap(DMA_SLAVE, atdma->dma_common.cap_mask)) {
Nicolas Ferre808347f2009-07-22 20:04:45 +02002070 atdma->dma_common.device_prep_slave_sg = atc_prep_slave_sg;
Nicolas Ferred7db8082011-08-05 11:43:44 +00002071 /* controller can do slave DMA: can trigger cyclic transfers */
2072 dma_cap_set(DMA_CYCLIC, atdma->dma_common.cap_mask);
Nicolas Ferre53830cc2011-04-30 16:57:46 +02002073 atdma->dma_common.device_prep_dma_cyclic = atc_prep_dma_cyclic;
Maxime Ripard4facfe72014-11-17 14:42:06 +01002074 atdma->dma_common.device_config = atc_config;
2075 atdma->dma_common.device_pause = atc_pause;
2076 atdma->dma_common.device_resume = atc_resume;
2077 atdma->dma_common.device_terminate_all = atc_terminate_all;
Ludovic Desroches816070e2015-01-06 17:36:26 +01002078 atdma->dma_common.src_addr_widths = ATC_DMA_BUSWIDTHS;
2079 atdma->dma_common.dst_addr_widths = ATC_DMA_BUSWIDTHS;
2080 atdma->dma_common.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
2081 atdma->dma_common.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
Nicolas Ferred7db8082011-08-05 11:43:44 +00002082 }
Nicolas Ferre808347f2009-07-22 20:04:45 +02002083
Torsten Fleischer265567f2015-02-23 17:54:11 +01002084 if (dma_has_cap(DMA_SG, atdma->dma_common.cap_mask))
2085 atdma->dma_common.device_prep_dma_sg = atc_prep_dma_sg;
2086
Nicolas Ferredc78baa2009-07-03 19:24:33 +02002087 dma_writel(atdma, EN, AT_DMA_ENABLE);
2088
Maxime Ripard4d112422015-08-24 11:21:15 +02002089 dev_info(&pdev->dev, "Atmel AHB DMA Controller ( %s%s%s%s), %d channels\n",
Nicolas Ferredc78baa2009-07-03 19:24:33 +02002090 dma_has_cap(DMA_MEMCPY, atdma->dma_common.cap_mask) ? "cpy " : "",
Maxime Ripard4d112422015-08-24 11:21:15 +02002091 dma_has_cap(DMA_MEMSET, atdma->dma_common.cap_mask) ? "set " : "",
Nicolas Ferredc78baa2009-07-03 19:24:33 +02002092 dma_has_cap(DMA_SLAVE, atdma->dma_common.cap_mask) ? "slave " : "",
Torsten Fleischer265567f2015-02-23 17:54:11 +01002093 dma_has_cap(DMA_SG, atdma->dma_common.cap_mask) ? "sg-cpy " : "",
Nicolas Ferre02f88be2011-11-22 11:55:54 +01002094 plat_dat->nr_channels);
Nicolas Ferredc78baa2009-07-03 19:24:33 +02002095
2096 dma_async_device_register(&atdma->dma_common);
2097
Ludovic Desrochesbbe89c82013-04-19 09:11:18 +00002098 /*
2099 * Do not return an error if the dmac node is not present in order to
2100 * not break the existing way of requesting channel with
2101 * dma_request_channel().
2102 */
2103 if (pdev->dev.of_node) {
2104 err = of_dma_controller_register(pdev->dev.of_node,
2105 at_dma_xlate, atdma);
2106 if (err) {
2107 dev_err(&pdev->dev, "could not register of_dma_controller\n");
2108 goto err_of_dma_controller_register;
2109 }
2110 }
2111
Nicolas Ferredc78baa2009-07-03 19:24:33 +02002112 return 0;
2113
Ludovic Desrochesbbe89c82013-04-19 09:11:18 +00002114err_of_dma_controller_register:
2115 dma_async_device_unregister(&atdma->dma_common);
Maxime Ripard4d112422015-08-24 11:21:15 +02002116 dma_pool_destroy(atdma->memset_pool);
2117err_memset_pool_create:
Ludovic Desrochesbbe89c82013-04-19 09:11:18 +00002118 dma_pool_destroy(atdma->dma_desc_pool);
Maxime Ripard4d112422015-08-24 11:21:15 +02002119err_desc_pool_create:
Nicolas Ferredc78baa2009-07-03 19:24:33 +02002120 free_irq(platform_get_irq(pdev, 0), atdma);
2121err_irq:
Boris BREZILLONf784d9c2013-06-19 13:14:54 +02002122 clk_disable_unprepare(atdma->clk);
2123err_clk_prepare:
Nicolas Ferredc78baa2009-07-03 19:24:33 +02002124 clk_put(atdma->clk);
2125err_clk:
2126 iounmap(atdma->regs);
2127 atdma->regs = NULL;
2128err_release_r:
2129 release_mem_region(io->start, size);
2130err_kfree:
2131 kfree(atdma);
2132 return err;
2133}
2134
Maxin B. John1d1bbd32013-02-20 02:07:04 +02002135static int at_dma_remove(struct platform_device *pdev)
Nicolas Ferredc78baa2009-07-03 19:24:33 +02002136{
2137 struct at_dma *atdma = platform_get_drvdata(pdev);
2138 struct dma_chan *chan, *_chan;
2139 struct resource *io;
2140
2141 at_dma_off(atdma);
2142 dma_async_device_unregister(&atdma->dma_common);
2143
Maxime Ripard4d112422015-08-24 11:21:15 +02002144 dma_pool_destroy(atdma->memset_pool);
Nicolas Ferredc78baa2009-07-03 19:24:33 +02002145 dma_pool_destroy(atdma->dma_desc_pool);
Nicolas Ferredc78baa2009-07-03 19:24:33 +02002146 free_irq(platform_get_irq(pdev, 0), atdma);
2147
2148 list_for_each_entry_safe(chan, _chan, &atdma->dma_common.channels,
2149 device_node) {
2150 struct at_dma_chan *atchan = to_at_dma_chan(chan);
2151
2152 /* Disable interrupts */
Nikolaus Vossbda3a472012-01-17 10:28:33 +01002153 atc_disable_chan_irq(atdma, chan->chan_id);
Nicolas Ferredc78baa2009-07-03 19:24:33 +02002154
2155 tasklet_kill(&atchan->tasklet);
2156 list_del(&chan->device_node);
2157 }
2158
Boris BREZILLONf784d9c2013-06-19 13:14:54 +02002159 clk_disable_unprepare(atdma->clk);
Nicolas Ferredc78baa2009-07-03 19:24:33 +02002160 clk_put(atdma->clk);
2161
2162 iounmap(atdma->regs);
2163 atdma->regs = NULL;
2164
2165 io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
H Hartley Sweeten114df7d2011-06-01 15:16:09 -07002166 release_mem_region(io->start, resource_size(io));
Nicolas Ferredc78baa2009-07-03 19:24:33 +02002167
2168 kfree(atdma);
2169
2170 return 0;
2171}
2172
2173static void at_dma_shutdown(struct platform_device *pdev)
2174{
2175 struct at_dma *atdma = platform_get_drvdata(pdev);
2176
2177 at_dma_off(platform_get_drvdata(pdev));
Boris BREZILLONf784d9c2013-06-19 13:14:54 +02002178 clk_disable_unprepare(atdma->clk);
Nicolas Ferredc78baa2009-07-03 19:24:33 +02002179}
2180
Nicolas Ferrec0ba5942011-07-27 12:21:29 +00002181static int at_dma_prepare(struct device *dev)
2182{
2183 struct platform_device *pdev = to_platform_device(dev);
2184 struct at_dma *atdma = platform_get_drvdata(pdev);
2185 struct dma_chan *chan, *_chan;
2186
2187 list_for_each_entry_safe(chan, _chan, &atdma->dma_common.channels,
2188 device_node) {
2189 struct at_dma_chan *atchan = to_at_dma_chan(chan);
2190 /* wait for transaction completion (except in cyclic case) */
Nicolas Ferre3c477482011-07-25 21:09:23 +00002191 if (atc_chan_is_enabled(atchan) && !atc_chan_is_cyclic(atchan))
Nicolas Ferrec0ba5942011-07-27 12:21:29 +00002192 return -EAGAIN;
2193 }
2194 return 0;
2195}
2196
2197static void atc_suspend_cyclic(struct at_dma_chan *atchan)
2198{
2199 struct dma_chan *chan = &atchan->chan_common;
2200
2201 /* Channel should be paused by user
2202 * do it anyway even if it is not done already */
Nicolas Ferre3c477482011-07-25 21:09:23 +00002203 if (!atc_chan_is_paused(atchan)) {
Nicolas Ferrec0ba5942011-07-27 12:21:29 +00002204 dev_warn(chan2dev(chan),
2205 "cyclic channel not paused, should be done by channel user\n");
Maxime Ripard4facfe72014-11-17 14:42:06 +01002206 atc_pause(chan);
Nicolas Ferrec0ba5942011-07-27 12:21:29 +00002207 }
2208
2209 /* now preserve additional data for cyclic operations */
2210 /* next descriptor address in the cyclic list */
2211 atchan->save_dscr = channel_readl(atchan, DSCR);
2212
2213 vdbg_dump_regs(atchan);
2214}
2215
Dan Williams33f82d12009-09-10 00:06:44 +02002216static int at_dma_suspend_noirq(struct device *dev)
Nicolas Ferredc78baa2009-07-03 19:24:33 +02002217{
Dan Williams33f82d12009-09-10 00:06:44 +02002218 struct platform_device *pdev = to_platform_device(dev);
2219 struct at_dma *atdma = platform_get_drvdata(pdev);
Nicolas Ferrec0ba5942011-07-27 12:21:29 +00002220 struct dma_chan *chan, *_chan;
Nicolas Ferredc78baa2009-07-03 19:24:33 +02002221
Nicolas Ferrec0ba5942011-07-27 12:21:29 +00002222 /* preserve data */
2223 list_for_each_entry_safe(chan, _chan, &atdma->dma_common.channels,
2224 device_node) {
2225 struct at_dma_chan *atchan = to_at_dma_chan(chan);
2226
Nicolas Ferre3c477482011-07-25 21:09:23 +00002227 if (atc_chan_is_cyclic(atchan))
Nicolas Ferrec0ba5942011-07-27 12:21:29 +00002228 atc_suspend_cyclic(atchan);
2229 atchan->save_cfg = channel_readl(atchan, CFG);
2230 }
2231 atdma->save_imr = dma_readl(atdma, EBCIMR);
2232
2233 /* disable DMA controller */
2234 at_dma_off(atdma);
Boris BREZILLONf784d9c2013-06-19 13:14:54 +02002235 clk_disable_unprepare(atdma->clk);
Nicolas Ferredc78baa2009-07-03 19:24:33 +02002236 return 0;
2237}
2238
Nicolas Ferrec0ba5942011-07-27 12:21:29 +00002239static void atc_resume_cyclic(struct at_dma_chan *atchan)
2240{
2241 struct at_dma *atdma = to_at_dma(atchan->chan_common.device);
2242
2243 /* restore channel status for cyclic descriptors list:
2244 * next descriptor in the cyclic list at the time of suspend */
2245 channel_writel(atchan, SADDR, 0);
2246 channel_writel(atchan, DADDR, 0);
2247 channel_writel(atchan, CTRLA, 0);
2248 channel_writel(atchan, CTRLB, 0);
2249 channel_writel(atchan, DSCR, atchan->save_dscr);
2250 dma_writel(atdma, CHER, atchan->mask);
2251
2252 /* channel pause status should be removed by channel user
2253 * We cannot take the initiative to do it here */
2254
2255 vdbg_dump_regs(atchan);
2256}
2257
Dan Williams33f82d12009-09-10 00:06:44 +02002258static int at_dma_resume_noirq(struct device *dev)
Nicolas Ferredc78baa2009-07-03 19:24:33 +02002259{
Dan Williams33f82d12009-09-10 00:06:44 +02002260 struct platform_device *pdev = to_platform_device(dev);
2261 struct at_dma *atdma = platform_get_drvdata(pdev);
Nicolas Ferrec0ba5942011-07-27 12:21:29 +00002262 struct dma_chan *chan, *_chan;
Nicolas Ferredc78baa2009-07-03 19:24:33 +02002263
Nicolas Ferrec0ba5942011-07-27 12:21:29 +00002264 /* bring back DMA controller */
Boris BREZILLONf784d9c2013-06-19 13:14:54 +02002265 clk_prepare_enable(atdma->clk);
Nicolas Ferredc78baa2009-07-03 19:24:33 +02002266 dma_writel(atdma, EN, AT_DMA_ENABLE);
Nicolas Ferrec0ba5942011-07-27 12:21:29 +00002267
2268 /* clear any pending interrupt */
2269 while (dma_readl(atdma, EBCISR))
2270 cpu_relax();
2271
2272 /* restore saved data */
2273 dma_writel(atdma, EBCIER, atdma->save_imr);
2274 list_for_each_entry_safe(chan, _chan, &atdma->dma_common.channels,
2275 device_node) {
2276 struct at_dma_chan *atchan = to_at_dma_chan(chan);
2277
2278 channel_writel(atchan, CFG, atchan->save_cfg);
Nicolas Ferre3c477482011-07-25 21:09:23 +00002279 if (atc_chan_is_cyclic(atchan))
Nicolas Ferrec0ba5942011-07-27 12:21:29 +00002280 atc_resume_cyclic(atchan);
2281 }
Nicolas Ferredc78baa2009-07-03 19:24:33 +02002282 return 0;
Nicolas Ferredc78baa2009-07-03 19:24:33 +02002283}
2284
Alexey Dobriyan47145212009-12-14 18:00:08 -08002285static const struct dev_pm_ops at_dma_dev_pm_ops = {
Nicolas Ferrec0ba5942011-07-27 12:21:29 +00002286 .prepare = at_dma_prepare,
Dan Williams33f82d12009-09-10 00:06:44 +02002287 .suspend_noirq = at_dma_suspend_noirq,
2288 .resume_noirq = at_dma_resume_noirq,
2289};
2290
Nicolas Ferredc78baa2009-07-03 19:24:33 +02002291static struct platform_driver at_dma_driver = {
Maxin B. John1d1bbd32013-02-20 02:07:04 +02002292 .remove = at_dma_remove,
Nicolas Ferredc78baa2009-07-03 19:24:33 +02002293 .shutdown = at_dma_shutdown,
Nicolas Ferre67348452011-10-17 14:56:40 +02002294 .id_table = atdma_devtypes,
Nicolas Ferredc78baa2009-07-03 19:24:33 +02002295 .driver = {
2296 .name = "at_hdmac",
Dan Williams33f82d12009-09-10 00:06:44 +02002297 .pm = &at_dma_dev_pm_ops,
Nicolas Ferrec5115952011-10-17 14:56:41 +02002298 .of_match_table = of_match_ptr(atmel_dma_dt_ids),
Nicolas Ferredc78baa2009-07-03 19:24:33 +02002299 },
2300};
2301
2302static int __init at_dma_init(void)
2303{
2304 return platform_driver_probe(&at_dma_driver, at_dma_probe);
2305}
Eric Xu93d0bec2011-01-12 15:39:08 +01002306subsys_initcall(at_dma_init);
Nicolas Ferredc78baa2009-07-03 19:24:33 +02002307
2308static void __exit at_dma_exit(void)
2309{
2310 platform_driver_unregister(&at_dma_driver);
2311}
2312module_exit(at_dma_exit);
2313
2314MODULE_DESCRIPTION("Atmel AHB DMA Controller driver");
2315MODULE_AUTHOR("Nicolas Ferre <nicolas.ferre@atmel.com>");
2316MODULE_LICENSE("GPL");
2317MODULE_ALIAS("platform:at_hdmac");