blob: cd979543cdff21a3fc8b7e5f10a965a55c9b3268 [file] [log] [blame]
Ben Skeggs3f204642014-02-24 11:28:37 +10001/*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
Ben Skeggs97190472015-01-14 15:35:00 +100024#include "priv.h"
Ben Skeggs3f204642014-02-24 11:28:37 +100025
26#include <subdev/bios.h>
27#include <subdev/bus.h>
28#include <subdev/gpio.h>
29#include <subdev/i2c.h>
Martin Peres3ca6cd42014-08-26 00:26:38 +020030#include <subdev/fuse.h>
Ben Skeggsf3867f42015-01-13 23:37:38 +100031#include <subdev/clk.h>
Ben Skeggs3f204642014-02-24 11:28:37 +100032#include <subdev/therm.h>
33#include <subdev/mxm.h>
34#include <subdev/devinit.h>
35#include <subdev/mc.h>
36#include <subdev/timer.h>
37#include <subdev/fb.h>
Ben Skeggs95484b52014-08-10 04:10:28 +100038#include <subdev/ltc.h>
Ben Skeggs3f204642014-02-24 11:28:37 +100039#include <subdev/ibus.h>
40#include <subdev/instmem.h>
Ben Skeggs5ce3bf32015-01-14 09:57:36 +100041#include <subdev/mmu.h>
Ben Skeggs3f204642014-02-24 11:28:37 +100042#include <subdev/bar.h>
Ben Skeggsebb58dc2015-01-14 00:04:21 +100043#include <subdev/pmu.h>
Ben Skeggs3f204642014-02-24 11:28:37 +100044#include <subdev/volt.h>
45
Ben Skeggs3f204642014-02-24 11:28:37 +100046#include <engine/dmaobj.h>
47#include <engine/fifo.h>
Ben Skeggs87002872015-01-14 12:34:00 +100048#include <engine/sw.h>
Ben Skeggsb8bf04e2015-01-14 12:02:28 +100049#include <engine/gr.h>
Ben Skeggs3f204642014-02-24 11:28:37 +100050#include <engine/disp.h>
Ben Skeggsaedf24f2015-01-14 11:50:20 +100051#include <engine/ce.h>
Ben Skeggs3f204642014-02-24 11:28:37 +100052#include <engine/bsp.h>
Ben Skeggseccf7e8a2015-01-14 10:09:24 +100053#include <engine/msvld.h>
Ben Skeggs37a5d022015-01-14 12:50:04 +100054#include <engine/mspdec.h>
Ben Skeggsfd8666f2015-01-14 12:26:28 +100055#include <engine/msppp.h>
Ben Skeggsd5752b92015-01-14 12:11:28 +100056#include <engine/pm.h>
Ben Skeggs3f204642014-02-24 11:28:37 +100057
58int
Ben Skeggs97190472015-01-14 15:35:00 +100059gm100_identify(struct nvkm_device *device)
Ben Skeggs3f204642014-02-24 11:28:37 +100060{
61 switch (device->chipset) {
62 case 0x117:
63 device->cname = "GM107";
Ben Skeggs97190472015-01-14 15:35:00 +100064 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
Ben Skeggs4e7659f2015-01-14 15:02:59 +100065 device->oclass[NVDEV_SUBDEV_GPIO ] = gk104_gpio_oclass;
Ben Skeggsb9ec1422015-01-14 15:04:16 +100066 device->oclass[NVDEV_SUBDEV_I2C ] = gf110_i2c_oclass;
Martin Peres3ca6cd42014-08-26 00:26:38 +020067 device->oclass[NVDEV_SUBDEV_FUSE ] = &gm107_fuse_oclass;
Ben Skeggs7632b302015-01-14 14:47:24 +100068 device->oclass[NVDEV_SUBDEV_CLK ] = &gk104_clk_oclass;
Martin Peres808a1882014-08-17 17:33:08 +020069 device->oclass[NVDEV_SUBDEV_THERM ] = &gm107_therm_oclass;
Ben Skeggs3f204642014-02-24 11:28:37 +100070 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
71 device->oclass[NVDEV_SUBDEV_DEVINIT] = gm107_devinit_oclass;
Ben Skeggs7d155da2014-06-12 22:15:21 +100072 device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass;
Ben Skeggs5f8824d2015-01-14 14:40:22 +100073 device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
Ben Skeggs3f204642014-02-24 11:28:37 +100074 device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass;
75 device->oclass[NVDEV_SUBDEV_FB ] = gm107_fb_oclass;
Ben Skeggs95484b52014-08-10 04:10:28 +100076 device->oclass[NVDEV_SUBDEV_LTC ] = gm107_ltc_oclass;
Ben Skeggs5ecfade2015-01-14 15:04:31 +100077 device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass;
Ben Skeggs3f204642014-02-24 11:28:37 +100078 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
Ben Skeggs42594602015-01-14 15:09:19 +100079 device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
Ben Skeggs245dcfe2015-01-14 14:35:35 +100080 device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
Ben Skeggs21b13792015-01-14 15:10:40 +100081 device->oclass[NVDEV_SUBDEV_PMU ] = gk208_pmu_oclass;
Martin Peres2a5e5fa2014-08-17 17:33:09 +020082
83#if 0
Ben Skeggs3f204642014-02-24 11:28:37 +100084 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
85#endif
Ben Skeggs5b850572015-01-14 15:27:54 +100086 device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
Ben Skeggs05c71452015-01-14 15:28:47 +100087 device->oclass[NVDEV_ENGINE_FIFO ] = gk208_fifo_oclass;
Ben Skeggsf84aff42015-01-14 15:32:15 +100088 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
Ben Skeggsb8bf04e2015-01-14 12:02:28 +100089 device->oclass[NVDEV_ENGINE_GR ] = gm107_gr_oclass;
Ben Skeggs3f204642014-02-24 11:28:37 +100090 device->oclass[NVDEV_ENGINE_DISP ] = gm107_disp_oclass;
Ben Skeggsbd6c5ca2015-01-14 15:22:32 +100091 device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass;
Ben Skeggs3f204642014-02-24 11:28:37 +100092#if 0
Ben Skeggsbd6c5ca2015-01-14 15:22:32 +100093 device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass;
Ben Skeggs3f204642014-02-24 11:28:37 +100094#endif
Ben Skeggsbd6c5ca2015-01-14 15:22:32 +100095 device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass;
Ben Skeggs3f204642014-02-24 11:28:37 +100096#if 0
Ben Skeggs87c33f42015-01-14 15:30:40 +100097 device->oclass[NVDEV_ENGINE_MSVLD ] = &gk104_msvld_oclass;
Ben Skeggse3332c22015-01-14 15:30:09 +100098 device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass;
Ben Skeggs87a87652015-01-14 15:30:22 +100099 device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
Ben Skeggs3f204642014-02-24 11:28:37 +1000100#endif
101 break;
Ben Skeggs083dba02014-08-18 14:02:14 +1000102 case 0x124:
103 device->cname = "GM204";
Ben Skeggs97190472015-01-14 15:35:00 +1000104 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
Ben Skeggs4e7659f2015-01-14 15:02:59 +1000105 device->oclass[NVDEV_SUBDEV_GPIO ] = gk104_gpio_oclass;
Ben Skeggs083dba02014-08-18 14:02:14 +1000106 device->oclass[NVDEV_SUBDEV_I2C ] = gm204_i2c_oclass;
107 device->oclass[NVDEV_SUBDEV_FUSE ] = &gm107_fuse_oclass;
108#if 0
109 /* looks to be some non-trivial changes */
Ben Skeggs7632b302015-01-14 14:47:24 +1000110 device->oclass[NVDEV_SUBDEV_CLK ] = &gk104_clk_oclass;
Ben Skeggs083dba02014-08-18 14:02:14 +1000111 /* priv ring says no to 0x10eb14 writes */
112 device->oclass[NVDEV_SUBDEV_THERM ] = &gm107_therm_oclass;
113#endif
114 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
115 device->oclass[NVDEV_SUBDEV_DEVINIT] = gm204_devinit_oclass;
116 device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass;
Ben Skeggs5f8824d2015-01-14 14:40:22 +1000117 device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
Ben Skeggs083dba02014-08-18 14:02:14 +1000118 device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass;
119 device->oclass[NVDEV_SUBDEV_FB ] = gm107_fb_oclass;
120 device->oclass[NVDEV_SUBDEV_LTC ] = gm107_ltc_oclass;
Ben Skeggs5ecfade2015-01-14 15:04:31 +1000121 device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass;
Ben Skeggs083dba02014-08-18 14:02:14 +1000122 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
Ben Skeggs42594602015-01-14 15:09:19 +1000123 device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
Ben Skeggs245dcfe2015-01-14 14:35:35 +1000124 device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
Ben Skeggs21b13792015-01-14 15:10:40 +1000125 device->oclass[NVDEV_SUBDEV_PMU ] = gk208_pmu_oclass;
Ben Skeggs083dba02014-08-18 14:02:14 +1000126#if 0
127 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
128#endif
Ben Skeggs5b850572015-01-14 15:27:54 +1000129 device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
Ben Skeggs89025bd2015-03-11 12:21:15 +1000130 device->oclass[NVDEV_ENGINE_FIFO ] = gm204_fifo_oclass;
Ben Skeggsf84aff42015-01-14 15:32:15 +1000131 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
Ben Skeggs3fed3ea2015-03-26 09:28:34 +1000132 device->oclass[NVDEV_ENGINE_GR ] = gm204_gr_oclass;
Ben Skeggs083dba02014-08-18 14:02:14 +1000133 device->oclass[NVDEV_ENGINE_DISP ] = gm204_disp_oclass;
Ben Skeggsaedf24f2015-01-14 11:50:20 +1000134 device->oclass[NVDEV_ENGINE_CE0 ] = &gm204_ce0_oclass;
135 device->oclass[NVDEV_ENGINE_CE1 ] = &gm204_ce1_oclass;
136 device->oclass[NVDEV_ENGINE_CE2 ] = &gm204_ce2_oclass;
Ben Skeggsb44881e2015-03-11 12:24:45 +1000137#if 0
Ben Skeggs87c33f42015-01-14 15:30:40 +1000138 device->oclass[NVDEV_ENGINE_MSVLD ] = &gk104_msvld_oclass;
Ben Skeggse3332c22015-01-14 15:30:09 +1000139 device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass;
Ben Skeggs87a87652015-01-14 15:30:22 +1000140 device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
Ben Skeggs083dba02014-08-18 14:02:14 +1000141#endif
142 break;
Stefan Huehner7e547ad2015-02-21 22:23:56 +0100143 case 0x126:
144 device->cname = "GM206";
145 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
146 device->oclass[NVDEV_SUBDEV_GPIO ] = gk104_gpio_oclass;
147 device->oclass[NVDEV_SUBDEV_I2C ] = gm204_i2c_oclass;
148 device->oclass[NVDEV_SUBDEV_FUSE ] = &gm107_fuse_oclass;
149#if 0
150 /* looks to be some non-trivial changes */
151 device->oclass[NVDEV_SUBDEV_CLK ] = &gk104_clk_oclass;
152 /* priv ring says no to 0x10eb14 writes */
153 device->oclass[NVDEV_SUBDEV_THERM ] = &gm107_therm_oclass;
154#endif
155 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
156 device->oclass[NVDEV_SUBDEV_DEVINIT] = gm204_devinit_oclass;
157 device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass;
158 device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
159 device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass;
160 device->oclass[NVDEV_SUBDEV_FB ] = gm107_fb_oclass;
161 device->oclass[NVDEV_SUBDEV_LTC ] = gm107_ltc_oclass;
162 device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass;
163 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
164 device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
165 device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
166 device->oclass[NVDEV_SUBDEV_PMU ] = gk208_pmu_oclass;
167#if 0
168 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
169#endif
170 device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
Ben Skeggs5dd7fb72015-04-14 11:45:10 +1000171 device->oclass[NVDEV_ENGINE_FIFO ] = gm204_fifo_oclass;
Stefan Huehner7e547ad2015-02-21 22:23:56 +0100172 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
Ben Skeggs426b20e2015-04-14 12:06:44 +1000173 device->oclass[NVDEV_ENGINE_GR ] = gm206_gr_oclass;
Stefan Huehner7e547ad2015-02-21 22:23:56 +0100174 device->oclass[NVDEV_ENGINE_DISP ] = gm204_disp_oclass;
Stefan Huehner7e547ad2015-02-21 22:23:56 +0100175 device->oclass[NVDEV_ENGINE_CE0 ] = &gm204_ce0_oclass;
176 device->oclass[NVDEV_ENGINE_CE1 ] = &gm204_ce1_oclass;
177 device->oclass[NVDEV_ENGINE_CE2 ] = &gm204_ce2_oclass;
Ben Skeggs985826b2015-04-14 11:45:29 +1000178#if 0
Stefan Huehner7e547ad2015-02-21 22:23:56 +0100179 device->oclass[NVDEV_ENGINE_MSVLD ] = &gk104_msvld_oclass;
180 device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass;
181 device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
182#endif
183 break;
Alexandre Courbotd10ae272015-06-23 15:16:05 +0900184 case 0x12b:
185 device->cname = "GM20B";
186
187 device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass;
188 device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
189 device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
190 device->oclass[NVDEV_SUBDEV_FUSE ] = &gm107_fuse_oclass;
191 device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass;
192 device->oclass[NVDEV_SUBDEV_FB ] = gk20a_fb_oclass;
193 device->oclass[NVDEV_SUBDEV_LTC ] = gm107_ltc_oclass;
194 device->oclass[NVDEV_SUBDEV_IBUS ] = &gk20a_ibus_oclass;
195 device->oclass[NVDEV_SUBDEV_INSTMEM] = gk20a_instmem_oclass;
196 device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
197 device->oclass[NVDEV_SUBDEV_BAR ] = &gk20a_bar_oclass;
198 device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
199 device->oclass[NVDEV_ENGINE_FIFO ] = gm20b_fifo_oclass;
200 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
201 device->oclass[NVDEV_ENGINE_GR ] = gm20b_gr_oclass;
202 device->oclass[NVDEV_ENGINE_CE2 ] = &gm204_ce2_oclass;
203 break;
Ben Skeggs3f204642014-02-24 11:28:37 +1000204 default:
Ben Skeggs3f204642014-02-24 11:28:37 +1000205 return -EINVAL;
206 }
207
208 return 0;
209}