Ben Skeggs | 0a0afd2 | 2013-02-18 23:17:53 -0500 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2013 Red Hat Inc. |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice shall be included in |
| 12 | * all copies or substantial portions of the Software. |
| 13 | * |
| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 20 | * OTHER DEALINGS IN THE SOFTWARE. |
| 21 | * |
| 22 | * Authors: Ben Skeggs |
| 23 | */ |
| 24 | |
| 25 | #include <subdev/bios.h> |
| 26 | #include <subdev/bios/dcb.h> |
| 27 | #include <subdev/bios/dp.h> |
| 28 | #include <subdev/bios/init.h> |
| 29 | #include <subdev/i2c.h> |
| 30 | |
| 31 | #include <engine/disp.h> |
| 32 | |
Ben Skeggs | 04e7e92 | 2014-05-15 22:20:40 +1000 | [diff] [blame] | 33 | #include <core/class.h> |
| 34 | |
Ben Skeggs | 0a0afd2 | 2013-02-18 23:17:53 -0500 | [diff] [blame] | 35 | #include "dport.h" |
Ben Skeggs | 3b52a1f | 2014-05-19 14:06:07 +1000 | [diff] [blame] | 36 | #include "outpdp.h" |
Ben Skeggs | 0a0afd2 | 2013-02-18 23:17:53 -0500 | [diff] [blame] | 37 | |
| 38 | /****************************************************************************** |
| 39 | * link training |
| 40 | *****************************************************************************/ |
| 41 | struct dp_state { |
Ben Skeggs | 3b52a1f | 2014-05-19 14:06:07 +1000 | [diff] [blame] | 42 | struct nvkm_output_dp *outp; |
Ben Skeggs | 0a0afd2 | 2013-02-18 23:17:53 -0500 | [diff] [blame] | 43 | int link_nr; |
| 44 | u32 link_bw; |
| 45 | u8 stat[6]; |
| 46 | u8 conf[4]; |
Ben Skeggs | 04e7e92 | 2014-05-15 22:20:40 +1000 | [diff] [blame] | 47 | bool pc2; |
| 48 | u8 pc2stat; |
| 49 | u8 pc2conf[2]; |
Ben Skeggs | 0a0afd2 | 2013-02-18 23:17:53 -0500 | [diff] [blame] | 50 | }; |
| 51 | |
| 52 | static int |
| 53 | dp_set_link_config(struct dp_state *dp) |
| 54 | { |
Ben Skeggs | 3b52a1f | 2014-05-19 14:06:07 +1000 | [diff] [blame] | 55 | struct nvkm_output_dp_impl *impl = (void *)nv_oclass(dp->outp); |
| 56 | struct nvkm_output_dp *outp = dp->outp; |
| 57 | struct nouveau_disp *disp = nouveau_disp(outp); |
Ben Skeggs | 0a0afd2 | 2013-02-18 23:17:53 -0500 | [diff] [blame] | 58 | struct nouveau_bios *bios = nouveau_bios(disp); |
| 59 | struct nvbios_init init = { |
Ben Skeggs | 3b52a1f | 2014-05-19 14:06:07 +1000 | [diff] [blame] | 60 | .subdev = nv_subdev(disp), |
Ben Skeggs | 0a0afd2 | 2013-02-18 23:17:53 -0500 | [diff] [blame] | 61 | .bios = bios, |
| 62 | .offset = 0x0000, |
Ben Skeggs | 3b52a1f | 2014-05-19 14:06:07 +1000 | [diff] [blame] | 63 | .outp = &outp->base.info, |
| 64 | .crtc = -1, |
Ben Skeggs | 0a0afd2 | 2013-02-18 23:17:53 -0500 | [diff] [blame] | 65 | .execute = 1, |
| 66 | }; |
| 67 | u32 lnkcmp; |
| 68 | u8 sink[2]; |
Ben Skeggs | 8df1d0c | 2013-11-04 13:40:36 +1000 | [diff] [blame] | 69 | int ret; |
Ben Skeggs | 0a0afd2 | 2013-02-18 23:17:53 -0500 | [diff] [blame] | 70 | |
| 71 | DBG("%d lanes at %d KB/s\n", dp->link_nr, dp->link_bw); |
| 72 | |
Ben Skeggs | 0a0afd2 | 2013-02-18 23:17:53 -0500 | [diff] [blame] | 73 | /* set desired link configuration on the source */ |
Ben Skeggs | 3b52a1f | 2014-05-19 14:06:07 +1000 | [diff] [blame] | 74 | if ((lnkcmp = dp->outp->info.lnkcmp)) { |
| 75 | if (outp->version < 0x30) { |
Ben Skeggs | 0a0afd2 | 2013-02-18 23:17:53 -0500 | [diff] [blame] | 76 | while ((dp->link_bw / 10) < nv_ro16(bios, lnkcmp)) |
| 77 | lnkcmp += 4; |
| 78 | init.offset = nv_ro16(bios, lnkcmp + 2); |
| 79 | } else { |
| 80 | while ((dp->link_bw / 27000) < nv_ro08(bios, lnkcmp)) |
| 81 | lnkcmp += 3; |
| 82 | init.offset = nv_ro16(bios, lnkcmp + 1); |
| 83 | } |
| 84 | |
| 85 | nvbios_exec(&init); |
| 86 | } |
| 87 | |
Ben Skeggs | 3b52a1f | 2014-05-19 14:06:07 +1000 | [diff] [blame] | 88 | ret = impl->lnk_ctl(outp, dp->link_nr, dp->link_bw / 27000, |
| 89 | outp->dpcd[DPCD_RC02] & |
| 90 | DPCD_RC02_ENHANCED_FRAME_CAP); |
Ben Skeggs | 8df1d0c | 2013-11-04 13:40:36 +1000 | [diff] [blame] | 91 | if (ret) { |
Ben Skeggs | 3b52a1f | 2014-05-19 14:06:07 +1000 | [diff] [blame] | 92 | if (ret < 0) |
| 93 | ERR("lnk_ctl failed with %d\n", ret); |
Ben Skeggs | 8df1d0c | 2013-11-04 13:40:36 +1000 | [diff] [blame] | 94 | return ret; |
| 95 | } |
| 96 | |
Ben Skeggs | 1ecee1c | 2014-05-26 11:57:57 +1000 | [diff] [blame] | 97 | impl->lnk_pwr(outp, dp->link_nr); |
| 98 | |
Ben Skeggs | 8df1d0c | 2013-11-04 13:40:36 +1000 | [diff] [blame] | 99 | /* set desired link configuration on the sink */ |
| 100 | sink[0] = dp->link_bw / 27000; |
| 101 | sink[1] = dp->link_nr; |
Ben Skeggs | 3b52a1f | 2014-05-19 14:06:07 +1000 | [diff] [blame] | 102 | if (outp->dpcd[DPCD_RC02] & DPCD_RC02_ENHANCED_FRAME_CAP) |
Ben Skeggs | 8df1d0c | 2013-11-04 13:40:36 +1000 | [diff] [blame] | 103 | sink[1] |= DPCD_LC01_ENHANCED_FRAME_EN; |
| 104 | |
Ben Skeggs | 55f083c | 2014-05-20 10:18:03 +1000 | [diff] [blame] | 105 | return nv_wraux(outp->base.edid, DPCD_LC00_LINK_BW_SET, sink, 2); |
Ben Skeggs | 0a0afd2 | 2013-02-18 23:17:53 -0500 | [diff] [blame] | 106 | } |
| 107 | |
| 108 | static void |
| 109 | dp_set_training_pattern(struct dp_state *dp, u8 pattern) |
| 110 | { |
Ben Skeggs | 3b52a1f | 2014-05-19 14:06:07 +1000 | [diff] [blame] | 111 | struct nvkm_output_dp_impl *impl = (void *)nv_oclass(dp->outp); |
| 112 | struct nvkm_output_dp *outp = dp->outp; |
Ben Skeggs | 0a0afd2 | 2013-02-18 23:17:53 -0500 | [diff] [blame] | 113 | u8 sink_tp; |
| 114 | |
| 115 | DBG("training pattern %d\n", pattern); |
Ben Skeggs | 3b52a1f | 2014-05-19 14:06:07 +1000 | [diff] [blame] | 116 | impl->pattern(outp, pattern); |
Ben Skeggs | 0a0afd2 | 2013-02-18 23:17:53 -0500 | [diff] [blame] | 117 | |
Ben Skeggs | 3b52a1f | 2014-05-19 14:06:07 +1000 | [diff] [blame] | 118 | nv_rdaux(outp->base.edid, DPCD_LC02, &sink_tp, 1); |
Ben Skeggs | 0a0afd2 | 2013-02-18 23:17:53 -0500 | [diff] [blame] | 119 | sink_tp &= ~DPCD_LC02_TRAINING_PATTERN_SET; |
| 120 | sink_tp |= pattern; |
Ben Skeggs | 3b52a1f | 2014-05-19 14:06:07 +1000 | [diff] [blame] | 121 | nv_wraux(outp->base.edid, DPCD_LC02, &sink_tp, 1); |
Ben Skeggs | 0a0afd2 | 2013-02-18 23:17:53 -0500 | [diff] [blame] | 122 | } |
| 123 | |
| 124 | static int |
Ben Skeggs | 04e7e92 | 2014-05-15 22:20:40 +1000 | [diff] [blame] | 125 | dp_link_train_commit(struct dp_state *dp, bool pc) |
Ben Skeggs | 0a0afd2 | 2013-02-18 23:17:53 -0500 | [diff] [blame] | 126 | { |
Ben Skeggs | 3b52a1f | 2014-05-19 14:06:07 +1000 | [diff] [blame] | 127 | struct nvkm_output_dp_impl *impl = (void *)nv_oclass(dp->outp); |
| 128 | struct nvkm_output_dp *outp = dp->outp; |
Ben Skeggs | 04e7e92 | 2014-05-15 22:20:40 +1000 | [diff] [blame] | 129 | int ret, i; |
Ben Skeggs | 0a0afd2 | 2013-02-18 23:17:53 -0500 | [diff] [blame] | 130 | |
| 131 | for (i = 0; i < dp->link_nr; i++) { |
| 132 | u8 lane = (dp->stat[4 + (i >> 1)] >> ((i & 1) * 4)) & 0xf; |
Ben Skeggs | c33ba68 | 2014-06-03 14:48:18 +1000 | [diff] [blame] | 133 | u8 lpc2 = (dp->pc2stat >> (i * 2)) & 0x3; |
Ben Skeggs | 0a0afd2 | 2013-02-18 23:17:53 -0500 | [diff] [blame] | 134 | u8 lpre = (lane & 0x0c) >> 2; |
| 135 | u8 lvsw = (lane & 0x03) >> 0; |
Ben Skeggs | c33ba68 | 2014-06-03 14:48:18 +1000 | [diff] [blame] | 136 | u8 hivs = 3 - lpre; |
| 137 | u8 hipe = 3; |
| 138 | u8 hipc = 3; |
| 139 | |
| 140 | if (lpc2 >= hipc) |
| 141 | lpc2 = hipc | DPCD_LC0F_LANE0_MAX_POST_CURSOR2_REACHED; |
| 142 | if (lpre >= hipe) { |
| 143 | lpre = hipe | DPCD_LC03_MAX_SWING_REACHED; /* yes. */ |
| 144 | lvsw = hivs = 3 - (lpre & 3); |
| 145 | } else |
| 146 | if (lvsw >= hivs) { |
| 147 | lvsw = hivs | DPCD_LC03_MAX_SWING_REACHED; |
| 148 | } |
Ben Skeggs | 0a0afd2 | 2013-02-18 23:17:53 -0500 | [diff] [blame] | 149 | |
| 150 | dp->conf[i] = (lpre << 3) | lvsw; |
Ben Skeggs | c33ba68 | 2014-06-03 14:48:18 +1000 | [diff] [blame] | 151 | dp->pc2conf[i >> 1] |= lpc2 << ((i & 1) * 4); |
Ben Skeggs | 0a0afd2 | 2013-02-18 23:17:53 -0500 | [diff] [blame] | 152 | |
Ben Skeggs | c33ba68 | 2014-06-03 14:48:18 +1000 | [diff] [blame] | 153 | DBG("config lane %d %02x %02x\n", i, dp->conf[i], lpc2); |
| 154 | impl->drv_ctl(outp, i, lvsw & 3, lpre & 3, lpc2 & 3); |
Ben Skeggs | 0a0afd2 | 2013-02-18 23:17:53 -0500 | [diff] [blame] | 155 | } |
| 156 | |
Ben Skeggs | 3b52a1f | 2014-05-19 14:06:07 +1000 | [diff] [blame] | 157 | ret = nv_wraux(outp->base.edid, DPCD_LC03(0), dp->conf, 4); |
Ben Skeggs | 04e7e92 | 2014-05-15 22:20:40 +1000 | [diff] [blame] | 158 | if (ret) |
| 159 | return ret; |
| 160 | |
| 161 | if (pc) { |
Ben Skeggs | 3b52a1f | 2014-05-19 14:06:07 +1000 | [diff] [blame] | 162 | ret = nv_wraux(outp->base.edid, DPCD_LC0F, dp->pc2conf, 2); |
Ben Skeggs | 04e7e92 | 2014-05-15 22:20:40 +1000 | [diff] [blame] | 163 | if (ret) |
| 164 | return ret; |
| 165 | } |
| 166 | |
| 167 | return 0; |
Ben Skeggs | 0a0afd2 | 2013-02-18 23:17:53 -0500 | [diff] [blame] | 168 | } |
| 169 | |
| 170 | static int |
Ben Skeggs | 04e7e92 | 2014-05-15 22:20:40 +1000 | [diff] [blame] | 171 | dp_link_train_update(struct dp_state *dp, bool pc, u32 delay) |
Ben Skeggs | 0a0afd2 | 2013-02-18 23:17:53 -0500 | [diff] [blame] | 172 | { |
Ben Skeggs | 3b52a1f | 2014-05-19 14:06:07 +1000 | [diff] [blame] | 173 | struct nvkm_output_dp *outp = dp->outp; |
Ben Skeggs | 0a0afd2 | 2013-02-18 23:17:53 -0500 | [diff] [blame] | 174 | int ret; |
| 175 | |
Ben Skeggs | 3b52a1f | 2014-05-19 14:06:07 +1000 | [diff] [blame] | 176 | if (outp->dpcd[DPCD_RC0E_AUX_RD_INTERVAL]) |
| 177 | mdelay(outp->dpcd[DPCD_RC0E_AUX_RD_INTERVAL] * 4); |
Ben Skeggs | fb7c2a7 | 2014-05-15 21:50:07 +1000 | [diff] [blame] | 178 | else |
| 179 | udelay(delay); |
Ben Skeggs | 0a0afd2 | 2013-02-18 23:17:53 -0500 | [diff] [blame] | 180 | |
Ben Skeggs | 3b52a1f | 2014-05-19 14:06:07 +1000 | [diff] [blame] | 181 | ret = nv_rdaux(outp->base.edid, DPCD_LS02, dp->stat, 6); |
Ben Skeggs | 0a0afd2 | 2013-02-18 23:17:53 -0500 | [diff] [blame] | 182 | if (ret) |
| 183 | return ret; |
| 184 | |
Ben Skeggs | 04e7e92 | 2014-05-15 22:20:40 +1000 | [diff] [blame] | 185 | if (pc) { |
Ben Skeggs | 3b52a1f | 2014-05-19 14:06:07 +1000 | [diff] [blame] | 186 | ret = nv_rdaux(outp->base.edid, DPCD_LS0C, &dp->pc2stat, 1); |
Ben Skeggs | 04e7e92 | 2014-05-15 22:20:40 +1000 | [diff] [blame] | 187 | if (ret) |
| 188 | dp->pc2stat = 0x00; |
| 189 | DBG("status %6ph pc2 %02x\n", dp->stat, dp->pc2stat); |
| 190 | } else { |
| 191 | DBG("status %6ph\n", dp->stat); |
| 192 | } |
| 193 | |
Ben Skeggs | 0a0afd2 | 2013-02-18 23:17:53 -0500 | [diff] [blame] | 194 | return 0; |
| 195 | } |
| 196 | |
| 197 | static int |
| 198 | dp_link_train_cr(struct dp_state *dp) |
| 199 | { |
| 200 | bool cr_done = false, abort = false; |
| 201 | int voltage = dp->conf[0] & DPCD_LC03_VOLTAGE_SWING_SET; |
| 202 | int tries = 0, i; |
| 203 | |
| 204 | dp_set_training_pattern(dp, 1); |
| 205 | |
| 206 | do { |
Ben Skeggs | 04e7e92 | 2014-05-15 22:20:40 +1000 | [diff] [blame] | 207 | if (dp_link_train_commit(dp, false) || |
| 208 | dp_link_train_update(dp, false, 100)) |
Ben Skeggs | 0a0afd2 | 2013-02-18 23:17:53 -0500 | [diff] [blame] | 209 | break; |
| 210 | |
| 211 | cr_done = true; |
| 212 | for (i = 0; i < dp->link_nr; i++) { |
| 213 | u8 lane = (dp->stat[i >> 1] >> ((i & 1) * 4)) & 0xf; |
| 214 | if (!(lane & DPCD_LS02_LANE0_CR_DONE)) { |
| 215 | cr_done = false; |
| 216 | if (dp->conf[i] & DPCD_LC03_MAX_SWING_REACHED) |
| 217 | abort = true; |
| 218 | break; |
| 219 | } |
| 220 | } |
| 221 | |
| 222 | if ((dp->conf[0] & DPCD_LC03_VOLTAGE_SWING_SET) != voltage) { |
| 223 | voltage = dp->conf[0] & DPCD_LC03_VOLTAGE_SWING_SET; |
| 224 | tries = 0; |
| 225 | } |
| 226 | } while (!cr_done && !abort && ++tries < 5); |
| 227 | |
| 228 | return cr_done ? 0 : -1; |
| 229 | } |
| 230 | |
| 231 | static int |
| 232 | dp_link_train_eq(struct dp_state *dp) |
| 233 | { |
Ben Skeggs | 3b52a1f | 2014-05-19 14:06:07 +1000 | [diff] [blame] | 234 | struct nvkm_output_dp *outp = dp->outp; |
Ben Skeggs | c5bd028 | 2013-04-11 10:12:48 +1000 | [diff] [blame] | 235 | bool eq_done = false, cr_done = true; |
Ben Skeggs | 0a0afd2 | 2013-02-18 23:17:53 -0500 | [diff] [blame] | 236 | int tries = 0, i; |
| 237 | |
Ben Skeggs | 3b52a1f | 2014-05-19 14:06:07 +1000 | [diff] [blame] | 238 | if (outp->dpcd[2] & DPCD_RC02_TPS3_SUPPORTED) |
Ben Skeggs | 6e8e268 | 2014-05-15 22:00:06 +1000 | [diff] [blame] | 239 | dp_set_training_pattern(dp, 3); |
| 240 | else |
| 241 | dp_set_training_pattern(dp, 2); |
Ben Skeggs | 0a0afd2 | 2013-02-18 23:17:53 -0500 | [diff] [blame] | 242 | |
| 243 | do { |
Ben Skeggs | cf7c5d6 | 2014-06-16 15:45:01 +1000 | [diff] [blame] | 244 | if ((tries && |
| 245 | dp_link_train_commit(dp, dp->pc2)) || |
| 246 | dp_link_train_update(dp, dp->pc2, 400)) |
Ben Skeggs | 0a0afd2 | 2013-02-18 23:17:53 -0500 | [diff] [blame] | 247 | break; |
| 248 | |
| 249 | eq_done = !!(dp->stat[2] & DPCD_LS04_INTERLANE_ALIGN_DONE); |
| 250 | for (i = 0; i < dp->link_nr && eq_done; i++) { |
| 251 | u8 lane = (dp->stat[i >> 1] >> ((i & 1) * 4)) & 0xf; |
| 252 | if (!(lane & DPCD_LS02_LANE0_CR_DONE)) |
| 253 | cr_done = false; |
| 254 | if (!(lane & DPCD_LS02_LANE0_CHANNEL_EQ_DONE) || |
| 255 | !(lane & DPCD_LS02_LANE0_SYMBOL_LOCKED)) |
| 256 | eq_done = false; |
| 257 | } |
Ben Skeggs | 0a0afd2 | 2013-02-18 23:17:53 -0500 | [diff] [blame] | 258 | } while (!eq_done && cr_done && ++tries <= 5); |
| 259 | |
| 260 | return eq_done ? 0 : -1; |
| 261 | } |
| 262 | |
| 263 | static void |
| 264 | dp_link_train_init(struct dp_state *dp, bool spread) |
| 265 | { |
Ben Skeggs | 3b52a1f | 2014-05-19 14:06:07 +1000 | [diff] [blame] | 266 | struct nvkm_output_dp *outp = dp->outp; |
| 267 | struct nouveau_disp *disp = nouveau_disp(outp); |
| 268 | struct nouveau_bios *bios = nouveau_bios(disp); |
Ben Skeggs | 0a0afd2 | 2013-02-18 23:17:53 -0500 | [diff] [blame] | 269 | struct nvbios_init init = { |
Ben Skeggs | 3b52a1f | 2014-05-19 14:06:07 +1000 | [diff] [blame] | 270 | .subdev = nv_subdev(disp), |
| 271 | .bios = bios, |
| 272 | .outp = &outp->base.info, |
| 273 | .crtc = -1, |
Ben Skeggs | 0a0afd2 | 2013-02-18 23:17:53 -0500 | [diff] [blame] | 274 | .execute = 1, |
| 275 | }; |
| 276 | |
| 277 | /* set desired spread */ |
| 278 | if (spread) |
Ben Skeggs | 3b52a1f | 2014-05-19 14:06:07 +1000 | [diff] [blame] | 279 | init.offset = outp->info.script[2]; |
Ben Skeggs | 0a0afd2 | 2013-02-18 23:17:53 -0500 | [diff] [blame] | 280 | else |
Ben Skeggs | 3b52a1f | 2014-05-19 14:06:07 +1000 | [diff] [blame] | 281 | init.offset = outp->info.script[3]; |
Ben Skeggs | 0a0afd2 | 2013-02-18 23:17:53 -0500 | [diff] [blame] | 282 | nvbios_exec(&init); |
| 283 | |
| 284 | /* pre-train script */ |
Ben Skeggs | 3b52a1f | 2014-05-19 14:06:07 +1000 | [diff] [blame] | 285 | init.offset = outp->info.script[0]; |
Ben Skeggs | 0a0afd2 | 2013-02-18 23:17:53 -0500 | [diff] [blame] | 286 | nvbios_exec(&init); |
| 287 | } |
| 288 | |
| 289 | static void |
| 290 | dp_link_train_fini(struct dp_state *dp) |
| 291 | { |
Ben Skeggs | 3b52a1f | 2014-05-19 14:06:07 +1000 | [diff] [blame] | 292 | struct nvkm_output_dp *outp = dp->outp; |
| 293 | struct nouveau_disp *disp = nouveau_disp(outp); |
| 294 | struct nouveau_bios *bios = nouveau_bios(disp); |
Ben Skeggs | 0a0afd2 | 2013-02-18 23:17:53 -0500 | [diff] [blame] | 295 | struct nvbios_init init = { |
Ben Skeggs | 3b52a1f | 2014-05-19 14:06:07 +1000 | [diff] [blame] | 296 | .subdev = nv_subdev(disp), |
| 297 | .bios = bios, |
| 298 | .outp = &outp->base.info, |
| 299 | .crtc = -1, |
Ben Skeggs | 0a0afd2 | 2013-02-18 23:17:53 -0500 | [diff] [blame] | 300 | .execute = 1, |
| 301 | }; |
| 302 | |
| 303 | /* post-train script */ |
Ben Skeggs | 3b52a1f | 2014-05-19 14:06:07 +1000 | [diff] [blame] | 304 | init.offset = outp->info.script[1], |
Ben Skeggs | 0a0afd2 | 2013-02-18 23:17:53 -0500 | [diff] [blame] | 305 | nvbios_exec(&init); |
| 306 | } |
| 307 | |
Ben Skeggs | 1f86ca1 | 2014-05-16 10:49:28 +1000 | [diff] [blame] | 308 | static const struct dp_rates { |
| 309 | u32 rate; |
| 310 | u8 bw; |
| 311 | u8 nr; |
| 312 | } nouveau_dp_rates[] = { |
| 313 | { 2160000, 0x14, 4 }, |
| 314 | { 1080000, 0x0a, 4 }, |
| 315 | { 1080000, 0x14, 2 }, |
| 316 | { 648000, 0x06, 4 }, |
| 317 | { 540000, 0x0a, 2 }, |
| 318 | { 540000, 0x14, 1 }, |
| 319 | { 324000, 0x06, 2 }, |
| 320 | { 270000, 0x0a, 1 }, |
| 321 | { 162000, 0x06, 1 }, |
| 322 | {} |
| 323 | }; |
| 324 | |
Ben Skeggs | 55f083c | 2014-05-20 10:18:03 +1000 | [diff] [blame] | 325 | void |
| 326 | nouveau_dp_train(struct work_struct *w) |
Ben Skeggs | 0a0afd2 | 2013-02-18 23:17:53 -0500 | [diff] [blame] | 327 | { |
Ben Skeggs | 55f083c | 2014-05-20 10:18:03 +1000 | [diff] [blame] | 328 | struct nvkm_output_dp *outp = container_of(w, typeof(*outp), lt.work); |
Ben Skeggs | 3b52a1f | 2014-05-19 14:06:07 +1000 | [diff] [blame] | 329 | struct nouveau_disp *disp = nouveau_disp(outp); |
Ben Skeggs | 1f86ca1 | 2014-05-16 10:49:28 +1000 | [diff] [blame] | 330 | const struct dp_rates *cfg = nouveau_dp_rates; |
Ben Skeggs | 0a0afd2 | 2013-02-18 23:17:53 -0500 | [diff] [blame] | 331 | struct dp_state _dp = { |
Ben Skeggs | 0a0afd2 | 2013-02-18 23:17:53 -0500 | [diff] [blame] | 332 | .outp = outp, |
Ben Skeggs | 0a0afd2 | 2013-02-18 23:17:53 -0500 | [diff] [blame] | 333 | }, *dp = &_dp; |
Ben Skeggs | 55f083c | 2014-05-20 10:18:03 +1000 | [diff] [blame] | 334 | u32 datarate = 0; |
Ben Skeggs | 0a0afd2 | 2013-02-18 23:17:53 -0500 | [diff] [blame] | 335 | int ret; |
| 336 | |
Ben Skeggs | fc243d7 | 2014-03-20 09:28:00 +1000 | [diff] [blame] | 337 | /* bring capabilities within encoder limits */ |
Ben Skeggs | 04e7e92 | 2014-05-15 22:20:40 +1000 | [diff] [blame] | 338 | if (nv_mclass(disp) < NVD0_DISP_CLASS) |
Ben Skeggs | 3b52a1f | 2014-05-19 14:06:07 +1000 | [diff] [blame] | 339 | outp->dpcd[2] &= ~DPCD_RC02_TPS3_SUPPORTED; |
| 340 | if ((outp->dpcd[2] & 0x1f) > outp->base.info.dpconf.link_nr) { |
| 341 | outp->dpcd[2] &= ~DPCD_RC02_MAX_LANE_COUNT; |
| 342 | outp->dpcd[2] |= outp->base.info.dpconf.link_nr; |
Ben Skeggs | fc243d7 | 2014-03-20 09:28:00 +1000 | [diff] [blame] | 343 | } |
Ben Skeggs | 3b52a1f | 2014-05-19 14:06:07 +1000 | [diff] [blame] | 344 | if (outp->dpcd[1] > outp->base.info.dpconf.link_bw) |
| 345 | outp->dpcd[1] = outp->base.info.dpconf.link_bw; |
| 346 | dp->pc2 = outp->dpcd[2] & DPCD_RC02_TPS3_SUPPORTED; |
Ben Skeggs | fc243d7 | 2014-03-20 09:28:00 +1000 | [diff] [blame] | 347 | |
Ben Skeggs | 1f86ca1 | 2014-05-16 10:49:28 +1000 | [diff] [blame] | 348 | /* restrict link config to the lowest required rate, if requested */ |
| 349 | if (datarate) { |
| 350 | datarate = (datarate / 8) * 10; /* 8B/10B coding overhead */ |
| 351 | while (cfg[1].rate >= datarate) |
| 352 | cfg++; |
| 353 | } |
| 354 | cfg--; |
Ben Skeggs | 0a0afd2 | 2013-02-18 23:17:53 -0500 | [diff] [blame] | 355 | |
Ben Skeggs | 55f083c | 2014-05-20 10:18:03 +1000 | [diff] [blame] | 356 | /* disable link interrupt handling during link training */ |
Ben Skeggs | 79ca277 | 2014-08-10 04:10:20 +1000 | [diff] [blame^] | 357 | nvkm_notify_put(&outp->irq); |
Ben Skeggs | 55f083c | 2014-05-20 10:18:03 +1000 | [diff] [blame] | 358 | |
Ben Skeggs | 0a0afd2 | 2013-02-18 23:17:53 -0500 | [diff] [blame] | 359 | /* enable down-spreading and execute pre-train script from vbios */ |
Ben Skeggs | 3b52a1f | 2014-05-19 14:06:07 +1000 | [diff] [blame] | 360 | dp_link_train_init(dp, outp->dpcd[3] & 0x01); |
Ben Skeggs | 0a0afd2 | 2013-02-18 23:17:53 -0500 | [diff] [blame] | 361 | |
Ben Skeggs | 1f86ca1 | 2014-05-16 10:49:28 +1000 | [diff] [blame] | 362 | while (ret = -EIO, (++cfg)->rate) { |
| 363 | /* select next configuration supported by encoder and sink */ |
Ben Skeggs | 3b52a1f | 2014-05-19 14:06:07 +1000 | [diff] [blame] | 364 | while (cfg->nr > (outp->dpcd[2] & DPCD_RC02_MAX_LANE_COUNT) || |
| 365 | cfg->bw > (outp->dpcd[DPCD_RC01_MAX_LINK_RATE])) |
Ben Skeggs | 1f86ca1 | 2014-05-16 10:49:28 +1000 | [diff] [blame] | 366 | cfg++; |
| 367 | dp->link_bw = cfg->bw * 27000; |
| 368 | dp->link_nr = cfg->nr; |
Ben Skeggs | 0a0afd2 | 2013-02-18 23:17:53 -0500 | [diff] [blame] | 369 | |
| 370 | /* program selected link configuration */ |
| 371 | ret = dp_set_link_config(dp); |
| 372 | if (ret == 0) { |
| 373 | /* attempt to train the link at this configuration */ |
| 374 | memset(dp->stat, 0x00, sizeof(dp->stat)); |
| 375 | if (!dp_link_train_cr(dp) && |
| 376 | !dp_link_train_eq(dp)) |
| 377 | break; |
| 378 | } else |
Ben Skeggs | 8df1d0c | 2013-11-04 13:40:36 +1000 | [diff] [blame] | 379 | if (ret) { |
| 380 | /* dp_set_link_config() handled training, or |
| 381 | * we failed to communicate with the sink. |
| 382 | */ |
Ben Skeggs | 0a0afd2 | 2013-02-18 23:17:53 -0500 | [diff] [blame] | 383 | break; |
| 384 | } |
Ben Skeggs | 0a0afd2 | 2013-02-18 23:17:53 -0500 | [diff] [blame] | 385 | } |
| 386 | |
Ben Skeggs | 55f083c | 2014-05-20 10:18:03 +1000 | [diff] [blame] | 387 | /* finish link training and execute post-train script from vbios */ |
Ben Skeggs | 0a0afd2 | 2013-02-18 23:17:53 -0500 | [diff] [blame] | 388 | dp_set_training_pattern(dp, 0); |
Ben Skeggs | 687d8f6 | 2013-11-01 09:36:42 +1000 | [diff] [blame] | 389 | if (ret < 0) |
| 390 | ERR("link training failed\n"); |
Ben Skeggs | 0a0afd2 | 2013-02-18 23:17:53 -0500 | [diff] [blame] | 391 | |
Ben Skeggs | 0a0afd2 | 2013-02-18 23:17:53 -0500 | [diff] [blame] | 392 | dp_link_train_fini(dp); |
Ben Skeggs | 55f083c | 2014-05-20 10:18:03 +1000 | [diff] [blame] | 393 | |
| 394 | /* signal completion and enable link interrupt handling */ |
| 395 | DBG("training complete\n"); |
| 396 | atomic_set(&outp->lt.done, 1); |
| 397 | wake_up(&outp->lt.wait); |
Ben Skeggs | 79ca277 | 2014-08-10 04:10:20 +1000 | [diff] [blame^] | 398 | nvkm_notify_get(&outp->irq); |
Ben Skeggs | 0a0afd2 | 2013-02-18 23:17:53 -0500 | [diff] [blame] | 399 | } |