Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2012 Red Hat Inc. |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice shall be included in |
| 12 | * all copies or substantial portions of the Software. |
| 13 | * |
| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 20 | * OTHER DEALINGS IN THE SOFTWARE. |
| 21 | * |
| 22 | * Authors: Ben Skeggs |
| 23 | */ |
| 24 | |
Ben Skeggs | 370c00f | 2012-08-14 14:11:49 +1000 | [diff] [blame] | 25 | #include <core/object.h> |
| 26 | #include <core/parent.h> |
| 27 | #include <core/handle.h> |
| 28 | #include <core/class.h> |
Ben Skeggs | 117e1633 | 2014-02-21 11:06:40 +1000 | [diff] [blame] | 29 | #include <core/enum.h> |
Ben Skeggs | 370c00f | 2012-08-14 14:11:49 +1000 | [diff] [blame] | 30 | |
Ben Skeggs | 186ecad | 2012-11-09 12:09:48 +1000 | [diff] [blame] | 31 | #include <subdev/bios.h> |
| 32 | #include <subdev/bios/dcb.h> |
| 33 | #include <subdev/bios/disp.h> |
| 34 | #include <subdev/bios/init.h> |
| 35 | #include <subdev/bios/pll.h> |
Ben Skeggs | 88524bc | 2013-03-05 10:53:54 +1000 | [diff] [blame] | 36 | #include <subdev/devinit.h> |
Ben Skeggs | 446b05a | 2012-08-14 12:50:14 +1000 | [diff] [blame] | 37 | #include <subdev/timer.h> |
Ben Skeggs | 370c00f | 2012-08-14 14:11:49 +1000 | [diff] [blame] | 38 | #include <subdev/fb.h> |
Ben Skeggs | 446b05a | 2012-08-14 12:50:14 +1000 | [diff] [blame] | 39 | |
Ben Skeggs | 70cabe4 | 2012-08-14 10:04:04 +1000 | [diff] [blame] | 40 | #include "nv50.h" |
| 41 | |
| 42 | /******************************************************************************* |
Ben Skeggs | 370c00f | 2012-08-14 14:11:49 +1000 | [diff] [blame] | 43 | * EVO channel base class |
Ben Skeggs | 70cabe4 | 2012-08-14 10:04:04 +1000 | [diff] [blame] | 44 | ******************************************************************************/ |
| 45 | |
Ben Skeggs | 370c00f | 2012-08-14 14:11:49 +1000 | [diff] [blame] | 46 | int |
| 47 | nv50_disp_chan_create_(struct nouveau_object *parent, |
| 48 | struct nouveau_object *engine, |
| 49 | struct nouveau_oclass *oclass, int chid, |
| 50 | int length, void **pobject) |
| 51 | { |
| 52 | struct nv50_disp_base *base = (void *)parent; |
| 53 | struct nv50_disp_chan *chan; |
| 54 | int ret; |
| 55 | |
| 56 | if (base->chan & (1 << chid)) |
| 57 | return -EBUSY; |
| 58 | base->chan |= (1 << chid); |
| 59 | |
| 60 | ret = nouveau_namedb_create_(parent, engine, oclass, 0, NULL, |
| 61 | (1ULL << NVDEV_ENGINE_DMAOBJ), |
| 62 | length, pobject); |
| 63 | chan = *pobject; |
| 64 | if (ret) |
| 65 | return ret; |
| 66 | |
| 67 | chan->chid = chid; |
| 68 | return 0; |
| 69 | } |
| 70 | |
| 71 | void |
| 72 | nv50_disp_chan_destroy(struct nv50_disp_chan *chan) |
| 73 | { |
| 74 | struct nv50_disp_base *base = (void *)nv_object(chan)->parent; |
| 75 | base->chan &= ~(1 << chan->chid); |
| 76 | nouveau_namedb_destroy(&chan->base); |
| 77 | } |
| 78 | |
| 79 | u32 |
Ben Skeggs | 70cabe4 | 2012-08-14 10:04:04 +1000 | [diff] [blame] | 80 | nv50_disp_chan_rd32(struct nouveau_object *object, u64 addr) |
| 81 | { |
Ben Skeggs | 370c00f | 2012-08-14 14:11:49 +1000 | [diff] [blame] | 82 | struct nv50_disp_priv *priv = (void *)object->engine; |
| 83 | struct nv50_disp_chan *chan = (void *)object; |
| 84 | return nv_rd32(priv, 0x640000 + (chan->chid * 0x1000) + addr); |
| 85 | } |
| 86 | |
| 87 | void |
| 88 | nv50_disp_chan_wr32(struct nouveau_object *object, u64 addr, u32 data) |
| 89 | { |
| 90 | struct nv50_disp_priv *priv = (void *)object->engine; |
| 91 | struct nv50_disp_chan *chan = (void *)object; |
| 92 | nv_wr32(priv, 0x640000 + (chan->chid * 0x1000) + addr, data); |
| 93 | } |
| 94 | |
| 95 | /******************************************************************************* |
| 96 | * EVO DMA channel base class |
| 97 | ******************************************************************************/ |
| 98 | |
| 99 | static int |
| 100 | nv50_disp_dmac_object_attach(struct nouveau_object *parent, |
| 101 | struct nouveau_object *object, u32 name) |
| 102 | { |
| 103 | struct nv50_disp_base *base = (void *)parent->parent; |
| 104 | struct nv50_disp_chan *chan = (void *)parent; |
| 105 | u32 addr = nv_gpuobj(object)->node->offset; |
| 106 | u32 chid = chan->chid; |
| 107 | u32 data = (chid << 28) | (addr << 10) | chid; |
| 108 | return nouveau_ramht_insert(base->ramht, chid, name, data); |
Ben Skeggs | 70cabe4 | 2012-08-14 10:04:04 +1000 | [diff] [blame] | 109 | } |
| 110 | |
| 111 | static void |
Ben Skeggs | 370c00f | 2012-08-14 14:11:49 +1000 | [diff] [blame] | 112 | nv50_disp_dmac_object_detach(struct nouveau_object *parent, int cookie) |
Ben Skeggs | 70cabe4 | 2012-08-14 10:04:04 +1000 | [diff] [blame] | 113 | { |
Ben Skeggs | 370c00f | 2012-08-14 14:11:49 +1000 | [diff] [blame] | 114 | struct nv50_disp_base *base = (void *)parent->parent; |
| 115 | nouveau_ramht_remove(base->ramht, cookie); |
| 116 | } |
| 117 | |
| 118 | int |
| 119 | nv50_disp_dmac_create_(struct nouveau_object *parent, |
| 120 | struct nouveau_object *engine, |
| 121 | struct nouveau_oclass *oclass, u32 pushbuf, int chid, |
| 122 | int length, void **pobject) |
| 123 | { |
| 124 | struct nv50_disp_dmac *dmac; |
| 125 | int ret; |
| 126 | |
| 127 | ret = nv50_disp_chan_create_(parent, engine, oclass, chid, |
| 128 | length, pobject); |
| 129 | dmac = *pobject; |
| 130 | if (ret) |
| 131 | return ret; |
| 132 | |
| 133 | dmac->pushdma = (void *)nouveau_handle_ref(parent, pushbuf); |
| 134 | if (!dmac->pushdma) |
| 135 | return -ENOENT; |
| 136 | |
| 137 | switch (nv_mclass(dmac->pushdma)) { |
| 138 | case 0x0002: |
| 139 | case 0x003d: |
| 140 | if (dmac->pushdma->limit - dmac->pushdma->start != 0xfff) |
| 141 | return -EINVAL; |
| 142 | |
| 143 | switch (dmac->pushdma->target) { |
| 144 | case NV_MEM_TARGET_VRAM: |
| 145 | dmac->push = 0x00000000 | dmac->pushdma->start >> 8; |
| 146 | break; |
Ben Skeggs | 944234d | 2012-10-30 10:03:38 +1000 | [diff] [blame] | 147 | case NV_MEM_TARGET_PCI_NOSNOOP: |
| 148 | dmac->push = 0x00000003 | dmac->pushdma->start >> 8; |
| 149 | break; |
Ben Skeggs | 370c00f | 2012-08-14 14:11:49 +1000 | [diff] [blame] | 150 | default: |
| 151 | return -EINVAL; |
| 152 | } |
| 153 | break; |
| 154 | default: |
| 155 | return -EINVAL; |
| 156 | } |
| 157 | |
| 158 | return 0; |
| 159 | } |
| 160 | |
| 161 | void |
| 162 | nv50_disp_dmac_dtor(struct nouveau_object *object) |
| 163 | { |
| 164 | struct nv50_disp_dmac *dmac = (void *)object; |
| 165 | nouveau_object_ref(NULL, (struct nouveau_object **)&dmac->pushdma); |
| 166 | nv50_disp_chan_destroy(&dmac->base); |
| 167 | } |
| 168 | |
| 169 | static int |
| 170 | nv50_disp_dmac_init(struct nouveau_object *object) |
| 171 | { |
| 172 | struct nv50_disp_priv *priv = (void *)object->engine; |
| 173 | struct nv50_disp_dmac *dmac = (void *)object; |
| 174 | int chid = dmac->base.chid; |
| 175 | int ret; |
| 176 | |
| 177 | ret = nv50_disp_chan_init(&dmac->base); |
| 178 | if (ret) |
| 179 | return ret; |
| 180 | |
| 181 | /* enable error reporting */ |
| 182 | nv_mask(priv, 0x610028, 0x00010001 << chid, 0x00010001 << chid); |
| 183 | |
| 184 | /* initialise channel for dma command submission */ |
| 185 | nv_wr32(priv, 0x610204 + (chid * 0x0010), dmac->push); |
| 186 | nv_wr32(priv, 0x610208 + (chid * 0x0010), 0x00010000); |
| 187 | nv_wr32(priv, 0x61020c + (chid * 0x0010), chid); |
| 188 | nv_mask(priv, 0x610200 + (chid * 0x0010), 0x00000010, 0x00000010); |
| 189 | nv_wr32(priv, 0x640000 + (chid * 0x1000), 0x00000000); |
| 190 | nv_wr32(priv, 0x610200 + (chid * 0x0010), 0x00000013); |
| 191 | |
| 192 | /* wait for it to go inactive */ |
| 193 | if (!nv_wait(priv, 0x610200 + (chid * 0x10), 0x80000000, 0x00000000)) { |
| 194 | nv_error(dmac, "init timeout, 0x%08x\n", |
| 195 | nv_rd32(priv, 0x610200 + (chid * 0x10))); |
| 196 | return -EBUSY; |
| 197 | } |
| 198 | |
| 199 | return 0; |
| 200 | } |
| 201 | |
| 202 | static int |
| 203 | nv50_disp_dmac_fini(struct nouveau_object *object, bool suspend) |
| 204 | { |
| 205 | struct nv50_disp_priv *priv = (void *)object->engine; |
| 206 | struct nv50_disp_dmac *dmac = (void *)object; |
| 207 | int chid = dmac->base.chid; |
| 208 | |
| 209 | /* deactivate channel */ |
| 210 | nv_mask(priv, 0x610200 + (chid * 0x0010), 0x00001010, 0x00001000); |
| 211 | nv_mask(priv, 0x610200 + (chid * 0x0010), 0x00000003, 0x00000000); |
| 212 | if (!nv_wait(priv, 0x610200 + (chid * 0x10), 0x001e0000, 0x00000000)) { |
| 213 | nv_error(dmac, "fini timeout, 0x%08x\n", |
| 214 | nv_rd32(priv, 0x610200 + (chid * 0x10))); |
| 215 | if (suspend) |
| 216 | return -EBUSY; |
| 217 | } |
| 218 | |
| 219 | /* disable error reporting */ |
| 220 | nv_mask(priv, 0x610028, 0x00010001 << chid, 0x00000000 << chid); |
| 221 | |
| 222 | return nv50_disp_chan_fini(&dmac->base, suspend); |
Ben Skeggs | 70cabe4 | 2012-08-14 10:04:04 +1000 | [diff] [blame] | 223 | } |
| 224 | |
| 225 | /******************************************************************************* |
| 226 | * EVO master channel object |
| 227 | ******************************************************************************/ |
| 228 | |
Ben Skeggs | d67d92c | 2014-02-20 15:14:10 +1000 | [diff] [blame] | 229 | static void |
| 230 | nv50_disp_mthd_list(struct nv50_disp_priv *priv, int debug, u32 base, int c, |
| 231 | const struct nv50_disp_mthd_list *list, int inst) |
| 232 | { |
| 233 | struct nouveau_object *disp = nv_object(priv); |
| 234 | int i; |
| 235 | |
| 236 | for (i = 0; list->data[i].mthd; i++) { |
| 237 | if (list->data[i].addr) { |
| 238 | u32 next = nv_rd32(priv, list->data[i].addr + base + 0); |
| 239 | u32 prev = nv_rd32(priv, list->data[i].addr + base + c); |
| 240 | u32 mthd = list->data[i].mthd + (list->mthd * inst); |
| 241 | const char *name = list->data[i].name; |
| 242 | char mods[16]; |
| 243 | |
| 244 | if (prev != next) |
| 245 | snprintf(mods, sizeof(mods), "-> 0x%08x", next); |
| 246 | else |
| 247 | snprintf(mods, sizeof(mods), "%13c", ' '); |
| 248 | |
| 249 | nv_printk_(disp, debug, "\t0x%04x: 0x%08x %s%s%s\n", |
| 250 | mthd, prev, mods, name ? " // " : "", |
| 251 | name ? name : ""); |
| 252 | } |
| 253 | } |
| 254 | } |
| 255 | |
| 256 | void |
| 257 | nv50_disp_mthd_chan(struct nv50_disp_priv *priv, int debug, int head, |
| 258 | const struct nv50_disp_mthd_chan *chan) |
| 259 | { |
| 260 | struct nouveau_object *disp = nv_object(priv); |
| 261 | const struct nv50_disp_impl *impl = (void *)disp->oclass; |
| 262 | const struct nv50_disp_mthd_list *list; |
| 263 | int i, j; |
| 264 | |
| 265 | if (debug > nv_subdev(priv)->debug) |
| 266 | return; |
| 267 | |
| 268 | for (i = 0; (list = chan->data[i].mthd) != NULL; i++) { |
| 269 | u32 base = head * chan->addr; |
| 270 | for (j = 0; j < chan->data[i].nr; j++, base += list->addr) { |
| 271 | const char *cname = chan->name; |
| 272 | const char *sname = ""; |
| 273 | char cname_[16], sname_[16]; |
| 274 | |
| 275 | if (chan->addr) { |
| 276 | snprintf(cname_, sizeof(cname_), "%s %d", |
| 277 | chan->name, head); |
| 278 | cname = cname_; |
| 279 | } |
| 280 | |
| 281 | if (chan->data[i].nr > 1) { |
| 282 | snprintf(sname_, sizeof(sname_), " - %s %d", |
| 283 | chan->data[i].name, j); |
| 284 | sname = sname_; |
| 285 | } |
| 286 | |
| 287 | nv_printk_(disp, debug, "%s%s:\n", cname, sname); |
| 288 | nv50_disp_mthd_list(priv, debug, base, impl->mthd.prev, |
| 289 | list, j); |
| 290 | } |
| 291 | } |
| 292 | } |
| 293 | |
| 294 | const struct nv50_disp_mthd_list |
| 295 | nv50_disp_mast_mthd_base = { |
| 296 | .mthd = 0x0000, |
| 297 | .addr = 0x000000, |
| 298 | .data = { |
| 299 | { 0x0080, 0x000000 }, |
| 300 | { 0x0084, 0x610bb8 }, |
| 301 | { 0x0088, 0x610b9c }, |
| 302 | { 0x008c, 0x000000 }, |
| 303 | {} |
| 304 | } |
| 305 | }; |
| 306 | |
| 307 | static const struct nv50_disp_mthd_list |
| 308 | nv50_disp_mast_mthd_dac = { |
| 309 | .mthd = 0x0080, |
| 310 | .addr = 0x000008, |
| 311 | .data = { |
| 312 | { 0x0400, 0x610b58 }, |
| 313 | { 0x0404, 0x610bdc }, |
| 314 | { 0x0420, 0x610828 }, |
| 315 | {} |
| 316 | } |
| 317 | }; |
| 318 | |
| 319 | const struct nv50_disp_mthd_list |
| 320 | nv50_disp_mast_mthd_sor = { |
| 321 | .mthd = 0x0040, |
| 322 | .addr = 0x000008, |
| 323 | .data = { |
| 324 | { 0x0600, 0x610b70 }, |
| 325 | {} |
| 326 | } |
| 327 | }; |
| 328 | |
| 329 | const struct nv50_disp_mthd_list |
| 330 | nv50_disp_mast_mthd_pior = { |
| 331 | .mthd = 0x0040, |
| 332 | .addr = 0x000008, |
| 333 | .data = { |
| 334 | { 0x0700, 0x610b80 }, |
| 335 | {} |
| 336 | } |
| 337 | }; |
| 338 | |
| 339 | static const struct nv50_disp_mthd_list |
| 340 | nv50_disp_mast_mthd_head = { |
| 341 | .mthd = 0x0400, |
| 342 | .addr = 0x000540, |
| 343 | .data = { |
| 344 | { 0x0800, 0x610ad8 }, |
| 345 | { 0x0804, 0x610ad0 }, |
| 346 | { 0x0808, 0x610a48 }, |
| 347 | { 0x080c, 0x610a78 }, |
| 348 | { 0x0810, 0x610ac0 }, |
| 349 | { 0x0814, 0x610af8 }, |
| 350 | { 0x0818, 0x610b00 }, |
| 351 | { 0x081c, 0x610ae8 }, |
| 352 | { 0x0820, 0x610af0 }, |
| 353 | { 0x0824, 0x610b08 }, |
| 354 | { 0x0828, 0x610b10 }, |
| 355 | { 0x082c, 0x610a68 }, |
| 356 | { 0x0830, 0x610a60 }, |
| 357 | { 0x0834, 0x000000 }, |
| 358 | { 0x0838, 0x610a40 }, |
| 359 | { 0x0840, 0x610a24 }, |
| 360 | { 0x0844, 0x610a2c }, |
| 361 | { 0x0848, 0x610aa8 }, |
| 362 | { 0x084c, 0x610ab0 }, |
| 363 | { 0x0860, 0x610a84 }, |
| 364 | { 0x0864, 0x610a90 }, |
| 365 | { 0x0868, 0x610b18 }, |
| 366 | { 0x086c, 0x610b20 }, |
| 367 | { 0x0870, 0x610ac8 }, |
| 368 | { 0x0874, 0x610a38 }, |
| 369 | { 0x0880, 0x610a58 }, |
| 370 | { 0x0884, 0x610a9c }, |
| 371 | { 0x08a0, 0x610a70 }, |
| 372 | { 0x08a4, 0x610a50 }, |
| 373 | { 0x08a8, 0x610ae0 }, |
| 374 | { 0x08c0, 0x610b28 }, |
| 375 | { 0x08c4, 0x610b30 }, |
| 376 | { 0x08c8, 0x610b40 }, |
| 377 | { 0x08d4, 0x610b38 }, |
| 378 | { 0x08d8, 0x610b48 }, |
| 379 | { 0x08dc, 0x610b50 }, |
| 380 | { 0x0900, 0x610a18 }, |
| 381 | { 0x0904, 0x610ab8 }, |
| 382 | {} |
| 383 | } |
| 384 | }; |
| 385 | |
| 386 | static const struct nv50_disp_mthd_chan |
| 387 | nv50_disp_mast_mthd_chan = { |
| 388 | .name = "Core", |
| 389 | .addr = 0x000000, |
| 390 | .data = { |
| 391 | { "Global", 1, &nv50_disp_mast_mthd_base }, |
| 392 | { "DAC", 3, &nv50_disp_mast_mthd_dac }, |
| 393 | { "SOR", 2, &nv50_disp_mast_mthd_sor }, |
| 394 | { "PIOR", 3, &nv50_disp_mast_mthd_pior }, |
| 395 | { "HEAD", 2, &nv50_disp_mast_mthd_head }, |
| 396 | {} |
| 397 | } |
| 398 | }; |
| 399 | |
Ben Skeggs | 70cabe4 | 2012-08-14 10:04:04 +1000 | [diff] [blame] | 400 | static int |
| 401 | nv50_disp_mast_ctor(struct nouveau_object *parent, |
| 402 | struct nouveau_object *engine, |
| 403 | struct nouveau_oclass *oclass, void *data, u32 size, |
| 404 | struct nouveau_object **pobject) |
| 405 | { |
Ben Skeggs | 370c00f | 2012-08-14 14:11:49 +1000 | [diff] [blame] | 406 | struct nv50_display_mast_class *args = data; |
| 407 | struct nv50_disp_dmac *mast; |
Ben Skeggs | 70cabe4 | 2012-08-14 10:04:04 +1000 | [diff] [blame] | 408 | int ret; |
| 409 | |
Ben Skeggs | 370c00f | 2012-08-14 14:11:49 +1000 | [diff] [blame] | 410 | if (size < sizeof(*args)) |
| 411 | return -EINVAL; |
| 412 | |
| 413 | ret = nv50_disp_dmac_create_(parent, engine, oclass, args->pushbuf, |
| 414 | 0, sizeof(*mast), (void **)&mast); |
| 415 | *pobject = nv_object(mast); |
Ben Skeggs | 70cabe4 | 2012-08-14 10:04:04 +1000 | [diff] [blame] | 416 | if (ret) |
| 417 | return ret; |
| 418 | |
Ben Skeggs | 370c00f | 2012-08-14 14:11:49 +1000 | [diff] [blame] | 419 | nv_parent(mast)->object_attach = nv50_disp_dmac_object_attach; |
| 420 | nv_parent(mast)->object_detach = nv50_disp_dmac_object_detach; |
Ben Skeggs | 70cabe4 | 2012-08-14 10:04:04 +1000 | [diff] [blame] | 421 | return 0; |
| 422 | } |
| 423 | |
Ben Skeggs | 70cabe4 | 2012-08-14 10:04:04 +1000 | [diff] [blame] | 424 | static int |
| 425 | nv50_disp_mast_init(struct nouveau_object *object) |
| 426 | { |
Ben Skeggs | 370c00f | 2012-08-14 14:11:49 +1000 | [diff] [blame] | 427 | struct nv50_disp_priv *priv = (void *)object->engine; |
| 428 | struct nv50_disp_dmac *mast = (void *)object; |
Ben Skeggs | 70cabe4 | 2012-08-14 10:04:04 +1000 | [diff] [blame] | 429 | int ret; |
| 430 | |
Ben Skeggs | 370c00f | 2012-08-14 14:11:49 +1000 | [diff] [blame] | 431 | ret = nv50_disp_chan_init(&mast->base); |
Ben Skeggs | 70cabe4 | 2012-08-14 10:04:04 +1000 | [diff] [blame] | 432 | if (ret) |
| 433 | return ret; |
| 434 | |
Ben Skeggs | 370c00f | 2012-08-14 14:11:49 +1000 | [diff] [blame] | 435 | /* enable error reporting */ |
| 436 | nv_mask(priv, 0x610028, 0x00010001, 0x00010001); |
| 437 | |
| 438 | /* attempt to unstick channel from some unknown state */ |
| 439 | if ((nv_rd32(priv, 0x610200) & 0x009f0000) == 0x00020000) |
| 440 | nv_mask(priv, 0x610200, 0x00800000, 0x00800000); |
| 441 | if ((nv_rd32(priv, 0x610200) & 0x003f0000) == 0x00030000) |
| 442 | nv_mask(priv, 0x610200, 0x00600000, 0x00600000); |
| 443 | |
| 444 | /* initialise channel for dma command submission */ |
| 445 | nv_wr32(priv, 0x610204, mast->push); |
| 446 | nv_wr32(priv, 0x610208, 0x00010000); |
| 447 | nv_wr32(priv, 0x61020c, 0x00000000); |
| 448 | nv_mask(priv, 0x610200, 0x00000010, 0x00000010); |
| 449 | nv_wr32(priv, 0x640000, 0x00000000); |
| 450 | nv_wr32(priv, 0x610200, 0x01000013); |
| 451 | |
| 452 | /* wait for it to go inactive */ |
| 453 | if (!nv_wait(priv, 0x610200, 0x80000000, 0x00000000)) { |
| 454 | nv_error(mast, "init: 0x%08x\n", nv_rd32(priv, 0x610200)); |
| 455 | return -EBUSY; |
| 456 | } |
| 457 | |
Ben Skeggs | 70cabe4 | 2012-08-14 10:04:04 +1000 | [diff] [blame] | 458 | return 0; |
| 459 | } |
| 460 | |
| 461 | static int |
| 462 | nv50_disp_mast_fini(struct nouveau_object *object, bool suspend) |
| 463 | { |
Ben Skeggs | 370c00f | 2012-08-14 14:11:49 +1000 | [diff] [blame] | 464 | struct nv50_disp_priv *priv = (void *)object->engine; |
| 465 | struct nv50_disp_dmac *mast = (void *)object; |
| 466 | |
| 467 | /* deactivate channel */ |
| 468 | nv_mask(priv, 0x610200, 0x00000010, 0x00000000); |
| 469 | nv_mask(priv, 0x610200, 0x00000003, 0x00000000); |
| 470 | if (!nv_wait(priv, 0x610200, 0x001e0000, 0x00000000)) { |
| 471 | nv_error(mast, "fini: 0x%08x\n", nv_rd32(priv, 0x610200)); |
| 472 | if (suspend) |
| 473 | return -EBUSY; |
| 474 | } |
| 475 | |
| 476 | /* disable error reporting */ |
| 477 | nv_mask(priv, 0x610028, 0x00010001, 0x00000000); |
| 478 | |
| 479 | return nv50_disp_chan_fini(&mast->base, suspend); |
Ben Skeggs | 70cabe4 | 2012-08-14 10:04:04 +1000 | [diff] [blame] | 480 | } |
| 481 | |
| 482 | struct nouveau_ofuncs |
| 483 | nv50_disp_mast_ofuncs = { |
| 484 | .ctor = nv50_disp_mast_ctor, |
Ben Skeggs | 370c00f | 2012-08-14 14:11:49 +1000 | [diff] [blame] | 485 | .dtor = nv50_disp_dmac_dtor, |
Ben Skeggs | 70cabe4 | 2012-08-14 10:04:04 +1000 | [diff] [blame] | 486 | .init = nv50_disp_mast_init, |
| 487 | .fini = nv50_disp_mast_fini, |
| 488 | .rd32 = nv50_disp_chan_rd32, |
| 489 | .wr32 = nv50_disp_chan_wr32, |
| 490 | }; |
| 491 | |
| 492 | /******************************************************************************* |
Ben Skeggs | 370c00f | 2012-08-14 14:11:49 +1000 | [diff] [blame] | 493 | * EVO sync channel objects |
Ben Skeggs | 70cabe4 | 2012-08-14 10:04:04 +1000 | [diff] [blame] | 494 | ******************************************************************************/ |
| 495 | |
Ben Skeggs | d67d92c | 2014-02-20 15:14:10 +1000 | [diff] [blame] | 496 | static const struct nv50_disp_mthd_list |
| 497 | nv50_disp_sync_mthd_base = { |
| 498 | .mthd = 0x0000, |
| 499 | .addr = 0x000000, |
| 500 | .data = { |
| 501 | { 0x0080, 0x000000 }, |
| 502 | { 0x0084, 0x0008c4 }, |
| 503 | { 0x0088, 0x0008d0 }, |
| 504 | { 0x008c, 0x0008dc }, |
| 505 | { 0x0090, 0x0008e4 }, |
| 506 | { 0x0094, 0x610884 }, |
| 507 | { 0x00a0, 0x6108a0 }, |
| 508 | { 0x00a4, 0x610878 }, |
| 509 | { 0x00c0, 0x61086c }, |
| 510 | { 0x00e0, 0x610858 }, |
| 511 | { 0x00e4, 0x610860 }, |
| 512 | { 0x00e8, 0x6108ac }, |
| 513 | { 0x00ec, 0x6108b4 }, |
| 514 | { 0x0100, 0x610894 }, |
| 515 | { 0x0110, 0x6108bc }, |
| 516 | { 0x0114, 0x61088c }, |
| 517 | {} |
| 518 | } |
| 519 | }; |
| 520 | |
| 521 | const struct nv50_disp_mthd_list |
| 522 | nv50_disp_sync_mthd_image = { |
| 523 | .mthd = 0x0400, |
| 524 | .addr = 0x000000, |
| 525 | .data = { |
| 526 | { 0x0800, 0x6108f0 }, |
| 527 | { 0x0804, 0x6108fc }, |
| 528 | { 0x0808, 0x61090c }, |
| 529 | { 0x080c, 0x610914 }, |
| 530 | { 0x0810, 0x610904 }, |
| 531 | {} |
| 532 | } |
| 533 | }; |
| 534 | |
| 535 | static const struct nv50_disp_mthd_chan |
| 536 | nv50_disp_sync_mthd_chan = { |
| 537 | .name = "Base", |
| 538 | .addr = 0x000540, |
| 539 | .data = { |
| 540 | { "Global", 1, &nv50_disp_sync_mthd_base }, |
| 541 | { "Image", 2, &nv50_disp_sync_mthd_image }, |
| 542 | {} |
| 543 | } |
| 544 | }; |
| 545 | |
Ben Skeggs | 70cabe4 | 2012-08-14 10:04:04 +1000 | [diff] [blame] | 546 | static int |
Ben Skeggs | 370c00f | 2012-08-14 14:11:49 +1000 | [diff] [blame] | 547 | nv50_disp_sync_ctor(struct nouveau_object *parent, |
Ben Skeggs | 70cabe4 | 2012-08-14 10:04:04 +1000 | [diff] [blame] | 548 | struct nouveau_object *engine, |
| 549 | struct nouveau_oclass *oclass, void *data, u32 size, |
| 550 | struct nouveau_object **pobject) |
| 551 | { |
Ben Skeggs | 370c00f | 2012-08-14 14:11:49 +1000 | [diff] [blame] | 552 | struct nv50_display_sync_class *args = data; |
| 553 | struct nv50_disp_dmac *dmac; |
Ben Skeggs | 70cabe4 | 2012-08-14 10:04:04 +1000 | [diff] [blame] | 554 | int ret; |
| 555 | |
Dan Carpenter | af1ac18 | 2013-01-23 11:27:56 +0300 | [diff] [blame] | 556 | if (size < sizeof(*args) || args->head > 1) |
Ben Skeggs | 370c00f | 2012-08-14 14:11:49 +1000 | [diff] [blame] | 557 | return -EINVAL; |
| 558 | |
| 559 | ret = nv50_disp_dmac_create_(parent, engine, oclass, args->pushbuf, |
| 560 | 1 + args->head, sizeof(*dmac), |
| 561 | (void **)&dmac); |
| 562 | *pobject = nv_object(dmac); |
Ben Skeggs | 70cabe4 | 2012-08-14 10:04:04 +1000 | [diff] [blame] | 563 | if (ret) |
| 564 | return ret; |
| 565 | |
Ben Skeggs | 370c00f | 2012-08-14 14:11:49 +1000 | [diff] [blame] | 566 | nv_parent(dmac)->object_attach = nv50_disp_dmac_object_attach; |
| 567 | nv_parent(dmac)->object_detach = nv50_disp_dmac_object_detach; |
Ben Skeggs | 70cabe4 | 2012-08-14 10:04:04 +1000 | [diff] [blame] | 568 | return 0; |
| 569 | } |
| 570 | |
Ben Skeggs | 70cabe4 | 2012-08-14 10:04:04 +1000 | [diff] [blame] | 571 | struct nouveau_ofuncs |
Ben Skeggs | 370c00f | 2012-08-14 14:11:49 +1000 | [diff] [blame] | 572 | nv50_disp_sync_ofuncs = { |
| 573 | .ctor = nv50_disp_sync_ctor, |
Ben Skeggs | 70cabe4 | 2012-08-14 10:04:04 +1000 | [diff] [blame] | 574 | .dtor = nv50_disp_dmac_dtor, |
| 575 | .init = nv50_disp_dmac_init, |
| 576 | .fini = nv50_disp_dmac_fini, |
| 577 | .rd32 = nv50_disp_chan_rd32, |
| 578 | .wr32 = nv50_disp_chan_wr32, |
| 579 | }; |
| 580 | |
| 581 | /******************************************************************************* |
Ben Skeggs | 370c00f | 2012-08-14 14:11:49 +1000 | [diff] [blame] | 582 | * EVO overlay channel objects |
Ben Skeggs | 70cabe4 | 2012-08-14 10:04:04 +1000 | [diff] [blame] | 583 | ******************************************************************************/ |
| 584 | |
Ben Skeggs | d67d92c | 2014-02-20 15:14:10 +1000 | [diff] [blame] | 585 | const struct nv50_disp_mthd_list |
| 586 | nv50_disp_ovly_mthd_base = { |
| 587 | .mthd = 0x0000, |
| 588 | .addr = 0x000000, |
| 589 | .data = { |
| 590 | { 0x0080, 0x000000 }, |
| 591 | { 0x0084, 0x0009a0 }, |
| 592 | { 0x0088, 0x0009c0 }, |
| 593 | { 0x008c, 0x0009c8 }, |
| 594 | { 0x0090, 0x6109b4 }, |
| 595 | { 0x0094, 0x610970 }, |
| 596 | { 0x00a0, 0x610998 }, |
| 597 | { 0x00a4, 0x610964 }, |
| 598 | { 0x00c0, 0x610958 }, |
| 599 | { 0x00e0, 0x6109a8 }, |
| 600 | { 0x00e4, 0x6109d0 }, |
| 601 | { 0x00e8, 0x6109d8 }, |
| 602 | { 0x0100, 0x61094c }, |
| 603 | { 0x0104, 0x610984 }, |
| 604 | { 0x0108, 0x61098c }, |
| 605 | { 0x0800, 0x6109f8 }, |
| 606 | { 0x0808, 0x610a08 }, |
| 607 | { 0x080c, 0x610a10 }, |
| 608 | { 0x0810, 0x610a00 }, |
| 609 | {} |
| 610 | } |
| 611 | }; |
| 612 | |
| 613 | static const struct nv50_disp_mthd_chan |
| 614 | nv50_disp_ovly_mthd_chan = { |
| 615 | .name = "Overlay", |
| 616 | .addr = 0x000540, |
| 617 | .data = { |
| 618 | { "Global", 1, &nv50_disp_ovly_mthd_base }, |
| 619 | {} |
| 620 | } |
| 621 | }; |
| 622 | |
Ben Skeggs | 70cabe4 | 2012-08-14 10:04:04 +1000 | [diff] [blame] | 623 | static int |
Ben Skeggs | 370c00f | 2012-08-14 14:11:49 +1000 | [diff] [blame] | 624 | nv50_disp_ovly_ctor(struct nouveau_object *parent, |
Ben Skeggs | 70cabe4 | 2012-08-14 10:04:04 +1000 | [diff] [blame] | 625 | struct nouveau_object *engine, |
| 626 | struct nouveau_oclass *oclass, void *data, u32 size, |
| 627 | struct nouveau_object **pobject) |
| 628 | { |
Ben Skeggs | 370c00f | 2012-08-14 14:11:49 +1000 | [diff] [blame] | 629 | struct nv50_display_ovly_class *args = data; |
| 630 | struct nv50_disp_dmac *dmac; |
Ben Skeggs | 70cabe4 | 2012-08-14 10:04:04 +1000 | [diff] [blame] | 631 | int ret; |
| 632 | |
Dan Carpenter | af1ac18 | 2013-01-23 11:27:56 +0300 | [diff] [blame] | 633 | if (size < sizeof(*args) || args->head > 1) |
Ben Skeggs | 370c00f | 2012-08-14 14:11:49 +1000 | [diff] [blame] | 634 | return -EINVAL; |
| 635 | |
| 636 | ret = nv50_disp_dmac_create_(parent, engine, oclass, args->pushbuf, |
| 637 | 3 + args->head, sizeof(*dmac), |
| 638 | (void **)&dmac); |
| 639 | *pobject = nv_object(dmac); |
Ben Skeggs | 70cabe4 | 2012-08-14 10:04:04 +1000 | [diff] [blame] | 640 | if (ret) |
| 641 | return ret; |
| 642 | |
Ben Skeggs | 370c00f | 2012-08-14 14:11:49 +1000 | [diff] [blame] | 643 | nv_parent(dmac)->object_attach = nv50_disp_dmac_object_attach; |
| 644 | nv_parent(dmac)->object_detach = nv50_disp_dmac_object_detach; |
Ben Skeggs | 70cabe4 | 2012-08-14 10:04:04 +1000 | [diff] [blame] | 645 | return 0; |
| 646 | } |
| 647 | |
Ben Skeggs | 370c00f | 2012-08-14 14:11:49 +1000 | [diff] [blame] | 648 | struct nouveau_ofuncs |
| 649 | nv50_disp_ovly_ofuncs = { |
| 650 | .ctor = nv50_disp_ovly_ctor, |
| 651 | .dtor = nv50_disp_dmac_dtor, |
| 652 | .init = nv50_disp_dmac_init, |
| 653 | .fini = nv50_disp_dmac_fini, |
| 654 | .rd32 = nv50_disp_chan_rd32, |
| 655 | .wr32 = nv50_disp_chan_wr32, |
| 656 | }; |
| 657 | |
| 658 | /******************************************************************************* |
| 659 | * EVO PIO channel base class |
| 660 | ******************************************************************************/ |
| 661 | |
| 662 | static int |
| 663 | nv50_disp_pioc_create_(struct nouveau_object *parent, |
| 664 | struct nouveau_object *engine, |
| 665 | struct nouveau_oclass *oclass, int chid, |
| 666 | int length, void **pobject) |
| 667 | { |
| 668 | return nv50_disp_chan_create_(parent, engine, oclass, chid, |
| 669 | length, pobject); |
| 670 | } |
| 671 | |
Ben Skeggs | 70cabe4 | 2012-08-14 10:04:04 +1000 | [diff] [blame] | 672 | static void |
| 673 | nv50_disp_pioc_dtor(struct nouveau_object *object) |
| 674 | { |
Ben Skeggs | 370c00f | 2012-08-14 14:11:49 +1000 | [diff] [blame] | 675 | struct nv50_disp_pioc *pioc = (void *)object; |
| 676 | nv50_disp_chan_destroy(&pioc->base); |
Ben Skeggs | 70cabe4 | 2012-08-14 10:04:04 +1000 | [diff] [blame] | 677 | } |
| 678 | |
| 679 | static int |
| 680 | nv50_disp_pioc_init(struct nouveau_object *object) |
| 681 | { |
Ben Skeggs | 370c00f | 2012-08-14 14:11:49 +1000 | [diff] [blame] | 682 | struct nv50_disp_priv *priv = (void *)object->engine; |
| 683 | struct nv50_disp_pioc *pioc = (void *)object; |
| 684 | int chid = pioc->base.chid; |
Ben Skeggs | 70cabe4 | 2012-08-14 10:04:04 +1000 | [diff] [blame] | 685 | int ret; |
| 686 | |
Ben Skeggs | 370c00f | 2012-08-14 14:11:49 +1000 | [diff] [blame] | 687 | ret = nv50_disp_chan_init(&pioc->base); |
Ben Skeggs | 70cabe4 | 2012-08-14 10:04:04 +1000 | [diff] [blame] | 688 | if (ret) |
| 689 | return ret; |
| 690 | |
Ben Skeggs | 370c00f | 2012-08-14 14:11:49 +1000 | [diff] [blame] | 691 | nv_wr32(priv, 0x610200 + (chid * 0x10), 0x00002000); |
| 692 | if (!nv_wait(priv, 0x610200 + (chid * 0x10), 0x00000000, 0x00000000)) { |
| 693 | nv_error(pioc, "timeout0: 0x%08x\n", |
| 694 | nv_rd32(priv, 0x610200 + (chid * 0x10))); |
| 695 | return -EBUSY; |
| 696 | } |
| 697 | |
| 698 | nv_wr32(priv, 0x610200 + (chid * 0x10), 0x00000001); |
| 699 | if (!nv_wait(priv, 0x610200 + (chid * 0x10), 0x00030000, 0x00010000)) { |
| 700 | nv_error(pioc, "timeout1: 0x%08x\n", |
| 701 | nv_rd32(priv, 0x610200 + (chid * 0x10))); |
| 702 | return -EBUSY; |
| 703 | } |
| 704 | |
Ben Skeggs | 70cabe4 | 2012-08-14 10:04:04 +1000 | [diff] [blame] | 705 | return 0; |
| 706 | } |
| 707 | |
| 708 | static int |
| 709 | nv50_disp_pioc_fini(struct nouveau_object *object, bool suspend) |
| 710 | { |
Ben Skeggs | 370c00f | 2012-08-14 14:11:49 +1000 | [diff] [blame] | 711 | struct nv50_disp_priv *priv = (void *)object->engine; |
| 712 | struct nv50_disp_pioc *pioc = (void *)object; |
| 713 | int chid = pioc->base.chid; |
| 714 | |
| 715 | nv_mask(priv, 0x610200 + (chid * 0x10), 0x00000001, 0x00000000); |
| 716 | if (!nv_wait(priv, 0x610200 + (chid * 0x10), 0x00030000, 0x00000000)) { |
| 717 | nv_error(pioc, "timeout: 0x%08x\n", |
| 718 | nv_rd32(priv, 0x610200 + (chid * 0x10))); |
| 719 | if (suspend) |
| 720 | return -EBUSY; |
| 721 | } |
| 722 | |
| 723 | return nv50_disp_chan_fini(&pioc->base, suspend); |
| 724 | } |
| 725 | |
| 726 | /******************************************************************************* |
| 727 | * EVO immediate overlay channel objects |
| 728 | ******************************************************************************/ |
| 729 | |
| 730 | static int |
| 731 | nv50_disp_oimm_ctor(struct nouveau_object *parent, |
| 732 | struct nouveau_object *engine, |
| 733 | struct nouveau_oclass *oclass, void *data, u32 size, |
| 734 | struct nouveau_object **pobject) |
| 735 | { |
| 736 | struct nv50_display_oimm_class *args = data; |
| 737 | struct nv50_disp_pioc *pioc; |
| 738 | int ret; |
| 739 | |
| 740 | if (size < sizeof(*args) || args->head > 1) |
| 741 | return -EINVAL; |
| 742 | |
| 743 | ret = nv50_disp_pioc_create_(parent, engine, oclass, 5 + args->head, |
| 744 | sizeof(*pioc), (void **)&pioc); |
| 745 | *pobject = nv_object(pioc); |
| 746 | if (ret) |
| 747 | return ret; |
| 748 | |
| 749 | return 0; |
Ben Skeggs | 70cabe4 | 2012-08-14 10:04:04 +1000 | [diff] [blame] | 750 | } |
| 751 | |
| 752 | struct nouveau_ofuncs |
Ben Skeggs | 370c00f | 2012-08-14 14:11:49 +1000 | [diff] [blame] | 753 | nv50_disp_oimm_ofuncs = { |
| 754 | .ctor = nv50_disp_oimm_ctor, |
| 755 | .dtor = nv50_disp_pioc_dtor, |
| 756 | .init = nv50_disp_pioc_init, |
| 757 | .fini = nv50_disp_pioc_fini, |
| 758 | .rd32 = nv50_disp_chan_rd32, |
| 759 | .wr32 = nv50_disp_chan_wr32, |
| 760 | }; |
| 761 | |
| 762 | /******************************************************************************* |
| 763 | * EVO cursor channel objects |
| 764 | ******************************************************************************/ |
| 765 | |
| 766 | static int |
| 767 | nv50_disp_curs_ctor(struct nouveau_object *parent, |
| 768 | struct nouveau_object *engine, |
| 769 | struct nouveau_oclass *oclass, void *data, u32 size, |
| 770 | struct nouveau_object **pobject) |
| 771 | { |
| 772 | struct nv50_display_curs_class *args = data; |
| 773 | struct nv50_disp_pioc *pioc; |
| 774 | int ret; |
| 775 | |
| 776 | if (size < sizeof(*args) || args->head > 1) |
| 777 | return -EINVAL; |
| 778 | |
| 779 | ret = nv50_disp_pioc_create_(parent, engine, oclass, 7 + args->head, |
| 780 | sizeof(*pioc), (void **)&pioc); |
| 781 | *pobject = nv_object(pioc); |
| 782 | if (ret) |
| 783 | return ret; |
| 784 | |
| 785 | return 0; |
| 786 | } |
| 787 | |
| 788 | struct nouveau_ofuncs |
| 789 | nv50_disp_curs_ofuncs = { |
| 790 | .ctor = nv50_disp_curs_ctor, |
Ben Skeggs | 70cabe4 | 2012-08-14 10:04:04 +1000 | [diff] [blame] | 791 | .dtor = nv50_disp_pioc_dtor, |
| 792 | .init = nv50_disp_pioc_init, |
| 793 | .fini = nv50_disp_pioc_fini, |
| 794 | .rd32 = nv50_disp_chan_rd32, |
| 795 | .wr32 = nv50_disp_chan_wr32, |
| 796 | }; |
| 797 | |
| 798 | /******************************************************************************* |
| 799 | * Base display object |
| 800 | ******************************************************************************/ |
| 801 | |
Ben Skeggs | d2fa7d3 | 2013-11-14 13:37:48 +1000 | [diff] [blame] | 802 | int |
| 803 | nv50_disp_base_scanoutpos(struct nouveau_object *object, u32 mthd, |
| 804 | void *data, u32 size) |
| 805 | { |
| 806 | struct nv50_disp_priv *priv = (void *)object->engine; |
| 807 | struct nv04_display_scanoutpos *args = data; |
| 808 | const int head = (mthd & NV50_DISP_MTHD_HEAD); |
| 809 | u32 blanke, blanks, total; |
| 810 | |
| 811 | if (size < sizeof(*args) || head >= priv->head.nr) |
| 812 | return -EINVAL; |
| 813 | blanke = nv_rd32(priv, 0x610aec + (head * 0x540)); |
| 814 | blanks = nv_rd32(priv, 0x610af4 + (head * 0x540)); |
| 815 | total = nv_rd32(priv, 0x610afc + (head * 0x540)); |
| 816 | |
| 817 | args->vblanke = (blanke & 0xffff0000) >> 16; |
| 818 | args->hblanke = (blanke & 0x0000ffff); |
| 819 | args->vblanks = (blanks & 0xffff0000) >> 16; |
| 820 | args->hblanks = (blanks & 0x0000ffff); |
| 821 | args->vtotal = ( total & 0xffff0000) >> 16; |
| 822 | args->htotal = ( total & 0x0000ffff); |
| 823 | |
| 824 | args->time[0] = ktime_to_ns(ktime_get()); |
| 825 | args->vline = nv_rd32(priv, 0x616340 + (head * 0x800)) & 0xffff; |
| 826 | args->time[1] = ktime_to_ns(ktime_get()); /* vline read locks hline */ |
| 827 | args->hline = nv_rd32(priv, 0x616344 + (head * 0x800)) & 0xffff; |
| 828 | return 0; |
| 829 | } |
| 830 | |
Ben Skeggs | 79ca277 | 2014-08-10 04:10:20 +1000 | [diff] [blame^] | 831 | int |
Ben Skeggs | 70cabe4 | 2012-08-14 10:04:04 +1000 | [diff] [blame] | 832 | nv50_disp_base_ctor(struct nouveau_object *parent, |
| 833 | struct nouveau_object *engine, |
| 834 | struct nouveau_oclass *oclass, void *data, u32 size, |
| 835 | struct nouveau_object **pobject) |
| 836 | { |
| 837 | struct nv50_disp_priv *priv = (void *)engine; |
| 838 | struct nv50_disp_base *base; |
| 839 | int ret; |
| 840 | |
| 841 | ret = nouveau_parent_create(parent, engine, oclass, 0, |
| 842 | priv->sclass, 0, &base); |
| 843 | *pobject = nv_object(base); |
| 844 | if (ret) |
| 845 | return ret; |
| 846 | |
Ben Skeggs | 2ecda48 | 2013-04-24 18:04:22 +1000 | [diff] [blame] | 847 | return nouveau_ramht_new(nv_object(base), nv_object(base), 0x1000, 0, |
| 848 | &base->ramht); |
Ben Skeggs | 70cabe4 | 2012-08-14 10:04:04 +1000 | [diff] [blame] | 849 | } |
| 850 | |
Ben Skeggs | 79ca277 | 2014-08-10 04:10:20 +1000 | [diff] [blame^] | 851 | void |
Ben Skeggs | 70cabe4 | 2012-08-14 10:04:04 +1000 | [diff] [blame] | 852 | nv50_disp_base_dtor(struct nouveau_object *object) |
| 853 | { |
| 854 | struct nv50_disp_base *base = (void *)object; |
Ben Skeggs | 370c00f | 2012-08-14 14:11:49 +1000 | [diff] [blame] | 855 | nouveau_ramht_ref(NULL, &base->ramht); |
Ben Skeggs | 70cabe4 | 2012-08-14 10:04:04 +1000 | [diff] [blame] | 856 | nouveau_parent_destroy(&base->base); |
| 857 | } |
| 858 | |
| 859 | static int |
| 860 | nv50_disp_base_init(struct nouveau_object *object) |
| 861 | { |
Ben Skeggs | ab77214 | 2012-08-14 11:29:57 +1000 | [diff] [blame] | 862 | struct nv50_disp_priv *priv = (void *)object->engine; |
Ben Skeggs | 70cabe4 | 2012-08-14 10:04:04 +1000 | [diff] [blame] | 863 | struct nv50_disp_base *base = (void *)object; |
Ben Skeggs | ab77214 | 2012-08-14 11:29:57 +1000 | [diff] [blame] | 864 | int ret, i; |
| 865 | u32 tmp; |
Ben Skeggs | 70cabe4 | 2012-08-14 10:04:04 +1000 | [diff] [blame] | 866 | |
| 867 | ret = nouveau_parent_init(&base->base); |
| 868 | if (ret) |
| 869 | return ret; |
| 870 | |
Ben Skeggs | ab77214 | 2012-08-14 11:29:57 +1000 | [diff] [blame] | 871 | /* The below segments of code copying values from one register to |
| 872 | * another appear to inform EVO of the display capabilities or |
| 873 | * something similar. NFI what the 0x614004 caps are for.. |
| 874 | */ |
| 875 | tmp = nv_rd32(priv, 0x614004); |
| 876 | nv_wr32(priv, 0x610184, tmp); |
| 877 | |
| 878 | /* ... CRTC caps */ |
| 879 | for (i = 0; i < priv->head.nr; i++) { |
| 880 | tmp = nv_rd32(priv, 0x616100 + (i * 0x800)); |
| 881 | nv_wr32(priv, 0x610190 + (i * 0x10), tmp); |
| 882 | tmp = nv_rd32(priv, 0x616104 + (i * 0x800)); |
| 883 | nv_wr32(priv, 0x610194 + (i * 0x10), tmp); |
| 884 | tmp = nv_rd32(priv, 0x616108 + (i * 0x800)); |
| 885 | nv_wr32(priv, 0x610198 + (i * 0x10), tmp); |
| 886 | tmp = nv_rd32(priv, 0x61610c + (i * 0x800)); |
| 887 | nv_wr32(priv, 0x61019c + (i * 0x10), tmp); |
| 888 | } |
| 889 | |
| 890 | /* ... DAC caps */ |
| 891 | for (i = 0; i < priv->dac.nr; i++) { |
| 892 | tmp = nv_rd32(priv, 0x61a000 + (i * 0x800)); |
| 893 | nv_wr32(priv, 0x6101d0 + (i * 0x04), tmp); |
| 894 | } |
| 895 | |
| 896 | /* ... SOR caps */ |
| 897 | for (i = 0; i < priv->sor.nr; i++) { |
| 898 | tmp = nv_rd32(priv, 0x61c000 + (i * 0x800)); |
| 899 | nv_wr32(priv, 0x6101e0 + (i * 0x04), tmp); |
| 900 | } |
| 901 | |
Ben Skeggs | 476e84e | 2013-02-11 09:24:23 +1000 | [diff] [blame] | 902 | /* ... PIOR caps */ |
Emil Velikov | b969fa5 | 2013-07-30 01:01:10 +0100 | [diff] [blame] | 903 | for (i = 0; i < priv->pior.nr; i++) { |
Ben Skeggs | ab77214 | 2012-08-14 11:29:57 +1000 | [diff] [blame] | 904 | tmp = nv_rd32(priv, 0x61e000 + (i * 0x800)); |
| 905 | nv_wr32(priv, 0x6101f0 + (i * 0x04), tmp); |
| 906 | } |
| 907 | |
Ben Skeggs | 446b05a | 2012-08-14 12:50:14 +1000 | [diff] [blame] | 908 | /* steal display away from vbios, or something like that */ |
| 909 | if (nv_rd32(priv, 0x610024) & 0x00000100) { |
| 910 | nv_wr32(priv, 0x610024, 0x00000100); |
| 911 | nv_mask(priv, 0x6194e8, 0x00000001, 0x00000000); |
| 912 | if (!nv_wait(priv, 0x6194e8, 0x00000002, 0x00000000)) { |
| 913 | nv_error(priv, "timeout acquiring display\n"); |
| 914 | return -EBUSY; |
| 915 | } |
| 916 | } |
| 917 | |
| 918 | /* point at display engine memory area (hash table, objects) */ |
Ben Skeggs | 370c00f | 2012-08-14 14:11:49 +1000 | [diff] [blame] | 919 | nv_wr32(priv, 0x610010, (nv_gpuobj(base->ramht)->addr >> 8) | 9); |
Ben Skeggs | 446b05a | 2012-08-14 12:50:14 +1000 | [diff] [blame] | 920 | |
| 921 | /* enable supervisor interrupts, disable everything else */ |
Ben Skeggs | 370c00f | 2012-08-14 14:11:49 +1000 | [diff] [blame] | 922 | nv_wr32(priv, 0x61002c, 0x00000370); |
| 923 | nv_wr32(priv, 0x610028, 0x00000000); |
Ben Skeggs | 70cabe4 | 2012-08-14 10:04:04 +1000 | [diff] [blame] | 924 | return 0; |
| 925 | } |
| 926 | |
| 927 | static int |
| 928 | nv50_disp_base_fini(struct nouveau_object *object, bool suspend) |
| 929 | { |
Ben Skeggs | 446b05a | 2012-08-14 12:50:14 +1000 | [diff] [blame] | 930 | struct nv50_disp_priv *priv = (void *)object->engine; |
Ben Skeggs | 70cabe4 | 2012-08-14 10:04:04 +1000 | [diff] [blame] | 931 | struct nv50_disp_base *base = (void *)object; |
Ben Skeggs | 446b05a | 2012-08-14 12:50:14 +1000 | [diff] [blame] | 932 | |
| 933 | /* disable all interrupts */ |
| 934 | nv_wr32(priv, 0x610024, 0x00000000); |
| 935 | nv_wr32(priv, 0x610020, 0x00000000); |
| 936 | |
Ben Skeggs | 70cabe4 | 2012-08-14 10:04:04 +1000 | [diff] [blame] | 937 | return nouveau_parent_fini(&base->base, suspend); |
| 938 | } |
| 939 | |
| 940 | struct nouveau_ofuncs |
| 941 | nv50_disp_base_ofuncs = { |
| 942 | .ctor = nv50_disp_base_ctor, |
| 943 | .dtor = nv50_disp_base_dtor, |
| 944 | .init = nv50_disp_base_init, |
| 945 | .fini = nv50_disp_base_fini, |
| 946 | }; |
| 947 | |
Ben Skeggs | ef22c8b | 2012-11-09 09:32:56 +1000 | [diff] [blame] | 948 | static struct nouveau_omthds |
| 949 | nv50_disp_base_omthds[] = { |
Ben Skeggs | d2fa7d3 | 2013-11-14 13:37:48 +1000 | [diff] [blame] | 950 | { HEAD_MTHD(NV50_DISP_SCANOUTPOS) , nv50_disp_base_scanoutpos }, |
Ben Skeggs | ef22c8b | 2012-11-09 09:32:56 +1000 | [diff] [blame] | 951 | { SOR_MTHD(NV50_DISP_SOR_PWR) , nv50_sor_mthd }, |
Ben Skeggs | 4a230fa | 2012-11-09 11:25:37 +1000 | [diff] [blame] | 952 | { SOR_MTHD(NV50_DISP_SOR_LVDS_SCRIPT) , nv50_sor_mthd }, |
Ben Skeggs | ef22c8b | 2012-11-09 09:32:56 +1000 | [diff] [blame] | 953 | { DAC_MTHD(NV50_DISP_DAC_PWR) , nv50_dac_mthd }, |
| 954 | { DAC_MTHD(NV50_DISP_DAC_LOAD) , nv50_dac_mthd }, |
Ben Skeggs | a2bc283 | 2013-02-11 09:11:08 +1000 | [diff] [blame] | 955 | { PIOR_MTHD(NV50_DISP_PIOR_PWR) , nv50_pior_mthd }, |
| 956 | { PIOR_MTHD(NV50_DISP_PIOR_TMDS_PWR) , nv50_pior_mthd }, |
| 957 | { PIOR_MTHD(NV50_DISP_PIOR_DP_PWR) , nv50_pior_mthd }, |
Ben Skeggs | ef22c8b | 2012-11-09 09:32:56 +1000 | [diff] [blame] | 958 | {}, |
| 959 | }; |
| 960 | |
Ben Skeggs | 70cabe4 | 2012-08-14 10:04:04 +1000 | [diff] [blame] | 961 | static struct nouveau_oclass |
| 962 | nv50_disp_base_oclass[] = { |
Ben Skeggs | ef22c8b | 2012-11-09 09:32:56 +1000 | [diff] [blame] | 963 | { NV50_DISP_CLASS, &nv50_disp_base_ofuncs, nv50_disp_base_omthds }, |
Ben Skeggs | 370c00f | 2012-08-14 14:11:49 +1000 | [diff] [blame] | 964 | {} |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 965 | }; |
| 966 | |
| 967 | static struct nouveau_oclass |
| 968 | nv50_disp_sclass[] = { |
Ben Skeggs | 370c00f | 2012-08-14 14:11:49 +1000 | [diff] [blame] | 969 | { NV50_DISP_MAST_CLASS, &nv50_disp_mast_ofuncs }, |
| 970 | { NV50_DISP_SYNC_CLASS, &nv50_disp_sync_ofuncs }, |
| 971 | { NV50_DISP_OVLY_CLASS, &nv50_disp_ovly_ofuncs }, |
| 972 | { NV50_DISP_OIMM_CLASS, &nv50_disp_oimm_ofuncs }, |
| 973 | { NV50_DISP_CURS_CLASS, &nv50_disp_curs_ofuncs }, |
Ben Skeggs | 70cabe4 | 2012-08-14 10:04:04 +1000 | [diff] [blame] | 974 | {} |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 975 | }; |
| 976 | |
Ben Skeggs | 70cabe4 | 2012-08-14 10:04:04 +1000 | [diff] [blame] | 977 | /******************************************************************************* |
| 978 | * Display context, tracks instmem allocation and prevents more than one |
| 979 | * client using the display hardware at any time. |
| 980 | ******************************************************************************/ |
| 981 | |
| 982 | static int |
| 983 | nv50_disp_data_ctor(struct nouveau_object *parent, |
| 984 | struct nouveau_object *engine, |
| 985 | struct nouveau_oclass *oclass, void *data, u32 size, |
| 986 | struct nouveau_object **pobject) |
| 987 | { |
Ben Skeggs | 370c00f | 2012-08-14 14:11:49 +1000 | [diff] [blame] | 988 | struct nv50_disp_priv *priv = (void *)engine; |
Ben Skeggs | 70cabe4 | 2012-08-14 10:04:04 +1000 | [diff] [blame] | 989 | struct nouveau_engctx *ectx; |
Ben Skeggs | 370c00f | 2012-08-14 14:11:49 +1000 | [diff] [blame] | 990 | int ret = -EBUSY; |
Ben Skeggs | 70cabe4 | 2012-08-14 10:04:04 +1000 | [diff] [blame] | 991 | |
Ben Skeggs | 370c00f | 2012-08-14 14:11:49 +1000 | [diff] [blame] | 992 | /* no context needed for channel objects... */ |
| 993 | if (nv_mclass(parent) != NV_DEVICE_CLASS) { |
| 994 | atomic_inc(&parent->refcount); |
| 995 | *pobject = parent; |
Ben Skeggs | 43e6e51 | 2013-04-26 00:12:59 +1000 | [diff] [blame] | 996 | return 1; |
Ben Skeggs | 370c00f | 2012-08-14 14:11:49 +1000 | [diff] [blame] | 997 | } |
Ben Skeggs | 70cabe4 | 2012-08-14 10:04:04 +1000 | [diff] [blame] | 998 | |
Ben Skeggs | 370c00f | 2012-08-14 14:11:49 +1000 | [diff] [blame] | 999 | /* allocate display hardware to client */ |
| 1000 | mutex_lock(&nv_subdev(priv)->mutex); |
| 1001 | if (list_empty(&nv_engine(priv)->contexts)) { |
| 1002 | ret = nouveau_engctx_create(parent, engine, oclass, NULL, |
| 1003 | 0x10000, 0x10000, |
| 1004 | NVOBJ_FLAG_HEAP, &ectx); |
| 1005 | *pobject = nv_object(ectx); |
| 1006 | } |
| 1007 | mutex_unlock(&nv_subdev(priv)->mutex); |
| 1008 | return ret; |
Ben Skeggs | 70cabe4 | 2012-08-14 10:04:04 +1000 | [diff] [blame] | 1009 | } |
| 1010 | |
| 1011 | struct nouveau_oclass |
| 1012 | nv50_disp_cclass = { |
| 1013 | .handle = NV_ENGCTX(DISP, 0x50), |
| 1014 | .ofuncs = &(struct nouveau_ofuncs) { |
| 1015 | .ctor = nv50_disp_data_ctor, |
| 1016 | .dtor = _nouveau_engctx_dtor, |
| 1017 | .init = _nouveau_engctx_init, |
| 1018 | .fini = _nouveau_engctx_fini, |
| 1019 | .rd32 = _nouveau_engctx_rd32, |
| 1020 | .wr32 = _nouveau_engctx_wr32, |
| 1021 | }, |
| 1022 | }; |
| 1023 | |
| 1024 | /******************************************************************************* |
| 1025 | * Display engine implementation |
| 1026 | ******************************************************************************/ |
| 1027 | |
Ben Skeggs | 79ca277 | 2014-08-10 04:10:20 +1000 | [diff] [blame^] | 1028 | static void |
| 1029 | nv50_disp_vblank_fini(struct nvkm_event *event, int type, int head) |
| 1030 | { |
| 1031 | struct nouveau_disp *disp = container_of(event, typeof(*disp), vblank); |
| 1032 | nv_mask(disp, 0x61002c, (4 << head), 0); |
| 1033 | } |
| 1034 | |
| 1035 | static void |
| 1036 | nv50_disp_vblank_init(struct nvkm_event *event, int type, int head) |
| 1037 | { |
| 1038 | struct nouveau_disp *disp = container_of(event, typeof(*disp), vblank); |
| 1039 | nv_mask(disp, 0x61002c, (4 << head), (4 << head)); |
| 1040 | } |
| 1041 | |
| 1042 | const struct nvkm_event_func |
| 1043 | nv50_disp_vblank_func = { |
| 1044 | .ctor = nouveau_disp_vblank_ctor, |
| 1045 | .init = nv50_disp_vblank_init, |
| 1046 | .fini = nv50_disp_vblank_fini, |
| 1047 | }; |
| 1048 | |
Ben Skeggs | 117e1633 | 2014-02-21 11:06:40 +1000 | [diff] [blame] | 1049 | static const struct nouveau_enum |
| 1050 | nv50_disp_intr_error_type[] = { |
| 1051 | { 3, "ILLEGAL_MTHD" }, |
| 1052 | { 4, "INVALID_VALUE" }, |
| 1053 | { 5, "INVALID_STATE" }, |
| 1054 | { 7, "INVALID_HANDLE" }, |
| 1055 | {} |
| 1056 | }; |
| 1057 | |
| 1058 | static const struct nouveau_enum |
| 1059 | nv50_disp_intr_error_code[] = { |
| 1060 | { 0x00, "" }, |
| 1061 | {} |
| 1062 | }; |
| 1063 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 1064 | static void |
Ben Skeggs | 117e1633 | 2014-02-21 11:06:40 +1000 | [diff] [blame] | 1065 | nv50_disp_intr_error(struct nv50_disp_priv *priv, int chid) |
Ben Skeggs | 186ecad | 2012-11-09 12:09:48 +1000 | [diff] [blame] | 1066 | { |
Ben Skeggs | 9cf6ba2 | 2014-02-20 23:26:18 +1000 | [diff] [blame] | 1067 | struct nv50_disp_impl *impl = (void *)nv_object(priv)->oclass; |
Ben Skeggs | 117e1633 | 2014-02-21 11:06:40 +1000 | [diff] [blame] | 1068 | u32 data = nv_rd32(priv, 0x610084 + (chid * 0x08)); |
| 1069 | u32 addr = nv_rd32(priv, 0x610080 + (chid * 0x08)); |
| 1070 | u32 code = (addr & 0x00ff0000) >> 16; |
| 1071 | u32 type = (addr & 0x00007000) >> 12; |
| 1072 | u32 mthd = (addr & 0x00000ffc); |
| 1073 | const struct nouveau_enum *ec, *et; |
| 1074 | char ecunk[6], etunk[6]; |
Ben Skeggs | 186ecad | 2012-11-09 12:09:48 +1000 | [diff] [blame] | 1075 | |
Ben Skeggs | 117e1633 | 2014-02-21 11:06:40 +1000 | [diff] [blame] | 1076 | et = nouveau_enum_find(nv50_disp_intr_error_type, type); |
| 1077 | if (!et) |
| 1078 | snprintf(etunk, sizeof(etunk), "UNK%02X", type); |
Ben Skeggs | 186ecad | 2012-11-09 12:09:48 +1000 | [diff] [blame] | 1079 | |
Ben Skeggs | 117e1633 | 2014-02-21 11:06:40 +1000 | [diff] [blame] | 1080 | ec = nouveau_enum_find(nv50_disp_intr_error_code, code); |
| 1081 | if (!ec) |
| 1082 | snprintf(ecunk, sizeof(ecunk), "UNK%02X", code); |
Ben Skeggs | 186ecad | 2012-11-09 12:09:48 +1000 | [diff] [blame] | 1083 | |
Ben Skeggs | 117e1633 | 2014-02-21 11:06:40 +1000 | [diff] [blame] | 1084 | nv_error(priv, "%s [%s] chid %d mthd 0x%04x data 0x%08x\n", |
| 1085 | et ? et->name : etunk, ec ? ec->name : ecunk, |
| 1086 | chid, mthd, data); |
| 1087 | |
Ben Skeggs | 9cf6ba2 | 2014-02-20 23:26:18 +1000 | [diff] [blame] | 1088 | if (chid == 0) { |
| 1089 | switch (mthd) { |
| 1090 | case 0x0080: |
| 1091 | nv50_disp_mthd_chan(priv, NV_DBG_ERROR, chid - 0, |
| 1092 | impl->mthd.core); |
| 1093 | break; |
| 1094 | default: |
| 1095 | break; |
| 1096 | } |
| 1097 | } else |
| 1098 | if (chid <= 2) { |
| 1099 | switch (mthd) { |
| 1100 | case 0x0080: |
| 1101 | nv50_disp_mthd_chan(priv, NV_DBG_ERROR, chid - 1, |
| 1102 | impl->mthd.base); |
| 1103 | break; |
| 1104 | default: |
| 1105 | break; |
| 1106 | } |
| 1107 | } else |
| 1108 | if (chid <= 4) { |
| 1109 | switch (mthd) { |
| 1110 | case 0x0080: |
| 1111 | nv50_disp_mthd_chan(priv, NV_DBG_ERROR, chid - 3, |
| 1112 | impl->mthd.ovly); |
| 1113 | break; |
| 1114 | default: |
| 1115 | break; |
| 1116 | } |
| 1117 | } |
| 1118 | |
Ben Skeggs | 117e1633 | 2014-02-21 11:06:40 +1000 | [diff] [blame] | 1119 | nv_wr32(priv, 0x610020, 0x00010000 << chid); |
| 1120 | nv_wr32(priv, 0x610080 + (chid * 0x08), 0x90000000); |
Ben Skeggs | 186ecad | 2012-11-09 12:09:48 +1000 | [diff] [blame] | 1121 | } |
| 1122 | |
Ben Skeggs | 415f12e | 2014-05-21 11:24:43 +1000 | [diff] [blame] | 1123 | static struct nvkm_output * |
| 1124 | exec_lookup(struct nv50_disp_priv *priv, int head, int or, u32 ctrl, |
| 1125 | u32 *data, u8 *ver, u8 *hdr, u8 *cnt, u8 *len, |
Ben Skeggs | 186ecad | 2012-11-09 12:09:48 +1000 | [diff] [blame] | 1126 | struct nvbios_outp *info) |
| 1127 | { |
| 1128 | struct nouveau_bios *bios = nouveau_bios(priv); |
Ben Skeggs | 415f12e | 2014-05-21 11:24:43 +1000 | [diff] [blame] | 1129 | struct nvkm_output *outp; |
| 1130 | u16 mask, type; |
Ben Skeggs | 186ecad | 2012-11-09 12:09:48 +1000 | [diff] [blame] | 1131 | |
Ben Skeggs | 415f12e | 2014-05-21 11:24:43 +1000 | [diff] [blame] | 1132 | if (or < 4) { |
Ben Skeggs | 186ecad | 2012-11-09 12:09:48 +1000 | [diff] [blame] | 1133 | type = DCB_OUTPUT_ANALOG; |
| 1134 | mask = 0; |
Ben Skeggs | 476e84e | 2013-02-11 09:24:23 +1000 | [diff] [blame] | 1135 | } else |
Ben Skeggs | 415f12e | 2014-05-21 11:24:43 +1000 | [diff] [blame] | 1136 | if (or < 8) { |
Ben Skeggs | 186ecad | 2012-11-09 12:09:48 +1000 | [diff] [blame] | 1137 | switch (ctrl & 0x00000f00) { |
| 1138 | case 0x00000000: type = DCB_OUTPUT_LVDS; mask = 1; break; |
| 1139 | case 0x00000100: type = DCB_OUTPUT_TMDS; mask = 1; break; |
| 1140 | case 0x00000200: type = DCB_OUTPUT_TMDS; mask = 2; break; |
| 1141 | case 0x00000500: type = DCB_OUTPUT_TMDS; mask = 3; break; |
| 1142 | case 0x00000800: type = DCB_OUTPUT_DP; mask = 1; break; |
| 1143 | case 0x00000900: type = DCB_OUTPUT_DP; mask = 2; break; |
| 1144 | default: |
| 1145 | nv_error(priv, "unknown SOR mc 0x%08x\n", ctrl); |
Ben Skeggs | 415f12e | 2014-05-21 11:24:43 +1000 | [diff] [blame] | 1146 | return NULL; |
Ben Skeggs | 186ecad | 2012-11-09 12:09:48 +1000 | [diff] [blame] | 1147 | } |
Ben Skeggs | 415f12e | 2014-05-21 11:24:43 +1000 | [diff] [blame] | 1148 | or -= 4; |
Ben Skeggs | 476e84e | 2013-02-11 09:24:23 +1000 | [diff] [blame] | 1149 | } else { |
Ben Skeggs | 415f12e | 2014-05-21 11:24:43 +1000 | [diff] [blame] | 1150 | or = or - 8; |
Ben Skeggs | 476e84e | 2013-02-11 09:24:23 +1000 | [diff] [blame] | 1151 | type = 0x0010; |
| 1152 | mask = 0; |
| 1153 | switch (ctrl & 0x00000f00) { |
Ben Skeggs | 415f12e | 2014-05-21 11:24:43 +1000 | [diff] [blame] | 1154 | case 0x00000000: type |= priv->pior.type[or]; break; |
Ben Skeggs | 476e84e | 2013-02-11 09:24:23 +1000 | [diff] [blame] | 1155 | default: |
| 1156 | nv_error(priv, "unknown PIOR mc 0x%08x\n", ctrl); |
Ben Skeggs | 415f12e | 2014-05-21 11:24:43 +1000 | [diff] [blame] | 1157 | return NULL; |
Ben Skeggs | 476e84e | 2013-02-11 09:24:23 +1000 | [diff] [blame] | 1158 | } |
Ben Skeggs | 186ecad | 2012-11-09 12:09:48 +1000 | [diff] [blame] | 1159 | } |
| 1160 | |
| 1161 | mask = 0x00c0 & (mask << 6); |
Ben Skeggs | 415f12e | 2014-05-21 11:24:43 +1000 | [diff] [blame] | 1162 | mask |= 0x0001 << or; |
Ben Skeggs | 186ecad | 2012-11-09 12:09:48 +1000 | [diff] [blame] | 1163 | mask |= 0x0100 << head; |
| 1164 | |
Ben Skeggs | 415f12e | 2014-05-21 11:24:43 +1000 | [diff] [blame] | 1165 | list_for_each_entry(outp, &priv->base.outp, head) { |
| 1166 | if ((outp->info.hasht & 0xff) == type && |
| 1167 | (outp->info.hashm & mask) == mask) { |
| 1168 | *data = nvbios_outp_match(bios, outp->info.hasht, |
| 1169 | outp->info.hashm, |
| 1170 | ver, hdr, cnt, len, info); |
| 1171 | if (!*data) |
| 1172 | return NULL; |
| 1173 | return outp; |
| 1174 | } |
| 1175 | } |
Ben Skeggs | 186ecad | 2012-11-09 12:09:48 +1000 | [diff] [blame] | 1176 | |
Ben Skeggs | 415f12e | 2014-05-21 11:24:43 +1000 | [diff] [blame] | 1177 | return NULL; |
Ben Skeggs | 186ecad | 2012-11-09 12:09:48 +1000 | [diff] [blame] | 1178 | } |
| 1179 | |
Ben Skeggs | 1ae5a62 | 2014-06-11 13:06:48 +1000 | [diff] [blame] | 1180 | static struct nvkm_output * |
Ben Skeggs | 186ecad | 2012-11-09 12:09:48 +1000 | [diff] [blame] | 1181 | exec_script(struct nv50_disp_priv *priv, int head, int id) |
| 1182 | { |
| 1183 | struct nouveau_bios *bios = nouveau_bios(priv); |
Ben Skeggs | 415f12e | 2014-05-21 11:24:43 +1000 | [diff] [blame] | 1184 | struct nvkm_output *outp; |
Ben Skeggs | 186ecad | 2012-11-09 12:09:48 +1000 | [diff] [blame] | 1185 | struct nvbios_outp info; |
Ben Skeggs | 186ecad | 2012-11-09 12:09:48 +1000 | [diff] [blame] | 1186 | u8 ver, hdr, cnt, len; |
Ben Skeggs | 415f12e | 2014-05-21 11:24:43 +1000 | [diff] [blame] | 1187 | u32 data, ctrl = 0; |
Emil Velikov | b969fa5 | 2013-07-30 01:01:10 +0100 | [diff] [blame] | 1188 | u32 reg; |
Ben Skeggs | 186ecad | 2012-11-09 12:09:48 +1000 | [diff] [blame] | 1189 | int i; |
| 1190 | |
Ben Skeggs | 476e84e | 2013-02-11 09:24:23 +1000 | [diff] [blame] | 1191 | /* DAC */ |
Emil Velikov | b969fa5 | 2013-07-30 01:01:10 +0100 | [diff] [blame] | 1192 | for (i = 0; !(ctrl & (1 << head)) && i < priv->dac.nr; i++) |
Ben Skeggs | 186ecad | 2012-11-09 12:09:48 +1000 | [diff] [blame] | 1193 | ctrl = nv_rd32(priv, 0x610b5c + (i * 8)); |
| 1194 | |
Ben Skeggs | 476e84e | 2013-02-11 09:24:23 +1000 | [diff] [blame] | 1195 | /* SOR */ |
Marcin Slusarz | c684cef | 2013-01-03 19:38:45 +0100 | [diff] [blame] | 1196 | if (!(ctrl & (1 << head))) { |
| 1197 | if (nv_device(priv)->chipset < 0x90 || |
| 1198 | nv_device(priv)->chipset == 0x92 || |
| 1199 | nv_device(priv)->chipset == 0xa0) { |
Emil Velikov | b969fa5 | 2013-07-30 01:01:10 +0100 | [diff] [blame] | 1200 | reg = 0x610b74; |
Marcin Slusarz | c684cef | 2013-01-03 19:38:45 +0100 | [diff] [blame] | 1201 | } else { |
Emil Velikov | b969fa5 | 2013-07-30 01:01:10 +0100 | [diff] [blame] | 1202 | reg = 0x610798; |
Marcin Slusarz | c684cef | 2013-01-03 19:38:45 +0100 | [diff] [blame] | 1203 | } |
Emil Velikov | b969fa5 | 2013-07-30 01:01:10 +0100 | [diff] [blame] | 1204 | for (i = 0; !(ctrl & (1 << head)) && i < priv->sor.nr; i++) |
| 1205 | ctrl = nv_rd32(priv, reg + (i * 8)); |
| 1206 | i += 4; |
Ben Skeggs | 186ecad | 2012-11-09 12:09:48 +1000 | [diff] [blame] | 1207 | } |
| 1208 | |
Ben Skeggs | 476e84e | 2013-02-11 09:24:23 +1000 | [diff] [blame] | 1209 | /* PIOR */ |
| 1210 | if (!(ctrl & (1 << head))) { |
Emil Velikov | b969fa5 | 2013-07-30 01:01:10 +0100 | [diff] [blame] | 1211 | for (i = 0; !(ctrl & (1 << head)) && i < priv->pior.nr; i++) |
Ben Skeggs | 476e84e | 2013-02-11 09:24:23 +1000 | [diff] [blame] | 1212 | ctrl = nv_rd32(priv, 0x610b84 + (i * 8)); |
| 1213 | i += 8; |
| 1214 | } |
| 1215 | |
Ben Skeggs | 186ecad | 2012-11-09 12:09:48 +1000 | [diff] [blame] | 1216 | if (!(ctrl & (1 << head))) |
Ben Skeggs | 1ae5a62 | 2014-06-11 13:06:48 +1000 | [diff] [blame] | 1217 | return NULL; |
Marcin Slusarz | c684cef | 2013-01-03 19:38:45 +0100 | [diff] [blame] | 1218 | i--; |
Ben Skeggs | 186ecad | 2012-11-09 12:09:48 +1000 | [diff] [blame] | 1219 | |
Ben Skeggs | 415f12e | 2014-05-21 11:24:43 +1000 | [diff] [blame] | 1220 | outp = exec_lookup(priv, head, i, ctrl, &data, &ver, &hdr, &cnt, &len, &info); |
| 1221 | if (outp) { |
Ben Skeggs | 186ecad | 2012-11-09 12:09:48 +1000 | [diff] [blame] | 1222 | struct nvbios_init init = { |
| 1223 | .subdev = nv_subdev(priv), |
| 1224 | .bios = bios, |
| 1225 | .offset = info.script[id], |
Ben Skeggs | 415f12e | 2014-05-21 11:24:43 +1000 | [diff] [blame] | 1226 | .outp = &outp->info, |
Ben Skeggs | 186ecad | 2012-11-09 12:09:48 +1000 | [diff] [blame] | 1227 | .crtc = head, |
| 1228 | .execute = 1, |
| 1229 | }; |
| 1230 | |
Ben Skeggs | 1ae5a62 | 2014-06-11 13:06:48 +1000 | [diff] [blame] | 1231 | nvbios_exec(&init); |
Ben Skeggs | 186ecad | 2012-11-09 12:09:48 +1000 | [diff] [blame] | 1232 | } |
| 1233 | |
Ben Skeggs | 1ae5a62 | 2014-06-11 13:06:48 +1000 | [diff] [blame] | 1234 | return outp; |
Ben Skeggs | 186ecad | 2012-11-09 12:09:48 +1000 | [diff] [blame] | 1235 | } |
| 1236 | |
Ben Skeggs | 415f12e | 2014-05-21 11:24:43 +1000 | [diff] [blame] | 1237 | static struct nvkm_output * |
| 1238 | exec_clkcmp(struct nv50_disp_priv *priv, int head, int id, u32 pclk, u32 *conf) |
Ben Skeggs | 186ecad | 2012-11-09 12:09:48 +1000 | [diff] [blame] | 1239 | { |
| 1240 | struct nouveau_bios *bios = nouveau_bios(priv); |
Ben Skeggs | 415f12e | 2014-05-21 11:24:43 +1000 | [diff] [blame] | 1241 | struct nvkm_output *outp; |
Ben Skeggs | 186ecad | 2012-11-09 12:09:48 +1000 | [diff] [blame] | 1242 | struct nvbios_outp info1; |
| 1243 | struct nvbios_ocfg info2; |
| 1244 | u8 ver, hdr, cnt, len; |
Ben Skeggs | 415f12e | 2014-05-21 11:24:43 +1000 | [diff] [blame] | 1245 | u32 data, ctrl = 0; |
Emil Velikov | b969fa5 | 2013-07-30 01:01:10 +0100 | [diff] [blame] | 1246 | u32 reg; |
Ben Skeggs | 186ecad | 2012-11-09 12:09:48 +1000 | [diff] [blame] | 1247 | int i; |
| 1248 | |
Ben Skeggs | 476e84e | 2013-02-11 09:24:23 +1000 | [diff] [blame] | 1249 | /* DAC */ |
Emil Velikov | b969fa5 | 2013-07-30 01:01:10 +0100 | [diff] [blame] | 1250 | for (i = 0; !(ctrl & (1 << head)) && i < priv->dac.nr; i++) |
Ben Skeggs | 186ecad | 2012-11-09 12:09:48 +1000 | [diff] [blame] | 1251 | ctrl = nv_rd32(priv, 0x610b58 + (i * 8)); |
| 1252 | |
Ben Skeggs | 476e84e | 2013-02-11 09:24:23 +1000 | [diff] [blame] | 1253 | /* SOR */ |
Marcin Slusarz | c684cef | 2013-01-03 19:38:45 +0100 | [diff] [blame] | 1254 | if (!(ctrl & (1 << head))) { |
| 1255 | if (nv_device(priv)->chipset < 0x90 || |
| 1256 | nv_device(priv)->chipset == 0x92 || |
| 1257 | nv_device(priv)->chipset == 0xa0) { |
Emil Velikov | b969fa5 | 2013-07-30 01:01:10 +0100 | [diff] [blame] | 1258 | reg = 0x610b70; |
Marcin Slusarz | c684cef | 2013-01-03 19:38:45 +0100 | [diff] [blame] | 1259 | } else { |
Emil Velikov | b969fa5 | 2013-07-30 01:01:10 +0100 | [diff] [blame] | 1260 | reg = 0x610794; |
Marcin Slusarz | c684cef | 2013-01-03 19:38:45 +0100 | [diff] [blame] | 1261 | } |
Emil Velikov | b969fa5 | 2013-07-30 01:01:10 +0100 | [diff] [blame] | 1262 | for (i = 0; !(ctrl & (1 << head)) && i < priv->sor.nr; i++) |
| 1263 | ctrl = nv_rd32(priv, reg + (i * 8)); |
| 1264 | i += 4; |
Ben Skeggs | 186ecad | 2012-11-09 12:09:48 +1000 | [diff] [blame] | 1265 | } |
| 1266 | |
Ben Skeggs | 476e84e | 2013-02-11 09:24:23 +1000 | [diff] [blame] | 1267 | /* PIOR */ |
| 1268 | if (!(ctrl & (1 << head))) { |
Emil Velikov | b969fa5 | 2013-07-30 01:01:10 +0100 | [diff] [blame] | 1269 | for (i = 0; !(ctrl & (1 << head)) && i < priv->pior.nr; i++) |
Ben Skeggs | 476e84e | 2013-02-11 09:24:23 +1000 | [diff] [blame] | 1270 | ctrl = nv_rd32(priv, 0x610b80 + (i * 8)); |
| 1271 | i += 8; |
| 1272 | } |
| 1273 | |
Ben Skeggs | 186ecad | 2012-11-09 12:09:48 +1000 | [diff] [blame] | 1274 | if (!(ctrl & (1 << head))) |
Ben Skeggs | 415f12e | 2014-05-21 11:24:43 +1000 | [diff] [blame] | 1275 | return NULL; |
Marcin Slusarz | c684cef | 2013-01-03 19:38:45 +0100 | [diff] [blame] | 1276 | i--; |
Ben Skeggs | 186ecad | 2012-11-09 12:09:48 +1000 | [diff] [blame] | 1277 | |
Ben Skeggs | 415f12e | 2014-05-21 11:24:43 +1000 | [diff] [blame] | 1278 | outp = exec_lookup(priv, head, i, ctrl, &data, &ver, &hdr, &cnt, &len, &info1); |
Ben Skeggs | ba5e01b | 2014-06-17 09:39:18 +1000 | [diff] [blame] | 1279 | if (!outp) |
Ben Skeggs | 415f12e | 2014-05-21 11:24:43 +1000 | [diff] [blame] | 1280 | return NULL; |
Ben Skeggs | 186ecad | 2012-11-09 12:09:48 +1000 | [diff] [blame] | 1281 | |
Ben Skeggs | 415f12e | 2014-05-21 11:24:43 +1000 | [diff] [blame] | 1282 | if (outp->info.location == 0) { |
| 1283 | switch (outp->info.type) { |
Ben Skeggs | 476e84e | 2013-02-11 09:24:23 +1000 | [diff] [blame] | 1284 | case DCB_OUTPUT_TMDS: |
Ben Skeggs | 415f12e | 2014-05-21 11:24:43 +1000 | [diff] [blame] | 1285 | *conf = (ctrl & 0x00000f00) >> 8; |
Ben Skeggs | 476e84e | 2013-02-11 09:24:23 +1000 | [diff] [blame] | 1286 | if (pclk >= 165000) |
Ben Skeggs | 415f12e | 2014-05-21 11:24:43 +1000 | [diff] [blame] | 1287 | *conf |= 0x0100; |
Ben Skeggs | 476e84e | 2013-02-11 09:24:23 +1000 | [diff] [blame] | 1288 | break; |
| 1289 | case DCB_OUTPUT_LVDS: |
Ben Skeggs | 415f12e | 2014-05-21 11:24:43 +1000 | [diff] [blame] | 1290 | *conf = priv->sor.lvdsconf; |
Ben Skeggs | 476e84e | 2013-02-11 09:24:23 +1000 | [diff] [blame] | 1291 | break; |
| 1292 | case DCB_OUTPUT_DP: |
Ben Skeggs | 415f12e | 2014-05-21 11:24:43 +1000 | [diff] [blame] | 1293 | *conf = (ctrl & 0x00000f00) >> 8; |
Ben Skeggs | 476e84e | 2013-02-11 09:24:23 +1000 | [diff] [blame] | 1294 | break; |
| 1295 | case DCB_OUTPUT_ANALOG: |
| 1296 | default: |
Ben Skeggs | 415f12e | 2014-05-21 11:24:43 +1000 | [diff] [blame] | 1297 | *conf = 0x00ff; |
Ben Skeggs | 476e84e | 2013-02-11 09:24:23 +1000 | [diff] [blame] | 1298 | break; |
| 1299 | } |
| 1300 | } else { |
Ben Skeggs | 415f12e | 2014-05-21 11:24:43 +1000 | [diff] [blame] | 1301 | *conf = (ctrl & 0x00000f00) >> 8; |
Ben Skeggs | 476e84e | 2013-02-11 09:24:23 +1000 | [diff] [blame] | 1302 | pclk = pclk / 2; |
Ben Skeggs | 186ecad | 2012-11-09 12:09:48 +1000 | [diff] [blame] | 1303 | } |
| 1304 | |
Ben Skeggs | 415f12e | 2014-05-21 11:24:43 +1000 | [diff] [blame] | 1305 | data = nvbios_ocfg_match(bios, data, *conf, &ver, &hdr, &cnt, &len, &info2); |
Ben Skeggs | 0a0afd2 | 2013-02-18 23:17:53 -0500 | [diff] [blame] | 1306 | if (data && id < 0xff) { |
Ben Skeggs | 186ecad | 2012-11-09 12:09:48 +1000 | [diff] [blame] | 1307 | data = nvbios_oclk_match(bios, info2.clkcmp[id], pclk); |
| 1308 | if (data) { |
| 1309 | struct nvbios_init init = { |
| 1310 | .subdev = nv_subdev(priv), |
| 1311 | .bios = bios, |
| 1312 | .offset = data, |
Ben Skeggs | 415f12e | 2014-05-21 11:24:43 +1000 | [diff] [blame] | 1313 | .outp = &outp->info, |
Ben Skeggs | 186ecad | 2012-11-09 12:09:48 +1000 | [diff] [blame] | 1314 | .crtc = head, |
| 1315 | .execute = 1, |
| 1316 | }; |
| 1317 | |
Ben Skeggs | 46c13c1 | 2013-02-16 13:49:21 +1000 | [diff] [blame] | 1318 | nvbios_exec(&init); |
Ben Skeggs | 186ecad | 2012-11-09 12:09:48 +1000 | [diff] [blame] | 1319 | } |
| 1320 | } |
| 1321 | |
Ben Skeggs | 415f12e | 2014-05-21 11:24:43 +1000 | [diff] [blame] | 1322 | return outp; |
Ben Skeggs | 186ecad | 2012-11-09 12:09:48 +1000 | [diff] [blame] | 1323 | } |
| 1324 | |
| 1325 | static void |
Ben Skeggs | 16d4c03 | 2013-02-20 18:56:33 +1000 | [diff] [blame] | 1326 | nv50_disp_intr_unk10_0(struct nv50_disp_priv *priv, int head) |
Ben Skeggs | 186ecad | 2012-11-09 12:09:48 +1000 | [diff] [blame] | 1327 | { |
Ben Skeggs | 16d4c03 | 2013-02-20 18:56:33 +1000 | [diff] [blame] | 1328 | exec_script(priv, head, 1); |
Ben Skeggs | 186ecad | 2012-11-09 12:09:48 +1000 | [diff] [blame] | 1329 | } |
| 1330 | |
| 1331 | static void |
Ben Skeggs | 16d4c03 | 2013-02-20 18:56:33 +1000 | [diff] [blame] | 1332 | nv50_disp_intr_unk20_0(struct nv50_disp_priv *priv, int head) |
| 1333 | { |
Ben Skeggs | 1ae5a62 | 2014-06-11 13:06:48 +1000 | [diff] [blame] | 1334 | struct nvkm_output *outp = exec_script(priv, head, 2); |
| 1335 | |
| 1336 | /* the binary driver does this outside of the supervisor handling |
| 1337 | * (after the third supervisor from a detach). we (currently?) |
| 1338 | * allow both detach/attach to happen in the same set of |
| 1339 | * supervisor interrupts, so it would make sense to execute this |
| 1340 | * (full power down?) script after all the detach phases of the |
| 1341 | * supervisor handling. like with training if needed from the |
| 1342 | * second supervisor, nvidia doesn't do this, so who knows if it's |
| 1343 | * entirely safe, but it does appear to work.. |
| 1344 | * |
| 1345 | * without this script being run, on some configurations i've |
| 1346 | * seen, switching from DP to TMDS on a DP connector may result |
| 1347 | * in a blank screen (SOR_PWR off/on can restore it) |
| 1348 | */ |
| 1349 | if (outp && outp->info.type == DCB_OUTPUT_DP) { |
| 1350 | struct nvkm_output_dp *outpdp = (void *)outp; |
| 1351 | struct nvbios_init init = { |
| 1352 | .subdev = nv_subdev(priv), |
| 1353 | .bios = nouveau_bios(priv), |
| 1354 | .outp = &outp->info, |
| 1355 | .crtc = head, |
| 1356 | .offset = outpdp->info.script[4], |
| 1357 | .execute = 1, |
| 1358 | }; |
| 1359 | |
| 1360 | nvbios_exec(&init); |
| 1361 | atomic_set(&outpdp->lt.done, 0); |
| 1362 | } |
Ben Skeggs | 16d4c03 | 2013-02-20 18:56:33 +1000 | [diff] [blame] | 1363 | } |
| 1364 | |
| 1365 | static void |
| 1366 | nv50_disp_intr_unk20_1(struct nv50_disp_priv *priv, int head) |
| 1367 | { |
Ben Skeggs | 88524bc | 2013-03-05 10:53:54 +1000 | [diff] [blame] | 1368 | struct nouveau_devinit *devinit = nouveau_devinit(priv); |
Ben Skeggs | 16d4c03 | 2013-02-20 18:56:33 +1000 | [diff] [blame] | 1369 | u32 pclk = nv_rd32(priv, 0x610ad0 + (head * 0x540)) & 0x3fffff; |
| 1370 | if (pclk) |
Ben Skeggs | 88524bc | 2013-03-05 10:53:54 +1000 | [diff] [blame] | 1371 | devinit->pll_set(devinit, PLL_VPLL0 + head, pclk); |
Ben Skeggs | 16d4c03 | 2013-02-20 18:56:33 +1000 | [diff] [blame] | 1372 | } |
| 1373 | |
| 1374 | static void |
| 1375 | nv50_disp_intr_unk20_2_dp(struct nv50_disp_priv *priv, |
| 1376 | struct dcb_output *outp, u32 pclk) |
Ben Skeggs | 186ecad | 2012-11-09 12:09:48 +1000 | [diff] [blame] | 1377 | { |
| 1378 | const int link = !(outp->sorconf.link & 1); |
| 1379 | const int or = ffs(outp->or) - 1; |
| 1380 | const u32 soff = ( or * 0x800); |
| 1381 | const u32 loff = (link * 0x080) + soff; |
| 1382 | const u32 ctrl = nv_rd32(priv, 0x610794 + (or * 8)); |
Ben Skeggs | 186ecad | 2012-11-09 12:09:48 +1000 | [diff] [blame] | 1383 | const u32 symbol = 100000; |
| 1384 | u32 dpctrl = nv_rd32(priv, 0x61c10c + loff) & 0x0000f0000; |
| 1385 | u32 clksor = nv_rd32(priv, 0x614300 + soff); |
| 1386 | int bestTU = 0, bestVTUi = 0, bestVTUf = 0, bestVTUa = 0; |
| 1387 | int TU, VTUi, VTUf, VTUa; |
| 1388 | u64 link_data_rate, link_ratio, unk; |
| 1389 | u32 best_diff = 64 * symbol; |
Ben Skeggs | bf2c886 | 2012-11-21 14:49:54 +1000 | [diff] [blame] | 1390 | u32 link_nr, link_bw, bits, r; |
Ben Skeggs | 186ecad | 2012-11-09 12:09:48 +1000 | [diff] [blame] | 1391 | |
| 1392 | /* calculate packed data rate for each lane */ |
| 1393 | if (dpctrl > 0x00030000) link_nr = 4; |
| 1394 | else if (dpctrl > 0x00010000) link_nr = 2; |
| 1395 | else link_nr = 1; |
| 1396 | |
| 1397 | if (clksor & 0x000c0000) |
| 1398 | link_bw = 270000; |
| 1399 | else |
| 1400 | link_bw = 162000; |
| 1401 | |
Ben Skeggs | bf2c886 | 2012-11-21 14:49:54 +1000 | [diff] [blame] | 1402 | if ((ctrl & 0xf0000) == 0x60000) bits = 30; |
| 1403 | else if ((ctrl & 0xf0000) == 0x50000) bits = 24; |
| 1404 | else bits = 18; |
| 1405 | |
Ben Skeggs | 186ecad | 2012-11-09 12:09:48 +1000 | [diff] [blame] | 1406 | link_data_rate = (pclk * bits / 8) / link_nr; |
| 1407 | |
| 1408 | /* calculate ratio of packed data rate to link symbol rate */ |
| 1409 | link_ratio = link_data_rate * symbol; |
| 1410 | r = do_div(link_ratio, link_bw); |
| 1411 | |
| 1412 | for (TU = 64; TU >= 32; TU--) { |
| 1413 | /* calculate average number of valid symbols in each TU */ |
| 1414 | u32 tu_valid = link_ratio * TU; |
| 1415 | u32 calc, diff; |
| 1416 | |
| 1417 | /* find a hw representation for the fraction.. */ |
| 1418 | VTUi = tu_valid / symbol; |
| 1419 | calc = VTUi * symbol; |
| 1420 | diff = tu_valid - calc; |
| 1421 | if (diff) { |
| 1422 | if (diff >= (symbol / 2)) { |
| 1423 | VTUf = symbol / (symbol - diff); |
| 1424 | if (symbol - (VTUf * diff)) |
| 1425 | VTUf++; |
| 1426 | |
| 1427 | if (VTUf <= 15) { |
| 1428 | VTUa = 1; |
| 1429 | calc += symbol - (symbol / VTUf); |
| 1430 | } else { |
| 1431 | VTUa = 0; |
| 1432 | VTUf = 1; |
| 1433 | calc += symbol; |
| 1434 | } |
| 1435 | } else { |
| 1436 | VTUa = 0; |
| 1437 | VTUf = min((int)(symbol / diff), 15); |
| 1438 | calc += symbol / VTUf; |
| 1439 | } |
| 1440 | |
| 1441 | diff = calc - tu_valid; |
| 1442 | } else { |
| 1443 | /* no remainder, but the hw doesn't like the fractional |
| 1444 | * part to be zero. decrement the integer part and |
| 1445 | * have the fraction add a whole symbol back |
| 1446 | */ |
| 1447 | VTUa = 0; |
| 1448 | VTUf = 1; |
| 1449 | VTUi--; |
| 1450 | } |
| 1451 | |
| 1452 | if (diff < best_diff) { |
| 1453 | best_diff = diff; |
| 1454 | bestTU = TU; |
| 1455 | bestVTUa = VTUa; |
| 1456 | bestVTUf = VTUf; |
| 1457 | bestVTUi = VTUi; |
| 1458 | if (diff == 0) |
| 1459 | break; |
| 1460 | } |
| 1461 | } |
| 1462 | |
| 1463 | if (!bestTU) { |
| 1464 | nv_error(priv, "unable to find suitable dp config\n"); |
| 1465 | return; |
| 1466 | } |
| 1467 | |
| 1468 | /* XXX close to vbios numbers, but not right */ |
| 1469 | unk = (symbol - link_ratio) * bestTU; |
| 1470 | unk *= link_ratio; |
| 1471 | r = do_div(unk, symbol); |
| 1472 | r = do_div(unk, symbol); |
| 1473 | unk += 6; |
| 1474 | |
| 1475 | nv_mask(priv, 0x61c10c + loff, 0x000001fc, bestTU << 2); |
| 1476 | nv_mask(priv, 0x61c128 + loff, 0x010f7f3f, bestVTUa << 24 | |
| 1477 | bestVTUf << 16 | |
| 1478 | bestVTUi << 8 | unk); |
| 1479 | } |
| 1480 | |
| 1481 | static void |
Ben Skeggs | 16d4c03 | 2013-02-20 18:56:33 +1000 | [diff] [blame] | 1482 | nv50_disp_intr_unk20_2(struct nv50_disp_priv *priv, int head) |
Ben Skeggs | 186ecad | 2012-11-09 12:09:48 +1000 | [diff] [blame] | 1483 | { |
Ben Skeggs | 415f12e | 2014-05-21 11:24:43 +1000 | [diff] [blame] | 1484 | struct nvkm_output *outp; |
Ben Skeggs | 16d4c03 | 2013-02-20 18:56:33 +1000 | [diff] [blame] | 1485 | u32 pclk = nv_rd32(priv, 0x610ad0 + (head * 0x540)) & 0x3fffff; |
| 1486 | u32 hval, hreg = 0x614200 + (head * 0x800); |
| 1487 | u32 oval, oreg; |
Ben Skeggs | 415f12e | 2014-05-21 11:24:43 +1000 | [diff] [blame] | 1488 | u32 mask, conf; |
Ben Skeggs | 186ecad | 2012-11-09 12:09:48 +1000 | [diff] [blame] | 1489 | |
Ben Skeggs | 415f12e | 2014-05-21 11:24:43 +1000 | [diff] [blame] | 1490 | outp = exec_clkcmp(priv, head, 0xff, pclk, &conf); |
| 1491 | if (!outp) |
| 1492 | return; |
Ben Skeggs | 0a0afd2 | 2013-02-18 23:17:53 -0500 | [diff] [blame] | 1493 | |
Ben Skeggs | 55f083c | 2014-05-20 10:18:03 +1000 | [diff] [blame] | 1494 | /* we allow both encoder attach and detach operations to occur |
| 1495 | * within a single supervisor (ie. modeset) sequence. the |
| 1496 | * encoder detach scripts quite often switch off power to the |
| 1497 | * lanes, which requires the link to be re-trained. |
| 1498 | * |
| 1499 | * this is not generally an issue as the sink "must" (heh) |
| 1500 | * signal an irq when it's lost sync so the driver can |
| 1501 | * re-train. |
| 1502 | * |
| 1503 | * however, on some boards, if one does not configure at least |
| 1504 | * the gpu side of the link *before* attaching, then various |
| 1505 | * things can go horribly wrong (PDISP disappearing from mmio, |
| 1506 | * third supervisor never happens, etc). |
| 1507 | * |
| 1508 | * the solution is simply to retrain here, if necessary. last |
| 1509 | * i checked, the binary driver userspace does not appear to |
| 1510 | * trigger this situation (it forces an UPDATE between steps). |
| 1511 | */ |
Ben Skeggs | b17932c | 2014-05-27 15:00:36 +1000 | [diff] [blame] | 1512 | if (outp->info.type == DCB_OUTPUT_DP) { |
Ben Skeggs | 415f12e | 2014-05-21 11:24:43 +1000 | [diff] [blame] | 1513 | u32 soff = (ffs(outp->info.or) - 1) * 0x08; |
Ben Skeggs | b17932c | 2014-05-27 15:00:36 +1000 | [diff] [blame] | 1514 | u32 ctrl, datarate; |
| 1515 | |
| 1516 | if (outp->info.location == 0) { |
| 1517 | ctrl = nv_rd32(priv, 0x610794 + soff); |
| 1518 | soff = 1; |
| 1519 | } else { |
| 1520 | ctrl = nv_rd32(priv, 0x610b80 + soff); |
| 1521 | soff = 2; |
| 1522 | } |
Ben Skeggs | 415f12e | 2014-05-21 11:24:43 +1000 | [diff] [blame] | 1523 | |
| 1524 | switch ((ctrl & 0x000f0000) >> 16) { |
Ben Skeggs | 0713b45 | 2014-07-01 10:54:52 +1000 | [diff] [blame] | 1525 | case 6: datarate = pclk * 30; break; |
| 1526 | case 5: datarate = pclk * 24; break; |
Ben Skeggs | 415f12e | 2014-05-21 11:24:43 +1000 | [diff] [blame] | 1527 | case 2: |
| 1528 | default: |
Ben Skeggs | 0713b45 | 2014-07-01 10:54:52 +1000 | [diff] [blame] | 1529 | datarate = pclk * 18; |
Ben Skeggs | 415f12e | 2014-05-21 11:24:43 +1000 | [diff] [blame] | 1530 | break; |
Ben Skeggs | 186ecad | 2012-11-09 12:09:48 +1000 | [diff] [blame] | 1531 | } |
Ben Skeggs | 186ecad | 2012-11-09 12:09:48 +1000 | [diff] [blame] | 1532 | |
Ben Skeggs | 55f083c | 2014-05-20 10:18:03 +1000 | [diff] [blame] | 1533 | if (nvkm_output_dp_train(outp, datarate / soff, true)) |
| 1534 | ERR("link not trained before attach\n"); |
Ben Skeggs | 16d4c03 | 2013-02-20 18:56:33 +1000 | [diff] [blame] | 1535 | } |
Ben Skeggs | 415f12e | 2014-05-21 11:24:43 +1000 | [diff] [blame] | 1536 | |
| 1537 | exec_clkcmp(priv, head, 0, pclk, &conf); |
| 1538 | |
| 1539 | if (!outp->info.location && outp->info.type == DCB_OUTPUT_ANALOG) { |
| 1540 | oreg = 0x614280 + (ffs(outp->info.or) - 1) * 0x800; |
| 1541 | oval = 0x00000000; |
| 1542 | hval = 0x00000000; |
| 1543 | mask = 0xffffffff; |
| 1544 | } else |
| 1545 | if (!outp->info.location) { |
| 1546 | if (outp->info.type == DCB_OUTPUT_DP) |
| 1547 | nv50_disp_intr_unk20_2_dp(priv, &outp->info, pclk); |
| 1548 | oreg = 0x614300 + (ffs(outp->info.or) - 1) * 0x800; |
| 1549 | oval = (conf & 0x0100) ? 0x00000101 : 0x00000000; |
| 1550 | hval = 0x00000000; |
| 1551 | mask = 0x00000707; |
| 1552 | } else { |
| 1553 | oreg = 0x614380 + (ffs(outp->info.or) - 1) * 0x800; |
| 1554 | oval = 0x00000001; |
| 1555 | hval = 0x00000001; |
| 1556 | mask = 0x00000707; |
| 1557 | } |
| 1558 | |
| 1559 | nv_mask(priv, hreg, 0x0000000f, hval); |
| 1560 | nv_mask(priv, oreg, mask, oval); |
Ben Skeggs | 186ecad | 2012-11-09 12:09:48 +1000 | [diff] [blame] | 1561 | } |
| 1562 | |
| 1563 | /* If programming a TMDS output on a SOR that can also be configured for |
| 1564 | * DisplayPort, make sure NV50_SOR_DP_CTRL_ENABLE is forced off. |
| 1565 | * |
| 1566 | * It looks like the VBIOS TMDS scripts make an attempt at this, however, |
| 1567 | * the VBIOS scripts on at least one board I have only switch it off on |
| 1568 | * link 0, causing a blank display if the output has previously been |
| 1569 | * programmed for DisplayPort. |
| 1570 | */ |
| 1571 | static void |
Ben Skeggs | 16d4c03 | 2013-02-20 18:56:33 +1000 | [diff] [blame] | 1572 | nv50_disp_intr_unk40_0_tmds(struct nv50_disp_priv *priv, struct dcb_output *outp) |
Ben Skeggs | 186ecad | 2012-11-09 12:09:48 +1000 | [diff] [blame] | 1573 | { |
| 1574 | struct nouveau_bios *bios = nouveau_bios(priv); |
| 1575 | const int link = !(outp->sorconf.link & 1); |
| 1576 | const int or = ffs(outp->or) - 1; |
| 1577 | const u32 loff = (or * 0x800) + (link * 0x80); |
| 1578 | const u16 mask = (outp->sorconf.link << 6) | outp->or; |
| 1579 | u8 ver, hdr; |
| 1580 | |
| 1581 | if (dcb_outp_match(bios, DCB_OUTPUT_DP, mask, &ver, &hdr, outp)) |
| 1582 | nv_mask(priv, 0x61c10c + loff, 0x00000001, 0x00000000); |
| 1583 | } |
| 1584 | |
| 1585 | static void |
Ben Skeggs | 16d4c03 | 2013-02-20 18:56:33 +1000 | [diff] [blame] | 1586 | nv50_disp_intr_unk40_0(struct nv50_disp_priv *priv, int head) |
Ben Skeggs | 186ecad | 2012-11-09 12:09:48 +1000 | [diff] [blame] | 1587 | { |
Ben Skeggs | 415f12e | 2014-05-21 11:24:43 +1000 | [diff] [blame] | 1588 | struct nvkm_output *outp; |
Ben Skeggs | 16d4c03 | 2013-02-20 18:56:33 +1000 | [diff] [blame] | 1589 | u32 pclk = nv_rd32(priv, 0x610ad0 + (head * 0x540)) & 0x3fffff; |
Ben Skeggs | 415f12e | 2014-05-21 11:24:43 +1000 | [diff] [blame] | 1590 | u32 conf; |
Ben Skeggs | 476e84e | 2013-02-11 09:24:23 +1000 | [diff] [blame] | 1591 | |
Ben Skeggs | 415f12e | 2014-05-21 11:24:43 +1000 | [diff] [blame] | 1592 | outp = exec_clkcmp(priv, head, 1, pclk, &conf); |
| 1593 | if (!outp) |
| 1594 | return; |
Ben Skeggs | 16d4c03 | 2013-02-20 18:56:33 +1000 | [diff] [blame] | 1595 | |
Ben Skeggs | 415f12e | 2014-05-21 11:24:43 +1000 | [diff] [blame] | 1596 | if (outp->info.location == 0 && outp->info.type == DCB_OUTPUT_TMDS) |
| 1597 | nv50_disp_intr_unk40_0_tmds(priv, &outp->info); |
Ben Skeggs | 186ecad | 2012-11-09 12:09:48 +1000 | [diff] [blame] | 1598 | } |
| 1599 | |
Ben Skeggs | 5cc027f | 2013-02-18 17:50:51 -0500 | [diff] [blame] | 1600 | void |
| 1601 | nv50_disp_intr_supervisor(struct work_struct *work) |
Ben Skeggs | 186ecad | 2012-11-09 12:09:48 +1000 | [diff] [blame] | 1602 | { |
Ben Skeggs | 5cc027f | 2013-02-18 17:50:51 -0500 | [diff] [blame] | 1603 | struct nv50_disp_priv *priv = |
| 1604 | container_of(work, struct nv50_disp_priv, supervisor); |
Ben Skeggs | b62b9ec | 2014-02-20 23:19:58 +1000 | [diff] [blame] | 1605 | struct nv50_disp_impl *impl = (void *)nv_object(priv)->oclass; |
Ben Skeggs | 186ecad | 2012-11-09 12:09:48 +1000 | [diff] [blame] | 1606 | u32 super = nv_rd32(priv, 0x610030); |
Ben Skeggs | 16d4c03 | 2013-02-20 18:56:33 +1000 | [diff] [blame] | 1607 | int head; |
Ben Skeggs | 186ecad | 2012-11-09 12:09:48 +1000 | [diff] [blame] | 1608 | |
Ben Skeggs | 5cc027f | 2013-02-18 17:50:51 -0500 | [diff] [blame] | 1609 | nv_debug(priv, "supervisor 0x%08x 0x%08x\n", priv->super, super); |
Ben Skeggs | 186ecad | 2012-11-09 12:09:48 +1000 | [diff] [blame] | 1610 | |
Ben Skeggs | 16d4c03 | 2013-02-20 18:56:33 +1000 | [diff] [blame] | 1611 | if (priv->super & 0x00000010) { |
Ben Skeggs | b62b9ec | 2014-02-20 23:19:58 +1000 | [diff] [blame] | 1612 | nv50_disp_mthd_chan(priv, NV_DBG_DEBUG, 0, impl->mthd.core); |
Ben Skeggs | 16d4c03 | 2013-02-20 18:56:33 +1000 | [diff] [blame] | 1613 | for (head = 0; head < priv->head.nr; head++) { |
| 1614 | if (!(super & (0x00000020 << head))) |
| 1615 | continue; |
| 1616 | if (!(super & (0x00000080 << head))) |
| 1617 | continue; |
| 1618 | nv50_disp_intr_unk10_0(priv, head); |
| 1619 | } |
| 1620 | } else |
| 1621 | if (priv->super & 0x00000020) { |
| 1622 | for (head = 0; head < priv->head.nr; head++) { |
| 1623 | if (!(super & (0x00000080 << head))) |
| 1624 | continue; |
| 1625 | nv50_disp_intr_unk20_0(priv, head); |
| 1626 | } |
| 1627 | for (head = 0; head < priv->head.nr; head++) { |
| 1628 | if (!(super & (0x00000200 << head))) |
| 1629 | continue; |
| 1630 | nv50_disp_intr_unk20_1(priv, head); |
| 1631 | } |
| 1632 | for (head = 0; head < priv->head.nr; head++) { |
| 1633 | if (!(super & (0x00000080 << head))) |
| 1634 | continue; |
| 1635 | nv50_disp_intr_unk20_2(priv, head); |
| 1636 | } |
| 1637 | } else |
| 1638 | if (priv->super & 0x00000040) { |
| 1639 | for (head = 0; head < priv->head.nr; head++) { |
| 1640 | if (!(super & (0x00000080 << head))) |
| 1641 | continue; |
| 1642 | nv50_disp_intr_unk40_0(priv, head); |
| 1643 | } |
| 1644 | } |
| 1645 | |
| 1646 | nv_wr32(priv, 0x610030, 0x80000000); |
Ben Skeggs | 186ecad | 2012-11-09 12:09:48 +1000 | [diff] [blame] | 1647 | } |
| 1648 | |
Ben Skeggs | 70cabe4 | 2012-08-14 10:04:04 +1000 | [diff] [blame] | 1649 | void |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 1650 | nv50_disp_intr(struct nouveau_subdev *subdev) |
| 1651 | { |
| 1652 | struct nv50_disp_priv *priv = (void *)subdev; |
Ben Skeggs | 186ecad | 2012-11-09 12:09:48 +1000 | [diff] [blame] | 1653 | u32 intr0 = nv_rd32(priv, 0x610020); |
| 1654 | u32 intr1 = nv_rd32(priv, 0x610024); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 1655 | |
Ben Skeggs | 117e1633 | 2014-02-21 11:06:40 +1000 | [diff] [blame] | 1656 | while (intr0 & 0x001f0000) { |
| 1657 | u32 chid = __ffs(intr0 & 0x001f0000) - 16; |
| 1658 | nv50_disp_intr_error(priv, chid); |
| 1659 | intr0 &= ~(0x00010000 << chid); |
Ben Skeggs | 186ecad | 2012-11-09 12:09:48 +1000 | [diff] [blame] | 1660 | } |
| 1661 | |
| 1662 | if (intr1 & 0x00000004) { |
Ben Skeggs | 79ca277 | 2014-08-10 04:10:20 +1000 | [diff] [blame^] | 1663 | nouveau_disp_vblank(&priv->base, 0); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 1664 | nv_wr32(priv, 0x610024, 0x00000004); |
Ben Skeggs | 186ecad | 2012-11-09 12:09:48 +1000 | [diff] [blame] | 1665 | intr1 &= ~0x00000004; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 1666 | } |
| 1667 | |
Ben Skeggs | 186ecad | 2012-11-09 12:09:48 +1000 | [diff] [blame] | 1668 | if (intr1 & 0x00000008) { |
Ben Skeggs | 79ca277 | 2014-08-10 04:10:20 +1000 | [diff] [blame^] | 1669 | nouveau_disp_vblank(&priv->base, 1); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 1670 | nv_wr32(priv, 0x610024, 0x00000008); |
Ben Skeggs | 186ecad | 2012-11-09 12:09:48 +1000 | [diff] [blame] | 1671 | intr1 &= ~0x00000008; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 1672 | } |
| 1673 | |
Ben Skeggs | 186ecad | 2012-11-09 12:09:48 +1000 | [diff] [blame] | 1674 | if (intr1 & 0x00000070) { |
Ben Skeggs | 5cc027f | 2013-02-18 17:50:51 -0500 | [diff] [blame] | 1675 | priv->super = (intr1 & 0x00000070); |
| 1676 | schedule_work(&priv->supervisor); |
| 1677 | nv_wr32(priv, 0x610024, priv->super); |
Ben Skeggs | 186ecad | 2012-11-09 12:09:48 +1000 | [diff] [blame] | 1678 | intr1 &= ~0x00000070; |
| 1679 | } |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 1680 | } |
| 1681 | |
| 1682 | static int |
| 1683 | nv50_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, |
Ben Skeggs | 370c00f | 2012-08-14 14:11:49 +1000 | [diff] [blame] | 1684 | struct nouveau_oclass *oclass, void *data, u32 size, |
| 1685 | struct nouveau_object **pobject) |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 1686 | { |
| 1687 | struct nv50_disp_priv *priv; |
| 1688 | int ret; |
| 1689 | |
Ben Skeggs | 1d7c71a | 2013-01-31 09:23:34 +1000 | [diff] [blame] | 1690 | ret = nouveau_disp_create(parent, engine, oclass, 2, "PDISP", |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 1691 | "display", &priv); |
| 1692 | *pobject = nv_object(priv); |
| 1693 | if (ret) |
| 1694 | return ret; |
| 1695 | |
Ben Skeggs | 70cabe4 | 2012-08-14 10:04:04 +1000 | [diff] [blame] | 1696 | nv_engine(priv)->sclass = nv50_disp_base_oclass; |
| 1697 | nv_engine(priv)->cclass = &nv50_disp_cclass; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 1698 | nv_subdev(priv)->intr = nv50_disp_intr; |
Ben Skeggs | 5cc027f | 2013-02-18 17:50:51 -0500 | [diff] [blame] | 1699 | INIT_WORK(&priv->supervisor, nv50_disp_intr_supervisor); |
Ben Skeggs | 70cabe4 | 2012-08-14 10:04:04 +1000 | [diff] [blame] | 1700 | priv->sclass = nv50_disp_sclass; |
| 1701 | priv->head.nr = 2; |
| 1702 | priv->dac.nr = 3; |
| 1703 | priv->sor.nr = 2; |
Ben Skeggs | a2bc283 | 2013-02-11 09:11:08 +1000 | [diff] [blame] | 1704 | priv->pior.nr = 3; |
Ben Skeggs | ef22c8b | 2012-11-09 09:32:56 +1000 | [diff] [blame] | 1705 | priv->dac.power = nv50_dac_power; |
Ben Skeggs | 7ebb38b | 2012-11-09 09:38:06 +1000 | [diff] [blame] | 1706 | priv->dac.sense = nv50_dac_sense; |
Ben Skeggs | ef22c8b | 2012-11-09 09:32:56 +1000 | [diff] [blame] | 1707 | priv->sor.power = nv50_sor_power; |
Ben Skeggs | a2bc283 | 2013-02-11 09:11:08 +1000 | [diff] [blame] | 1708 | priv->pior.power = nv50_pior_power; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 1709 | return 0; |
| 1710 | } |
| 1711 | |
Ben Skeggs | a8f8b48 | 2014-02-20 21:33:34 +1000 | [diff] [blame] | 1712 | struct nouveau_oclass * |
Ben Skeggs | b8407c9 | 2014-05-17 11:19:54 +1000 | [diff] [blame] | 1713 | nv50_disp_outp_sclass[] = { |
| 1714 | &nv50_pior_dp_impl.base.base, |
| 1715 | NULL |
| 1716 | }; |
| 1717 | |
| 1718 | struct nouveau_oclass * |
Ben Skeggs | a8f8b48 | 2014-02-20 21:33:34 +1000 | [diff] [blame] | 1719 | nv50_disp_oclass = &(struct nv50_disp_impl) { |
| 1720 | .base.base.handle = NV_ENGINE(DISP, 0x50), |
| 1721 | .base.base.ofuncs = &(struct nouveau_ofuncs) { |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 1722 | .ctor = nv50_disp_ctor, |
| 1723 | .dtor = _nouveau_disp_dtor, |
| 1724 | .init = _nouveau_disp_init, |
| 1725 | .fini = _nouveau_disp_fini, |
| 1726 | }, |
Ben Skeggs | 79ca277 | 2014-08-10 04:10:20 +1000 | [diff] [blame^] | 1727 | .base.vblank = &nv50_disp_vblank_func, |
Ben Skeggs | b8407c9 | 2014-05-17 11:19:54 +1000 | [diff] [blame] | 1728 | .base.outp = nv50_disp_outp_sclass, |
Ben Skeggs | d67d92c | 2014-02-20 15:14:10 +1000 | [diff] [blame] | 1729 | .mthd.core = &nv50_disp_mast_mthd_chan, |
| 1730 | .mthd.base = &nv50_disp_sync_mthd_chan, |
| 1731 | .mthd.ovly = &nv50_disp_ovly_mthd_chan, |
| 1732 | .mthd.prev = 0x000004, |
Ben Skeggs | a8f8b48 | 2014-02-20 21:33:34 +1000 | [diff] [blame] | 1733 | }.base.base; |