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gerrit-public.fairphone.software / kernel / msm-4.9 / 7d5684575c1729952effc6b285eb74d2009839c5 / . / drivers / pinctrl / sh-pfc / pfc-r8a7740.c
blob: 6af8fae412b613f22efcd787de6f4803fb923aa7 [file] [log] [blame]
Laurent Pinchartd5b15212012-12-15 23:51:21 +0100[diff] [blame]1/*
2 * R8A7740 processor support
3 *
4 * Copyright (C) 2011 Renesas Solutions Corp.
5 * Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; version 2 of the
10 * License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 */
21#include <linux/kernel.h>
Laurent Pinchartd5b15212012-12-15 23:51:21 +0100[diff] [blame]22#include <mach/r8a7740.h>
23#include <mach/irqs.h>
24
Laurent Pinchartc3323802012-12-15 23:51:55 +0100[diff] [blame]25#include "sh_pfc.h"
26
Laurent Pinchartd5b15212012-12-15 23:51:21 +0100[diff] [blame]27#define CPU_ALL_PORT(fn, pfx, sfx) \
28 PORT_10(fn, pfx, sfx), PORT_90(fn, pfx, sfx), \
29 PORT_10(fn, pfx##10, sfx), PORT_90(fn, pfx##1, sfx), \
30 PORT_10(fn, pfx##20, sfx), \
31 PORT_1(fn, pfx##210, sfx), PORT_1(fn, pfx##211, sfx)
32
Laurent Pinchart7d568452013-04-23 00:36:40 +0200[diff] [blame^]33#undef _GPIO_PORT
34#define _GPIO_PORT(gpio, sfx) \
35 [gpio] = { \
36 .name = __stringify(PORT##gpio), \
37 .enum_id = PORT##gpio##_DATA, \
38 }
39
Bastian Hecht09bbc1f2013-04-09 10:48:50 +0000[diff] [blame]40#define IRQC_PIN_MUX(irq, pin) \
41static const unsigned int intc_irq##irq##_pins[] = { \
42 pin, \
43}; \
44static const unsigned int intc_irq##irq##_mux[] = { \
45 IRQ##irq##_MARK, \
46}
47
48#define IRQC_PINS_MUX(irq, idx, pin) \
49static const unsigned int intc_irq##irq##_##idx##_pins[] = { \
50 pin, \
51}; \
52static const unsigned int intc_irq##irq##_##idx##_mux[] = { \
53 IRQ##irq##_PORT##pin##_MARK, \
54}
55
Laurent Pinchartd5b15212012-12-15 23:51:21 +0100[diff] [blame]56enum {
57 PINMUX_RESERVED = 0,
58
59 /* PORT0_DATA -> PORT211_DATA */
60 PINMUX_DATA_BEGIN,
61 PORT_ALL(DATA),
62 PINMUX_DATA_END,
63
64 /* PORT0_IN -> PORT211_IN */
65 PINMUX_INPUT_BEGIN,
66 PORT_ALL(IN),
67 PINMUX_INPUT_END,
68
69 /* PORT0_IN_PU -> PORT211_IN_PU */
70 PINMUX_INPUT_PULLUP_BEGIN,
71 PORT_ALL(IN_PU),
72 PINMUX_INPUT_PULLUP_END,
73
74 /* PORT0_IN_PD -> PORT211_IN_PD */
75 PINMUX_INPUT_PULLDOWN_BEGIN,
76 PORT_ALL(IN_PD),
77 PINMUX_INPUT_PULLDOWN_END,
78
79 /* PORT0_OUT -> PORT211_OUT */
80 PINMUX_OUTPUT_BEGIN,
81 PORT_ALL(OUT),
82 PINMUX_OUTPUT_END,
83
84 PINMUX_FUNCTION_BEGIN,
85 PORT_ALL(FN_IN), /* PORT0_FN_IN -> PORT211_FN_IN */
86 PORT_ALL(FN_OUT), /* PORT0_FN_OUT -> PORT211_FN_OUT */
87 PORT_ALL(FN0), /* PORT0_FN0 -> PORT211_FN0 */
88 PORT_ALL(FN1), /* PORT0_FN1 -> PORT211_FN1 */
89 PORT_ALL(FN2), /* PORT0_FN2 -> PORT211_FN2 */
90 PORT_ALL(FN3), /* PORT0_FN3 -> PORT211_FN3 */
91 PORT_ALL(FN4), /* PORT0_FN4 -> PORT211_FN4 */
92 PORT_ALL(FN5), /* PORT0_FN5 -> PORT211_FN5 */
93 PORT_ALL(FN6), /* PORT0_FN6 -> PORT211_FN6 */
94 PORT_ALL(FN7), /* PORT0_FN7 -> PORT211_FN7 */
95
96 MSEL1CR_31_0, MSEL1CR_31_1,
97 MSEL1CR_30_0, MSEL1CR_30_1,
98 MSEL1CR_29_0, MSEL1CR_29_1,
99 MSEL1CR_28_0, MSEL1CR_28_1,
100 MSEL1CR_27_0, MSEL1CR_27_1,
101 MSEL1CR_26_0, MSEL1CR_26_1,
102 MSEL1CR_16_0, MSEL1CR_16_1,
103 MSEL1CR_15_0, MSEL1CR_15_1,
104 MSEL1CR_14_0, MSEL1CR_14_1,
105 MSEL1CR_13_0, MSEL1CR_13_1,
106 MSEL1CR_12_0, MSEL1CR_12_1,
107 MSEL1CR_9_0, MSEL1CR_9_1,
108 MSEL1CR_7_0, MSEL1CR_7_1,
109 MSEL1CR_6_0, MSEL1CR_6_1,
110 MSEL1CR_5_0, MSEL1CR_5_1,
111 MSEL1CR_4_0, MSEL1CR_4_1,
112 MSEL1CR_3_0, MSEL1CR_3_1,
113 MSEL1CR_2_0, MSEL1CR_2_1,
114 MSEL1CR_0_0, MSEL1CR_0_1,
115
116 MSEL3CR_15_0, MSEL3CR_15_1, /* Trace / Debug ? */
117 MSEL3CR_6_0, MSEL3CR_6_1,
118
119 MSEL4CR_19_0, MSEL4CR_19_1,
120 MSEL4CR_18_0, MSEL4CR_18_1,
121 MSEL4CR_15_0, MSEL4CR_15_1,
122 MSEL4CR_10_0, MSEL4CR_10_1,
123 MSEL4CR_6_0, MSEL4CR_6_1,
124 MSEL4CR_4_0, MSEL4CR_4_1,
125 MSEL4CR_1_0, MSEL4CR_1_1,
126
127 MSEL5CR_31_0, MSEL5CR_31_1, /* irq/fiq output */
128 MSEL5CR_30_0, MSEL5CR_30_1,
129 MSEL5CR_29_0, MSEL5CR_29_1,
130 MSEL5CR_27_0, MSEL5CR_27_1,
131 MSEL5CR_25_0, MSEL5CR_25_1,
132 MSEL5CR_23_0, MSEL5CR_23_1,
133 MSEL5CR_21_0, MSEL5CR_21_1,
134 MSEL5CR_19_0, MSEL5CR_19_1,
135 MSEL5CR_17_0, MSEL5CR_17_1,
136 MSEL5CR_15_0, MSEL5CR_15_1,
137 MSEL5CR_14_0, MSEL5CR_14_1,
138 MSEL5CR_13_0, MSEL5CR_13_1,
139 MSEL5CR_12_0, MSEL5CR_12_1,
140 MSEL5CR_11_0, MSEL5CR_11_1,
141 MSEL5CR_10_0, MSEL5CR_10_1,
142 MSEL5CR_8_0, MSEL5CR_8_1,
143 MSEL5CR_7_0, MSEL5CR_7_1,
144 MSEL5CR_6_0, MSEL5CR_6_1,
145 MSEL5CR_5_0, MSEL5CR_5_1,
146 MSEL5CR_4_0, MSEL5CR_4_1,
147 MSEL5CR_3_0, MSEL5CR_3_1,
148 MSEL5CR_2_0, MSEL5CR_2_1,
149 MSEL5CR_0_0, MSEL5CR_0_1,
150 PINMUX_FUNCTION_END,
151
152 PINMUX_MARK_BEGIN,
153
154 /* IRQ */
155 IRQ0_PORT2_MARK, IRQ0_PORT13_MARK,
156 IRQ1_MARK,
157 IRQ2_PORT11_MARK, IRQ2_PORT12_MARK,
158 IRQ3_PORT10_MARK, IRQ3_PORT14_MARK,
159 IRQ4_PORT15_MARK, IRQ4_PORT172_MARK,
160 IRQ5_PORT0_MARK, IRQ5_PORT1_MARK,
161 IRQ6_PORT121_MARK, IRQ6_PORT173_MARK,
162 IRQ7_PORT120_MARK, IRQ7_PORT209_MARK,
163 IRQ8_MARK,
164 IRQ9_PORT118_MARK, IRQ9_PORT210_MARK,
165 IRQ10_MARK,
166 IRQ11_MARK,
167 IRQ12_PORT42_MARK, IRQ12_PORT97_MARK,
168 IRQ13_PORT64_MARK, IRQ13_PORT98_MARK,
169 IRQ14_PORT63_MARK, IRQ14_PORT99_MARK,
170 IRQ15_PORT62_MARK, IRQ15_PORT100_MARK,
171 IRQ16_PORT68_MARK, IRQ16_PORT211_MARK,
172 IRQ17_MARK,
173 IRQ18_MARK,
174 IRQ19_MARK,
175 IRQ20_MARK,
176 IRQ21_MARK,
177 IRQ22_MARK,
178 IRQ23_MARK,
179 IRQ24_MARK,
180 IRQ25_MARK,
181 IRQ26_PORT58_MARK, IRQ26_PORT81_MARK,
182 IRQ27_PORT57_MARK, IRQ27_PORT168_MARK,
183 IRQ28_PORT56_MARK, IRQ28_PORT169_MARK,
184 IRQ29_PORT50_MARK, IRQ29_PORT170_MARK,
185 IRQ30_PORT49_MARK, IRQ30_PORT171_MARK,
186 IRQ31_PORT41_MARK, IRQ31_PORT167_MARK,
187
188 /* Function */
189
190 /* DBGT */
191 DBGMDT2_MARK, DBGMDT1_MARK, DBGMDT0_MARK,
192 DBGMD10_MARK, DBGMD11_MARK, DBGMD20_MARK,
193 DBGMD21_MARK,
194
195 /* FSI-A */
196 FSIAISLD_PORT0_MARK, /* FSIAISLD Port 0/5 */
197 FSIAISLD_PORT5_MARK,
198 FSIASPDIF_PORT9_MARK, /* FSIASPDIF Port 9/18 */
199 FSIASPDIF_PORT18_MARK,
200 FSIAOSLD1_MARK, FSIAOSLD2_MARK, FSIAOLR_MARK,
201 FSIAOBT_MARK, FSIAOSLD_MARK, FSIAOMC_MARK,
202 FSIACK_MARK, FSIAILR_MARK, FSIAIBT_MARK,
203
204 /* FSI-B */
205 FSIBCK_MARK,
206
207 /* FMSI */
208 FMSISLD_PORT1_MARK, /* FMSISLD Port 1/6 */
209 FMSISLD_PORT6_MARK,
210 FMSIILR_MARK, FMSIIBT_MARK, FMSIOLR_MARK, FMSIOBT_MARK,
211 FMSICK_MARK, FMSOILR_MARK, FMSOIBT_MARK, FMSOOLR_MARK,
212 FMSOOBT_MARK, FMSOSLD_MARK, FMSOCK_MARK,
213
214 /* SCIFA0 */
215 SCIFA0_SCK_MARK, SCIFA0_CTS_MARK, SCIFA0_RTS_MARK,
216 SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
217
218 /* SCIFA1 */
219 SCIFA1_CTS_MARK, SCIFA1_SCK_MARK, SCIFA1_RXD_MARK,
220 SCIFA1_TXD_MARK, SCIFA1_RTS_MARK,
221
222 /* SCIFA2 */
223 SCIFA2_SCK_PORT22_MARK, /* SCIFA2_SCK Port 22/199 */
224 SCIFA2_SCK_PORT199_MARK,
225 SCIFA2_RXD_MARK, SCIFA2_TXD_MARK,
226 SCIFA2_CTS_MARK, SCIFA2_RTS_MARK,
227
228 /* SCIFA3 */
229 SCIFA3_RTS_PORT105_MARK, /* MSEL5CR_8_0 */
230 SCIFA3_SCK_PORT116_MARK,
231 SCIFA3_CTS_PORT117_MARK,
232 SCIFA3_RXD_PORT174_MARK,
233 SCIFA3_TXD_PORT175_MARK,
234
235 SCIFA3_RTS_PORT161_MARK, /* MSEL5CR_8_1 */
236 SCIFA3_SCK_PORT158_MARK,
237 SCIFA3_CTS_PORT162_MARK,
238 SCIFA3_RXD_PORT159_MARK,
239 SCIFA3_TXD_PORT160_MARK,
240
241 /* SCIFA4 */
242 SCIFA4_RXD_PORT12_MARK, /* MSEL5CR[12:11] = 00 */
243 SCIFA4_TXD_PORT13_MARK,
244
245 SCIFA4_RXD_PORT204_MARK, /* MSEL5CR[12:11] = 01 */
246 SCIFA4_TXD_PORT203_MARK,
247
248 SCIFA4_RXD_PORT94_MARK, /* MSEL5CR[12:11] = 10 */
249 SCIFA4_TXD_PORT93_MARK,
250
251 SCIFA4_SCK_PORT21_MARK, /* SCIFA4_SCK Port 21/205 */
252 SCIFA4_SCK_PORT205_MARK,
253
254 /* SCIFA5 */
255 SCIFA5_TXD_PORT20_MARK, /* MSEL5CR[15:14] = 00 */
256 SCIFA5_RXD_PORT10_MARK,
257
258 SCIFA5_RXD_PORT207_MARK, /* MSEL5CR[15:14] = 01 */
259 SCIFA5_TXD_PORT208_MARK,
260
261 SCIFA5_TXD_PORT91_MARK, /* MSEL5CR[15:14] = 10 */
262 SCIFA5_RXD_PORT92_MARK,
263
264 SCIFA5_SCK_PORT23_MARK, /* SCIFA5_SCK Port 23/206 */
265 SCIFA5_SCK_PORT206_MARK,
266
267 /* SCIFA6 */
268 SCIFA6_SCK_MARK, SCIFA6_RXD_MARK, SCIFA6_TXD_MARK,
269
270 /* SCIFA7 */
271 SCIFA7_TXD_MARK, SCIFA7_RXD_MARK,
272
273 /* SCIFAB */
274 SCIFB_SCK_PORT190_MARK, /* MSEL5CR_17_0 */
275 SCIFB_RXD_PORT191_MARK,
276 SCIFB_TXD_PORT192_MARK,
277 SCIFB_RTS_PORT186_MARK,
278 SCIFB_CTS_PORT187_MARK,
279
280 SCIFB_SCK_PORT2_MARK, /* MSEL5CR_17_1 */
281 SCIFB_RXD_PORT3_MARK,
282 SCIFB_TXD_PORT4_MARK,
283 SCIFB_RTS_PORT172_MARK,
284 SCIFB_CTS_PORT173_MARK,
285
286 /* LCD0 */
Laurent Pinchartd5b15212012-12-15 23:51:21 +0100[diff] [blame]287 LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
288 LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
289 LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
290 LCD0_D12_MARK, LCD0_D13_MARK, LCD0_D14_MARK, LCD0_D15_MARK,
291 LCD0_D16_MARK, LCD0_D17_MARK,
292 LCD0_DON_MARK, LCD0_VCPWC_MARK, LCD0_VEPWC_MARK,
293 LCD0_DCK_MARK, LCD0_VSYN_MARK, /* for RGB */
294 LCD0_HSYN_MARK, LCD0_DISP_MARK, /* for RGB */
295 LCD0_WR_MARK, LCD0_RD_MARK, /* for SYS */
296 LCD0_CS_MARK, LCD0_RS_MARK, /* for SYS */
297
298 LCD0_D21_PORT158_MARK, LCD0_D23_PORT159_MARK, /* MSEL5CR_6_1 */
299 LCD0_D22_PORT160_MARK, LCD0_D20_PORT161_MARK,
300 LCD0_D19_PORT162_MARK, LCD0_D18_PORT163_MARK,
301 LCD0_LCLK_PORT165_MARK,
302
303 LCD0_D18_PORT40_MARK, LCD0_D22_PORT0_MARK, /* MSEL5CR_6_0 */
304 LCD0_D23_PORT1_MARK, LCD0_D21_PORT2_MARK,
305 LCD0_D20_PORT3_MARK, LCD0_D19_PORT4_MARK,
306 LCD0_LCLK_PORT102_MARK,
307
308 /* LCD1 */
Laurent Pinchartd5b15212012-12-15 23:51:21 +0100[diff] [blame]309 LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
310 LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
311 LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
312 LCD1_D12_MARK, LCD1_D13_MARK, LCD1_D14_MARK, LCD1_D15_MARK,
313 LCD1_D16_MARK, LCD1_D17_MARK, LCD1_D18_MARK, LCD1_D19_MARK,
314 LCD1_D20_MARK, LCD1_D21_MARK, LCD1_D22_MARK, LCD1_D23_MARK,
315 LCD1_DON_MARK, LCD1_VCPWC_MARK,
316 LCD1_LCLK_MARK, LCD1_VEPWC_MARK,
317
318 LCD1_DCK_MARK, LCD1_VSYN_MARK, /* for RGB */
319 LCD1_HSYN_MARK, LCD1_DISP_MARK, /* for RGB */
320 LCD1_RS_MARK, LCD1_CS_MARK, /* for SYS */
321 LCD1_RD_MARK, LCD1_WR_MARK, /* for SYS */
322
323 /* RSPI */
324 RSPI_SSL0_A_MARK, RSPI_SSL1_A_MARK, RSPI_SSL2_A_MARK,
325 RSPI_SSL3_A_MARK, RSPI_CK_A_MARK, RSPI_MOSI_A_MARK,
326 RSPI_MISO_A_MARK,
327
328 /* VIO CKO */
329 VIO_CKO1_MARK, /* needs fixup */
330 VIO_CKO2_MARK,
331 VIO_CKO_1_MARK,
332 VIO_CKO_MARK,
333
334 /* VIO0 */
335 VIO0_D0_MARK, VIO0_D1_MARK, VIO0_D2_MARK, VIO0_D3_MARK,
336 VIO0_D4_MARK, VIO0_D5_MARK, VIO0_D6_MARK, VIO0_D7_MARK,
337 VIO0_D8_MARK, VIO0_D9_MARK, VIO0_D10_MARK, VIO0_D11_MARK,
338 VIO0_D12_MARK, VIO0_VD_MARK, VIO0_HD_MARK, VIO0_CLK_MARK,
339 VIO0_FIELD_MARK,
340
341 VIO0_D13_PORT26_MARK, /* MSEL5CR_27_0 */
342 VIO0_D14_PORT25_MARK,
343 VIO0_D15_PORT24_MARK,
344
345 VIO0_D13_PORT22_MARK, /* MSEL5CR_27_1 */
346 VIO0_D14_PORT95_MARK,
347 VIO0_D15_PORT96_MARK,
348
349 /* VIO1 */
350 VIO1_D0_MARK, VIO1_D1_MARK, VIO1_D2_MARK, VIO1_D3_MARK,
351 VIO1_D4_MARK, VIO1_D5_MARK, VIO1_D6_MARK, VIO1_D7_MARK,
352 VIO1_VD_MARK, VIO1_HD_MARK, VIO1_CLK_MARK, VIO1_FIELD_MARK,
353
354 /* TPU0 */
355 TPU0TO0_MARK, TPU0TO1_MARK, TPU0TO3_MARK,
356 TPU0TO2_PORT66_MARK, /* TPU0TO2 Port 66/202 */
357 TPU0TO2_PORT202_MARK,
358
359 /* SSP1 0 */
360 STP0_IPD0_MARK, STP0_IPD1_MARK, STP0_IPD2_MARK, STP0_IPD3_MARK,
361 STP0_IPD4_MARK, STP0_IPD5_MARK, STP0_IPD6_MARK, STP0_IPD7_MARK,
362 STP0_IPEN_MARK, STP0_IPCLK_MARK, STP0_IPSYNC_MARK,
363
364 /* SSP1 1 */
365 STP1_IPD1_MARK, STP1_IPD2_MARK, STP1_IPD3_MARK, STP1_IPD4_MARK,
366 STP1_IPD5_MARK, STP1_IPD6_MARK, STP1_IPD7_MARK, STP1_IPCLK_MARK,
367 STP1_IPSYNC_MARK,
368
369 STP1_IPD0_PORT186_MARK, /* MSEL5CR_23_0 */
370 STP1_IPEN_PORT187_MARK,
371
372 STP1_IPD0_PORT194_MARK, /* MSEL5CR_23_1 */
373 STP1_IPEN_PORT193_MARK,
374
375 /* SIM */
376 SIM_RST_MARK, SIM_CLK_MARK,
377 SIM_D_PORT22_MARK, /* SIM_D Port 22/199 */
378 SIM_D_PORT199_MARK,
379
380 /* SDHI0 */
381 SDHI0_D0_MARK, SDHI0_D1_MARK, SDHI0_D2_MARK, SDHI0_D3_MARK,
382 SDHI0_CD_MARK, SDHI0_WP_MARK, SDHI0_CMD_MARK, SDHI0_CLK_MARK,
383
384 /* SDHI1 */
385 SDHI1_D0_MARK, SDHI1_D1_MARK, SDHI1_D2_MARK, SDHI1_D3_MARK,
386 SDHI1_CD_MARK, SDHI1_WP_MARK, SDHI1_CMD_MARK, SDHI1_CLK_MARK,
387
388 /* SDHI2 */
389 SDHI2_D0_MARK, SDHI2_D1_MARK, SDHI2_D2_MARK, SDHI2_D3_MARK,
390 SDHI2_CLK_MARK, SDHI2_CMD_MARK,
391
392 SDHI2_CD_PORT24_MARK, /* MSEL5CR_19_0 */
393 SDHI2_WP_PORT25_MARK,
394
395 SDHI2_WP_PORT177_MARK, /* MSEL5CR_19_1 */
396 SDHI2_CD_PORT202_MARK,
397
398 /* MSIOF2 */
399 MSIOF2_TXD_MARK, MSIOF2_RXD_MARK, MSIOF2_TSCK_MARK,
400 MSIOF2_SS2_MARK, MSIOF2_TSYNC_MARK, MSIOF2_SS1_MARK,
401 MSIOF2_MCK1_MARK, MSIOF2_MCK0_MARK, MSIOF2_RSYNC_MARK,
402 MSIOF2_RSCK_MARK,
403
404 /* KEYSC */
405 KEYIN4_MARK, KEYIN5_MARK, KEYIN6_MARK, KEYIN7_MARK,
406 KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK,
407 KEYOUT4_MARK, KEYOUT5_MARK, KEYOUT6_MARK, KEYOUT7_MARK,
408
409 KEYIN0_PORT43_MARK, /* MSEL4CR_18_0 */
410 KEYIN1_PORT44_MARK,
411 KEYIN2_PORT45_MARK,
412 KEYIN3_PORT46_MARK,
413
414 KEYIN0_PORT58_MARK, /* MSEL4CR_18_1 */
415 KEYIN1_PORT57_MARK,
416 KEYIN2_PORT56_MARK,
417 KEYIN3_PORT55_MARK,
418
419 /* VOU */
420 DV_D0_MARK, DV_D1_MARK, DV_D2_MARK, DV_D3_MARK,
421 DV_D4_MARK, DV_D5_MARK, DV_D6_MARK, DV_D7_MARK,
422 DV_D8_MARK, DV_D9_MARK, DV_D10_MARK, DV_D11_MARK,
423 DV_D12_MARK, DV_D13_MARK, DV_D14_MARK, DV_D15_MARK,
424 DV_CLK_MARK, DV_VSYNC_MARK, DV_HSYNC_MARK,
425
426 /* MEMC */
427 MEMC_AD0_MARK, MEMC_AD1_MARK, MEMC_AD2_MARK, MEMC_AD3_MARK,
428 MEMC_AD4_MARK, MEMC_AD5_MARK, MEMC_AD6_MARK, MEMC_AD7_MARK,
429 MEMC_AD8_MARK, MEMC_AD9_MARK, MEMC_AD10_MARK, MEMC_AD11_MARK,
430 MEMC_AD12_MARK, MEMC_AD13_MARK, MEMC_AD14_MARK, MEMC_AD15_MARK,
431 MEMC_CS0_MARK, MEMC_INT_MARK, MEMC_NWE_MARK, MEMC_NOE_MARK,
432
433 MEMC_CS1_MARK, /* MSEL4CR_6_0 */
434 MEMC_ADV_MARK,
435 MEMC_WAIT_MARK,
436 MEMC_BUSCLK_MARK,
437
438 MEMC_A1_MARK, /* MSEL4CR_6_1 */
439 MEMC_DREQ0_MARK,
440 MEMC_DREQ1_MARK,
441 MEMC_A0_MARK,
442
443 /* MMC */
444 MMC0_D0_PORT68_MARK, MMC0_D1_PORT69_MARK, MMC0_D2_PORT70_MARK,
445 MMC0_D3_PORT71_MARK, MMC0_D4_PORT72_MARK, MMC0_D5_PORT73_MARK,
446 MMC0_D6_PORT74_MARK, MMC0_D7_PORT75_MARK, MMC0_CLK_PORT66_MARK,
447 MMC0_CMD_PORT67_MARK, /* MSEL4CR_15_0 */
448
449 MMC1_D0_PORT149_MARK, MMC1_D1_PORT148_MARK, MMC1_D2_PORT147_MARK,
450 MMC1_D3_PORT146_MARK, MMC1_D4_PORT145_MARK, MMC1_D5_PORT144_MARK,
451 MMC1_D6_PORT143_MARK, MMC1_D7_PORT142_MARK, MMC1_CLK_PORT103_MARK,
452 MMC1_CMD_PORT104_MARK, /* MSEL4CR_15_1 */
453
454 /* MSIOF0 */
455 MSIOF0_SS1_MARK, MSIOF0_SS2_MARK, MSIOF0_RXD_MARK,
456 MSIOF0_TXD_MARK, MSIOF0_MCK0_MARK, MSIOF0_MCK1_MARK,
457 MSIOF0_RSYNC_MARK, MSIOF0_RSCK_MARK, MSIOF0_TSCK_MARK,
458 MSIOF0_TSYNC_MARK,
459
460 /* MSIOF1 */
461 MSIOF1_RSCK_MARK, MSIOF1_RSYNC_MARK,
462 MSIOF1_MCK0_MARK, MSIOF1_MCK1_MARK,
463
464 MSIOF1_SS2_PORT116_MARK, MSIOF1_SS1_PORT117_MARK,
465 MSIOF1_RXD_PORT118_MARK, MSIOF1_TXD_PORT119_MARK,
466 MSIOF1_TSYNC_PORT120_MARK,
467 MSIOF1_TSCK_PORT121_MARK, /* MSEL4CR_10_0 */
468
469 MSIOF1_SS1_PORT67_MARK, MSIOF1_TSCK_PORT72_MARK,
470 MSIOF1_TSYNC_PORT73_MARK, MSIOF1_TXD_PORT74_MARK,
471 MSIOF1_RXD_PORT75_MARK,
472 MSIOF1_SS2_PORT202_MARK, /* MSEL4CR_10_1 */
473
474 /* GPIO */
475 GPO0_MARK, GPI0_MARK, GPO1_MARK, GPI1_MARK,
476
477 /* USB0 */
478 USB0_OCI_MARK, USB0_PPON_MARK, VBUS_MARK,
479
480 /* USB1 */
481 USB1_OCI_MARK, USB1_PPON_MARK,
482
483 /* BBIF1 */
484 BBIF1_RXD_MARK, BBIF1_TXD_MARK, BBIF1_TSYNC_MARK,
485 BBIF1_TSCK_MARK, BBIF1_RSCK_MARK, BBIF1_RSYNC_MARK,
486 BBIF1_FLOW_MARK, BBIF1_RX_FLOW_N_MARK,
487
488 /* BBIF2 */
489 BBIF2_TXD2_PORT5_MARK, /* MSEL5CR_0_0 */
490 BBIF2_RXD2_PORT60_MARK,
491 BBIF2_TSYNC2_PORT6_MARK,
492 BBIF2_TSCK2_PORT59_MARK,
493
494 BBIF2_RXD2_PORT90_MARK, /* MSEL5CR_0_1 */
495 BBIF2_TXD2_PORT183_MARK,
496 BBIF2_TSCK2_PORT89_MARK,
497 BBIF2_TSYNC2_PORT184_MARK,
498
499 /* BSC / FLCTL / PCMCIA */
500 CS0_MARK, CS2_MARK, CS4_MARK,
501 CS5B_MARK, CS6A_MARK,
502 CS5A_PORT105_MARK, /* CS5A PORT 19/105 */
503 CS5A_PORT19_MARK,
504 IOIS16_MARK, /* ? */
505
506 A0_MARK, A1_MARK, A2_MARK, A3_MARK,
507 A4_FOE_MARK, /* share with FLCTL */
508 A5_FCDE_MARK, /* share with FLCTL */
509 A6_MARK, A7_MARK, A8_MARK, A9_MARK,
510 A10_MARK, A11_MARK, A12_MARK, A13_MARK,
511 A14_MARK, A15_MARK, A16_MARK, A17_MARK,
512 A18_MARK, A19_MARK, A20_MARK, A21_MARK,
513 A22_MARK, A23_MARK, A24_MARK, A25_MARK,
514 A26_MARK,
515
516 D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, /* share with FLCTL */
517 D3_NAF3_MARK, D4_NAF4_MARK, D5_NAF5_MARK, /* share with FLCTL */
518 D6_NAF6_MARK, D7_NAF7_MARK, D8_NAF8_MARK, /* share with FLCTL */
519 D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK, /* share with FLCTL */
520 D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, /* share with FLCTL */
521 D15_NAF15_MARK, /* share with FLCTL */
522 D16_MARK, D17_MARK, D18_MARK, D19_MARK,
523 D20_MARK, D21_MARK, D22_MARK, D23_MARK,
524 D24_MARK, D25_MARK, D26_MARK, D27_MARK,
525 D28_MARK, D29_MARK, D30_MARK, D31_MARK,
526
527 WE0_FWE_MARK, /* share with FLCTL */
528 WE1_MARK,
529 WE2_ICIORD_MARK, /* share with PCMCIA */
530 WE3_ICIOWR_MARK, /* share with PCMCIA */
531 CKO_MARK, BS_MARK, RDWR_MARK,
532 RD_FSC_MARK, /* share with FLCTL */
533 WAIT_PORT177_MARK, /* WAIT Port 90/177 */
534 WAIT_PORT90_MARK,
535
536 FCE0_MARK, FCE1_MARK, FRB_MARK, /* FLCTL */
537
538 /* IRDA */
539 IRDA_FIRSEL_MARK, IRDA_IN_MARK, IRDA_OUT_MARK,
540
541 /* ATAPI */
542 IDE_D0_MARK, IDE_D1_MARK, IDE_D2_MARK, IDE_D3_MARK,
543 IDE_D4_MARK, IDE_D5_MARK, IDE_D6_MARK, IDE_D7_MARK,
544 IDE_D8_MARK, IDE_D9_MARK, IDE_D10_MARK, IDE_D11_MARK,
545 IDE_D12_MARK, IDE_D13_MARK, IDE_D14_MARK, IDE_D15_MARK,
546 IDE_A0_MARK, IDE_A1_MARK, IDE_A2_MARK, IDE_CS0_MARK,
547 IDE_CS1_MARK, IDE_IOWR_MARK, IDE_IORD_MARK, IDE_IORDY_MARK,
548 IDE_INT_MARK, IDE_RST_MARK, IDE_DIRECTION_MARK,
549 IDE_EXBUF_ENB_MARK, IDE_IODACK_MARK, IDE_IODREQ_MARK,
550
551 /* RMII */
552 RMII_CRS_DV_MARK, RMII_RX_ER_MARK, RMII_RXD0_MARK,
553 RMII_RXD1_MARK, RMII_TX_EN_MARK, RMII_TXD0_MARK,
554 RMII_MDC_MARK, RMII_TXD1_MARK, RMII_MDIO_MARK,
555 RMII_REF50CK_MARK, /* for RMII */
556 RMII_REF125CK_MARK, /* for GMII */
557
558 /* GEther */
559 ET_TX_CLK_MARK, ET_TX_EN_MARK, ET_ETXD0_MARK, ET_ETXD1_MARK,
560 ET_ETXD2_MARK, ET_ETXD3_MARK,
561 ET_ETXD4_MARK, ET_ETXD5_MARK, /* for GEther */
562 ET_ETXD6_MARK, ET_ETXD7_MARK, /* for GEther */
563 ET_COL_MARK, ET_TX_ER_MARK, ET_RX_CLK_MARK, ET_RX_DV_MARK,
564 ET_ERXD0_MARK, ET_ERXD1_MARK, ET_ERXD2_MARK, ET_ERXD3_MARK,
565 ET_ERXD4_MARK, ET_ERXD5_MARK, /* for GEther */
566 ET_ERXD6_MARK, ET_ERXD7_MARK, /* for GEther */
567 ET_RX_ER_MARK, ET_CRS_MARK, ET_MDC_MARK, ET_MDIO_MARK,
568 ET_LINK_MARK, ET_PHY_INT_MARK, ET_WOL_MARK, ET_GTX_CLK_MARK,
569
570 /* DMA0 */
571 DREQ0_MARK, DACK0_MARK,
572
573 /* DMA1 */
574 DREQ1_MARK, DACK1_MARK,
575
576 /* SYSC */
577 RESETOUTS_MARK, RESETP_PULLUP_MARK, RESETP_PLAIN_MARK,
578
579 /* IRREM */
580 IROUT_MARK,
581
582 /* SDENC */
583 SDENC_CPG_MARK, SDENC_DV_CLKI_MARK,
584
585 /* HDMI */
586 HDMI_HPD_MARK, HDMI_CEC_MARK,
587
588 /* DEBUG */
589 EDEBGREQ_PULLUP_MARK, /* for JTAG */
590 EDEBGREQ_PULLDOWN_MARK,
591
592 TRACEAUD_FROM_VIO_MARK, /* for TRACE/AUD */
593 TRACEAUD_FROM_LCDC0_MARK,
594 TRACEAUD_FROM_MEMC_MARK,
595
596 PINMUX_MARK_END,
597};
598
Laurent Pinchartcd3c1be2013-02-16 18:47:05 +0100[diff] [blame]599static const pinmux_enum_t pinmux_data[] = {
Laurent Pinchartd5b15212012-12-15 23:51:21 +0100[diff] [blame]600 /* specify valid pin states for each pin in GPIO mode */
601
602 /* I/O and Pull U/D */
603 PORT_DATA_IO_PD(0), PORT_DATA_IO_PD(1),
604 PORT_DATA_IO_PD(2), PORT_DATA_IO_PD(3),
605 PORT_DATA_IO_PD(4), PORT_DATA_IO_PD(5),
606 PORT_DATA_IO_PD(6), PORT_DATA_IO(7),
607 PORT_DATA_IO(8), PORT_DATA_IO(9),
608
609 PORT_DATA_IO_PD(10), PORT_DATA_IO_PD(11),
610 PORT_DATA_IO_PD(12), PORT_DATA_IO_PU_PD(13),
611 PORT_DATA_IO_PD(14), PORT_DATA_IO_PD(15),
612 PORT_DATA_IO_PD(16), PORT_DATA_IO_PD(17),
613 PORT_DATA_IO(18), PORT_DATA_IO_PU(19),
614
615 PORT_DATA_IO_PU_PD(20), PORT_DATA_IO_PD(21),
616 PORT_DATA_IO_PU_PD(22), PORT_DATA_IO(23),
617 PORT_DATA_IO_PU(24), PORT_DATA_IO_PU(25),
618 PORT_DATA_IO_PU(26), PORT_DATA_IO_PU(27),
619 PORT_DATA_IO_PU(28), PORT_DATA_IO_PU(29),
620
621 PORT_DATA_IO_PU(30), PORT_DATA_IO_PD(31),
622 PORT_DATA_IO_PD(32), PORT_DATA_IO_PD(33),
623 PORT_DATA_IO_PD(34), PORT_DATA_IO_PU(35),
624 PORT_DATA_IO_PU(36), PORT_DATA_IO_PD(37),
625 PORT_DATA_IO_PU(38), PORT_DATA_IO_PD(39),
626
627 PORT_DATA_IO_PU_PD(40), PORT_DATA_IO_PD(41),
628 PORT_DATA_IO_PD(42), PORT_DATA_IO_PU_PD(43),
629 PORT_DATA_IO_PU_PD(44), PORT_DATA_IO_PU_PD(45),
630 PORT_DATA_IO_PU_PD(46), PORT_DATA_IO_PU_PD(47),
631 PORT_DATA_IO_PU_PD(48), PORT_DATA_IO_PU_PD(49),
632
633 PORT_DATA_IO_PU_PD(50), PORT_DATA_IO_PD(51),
634 PORT_DATA_IO_PD(52), PORT_DATA_IO_PD(53),
635 PORT_DATA_IO_PD(54), PORT_DATA_IO_PU_PD(55),
636 PORT_DATA_IO_PU_PD(56), PORT_DATA_IO_PU_PD(57),
637 PORT_DATA_IO_PU_PD(58), PORT_DATA_IO_PU_PD(59),
638
639 PORT_DATA_IO_PU_PD(60), PORT_DATA_IO_PD(61),
640 PORT_DATA_IO_PD(62), PORT_DATA_IO_PD(63),
641 PORT_DATA_IO_PD(64), PORT_DATA_IO_PD(65),
642 PORT_DATA_IO_PU_PD(66), PORT_DATA_IO_PU_PD(67),
643 PORT_DATA_IO_PU_PD(68), PORT_DATA_IO_PU_PD(69),
644
645 PORT_DATA_IO_PU_PD(70), PORT_DATA_IO_PU_PD(71),
646 PORT_DATA_IO_PU_PD(72), PORT_DATA_IO_PU_PD(73),
647 PORT_DATA_IO_PU_PD(74), PORT_DATA_IO_PU_PD(75),
648 PORT_DATA_IO_PU_PD(76), PORT_DATA_IO_PU_PD(77),
649 PORT_DATA_IO_PU_PD(78), PORT_DATA_IO_PU_PD(79),
650
651 PORT_DATA_IO_PU_PD(80), PORT_DATA_IO_PU_PD(81),
652 PORT_DATA_IO(82), PORT_DATA_IO_PU_PD(83),
653 PORT_DATA_IO(84), PORT_DATA_IO_PD(85),
654 PORT_DATA_IO_PD(86), PORT_DATA_IO_PD(87),
655 PORT_DATA_IO_PD(88), PORT_DATA_IO_PD(89),
656
657 PORT_DATA_IO_PD(90), PORT_DATA_IO_PU_PD(91),
658 PORT_DATA_IO_PU_PD(92), PORT_DATA_IO_PU_PD(93),
659 PORT_DATA_IO_PU_PD(94), PORT_DATA_IO_PU_PD(95),
660 PORT_DATA_IO_PU_PD(96), PORT_DATA_IO_PU_PD(97),
661 PORT_DATA_IO_PU_PD(98), PORT_DATA_IO_PU_PD(99),
662
663 PORT_DATA_IO_PU_PD(100), PORT_DATA_IO(101),
664 PORT_DATA_IO_PU(102), PORT_DATA_IO_PU_PD(103),
665 PORT_DATA_IO_PU(104), PORT_DATA_IO_PU(105),
666 PORT_DATA_IO_PU_PD(106), PORT_DATA_IO(107),
667 PORT_DATA_IO(108), PORT_DATA_IO(109),
668
669 PORT_DATA_IO(110), PORT_DATA_IO(111),
670 PORT_DATA_IO(112), PORT_DATA_IO(113),
671 PORT_DATA_IO_PU_PD(114), PORT_DATA_IO(115),
672 PORT_DATA_IO_PD(116), PORT_DATA_IO_PD(117),
673 PORT_DATA_IO_PD(118), PORT_DATA_IO_PD(119),
674
675 PORT_DATA_IO_PD(120), PORT_DATA_IO_PD(121),
676 PORT_DATA_IO_PD(122), PORT_DATA_IO_PD(123),
677 PORT_DATA_IO_PD(124), PORT_DATA_IO(125),
678 PORT_DATA_IO(126), PORT_DATA_IO(127),
679 PORT_DATA_IO(128), PORT_DATA_IO(129),
680
681 PORT_DATA_IO(130), PORT_DATA_IO(131),
682 PORT_DATA_IO(132), PORT_DATA_IO(133),
683 PORT_DATA_IO(134), PORT_DATA_IO(135),
684 PORT_DATA_IO(136), PORT_DATA_IO(137),
685 PORT_DATA_IO(138), PORT_DATA_IO(139),
686
687 PORT_DATA_IO(140), PORT_DATA_IO(141),
688 PORT_DATA_IO_PU(142), PORT_DATA_IO_PU(143),
689 PORT_DATA_IO_PU(144), PORT_DATA_IO_PU(145),
690 PORT_DATA_IO_PU(146), PORT_DATA_IO_PU(147),
691 PORT_DATA_IO_PU(148), PORT_DATA_IO_PU(149),
692
693 PORT_DATA_IO_PU(150), PORT_DATA_IO_PU(151),
694 PORT_DATA_IO_PU(152), PORT_DATA_IO_PU(153),
695 PORT_DATA_IO_PU(154), PORT_DATA_IO_PU(155),
696 PORT_DATA_IO_PU(156), PORT_DATA_IO_PU(157),
697 PORT_DATA_IO_PD(158), PORT_DATA_IO_PD(159),
698
699 PORT_DATA_IO_PU_PD(160), PORT_DATA_IO_PD(161),
700 PORT_DATA_IO_PD(162), PORT_DATA_IO_PD(163),
701 PORT_DATA_IO_PD(164), PORT_DATA_IO_PD(165),
702 PORT_DATA_IO_PU(166), PORT_DATA_IO_PU(167),
703 PORT_DATA_IO_PU(168), PORT_DATA_IO_PU(169),
704
705 PORT_DATA_IO_PU(170), PORT_DATA_IO_PU(171),
706 PORT_DATA_IO_PD(172), PORT_DATA_IO_PD(173),
707 PORT_DATA_IO_PD(174), PORT_DATA_IO_PD(175),
708 PORT_DATA_IO_PU(176), PORT_DATA_IO_PU_PD(177),
709 PORT_DATA_IO_PU(178), PORT_DATA_IO_PD(179),
710
711 PORT_DATA_IO_PD(180), PORT_DATA_IO_PU(181),
712 PORT_DATA_IO_PU(182), PORT_DATA_IO(183),
713 PORT_DATA_IO_PD(184), PORT_DATA_IO_PD(185),
714 PORT_DATA_IO_PD(186), PORT_DATA_IO_PD(187),
715 PORT_DATA_IO_PD(188), PORT_DATA_IO_PD(189),
716
717 PORT_DATA_IO_PD(190), PORT_DATA_IO_PD(191),
718 PORT_DATA_IO_PD(192), PORT_DATA_IO_PU_PD(193),
719 PORT_DATA_IO_PU_PD(194), PORT_DATA_IO_PD(195),
720 PORT_DATA_IO_PU_PD(196), PORT_DATA_IO_PD(197),
721 PORT_DATA_IO_PU_PD(198), PORT_DATA_IO_PU_PD(199),
722
723 PORT_DATA_IO_PU_PD(200), PORT_DATA_IO_PU(201),
724 PORT_DATA_IO_PU_PD(202), PORT_DATA_IO(203),
725 PORT_DATA_IO_PU_PD(204), PORT_DATA_IO_PU_PD(205),
726 PORT_DATA_IO_PU_PD(206), PORT_DATA_IO_PU_PD(207),
727 PORT_DATA_IO_PU_PD(208), PORT_DATA_IO_PD(209),
728
729 PORT_DATA_IO_PD(210), PORT_DATA_IO_PD(211),
730
731 /* Port0 */
732 PINMUX_DATA(DBGMDT2_MARK, PORT0_FN1),
733 PINMUX_DATA(FSIAISLD_PORT0_MARK, PORT0_FN2, MSEL5CR_3_0),
734 PINMUX_DATA(FSIAOSLD1_MARK, PORT0_FN3),
735 PINMUX_DATA(LCD0_D22_PORT0_MARK, PORT0_FN4, MSEL5CR_6_0),
736 PINMUX_DATA(SCIFA7_RXD_MARK, PORT0_FN6),
737 PINMUX_DATA(LCD1_D4_MARK, PORT0_FN7),
738 PINMUX_DATA(IRQ5_PORT0_MARK, PORT0_FN0, MSEL1CR_5_0),
739
740 /* Port1 */
741 PINMUX_DATA(DBGMDT1_MARK, PORT1_FN1),
742 PINMUX_DATA(FMSISLD_PORT1_MARK, PORT1_FN2, MSEL5CR_5_0),
743 PINMUX_DATA(FSIAOSLD2_MARK, PORT1_FN3),
744 PINMUX_DATA(LCD0_D23_PORT1_MARK, PORT1_FN4, MSEL5CR_6_0),
745 PINMUX_DATA(SCIFA7_TXD_MARK, PORT1_FN6),
746 PINMUX_DATA(LCD1_D3_MARK, PORT1_FN7),
747 PINMUX_DATA(IRQ5_PORT1_MARK, PORT1_FN0, MSEL1CR_5_1),
748
749 /* Port2 */
750 PINMUX_DATA(DBGMDT0_MARK, PORT2_FN1),
751 PINMUX_DATA(SCIFB_SCK_PORT2_MARK, PORT2_FN2, MSEL5CR_17_1),
752 PINMUX_DATA(LCD0_D21_PORT2_MARK, PORT2_FN4, MSEL5CR_6_0),
753 PINMUX_DATA(LCD1_D2_MARK, PORT2_FN7),
754 PINMUX_DATA(IRQ0_PORT2_MARK, PORT2_FN0, MSEL1CR_0_1),
755
756 /* Port3 */
757 PINMUX_DATA(DBGMD21_MARK, PORT3_FN1),
758 PINMUX_DATA(SCIFB_RXD_PORT3_MARK, PORT3_FN2, MSEL5CR_17_1),
759 PINMUX_DATA(LCD0_D20_PORT3_MARK, PORT3_FN4, MSEL5CR_6_0),
760 PINMUX_DATA(LCD1_D1_MARK, PORT3_FN7),
761
762 /* Port4 */
763 PINMUX_DATA(DBGMD20_MARK, PORT4_FN1),
764 PINMUX_DATA(SCIFB_TXD_PORT4_MARK, PORT4_FN2, MSEL5CR_17_1),
765 PINMUX_DATA(LCD0_D19_PORT4_MARK, PORT4_FN4, MSEL5CR_6_0),
766 PINMUX_DATA(LCD1_D0_MARK, PORT4_FN7),
767
768 /* Port5 */
769 PINMUX_DATA(DBGMD11_MARK, PORT5_FN1),
770 PINMUX_DATA(BBIF2_TXD2_PORT5_MARK, PORT5_FN2, MSEL5CR_0_0),
771 PINMUX_DATA(FSIAISLD_PORT5_MARK, PORT5_FN4, MSEL5CR_3_1),
772 PINMUX_DATA(RSPI_SSL0_A_MARK, PORT5_FN6),
773 PINMUX_DATA(LCD1_VCPWC_MARK, PORT5_FN7),
774
775 /* Port6 */
776 PINMUX_DATA(DBGMD10_MARK, PORT6_FN1),
777 PINMUX_DATA(BBIF2_TSYNC2_PORT6_MARK, PORT6_FN2, MSEL5CR_0_0),
778 PINMUX_DATA(FMSISLD_PORT6_MARK, PORT6_FN4, MSEL5CR_5_1),
779 PINMUX_DATA(RSPI_SSL1_A_MARK, PORT6_FN6),
780 PINMUX_DATA(LCD1_VEPWC_MARK, PORT6_FN7),
781
782 /* Port7 */
783 PINMUX_DATA(FSIAOLR_MARK, PORT7_FN1),
784
785 /* Port8 */
786 PINMUX_DATA(FSIAOBT_MARK, PORT8_FN1),
787
788 /* Port9 */
789 PINMUX_DATA(FSIAOSLD_MARK, PORT9_FN1),
790 PINMUX_DATA(FSIASPDIF_PORT9_MARK, PORT9_FN2, MSEL5CR_4_0),
791
792 /* Port10 */
793 PINMUX_DATA(FSIAOMC_MARK, PORT10_FN1),
794 PINMUX_DATA(SCIFA5_RXD_PORT10_MARK, PORT10_FN3, MSEL5CR_14_0, MSEL5CR_15_0),
795 PINMUX_DATA(IRQ3_PORT10_MARK, PORT10_FN0, MSEL1CR_3_0),
796
797 /* Port11 */
798 PINMUX_DATA(FSIACK_MARK, PORT11_FN1),
799 PINMUX_DATA(FSIBCK_MARK, PORT11_FN2),
800 PINMUX_DATA(IRQ2_PORT11_MARK, PORT11_FN0, MSEL1CR_2_0),
801
802 /* Port12 */
803 PINMUX_DATA(FSIAILR_MARK, PORT12_FN1),
804 PINMUX_DATA(SCIFA4_RXD_PORT12_MARK, PORT12_FN2, MSEL5CR_12_0, MSEL5CR_11_0),
805 PINMUX_DATA(LCD1_RS_MARK, PORT12_FN6),
806 PINMUX_DATA(LCD1_DISP_MARK, PORT12_FN7),
807 PINMUX_DATA(IRQ2_PORT12_MARK, PORT12_FN0, MSEL1CR_2_1),
808
809 /* Port13 */
810 PINMUX_DATA(FSIAIBT_MARK, PORT13_FN1),
811 PINMUX_DATA(SCIFA4_TXD_PORT13_MARK, PORT13_FN2, MSEL5CR_12_0, MSEL5CR_11_0),
812 PINMUX_DATA(LCD1_RD_MARK, PORT13_FN7),
813 PINMUX_DATA(IRQ0_PORT13_MARK, PORT13_FN0, MSEL1CR_0_0),
814
815 /* Port14 */
816 PINMUX_DATA(FMSOILR_MARK, PORT14_FN1),
817 PINMUX_DATA(FMSIILR_MARK, PORT14_FN2),
818 PINMUX_DATA(VIO_CKO1_MARK, PORT14_FN3),
819 PINMUX_DATA(LCD1_D23_MARK, PORT14_FN7),
820 PINMUX_DATA(IRQ3_PORT14_MARK, PORT14_FN0, MSEL1CR_3_1),
821
822 /* Port15 */
823 PINMUX_DATA(FMSOIBT_MARK, PORT15_FN1),
824 PINMUX_DATA(FMSIIBT_MARK, PORT15_FN2),
825 PINMUX_DATA(VIO_CKO2_MARK, PORT15_FN3),
826 PINMUX_DATA(LCD1_D22_MARK, PORT15_FN7),
827 PINMUX_DATA(IRQ4_PORT15_MARK, PORT15_FN0, MSEL1CR_4_0),
828
829 /* Port16 */
830 PINMUX_DATA(FMSOOLR_MARK, PORT16_FN1),
831 PINMUX_DATA(FMSIOLR_MARK, PORT16_FN2),
832
833 /* Port17 */
834 PINMUX_DATA(FMSOOBT_MARK, PORT17_FN1),
835 PINMUX_DATA(FMSIOBT_MARK, PORT17_FN2),
836
837 /* Port18 */
838 PINMUX_DATA(FMSOSLD_MARK, PORT18_FN1),
839 PINMUX_DATA(FSIASPDIF_PORT18_MARK, PORT18_FN2, MSEL5CR_4_1),
840
841 /* Port19 */
842 PINMUX_DATA(FMSICK_MARK, PORT19_FN1),
843 PINMUX_DATA(CS5A_PORT19_MARK, PORT19_FN7, MSEL5CR_2_1),
844 PINMUX_DATA(IRQ10_MARK, PORT19_FN0),
845
846 /* Port20 */
847 PINMUX_DATA(FMSOCK_MARK, PORT20_FN1),
848 PINMUX_DATA(SCIFA5_TXD_PORT20_MARK, PORT20_FN3, MSEL5CR_15_0, MSEL5CR_14_0),
849 PINMUX_DATA(IRQ1_MARK, PORT20_FN0),
850
851 /* Port21 */
852 PINMUX_DATA(SCIFA1_CTS_MARK, PORT21_FN1),
853 PINMUX_DATA(SCIFA4_SCK_PORT21_MARK, PORT21_FN2, MSEL5CR_10_0),
854 PINMUX_DATA(TPU0TO1_MARK, PORT21_FN4),
855 PINMUX_DATA(VIO1_FIELD_MARK, PORT21_FN5),
856 PINMUX_DATA(STP0_IPD5_MARK, PORT21_FN6),
857 PINMUX_DATA(LCD1_D10_MARK, PORT21_FN7),
858
859 /* Port22 */
860 PINMUX_DATA(SCIFA2_SCK_PORT22_MARK, PORT22_FN1, MSEL5CR_7_0),
861 PINMUX_DATA(SIM_D_PORT22_MARK, PORT22_FN4, MSEL5CR_21_0),
862 PINMUX_DATA(VIO0_D13_PORT22_MARK, PORT22_FN7, MSEL5CR_27_1),
863
864 /* Port23 */
865 PINMUX_DATA(SCIFA1_RTS_MARK, PORT23_FN1),
866 PINMUX_DATA(SCIFA5_SCK_PORT23_MARK, PORT23_FN3, MSEL5CR_13_0),
867 PINMUX_DATA(TPU0TO0_MARK, PORT23_FN4),
868 PINMUX_DATA(VIO_CKO_1_MARK, PORT23_FN5),
869 PINMUX_DATA(STP0_IPD2_MARK, PORT23_FN6),
870 PINMUX_DATA(LCD1_D7_MARK, PORT23_FN7),
871
872 /* Port24 */
873 PINMUX_DATA(VIO0_D15_PORT24_MARK, PORT24_FN1, MSEL5CR_27_0),
874 PINMUX_DATA(VIO1_D7_MARK, PORT24_FN5),
875 PINMUX_DATA(SCIFA6_SCK_MARK, PORT24_FN6),
876 PINMUX_DATA(SDHI2_CD_PORT24_MARK, PORT24_FN7, MSEL5CR_19_0),
877
878 /* Port25 */
879 PINMUX_DATA(VIO0_D14_PORT25_MARK, PORT25_FN1, MSEL5CR_27_0),
880 PINMUX_DATA(VIO1_D6_MARK, PORT25_FN5),
881 PINMUX_DATA(SCIFA6_RXD_MARK, PORT25_FN6),
882 PINMUX_DATA(SDHI2_WP_PORT25_MARK, PORT25_FN7, MSEL5CR_19_0),
883
884 /* Port26 */
885 PINMUX_DATA(VIO0_D13_PORT26_MARK, PORT26_FN1, MSEL5CR_27_0),
886 PINMUX_DATA(VIO1_D5_MARK, PORT26_FN5),
887 PINMUX_DATA(SCIFA6_TXD_MARK, PORT26_FN6),
888
889 /* Port27 - Port39 Function */
890 PINMUX_DATA(VIO0_D7_MARK, PORT27_FN1),
891 PINMUX_DATA(VIO0_D6_MARK, PORT28_FN1),
892 PINMUX_DATA(VIO0_D5_MARK, PORT29_FN1),
893 PINMUX_DATA(VIO0_D4_MARK, PORT30_FN1),
894 PINMUX_DATA(VIO0_D3_MARK, PORT31_FN1),
895 PINMUX_DATA(VIO0_D2_MARK, PORT32_FN1),
896 PINMUX_DATA(VIO0_D1_MARK, PORT33_FN1),
897 PINMUX_DATA(VIO0_D0_MARK, PORT34_FN1),
898 PINMUX_DATA(VIO0_CLK_MARK, PORT35_FN1),
899 PINMUX_DATA(VIO_CKO_MARK, PORT36_FN1),
900 PINMUX_DATA(VIO0_HD_MARK, PORT37_FN1),
901 PINMUX_DATA(VIO0_FIELD_MARK, PORT38_FN1),
902 PINMUX_DATA(VIO0_VD_MARK, PORT39_FN1),
903
904 /* Port38 IRQ */
905 PINMUX_DATA(IRQ25_MARK, PORT38_FN0),
906
907 /* Port40 */
908 PINMUX_DATA(LCD0_D18_PORT40_MARK, PORT40_FN4, MSEL5CR_6_0),
909 PINMUX_DATA(RSPI_CK_A_MARK, PORT40_FN6),
910 PINMUX_DATA(LCD1_LCLK_MARK, PORT40_FN7),
911
912 /* Port41 */
913 PINMUX_DATA(LCD0_D17_MARK, PORT41_FN1),
914 PINMUX_DATA(MSIOF2_SS1_MARK, PORT41_FN2),
915 PINMUX_DATA(IRQ31_PORT41_MARK, PORT41_FN0, MSEL1CR_31_1),
916
917 /* Port42 */
918 PINMUX_DATA(LCD0_D16_MARK, PORT42_FN1),
919 PINMUX_DATA(MSIOF2_MCK1_MARK, PORT42_FN2),
920 PINMUX_DATA(IRQ12_PORT42_MARK, PORT42_FN0, MSEL1CR_12_1),
921
922 /* Port43 */
923 PINMUX_DATA(LCD0_D15_MARK, PORT43_FN1),
924 PINMUX_DATA(MSIOF2_MCK0_MARK, PORT43_FN2),
925 PINMUX_DATA(KEYIN0_PORT43_MARK, PORT43_FN3, MSEL4CR_18_0),
926 PINMUX_DATA(DV_D15_MARK, PORT43_FN6),
927
928 /* Port44 */
929 PINMUX_DATA(LCD0_D14_MARK, PORT44_FN1),
930 PINMUX_DATA(MSIOF2_RSYNC_MARK, PORT44_FN2),
931 PINMUX_DATA(KEYIN1_PORT44_MARK, PORT44_FN3, MSEL4CR_18_0),
932 PINMUX_DATA(DV_D14_MARK, PORT44_FN6),
933
934 /* Port45 */
935 PINMUX_DATA(LCD0_D13_MARK, PORT45_FN1),
936 PINMUX_DATA(MSIOF2_RSCK_MARK, PORT45_FN2),
937 PINMUX_DATA(KEYIN2_PORT45_MARK, PORT45_FN3, MSEL4CR_18_0),
938 PINMUX_DATA(DV_D13_MARK, PORT45_FN6),
939
940 /* Port46 */
941 PINMUX_DATA(LCD0_D12_MARK, PORT46_FN1),
942 PINMUX_DATA(KEYIN3_PORT46_MARK, PORT46_FN3, MSEL4CR_18_0),
943 PINMUX_DATA(DV_D12_MARK, PORT46_FN6),
944
945 /* Port47 */
946 PINMUX_DATA(LCD0_D11_MARK, PORT47_FN1),
947 PINMUX_DATA(KEYIN4_MARK, PORT47_FN3),
948 PINMUX_DATA(DV_D11_MARK, PORT47_FN6),
949
950 /* Port48 */
951 PINMUX_DATA(LCD0_D10_MARK, PORT48_FN1),
952 PINMUX_DATA(KEYIN5_MARK, PORT48_FN3),
953 PINMUX_DATA(DV_D10_MARK, PORT48_FN6),
954
955 /* Port49 */
956 PINMUX_DATA(LCD0_D9_MARK, PORT49_FN1),
957 PINMUX_DATA(KEYIN6_MARK, PORT49_FN3),
958 PINMUX_DATA(DV_D9_MARK, PORT49_FN6),
959 PINMUX_DATA(IRQ30_PORT49_MARK, PORT49_FN0, MSEL1CR_30_1),
960
961 /* Port50 */
962 PINMUX_DATA(LCD0_D8_MARK, PORT50_FN1),
963 PINMUX_DATA(KEYIN7_MARK, PORT50_FN3),
964 PINMUX_DATA(DV_D8_MARK, PORT50_FN6),
965 PINMUX_DATA(IRQ29_PORT50_MARK, PORT50_FN0, MSEL1CR_29_1),
966
967 /* Port51 */
968 PINMUX_DATA(LCD0_D7_MARK, PORT51_FN1),
969 PINMUX_DATA(KEYOUT0_MARK, PORT51_FN3),
970 PINMUX_DATA(DV_D7_MARK, PORT51_FN6),
971
972 /* Port52 */
973 PINMUX_DATA(LCD0_D6_MARK, PORT52_FN1),
974 PINMUX_DATA(KEYOUT1_MARK, PORT52_FN3),
975 PINMUX_DATA(DV_D6_MARK, PORT52_FN6),
976
977 /* Port53 */
978 PINMUX_DATA(LCD0_D5_MARK, PORT53_FN1),
979 PINMUX_DATA(KEYOUT2_MARK, PORT53_FN3),
980 PINMUX_DATA(DV_D5_MARK, PORT53_FN6),
981
982 /* Port54 */
983 PINMUX_DATA(LCD0_D4_MARK, PORT54_FN1),
984 PINMUX_DATA(KEYOUT3_MARK, PORT54_FN3),
985 PINMUX_DATA(DV_D4_MARK, PORT54_FN6),
986
987 /* Port55 */
988 PINMUX_DATA(LCD0_D3_MARK, PORT55_FN1),
989 PINMUX_DATA(KEYOUT4_MARK, PORT55_FN3),
990 PINMUX_DATA(KEYIN3_PORT55_MARK, PORT55_FN4, MSEL4CR_18_1),
991 PINMUX_DATA(DV_D3_MARK, PORT55_FN6),
992
993 /* Port56 */
994 PINMUX_DATA(LCD0_D2_MARK, PORT56_FN1),
995 PINMUX_DATA(KEYOUT5_MARK, PORT56_FN3),
996 PINMUX_DATA(KEYIN2_PORT56_MARK, PORT56_FN4, MSEL4CR_18_1),
997 PINMUX_DATA(DV_D2_MARK, PORT56_FN6),
998 PINMUX_DATA(IRQ28_PORT56_MARK, PORT56_FN0, MSEL1CR_28_1),
999
1000 /* Port57 */
1001 PINMUX_DATA(LCD0_D1_MARK, PORT57_FN1),
1002 PINMUX_DATA(KEYOUT6_MARK, PORT57_FN3),
1003 PINMUX_DATA(KEYIN1_PORT57_MARK, PORT57_FN4, MSEL4CR_18_1),
1004 PINMUX_DATA(DV_D1_MARK, PORT57_FN6),
1005 PINMUX_DATA(IRQ27_PORT57_MARK, PORT57_FN0, MSEL1CR_27_1),
1006
1007 /* Port58 */
Laurent Pinchartb7983902013-04-19 11:52:59 +0200[diff] [blame]1008 PINMUX_DATA(LCD0_D0_MARK, PORT58_FN1, MSEL3CR_6_0),
Laurent Pinchartd5b15212012-12-15 23:51:21 +0100[diff] [blame]1009 PINMUX_DATA(KEYOUT7_MARK, PORT58_FN3),
1010 PINMUX_DATA(KEYIN0_PORT58_MARK, PORT58_FN4, MSEL4CR_18_1),
1011 PINMUX_DATA(DV_D0_MARK, PORT58_FN6),
1012 PINMUX_DATA(IRQ26_PORT58_MARK, PORT58_FN0, MSEL1CR_26_1),
1013
1014 /* Port59 */
1015 PINMUX_DATA(LCD0_VCPWC_MARK, PORT59_FN1),
1016 PINMUX_DATA(BBIF2_TSCK2_PORT59_MARK, PORT59_FN2, MSEL5CR_0_0),
1017 PINMUX_DATA(RSPI_MOSI_A_MARK, PORT59_FN6),
1018
1019 /* Port60 */
1020 PINMUX_DATA(LCD0_VEPWC_MARK, PORT60_FN1),
1021 PINMUX_DATA(BBIF2_RXD2_PORT60_MARK, PORT60_FN2, MSEL5CR_0_0),
1022 PINMUX_DATA(RSPI_MISO_A_MARK, PORT60_FN6),
1023
1024 /* Port61 */
1025 PINMUX_DATA(LCD0_DON_MARK, PORT61_FN1),
1026 PINMUX_DATA(MSIOF2_TXD_MARK, PORT61_FN2),
1027
1028 /* Port62 */
1029 PINMUX_DATA(LCD0_DCK_MARK, PORT62_FN1),
1030 PINMUX_DATA(LCD0_WR_MARK, PORT62_FN4),
1031 PINMUX_DATA(DV_CLK_MARK, PORT62_FN6),
1032 PINMUX_DATA(IRQ15_PORT62_MARK, PORT62_FN0, MSEL1CR_15_1),
1033
1034 /* Port63 */
1035 PINMUX_DATA(LCD0_VSYN_MARK, PORT63_FN1),
1036 PINMUX_DATA(DV_VSYNC_MARK, PORT63_FN6),
1037 PINMUX_DATA(IRQ14_PORT63_MARK, PORT63_FN0, MSEL1CR_14_1),
1038
1039 /* Port64 */
1040 PINMUX_DATA(LCD0_HSYN_MARK, PORT64_FN1),
1041 PINMUX_DATA(LCD0_CS_MARK, PORT64_FN4),
1042 PINMUX_DATA(DV_HSYNC_MARK, PORT64_FN6),
1043 PINMUX_DATA(IRQ13_PORT64_MARK, PORT64_FN0, MSEL1CR_13_1),
1044
1045 /* Port65 */
1046 PINMUX_DATA(LCD0_DISP_MARK, PORT65_FN1),
1047 PINMUX_DATA(MSIOF2_TSCK_MARK, PORT65_FN2),
1048 PINMUX_DATA(LCD0_RS_MARK, PORT65_FN4),
1049
1050 /* Port66 */
1051 PINMUX_DATA(MEMC_INT_MARK, PORT66_FN1),
1052 PINMUX_DATA(TPU0TO2_PORT66_MARK, PORT66_FN3, MSEL5CR_25_0),
1053 PINMUX_DATA(MMC0_CLK_PORT66_MARK, PORT66_FN4, MSEL4CR_15_0),
1054 PINMUX_DATA(SDHI1_CLK_MARK, PORT66_FN6),
1055
1056 /* Port67 - Port73 Function1 */
1057 PINMUX_DATA(MEMC_CS0_MARK, PORT67_FN1),
1058 PINMUX_DATA(MEMC_AD8_MARK, PORT68_FN1),
1059 PINMUX_DATA(MEMC_AD9_MARK, PORT69_FN1),
1060 PINMUX_DATA(MEMC_AD10_MARK, PORT70_FN1),
1061 PINMUX_DATA(MEMC_AD11_MARK, PORT71_FN1),
1062 PINMUX_DATA(MEMC_AD12_MARK, PORT72_FN1),
1063 PINMUX_DATA(MEMC_AD13_MARK, PORT73_FN1),
1064
1065 /* Port67 - Port73 Function2 */
1066 PINMUX_DATA(MSIOF1_SS1_PORT67_MARK, PORT67_FN2, MSEL4CR_10_1),
1067 PINMUX_DATA(MSIOF1_RSCK_MARK, PORT68_FN2),
1068 PINMUX_DATA(MSIOF1_RSYNC_MARK, PORT69_FN2),
1069 PINMUX_DATA(MSIOF1_MCK0_MARK, PORT70_FN2),
1070 PINMUX_DATA(MSIOF1_MCK1_MARK, PORT71_FN2),
1071 PINMUX_DATA(MSIOF1_TSCK_PORT72_MARK, PORT72_FN2, MSEL4CR_10_1),
1072 PINMUX_DATA(MSIOF1_TSYNC_PORT73_MARK, PORT73_FN2, MSEL4CR_10_1),
1073
1074 /* Port67 - Port73 Function4 */
1075 PINMUX_DATA(MMC0_CMD_PORT67_MARK, PORT67_FN4, MSEL4CR_15_0),
1076 PINMUX_DATA(MMC0_D0_PORT68_MARK, PORT68_FN4, MSEL4CR_15_0),
1077 PINMUX_DATA(MMC0_D1_PORT69_MARK, PORT69_FN4, MSEL4CR_15_0),
1078 PINMUX_DATA(MMC0_D2_PORT70_MARK, PORT70_FN4, MSEL4CR_15_0),
1079 PINMUX_DATA(MMC0_D3_PORT71_MARK, PORT71_FN4, MSEL4CR_15_0),
1080 PINMUX_DATA(MMC0_D4_PORT72_MARK, PORT72_FN4, MSEL4CR_15_0),
1081 PINMUX_DATA(MMC0_D5_PORT73_MARK, PORT73_FN4, MSEL4CR_15_0),
1082
1083 /* Port67 - Port73 Function6 */
1084 PINMUX_DATA(SDHI1_CMD_MARK, PORT67_FN6),
1085 PINMUX_DATA(SDHI1_D0_MARK, PORT68_FN6),
1086 PINMUX_DATA(SDHI1_D1_MARK, PORT69_FN6),
1087 PINMUX_DATA(SDHI1_D2_MARK, PORT70_FN6),
1088 PINMUX_DATA(SDHI1_D3_MARK, PORT71_FN6),
1089 PINMUX_DATA(SDHI1_CD_MARK, PORT72_FN6),
1090 PINMUX_DATA(SDHI1_WP_MARK, PORT73_FN6),
1091
1092 /* Port67 - Port71 IRQ */
1093 PINMUX_DATA(IRQ20_MARK, PORT67_FN0),
1094 PINMUX_DATA(IRQ16_PORT68_MARK, PORT68_FN0, MSEL1CR_16_0),
1095 PINMUX_DATA(IRQ17_MARK, PORT69_FN0),
1096 PINMUX_DATA(IRQ18_MARK, PORT70_FN0),
1097 PINMUX_DATA(IRQ19_MARK, PORT71_FN0),
1098
1099 /* Port74 */
1100 PINMUX_DATA(MEMC_AD14_MARK, PORT74_FN1),
1101 PINMUX_DATA(MSIOF1_TXD_PORT74_MARK, PORT74_FN2, MSEL4CR_10_1),
1102 PINMUX_DATA(MMC0_D6_PORT74_MARK, PORT74_FN4, MSEL4CR_15_0),
1103 PINMUX_DATA(STP1_IPD7_MARK, PORT74_FN6),
1104 PINMUX_DATA(LCD1_D21_MARK, PORT74_FN7),
1105
1106 /* Port75 */
1107 PINMUX_DATA(MEMC_AD15_MARK, PORT75_FN1),
1108 PINMUX_DATA(MSIOF1_RXD_PORT75_MARK, PORT75_FN2, MSEL4CR_10_1),
1109 PINMUX_DATA(MMC0_D7_PORT75_MARK, PORT75_FN4, MSEL4CR_15_0),
1110 PINMUX_DATA(STP1_IPD6_MARK, PORT75_FN6),
1111 PINMUX_DATA(LCD1_D20_MARK, PORT75_FN7),
1112
1113 /* Port76 - Port80 Function */
1114 PINMUX_DATA(SDHI0_CMD_MARK, PORT76_FN1),
1115 PINMUX_DATA(SDHI0_D0_MARK, PORT77_FN1),
1116 PINMUX_DATA(SDHI0_D1_MARK, PORT78_FN1),
1117 PINMUX_DATA(SDHI0_D2_MARK, PORT79_FN1),
1118 PINMUX_DATA(SDHI0_D3_MARK, PORT80_FN1),
1119
1120 /* Port81 */
1121 PINMUX_DATA(SDHI0_CD_MARK, PORT81_FN1),
1122 PINMUX_DATA(IRQ26_PORT81_MARK, PORT81_FN0, MSEL1CR_26_0),
1123
1124 /* Port82 - Port88 Function */
1125 PINMUX_DATA(SDHI0_CLK_MARK, PORT82_FN1),
1126 PINMUX_DATA(SDHI0_WP_MARK, PORT83_FN1),
1127 PINMUX_DATA(RESETOUTS_MARK, PORT84_FN1),
1128 PINMUX_DATA(USB0_PPON_MARK, PORT85_FN1),
1129 PINMUX_DATA(USB0_OCI_MARK, PORT86_FN1),
1130 PINMUX_DATA(USB1_PPON_MARK, PORT87_FN1),
1131 PINMUX_DATA(USB1_OCI_MARK, PORT88_FN1),
1132
1133 /* Port89 */
1134 PINMUX_DATA(DREQ0_MARK, PORT89_FN1),
1135 PINMUX_DATA(BBIF2_TSCK2_PORT89_MARK, PORT89_FN2, MSEL5CR_0_1),
1136 PINMUX_DATA(RSPI_SSL3_A_MARK, PORT89_FN6),
1137
1138 /* Port90 */
1139 PINMUX_DATA(DACK0_MARK, PORT90_FN1),
1140 PINMUX_DATA(BBIF2_RXD2_PORT90_MARK, PORT90_FN2, MSEL5CR_0_1),
1141 PINMUX_DATA(RSPI_SSL2_A_MARK, PORT90_FN6),
1142 PINMUX_DATA(WAIT_PORT90_MARK, PORT90_FN7, MSEL5CR_2_1),
1143
1144 /* Port91 */
1145 PINMUX_DATA(MEMC_AD0_MARK, PORT91_FN1),
1146 PINMUX_DATA(BBIF1_RXD_MARK, PORT91_FN2),
1147 PINMUX_DATA(SCIFA5_TXD_PORT91_MARK, PORT91_FN3, MSEL5CR_15_1, MSEL5CR_14_0),
1148 PINMUX_DATA(LCD1_D5_MARK, PORT91_FN7),
1149
1150 /* Port92 */
1151 PINMUX_DATA(MEMC_AD1_MARK, PORT92_FN1),
1152 PINMUX_DATA(BBIF1_TSYNC_MARK, PORT92_FN2),
1153 PINMUX_DATA(SCIFA5_RXD_PORT92_MARK, PORT92_FN3, MSEL5CR_15_1, MSEL5CR_14_0),
1154 PINMUX_DATA(STP0_IPD1_MARK, PORT92_FN6),
1155 PINMUX_DATA(LCD1_D6_MARK, PORT92_FN7),
1156
1157 /* Port93 */
1158 PINMUX_DATA(MEMC_AD2_MARK, PORT93_FN1),
1159 PINMUX_DATA(BBIF1_TSCK_MARK, PORT93_FN2),
1160 PINMUX_DATA(SCIFA4_TXD_PORT93_MARK, PORT93_FN3, MSEL5CR_12_1, MSEL5CR_11_0),
1161 PINMUX_DATA(STP0_IPD3_MARK, PORT93_FN6),
1162 PINMUX_DATA(LCD1_D8_MARK, PORT93_FN7),
1163
1164 /* Port94 */
1165 PINMUX_DATA(MEMC_AD3_MARK, PORT94_FN1),
1166 PINMUX_DATA(BBIF1_TXD_MARK, PORT94_FN2),
1167 PINMUX_DATA(SCIFA4_RXD_PORT94_MARK, PORT94_FN3, MSEL5CR_12_1, MSEL5CR_11_0),
1168 PINMUX_DATA(STP0_IPD4_MARK, PORT94_FN6),
1169 PINMUX_DATA(LCD1_D9_MARK, PORT94_FN7),
1170
1171 /* Port95 */
1172 PINMUX_DATA(MEMC_CS1_MARK, PORT95_FN1, MSEL4CR_6_0),
1173 PINMUX_DATA(MEMC_A1_MARK, PORT95_FN1, MSEL4CR_6_1),
1174
1175 PINMUX_DATA(SCIFA2_CTS_MARK, PORT95_FN2),
1176 PINMUX_DATA(SIM_RST_MARK, PORT95_FN4),
1177 PINMUX_DATA(VIO0_D14_PORT95_MARK, PORT95_FN7, MSEL5CR_27_1),
1178 PINMUX_DATA(IRQ22_MARK, PORT95_FN0),
1179
1180 /* Port96 */
1181 PINMUX_DATA(MEMC_ADV_MARK, PORT96_FN1, MSEL4CR_6_0),
1182 PINMUX_DATA(MEMC_DREQ0_MARK, PORT96_FN1, MSEL4CR_6_1),
1183
1184 PINMUX_DATA(SCIFA2_RTS_MARK, PORT96_FN2),
1185 PINMUX_DATA(SIM_CLK_MARK, PORT96_FN4),
1186 PINMUX_DATA(VIO0_D15_PORT96_MARK, PORT96_FN7, MSEL5CR_27_1),
1187 PINMUX_DATA(IRQ23_MARK, PORT96_FN0),
1188
1189 /* Port97 */
1190 PINMUX_DATA(MEMC_AD4_MARK, PORT97_FN1),
1191 PINMUX_DATA(BBIF1_RSCK_MARK, PORT97_FN2),
1192 PINMUX_DATA(LCD1_CS_MARK, PORT97_FN6),
1193 PINMUX_DATA(LCD1_HSYN_MARK, PORT97_FN7),
1194 PINMUX_DATA(IRQ12_PORT97_MARK, PORT97_FN0, MSEL1CR_12_0),
1195
1196 /* Port98 */
1197 PINMUX_DATA(MEMC_AD5_MARK, PORT98_FN1),
1198 PINMUX_DATA(BBIF1_RSYNC_MARK, PORT98_FN2),
1199 PINMUX_DATA(LCD1_VSYN_MARK, PORT98_FN7),
1200 PINMUX_DATA(IRQ13_PORT98_MARK, PORT98_FN0, MSEL1CR_13_0),
1201
1202 /* Port99 */
1203 PINMUX_DATA(MEMC_AD6_MARK, PORT99_FN1),
1204 PINMUX_DATA(BBIF1_FLOW_MARK, PORT99_FN2),
1205 PINMUX_DATA(LCD1_WR_MARK, PORT99_FN6),
1206 PINMUX_DATA(LCD1_DCK_MARK, PORT99_FN7),
1207 PINMUX_DATA(IRQ14_PORT99_MARK, PORT99_FN0, MSEL1CR_14_0),
1208
1209 /* Port100 */
1210 PINMUX_DATA(MEMC_AD7_MARK, PORT100_FN1),
1211 PINMUX_DATA(BBIF1_RX_FLOW_N_MARK, PORT100_FN2),
1212 PINMUX_DATA(LCD1_DON_MARK, PORT100_FN7),
1213 PINMUX_DATA(IRQ15_PORT100_MARK, PORT100_FN0, MSEL1CR_15_0),
1214
1215 /* Port101 */
1216 PINMUX_DATA(FCE0_MARK, PORT101_FN1),
1217
1218 /* Port102 */
1219 PINMUX_DATA(FRB_MARK, PORT102_FN1),
1220 PINMUX_DATA(LCD0_LCLK_PORT102_MARK, PORT102_FN4, MSEL5CR_6_0),
1221
1222 /* Port103 */
1223 PINMUX_DATA(CS5B_MARK, PORT103_FN1),
1224 PINMUX_DATA(FCE1_MARK, PORT103_FN2),
1225 PINMUX_DATA(MMC1_CLK_PORT103_MARK, PORT103_FN3, MSEL4CR_15_1),
1226
1227 /* Port104 */
1228 PINMUX_DATA(CS6A_MARK, PORT104_FN1),
1229 PINMUX_DATA(MMC1_CMD_PORT104_MARK, PORT104_FN3, MSEL4CR_15_1),
1230 PINMUX_DATA(IRQ11_MARK, PORT104_FN0),
1231
1232 /* Port105 */
1233 PINMUX_DATA(CS5A_PORT105_MARK, PORT105_FN1, MSEL5CR_2_0),
1234 PINMUX_DATA(SCIFA3_RTS_PORT105_MARK, PORT105_FN4, MSEL5CR_8_0),
1235
1236 /* Port106 */
1237 PINMUX_DATA(IOIS16_MARK, PORT106_FN1),
1238 PINMUX_DATA(IDE_EXBUF_ENB_MARK, PORT106_FN6),
1239
1240 /* Port107 - Port115 Function */
1241 PINMUX_DATA(WE3_ICIOWR_MARK, PORT107_FN1),
1242 PINMUX_DATA(WE2_ICIORD_MARK, PORT108_FN1),
1243 PINMUX_DATA(CS0_MARK, PORT109_FN1),
1244 PINMUX_DATA(CS2_MARK, PORT110_FN1),
1245 PINMUX_DATA(CS4_MARK, PORT111_FN1),
1246 PINMUX_DATA(WE1_MARK, PORT112_FN1),
1247 PINMUX_DATA(WE0_FWE_MARK, PORT113_FN1),
1248 PINMUX_DATA(RDWR_MARK, PORT114_FN1),
1249 PINMUX_DATA(RD_FSC_MARK, PORT115_FN1),
1250
1251 /* Port116 */
1252 PINMUX_DATA(A25_MARK, PORT116_FN1),
1253 PINMUX_DATA(MSIOF0_SS2_MARK, PORT116_FN2),
1254 PINMUX_DATA(MSIOF1_SS2_PORT116_MARK, PORT116_FN3, MSEL4CR_10_0),
1255 PINMUX_DATA(SCIFA3_SCK_PORT116_MARK, PORT116_FN4, MSEL5CR_8_0),
1256 PINMUX_DATA(GPO1_MARK, PORT116_FN5),
1257
1258 /* Port117 */
1259 PINMUX_DATA(A24_MARK, PORT117_FN1),
1260 PINMUX_DATA(MSIOF0_SS1_MARK, PORT117_FN2),
1261 PINMUX_DATA(MSIOF1_SS1_PORT117_MARK, PORT117_FN3, MSEL4CR_10_0),
1262 PINMUX_DATA(SCIFA3_CTS_PORT117_MARK, PORT117_FN4, MSEL5CR_8_0),
1263 PINMUX_DATA(GPO0_MARK, PORT117_FN5),
1264
1265 /* Port118 */
1266 PINMUX_DATA(A23_MARK, PORT118_FN1),
1267 PINMUX_DATA(MSIOF0_MCK1_MARK, PORT118_FN2),
1268 PINMUX_DATA(MSIOF1_RXD_PORT118_MARK, PORT118_FN3, MSEL4CR_10_0),
1269 PINMUX_DATA(GPI1_MARK, PORT118_FN5),
1270 PINMUX_DATA(IRQ9_PORT118_MARK, PORT118_FN0, MSEL1CR_9_0),
1271
1272 /* Port119 */
1273 PINMUX_DATA(A22_MARK, PORT119_FN1),
1274 PINMUX_DATA(MSIOF0_MCK0_MARK, PORT119_FN2),
1275 PINMUX_DATA(MSIOF1_TXD_PORT119_MARK, PORT119_FN3, MSEL4CR_10_0),
1276 PINMUX_DATA(GPI0_MARK, PORT119_FN5),
1277 PINMUX_DATA(IRQ8_MARK, PORT119_FN0),
1278
1279 /* Port120 */
1280 PINMUX_DATA(A21_MARK, PORT120_FN1),
1281 PINMUX_DATA(MSIOF0_RSYNC_MARK, PORT120_FN2),
1282 PINMUX_DATA(MSIOF1_TSYNC_PORT120_MARK, PORT120_FN3, MSEL4CR_10_0),
1283 PINMUX_DATA(IRQ7_PORT120_MARK, PORT120_FN0, MSEL1CR_7_1),
1284
1285 /* Port121 */
1286 PINMUX_DATA(A20_MARK, PORT121_FN1),
1287 PINMUX_DATA(MSIOF0_RSCK_MARK, PORT121_FN2),
1288 PINMUX_DATA(MSIOF1_TSCK_PORT121_MARK, PORT121_FN3, MSEL4CR_10_0),
1289 PINMUX_DATA(IRQ6_PORT121_MARK, PORT121_FN0, MSEL1CR_6_0),
1290
1291 /* Port122 */
1292 PINMUX_DATA(A19_MARK, PORT122_FN1),
1293 PINMUX_DATA(MSIOF0_RXD_MARK, PORT122_FN2),
1294
1295 /* Port123 */
1296 PINMUX_DATA(A18_MARK, PORT123_FN1),
1297 PINMUX_DATA(MSIOF0_TSCK_MARK, PORT123_FN2),
1298
1299 /* Port124 */
1300 PINMUX_DATA(A17_MARK, PORT124_FN1),
1301 PINMUX_DATA(MSIOF0_TSYNC_MARK, PORT124_FN2),
1302
1303 /* Port125 - Port141 Function */
1304 PINMUX_DATA(A16_MARK, PORT125_FN1),
1305 PINMUX_DATA(A15_MARK, PORT126_FN1),
1306 PINMUX_DATA(A14_MARK, PORT127_FN1),
1307 PINMUX_DATA(A13_MARK, PORT128_FN1),
1308 PINMUX_DATA(A12_MARK, PORT129_FN1),
1309 PINMUX_DATA(A11_MARK, PORT130_FN1),
1310 PINMUX_DATA(A10_MARK, PORT131_FN1),
1311 PINMUX_DATA(A9_MARK, PORT132_FN1),
1312 PINMUX_DATA(A8_MARK, PORT133_FN1),
1313 PINMUX_DATA(A7_MARK, PORT134_FN1),
1314 PINMUX_DATA(A6_MARK, PORT135_FN1),
1315 PINMUX_DATA(A5_FCDE_MARK, PORT136_FN1),
1316 PINMUX_DATA(A4_FOE_MARK, PORT137_FN1),
1317 PINMUX_DATA(A3_MARK, PORT138_FN1),
1318 PINMUX_DATA(A2_MARK, PORT139_FN1),
1319 PINMUX_DATA(A1_MARK, PORT140_FN1),
1320 PINMUX_DATA(CKO_MARK, PORT141_FN1),
1321
1322 /* Port142 - Port157 Function1 */
1323 PINMUX_DATA(D15_NAF15_MARK, PORT142_FN1),
1324 PINMUX_DATA(D14_NAF14_MARK, PORT143_FN1),
1325 PINMUX_DATA(D13_NAF13_MARK, PORT144_FN1),
1326 PINMUX_DATA(D12_NAF12_MARK, PORT145_FN1),
1327 PINMUX_DATA(D11_NAF11_MARK, PORT146_FN1),
1328 PINMUX_DATA(D10_NAF10_MARK, PORT147_FN1),
1329 PINMUX_DATA(D9_NAF9_MARK, PORT148_FN1),
1330 PINMUX_DATA(D8_NAF8_MARK, PORT149_FN1),
1331 PINMUX_DATA(D7_NAF7_MARK, PORT150_FN1),
1332 PINMUX_DATA(D6_NAF6_MARK, PORT151_FN1),
1333 PINMUX_DATA(D5_NAF5_MARK, PORT152_FN1),
1334 PINMUX_DATA(D4_NAF4_MARK, PORT153_FN1),
1335 PINMUX_DATA(D3_NAF3_MARK, PORT154_FN1),
1336 PINMUX_DATA(D2_NAF2_MARK, PORT155_FN1),
1337 PINMUX_DATA(D1_NAF1_MARK, PORT156_FN1),
1338 PINMUX_DATA(D0_NAF0_MARK, PORT157_FN1),
1339
1340 /* Port142 - Port149 Function3 */
1341 PINMUX_DATA(MMC1_D7_PORT142_MARK, PORT142_FN3, MSEL4CR_15_1),
1342 PINMUX_DATA(MMC1_D6_PORT143_MARK, PORT143_FN3, MSEL4CR_15_1),
1343 PINMUX_DATA(MMC1_D5_PORT144_MARK, PORT144_FN3, MSEL4CR_15_1),
1344 PINMUX_DATA(MMC1_D4_PORT145_MARK, PORT145_FN3, MSEL4CR_15_1),
1345 PINMUX_DATA(MMC1_D3_PORT146_MARK, PORT146_FN3, MSEL4CR_15_1),
1346 PINMUX_DATA(MMC1_D2_PORT147_MARK, PORT147_FN3, MSEL4CR_15_1),
1347 PINMUX_DATA(MMC1_D1_PORT148_MARK, PORT148_FN3, MSEL4CR_15_1),
1348 PINMUX_DATA(MMC1_D0_PORT149_MARK, PORT149_FN3, MSEL4CR_15_1),
1349
1350 /* Port158 */
1351 PINMUX_DATA(D31_MARK, PORT158_FN1),
1352 PINMUX_DATA(SCIFA3_SCK_PORT158_MARK, PORT158_FN2, MSEL5CR_8_1),
1353 PINMUX_DATA(RMII_REF125CK_MARK, PORT158_FN3),
1354 PINMUX_DATA(LCD0_D21_PORT158_MARK, PORT158_FN4, MSEL5CR_6_1),
1355 PINMUX_DATA(IRDA_FIRSEL_MARK, PORT158_FN5),
1356 PINMUX_DATA(IDE_D15_MARK, PORT158_FN6),
1357
1358 /* Port159 */
1359 PINMUX_DATA(D30_MARK, PORT159_FN1),
1360 PINMUX_DATA(SCIFA3_RXD_PORT159_MARK, PORT159_FN2, MSEL5CR_8_1),
1361 PINMUX_DATA(RMII_REF50CK_MARK, PORT159_FN3),
1362 PINMUX_DATA(LCD0_D23_PORT159_MARK, PORT159_FN4, MSEL5CR_6_1),
1363 PINMUX_DATA(IDE_D14_MARK, PORT159_FN6),
1364
1365 /* Port160 */
1366 PINMUX_DATA(D29_MARK, PORT160_FN1),
1367 PINMUX_DATA(SCIFA3_TXD_PORT160_MARK, PORT160_FN2, MSEL5CR_8_1),
1368 PINMUX_DATA(LCD0_D22_PORT160_MARK, PORT160_FN4, MSEL5CR_6_1),
1369 PINMUX_DATA(VIO1_HD_MARK, PORT160_FN5),
1370 PINMUX_DATA(IDE_D13_MARK, PORT160_FN6),
1371
1372 /* Port161 */
1373 PINMUX_DATA(D28_MARK, PORT161_FN1),
1374 PINMUX_DATA(SCIFA3_RTS_PORT161_MARK, PORT161_FN2, MSEL5CR_8_1),
1375 PINMUX_DATA(ET_RX_DV_MARK, PORT161_FN3),
1376 PINMUX_DATA(LCD0_D20_PORT161_MARK, PORT161_FN4, MSEL5CR_6_1),
1377 PINMUX_DATA(IRDA_IN_MARK, PORT161_FN5),
1378 PINMUX_DATA(IDE_D12_MARK, PORT161_FN6),
1379
1380 /* Port162 */
1381 PINMUX_DATA(D27_MARK, PORT162_FN1),
1382 PINMUX_DATA(SCIFA3_CTS_PORT162_MARK, PORT162_FN2, MSEL5CR_8_1),
1383 PINMUX_DATA(LCD0_D19_PORT162_MARK, PORT162_FN4, MSEL5CR_6_1),
1384 PINMUX_DATA(IRDA_OUT_MARK, PORT162_FN5),
1385 PINMUX_DATA(IDE_D11_MARK, PORT162_FN6),
1386
1387 /* Port163 */
1388 PINMUX_DATA(D26_MARK, PORT163_FN1),
1389 PINMUX_DATA(MSIOF2_SS2_MARK, PORT163_FN2),
1390 PINMUX_DATA(ET_COL_MARK, PORT163_FN3),
1391 PINMUX_DATA(LCD0_D18_PORT163_MARK, PORT163_FN4, MSEL5CR_6_1),
1392 PINMUX_DATA(IROUT_MARK, PORT163_FN5),
1393 PINMUX_DATA(IDE_D10_MARK, PORT163_FN6),
1394
1395 /* Port164 */
1396 PINMUX_DATA(D25_MARK, PORT164_FN1),
1397 PINMUX_DATA(MSIOF2_TSYNC_MARK, PORT164_FN2),
1398 PINMUX_DATA(ET_PHY_INT_MARK, PORT164_FN3),
1399 PINMUX_DATA(LCD0_RD_MARK, PORT164_FN4),
1400 PINMUX_DATA(IDE_D9_MARK, PORT164_FN6),
1401
1402 /* Port165 */
1403 PINMUX_DATA(D24_MARK, PORT165_FN1),
1404 PINMUX_DATA(MSIOF2_RXD_MARK, PORT165_FN2),
1405 PINMUX_DATA(LCD0_LCLK_PORT165_MARK, PORT165_FN4, MSEL5CR_6_1),
1406 PINMUX_DATA(IDE_D8_MARK, PORT165_FN6),
1407
1408 /* Port166 - Port171 Function1 */
1409 PINMUX_DATA(D21_MARK, PORT166_FN1),
1410 PINMUX_DATA(D20_MARK, PORT167_FN1),
1411 PINMUX_DATA(D19_MARK, PORT168_FN1),
1412 PINMUX_DATA(D18_MARK, PORT169_FN1),
1413 PINMUX_DATA(D17_MARK, PORT170_FN1),
1414 PINMUX_DATA(D16_MARK, PORT171_FN1),
1415
1416 /* Port166 - Port171 Function3 */
1417 PINMUX_DATA(ET_ETXD5_MARK, PORT166_FN3),
1418 PINMUX_DATA(ET_ETXD4_MARK, PORT167_FN3),
1419 PINMUX_DATA(ET_ETXD3_MARK, PORT168_FN3),
1420 PINMUX_DATA(ET_ETXD2_MARK, PORT169_FN3),
1421 PINMUX_DATA(ET_ETXD1_MARK, PORT170_FN3),
1422 PINMUX_DATA(ET_ETXD0_MARK, PORT171_FN3),
1423
1424 /* Port166 - Port171 Function6 */
1425 PINMUX_DATA(IDE_D5_MARK, PORT166_FN6),
1426 PINMUX_DATA(IDE_D4_MARK, PORT167_FN6),
1427 PINMUX_DATA(IDE_D3_MARK, PORT168_FN6),
1428 PINMUX_DATA(IDE_D2_MARK, PORT169_FN6),
1429 PINMUX_DATA(IDE_D1_MARK, PORT170_FN6),
1430 PINMUX_DATA(IDE_D0_MARK, PORT171_FN6),
1431
1432 /* Port167 - Port171 IRQ */
1433 PINMUX_DATA(IRQ31_PORT167_MARK, PORT167_FN0, MSEL1CR_31_0),
1434 PINMUX_DATA(IRQ27_PORT168_MARK, PORT168_FN0, MSEL1CR_27_0),
1435 PINMUX_DATA(IRQ28_PORT169_MARK, PORT169_FN0, MSEL1CR_28_0),
1436 PINMUX_DATA(IRQ29_PORT170_MARK, PORT170_FN0, MSEL1CR_29_0),
1437 PINMUX_DATA(IRQ30_PORT171_MARK, PORT171_FN0, MSEL1CR_30_0),
1438
1439 /* Port172 */
1440 PINMUX_DATA(D23_MARK, PORT172_FN1),
1441 PINMUX_DATA(SCIFB_RTS_PORT172_MARK, PORT172_FN2, MSEL5CR_17_1),
1442 PINMUX_DATA(ET_ETXD7_MARK, PORT172_FN3),
1443 PINMUX_DATA(IDE_D7_MARK, PORT172_FN6),
1444 PINMUX_DATA(IRQ4_PORT172_MARK, PORT172_FN0, MSEL1CR_4_1),
1445
1446 /* Port173 */
1447 PINMUX_DATA(D22_MARK, PORT173_FN1),
1448 PINMUX_DATA(SCIFB_CTS_PORT173_MARK, PORT173_FN2, MSEL5CR_17_1),
1449 PINMUX_DATA(ET_ETXD6_MARK, PORT173_FN3),
1450 PINMUX_DATA(IDE_D6_MARK, PORT173_FN6),
1451 PINMUX_DATA(IRQ6_PORT173_MARK, PORT173_FN0, MSEL1CR_6_1),
1452
1453 /* Port174 */
1454 PINMUX_DATA(A26_MARK, PORT174_FN1),
1455 PINMUX_DATA(MSIOF0_TXD_MARK, PORT174_FN2),
1456 PINMUX_DATA(ET_RX_CLK_MARK, PORT174_FN3),
1457 PINMUX_DATA(SCIFA3_RXD_PORT174_MARK, PORT174_FN4, MSEL5CR_8_0),
1458
1459 /* Port175 */
1460 PINMUX_DATA(A0_MARK, PORT175_FN1),
1461 PINMUX_DATA(BS_MARK, PORT175_FN2),
1462 PINMUX_DATA(ET_WOL_MARK, PORT175_FN3),
1463 PINMUX_DATA(SCIFA3_TXD_PORT175_MARK, PORT175_FN4, MSEL5CR_8_0),
1464
1465 /* Port176 */
1466 PINMUX_DATA(ET_GTX_CLK_MARK, PORT176_FN3),
1467
1468 /* Port177 */
1469 PINMUX_DATA(WAIT_PORT177_MARK, PORT177_FN1, MSEL5CR_2_0),
1470 PINMUX_DATA(ET_LINK_MARK, PORT177_FN3),
1471 PINMUX_DATA(IDE_IOWR_MARK, PORT177_FN6),
1472 PINMUX_DATA(SDHI2_WP_PORT177_MARK, PORT177_FN7, MSEL5CR_19_1),
1473
1474 /* Port178 */
1475 PINMUX_DATA(VIO0_D12_MARK, PORT178_FN1),
1476 PINMUX_DATA(VIO1_D4_MARK, PORT178_FN5),
1477 PINMUX_DATA(IDE_IORD_MARK, PORT178_FN6),
1478
1479 /* Port179 */
1480 PINMUX_DATA(VIO0_D11_MARK, PORT179_FN1),
1481 PINMUX_DATA(VIO1_D3_MARK, PORT179_FN5),
1482 PINMUX_DATA(IDE_IORDY_MARK, PORT179_FN6),
1483
1484 /* Port180 */
1485 PINMUX_DATA(VIO0_D10_MARK, PORT180_FN1),
1486 PINMUX_DATA(TPU0TO3_MARK, PORT180_FN4),
1487 PINMUX_DATA(VIO1_D2_MARK, PORT180_FN5),
1488 PINMUX_DATA(IDE_INT_MARK, PORT180_FN6),
1489 PINMUX_DATA(IRQ24_MARK, PORT180_FN0),
1490
1491 /* Port181 */
1492 PINMUX_DATA(VIO0_D9_MARK, PORT181_FN1),
1493 PINMUX_DATA(VIO1_D1_MARK, PORT181_FN5),
1494 PINMUX_DATA(IDE_RST_MARK, PORT181_FN6),
1495
1496 /* Port182 */
1497 PINMUX_DATA(VIO0_D8_MARK, PORT182_FN1),
1498 PINMUX_DATA(VIO1_D0_MARK, PORT182_FN5),
1499 PINMUX_DATA(IDE_DIRECTION_MARK, PORT182_FN6),
1500
1501 /* Port183 */
1502 PINMUX_DATA(DREQ1_MARK, PORT183_FN1),
1503 PINMUX_DATA(BBIF2_TXD2_PORT183_MARK, PORT183_FN2, MSEL5CR_0_1),
1504 PINMUX_DATA(ET_TX_EN_MARK, PORT183_FN3),
1505
1506 /* Port184 */
1507 PINMUX_DATA(DACK1_MARK, PORT184_FN1),
1508 PINMUX_DATA(BBIF2_TSYNC2_PORT184_MARK, PORT184_FN2, MSEL5CR_0_1),
1509 PINMUX_DATA(ET_TX_CLK_MARK, PORT184_FN3),
1510
1511 /* Port185 - Port192 Function1 */
1512 PINMUX_DATA(SCIFA1_SCK_MARK, PORT185_FN1),
1513 PINMUX_DATA(SCIFB_RTS_PORT186_MARK, PORT186_FN1, MSEL5CR_17_0),
1514 PINMUX_DATA(SCIFB_CTS_PORT187_MARK, PORT187_FN1, MSEL5CR_17_0),
1515 PINMUX_DATA(SCIFA0_SCK_MARK, PORT188_FN1),
1516 PINMUX_DATA(SCIFB_SCK_PORT190_MARK, PORT190_FN1, MSEL5CR_17_0),
1517 PINMUX_DATA(SCIFB_RXD_PORT191_MARK, PORT191_FN1, MSEL5CR_17_0),
1518 PINMUX_DATA(SCIFB_TXD_PORT192_MARK, PORT192_FN1, MSEL5CR_17_0),
1519
1520 /* Port185 - Port192 Function3 */
1521 PINMUX_DATA(ET_ERXD0_MARK, PORT185_FN3),
1522 PINMUX_DATA(ET_ERXD1_MARK, PORT186_FN3),
1523 PINMUX_DATA(ET_ERXD2_MARK, PORT187_FN3),
1524 PINMUX_DATA(ET_ERXD3_MARK, PORT188_FN3),
1525 PINMUX_DATA(ET_ERXD4_MARK, PORT189_FN3),
1526 PINMUX_DATA(ET_ERXD5_MARK, PORT190_FN3),
1527 PINMUX_DATA(ET_ERXD6_MARK, PORT191_FN3),
1528 PINMUX_DATA(ET_ERXD7_MARK, PORT192_FN3),
1529
1530 /* Port185 - Port192 Function6 */
1531 PINMUX_DATA(STP1_IPCLK_MARK, PORT185_FN6),
1532 PINMUX_DATA(STP1_IPD0_PORT186_MARK, PORT186_FN6, MSEL5CR_23_0),
1533 PINMUX_DATA(STP1_IPEN_PORT187_MARK, PORT187_FN6, MSEL5CR_23_0),
1534 PINMUX_DATA(STP1_IPSYNC_MARK, PORT188_FN6),
1535 PINMUX_DATA(STP0_IPCLK_MARK, PORT189_FN6),
1536 PINMUX_DATA(STP0_IPD0_MARK, PORT190_FN6),
1537 PINMUX_DATA(STP0_IPEN_MARK, PORT191_FN6),
1538 PINMUX_DATA(STP0_IPSYNC_MARK, PORT192_FN6),
1539
1540 /* Port193 */
1541 PINMUX_DATA(SCIFA0_CTS_MARK, PORT193_FN1),
1542 PINMUX_DATA(RMII_CRS_DV_MARK, PORT193_FN3),
1543 PINMUX_DATA(STP1_IPEN_PORT193_MARK, PORT193_FN6, MSEL5CR_23_1), /* ? */
1544 PINMUX_DATA(LCD1_D17_MARK, PORT193_FN7),
1545
1546 /* Port194 */
1547 PINMUX_DATA(SCIFA0_RTS_MARK, PORT194_FN1),
1548 PINMUX_DATA(RMII_RX_ER_MARK, PORT194_FN3),
1549 PINMUX_DATA(STP1_IPD0_PORT194_MARK, PORT194_FN6, MSEL5CR_23_1), /* ? */
1550 PINMUX_DATA(LCD1_D16_MARK, PORT194_FN7),
1551
1552 /* Port195 */
1553 PINMUX_DATA(SCIFA1_RXD_MARK, PORT195_FN1),
1554 PINMUX_DATA(RMII_RXD0_MARK, PORT195_FN3),
1555 PINMUX_DATA(STP1_IPD3_MARK, PORT195_FN6),
1556 PINMUX_DATA(LCD1_D15_MARK, PORT195_FN7),
1557
1558 /* Port196 */
1559 PINMUX_DATA(SCIFA1_TXD_MARK, PORT196_FN1),
1560 PINMUX_DATA(RMII_RXD1_MARK, PORT196_FN3),
1561 PINMUX_DATA(STP1_IPD2_MARK, PORT196_FN6),
1562 PINMUX_DATA(LCD1_D14_MARK, PORT196_FN7),
1563
1564 /* Port197 */
1565 PINMUX_DATA(SCIFA0_RXD_MARK, PORT197_FN1),
1566 PINMUX_DATA(VIO1_CLK_MARK, PORT197_FN5),
1567 PINMUX_DATA(STP1_IPD5_MARK, PORT197_FN6),
1568 PINMUX_DATA(LCD1_D19_MARK, PORT197_FN7),
1569
1570 /* Port198 */
1571 PINMUX_DATA(SCIFA0_TXD_MARK, PORT198_FN1),
1572 PINMUX_DATA(VIO1_VD_MARK, PORT198_FN5),
1573 PINMUX_DATA(STP1_IPD4_MARK, PORT198_FN6),
1574 PINMUX_DATA(LCD1_D18_MARK, PORT198_FN7),
1575
1576 /* Port199 */
1577 PINMUX_DATA(MEMC_NWE_MARK, PORT199_FN1),
1578 PINMUX_DATA(SCIFA2_SCK_PORT199_MARK, PORT199_FN2, MSEL5CR_7_1),
1579 PINMUX_DATA(RMII_TX_EN_MARK, PORT199_FN3),
1580 PINMUX_DATA(SIM_D_PORT199_MARK, PORT199_FN4, MSEL5CR_21_1),
1581 PINMUX_DATA(STP1_IPD1_MARK, PORT199_FN6),
1582 PINMUX_DATA(LCD1_D13_MARK, PORT199_FN7),
1583
1584 /* Port200 */
1585 PINMUX_DATA(MEMC_NOE_MARK, PORT200_FN1),
1586 PINMUX_DATA(SCIFA2_RXD_MARK, PORT200_FN2),
1587 PINMUX_DATA(RMII_TXD0_MARK, PORT200_FN3),
1588 PINMUX_DATA(STP0_IPD7_MARK, PORT200_FN6),
1589 PINMUX_DATA(LCD1_D12_MARK, PORT200_FN7),
1590
1591 /* Port201 */
1592 PINMUX_DATA(MEMC_WAIT_MARK, PORT201_FN1, MSEL4CR_6_0),
1593 PINMUX_DATA(MEMC_DREQ1_MARK, PORT201_FN1, MSEL4CR_6_1),
1594
1595 PINMUX_DATA(SCIFA2_TXD_MARK, PORT201_FN2),
1596 PINMUX_DATA(RMII_TXD1_MARK, PORT201_FN3),
1597 PINMUX_DATA(STP0_IPD6_MARK, PORT201_FN6),
1598 PINMUX_DATA(LCD1_D11_MARK, PORT201_FN7),
1599
1600 /* Port202 */
1601 PINMUX_DATA(MEMC_BUSCLK_MARK, PORT202_FN1, MSEL4CR_6_0),
1602 PINMUX_DATA(MEMC_A0_MARK, PORT202_FN1, MSEL4CR_6_1),
1603
1604 PINMUX_DATA(MSIOF1_SS2_PORT202_MARK, PORT202_FN2, MSEL4CR_10_1),
1605 PINMUX_DATA(RMII_MDC_MARK, PORT202_FN3),
1606 PINMUX_DATA(TPU0TO2_PORT202_MARK, PORT202_FN4, MSEL5CR_25_1),
1607 PINMUX_DATA(IDE_CS0_MARK, PORT202_FN6),
1608 PINMUX_DATA(SDHI2_CD_PORT202_MARK, PORT202_FN7, MSEL5CR_19_1),
1609 PINMUX_DATA(IRQ21_MARK, PORT202_FN0),
1610
1611 /* Port203 - Port208 Function1 */
1612 PINMUX_DATA(SDHI2_CLK_MARK, PORT203_FN1),
1613 PINMUX_DATA(SDHI2_CMD_MARK, PORT204_FN1),
1614 PINMUX_DATA(SDHI2_D0_MARK, PORT205_FN1),
1615 PINMUX_DATA(SDHI2_D1_MARK, PORT206_FN1),
1616 PINMUX_DATA(SDHI2_D2_MARK, PORT207_FN1),
1617 PINMUX_DATA(SDHI2_D3_MARK, PORT208_FN1),
1618
1619 /* Port203 - Port208 Function3 */
1620 PINMUX_DATA(ET_TX_ER_MARK, PORT203_FN3),
1621 PINMUX_DATA(ET_RX_ER_MARK, PORT204_FN3),
1622 PINMUX_DATA(ET_CRS_MARK, PORT205_FN3),
1623 PINMUX_DATA(ET_MDC_MARK, PORT206_FN3),
1624 PINMUX_DATA(ET_MDIO_MARK, PORT207_FN3),
1625 PINMUX_DATA(RMII_MDIO_MARK, PORT208_FN3),
1626
1627 /* Port203 - Port208 Function6 */
1628 PINMUX_DATA(IDE_A2_MARK, PORT203_FN6),
1629 PINMUX_DATA(IDE_A1_MARK, PORT204_FN6),
1630 PINMUX_DATA(IDE_A0_MARK, PORT205_FN6),
1631 PINMUX_DATA(IDE_IODACK_MARK, PORT206_FN6),
1632 PINMUX_DATA(IDE_IODREQ_MARK, PORT207_FN6),
1633 PINMUX_DATA(IDE_CS1_MARK, PORT208_FN6),
1634
1635 /* Port203 - Port208 Function7 */
1636 PINMUX_DATA(SCIFA4_TXD_PORT203_MARK, PORT203_FN7, MSEL5CR_12_0, MSEL5CR_11_1),
1637 PINMUX_DATA(SCIFA4_RXD_PORT204_MARK, PORT204_FN7, MSEL5CR_12_0, MSEL5CR_11_1),
1638 PINMUX_DATA(SCIFA4_SCK_PORT205_MARK, PORT205_FN7, MSEL5CR_10_1),
1639 PINMUX_DATA(SCIFA5_SCK_PORT206_MARK, PORT206_FN7, MSEL5CR_13_1),
1640 PINMUX_DATA(SCIFA5_RXD_PORT207_MARK, PORT207_FN7, MSEL5CR_15_0, MSEL5CR_14_1),
1641 PINMUX_DATA(SCIFA5_TXD_PORT208_MARK, PORT208_FN7, MSEL5CR_15_0, MSEL5CR_14_1),
1642
1643 /* Port209 */
1644 PINMUX_DATA(VBUS_MARK, PORT209_FN1),
1645 PINMUX_DATA(IRQ7_PORT209_MARK, PORT209_FN0, MSEL1CR_7_0),
1646
1647 /* Port210 */
1648 PINMUX_DATA(IRQ9_PORT210_MARK, PORT210_FN0, MSEL1CR_9_1),
1649 PINMUX_DATA(HDMI_HPD_MARK, PORT210_FN1),
1650
1651 /* Port211 */
1652 PINMUX_DATA(IRQ16_PORT211_MARK, PORT211_FN0, MSEL1CR_16_1),
1653 PINMUX_DATA(HDMI_CEC_MARK, PORT211_FN1),
1654
Laurent Pinchartd5b15212012-12-15 23:51:21 +0100[diff] [blame]1655 /* SDENC */
1656 PINMUX_DATA(SDENC_CPG_MARK, MSEL4CR_19_0),
1657 PINMUX_DATA(SDENC_DV_CLKI_MARK, MSEL4CR_19_1),
1658
1659 /* SYSC */
1660 PINMUX_DATA(RESETP_PULLUP_MARK, MSEL4CR_4_0),
1661 PINMUX_DATA(RESETP_PLAIN_MARK, MSEL4CR_4_1),
1662
1663 /* DEBUG */
1664 PINMUX_DATA(EDEBGREQ_PULLDOWN_MARK, MSEL4CR_1_0),
1665 PINMUX_DATA(EDEBGREQ_PULLUP_MARK, MSEL4CR_1_1),
1666
1667 PINMUX_DATA(TRACEAUD_FROM_VIO_MARK, MSEL5CR_30_0, MSEL5CR_29_0),
1668 PINMUX_DATA(TRACEAUD_FROM_LCDC0_MARK, MSEL5CR_30_0, MSEL5CR_29_1),
1669 PINMUX_DATA(TRACEAUD_FROM_MEMC_MARK, MSEL5CR_30_1, MSEL5CR_29_0),
1670};
1671
Laurent Pincharta3db40a62013-01-02 14:53:37 +0100[diff] [blame]1672static struct sh_pfc_pin pinmux_pins[] = {
Laurent Pinchartd5b15212012-12-15 23:51:21 +0100[diff] [blame]1673 GPIO_PORT_ALL(),
Laurent Pincharta373ed02012-11-29 13:24:07 +0100[diff] [blame]1674};
Laurent Pinchartd5b15212012-12-15 23:51:21 +0100[diff] [blame]1675
Laurent Pinchartb7099c42013-04-18 01:04:30 +0200[diff] [blame]1676/* - BSC -------------------------------------------------------------------- */
1677static const unsigned int bsc_data8_pins[] = {
1678 /* D[0:7] */
1679 157, 156, 155, 154, 153, 152, 151, 150,
1680};
1681static const unsigned int bsc_data8_mux[] = {
1682 D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
1683 D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
1684};
1685static const unsigned int bsc_data16_pins[] = {
1686 /* D[0:15] */
1687 157, 156, 155, 154, 153, 152, 151, 150,
1688 149, 148, 147, 146, 145, 144, 143, 142,
1689};
1690static const unsigned int bsc_data16_mux[] = {
1691 D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
1692 D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
1693 D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK,
1694 D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, D15_NAF15_MARK,
1695};
1696static const unsigned int bsc_data32_pins[] = {
1697 /* D[0:31] */
1698 157, 156, 155, 154, 153, 152, 151, 150,
1699 149, 148, 147, 146, 145, 144, 143, 142,
1700 171, 170, 169, 168, 167, 166, 173, 172,
1701 165, 164, 163, 162, 161, 160, 159, 158,
1702};
1703static const unsigned int bsc_data32_mux[] = {
1704 D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
1705 D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
1706 D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK,
1707 D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, D15_NAF15_MARK,
1708 D16_MARK, D17_MARK, D18_MARK, D19_MARK,
1709 D20_MARK, D21_MARK, D22_MARK, D23_MARK,
1710 D24_MARK, D25_MARK, D26_MARK, D27_MARK,
1711 D28_MARK, D29_MARK, D30_MARK, D31_MARK,
1712};
1713static const unsigned int bsc_cs0_pins[] = {
1714 /* CS */
1715 109,
1716};
1717static const unsigned int bsc_cs0_mux[] = {
1718 CS0_MARK,
1719};
1720static const unsigned int bsc_cs2_pins[] = {
1721 /* CS */
1722 110,
1723};
1724static const unsigned int bsc_cs2_mux[] = {
1725 CS2_MARK,
1726};
1727static const unsigned int bsc_cs4_pins[] = {
1728 /* CS */
1729 111,
1730};
1731static const unsigned int bsc_cs4_mux[] = {
1732 CS4_MARK,
1733};
1734static const unsigned int bsc_cs5a_0_pins[] = {
1735 /* CS */
1736 105,
1737};
1738static const unsigned int bsc_cs5a_0_mux[] = {
1739 CS5A_PORT105_MARK,
1740};
1741static const unsigned int bsc_cs5a_1_pins[] = {
1742 /* CS */
1743 19,
1744};
1745static const unsigned int bsc_cs5a_1_mux[] = {
1746 CS5A_PORT19_MARK,
1747};
1748static const unsigned int bsc_cs5b_pins[] = {
1749 /* CS */
1750 103,
1751};
1752static const unsigned int bsc_cs5b_mux[] = {
1753 CS5B_MARK,
1754};
1755static const unsigned int bsc_cs6a_pins[] = {
1756 /* CS */
1757 104,
1758};
1759static const unsigned int bsc_cs6a_mux[] = {
1760 CS6A_MARK,
1761};
1762static const unsigned int bsc_rd_we8_pins[] = {
1763 /* RD, WE[0] */
1764 115, 113,
1765};
1766static const unsigned int bsc_rd_we8_mux[] = {
1767 RD_FSC_MARK, WE0_FWE_MARK,
1768};
1769static const unsigned int bsc_rd_we16_pins[] = {
1770 /* RD, WE[0:1] */
1771 115, 113, 112,
1772};
1773static const unsigned int bsc_rd_we16_mux[] = {
1774 RD_FSC_MARK, WE0_FWE_MARK, WE1_MARK,
1775};
1776static const unsigned int bsc_rd_we32_pins[] = {
1777 /* RD, WE[0:3] */
1778 115, 113, 112, 108, 107,
1779};
1780static const unsigned int bsc_rd_we32_mux[] = {
1781 RD_FSC_MARK, WE0_FWE_MARK, WE1_MARK, WE2_ICIORD_MARK, WE3_ICIOWR_MARK,
1782};
1783static const unsigned int bsc_bs_pins[] = {
1784 /* BS */
1785 175,
1786};
1787static const unsigned int bsc_bs_mux[] = {
1788 BS_MARK,
1789};
1790static const unsigned int bsc_rdwr_pins[] = {
1791 /* RDWR */
1792 114,
1793};
1794static const unsigned int bsc_rdwr_mux[] = {
1795 RDWR_MARK,
1796};
Laurent Pinchart0ec939b2013-04-18 01:04:30 +0200[diff] [blame]1797/* - CEU0 ------------------------------------------------------------------- */
1798static const unsigned int ceu0_data_0_7_pins[] = {
1799 /* D[0:7] */
1800 34, 33, 32, 31, 30, 29, 28, 27,
1801};
1802static const unsigned int ceu0_data_0_7_mux[] = {
1803 VIO0_D0_MARK, VIO0_D1_MARK, VIO0_D2_MARK, VIO0_D3_MARK,
1804 VIO0_D4_MARK, VIO0_D5_MARK, VIO0_D6_MARK, VIO0_D7_MARK,
1805};
1806static const unsigned int ceu0_data_8_15_0_pins[] = {
1807 /* D[8:15] */
1808 182, 181, 180, 179, 178, 26, 25, 24,
1809};
1810static const unsigned int ceu0_data_8_15_0_mux[] = {
1811 VIO0_D8_MARK, VIO0_D9_MARK, VIO0_D10_MARK, VIO0_D11_MARK,
1812 VIO0_D12_MARK, VIO0_D13_PORT26_MARK, VIO0_D14_PORT25_MARK,
1813 VIO0_D15_PORT24_MARK,
1814};
1815static const unsigned int ceu0_data_8_15_1_pins[] = {
1816 /* D[8:15] */
1817 182, 181, 180, 179, 178, 22, 95, 96,
1818};
1819static const unsigned int ceu0_data_8_15_1_mux[] = {
1820 VIO0_D8_MARK, VIO0_D9_MARK, VIO0_D10_MARK, VIO0_D11_MARK,
1821 VIO0_D12_MARK, VIO0_D13_PORT22_MARK, VIO0_D14_PORT95_MARK,
1822 VIO0_D15_PORT96_MARK,
1823};
1824static const unsigned int ceu0_clk_0_pins[] = {
1825 /* CKO */
1826 36,
1827};
1828static const unsigned int ceu0_clk_0_mux[] = {
1829 VIO_CKO_MARK,
1830};
1831static const unsigned int ceu0_clk_1_pins[] = {
1832 /* CKO */
1833 14,
1834};
1835static const unsigned int ceu0_clk_1_mux[] = {
1836 VIO_CKO1_MARK,
1837};
1838static const unsigned int ceu0_clk_2_pins[] = {
1839 /* CKO */
1840 15,
1841};
1842static const unsigned int ceu0_clk_2_mux[] = {
1843 VIO_CKO2_MARK,
1844};
1845static const unsigned int ceu0_sync_pins[] = {
1846 /* CLK, VD, HD */
1847 35, 39, 37,
1848};
1849static const unsigned int ceu0_sync_mux[] = {
1850 VIO0_CLK_MARK, VIO0_VD_MARK, VIO0_HD_MARK,
1851};
1852static const unsigned int ceu0_field_pins[] = {
1853 /* FIELD */
1854 38,
1855};
1856static const unsigned int ceu0_field_mux[] = {
1857 VIO0_FIELD_MARK,
1858};
1859/* - CEU1 ------------------------------------------------------------------- */
1860static const unsigned int ceu1_data_pins[] = {
1861 /* D[0:7] */
1862 182, 181, 180, 179, 178, 26, 25, 24,
1863};
1864static const unsigned int ceu1_data_mux[] = {
1865 VIO1_D0_MARK, VIO1_D1_MARK, VIO1_D2_MARK, VIO1_D3_MARK,
1866 VIO1_D4_MARK, VIO1_D5_MARK, VIO1_D6_MARK, VIO1_D7_MARK,
1867};
1868static const unsigned int ceu1_clk_pins[] = {
1869 /* CKO */
1870 23,
1871};
1872static const unsigned int ceu1_clk_mux[] = {
1873 VIO_CKO_1_MARK,
1874};
1875static const unsigned int ceu1_sync_pins[] = {
1876 /* CLK, VD, HD */
1877 197, 198, 160,
1878};
1879static const unsigned int ceu1_sync_mux[] = {
1880 VIO1_CLK_MARK, VIO1_VD_MARK, VIO1_HD_MARK,
1881};
1882static const unsigned int ceu1_field_pins[] = {
1883 /* FIELD */
1884 21,
1885};
1886static const unsigned int ceu1_field_mux[] = {
1887 VIO1_FIELD_MARK,
1888};
Laurent Pinchart909dd952013-04-18 01:04:30 +0200[diff] [blame]1889/* - FSIA ------------------------------------------------------------------- */
1890static const unsigned int fsia_mclk_in_pins[] = {
1891 /* CK */
1892 11,
1893};
1894static const unsigned int fsia_mclk_in_mux[] = {
1895 FSIACK_MARK,
1896};
1897static const unsigned int fsia_mclk_out_pins[] = {
1898 /* OMC */
1899 10,
1900};
1901static const unsigned int fsia_mclk_out_mux[] = {
1902 FSIAOMC_MARK,
1903};
1904static const unsigned int fsia_sclk_in_pins[] = {
1905 /* ILR, IBT */
1906 12, 13,
1907};
1908static const unsigned int fsia_sclk_in_mux[] = {
1909 FSIAILR_MARK, FSIAIBT_MARK,
1910};
1911static const unsigned int fsia_sclk_out_pins[] = {
1912 /* OLR, OBT */
1913 7, 8,
1914};
1915static const unsigned int fsia_sclk_out_mux[] = {
1916 FSIAOLR_MARK, FSIAOBT_MARK,
1917};
1918static const unsigned int fsia_data_in_0_pins[] = {
1919 /* ISLD */
1920 0,
1921};
1922static const unsigned int fsia_data_in_0_mux[] = {
1923 FSIAISLD_PORT0_MARK,
1924};
1925static const unsigned int fsia_data_in_1_pins[] = {
1926 /* ISLD */
1927 5,
1928};
1929static const unsigned int fsia_data_in_1_mux[] = {
1930 FSIAISLD_PORT5_MARK,
1931};
1932static const unsigned int fsia_data_out_0_pins[] = {
1933 /* OSLD */
1934 9,
1935};
1936static const unsigned int fsia_data_out_0_mux[] = {
1937 FSIAOSLD_MARK,
1938};
1939static const unsigned int fsia_data_out_1_pins[] = {
1940 /* OSLD */
1941 0,
1942};
1943static const unsigned int fsia_data_out_1_mux[] = {
1944 FSIAOSLD1_MARK,
1945};
1946static const unsigned int fsia_data_out_2_pins[] = {
1947 /* OSLD */
1948 1,
1949};
1950static const unsigned int fsia_data_out_2_mux[] = {
1951 FSIAOSLD2_MARK,
1952};
1953static const unsigned int fsia_spdif_0_pins[] = {
1954 /* SPDIF */
1955 9,
1956};
1957static const unsigned int fsia_spdif_0_mux[] = {
1958 FSIASPDIF_PORT9_MARK,
1959};
1960static const unsigned int fsia_spdif_1_pins[] = {
1961 /* SPDIF */
1962 18,
1963};
1964static const unsigned int fsia_spdif_1_mux[] = {
1965 FSIASPDIF_PORT18_MARK,
1966};
1967/* - FSIB ------------------------------------------------------------------- */
1968static const unsigned int fsib_mclk_in_pins[] = {
1969 /* CK */
1970 11,
1971};
1972static const unsigned int fsib_mclk_in_mux[] = {
1973 FSIBCK_MARK,
1974};
Laurent Pinchartbae11d32013-04-18 01:04:30 +0200[diff] [blame]1975/* - GETHER ----------------------------------------------------------------- */
1976static const unsigned int gether_rmii_pins[] = {
1977 /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK, MDC, MDIO */
1978 195, 196, 194, 193, 200, 201, 199, 159, 202, 208,
1979};
1980static const unsigned int gether_rmii_mux[] = {
1981 RMII_RXD0_MARK, RMII_RXD1_MARK, RMII_RX_ER_MARK, RMII_CRS_DV_MARK,
1982 RMII_TXD0_MARK, RMII_TXD1_MARK, RMII_TX_EN_MARK, RMII_REF50CK_MARK,
1983 RMII_MDC_MARK, RMII_MDIO_MARK,
1984};
1985static const unsigned int gether_mii_pins[] = {
1986 /* RXD[0:3], RX_CLK, RX_DV, RX_ER
1987 * TXD[0:3], TX_CLK, TX_EN, TX_ER
1988 * CRS, COL, MDC, MDIO,
1989 */
1990 185, 186, 187, 188, 174, 161, 204,
1991 171, 170, 169, 168, 184, 183, 203,
1992 205, 163, 206, 207,
1993};
1994static const unsigned int gether_mii_mux[] = {
1995 ET_ERXD0_MARK, ET_ERXD1_MARK, ET_ERXD2_MARK, ET_ERXD3_MARK,
1996 ET_RX_CLK_MARK, ET_RX_DV_MARK, ET_RX_ER_MARK,
1997 ET_ETXD0_MARK, ET_ETXD1_MARK, ET_ETXD2_MARK, ET_ETXD3_MARK,
1998 ET_TX_CLK_MARK, ET_TX_EN_MARK, ET_TX_ER_MARK,
1999 ET_CRS_MARK, ET_COL_MARK, ET_MDC_MARK, ET_MDIO_MARK,
2000};
2001static const unsigned int gether_gmii_pins[] = {
2002 /* RXD[0:7], RX_CLK, RX_DV, RX_ER
2003 * TXD[0:7], GTX_CLK, TX_CLK, TX_EN, TX_ER
2004 * CRS, COL, MDC, MDIO, REF125CK_MARK,
2005 */
2006 185, 186, 187, 188, 189, 190, 191, 192, 174, 161, 204,
2007 171, 170, 169, 168, 167, 166, 173, 172, 176, 184, 183, 203,
2008 205, 163, 206, 207,
2009};
2010static const unsigned int gether_gmii_mux[] = {
2011 ET_ERXD0_MARK, ET_ERXD1_MARK, ET_ERXD2_MARK, ET_ERXD3_MARK,
2012 ET_ERXD4_MARK, ET_ERXD5_MARK, ET_ERXD6_MARK, ET_ERXD7_MARK,
2013 ET_RX_CLK_MARK, ET_RX_DV_MARK, ET_RX_ER_MARK,
2014 ET_ETXD0_MARK, ET_ETXD1_MARK, ET_ETXD2_MARK, ET_ETXD3_MARK,
2015 ET_ETXD4_MARK, ET_ETXD5_MARK, ET_ETXD6_MARK, ET_ETXD7_MARK,
2016 ET_GTX_CLK_MARK, ET_TX_CLK_MARK, ET_TX_EN_MARK, ET_TX_ER_MARK,
2017 ET_CRS_MARK, ET_COL_MARK, ET_MDC_MARK, ET_MDIO_MARK,
2018 RMII_REF125CK_MARK,
2019};
2020static const unsigned int gether_int_pins[] = {
2021 /* PHY_INT */
2022 164,
2023};
2024static const unsigned int gether_int_mux[] = {
2025 ET_PHY_INT_MARK,
2026};
2027static const unsigned int gether_link_pins[] = {
2028 /* LINK */
2029 177,
2030};
2031static const unsigned int gether_link_mux[] = {
2032 ET_LINK_MARK,
2033};
2034static const unsigned int gether_wol_pins[] = {
2035 /* WOL */
2036 175,
2037};
2038static const unsigned int gether_wol_mux[] = {
2039 ET_WOL_MARK,
2040};
Laurent Pincharta37d6062013-04-18 01:04:30 +0200[diff] [blame]2041/* - HDMI ------------------------------------------------------------------- */
2042static const unsigned int hdmi_pins[] = {
2043 /* HPD, CEC */
2044 210, 211,
2045};
2046static const unsigned int hdmi_mux[] = {
2047 HDMI_HPD_MARK, HDMI_CEC_MARK,
2048};
Bastian Hecht09bbc1f2013-04-09 10:48:50 +0000[diff] [blame]2049/* - INTC ------------------------------------------------------------------- */
2050IRQC_PINS_MUX(0, 0, 2);
2051IRQC_PINS_MUX(0, 1, 13);
2052IRQC_PIN_MUX(1, 20);
2053IRQC_PINS_MUX(2, 0, 11);
2054IRQC_PINS_MUX(2, 1, 12);
2055IRQC_PINS_MUX(3, 0, 10);
2056IRQC_PINS_MUX(3, 1, 14);
2057IRQC_PINS_MUX(4, 0, 15);
2058IRQC_PINS_MUX(4, 1, 172);
2059IRQC_PINS_MUX(5, 0, 0);
2060IRQC_PINS_MUX(5, 1, 1);
2061IRQC_PINS_MUX(6, 0, 121);
2062IRQC_PINS_MUX(6, 1, 173);
2063IRQC_PINS_MUX(7, 0, 120);
2064IRQC_PINS_MUX(7, 1, 209);
2065IRQC_PIN_MUX(8, 119);
2066IRQC_PINS_MUX(9, 0, 118);
2067IRQC_PINS_MUX(9, 1, 210);
2068IRQC_PIN_MUX(10, 19);
2069IRQC_PIN_MUX(11, 104);
2070IRQC_PINS_MUX(12, 0, 42);
2071IRQC_PINS_MUX(12, 1, 97);
2072IRQC_PINS_MUX(13, 0, 64);
2073IRQC_PINS_MUX(13, 1, 98);
2074IRQC_PINS_MUX(14, 0, 63);
2075IRQC_PINS_MUX(14, 1, 99);
2076IRQC_PINS_MUX(15, 0, 62);
2077IRQC_PINS_MUX(15, 1, 100);
2078IRQC_PINS_MUX(16, 0, 68);
2079IRQC_PINS_MUX(16, 1, 211);
2080IRQC_PIN_MUX(17, 69);
2081IRQC_PIN_MUX(18, 70);
2082IRQC_PIN_MUX(19, 71);
2083IRQC_PIN_MUX(20, 67);
2084IRQC_PIN_MUX(21, 202);
2085IRQC_PIN_MUX(22, 95);
2086IRQC_PIN_MUX(23, 96);
2087IRQC_PIN_MUX(24, 180);
2088IRQC_PIN_MUX(25, 38);
2089IRQC_PINS_MUX(26, 0, 58);
2090IRQC_PINS_MUX(26, 1, 81);
2091IRQC_PINS_MUX(27, 0, 57);
2092IRQC_PINS_MUX(27, 1, 168);
2093IRQC_PINS_MUX(28, 0, 56);
2094IRQC_PINS_MUX(28, 1, 169);
2095IRQC_PINS_MUX(29, 0, 50);
2096IRQC_PINS_MUX(29, 1, 170);
2097IRQC_PINS_MUX(30, 0, 49);
2098IRQC_PINS_MUX(30, 1, 171);
2099IRQC_PINS_MUX(31, 0, 41);
2100IRQC_PINS_MUX(31, 1, 167);
2101
Laurent Pinchart06c7dd82013-01-03 13:07:05 +0100[diff] [blame]2102/* - LCD0 ------------------------------------------------------------------- */
2103static const unsigned int lcd0_data8_pins[] = {
2104 /* D[0:7] */
2105 58, 57, 56, 55, 54, 53, 52, 51,
2106};
2107static const unsigned int lcd0_data8_mux[] = {
2108 LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
2109 LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
2110};
2111static const unsigned int lcd0_data9_pins[] = {
2112 /* D[0:8] */
2113 58, 57, 56, 55, 54, 53, 52, 51,
2114 50,
2115};
2116static const unsigned int lcd0_data9_mux[] = {
2117 LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
2118 LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
2119 LCD0_D8_MARK,
2120};
2121static const unsigned int lcd0_data12_pins[] = {
2122 /* D[0:11] */
2123 58, 57, 56, 55, 54, 53, 52, 51,
2124 50, 49, 48, 47,
2125};
2126static const unsigned int lcd0_data12_mux[] = {
2127 LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
2128 LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
2129 LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
2130};
2131static const unsigned int lcd0_data16_pins[] = {
2132 /* D[0:15] */
2133 58, 57, 56, 55, 54, 53, 52, 51,
2134 50, 49, 48, 47, 46, 45, 44, 43,
2135};
2136static const unsigned int lcd0_data16_mux[] = {
2137 LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
2138 LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
2139 LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
2140 LCD0_D12_MARK, LCD0_D13_MARK, LCD0_D14_MARK, LCD0_D15_MARK,
2141};
2142static const unsigned int lcd0_data18_pins[] = {
2143 /* D[0:17] */
2144 58, 57, 56, 55, 54, 53, 52, 51,
2145 50, 49, 48, 47, 46, 45, 44, 43,
2146 42, 41,
2147};
2148static const unsigned int lcd0_data18_mux[] = {
2149 LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
2150 LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
2151 LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
2152 LCD0_D12_MARK, LCD0_D13_MARK, LCD0_D14_MARK, LCD0_D15_MARK,
2153 LCD0_D16_MARK, LCD0_D17_MARK,
2154};
2155static const unsigned int lcd0_data24_0_pins[] = {
2156 /* D[0:23] */
2157 58, 57, 56, 55, 54, 53, 52, 51,
2158 50, 49, 48, 47, 46, 45, 44, 43,
2159 42, 41, 40, 4, 3, 2, 0, 1,
2160};
2161static const unsigned int lcd0_data24_0_mux[] = {
2162 LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
2163 LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
2164 LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
2165 LCD0_D12_MARK, LCD0_D13_MARK, LCD0_D14_MARK, LCD0_D15_MARK,
2166 LCD0_D16_MARK, LCD0_D17_MARK, LCD0_D18_PORT40_MARK, LCD0_D19_PORT4_MARK,
2167 LCD0_D20_PORT3_MARK, LCD0_D21_PORT2_MARK, LCD0_D22_PORT0_MARK,
2168 LCD0_D23_PORT1_MARK,
2169};
2170static const unsigned int lcd0_data24_1_pins[] = {
2171 /* D[0:23] */
2172 58, 57, 56, 55, 54, 53, 52, 51,
2173 50, 49, 48, 47, 46, 45, 44, 43,
2174 42, 41, 163, 162, 161, 158, 160, 159,
2175};
2176static const unsigned int lcd0_data24_1_mux[] = {
2177 LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
2178 LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
2179 LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
2180 LCD0_D16_MARK, LCD0_D17_MARK, LCD0_D18_PORT163_MARK,
2181 LCD0_D19_PORT162_MARK, LCD0_D20_PORT161_MARK, LCD0_D21_PORT158_MARK,
2182 LCD0_D22_PORT160_MARK, LCD0_D23_PORT159_MARK,
2183};
2184static const unsigned int lcd0_display_pins[] = {
2185 /* DON, VCPWC, VEPWC */
2186 61, 59, 60,
2187};
2188static const unsigned int lcd0_display_mux[] = {
2189 LCD0_DON_MARK, LCD0_VCPWC_MARK, LCD0_VEPWC_MARK,
2190};
2191static const unsigned int lcd0_lclk_0_pins[] = {
2192 /* LCLK */
2193 102,
2194};
2195static const unsigned int lcd0_lclk_0_mux[] = {
2196 LCD0_LCLK_PORT102_MARK,
2197};
2198static const unsigned int lcd0_lclk_1_pins[] = {
2199 /* LCLK */
2200 165,
2201};
2202static const unsigned int lcd0_lclk_1_mux[] = {
2203 LCD0_LCLK_PORT165_MARK,
2204};
2205static const unsigned int lcd0_sync_pins[] = {
2206 /* VSYN, HSYN, DCK, DISP */
2207 63, 64, 62, 65,
2208};
2209static const unsigned int lcd0_sync_mux[] = {
2210 LCD0_VSYN_MARK, LCD0_HSYN_MARK, LCD0_DCK_MARK, LCD0_DISP_MARK,
2211};
2212static const unsigned int lcd0_sys_pins[] = {
2213 /* CS, WR, RD, RS */
2214 64, 62, 164, 65,
2215};
2216static const unsigned int lcd0_sys_mux[] = {
2217 LCD0_CS_MARK, LCD0_WR_MARK, LCD0_RD_MARK, LCD0_RS_MARK,
2218};
2219/* - LCD1 ------------------------------------------------------------------- */
2220static const unsigned int lcd1_data8_pins[] = {
2221 /* D[0:7] */
2222 4, 3, 2, 1, 0, 91, 92, 23,
2223};
2224static const unsigned int lcd1_data8_mux[] = {
2225 LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
2226 LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
2227};
2228static const unsigned int lcd1_data9_pins[] = {
2229 /* D[0:8] */
2230 4, 3, 2, 1, 0, 91, 92, 23,
2231 93,
2232};
2233static const unsigned int lcd1_data9_mux[] = {
2234 LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
2235 LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
2236 LCD1_D8_MARK,
2237};
2238static const unsigned int lcd1_data12_pins[] = {
2239 /* D[0:12] */
2240 4, 3, 2, 1, 0, 91, 92, 23,
2241 93, 94, 21, 201,
2242};
2243static const unsigned int lcd1_data12_mux[] = {
2244 LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
2245 LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
2246 LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
2247};
2248static const unsigned int lcd1_data16_pins[] = {
2249 /* D[0:15] */
2250 4, 3, 2, 1, 0, 91, 92, 23,
2251 93, 94, 21, 201, 200, 199, 196, 195,
2252};
2253static const unsigned int lcd1_data16_mux[] = {
2254 LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
2255 LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
2256 LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
2257 LCD1_D12_MARK, LCD1_D13_MARK, LCD1_D14_MARK, LCD1_D15_MARK,
2258};
2259static const unsigned int lcd1_data18_pins[] = {
2260 /* D[0:17] */
2261 4, 3, 2, 1, 0, 91, 92, 23,
2262 93, 94, 21, 201, 200, 199, 196, 195,
2263 194, 193,
2264};
2265static const unsigned int lcd1_data18_mux[] = {
2266 LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
2267 LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
2268 LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
2269 LCD1_D12_MARK, LCD1_D13_MARK, LCD1_D14_MARK, LCD1_D15_MARK,
2270 LCD1_D16_MARK, LCD1_D17_MARK,
2271};
2272static const unsigned int lcd1_data24_pins[] = {
2273 /* D[0:23] */
2274 4, 3, 2, 1, 0, 91, 92, 23,
2275 93, 94, 21, 201, 200, 199, 196, 195,
2276 194, 193, 198, 197, 75, 74, 15, 14,
2277};
2278static const unsigned int lcd1_data24_mux[] = {
2279 LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
2280 LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
2281 LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
2282 LCD1_D12_MARK, LCD1_D13_MARK, LCD1_D14_MARK, LCD1_D15_MARK,
2283 LCD1_D16_MARK, LCD1_D17_MARK, LCD1_D18_MARK, LCD1_D19_MARK,
2284 LCD1_D20_MARK, LCD1_D21_MARK, LCD1_D22_MARK, LCD1_D23_MARK,
2285};
2286static const unsigned int lcd1_display_pins[] = {
2287 /* DON, VCPWC, VEPWC */
2288 100, 5, 6,
2289};
2290static const unsigned int lcd1_display_mux[] = {
2291 LCD1_DON_MARK, LCD1_VCPWC_MARK, LCD1_VEPWC_MARK,
2292};
2293static const unsigned int lcd1_lclk_pins[] = {
2294 /* LCLK */
2295 40,
2296};
2297static const unsigned int lcd1_lclk_mux[] = {
2298 LCD1_LCLK_MARK,
2299};
2300static const unsigned int lcd1_sync_pins[] = {
2301 /* VSYN, HSYN, DCK, DISP */
2302 98, 97, 99, 12,
2303};
2304static const unsigned int lcd1_sync_mux[] = {
2305 LCD1_VSYN_MARK, LCD1_HSYN_MARK, LCD1_DCK_MARK, LCD1_DISP_MARK,
2306};
2307static const unsigned int lcd1_sys_pins[] = {
2308 /* CS, WR, RD, RS */
2309 97, 99, 13, 12,
2310};
2311static const unsigned int lcd1_sys_mux[] = {
2312 LCD1_CS_MARK, LCD1_WR_MARK, LCD1_RD_MARK, LCD1_RS_MARK,
2313};
Guennadi Liakhovetski8b2810b2013-01-23 17:37:44 +0100[diff] [blame]2314/* - MMCIF ------------------------------------------------------------------ */
2315static const unsigned int mmc0_data1_0_pins[] = {
2316 /* D[0] */
2317 68,
2318};
2319static const unsigned int mmc0_data1_0_mux[] = {
2320 MMC0_D0_PORT68_MARK,
2321};
2322static const unsigned int mmc0_data4_0_pins[] = {
2323 /* D[0:3] */
2324 68, 69, 70, 71,
2325};
2326static const unsigned int mmc0_data4_0_mux[] = {
2327 MMC0_D0_PORT68_MARK, MMC0_D1_PORT69_MARK, MMC0_D2_PORT70_MARK, MMC0_D3_PORT71_MARK,
2328};
2329static const unsigned int mmc0_data8_0_pins[] = {
2330 /* D[0:7] */
2331 68, 69, 70, 71, 72, 73, 74, 75,
2332};
2333static const unsigned int mmc0_data8_0_mux[] = {
2334 MMC0_D0_PORT68_MARK, MMC0_D1_PORT69_MARK, MMC0_D2_PORT70_MARK, MMC0_D3_PORT71_MARK,
2335 MMC0_D4_PORT72_MARK, MMC0_D5_PORT73_MARK, MMC0_D6_PORT74_MARK, MMC0_D7_PORT75_MARK,
2336};
2337static const unsigned int mmc0_ctrl_0_pins[] = {
2338 /* CMD, CLK */
2339 67, 66,
2340};
2341static const unsigned int mmc0_ctrl_0_mux[] = {
2342 MMC0_CMD_PORT67_MARK, MMC0_CLK_PORT66_MARK,
2343};
2344
2345static const unsigned int mmc0_data1_1_pins[] = {
2346 /* D[0] */
2347 149,
2348};
2349static const unsigned int mmc0_data1_1_mux[] = {
2350 MMC1_D0_PORT149_MARK,
2351};
2352static const unsigned int mmc0_data4_1_pins[] = {
2353 /* D[0:3] */
2354 149, 148, 147, 146,
2355};
2356static const unsigned int mmc0_data4_1_mux[] = {
2357 MMC1_D0_PORT149_MARK, MMC1_D1_PORT148_MARK, MMC1_D2_PORT147_MARK, MMC1_D3_PORT146_MARK,
2358};
2359static const unsigned int mmc0_data8_1_pins[] = {
2360 /* D[0:7] */
2361 149, 148, 147, 146, 145, 144, 143, 142,
2362};
2363static const unsigned int mmc0_data8_1_mux[] = {
2364 MMC1_D0_PORT149_MARK, MMC1_D1_PORT148_MARK, MMC1_D2_PORT147_MARK, MMC1_D3_PORT146_MARK,
2365 MMC1_D4_PORT145_MARK, MMC1_D5_PORT144_MARK, MMC1_D6_PORT143_MARK, MMC1_D7_PORT142_MARK,
2366};
2367static const unsigned int mmc0_ctrl_1_pins[] = {
2368 /* CMD, CLK */
2369 104, 103,
2370};
2371static const unsigned int mmc0_ctrl_1_mux[] = {
2372 MMC1_CMD_PORT104_MARK, MMC1_CLK_PORT103_MARK,
2373};
Laurent Pinchartcdd2c762013-04-18 01:04:30 +0200[diff] [blame]2374/* - SCIFA0 ----------------------------------------------------------------- */
2375static const unsigned int scifa0_data_pins[] = {
2376 /* RXD, TXD */
2377 197, 198,
2378};
2379static const unsigned int scifa0_data_mux[] = {
2380 SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
2381};
2382static const unsigned int scifa0_clk_pins[] = {
2383 /* SCK */
2384 188,
2385};
2386static const unsigned int scifa0_clk_mux[] = {
2387 SCIFA0_SCK_MARK,
2388};
2389static const unsigned int scifa0_ctrl_pins[] = {
2390 /* RTS, CTS */
2391 194, 193,
2392};
2393static const unsigned int scifa0_ctrl_mux[] = {
2394 SCIFA0_RTS_MARK, SCIFA0_CTS_MARK,
2395};
Bastian Hecht8fbfdbb2013-04-17 10:34:01 +0000[diff] [blame]2396/* - SCIFA1 ----------------------------------------------------------------- */
2397static const unsigned int scifa1_data_pins[] = {
2398 /* RXD, TXD */
2399 195, 196,
2400};
2401static const unsigned int scifa1_data_mux[] = {
2402 SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
2403};
Laurent Pinchartcdd2c762013-04-18 01:04:30 +0200[diff] [blame]2404static const unsigned int scifa1_clk_pins[] = {
2405 /* SCK */
2406 185,
2407};
2408static const unsigned int scifa1_clk_mux[] = {
2409 SCIFA1_SCK_MARK,
2410};
2411static const unsigned int scifa1_ctrl_pins[] = {
2412 /* RTS, CTS */
2413 23, 21,
2414};
2415static const unsigned int scifa1_ctrl_mux[] = {
2416 SCIFA1_RTS_MARK, SCIFA1_CTS_MARK,
2417};
2418/* - SCIFA2 ----------------------------------------------------------------- */
2419static const unsigned int scifa2_data_pins[] = {
2420 /* RXD, TXD */
2421 200, 201,
2422};
2423static const unsigned int scifa2_data_mux[] = {
2424 SCIFA2_RXD_MARK, SCIFA2_TXD_MARK,
2425};
2426static const unsigned int scifa2_clk_0_pins[] = {
2427 /* SCK */
2428 22,
2429};
2430static const unsigned int scifa2_clk_0_mux[] = {
2431 SCIFA2_SCK_PORT22_MARK,
2432};
2433static const unsigned int scifa2_clk_1_pins[] = {
2434 /* SCK */
2435 199,
2436};
2437static const unsigned int scifa2_clk_1_mux[] = {
2438 SCIFA2_SCK_PORT199_MARK,
2439};
2440static const unsigned int scifa2_ctrl_pins[] = {
2441 /* RTS, CTS */
2442 96, 95,
2443};
2444static const unsigned int scifa2_ctrl_mux[] = {
2445 SCIFA2_RTS_MARK, SCIFA2_CTS_MARK,
2446};
2447/* - SCIFA3 ----------------------------------------------------------------- */
2448static const unsigned int scifa3_data_0_pins[] = {
2449 /* RXD, TXD */
2450 174, 175,
2451};
2452static const unsigned int scifa3_data_0_mux[] = {
2453 SCIFA3_RXD_PORT174_MARK, SCIFA3_TXD_PORT175_MARK,
2454};
2455static const unsigned int scifa3_clk_0_pins[] = {
2456 /* SCK */
2457 116,
2458};
2459static const unsigned int scifa3_clk_0_mux[] = {
2460 SCIFA3_SCK_PORT116_MARK,
2461};
2462static const unsigned int scifa3_ctrl_0_pins[] = {
2463 /* RTS, CTS */
2464 105, 117,
2465};
2466static const unsigned int scifa3_ctrl_0_mux[] = {
2467 SCIFA3_RTS_PORT105_MARK, SCIFA3_CTS_PORT117_MARK,
2468};
2469static const unsigned int scifa3_data_1_pins[] = {
2470 /* RXD, TXD */
2471 159, 160,
2472};
2473static const unsigned int scifa3_data_1_mux[] = {
2474 SCIFA3_RXD_PORT159_MARK, SCIFA3_TXD_PORT160_MARK,
2475};
2476static const unsigned int scifa3_clk_1_pins[] = {
2477 /* SCK */
2478 158,
2479};
2480static const unsigned int scifa3_clk_1_mux[] = {
2481 SCIFA3_SCK_PORT158_MARK,
2482};
2483static const unsigned int scifa3_ctrl_1_pins[] = {
2484 /* RTS, CTS */
2485 161, 162,
2486};
2487static const unsigned int scifa3_ctrl_1_mux[] = {
2488 SCIFA3_RTS_PORT161_MARK, SCIFA3_CTS_PORT162_MARK,
2489};
2490/* - SCIFA4 ----------------------------------------------------------------- */
2491static const unsigned int scifa4_data_0_pins[] = {
2492 /* RXD, TXD */
2493 12, 13,
2494};
2495static const unsigned int scifa4_data_0_mux[] = {
2496 SCIFA4_RXD_PORT12_MARK, SCIFA4_TXD_PORT13_MARK,
2497};
2498static const unsigned int scifa4_data_1_pins[] = {
2499 /* RXD, TXD */
2500 204, 203,
2501};
2502static const unsigned int scifa4_data_1_mux[] = {
2503 SCIFA4_RXD_PORT204_MARK, SCIFA4_TXD_PORT203_MARK,
2504};
2505static const unsigned int scifa4_data_2_pins[] = {
2506 /* RXD, TXD */
2507 94, 93,
2508};
2509static const unsigned int scifa4_data_2_mux[] = {
2510 SCIFA4_RXD_PORT94_MARK, SCIFA4_TXD_PORT93_MARK,
2511};
2512static const unsigned int scifa4_clk_0_pins[] = {
2513 /* SCK */
2514 21,
2515};
2516static const unsigned int scifa4_clk_0_mux[] = {
2517 SCIFA4_SCK_PORT21_MARK,
2518};
2519static const unsigned int scifa4_clk_1_pins[] = {
2520 /* SCK */
2521 205,
2522};
2523static const unsigned int scifa4_clk_1_mux[] = {
2524 SCIFA4_SCK_PORT205_MARK,
2525};
2526/* - SCIFA5 ----------------------------------------------------------------- */
2527static const unsigned int scifa5_data_0_pins[] = {
2528 /* RXD, TXD */
2529 10, 20,
2530};
2531static const unsigned int scifa5_data_0_mux[] = {
2532 SCIFA5_RXD_PORT10_MARK, SCIFA5_TXD_PORT20_MARK,
2533};
2534static const unsigned int scifa5_data_1_pins[] = {
2535 /* RXD, TXD */
2536 207, 208,
2537};
2538static const unsigned int scifa5_data_1_mux[] = {
2539 SCIFA5_RXD_PORT207_MARK, SCIFA5_TXD_PORT208_MARK,
2540};
2541static const unsigned int scifa5_data_2_pins[] = {
2542 /* RXD, TXD */
2543 92, 91,
2544};
2545static const unsigned int scifa5_data_2_mux[] = {
2546 SCIFA5_RXD_PORT92_MARK, SCIFA5_TXD_PORT91_MARK,
2547};
2548static const unsigned int scifa5_clk_0_pins[] = {
2549 /* SCK */
2550 23,
2551};
2552static const unsigned int scifa5_clk_0_mux[] = {
2553 SCIFA5_SCK_PORT23_MARK,
2554};
2555static const unsigned int scifa5_clk_1_pins[] = {
2556 /* SCK */
2557 206,
2558};
2559static const unsigned int scifa5_clk_1_mux[] = {
2560 SCIFA5_SCK_PORT206_MARK,
2561};
2562/* - SCIFA6 ----------------------------------------------------------------- */
2563static const unsigned int scifa6_data_pins[] = {
2564 /* RXD, TXD */
2565 25, 26,
2566};
2567static const unsigned int scifa6_data_mux[] = {
2568 SCIFA6_RXD_MARK, SCIFA6_TXD_MARK,
2569};
2570static const unsigned int scifa6_clk_pins[] = {
2571 /* SCK */
2572 24,
2573};
2574static const unsigned int scifa6_clk_mux[] = {
2575 SCIFA6_SCK_MARK,
2576};
2577/* - SCIFA7 ----------------------------------------------------------------- */
2578static const unsigned int scifa7_data_pins[] = {
2579 /* RXD, TXD */
2580 0, 1,
2581};
2582static const unsigned int scifa7_data_mux[] = {
2583 SCIFA7_RXD_MARK, SCIFA7_TXD_MARK,
2584};
2585/* - SCIFB ------------------------------------------------------------------ */
2586static const unsigned int scifb_data_0_pins[] = {
2587 /* RXD, TXD */
2588 191, 192,
2589};
2590static const unsigned int scifb_data_0_mux[] = {
2591 SCIFB_RXD_PORT191_MARK, SCIFB_TXD_PORT192_MARK,
2592};
2593static const unsigned int scifb_clk_0_pins[] = {
2594 /* SCK */
2595 190,
2596};
2597static const unsigned int scifb_clk_0_mux[] = {
2598 SCIFB_SCK_PORT190_MARK,
2599};
2600static const unsigned int scifb_ctrl_0_pins[] = {
2601 /* RTS, CTS */
2602 186, 187,
2603};
2604static const unsigned int scifb_ctrl_0_mux[] = {
2605 SCIFB_RTS_PORT186_MARK, SCIFB_CTS_PORT187_MARK,
2606};
2607static const unsigned int scifb_data_1_pins[] = {
2608 /* RXD, TXD */
2609 3, 4,
2610};
2611static const unsigned int scifb_data_1_mux[] = {
2612 SCIFB_RXD_PORT3_MARK, SCIFB_TXD_PORT4_MARK,
2613};
2614static const unsigned int scifb_clk_1_pins[] = {
2615 /* SCK */
2616 2,
2617};
2618static const unsigned int scifb_clk_1_mux[] = {
2619 SCIFB_SCK_PORT2_MARK,
2620};
2621static const unsigned int scifb_ctrl_1_pins[] = {
2622 /* RTS, CTS */
2623 172, 173,
2624};
2625static const unsigned int scifb_ctrl_1_mux[] = {
2626 SCIFB_RTS_PORT172_MARK, SCIFB_CTS_PORT173_MARK,
2627};
Guennadi Liakhovetski8b2810b2013-01-23 17:37:44 +0100[diff] [blame]2628/* - SDHI0 ------------------------------------------------------------------ */
2629static const unsigned int sdhi0_data1_pins[] = {
2630 /* D0 */
2631 77,
2632};
2633static const unsigned int sdhi0_data1_mux[] = {
2634 SDHI0_D0_MARK,
2635};
2636static const unsigned int sdhi0_data4_pins[] = {
2637 /* D[0:3] */
2638 77, 78, 79, 80,
2639};
2640static const unsigned int sdhi0_data4_mux[] = {
2641 SDHI0_D0_MARK, SDHI0_D1_MARK, SDHI0_D2_MARK, SDHI0_D3_MARK,
2642};
2643static const unsigned int sdhi0_ctrl_pins[] = {
2644 /* CMD, CLK */
2645 76, 82,
2646};
2647static const unsigned int sdhi0_ctrl_mux[] = {
2648 SDHI0_CMD_MARK, SDHI0_CLK_MARK,
2649};
2650static const unsigned int sdhi0_cd_pins[] = {
2651 /* CD */
2652 81,
2653};
2654static const unsigned int sdhi0_cd_mux[] = {
2655 SDHI0_CD_MARK,
2656};
2657static const unsigned int sdhi0_wp_pins[] = {
2658 /* WP */
2659 83,
2660};
2661static const unsigned int sdhi0_wp_mux[] = {
2662 SDHI0_WP_MARK,
2663};
2664/* - SDHI1 ------------------------------------------------------------------ */
2665static const unsigned int sdhi1_data1_pins[] = {
2666 /* D0 */
2667 68,
2668};
2669static const unsigned int sdhi1_data1_mux[] = {
2670 SDHI1_D0_MARK,
2671};
2672static const unsigned int sdhi1_data4_pins[] = {
2673 /* D[0:3] */
2674 68, 69, 70, 71,
2675};
2676static const unsigned int sdhi1_data4_mux[] = {
2677 SDHI1_D0_MARK, SDHI1_D1_MARK, SDHI1_D2_MARK, SDHI1_D3_MARK,
2678};
2679static const unsigned int sdhi1_ctrl_pins[] = {
2680 /* CMD, CLK */
2681 67, 66,
2682};
2683static const unsigned int sdhi1_ctrl_mux[] = {
2684 SDHI1_CMD_MARK, SDHI1_CLK_MARK,
2685};
2686static const unsigned int sdhi1_cd_pins[] = {
2687 /* CD */
2688 72,
2689};
2690static const unsigned int sdhi1_cd_mux[] = {
2691 SDHI1_CD_MARK,
2692};
2693static const unsigned int sdhi1_wp_pins[] = {
2694 /* WP */
2695 73,
2696};
2697static const unsigned int sdhi1_wp_mux[] = {
2698 SDHI1_WP_MARK,
2699};
2700/* - SDHI2 ------------------------------------------------------------------ */
2701static const unsigned int sdhi2_data1_pins[] = {
2702 /* D0 */
2703 205,
2704};
2705static const unsigned int sdhi2_data1_mux[] = {
2706 SDHI2_D0_MARK,
2707};
2708static const unsigned int sdhi2_data4_pins[] = {
2709 /* D[0:3] */
2710 205, 206, 207, 208,
2711};
2712static const unsigned int sdhi2_data4_mux[] = {
2713 SDHI2_D0_MARK, SDHI2_D1_MARK, SDHI2_D2_MARK, SDHI2_D3_MARK,
2714};
2715static const unsigned int sdhi2_ctrl_pins[] = {
2716 /* CMD, CLK */
2717 204, 203,
2718};
2719static const unsigned int sdhi2_ctrl_mux[] = {
2720 SDHI2_CMD_MARK, SDHI2_CLK_MARK,
2721};
2722static const unsigned int sdhi2_cd_0_pins[] = {
2723 /* CD */
2724 202,
2725};
2726static const unsigned int sdhi2_cd_0_mux[] = {
2727 SDHI2_CD_PORT202_MARK,
2728};
2729static const unsigned int sdhi2_wp_0_pins[] = {
2730 /* WP */
2731 177,
2732};
2733static const unsigned int sdhi2_wp_0_mux[] = {
2734 SDHI2_WP_PORT177_MARK,
2735};
2736static const unsigned int sdhi2_cd_1_pins[] = {
2737 /* CD */
2738 24,
2739};
2740static const unsigned int sdhi2_cd_1_mux[] = {
2741 SDHI2_CD_PORT24_MARK,
2742};
2743static const unsigned int sdhi2_wp_1_pins[] = {
2744 /* WP */
2745 25,
2746};
2747static const unsigned int sdhi2_wp_1_mux[] = {
2748 SDHI2_WP_PORT25_MARK,
2749};
Laurent Pinchart06c7dd82013-01-03 13:07:05 +0100[diff] [blame]2750
2751static const struct sh_pfc_pin_group pinmux_groups[] = {
Laurent Pinchartb7099c42013-04-18 01:04:30 +0200[diff] [blame]2752 SH_PFC_PIN_GROUP(bsc_data8),
2753 SH_PFC_PIN_GROUP(bsc_data16),
2754 SH_PFC_PIN_GROUP(bsc_data32),
2755 SH_PFC_PIN_GROUP(bsc_cs0),
2756 SH_PFC_PIN_GROUP(bsc_cs2),
2757 SH_PFC_PIN_GROUP(bsc_cs4),
2758 SH_PFC_PIN_GROUP(bsc_cs5a_0),
2759 SH_PFC_PIN_GROUP(bsc_cs5a_1),
2760 SH_PFC_PIN_GROUP(bsc_cs5b),
2761 SH_PFC_PIN_GROUP(bsc_cs6a),
2762 SH_PFC_PIN_GROUP(bsc_rd_we8),
2763 SH_PFC_PIN_GROUP(bsc_rd_we16),
2764 SH_PFC_PIN_GROUP(bsc_rd_we32),
2765 SH_PFC_PIN_GROUP(bsc_bs),
2766 SH_PFC_PIN_GROUP(bsc_rdwr),
Laurent Pinchart0ec939b2013-04-18 01:04:30 +0200[diff] [blame]2767 SH_PFC_PIN_GROUP(ceu0_data_0_7),
2768 SH_PFC_PIN_GROUP(ceu0_data_8_15_0),
2769 SH_PFC_PIN_GROUP(ceu0_data_8_15_1),
2770 SH_PFC_PIN_GROUP(ceu0_clk_0),
2771 SH_PFC_PIN_GROUP(ceu0_clk_1),
2772 SH_PFC_PIN_GROUP(ceu0_clk_2),
2773 SH_PFC_PIN_GROUP(ceu0_sync),
2774 SH_PFC_PIN_GROUP(ceu0_field),
2775 SH_PFC_PIN_GROUP(ceu1_data),
2776 SH_PFC_PIN_GROUP(ceu1_clk),
2777 SH_PFC_PIN_GROUP(ceu1_sync),
2778 SH_PFC_PIN_GROUP(ceu1_field),
Laurent Pinchart909dd952013-04-18 01:04:30 +0200[diff] [blame]2779 SH_PFC_PIN_GROUP(fsia_mclk_in),
2780 SH_PFC_PIN_GROUP(fsia_mclk_out),
2781 SH_PFC_PIN_GROUP(fsia_sclk_in),
2782 SH_PFC_PIN_GROUP(fsia_sclk_out),
2783 SH_PFC_PIN_GROUP(fsia_data_in_0),
2784 SH_PFC_PIN_GROUP(fsia_data_in_1),
2785 SH_PFC_PIN_GROUP(fsia_data_out_0),
2786 SH_PFC_PIN_GROUP(fsia_data_out_1),
2787 SH_PFC_PIN_GROUP(fsia_data_out_2),
2788 SH_PFC_PIN_GROUP(fsia_spdif_0),
2789 SH_PFC_PIN_GROUP(fsia_spdif_1),
2790 SH_PFC_PIN_GROUP(fsib_mclk_in),
Laurent Pinchartbae11d32013-04-18 01:04:30 +0200[diff] [blame]2791 SH_PFC_PIN_GROUP(gether_rmii),
2792 SH_PFC_PIN_GROUP(gether_mii),
2793 SH_PFC_PIN_GROUP(gether_gmii),
2794 SH_PFC_PIN_GROUP(gether_int),
2795 SH_PFC_PIN_GROUP(gether_link),
2796 SH_PFC_PIN_GROUP(gether_wol),
Laurent Pincharta37d6062013-04-18 01:04:30 +0200[diff] [blame]2797 SH_PFC_PIN_GROUP(hdmi),
Bastian Hecht09bbc1f2013-04-09 10:48:50 +0000[diff] [blame]2798 SH_PFC_PIN_GROUP(intc_irq0_0),
2799 SH_PFC_PIN_GROUP(intc_irq0_1),
2800 SH_PFC_PIN_GROUP(intc_irq1),
2801 SH_PFC_PIN_GROUP(intc_irq2_0),
2802 SH_PFC_PIN_GROUP(intc_irq2_1),
2803 SH_PFC_PIN_GROUP(intc_irq3_0),
2804 SH_PFC_PIN_GROUP(intc_irq3_1),
2805 SH_PFC_PIN_GROUP(intc_irq4_0),
2806 SH_PFC_PIN_GROUP(intc_irq4_1),
2807 SH_PFC_PIN_GROUP(intc_irq5_0),
2808 SH_PFC_PIN_GROUP(intc_irq5_1),
2809 SH_PFC_PIN_GROUP(intc_irq6_0),
2810 SH_PFC_PIN_GROUP(intc_irq6_1),
2811 SH_PFC_PIN_GROUP(intc_irq7_0),
2812 SH_PFC_PIN_GROUP(intc_irq7_1),
2813 SH_PFC_PIN_GROUP(intc_irq8),
2814 SH_PFC_PIN_GROUP(intc_irq9_0),
2815 SH_PFC_PIN_GROUP(intc_irq9_1),
2816 SH_PFC_PIN_GROUP(intc_irq10),
2817 SH_PFC_PIN_GROUP(intc_irq11),
2818 SH_PFC_PIN_GROUP(intc_irq12_0),
2819 SH_PFC_PIN_GROUP(intc_irq12_1),
2820 SH_PFC_PIN_GROUP(intc_irq13_0),
2821 SH_PFC_PIN_GROUP(intc_irq13_1),
2822 SH_PFC_PIN_GROUP(intc_irq14_0),
2823 SH_PFC_PIN_GROUP(intc_irq14_1),
2824 SH_PFC_PIN_GROUP(intc_irq15_0),
2825 SH_PFC_PIN_GROUP(intc_irq15_1),
2826 SH_PFC_PIN_GROUP(intc_irq16_0),
2827 SH_PFC_PIN_GROUP(intc_irq16_1),
2828 SH_PFC_PIN_GROUP(intc_irq17),
2829 SH_PFC_PIN_GROUP(intc_irq18),
2830 SH_PFC_PIN_GROUP(intc_irq19),
2831 SH_PFC_PIN_GROUP(intc_irq20),
2832 SH_PFC_PIN_GROUP(intc_irq21),
2833 SH_PFC_PIN_GROUP(intc_irq22),
2834 SH_PFC_PIN_GROUP(intc_irq23),
2835 SH_PFC_PIN_GROUP(intc_irq24),
2836 SH_PFC_PIN_GROUP(intc_irq25),
2837 SH_PFC_PIN_GROUP(intc_irq26_0),
2838 SH_PFC_PIN_GROUP(intc_irq26_1),
2839 SH_PFC_PIN_GROUP(intc_irq27_0),
2840 SH_PFC_PIN_GROUP(intc_irq27_1),
2841 SH_PFC_PIN_GROUP(intc_irq28_0),
2842 SH_PFC_PIN_GROUP(intc_irq28_1),
2843 SH_PFC_PIN_GROUP(intc_irq29_0),
2844 SH_PFC_PIN_GROUP(intc_irq29_1),
2845 SH_PFC_PIN_GROUP(intc_irq30_0),
2846 SH_PFC_PIN_GROUP(intc_irq30_1),
2847 SH_PFC_PIN_GROUP(intc_irq31_0),
2848 SH_PFC_PIN_GROUP(intc_irq31_1),
Laurent Pinchart06c7dd82013-01-03 13:07:05 +0100[diff] [blame]2849 SH_PFC_PIN_GROUP(lcd0_data8),
2850 SH_PFC_PIN_GROUP(lcd0_data9),
2851 SH_PFC_PIN_GROUP(lcd0_data12),
2852 SH_PFC_PIN_GROUP(lcd0_data16),
2853 SH_PFC_PIN_GROUP(lcd0_data18),
2854 SH_PFC_PIN_GROUP(lcd0_data24_0),
2855 SH_PFC_PIN_GROUP(lcd0_data24_1),
2856 SH_PFC_PIN_GROUP(lcd0_display),
2857 SH_PFC_PIN_GROUP(lcd0_lclk_0),
2858 SH_PFC_PIN_GROUP(lcd0_lclk_1),
2859 SH_PFC_PIN_GROUP(lcd0_sync),
2860 SH_PFC_PIN_GROUP(lcd0_sys),
2861 SH_PFC_PIN_GROUP(lcd1_data8),
2862 SH_PFC_PIN_GROUP(lcd1_data9),
2863 SH_PFC_PIN_GROUP(lcd1_data12),
2864 SH_PFC_PIN_GROUP(lcd1_data16),
2865 SH_PFC_PIN_GROUP(lcd1_data18),
2866 SH_PFC_PIN_GROUP(lcd1_data24),
2867 SH_PFC_PIN_GROUP(lcd1_display),
2868 SH_PFC_PIN_GROUP(lcd1_lclk),
2869 SH_PFC_PIN_GROUP(lcd1_sync),
2870 SH_PFC_PIN_GROUP(lcd1_sys),
Guennadi Liakhovetski8b2810b2013-01-23 17:37:44 +0100[diff] [blame]2871 SH_PFC_PIN_GROUP(mmc0_data1_0),
2872 SH_PFC_PIN_GROUP(mmc0_data4_0),
2873 SH_PFC_PIN_GROUP(mmc0_data8_0),
2874 SH_PFC_PIN_GROUP(mmc0_ctrl_0),
2875 SH_PFC_PIN_GROUP(mmc0_data1_1),
2876 SH_PFC_PIN_GROUP(mmc0_data4_1),
2877 SH_PFC_PIN_GROUP(mmc0_data8_1),
2878 SH_PFC_PIN_GROUP(mmc0_ctrl_1),
Laurent Pinchartcdd2c762013-04-18 01:04:30 +0200[diff] [blame]2879 SH_PFC_PIN_GROUP(scifa0_data),
2880 SH_PFC_PIN_GROUP(scifa0_clk),
2881 SH_PFC_PIN_GROUP(scifa0_ctrl),
Bastian Hecht8fbfdbb2013-04-17 10:34:01 +0000[diff] [blame]2882 SH_PFC_PIN_GROUP(scifa1_data),
Laurent Pinchartcdd2c762013-04-18 01:04:30 +0200[diff] [blame]2883 SH_PFC_PIN_GROUP(scifa1_clk),
2884 SH_PFC_PIN_GROUP(scifa1_ctrl),
2885 SH_PFC_PIN_GROUP(scifa2_data),
2886 SH_PFC_PIN_GROUP(scifa2_clk_0),
2887 SH_PFC_PIN_GROUP(scifa2_clk_1),
2888 SH_PFC_PIN_GROUP(scifa2_ctrl),
2889 SH_PFC_PIN_GROUP(scifa3_data_0),
2890 SH_PFC_PIN_GROUP(scifa3_clk_0),
2891 SH_PFC_PIN_GROUP(scifa3_ctrl_0),
2892 SH_PFC_PIN_GROUP(scifa3_data_1),
2893 SH_PFC_PIN_GROUP(scifa3_clk_1),
2894 SH_PFC_PIN_GROUP(scifa3_ctrl_1),
2895 SH_PFC_PIN_GROUP(scifa4_data_0),
2896 SH_PFC_PIN_GROUP(scifa4_data_1),
2897 SH_PFC_PIN_GROUP(scifa4_data_2),
2898 SH_PFC_PIN_GROUP(scifa4_clk_0),
2899 SH_PFC_PIN_GROUP(scifa4_clk_1),
2900 SH_PFC_PIN_GROUP(scifa5_data_0),
2901 SH_PFC_PIN_GROUP(scifa5_data_1),
2902 SH_PFC_PIN_GROUP(scifa5_data_2),
2903 SH_PFC_PIN_GROUP(scifa5_clk_0),
2904 SH_PFC_PIN_GROUP(scifa5_clk_1),
2905 SH_PFC_PIN_GROUP(scifa6_data),
2906 SH_PFC_PIN_GROUP(scifa6_clk),
2907 SH_PFC_PIN_GROUP(scifa7_data),
2908 SH_PFC_PIN_GROUP(scifb_data_0),
2909 SH_PFC_PIN_GROUP(scifb_clk_0),
2910 SH_PFC_PIN_GROUP(scifb_ctrl_0),
2911 SH_PFC_PIN_GROUP(scifb_data_1),
2912 SH_PFC_PIN_GROUP(scifb_clk_1),
2913 SH_PFC_PIN_GROUP(scifb_ctrl_1),
Guennadi Liakhovetski8b2810b2013-01-23 17:37:44 +0100[diff] [blame]2914 SH_PFC_PIN_GROUP(sdhi0_data1),
2915 SH_PFC_PIN_GROUP(sdhi0_data4),
2916 SH_PFC_PIN_GROUP(sdhi0_ctrl),
2917 SH_PFC_PIN_GROUP(sdhi0_cd),
2918 SH_PFC_PIN_GROUP(sdhi0_wp),
2919 SH_PFC_PIN_GROUP(sdhi1_data1),
2920 SH_PFC_PIN_GROUP(sdhi1_data4),
2921 SH_PFC_PIN_GROUP(sdhi1_ctrl),
2922 SH_PFC_PIN_GROUP(sdhi1_cd),
2923 SH_PFC_PIN_GROUP(sdhi1_wp),
2924 SH_PFC_PIN_GROUP(sdhi2_data1),
2925 SH_PFC_PIN_GROUP(sdhi2_data4),
2926 SH_PFC_PIN_GROUP(sdhi2_ctrl),
2927 SH_PFC_PIN_GROUP(sdhi2_cd_0),
2928 SH_PFC_PIN_GROUP(sdhi2_wp_0),
2929 SH_PFC_PIN_GROUP(sdhi2_cd_1),
2930 SH_PFC_PIN_GROUP(sdhi2_wp_1),
Laurent Pinchart06c7dd82013-01-03 13:07:05 +0100[diff] [blame]2931};
2932
Laurent Pinchartb7099c42013-04-18 01:04:30 +0200[diff] [blame]2933static const char * const bsc_groups[] = {
2934 "bsc_data8",
2935 "bsc_data16",
2936 "bsc_data32",
2937 "bsc_cs0",
2938 "bsc_cs2",
2939 "bsc_cs4",
2940 "bsc_cs5a_0",
2941 "bsc_cs5a_1",
2942 "bsc_cs5b",
2943 "bsc_cs6a",
2944 "bsc_rd_we8",
2945 "bsc_rd_we16",
2946 "bsc_rd_we32",
2947 "bsc_bs",
2948 "bsc_rdwr",
2949};
2950
Laurent Pinchart0ec939b2013-04-18 01:04:30 +0200[diff] [blame]2951static const char * const ceu0_groups[] = {
2952 "ceu0_data_0_7",
2953 "ceu0_data_8_15_0",
2954 "ceu0_data_8_15_1",
2955 "ceu0_clk_0",
2956 "ceu0_clk_1",
2957 "ceu0_clk_2",
2958 "ceu0_sync",
2959 "ceu0_field",
2960};
2961
2962static const char * const ceu1_groups[] = {
2963 "ceu1_data",
2964 "ceu1_clk",
2965 "ceu1_sync",
2966 "ceu1_field",
2967};
2968
Laurent Pinchart909dd952013-04-18 01:04:30 +0200[diff] [blame]2969static const char * const fsia_groups[] = {
2970 "fsia_mclk_in",
2971 "fsia_mclk_out",
2972 "fsia_sclk_in",
2973 "fsia_sclk_out",
2974 "fsia_data_in_0",
2975 "fsia_data_in_1",
2976 "fsia_data_out_0",
2977 "fsia_data_out_1",
2978 "fsia_data_out_2",
2979 "fsia_spdif_0",
2980 "fsia_spdif_1",
2981};
2982
2983static const char * const fsib_groups[] = {
2984 "fsib_mclk_in",
2985};
2986
Laurent Pinchartbae11d32013-04-18 01:04:30 +0200[diff] [blame]2987static const char * const gether_groups[] = {
2988 "gether_rmii",
2989 "gether_mii",
2990 "gether_gmii",
2991 "gether_int",
2992 "gether_link",
2993 "gether_wol",
2994};
2995
Laurent Pincharta37d6062013-04-18 01:04:30 +0200[diff] [blame]2996static const char * const hdmi_groups[] = {
2997 "hdmi",
2998};
2999
Bastian Hecht09bbc1f2013-04-09 10:48:50 +0000[diff] [blame]3000static const char * const intc_groups[] = {
3001 "intc_irq0_0",
3002 "intc_irq0_1",
3003 "intc_irq1",
3004 "intc_irq2_0",
3005 "intc_irq2_1",
3006 "intc_irq3_0",
3007 "intc_irq3_1",
3008 "intc_irq4_0",
3009 "intc_irq4_1",
3010 "intc_irq5_0",
3011 "intc_irq5_1",
3012 "intc_irq6_0",
3013 "intc_irq6_1",
3014 "intc_irq7_0",
3015 "intc_irq7_1",
3016 "intc_irq8",
3017 "intc_irq9_0",
3018 "intc_irq9_1",
3019 "intc_irq10",
3020 "intc_irq11",
3021 "intc_irq12_0",
3022 "intc_irq12_1",
3023 "intc_irq13_0",
3024 "intc_irq13_1",
3025 "intc_irq14_0",
3026 "intc_irq14_1",
3027 "intc_irq15_0",
3028 "intc_irq15_1",
3029 "intc_irq16_0",
3030 "intc_irq16_1",
3031 "intc_irq17",
3032 "intc_irq18",
3033 "intc_irq19",
3034 "intc_irq20",
3035 "intc_irq21",
3036 "intc_irq22",
3037 "intc_irq23",
3038 "intc_irq24",
3039 "intc_irq25",
3040 "intc_irq26_0",
3041 "intc_irq26_1",
3042 "intc_irq27_0",
3043 "intc_irq27_1",
3044 "intc_irq28_0",
3045 "intc_irq28_1",
3046 "intc_irq29_0",
3047 "intc_irq29_1",
3048 "intc_irq30_0",
3049 "intc_irq30_1",
3050 "intc_irq31_0",
3051 "intc_irq31_1",
3052};
3053
Laurent Pinchart06c7dd82013-01-03 13:07:05 +0100[diff] [blame]3054static const char * const lcd0_groups[] = {
3055 "lcd0_data8",
3056 "lcd0_data9",
3057 "lcd0_data12",
3058 "lcd0_data16",
3059 "lcd0_data18",
3060 "lcd0_data24_0",
3061 "lcd0_data24_1",
3062 "lcd0_display",
3063 "lcd0_lclk_0",
3064 "lcd0_lclk_1",
3065 "lcd0_sync",
3066 "lcd0_sys",
3067};
3068
3069static const char * const lcd1_groups[] = {
3070 "lcd1_data8",
3071 "lcd1_data9",
3072 "lcd1_data12",
3073 "lcd1_data16",
3074 "lcd1_data18",
3075 "lcd1_data24",
3076 "lcd1_display",
3077 "lcd1_lclk",
3078 "lcd1_sync",
3079 "lcd1_sys",
3080};
3081
Guennadi Liakhovetski8b2810b2013-01-23 17:37:44 +0100[diff] [blame]3082static const char * const mmc0_groups[] = {
3083 "mmc0_data1_0",
3084 "mmc0_data4_0",
3085 "mmc0_data8_0",
3086 "mmc0_ctrl_0",
3087 "mmc0_data1_1",
3088 "mmc0_data4_1",
3089 "mmc0_data8_1",
3090 "mmc0_ctrl_1",
3091};
3092
Laurent Pinchartcdd2c762013-04-18 01:04:30 +0200[diff] [blame]3093static const char * const scifa0_groups[] = {
3094 "scifa0_data",
3095 "scifa0_clk",
3096 "scifa0_ctrl",
3097};
3098
Bastian Hecht8fbfdbb2013-04-17 10:34:01 +0000[diff] [blame]3099static const char * const scifa1_groups[] = {
3100 "scifa1_data",
Laurent Pinchartcdd2c762013-04-18 01:04:30 +0200[diff] [blame]3101 "scifa1_clk",
3102 "scifa1_ctrl",
3103};
3104
3105static const char * const scifa2_groups[] = {
3106 "scifa2_data",
3107 "scifa2_clk_0",
3108 "scifa2_clk_1",
3109 "scifa2_ctrl",
3110};
3111
3112static const char * const scifa3_groups[] = {
3113 "scifa3_data_0",
3114 "scifa3_clk_0",
3115 "scifa3_ctrl_0",
3116 "scifa3_data_1",
3117 "scifa3_clk_1",
3118 "scifa3_ctrl_1",
3119};
3120
3121static const char * const scifa4_groups[] = {
3122 "scifa4_data_0",
3123 "scifa4_data_1",
3124 "scifa4_data_2",
3125 "scifa4_clk_0",
3126 "scifa4_clk_1",
3127};
3128
3129static const char * const scifa5_groups[] = {
3130 "scifa5_data_0",
3131 "scifa5_data_1",
3132 "scifa5_data_2",
3133 "scifa5_clk_0",
3134 "scifa5_clk_1",
3135};
3136
3137static const char * const scifa6_groups[] = {
3138 "scifa6_data",
3139 "scifa6_clk",
3140};
3141
3142static const char * const scifa7_groups[] = {
3143 "scifa7_data",
3144};
3145
3146static const char * const scifb_groups[] = {
3147 "scifb_data_0",
3148 "scifb_clk_0",
3149 "scifb_ctrl_0",
3150 "scifb_data_1",
3151 "scifb_clk_1",
3152 "scifb_ctrl_1",
Bastian Hecht8fbfdbb2013-04-17 10:34:01 +0000[diff] [blame]3153};
3154
Guennadi Liakhovetski8b2810b2013-01-23 17:37:44 +0100[diff] [blame]3155static const char * const sdhi0_groups[] = {
3156 "sdhi0_data1",
3157 "sdhi0_data4",
3158 "sdhi0_ctrl",
3159 "sdhi0_cd",
3160 "sdhi0_wp",
3161};
3162
3163static const char * const sdhi1_groups[] = {
3164 "sdhi1_data1",
3165 "sdhi1_data4",
3166 "sdhi1_ctrl",
3167 "sdhi1_cd",
3168 "sdhi1_wp",
3169};
3170
3171static const char * const sdhi2_groups[] = {
3172 "sdhi2_data1",
3173 "sdhi2_data4",
3174 "sdhi2_ctrl",
3175 "sdhi2_cd_0",
3176 "sdhi2_wp_0",
3177 "sdhi2_cd_1",
3178 "sdhi2_wp_1",
3179};
3180
Laurent Pinchart06c7dd82013-01-03 13:07:05 +0100[diff] [blame]3181static const struct sh_pfc_function pinmux_functions[] = {
Laurent Pinchartb7099c42013-04-18 01:04:30 +0200[diff] [blame]3182 SH_PFC_FUNCTION(bsc),
Laurent Pinchart0ec939b2013-04-18 01:04:30 +0200[diff] [blame]3183 SH_PFC_FUNCTION(ceu0),
3184 SH_PFC_FUNCTION(ceu1),
Laurent Pinchart909dd952013-04-18 01:04:30 +0200[diff] [blame]3185 SH_PFC_FUNCTION(fsia),
3186 SH_PFC_FUNCTION(fsib),
Laurent Pinchartbae11d32013-04-18 01:04:30 +0200[diff] [blame]3187 SH_PFC_FUNCTION(gether),
Laurent Pincharta37d6062013-04-18 01:04:30 +0200[diff] [blame]3188 SH_PFC_FUNCTION(hdmi),
Laurent Pinchartd0316962013-04-18 10:54:18 +0200[diff] [blame]3189 SH_PFC_FUNCTION(intc),
Laurent Pinchart06c7dd82013-01-03 13:07:05 +0100[diff] [blame]3190 SH_PFC_FUNCTION(lcd0),
3191 SH_PFC_FUNCTION(lcd1),
Guennadi Liakhovetski8b2810b2013-01-23 17:37:44 +0100[diff] [blame]3192 SH_PFC_FUNCTION(mmc0),
Laurent Pinchartcdd2c762013-04-18 01:04:30 +0200[diff] [blame]3193 SH_PFC_FUNCTION(scifa0),
Bastian Hecht8fbfdbb2013-04-17 10:34:01 +0000[diff] [blame]3194 SH_PFC_FUNCTION(scifa1),
Laurent Pinchartcdd2c762013-04-18 01:04:30 +0200[diff] [blame]3195 SH_PFC_FUNCTION(scifa2),
3196 SH_PFC_FUNCTION(scifa3),
3197 SH_PFC_FUNCTION(scifa4),
3198 SH_PFC_FUNCTION(scifa5),
3199 SH_PFC_FUNCTION(scifa6),
3200 SH_PFC_FUNCTION(scifa7),
3201 SH_PFC_FUNCTION(scifb),
Guennadi Liakhovetski8b2810b2013-01-23 17:37:44 +0100[diff] [blame]3202 SH_PFC_FUNCTION(sdhi0),
3203 SH_PFC_FUNCTION(sdhi1),
3204 SH_PFC_FUNCTION(sdhi2),
Laurent Pinchart06c7dd82013-01-03 13:07:05 +0100[diff] [blame]3205};
3206
Laurent Pinchartcd3c1be2013-02-16 18:47:05 +0100[diff] [blame]3207static const struct pinmux_cfg_reg pinmux_config_regs[] = {
Laurent Pinchartd5b15212012-12-15 23:51:21 +0100[diff] [blame]3208 PORTCR(0, 0xe6050000), /* PORT0CR */
3209 PORTCR(1, 0xe6050001), /* PORT1CR */
3210 PORTCR(2, 0xe6050002), /* PORT2CR */
3211 PORTCR(3, 0xe6050003), /* PORT3CR */
3212 PORTCR(4, 0xe6050004), /* PORT4CR */
3213 PORTCR(5, 0xe6050005), /* PORT5CR */
3214 PORTCR(6, 0xe6050006), /* PORT6CR */
3215 PORTCR(7, 0xe6050007), /* PORT7CR */
3216 PORTCR(8, 0xe6050008), /* PORT8CR */
3217 PORTCR(9, 0xe6050009), /* PORT9CR */
3218 PORTCR(10, 0xe605000a), /* PORT10CR */
3219 PORTCR(11, 0xe605000b), /* PORT11CR */
3220 PORTCR(12, 0xe605000c), /* PORT12CR */
3221 PORTCR(13, 0xe605000d), /* PORT13CR */
3222 PORTCR(14, 0xe605000e), /* PORT14CR */
3223 PORTCR(15, 0xe605000f), /* PORT15CR */
3224 PORTCR(16, 0xe6050010), /* PORT16CR */
3225 PORTCR(17, 0xe6050011), /* PORT17CR */
3226 PORTCR(18, 0xe6050012), /* PORT18CR */
3227 PORTCR(19, 0xe6050013), /* PORT19CR */
3228 PORTCR(20, 0xe6050014), /* PORT20CR */
3229 PORTCR(21, 0xe6050015), /* PORT21CR */
3230 PORTCR(22, 0xe6050016), /* PORT22CR */
3231 PORTCR(23, 0xe6050017), /* PORT23CR */
3232 PORTCR(24, 0xe6050018), /* PORT24CR */
3233 PORTCR(25, 0xe6050019), /* PORT25CR */
3234 PORTCR(26, 0xe605001a), /* PORT26CR */
3235 PORTCR(27, 0xe605001b), /* PORT27CR */
3236 PORTCR(28, 0xe605001c), /* PORT28CR */
3237 PORTCR(29, 0xe605001d), /* PORT29CR */
3238 PORTCR(30, 0xe605001e), /* PORT30CR */
3239 PORTCR(31, 0xe605001f), /* PORT31CR */
3240 PORTCR(32, 0xe6050020), /* PORT32CR */
3241 PORTCR(33, 0xe6050021), /* PORT33CR */
3242 PORTCR(34, 0xe6050022), /* PORT34CR */
3243 PORTCR(35, 0xe6050023), /* PORT35CR */
3244 PORTCR(36, 0xe6050024), /* PORT36CR */
3245 PORTCR(37, 0xe6050025), /* PORT37CR */
3246 PORTCR(38, 0xe6050026), /* PORT38CR */
3247 PORTCR(39, 0xe6050027), /* PORT39CR */
3248 PORTCR(40, 0xe6050028), /* PORT40CR */
3249 PORTCR(41, 0xe6050029), /* PORT41CR */
3250 PORTCR(42, 0xe605002a), /* PORT42CR */
3251 PORTCR(43, 0xe605002b), /* PORT43CR */
3252 PORTCR(44, 0xe605002c), /* PORT44CR */
3253 PORTCR(45, 0xe605002d), /* PORT45CR */
3254 PORTCR(46, 0xe605002e), /* PORT46CR */
3255 PORTCR(47, 0xe605002f), /* PORT47CR */
3256 PORTCR(48, 0xe6050030), /* PORT48CR */
3257 PORTCR(49, 0xe6050031), /* PORT49CR */
3258 PORTCR(50, 0xe6050032), /* PORT50CR */
3259 PORTCR(51, 0xe6050033), /* PORT51CR */
3260 PORTCR(52, 0xe6050034), /* PORT52CR */
3261 PORTCR(53, 0xe6050035), /* PORT53CR */
3262 PORTCR(54, 0xe6050036), /* PORT54CR */
3263 PORTCR(55, 0xe6050037), /* PORT55CR */
3264 PORTCR(56, 0xe6050038), /* PORT56CR */
3265 PORTCR(57, 0xe6050039), /* PORT57CR */
3266 PORTCR(58, 0xe605003a), /* PORT58CR */
3267 PORTCR(59, 0xe605003b), /* PORT59CR */
3268 PORTCR(60, 0xe605003c), /* PORT60CR */
3269 PORTCR(61, 0xe605003d), /* PORT61CR */
3270 PORTCR(62, 0xe605003e), /* PORT62CR */
3271 PORTCR(63, 0xe605003f), /* PORT63CR */
3272 PORTCR(64, 0xe6050040), /* PORT64CR */
3273 PORTCR(65, 0xe6050041), /* PORT65CR */
3274 PORTCR(66, 0xe6050042), /* PORT66CR */
3275 PORTCR(67, 0xe6050043), /* PORT67CR */
3276 PORTCR(68, 0xe6050044), /* PORT68CR */
3277 PORTCR(69, 0xe6050045), /* PORT69CR */
3278 PORTCR(70, 0xe6050046), /* PORT70CR */
3279 PORTCR(71, 0xe6050047), /* PORT71CR */
3280 PORTCR(72, 0xe6050048), /* PORT72CR */
3281 PORTCR(73, 0xe6050049), /* PORT73CR */
3282 PORTCR(74, 0xe605004a), /* PORT74CR */
3283 PORTCR(75, 0xe605004b), /* PORT75CR */
3284 PORTCR(76, 0xe605004c), /* PORT76CR */
3285 PORTCR(77, 0xe605004d), /* PORT77CR */
3286 PORTCR(78, 0xe605004e), /* PORT78CR */
3287 PORTCR(79, 0xe605004f), /* PORT79CR */
3288 PORTCR(80, 0xe6050050), /* PORT80CR */
3289 PORTCR(81, 0xe6050051), /* PORT81CR */
3290 PORTCR(82, 0xe6050052), /* PORT82CR */
3291 PORTCR(83, 0xe6050053), /* PORT83CR */
3292
3293 PORTCR(84, 0xe6051054), /* PORT84CR */
3294 PORTCR(85, 0xe6051055), /* PORT85CR */
3295 PORTCR(86, 0xe6051056), /* PORT86CR */
3296 PORTCR(87, 0xe6051057), /* PORT87CR */
3297 PORTCR(88, 0xe6051058), /* PORT88CR */
3298 PORTCR(89, 0xe6051059), /* PORT89CR */
3299 PORTCR(90, 0xe605105a), /* PORT90CR */
3300 PORTCR(91, 0xe605105b), /* PORT91CR */
3301 PORTCR(92, 0xe605105c), /* PORT92CR */
3302 PORTCR(93, 0xe605105d), /* PORT93CR */
3303 PORTCR(94, 0xe605105e), /* PORT94CR */
3304 PORTCR(95, 0xe605105f), /* PORT95CR */
3305 PORTCR(96, 0xe6051060), /* PORT96CR */
3306 PORTCR(97, 0xe6051061), /* PORT97CR */
3307 PORTCR(98, 0xe6051062), /* PORT98CR */
3308 PORTCR(99, 0xe6051063), /* PORT99CR */
3309 PORTCR(100, 0xe6051064), /* PORT100CR */
3310 PORTCR(101, 0xe6051065), /* PORT101CR */
3311 PORTCR(102, 0xe6051066), /* PORT102CR */
3312 PORTCR(103, 0xe6051067), /* PORT103CR */
3313 PORTCR(104, 0xe6051068), /* PORT104CR */
3314 PORTCR(105, 0xe6051069), /* PORT105CR */
3315 PORTCR(106, 0xe605106a), /* PORT106CR */
3316 PORTCR(107, 0xe605106b), /* PORT107CR */
3317 PORTCR(108, 0xe605106c), /* PORT108CR */
3318 PORTCR(109, 0xe605106d), /* PORT109CR */
3319 PORTCR(110, 0xe605106e), /* PORT110CR */
3320 PORTCR(111, 0xe605106f), /* PORT111CR */
3321 PORTCR(112, 0xe6051070), /* PORT112CR */
3322 PORTCR(113, 0xe6051071), /* PORT113CR */
3323 PORTCR(114, 0xe6051072), /* PORT114CR */
3324
3325 PORTCR(115, 0xe6052073), /* PORT115CR */
3326 PORTCR(116, 0xe6052074), /* PORT116CR */
3327 PORTCR(117, 0xe6052075), /* PORT117CR */
3328 PORTCR(118, 0xe6052076), /* PORT118CR */
3329 PORTCR(119, 0xe6052077), /* PORT119CR */
3330 PORTCR(120, 0xe6052078), /* PORT120CR */
3331 PORTCR(121, 0xe6052079), /* PORT121CR */
3332 PORTCR(122, 0xe605207a), /* PORT122CR */
3333 PORTCR(123, 0xe605207b), /* PORT123CR */
3334 PORTCR(124, 0xe605207c), /* PORT124CR */
3335 PORTCR(125, 0xe605207d), /* PORT125CR */
3336 PORTCR(126, 0xe605207e), /* PORT126CR */
3337 PORTCR(127, 0xe605207f), /* PORT127CR */
3338 PORTCR(128, 0xe6052080), /* PORT128CR */
3339 PORTCR(129, 0xe6052081), /* PORT129CR */
3340 PORTCR(130, 0xe6052082), /* PORT130CR */
3341 PORTCR(131, 0xe6052083), /* PORT131CR */
3342 PORTCR(132, 0xe6052084), /* PORT132CR */
3343 PORTCR(133, 0xe6052085), /* PORT133CR */
3344 PORTCR(134, 0xe6052086), /* PORT134CR */
3345 PORTCR(135, 0xe6052087), /* PORT135CR */
3346 PORTCR(136, 0xe6052088), /* PORT136CR */
3347 PORTCR(137, 0xe6052089), /* PORT137CR */
3348 PORTCR(138, 0xe605208a), /* PORT138CR */
3349 PORTCR(139, 0xe605208b), /* PORT139CR */
3350 PORTCR(140, 0xe605208c), /* PORT140CR */
3351 PORTCR(141, 0xe605208d), /* PORT141CR */
3352 PORTCR(142, 0xe605208e), /* PORT142CR */
3353 PORTCR(143, 0xe605208f), /* PORT143CR */
3354 PORTCR(144, 0xe6052090), /* PORT144CR */
3355 PORTCR(145, 0xe6052091), /* PORT145CR */
3356 PORTCR(146, 0xe6052092), /* PORT146CR */
3357 PORTCR(147, 0xe6052093), /* PORT147CR */
3358 PORTCR(148, 0xe6052094), /* PORT148CR */
3359 PORTCR(149, 0xe6052095), /* PORT149CR */
3360 PORTCR(150, 0xe6052096), /* PORT150CR */
3361 PORTCR(151, 0xe6052097), /* PORT151CR */
3362 PORTCR(152, 0xe6052098), /* PORT152CR */
3363 PORTCR(153, 0xe6052099), /* PORT153CR */
3364 PORTCR(154, 0xe605209a), /* PORT154CR */
3365 PORTCR(155, 0xe605209b), /* PORT155CR */
3366 PORTCR(156, 0xe605209c), /* PORT156CR */
3367 PORTCR(157, 0xe605209d), /* PORT157CR */
3368 PORTCR(158, 0xe605209e), /* PORT158CR */
3369 PORTCR(159, 0xe605209f), /* PORT159CR */
3370 PORTCR(160, 0xe60520a0), /* PORT160CR */
3371 PORTCR(161, 0xe60520a1), /* PORT161CR */
3372 PORTCR(162, 0xe60520a2), /* PORT162CR */
3373 PORTCR(163, 0xe60520a3), /* PORT163CR */
3374 PORTCR(164, 0xe60520a4), /* PORT164CR */
3375 PORTCR(165, 0xe60520a5), /* PORT165CR */
3376 PORTCR(166, 0xe60520a6), /* PORT166CR */
3377 PORTCR(167, 0xe60520a7), /* PORT167CR */
3378 PORTCR(168, 0xe60520a8), /* PORT168CR */
3379 PORTCR(169, 0xe60520a9), /* PORT169CR */
3380 PORTCR(170, 0xe60520aa), /* PORT170CR */
3381 PORTCR(171, 0xe60520ab), /* PORT171CR */
3382 PORTCR(172, 0xe60520ac), /* PORT172CR */
3383 PORTCR(173, 0xe60520ad), /* PORT173CR */
3384 PORTCR(174, 0xe60520ae), /* PORT174CR */
3385 PORTCR(175, 0xe60520af), /* PORT175CR */
3386 PORTCR(176, 0xe60520b0), /* PORT176CR */
3387 PORTCR(177, 0xe60520b1), /* PORT177CR */
3388 PORTCR(178, 0xe60520b2), /* PORT178CR */
3389 PORTCR(179, 0xe60520b3), /* PORT179CR */
3390 PORTCR(180, 0xe60520b4), /* PORT180CR */
3391 PORTCR(181, 0xe60520b5), /* PORT181CR */
3392 PORTCR(182, 0xe60520b6), /* PORT182CR */
3393 PORTCR(183, 0xe60520b7), /* PORT183CR */
3394 PORTCR(184, 0xe60520b8), /* PORT184CR */
3395 PORTCR(185, 0xe60520b9), /* PORT185CR */
3396 PORTCR(186, 0xe60520ba), /* PORT186CR */
3397 PORTCR(187, 0xe60520bb), /* PORT187CR */
3398 PORTCR(188, 0xe60520bc), /* PORT188CR */
3399 PORTCR(189, 0xe60520bd), /* PORT189CR */
3400 PORTCR(190, 0xe60520be), /* PORT190CR */
3401 PORTCR(191, 0xe60520bf), /* PORT191CR */
3402 PORTCR(192, 0xe60520c0), /* PORT192CR */
3403 PORTCR(193, 0xe60520c1), /* PORT193CR */
3404 PORTCR(194, 0xe60520c2), /* PORT194CR */
3405 PORTCR(195, 0xe60520c3), /* PORT195CR */
3406 PORTCR(196, 0xe60520c4), /* PORT196CR */
3407 PORTCR(197, 0xe60520c5), /* PORT197CR */
3408 PORTCR(198, 0xe60520c6), /* PORT198CR */
3409 PORTCR(199, 0xe60520c7), /* PORT199CR */
3410 PORTCR(200, 0xe60520c8), /* PORT200CR */
3411 PORTCR(201, 0xe60520c9), /* PORT201CR */
3412 PORTCR(202, 0xe60520ca), /* PORT202CR */
3413 PORTCR(203, 0xe60520cb), /* PORT203CR */
3414 PORTCR(204, 0xe60520cc), /* PORT204CR */
3415 PORTCR(205, 0xe60520cd), /* PORT205CR */
3416 PORTCR(206, 0xe60520ce), /* PORT206CR */
3417 PORTCR(207, 0xe60520cf), /* PORT207CR */
3418 PORTCR(208, 0xe60520d0), /* PORT208CR */
3419 PORTCR(209, 0xe60520d1), /* PORT209CR */
3420
3421 PORTCR(210, 0xe60530d2), /* PORT210CR */
3422 PORTCR(211, 0xe60530d3), /* PORT211CR */
3423
3424 { PINMUX_CFG_REG("MSEL1CR", 0xe605800c, 32, 1) {
3425 MSEL1CR_31_0, MSEL1CR_31_1,
3426 MSEL1CR_30_0, MSEL1CR_30_1,
3427 MSEL1CR_29_0, MSEL1CR_29_1,
3428 MSEL1CR_28_0, MSEL1CR_28_1,
3429 MSEL1CR_27_0, MSEL1CR_27_1,
3430 MSEL1CR_26_0, MSEL1CR_26_1,
3431 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3432 0, 0, 0, 0, 0, 0, 0, 0,
3433 MSEL1CR_16_0, MSEL1CR_16_1,
3434 MSEL1CR_15_0, MSEL1CR_15_1,
3435 MSEL1CR_14_0, MSEL1CR_14_1,
3436 MSEL1CR_13_0, MSEL1CR_13_1,
3437 MSEL1CR_12_0, MSEL1CR_12_1,
3438 0, 0, 0, 0,
3439 MSEL1CR_9_0, MSEL1CR_9_1,
3440 0, 0,
3441 MSEL1CR_7_0, MSEL1CR_7_1,
3442 MSEL1CR_6_0, MSEL1CR_6_1,
3443 MSEL1CR_5_0, MSEL1CR_5_1,
3444 MSEL1CR_4_0, MSEL1CR_4_1,
3445 MSEL1CR_3_0, MSEL1CR_3_1,
3446 MSEL1CR_2_0, MSEL1CR_2_1,
3447 0, 0,
3448 MSEL1CR_0_0, MSEL1CR_0_1,
3449 }
3450 },
3451 { PINMUX_CFG_REG("MSEL3CR", 0xE6058020, 32, 1) {
3452 0, 0, 0, 0, 0, 0, 0, 0,
3453 0, 0, 0, 0, 0, 0, 0, 0,
3454 0, 0, 0, 0, 0, 0, 0, 0,
3455 0, 0, 0, 0, 0, 0, 0, 0,
3456 MSEL3CR_15_0, MSEL3CR_15_1,
3457 0, 0, 0, 0, 0, 0, 0, 0,
3458 0, 0, 0, 0, 0, 0, 0, 0,
3459 MSEL3CR_6_0, MSEL3CR_6_1,
3460 0, 0, 0, 0, 0, 0, 0, 0,
3461 0, 0, 0, 0,
3462 }
3463 },
3464 { PINMUX_CFG_REG("MSEL4CR", 0xE6058024, 32, 1) {
3465 0, 0, 0, 0, 0, 0, 0, 0,
3466 0, 0, 0, 0, 0, 0, 0, 0,
3467 0, 0, 0, 0, 0, 0, 0, 0,
3468 MSEL4CR_19_0, MSEL4CR_19_1,
3469 MSEL4CR_18_0, MSEL4CR_18_1,
3470 0, 0, 0, 0,
3471 MSEL4CR_15_0, MSEL4CR_15_1,
3472 0, 0, 0, 0, 0, 0, 0, 0,
3473 MSEL4CR_10_0, MSEL4CR_10_1,
3474 0, 0, 0, 0, 0, 0,
3475 MSEL4CR_6_0, MSEL4CR_6_1,
3476 0, 0,
3477 MSEL4CR_4_0, MSEL4CR_4_1,
3478 0, 0, 0, 0,
3479 MSEL4CR_1_0, MSEL4CR_1_1,
3480 0, 0,
3481 }
3482 },
3483 { PINMUX_CFG_REG("MSEL5CR", 0xE6058028, 32, 1) {
3484 MSEL5CR_31_0, MSEL5CR_31_1,
3485 MSEL5CR_30_0, MSEL5CR_30_1,
3486 MSEL5CR_29_0, MSEL5CR_29_1,
3487 0, 0,
3488 MSEL5CR_27_0, MSEL5CR_27_1,
3489 0, 0,
3490 MSEL5CR_25_0, MSEL5CR_25_1,
3491 0, 0,
3492 MSEL5CR_23_0, MSEL5CR_23_1,
3493 0, 0,
3494 MSEL5CR_21_0, MSEL5CR_21_1,
3495 0, 0,
3496 MSEL5CR_19_0, MSEL5CR_19_1,
3497 0, 0,
3498 MSEL5CR_17_0, MSEL5CR_17_1,
3499 0, 0,
3500 MSEL5CR_15_0, MSEL5CR_15_1,
3501 MSEL5CR_14_0, MSEL5CR_14_1,
3502 MSEL5CR_13_0, MSEL5CR_13_1,
3503 MSEL5CR_12_0, MSEL5CR_12_1,
3504 MSEL5CR_11_0, MSEL5CR_11_1,
3505 MSEL5CR_10_0, MSEL5CR_10_1,
3506 0, 0,
3507 MSEL5CR_8_0, MSEL5CR_8_1,
3508 MSEL5CR_7_0, MSEL5CR_7_1,
3509 MSEL5CR_6_0, MSEL5CR_6_1,
3510 MSEL5CR_5_0, MSEL5CR_5_1,
3511 MSEL5CR_4_0, MSEL5CR_4_1,
3512 MSEL5CR_3_0, MSEL5CR_3_1,
3513 MSEL5CR_2_0, MSEL5CR_2_1,
3514 0, 0,
3515 MSEL5CR_0_0, MSEL5CR_0_1,
3516 }
3517 },
3518 { },
3519};
3520
Laurent Pinchartcd3c1be2013-02-16 18:47:05 +0100[diff] [blame]3521static const struct pinmux_data_reg pinmux_data_regs[] = {
Laurent Pinchartd5b15212012-12-15 23:51:21 +0100[diff] [blame]3522 { PINMUX_DATA_REG("PORTL031_000DR", 0xe6054800, 32) {
3523 PORT31_DATA, PORT30_DATA, PORT29_DATA, PORT28_DATA,
3524 PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA,
3525 PORT23_DATA, PORT22_DATA, PORT21_DATA, PORT20_DATA,
3526 PORT19_DATA, PORT18_DATA, PORT17_DATA, PORT16_DATA,
3527 PORT15_DATA, PORT14_DATA, PORT13_DATA, PORT12_DATA,
3528 PORT11_DATA, PORT10_DATA, PORT9_DATA, PORT8_DATA,
3529 PORT7_DATA, PORT6_DATA, PORT5_DATA, PORT4_DATA,
3530 PORT3_DATA, PORT2_DATA, PORT1_DATA, PORT0_DATA }
3531 },
3532 { PINMUX_DATA_REG("PORTL063_032DR", 0xe6054804, 32) {
3533 PORT63_DATA, PORT62_DATA, PORT61_DATA, PORT60_DATA,
3534 PORT59_DATA, PORT58_DATA, PORT57_DATA, PORT56_DATA,
3535 PORT55_DATA, PORT54_DATA, PORT53_DATA, PORT52_DATA,
3536 PORT51_DATA, PORT50_DATA, PORT49_DATA, PORT48_DATA,
3537 PORT47_DATA, PORT46_DATA, PORT45_DATA, PORT44_DATA,
3538 PORT43_DATA, PORT42_DATA, PORT41_DATA, PORT40_DATA,
3539 PORT39_DATA, PORT38_DATA, PORT37_DATA, PORT36_DATA,
3540 PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA }
3541 },
3542 { PINMUX_DATA_REG("PORTL095_064DR", 0xe6054808, 32) {
3543 0, 0, 0, 0,
3544 0, 0, 0, 0,
3545 0, 0, 0, 0,
3546 PORT83_DATA, PORT82_DATA, PORT81_DATA, PORT80_DATA,
3547 PORT79_DATA, PORT78_DATA, PORT77_DATA, PORT76_DATA,
3548 PORT75_DATA, PORT74_DATA, PORT73_DATA, PORT72_DATA,
3549 PORT71_DATA, PORT70_DATA, PORT69_DATA, PORT68_DATA,
3550 PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA }
3551 },
3552 { PINMUX_DATA_REG("PORTD095_064DR", 0xe6055808, 32) {
3553 PORT95_DATA, PORT94_DATA, PORT93_DATA, PORT92_DATA,
3554 PORT91_DATA, PORT90_DATA, PORT89_DATA, PORT88_DATA,
3555 PORT87_DATA, PORT86_DATA, PORT85_DATA, PORT84_DATA,
3556 0, 0, 0, 0,
3557 0, 0, 0, 0,
3558 0, 0, 0, 0,
3559 0, 0, 0, 0,
3560 0, 0, 0, 0 }
3561 },
3562 { PINMUX_DATA_REG("PORTD127_096DR", 0xe605580c, 32) {
3563 0, 0, 0, 0,
3564 0, 0, 0, 0,
3565 0, 0, 0, 0,
3566 0, PORT114_DATA, PORT113_DATA, PORT112_DATA,
3567 PORT111_DATA, PORT110_DATA, PORT109_DATA, PORT108_DATA,
3568 PORT107_DATA, PORT106_DATA, PORT105_DATA, PORT104_DATA,
3569 PORT103_DATA, PORT102_DATA, PORT101_DATA, PORT100_DATA,
3570 PORT99_DATA, PORT98_DATA, PORT97_DATA, PORT96_DATA }
3571 },
3572 { PINMUX_DATA_REG("PORTR127_096DR", 0xe605680C, 32) {
3573 PORT127_DATA, PORT126_DATA, PORT125_DATA, PORT124_DATA,
3574 PORT123_DATA, PORT122_DATA, PORT121_DATA, PORT120_DATA,
3575 PORT119_DATA, PORT118_DATA, PORT117_DATA, PORT116_DATA,
3576 PORT115_DATA, 0, 0, 0,
3577 0, 0, 0, 0,
3578 0, 0, 0, 0,
3579 0, 0, 0, 0,
3580 0, 0, 0, 0 }
3581 },
3582 { PINMUX_DATA_REG("PORTR159_128DR", 0xe6056810, 32) {
3583 PORT159_DATA, PORT158_DATA, PORT157_DATA, PORT156_DATA,
3584 PORT155_DATA, PORT154_DATA, PORT153_DATA, PORT152_DATA,
3585 PORT151_DATA, PORT150_DATA, PORT149_DATA, PORT148_DATA,
3586 PORT147_DATA, PORT146_DATA, PORT145_DATA, PORT144_DATA,
3587 PORT143_DATA, PORT142_DATA, PORT141_DATA, PORT140_DATA,
3588 PORT139_DATA, PORT138_DATA, PORT137_DATA, PORT136_DATA,
3589 PORT135_DATA, PORT134_DATA, PORT133_DATA, PORT132_DATA,
3590 PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA }
3591 },
3592 { PINMUX_DATA_REG("PORTR191_160DR", 0xe6056814, 32) {
3593 PORT191_DATA, PORT190_DATA, PORT189_DATA, PORT188_DATA,
3594 PORT187_DATA, PORT186_DATA, PORT185_DATA, PORT184_DATA,
3595 PORT183_DATA, PORT182_DATA, PORT181_DATA, PORT180_DATA,
3596 PORT179_DATA, PORT178_DATA, PORT177_DATA, PORT176_DATA,
3597 PORT175_DATA, PORT174_DATA, PORT173_DATA, PORT172_DATA,
3598 PORT171_DATA, PORT170_DATA, PORT169_DATA, PORT168_DATA,
3599 PORT167_DATA, PORT166_DATA, PORT165_DATA, PORT164_DATA,
3600 PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA }
3601 },
3602 { PINMUX_DATA_REG("PORTR223_192DR", 0xe6056818, 32) {
3603 0, 0, 0, 0,
3604 0, 0, 0, 0,
3605 0, 0, 0, 0,
3606 0, 0, PORT209_DATA, PORT208_DATA,
3607 PORT207_DATA, PORT206_DATA, PORT205_DATA, PORT204_DATA,
3608 PORT203_DATA, PORT202_DATA, PORT201_DATA, PORT200_DATA,
3609 PORT199_DATA, PORT198_DATA, PORT197_DATA, PORT196_DATA,
3610 PORT195_DATA, PORT194_DATA, PORT193_DATA, PORT192_DATA }
3611 },
3612 { PINMUX_DATA_REG("PORTU223_192DR", 0xe6057818, 32) {
3613 0, 0, 0, 0,
3614 0, 0, 0, 0,
3615 0, 0, 0, 0,
3616 PORT211_DATA, PORT210_DATA, 0, 0,
3617 0, 0, 0, 0,
3618 0, 0, 0, 0,
3619 0, 0, 0, 0,
3620 0, 0, 0, 0 }
3621 },
3622 { },
3623};
3624
Laurent Pinchartcd3c1be2013-02-16 18:47:05 +0100[diff] [blame]3625static const struct pinmux_irq pinmux_irqs[] = {
Laurent Pinchart7d568452013-04-23 00:36:40 +0200[diff] [blame^]3626 PINMUX_IRQ(irq_pin(0), 2, 13), /* IRQ0A */
3627 PINMUX_IRQ(irq_pin(1), 20), /* IRQ1A */
3628 PINMUX_IRQ(irq_pin(2), 11, 12), /* IRQ2A */
3629 PINMUX_IRQ(irq_pin(3), 10, 14), /* IRQ3A */
3630 PINMUX_IRQ(irq_pin(4), 15, 172), /* IRQ4A */
3631 PINMUX_IRQ(irq_pin(5), 0, 1), /* IRQ5A */
3632 PINMUX_IRQ(irq_pin(6), 121, 173), /* IRQ6A */
3633 PINMUX_IRQ(irq_pin(7), 120, 209), /* IRQ7A */
3634 PINMUX_IRQ(irq_pin(8), 119), /* IRQ8A */
3635 PINMUX_IRQ(irq_pin(9), 118, 210), /* IRQ9A */
3636 PINMUX_IRQ(irq_pin(10), 19), /* IRQ10A */
3637 PINMUX_IRQ(irq_pin(11), 104), /* IRQ11A */
3638 PINMUX_IRQ(irq_pin(12), 42, 97), /* IRQ12A */
3639 PINMUX_IRQ(irq_pin(13), 64, 98), /* IRQ13A */
3640 PINMUX_IRQ(irq_pin(14), 63, 99), /* IRQ14A */
3641 PINMUX_IRQ(irq_pin(15), 62, 100), /* IRQ15A */
3642 PINMUX_IRQ(irq_pin(16), 68, 211), /* IRQ16A */
3643 PINMUX_IRQ(irq_pin(17), 69), /* IRQ17A */
3644 PINMUX_IRQ(irq_pin(18), 70), /* IRQ18A */
3645 PINMUX_IRQ(irq_pin(19), 71), /* IRQ19A */
3646 PINMUX_IRQ(irq_pin(20), 67), /* IRQ20A */
3647 PINMUX_IRQ(irq_pin(21), 202), /* IRQ21A */
3648 PINMUX_IRQ(irq_pin(22), 95), /* IRQ22A */
3649 PINMUX_IRQ(irq_pin(23), 96), /* IRQ23A */
3650 PINMUX_IRQ(irq_pin(24), 180), /* IRQ24A */
3651 PINMUX_IRQ(irq_pin(25), 38), /* IRQ25A */
3652 PINMUX_IRQ(irq_pin(26), 58, 81), /* IRQ26A */
3653 PINMUX_IRQ(irq_pin(27), 57, 168), /* IRQ27A */
3654 PINMUX_IRQ(irq_pin(28), 56, 169), /* IRQ28A */
3655 PINMUX_IRQ(irq_pin(29), 50, 170), /* IRQ29A */
3656 PINMUX_IRQ(irq_pin(30), 49, 171), /* IRQ30A */
3657 PINMUX_IRQ(irq_pin(31), 41, 167), /* IRQ31A */
Laurent Pinchartd5b15212012-12-15 23:51:21 +0100[diff] [blame]3658};
3659
Laurent Pinchartcd3c1be2013-02-16 18:47:05 +0100[diff] [blame]3660const struct sh_pfc_soc_info r8a7740_pinmux_info = {
Laurent Pinchartd5b15212012-12-15 23:51:21 +0100[diff] [blame]3661 .name = "r8a7740_pfc",
Laurent Pinchartd5b15212012-12-15 23:51:21 +0100[diff] [blame]3662 .input = { PINMUX_INPUT_BEGIN,
3663 PINMUX_INPUT_END },
3664 .input_pu = { PINMUX_INPUT_PULLUP_BEGIN,
3665 PINMUX_INPUT_PULLUP_END },
3666 .input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN,
3667 PINMUX_INPUT_PULLDOWN_END },
3668 .output = { PINMUX_OUTPUT_BEGIN,
3669 PINMUX_OUTPUT_END },
Laurent Pinchartd5b15212012-12-15 23:51:21 +0100[diff] [blame]3670 .function = { PINMUX_FUNCTION_BEGIN,
3671 PINMUX_FUNCTION_END },
3672
Laurent Pincharta373ed02012-11-29 13:24:07 +0100[diff] [blame]3673 .pins = pinmux_pins,
3674 .nr_pins = ARRAY_SIZE(pinmux_pins),
Laurent Pinchart06c7dd82013-01-03 13:07:05 +0100[diff] [blame]3675 .groups = pinmux_groups,
3676 .nr_groups = ARRAY_SIZE(pinmux_groups),
3677 .functions = pinmux_functions,
3678 .nr_functions = ARRAY_SIZE(pinmux_functions),
3679
Laurent Pinchartd5b15212012-12-15 23:51:21 +0100[diff] [blame]3680 .cfg_regs = pinmux_config_regs,
3681 .data_regs = pinmux_data_regs,
3682
3683 .gpio_data = pinmux_data,
3684 .gpio_data_size = ARRAY_SIZE(pinmux_data),
3685
3686 .gpio_irq = pinmux_irqs,
3687 .gpio_irq_size = ARRAY_SIZE(pinmux_irqs),
3688};