Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 1 | /* |
| 2 | * SuperH Timer Support - MTU2 |
| 3 | * |
| 4 | * Copyright (C) 2009 Magnus Damm |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; either version 2 of the License |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 18 | */ |
| 19 | |
| 20 | #include <linux/init.h> |
| 21 | #include <linux/platform_device.h> |
| 22 | #include <linux/spinlock.h> |
| 23 | #include <linux/interrupt.h> |
| 24 | #include <linux/ioport.h> |
| 25 | #include <linux/delay.h> |
| 26 | #include <linux/io.h> |
| 27 | #include <linux/clk.h> |
| 28 | #include <linux/irq.h> |
| 29 | #include <linux/err.h> |
| 30 | #include <linux/clockchips.h> |
Paul Mundt | 46a12f7 | 2009-05-03 17:57:17 +0900 | [diff] [blame] | 31 | #include <linux/sh_timer.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 32 | #include <linux/slab.h> |
Paul Gortmaker | 7deeab5 | 2011-07-03 13:36:22 -0400 | [diff] [blame] | 33 | #include <linux/module.h> |
Rafael J. Wysocki | 57d1337 | 2012-03-13 22:40:14 +0100 | [diff] [blame] | 34 | #include <linux/pm_domain.h> |
Rafael J. Wysocki | 3cb6f10 | 2012-08-13 14:00:16 +0200 | [diff] [blame] | 35 | #include <linux/pm_runtime.h> |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 36 | |
Laurent Pinchart | 7dad72d | 2014-03-04 13:04:48 +0100 | [diff] [blame^] | 37 | struct sh_mtu2_device; |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 38 | |
| 39 | struct sh_mtu2_channel { |
Laurent Pinchart | 7dad72d | 2014-03-04 13:04:48 +0100 | [diff] [blame^] | 40 | struct sh_mtu2_device *mtu; |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 41 | int irq; |
| 42 | struct clock_event_device ced; |
| 43 | }; |
| 44 | |
Laurent Pinchart | 7dad72d | 2014-03-04 13:04:48 +0100 | [diff] [blame^] | 45 | struct sh_mtu2_device { |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 46 | struct platform_device *pdev; |
| 47 | |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 48 | void __iomem *mapbase; |
| 49 | struct clk *clk; |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 50 | |
| 51 | struct sh_mtu2_channel channel; |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 52 | }; |
| 53 | |
Paul Mundt | 50393a9 | 2012-05-25 13:38:54 +0900 | [diff] [blame] | 54 | static DEFINE_RAW_SPINLOCK(sh_mtu2_lock); |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 55 | |
| 56 | #define TSTR -1 /* shared register */ |
| 57 | #define TCR 0 /* channel register */ |
| 58 | #define TMDR 1 /* channel register */ |
| 59 | #define TIOR 2 /* channel register */ |
| 60 | #define TIER 3 /* channel register */ |
| 61 | #define TSR 4 /* channel register */ |
| 62 | #define TCNT 5 /* channel register */ |
| 63 | #define TGR 6 /* channel register */ |
| 64 | |
| 65 | static unsigned long mtu2_reg_offs[] = { |
| 66 | [TCR] = 0, |
| 67 | [TMDR] = 1, |
| 68 | [TIOR] = 2, |
| 69 | [TIER] = 4, |
| 70 | [TSR] = 5, |
| 71 | [TCNT] = 6, |
| 72 | [TGR] = 8, |
| 73 | }; |
| 74 | |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 75 | static inline unsigned long sh_mtu2_read(struct sh_mtu2_channel *ch, int reg_nr) |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 76 | { |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 77 | struct sh_timer_config *cfg = ch->mtu->pdev->dev.platform_data; |
| 78 | void __iomem *base = ch->mtu->mapbase; |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 79 | unsigned long offs; |
| 80 | |
| 81 | if (reg_nr == TSTR) |
| 82 | return ioread8(base + cfg->channel_offset); |
| 83 | |
| 84 | offs = mtu2_reg_offs[reg_nr]; |
| 85 | |
| 86 | if ((reg_nr == TCNT) || (reg_nr == TGR)) |
| 87 | return ioread16(base + offs); |
| 88 | else |
| 89 | return ioread8(base + offs); |
| 90 | } |
| 91 | |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 92 | static inline void sh_mtu2_write(struct sh_mtu2_channel *ch, int reg_nr, |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 93 | unsigned long value) |
| 94 | { |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 95 | struct sh_timer_config *cfg = ch->mtu->pdev->dev.platform_data; |
| 96 | void __iomem *base = ch->mtu->mapbase; |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 97 | unsigned long offs; |
| 98 | |
| 99 | if (reg_nr == TSTR) { |
| 100 | iowrite8(value, base + cfg->channel_offset); |
| 101 | return; |
| 102 | } |
| 103 | |
| 104 | offs = mtu2_reg_offs[reg_nr]; |
| 105 | |
| 106 | if ((reg_nr == TCNT) || (reg_nr == TGR)) |
| 107 | iowrite16(value, base + offs); |
| 108 | else |
| 109 | iowrite8(value, base + offs); |
| 110 | } |
| 111 | |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 112 | static void sh_mtu2_start_stop_ch(struct sh_mtu2_channel *ch, int start) |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 113 | { |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 114 | struct sh_timer_config *cfg = ch->mtu->pdev->dev.platform_data; |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 115 | unsigned long flags, value; |
| 116 | |
| 117 | /* start stop register shared by multiple timer channels */ |
Paul Mundt | 50393a9 | 2012-05-25 13:38:54 +0900 | [diff] [blame] | 118 | raw_spin_lock_irqsave(&sh_mtu2_lock, flags); |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 119 | value = sh_mtu2_read(ch, TSTR); |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 120 | |
| 121 | if (start) |
| 122 | value |= 1 << cfg->timer_bit; |
| 123 | else |
| 124 | value &= ~(1 << cfg->timer_bit); |
| 125 | |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 126 | sh_mtu2_write(ch, TSTR, value); |
Paul Mundt | 50393a9 | 2012-05-25 13:38:54 +0900 | [diff] [blame] | 127 | raw_spin_unlock_irqrestore(&sh_mtu2_lock, flags); |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 128 | } |
| 129 | |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 130 | static int sh_mtu2_enable(struct sh_mtu2_channel *ch) |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 131 | { |
Laurent Pinchart | f92d62f5 | 2014-03-04 12:59:54 +0100 | [diff] [blame] | 132 | unsigned long periodic; |
| 133 | unsigned long rate; |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 134 | int ret; |
| 135 | |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 136 | pm_runtime_get_sync(&ch->mtu->pdev->dev); |
| 137 | dev_pm_syscore_device(&ch->mtu->pdev->dev, true); |
Rafael J. Wysocki | 3cb6f10 | 2012-08-13 14:00:16 +0200 | [diff] [blame] | 138 | |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 139 | /* enable clock */ |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 140 | ret = clk_enable(ch->mtu->clk); |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 141 | if (ret) { |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 142 | dev_err(&ch->mtu->pdev->dev, "cannot enable clock\n"); |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 143 | return ret; |
| 144 | } |
| 145 | |
| 146 | /* make sure channel is disabled */ |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 147 | sh_mtu2_start_stop_ch(ch, 0); |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 148 | |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 149 | rate = clk_get_rate(ch->mtu->clk) / 64; |
Laurent Pinchart | f92d62f5 | 2014-03-04 12:59:54 +0100 | [diff] [blame] | 150 | periodic = (rate + HZ/2) / HZ; |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 151 | |
| 152 | /* "Periodic Counter Operation" */ |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 153 | sh_mtu2_write(ch, TCR, 0x23); /* TGRA clear, divide clock by 64 */ |
| 154 | sh_mtu2_write(ch, TIOR, 0); |
| 155 | sh_mtu2_write(ch, TGR, periodic); |
| 156 | sh_mtu2_write(ch, TCNT, 0); |
| 157 | sh_mtu2_write(ch, TMDR, 0); |
| 158 | sh_mtu2_write(ch, TIER, 0x01); |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 159 | |
| 160 | /* enable channel */ |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 161 | sh_mtu2_start_stop_ch(ch, 1); |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 162 | |
| 163 | return 0; |
| 164 | } |
| 165 | |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 166 | static void sh_mtu2_disable(struct sh_mtu2_channel *ch) |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 167 | { |
| 168 | /* disable channel */ |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 169 | sh_mtu2_start_stop_ch(ch, 0); |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 170 | |
| 171 | /* stop clock */ |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 172 | clk_disable(ch->mtu->clk); |
Rafael J. Wysocki | 3cb6f10 | 2012-08-13 14:00:16 +0200 | [diff] [blame] | 173 | |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 174 | dev_pm_syscore_device(&ch->mtu->pdev->dev, false); |
| 175 | pm_runtime_put(&ch->mtu->pdev->dev); |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 176 | } |
| 177 | |
| 178 | static irqreturn_t sh_mtu2_interrupt(int irq, void *dev_id) |
| 179 | { |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 180 | struct sh_mtu2_channel *ch = dev_id; |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 181 | |
| 182 | /* acknowledge interrupt */ |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 183 | sh_mtu2_read(ch, TSR); |
| 184 | sh_mtu2_write(ch, TSR, 0xfe); |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 185 | |
| 186 | /* notify clockevent layer */ |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 187 | ch->ced.event_handler(&ch->ced); |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 188 | return IRQ_HANDLED; |
| 189 | } |
| 190 | |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 191 | static struct sh_mtu2_channel *ced_to_sh_mtu2(struct clock_event_device *ced) |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 192 | { |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 193 | return container_of(ced, struct sh_mtu2_channel, ced); |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 194 | } |
| 195 | |
| 196 | static void sh_mtu2_clock_event_mode(enum clock_event_mode mode, |
| 197 | struct clock_event_device *ced) |
| 198 | { |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 199 | struct sh_mtu2_channel *ch = ced_to_sh_mtu2(ced); |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 200 | int disabled = 0; |
| 201 | |
| 202 | /* deal with old setting first */ |
| 203 | switch (ced->mode) { |
| 204 | case CLOCK_EVT_MODE_PERIODIC: |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 205 | sh_mtu2_disable(ch); |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 206 | disabled = 1; |
| 207 | break; |
| 208 | default: |
| 209 | break; |
| 210 | } |
| 211 | |
| 212 | switch (mode) { |
| 213 | case CLOCK_EVT_MODE_PERIODIC: |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 214 | dev_info(&ch->mtu->pdev->dev, |
| 215 | "used for periodic clock events\n"); |
| 216 | sh_mtu2_enable(ch); |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 217 | break; |
| 218 | case CLOCK_EVT_MODE_UNUSED: |
| 219 | if (!disabled) |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 220 | sh_mtu2_disable(ch); |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 221 | break; |
| 222 | case CLOCK_EVT_MODE_SHUTDOWN: |
| 223 | default: |
| 224 | break; |
| 225 | } |
| 226 | } |
| 227 | |
Rafael J. Wysocki | cc7ad45 | 2012-08-06 01:43:41 +0200 | [diff] [blame] | 228 | static void sh_mtu2_clock_event_suspend(struct clock_event_device *ced) |
| 229 | { |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 230 | pm_genpd_syscore_poweroff(&ced_to_sh_mtu2(ced)->mtu->pdev->dev); |
Rafael J. Wysocki | cc7ad45 | 2012-08-06 01:43:41 +0200 | [diff] [blame] | 231 | } |
| 232 | |
| 233 | static void sh_mtu2_clock_event_resume(struct clock_event_device *ced) |
| 234 | { |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 235 | pm_genpd_syscore_poweron(&ced_to_sh_mtu2(ced)->mtu->pdev->dev); |
Rafael J. Wysocki | cc7ad45 | 2012-08-06 01:43:41 +0200 | [diff] [blame] | 236 | } |
| 237 | |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 238 | static void sh_mtu2_register_clockevent(struct sh_mtu2_channel *ch, |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 239 | char *name, unsigned long rating) |
| 240 | { |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 241 | struct clock_event_device *ced = &ch->ced; |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 242 | int ret; |
| 243 | |
| 244 | memset(ced, 0, sizeof(*ced)); |
| 245 | |
| 246 | ced->name = name; |
| 247 | ced->features = CLOCK_EVT_FEAT_PERIODIC; |
| 248 | ced->rating = rating; |
| 249 | ced->cpumask = cpumask_of(0); |
| 250 | ced->set_mode = sh_mtu2_clock_event_mode; |
Rafael J. Wysocki | cc7ad45 | 2012-08-06 01:43:41 +0200 | [diff] [blame] | 251 | ced->suspend = sh_mtu2_clock_event_suspend; |
| 252 | ced->resume = sh_mtu2_clock_event_resume; |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 253 | |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 254 | dev_info(&ch->mtu->pdev->dev, "used for clock events\n"); |
Paul Mundt | da64c2a | 2010-02-25 16:37:46 +0900 | [diff] [blame] | 255 | clockevents_register_device(ced); |
| 256 | |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 257 | ret = request_irq(ch->irq, sh_mtu2_interrupt, |
Laurent Pinchart | 276bee0 | 2014-02-17 11:27:49 +0100 | [diff] [blame] | 258 | IRQF_TIMER | IRQF_IRQPOLL | IRQF_NOBALANCING, |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 259 | dev_name(&ch->mtu->pdev->dev), ch); |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 260 | if (ret) { |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 261 | dev_err(&ch->mtu->pdev->dev, "failed to request irq %d\n", |
| 262 | ch->irq); |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 263 | return; |
| 264 | } |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 265 | } |
| 266 | |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 267 | static int sh_mtu2_register(struct sh_mtu2_channel *ch, char *name, |
Paul Mundt | d1fcc0a | 2009-05-03 18:05:42 +0900 | [diff] [blame] | 268 | unsigned long clockevent_rating) |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 269 | { |
| 270 | if (clockevent_rating) |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 271 | sh_mtu2_register_clockevent(ch, name, clockevent_rating); |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 272 | |
| 273 | return 0; |
| 274 | } |
| 275 | |
Laurent Pinchart | 7dad72d | 2014-03-04 13:04:48 +0100 | [diff] [blame^] | 276 | static int sh_mtu2_setup(struct sh_mtu2_device *mtu, |
| 277 | struct platform_device *pdev) |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 278 | { |
Paul Mundt | 46a12f7 | 2009-05-03 17:57:17 +0900 | [diff] [blame] | 279 | struct sh_timer_config *cfg = pdev->dev.platform_data; |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 280 | struct resource *res; |
Laurent Pinchart | 276bee0 | 2014-02-17 11:27:49 +0100 | [diff] [blame] | 281 | int ret; |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 282 | ret = -ENXIO; |
| 283 | |
Laurent Pinchart | 7dad72d | 2014-03-04 13:04:48 +0100 | [diff] [blame^] | 284 | memset(mtu, 0, sizeof(*mtu)); |
| 285 | mtu->pdev = pdev; |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 286 | |
| 287 | if (!cfg) { |
Laurent Pinchart | 7dad72d | 2014-03-04 13:04:48 +0100 | [diff] [blame^] | 288 | dev_err(&mtu->pdev->dev, "missing platform data\n"); |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 289 | goto err0; |
| 290 | } |
| 291 | |
Laurent Pinchart | 7dad72d | 2014-03-04 13:04:48 +0100 | [diff] [blame^] | 292 | platform_set_drvdata(pdev, mtu); |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 293 | |
Laurent Pinchart | 7dad72d | 2014-03-04 13:04:48 +0100 | [diff] [blame^] | 294 | res = platform_get_resource(mtu->pdev, IORESOURCE_MEM, 0); |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 295 | if (!res) { |
Laurent Pinchart | 7dad72d | 2014-03-04 13:04:48 +0100 | [diff] [blame^] | 296 | dev_err(&mtu->pdev->dev, "failed to get I/O memory\n"); |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 297 | goto err0; |
| 298 | } |
| 299 | |
Laurent Pinchart | 7dad72d | 2014-03-04 13:04:48 +0100 | [diff] [blame^] | 300 | mtu->channel.irq = platform_get_irq(mtu->pdev, 0); |
| 301 | if (mtu->channel.irq < 0) { |
| 302 | dev_err(&mtu->pdev->dev, "failed to get irq\n"); |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 303 | goto err0; |
| 304 | } |
| 305 | |
| 306 | /* map memory, let mapbase point to our channel */ |
Laurent Pinchart | 7dad72d | 2014-03-04 13:04:48 +0100 | [diff] [blame^] | 307 | mtu->mapbase = ioremap_nocache(res->start, resource_size(res)); |
| 308 | if (mtu->mapbase == NULL) { |
| 309 | dev_err(&mtu->pdev->dev, "failed to remap I/O memory\n"); |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 310 | goto err0; |
| 311 | } |
| 312 | |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 313 | /* get hold of clock */ |
Laurent Pinchart | 7dad72d | 2014-03-04 13:04:48 +0100 | [diff] [blame^] | 314 | mtu->clk = clk_get(&mtu->pdev->dev, "mtu2_fck"); |
| 315 | if (IS_ERR(mtu->clk)) { |
| 316 | dev_err(&mtu->pdev->dev, "cannot get clock\n"); |
| 317 | ret = PTR_ERR(mtu->clk); |
Magnus Damm | 03ff858 | 2010-10-13 07:36:38 +0000 | [diff] [blame] | 318 | goto err1; |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 319 | } |
| 320 | |
Laurent Pinchart | 7dad72d | 2014-03-04 13:04:48 +0100 | [diff] [blame^] | 321 | ret = clk_prepare(mtu->clk); |
Laurent Pinchart | a4a5fc3 | 2013-11-08 11:07:59 +0100 | [diff] [blame] | 322 | if (ret < 0) |
| 323 | goto err2; |
| 324 | |
Laurent Pinchart | 7dad72d | 2014-03-04 13:04:48 +0100 | [diff] [blame^] | 325 | mtu->channel.mtu = mtu; |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 326 | |
Laurent Pinchart | 7dad72d | 2014-03-04 13:04:48 +0100 | [diff] [blame^] | 327 | ret = sh_mtu2_register(&mtu->channel, (char *)dev_name(&mtu->pdev->dev), |
Laurent Pinchart | bd75493 | 2013-11-08 11:07:59 +0100 | [diff] [blame] | 328 | cfg->clockevent_rating); |
| 329 | if (ret < 0) |
| 330 | goto err3; |
Laurent Pinchart | a4a5fc3 | 2013-11-08 11:07:59 +0100 | [diff] [blame] | 331 | |
Laurent Pinchart | bd75493 | 2013-11-08 11:07:59 +0100 | [diff] [blame] | 332 | return 0; |
| 333 | err3: |
Laurent Pinchart | 7dad72d | 2014-03-04 13:04:48 +0100 | [diff] [blame^] | 334 | clk_unprepare(mtu->clk); |
Laurent Pinchart | a4a5fc3 | 2013-11-08 11:07:59 +0100 | [diff] [blame] | 335 | err2: |
Laurent Pinchart | 7dad72d | 2014-03-04 13:04:48 +0100 | [diff] [blame^] | 336 | clk_put(mtu->clk); |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 337 | err1: |
Laurent Pinchart | 7dad72d | 2014-03-04 13:04:48 +0100 | [diff] [blame^] | 338 | iounmap(mtu->mapbase); |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 339 | err0: |
| 340 | return ret; |
| 341 | } |
| 342 | |
Greg Kroah-Hartman | 1850514 | 2012-12-21 15:11:38 -0800 | [diff] [blame] | 343 | static int sh_mtu2_probe(struct platform_device *pdev) |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 344 | { |
Laurent Pinchart | 7dad72d | 2014-03-04 13:04:48 +0100 | [diff] [blame^] | 345 | struct sh_mtu2_device *mtu = platform_get_drvdata(pdev); |
Rafael J. Wysocki | 3cb6f10 | 2012-08-13 14:00:16 +0200 | [diff] [blame] | 346 | struct sh_timer_config *cfg = pdev->dev.platform_data; |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 347 | int ret; |
| 348 | |
Rafael J. Wysocki | cc7ad45 | 2012-08-06 01:43:41 +0200 | [diff] [blame] | 349 | if (!is_early_platform_device(pdev)) { |
Rafael J. Wysocki | 3cb6f10 | 2012-08-13 14:00:16 +0200 | [diff] [blame] | 350 | pm_runtime_set_active(&pdev->dev); |
| 351 | pm_runtime_enable(&pdev->dev); |
Rafael J. Wysocki | cc7ad45 | 2012-08-06 01:43:41 +0200 | [diff] [blame] | 352 | } |
Rafael J. Wysocki | 57d1337 | 2012-03-13 22:40:14 +0100 | [diff] [blame] | 353 | |
Laurent Pinchart | 7dad72d | 2014-03-04 13:04:48 +0100 | [diff] [blame^] | 354 | if (mtu) { |
Paul Mundt | 214a607 | 2010-03-10 16:26:25 +0900 | [diff] [blame] | 355 | dev_info(&pdev->dev, "kept as earlytimer\n"); |
Rafael J. Wysocki | 3cb6f10 | 2012-08-13 14:00:16 +0200 | [diff] [blame] | 356 | goto out; |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 357 | } |
| 358 | |
Laurent Pinchart | 7dad72d | 2014-03-04 13:04:48 +0100 | [diff] [blame^] | 359 | mtu = kmalloc(sizeof(*mtu), GFP_KERNEL); |
| 360 | if (mtu == NULL) { |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 361 | dev_err(&pdev->dev, "failed to allocate driver data\n"); |
| 362 | return -ENOMEM; |
| 363 | } |
| 364 | |
Laurent Pinchart | 7dad72d | 2014-03-04 13:04:48 +0100 | [diff] [blame^] | 365 | ret = sh_mtu2_setup(mtu, pdev); |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 366 | if (ret) { |
Laurent Pinchart | 7dad72d | 2014-03-04 13:04:48 +0100 | [diff] [blame^] | 367 | kfree(mtu); |
Rafael J. Wysocki | 3cb6f10 | 2012-08-13 14:00:16 +0200 | [diff] [blame] | 368 | pm_runtime_idle(&pdev->dev); |
| 369 | return ret; |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 370 | } |
Rafael J. Wysocki | 3cb6f10 | 2012-08-13 14:00:16 +0200 | [diff] [blame] | 371 | if (is_early_platform_device(pdev)) |
| 372 | return 0; |
| 373 | |
| 374 | out: |
| 375 | if (cfg->clockevent_rating) |
| 376 | pm_runtime_irq_safe(&pdev->dev); |
| 377 | else |
| 378 | pm_runtime_idle(&pdev->dev); |
| 379 | |
| 380 | return 0; |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 381 | } |
| 382 | |
Greg Kroah-Hartman | 1850514 | 2012-12-21 15:11:38 -0800 | [diff] [blame] | 383 | static int sh_mtu2_remove(struct platform_device *pdev) |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 384 | { |
| 385 | return -EBUSY; /* cannot unregister clockevent */ |
| 386 | } |
| 387 | |
| 388 | static struct platform_driver sh_mtu2_device_driver = { |
| 389 | .probe = sh_mtu2_probe, |
Greg Kroah-Hartman | 1850514 | 2012-12-21 15:11:38 -0800 | [diff] [blame] | 390 | .remove = sh_mtu2_remove, |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 391 | .driver = { |
| 392 | .name = "sh_mtu2", |
| 393 | } |
| 394 | }; |
| 395 | |
| 396 | static int __init sh_mtu2_init(void) |
| 397 | { |
| 398 | return platform_driver_register(&sh_mtu2_device_driver); |
| 399 | } |
| 400 | |
| 401 | static void __exit sh_mtu2_exit(void) |
| 402 | { |
| 403 | platform_driver_unregister(&sh_mtu2_device_driver); |
| 404 | } |
| 405 | |
| 406 | early_platform_init("earlytimer", &sh_mtu2_device_driver); |
Simon Horman | 342896a | 2013-03-05 15:40:42 +0900 | [diff] [blame] | 407 | subsys_initcall(sh_mtu2_init); |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 408 | module_exit(sh_mtu2_exit); |
| 409 | |
| 410 | MODULE_AUTHOR("Magnus Damm"); |
| 411 | MODULE_DESCRIPTION("SuperH MTU2 Timer Driver"); |
| 412 | MODULE_LICENSE("GPL v2"); |