Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 1 | /* |
| 2 | * drivers/mmc/host/sdhci-msm.c - Qualcomm Technologies, Inc. MSM SDHCI Platform |
| 3 | * driver source file |
| 4 | * |
| 5 | * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License version 2 and |
| 9 | * only version 2 as published by the Free Software Foundation. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | */ |
| 17 | |
| 18 | #include <linux/module.h> |
| 19 | #include <linux/mmc/host.h> |
| 20 | #include <linux/mmc/card.h> |
| 21 | #include <linux/mmc/sdio_func.h> |
| 22 | #include <linux/gfp.h> |
| 23 | #include <linux/of.h> |
| 24 | #include <linux/of_gpio.h> |
| 25 | #include <linux/regulator/consumer.h> |
| 26 | #include <linux/types.h> |
| 27 | #include <linux/input.h> |
| 28 | #include <linux/platform_device.h> |
| 29 | #include <linux/wait.h> |
Venkat Gopalakrishnan | 7944a37 | 2012-09-11 16:13:31 -0700 | [diff] [blame] | 30 | #include <linux/io.h> |
| 31 | #include <linux/delay.h> |
| 32 | #include <linux/scatterlist.h> |
| 33 | #include <linux/slab.h> |
| 34 | #include <linux/mmc/mmc.h> |
Sahitya Tummala | 581df13 | 2013-03-12 14:57:46 +0530 | [diff] [blame] | 35 | #include <linux/mmc/slot-gpio.h> |
Sahitya Tummala | eaa2186 | 2013-03-20 19:34:59 +0530 | [diff] [blame] | 36 | #include <linux/dma-mapping.h> |
Sahitya Tummala | 66b0fe3 | 2013-04-25 11:50:56 +0530 | [diff] [blame] | 37 | #include <linux/iopoll.h> |
Sahitya Tummala | 8a3e818 | 2013-03-10 14:12:52 +0530 | [diff] [blame] | 38 | #include <linux/msm-bus.h> |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 39 | |
| 40 | #include "sdhci-pltfm.h" |
| 41 | |
Venkat Gopalakrishnan | a58f91f | 2012-09-17 16:00:15 -0700 | [diff] [blame] | 42 | #define SDHCI_VER_100 0x2B |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 43 | #define CORE_HC_MODE 0x78 |
| 44 | #define HC_MODE_EN 0x1 |
Venkat Gopalakrishnan | 7f69157 | 2013-06-23 17:36:46 -0700 | [diff] [blame^] | 45 | #define FF_CLK_SW_RST_DIS (1 << 13) |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 46 | |
Sahitya Tummala | 481fbb0 | 2013-08-06 15:22:28 +0530 | [diff] [blame] | 47 | #define CORE_GENERICS 0x70 |
| 48 | #define SWITCHABLE_SIGNALLING_VOL (1 << 29) |
| 49 | |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 50 | #define CORE_POWER 0x0 |
| 51 | #define CORE_SW_RST (1 << 7) |
| 52 | |
Sahitya Tummala | 67717bc | 2013-08-02 09:21:37 +0530 | [diff] [blame] | 53 | #define CORE_MCI_VERSION 0x050 |
| 54 | #define CORE_TESTBUS_CONFIG 0x0CC |
| 55 | #define CORE_TESTBUS_ENA (1 << 3) |
| 56 | #define CORE_SDCC_DEBUG_REG 0x124 |
| 57 | |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 58 | #define CORE_PWRCTL_STATUS 0xDC |
| 59 | #define CORE_PWRCTL_MASK 0xE0 |
| 60 | #define CORE_PWRCTL_CLEAR 0xE4 |
| 61 | #define CORE_PWRCTL_CTL 0xE8 |
| 62 | |
| 63 | #define CORE_PWRCTL_BUS_OFF 0x01 |
| 64 | #define CORE_PWRCTL_BUS_ON (1 << 1) |
| 65 | #define CORE_PWRCTL_IO_LOW (1 << 2) |
| 66 | #define CORE_PWRCTL_IO_HIGH (1 << 3) |
| 67 | |
| 68 | #define CORE_PWRCTL_BUS_SUCCESS 0x01 |
| 69 | #define CORE_PWRCTL_BUS_FAIL (1 << 1) |
| 70 | #define CORE_PWRCTL_IO_SUCCESS (1 << 2) |
| 71 | #define CORE_PWRCTL_IO_FAIL (1 << 3) |
| 72 | |
| 73 | #define INT_MASK 0xF |
Venkat Gopalakrishnan | 7944a37 | 2012-09-11 16:13:31 -0700 | [diff] [blame] | 74 | #define MAX_PHASES 16 |
| 75 | |
| 76 | #define CORE_DLL_LOCK (1 << 7) |
| 77 | #define CORE_DLL_EN (1 << 16) |
| 78 | #define CORE_CDR_EN (1 << 17) |
| 79 | #define CORE_CK_OUT_EN (1 << 18) |
| 80 | #define CORE_CDR_EXT_EN (1 << 19) |
| 81 | #define CORE_DLL_PDN (1 << 29) |
| 82 | #define CORE_DLL_RST (1 << 30) |
| 83 | #define CORE_DLL_CONFIG 0x100 |
| 84 | #define CORE_DLL_TEST_CTL 0x104 |
| 85 | #define CORE_DLL_STATUS 0x108 |
| 86 | |
| 87 | #define CORE_VENDOR_SPEC 0x10C |
| 88 | #define CORE_CLK_PWRSAVE (1 << 1) |
Venkat Gopalakrishnan | 7f69157 | 2013-06-23 17:36:46 -0700 | [diff] [blame^] | 89 | #define CORE_HC_MCLK_SEL_DFLT (2 << 8) |
| 90 | #define CORE_HC_MCLK_SEL_HS400 (3 << 8) |
| 91 | #define CORE_HC_MCLK_SEL_MASK (3 << 8) |
Venkat Gopalakrishnan | 7944a37 | 2012-09-11 16:13:31 -0700 | [diff] [blame] | 92 | #define CORE_IO_PAD_PWR_SWITCH (1 << 16) |
Venkat Gopalakrishnan | 7f69157 | 2013-06-23 17:36:46 -0700 | [diff] [blame^] | 93 | #define CORE_HC_SELECT_IN_EN (1 << 18) |
| 94 | #define CORE_HC_SELECT_IN_HS400 (6 << 19) |
| 95 | #define CORE_HC_SELECT_IN_MASK (7 << 19) |
Venkat Gopalakrishnan | 7944a37 | 2012-09-11 16:13:31 -0700 | [diff] [blame] | 96 | |
Sahitya Tummala | 67717bc | 2013-08-02 09:21:37 +0530 | [diff] [blame] | 97 | #define CORE_VENDOR_SPEC_ADMA_ERR_ADDR0 0x114 |
| 98 | #define CORE_VENDOR_SPEC_ADMA_ERR_ADDR1 0x118 |
| 99 | |
| 100 | #define CORE_MCI_DATA_CNT 0x30 |
| 101 | #define CORE_MCI_STATUS 0x34 |
| 102 | #define CORE_MCI_FIFO_CNT 0x44 |
| 103 | |
| 104 | #define CORE_TESTBUS_SEL2_BIT 4 |
| 105 | #define CORE_TESTBUS_SEL2 (1 << CORE_TESTBUS_SEL2_BIT) |
| 106 | |
Asutosh Das | 648f9d1 | 2013-01-10 21:11:04 +0530 | [diff] [blame] | 107 | /* 8KB descriptors */ |
| 108 | #define SDHCI_MSM_MAX_SEGMENTS (1 << 13) |
Sahitya Tummala | a7f3c57 | 2013-01-11 11:30:45 +0530 | [diff] [blame] | 109 | #define SDHCI_MSM_MMC_CLK_GATE_DELAY 200 /* msecs */ |
Asutosh Das | 648f9d1 | 2013-01-10 21:11:04 +0530 | [diff] [blame] | 110 | |
Venkat Gopalakrishnan | 7f69157 | 2013-06-23 17:36:46 -0700 | [diff] [blame^] | 111 | #define CORE_FREQ_100MHZ (100 * 1000 * 1000) |
| 112 | |
Venkat Gopalakrishnan | 7944a37 | 2012-09-11 16:13:31 -0700 | [diff] [blame] | 113 | static const u32 tuning_block_64[] = { |
| 114 | 0x00FF0FFF, 0xCCC3CCFF, 0xFFCC3CC3, 0xEFFEFFFE, |
| 115 | 0xDDFFDFFF, 0xFBFFFBFF, 0xFF7FFFBF, 0xEFBDF777, |
| 116 | 0xF0FFF0FF, 0x3CCCFC0F, 0xCFCC33CC, 0xEEFFEFFF, |
| 117 | 0xFDFFFDFF, 0xFFBFFFDF, 0xFFF7FFBB, 0xDE7B7FF7 |
| 118 | }; |
| 119 | |
| 120 | static const u32 tuning_block_128[] = { |
| 121 | 0xFF00FFFF, 0x0000FFFF, 0xCCCCFFFF, 0xCCCC33CC, |
| 122 | 0xCC3333CC, 0xFFFFCCCC, 0xFFFFEEFF, 0xFFEEEEFF, |
| 123 | 0xFFDDFFFF, 0xDDDDFFFF, 0xBBFFFFFF, 0xBBFFFFFF, |
| 124 | 0xFFFFFFBB, 0xFFFFFF77, 0x77FF7777, 0xFFEEDDBB, |
| 125 | 0x00FFFFFF, 0x00FFFFFF, 0xCCFFFF00, 0xCC33CCCC, |
| 126 | 0x3333CCCC, 0xFFCCCCCC, 0xFFEEFFFF, 0xEEEEFFFF, |
| 127 | 0xDDFFFFFF, 0xDDFFFFFF, 0xFFFFFFDD, 0xFFFFFFBB, |
| 128 | 0xFFFFBBBB, 0xFFFF77FF, 0xFF7777FF, 0xEEDDBB77 |
| 129 | }; |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 130 | |
Venkat Gopalakrishnan | 270580a | 2013-03-11 12:17:57 -0700 | [diff] [blame] | 131 | static int disable_slots; |
| 132 | /* root can write, others read */ |
| 133 | module_param(disable_slots, int, S_IRUGO|S_IWUSR); |
| 134 | |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 135 | /* This structure keeps information per regulator */ |
| 136 | struct sdhci_msm_reg_data { |
| 137 | /* voltage regulator handle */ |
| 138 | struct regulator *reg; |
| 139 | /* regulator name */ |
| 140 | const char *name; |
| 141 | /* voltage level to be set */ |
| 142 | u32 low_vol_level; |
| 143 | u32 high_vol_level; |
| 144 | /* Load values for low power and high power mode */ |
| 145 | u32 lpm_uA; |
| 146 | u32 hpm_uA; |
| 147 | |
| 148 | /* is this regulator enabled? */ |
| 149 | bool is_enabled; |
| 150 | /* is this regulator needs to be always on? */ |
| 151 | bool is_always_on; |
| 152 | /* is low power mode setting required for this regulator? */ |
| 153 | bool lpm_sup; |
| 154 | bool set_voltage_sup; |
| 155 | }; |
| 156 | |
| 157 | /* |
| 158 | * This structure keeps information for all the |
| 159 | * regulators required for a SDCC slot. |
| 160 | */ |
| 161 | struct sdhci_msm_slot_reg_data { |
| 162 | /* keeps VDD/VCC regulator info */ |
| 163 | struct sdhci_msm_reg_data *vdd_data; |
| 164 | /* keeps VDD IO regulator info */ |
| 165 | struct sdhci_msm_reg_data *vdd_io_data; |
| 166 | }; |
| 167 | |
| 168 | struct sdhci_msm_gpio { |
| 169 | u32 no; |
| 170 | const char *name; |
| 171 | bool is_enabled; |
| 172 | }; |
| 173 | |
| 174 | struct sdhci_msm_gpio_data { |
| 175 | struct sdhci_msm_gpio *gpio; |
| 176 | u8 size; |
| 177 | }; |
| 178 | |
| 179 | struct sdhci_msm_pin_data { |
| 180 | /* |
| 181 | * = 1 if controller pins are using gpios |
| 182 | * = 0 if controller has dedicated MSM pads |
| 183 | */ |
| 184 | bool cfg_sts; |
| 185 | struct sdhci_msm_gpio_data *gpio_data; |
| 186 | }; |
| 187 | |
Sahitya Tummala | 8a3e818 | 2013-03-10 14:12:52 +0530 | [diff] [blame] | 188 | struct sdhci_msm_bus_voting_data { |
| 189 | struct msm_bus_scale_pdata *bus_pdata; |
| 190 | unsigned int *bw_vecs; |
| 191 | unsigned int bw_vecs_size; |
| 192 | }; |
| 193 | |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 194 | struct sdhci_msm_pltfm_data { |
| 195 | /* Supported UHS-I Modes */ |
| 196 | u32 caps; |
| 197 | |
| 198 | /* More capabilities */ |
| 199 | u32 caps2; |
| 200 | |
| 201 | unsigned long mmc_bus_width; |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 202 | struct sdhci_msm_slot_reg_data *vreg_data; |
| 203 | bool nonremovable; |
| 204 | struct sdhci_msm_pin_data *pin_data; |
Sahitya Tummala | c6f48d4 | 2013-03-10 07:03:17 +0530 | [diff] [blame] | 205 | u32 cpu_dma_latency_us; |
Sahitya Tummala | 581df13 | 2013-03-12 14:57:46 +0530 | [diff] [blame] | 206 | int status_gpio; /* card detection GPIO that is configured as IRQ */ |
Sahitya Tummala | 8a3e818 | 2013-03-10 14:12:52 +0530 | [diff] [blame] | 207 | struct sdhci_msm_bus_voting_data *voting_data; |
Sahitya Tummala | 22dd336 | 2013-02-28 19:50:51 +0530 | [diff] [blame] | 208 | u32 *sup_clk_table; |
| 209 | unsigned char sup_clk_cnt; |
Sahitya Tummala | 8a3e818 | 2013-03-10 14:12:52 +0530 | [diff] [blame] | 210 | }; |
| 211 | |
| 212 | struct sdhci_msm_bus_vote { |
| 213 | uint32_t client_handle; |
| 214 | uint32_t curr_vote; |
| 215 | int min_bw_vote; |
| 216 | int max_bw_vote; |
| 217 | bool is_max_bw_needed; |
| 218 | struct delayed_work vote_work; |
| 219 | struct device_attribute max_bus_bw; |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 220 | }; |
| 221 | |
| 222 | struct sdhci_msm_host { |
Sahitya Tummala | 8a3e818 | 2013-03-10 14:12:52 +0530 | [diff] [blame] | 223 | struct platform_device *pdev; |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 224 | void __iomem *core_mem; /* MSM SDCC mapped address */ |
| 225 | struct clk *clk; /* main SD/MMC bus clock */ |
| 226 | struct clk *pclk; /* SDHC peripheral bus clock */ |
| 227 | struct clk *bus_clk; /* SDHC bus voter clock */ |
Venkat Gopalakrishnan | 7f69157 | 2013-06-23 17:36:46 -0700 | [diff] [blame^] | 228 | struct clk *ff_clk; /* CDC calibration fixed feedback clock */ |
| 229 | struct clk *sleep_clk; /* CDC calibration sleep clock */ |
Sahitya Tummala | a7f3c57 | 2013-01-11 11:30:45 +0530 | [diff] [blame] | 230 | atomic_t clks_on; /* Set if clocks are enabled */ |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 231 | struct sdhci_msm_pltfm_data *pdata; |
| 232 | struct mmc_host *mmc; |
| 233 | struct sdhci_pltfm_data sdhci_msm_pdata; |
Sahitya Tummala | 1f52eaa | 2013-03-20 19:24:01 +0530 | [diff] [blame] | 234 | u32 curr_pwr_state; |
| 235 | u32 curr_io_level; |
| 236 | struct completion pwr_irq_completion; |
Sahitya Tummala | 8a3e818 | 2013-03-10 14:12:52 +0530 | [diff] [blame] | 237 | struct sdhci_msm_bus_vote msm_bus_vote; |
Sahitya Tummala | 5c55b93 | 2013-06-20 14:00:18 +0530 | [diff] [blame] | 238 | struct device_attribute polling; |
Sahitya Tummala | 22dd336 | 2013-02-28 19:50:51 +0530 | [diff] [blame] | 239 | u32 clk_rate; /* Keeps track of current clock rate that is set */ |
Venkat Gopalakrishnan | 7f69157 | 2013-06-23 17:36:46 -0700 | [diff] [blame^] | 240 | bool tuning_done; |
| 241 | bool calibration_done; |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 242 | }; |
| 243 | |
| 244 | enum vdd_io_level { |
| 245 | /* set vdd_io_data->low_vol_level */ |
| 246 | VDD_IO_LOW, |
| 247 | /* set vdd_io_data->high_vol_level */ |
| 248 | VDD_IO_HIGH, |
| 249 | /* |
| 250 | * set whatever there in voltage_level (third argument) of |
| 251 | * sdhci_msm_set_vdd_io_vol() function. |
| 252 | */ |
| 253 | VDD_IO_SET_LEVEL, |
| 254 | }; |
| 255 | |
Venkat Gopalakrishnan | 7944a37 | 2012-09-11 16:13:31 -0700 | [diff] [blame] | 256 | /* MSM platform specific tuning */ |
| 257 | static inline int msm_dll_poll_ck_out_en(struct sdhci_host *host, |
| 258 | u8 poll) |
| 259 | { |
| 260 | int rc = 0; |
| 261 | u32 wait_cnt = 50; |
| 262 | u8 ck_out_en = 0; |
| 263 | struct mmc_host *mmc = host->mmc; |
| 264 | |
| 265 | /* poll for CK_OUT_EN bit. max. poll time = 50us */ |
| 266 | ck_out_en = !!(readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) & |
| 267 | CORE_CK_OUT_EN); |
| 268 | |
| 269 | while (ck_out_en != poll) { |
| 270 | if (--wait_cnt == 0) { |
| 271 | pr_err("%s: %s: CK_OUT_EN bit is not %d\n", |
| 272 | mmc_hostname(mmc), __func__, poll); |
| 273 | rc = -ETIMEDOUT; |
| 274 | goto out; |
| 275 | } |
| 276 | udelay(1); |
| 277 | |
| 278 | ck_out_en = !!(readl_relaxed(host->ioaddr + |
| 279 | CORE_DLL_CONFIG) & CORE_CK_OUT_EN); |
| 280 | } |
| 281 | out: |
| 282 | return rc; |
| 283 | } |
| 284 | |
| 285 | static int msm_config_cm_dll_phase(struct sdhci_host *host, u8 phase) |
| 286 | { |
| 287 | int rc = 0; |
| 288 | u8 grey_coded_phase_table[] = {0x0, 0x1, 0x3, 0x2, 0x6, 0x7, 0x5, 0x4, |
| 289 | 0xC, 0xD, 0xF, 0xE, 0xA, 0xB, 0x9, |
| 290 | 0x8}; |
| 291 | unsigned long flags; |
| 292 | u32 config; |
| 293 | struct mmc_host *mmc = host->mmc; |
| 294 | |
| 295 | pr_debug("%s: Enter %s\n", mmc_hostname(mmc), __func__); |
| 296 | spin_lock_irqsave(&host->lock, flags); |
| 297 | |
| 298 | config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG); |
| 299 | config &= ~(CORE_CDR_EN | CORE_CK_OUT_EN); |
| 300 | config |= (CORE_CDR_EXT_EN | CORE_DLL_EN); |
| 301 | writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG); |
| 302 | |
| 303 | /* Wait until CK_OUT_EN bit of DLL_CONFIG register becomes '0' */ |
| 304 | rc = msm_dll_poll_ck_out_en(host, 0); |
| 305 | if (rc) |
| 306 | goto err_out; |
| 307 | |
| 308 | /* |
| 309 | * Write the selected DLL clock output phase (0 ... 15) |
| 310 | * to CDR_SELEXT bit field of DLL_CONFIG register. |
| 311 | */ |
| 312 | writel_relaxed(((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) |
| 313 | & ~(0xF << 20)) |
| 314 | | (grey_coded_phase_table[phase] << 20)), |
| 315 | host->ioaddr + CORE_DLL_CONFIG); |
| 316 | |
| 317 | /* Set CK_OUT_EN bit of DLL_CONFIG register to 1. */ |
| 318 | writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) |
| 319 | | CORE_CK_OUT_EN), host->ioaddr + CORE_DLL_CONFIG); |
| 320 | |
| 321 | /* Wait until CK_OUT_EN bit of DLL_CONFIG register becomes '1' */ |
| 322 | rc = msm_dll_poll_ck_out_en(host, 1); |
| 323 | if (rc) |
| 324 | goto err_out; |
| 325 | |
| 326 | config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG); |
| 327 | config |= CORE_CDR_EN; |
| 328 | config &= ~CORE_CDR_EXT_EN; |
| 329 | writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG); |
| 330 | goto out; |
| 331 | |
| 332 | err_out: |
| 333 | pr_err("%s: %s: Failed to set DLL phase: %d\n", |
| 334 | mmc_hostname(mmc), __func__, phase); |
| 335 | out: |
| 336 | spin_unlock_irqrestore(&host->lock, flags); |
| 337 | pr_debug("%s: Exit %s\n", mmc_hostname(mmc), __func__); |
| 338 | return rc; |
| 339 | } |
| 340 | |
| 341 | /* |
| 342 | * Find out the greatest range of consecuitive selected |
| 343 | * DLL clock output phases that can be used as sampling |
| 344 | * setting for SD3.0 UHS-I card read operation (in SDR104 |
Venkat Gopalakrishnan | 7f69157 | 2013-06-23 17:36:46 -0700 | [diff] [blame^] | 345 | * timing mode) or for eMMC4.5 card read operation (in |
| 346 | * HS400/HS200 timing mode). |
Venkat Gopalakrishnan | 7944a37 | 2012-09-11 16:13:31 -0700 | [diff] [blame] | 347 | * Select the 3/4 of the range and configure the DLL with the |
| 348 | * selected DLL clock output phase. |
| 349 | */ |
| 350 | |
| 351 | static int msm_find_most_appropriate_phase(struct sdhci_host *host, |
| 352 | u8 *phase_table, u8 total_phases) |
| 353 | { |
| 354 | int ret; |
| 355 | u8 ranges[MAX_PHASES][MAX_PHASES] = { {0}, {0} }; |
| 356 | u8 phases_per_row[MAX_PHASES] = {0}; |
| 357 | int row_index = 0, col_index = 0, selected_row_index = 0, curr_max = 0; |
| 358 | int i, cnt, phase_0_raw_index = 0, phase_15_raw_index = 0; |
| 359 | bool phase_0_found = false, phase_15_found = false; |
| 360 | struct mmc_host *mmc = host->mmc; |
| 361 | |
| 362 | pr_debug("%s: Enter %s\n", mmc_hostname(mmc), __func__); |
| 363 | if (!total_phases || (total_phases > MAX_PHASES)) { |
| 364 | pr_err("%s: %s: invalid argument: total_phases=%d\n", |
| 365 | mmc_hostname(mmc), __func__, total_phases); |
| 366 | return -EINVAL; |
| 367 | } |
| 368 | |
| 369 | for (cnt = 0; cnt < total_phases; cnt++) { |
| 370 | ranges[row_index][col_index] = phase_table[cnt]; |
| 371 | phases_per_row[row_index] += 1; |
| 372 | col_index++; |
| 373 | |
| 374 | if ((cnt + 1) == total_phases) { |
| 375 | continue; |
| 376 | /* check if next phase in phase_table is consecutive or not */ |
| 377 | } else if ((phase_table[cnt] + 1) != phase_table[cnt + 1]) { |
| 378 | row_index++; |
| 379 | col_index = 0; |
| 380 | } |
| 381 | } |
| 382 | |
| 383 | if (row_index >= MAX_PHASES) |
| 384 | return -EINVAL; |
| 385 | |
| 386 | /* Check if phase-0 is present in first valid window? */ |
| 387 | if (!ranges[0][0]) { |
| 388 | phase_0_found = true; |
| 389 | phase_0_raw_index = 0; |
| 390 | /* Check if cycle exist between 2 valid windows */ |
| 391 | for (cnt = 1; cnt <= row_index; cnt++) { |
| 392 | if (phases_per_row[cnt]) { |
| 393 | for (i = 0; i < phases_per_row[cnt]; i++) { |
| 394 | if (ranges[cnt][i] == 15) { |
| 395 | phase_15_found = true; |
| 396 | phase_15_raw_index = cnt; |
| 397 | break; |
| 398 | } |
| 399 | } |
| 400 | } |
| 401 | } |
| 402 | } |
| 403 | |
| 404 | /* If 2 valid windows form cycle then merge them as single window */ |
| 405 | if (phase_0_found && phase_15_found) { |
| 406 | /* number of phases in raw where phase 0 is present */ |
| 407 | u8 phases_0 = phases_per_row[phase_0_raw_index]; |
| 408 | /* number of phases in raw where phase 15 is present */ |
| 409 | u8 phases_15 = phases_per_row[phase_15_raw_index]; |
| 410 | |
| 411 | if (phases_0 + phases_15 >= MAX_PHASES) |
| 412 | /* |
| 413 | * If there are more than 1 phase windows then total |
| 414 | * number of phases in both the windows should not be |
| 415 | * more than or equal to MAX_PHASES. |
| 416 | */ |
| 417 | return -EINVAL; |
| 418 | |
| 419 | /* Merge 2 cyclic windows */ |
| 420 | i = phases_15; |
| 421 | for (cnt = 0; cnt < phases_0; cnt++) { |
| 422 | ranges[phase_15_raw_index][i] = |
| 423 | ranges[phase_0_raw_index][cnt]; |
| 424 | if (++i >= MAX_PHASES) |
| 425 | break; |
| 426 | } |
| 427 | |
| 428 | phases_per_row[phase_0_raw_index] = 0; |
| 429 | phases_per_row[phase_15_raw_index] = phases_15 + phases_0; |
| 430 | } |
| 431 | |
| 432 | for (cnt = 0; cnt <= row_index; cnt++) { |
| 433 | if (phases_per_row[cnt] > curr_max) { |
| 434 | curr_max = phases_per_row[cnt]; |
| 435 | selected_row_index = cnt; |
| 436 | } |
| 437 | } |
| 438 | |
| 439 | i = ((curr_max * 3) / 4); |
| 440 | if (i) |
| 441 | i--; |
| 442 | |
| 443 | ret = (int)ranges[selected_row_index][i]; |
| 444 | |
| 445 | if (ret >= MAX_PHASES) { |
| 446 | ret = -EINVAL; |
| 447 | pr_err("%s: %s: invalid phase selected=%d\n", |
| 448 | mmc_hostname(mmc), __func__, ret); |
| 449 | } |
| 450 | |
| 451 | pr_debug("%s: Exit %s\n", mmc_hostname(mmc), __func__); |
| 452 | return ret; |
| 453 | } |
| 454 | |
| 455 | static inline void msm_cm_dll_set_freq(struct sdhci_host *host) |
| 456 | { |
| 457 | u32 mclk_freq = 0; |
| 458 | |
| 459 | /* Program the MCLK value to MCLK_FREQ bit field */ |
| 460 | if (host->clock <= 112000000) |
| 461 | mclk_freq = 0; |
| 462 | else if (host->clock <= 125000000) |
| 463 | mclk_freq = 1; |
| 464 | else if (host->clock <= 137000000) |
| 465 | mclk_freq = 2; |
| 466 | else if (host->clock <= 150000000) |
| 467 | mclk_freq = 3; |
| 468 | else if (host->clock <= 162000000) |
| 469 | mclk_freq = 4; |
| 470 | else if (host->clock <= 175000000) |
| 471 | mclk_freq = 5; |
| 472 | else if (host->clock <= 187000000) |
| 473 | mclk_freq = 6; |
| 474 | else if (host->clock <= 200000000) |
| 475 | mclk_freq = 7; |
| 476 | |
| 477 | writel_relaxed(((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) |
| 478 | & ~(7 << 24)) | (mclk_freq << 24)), |
| 479 | host->ioaddr + CORE_DLL_CONFIG); |
| 480 | } |
| 481 | |
| 482 | /* Initialize the DLL (Programmable Delay Line ) */ |
| 483 | static int msm_init_cm_dll(struct sdhci_host *host) |
| 484 | { |
| 485 | struct mmc_host *mmc = host->mmc; |
| 486 | int rc = 0; |
| 487 | unsigned long flags; |
| 488 | u32 wait_cnt; |
Subhash Jadavani | 99bca3b | 2013-05-28 18:21:57 +0530 | [diff] [blame] | 489 | bool prev_pwrsave, curr_pwrsave; |
Venkat Gopalakrishnan | 7944a37 | 2012-09-11 16:13:31 -0700 | [diff] [blame] | 490 | |
| 491 | pr_debug("%s: Enter %s\n", mmc_hostname(mmc), __func__); |
| 492 | spin_lock_irqsave(&host->lock, flags); |
Subhash Jadavani | 99bca3b | 2013-05-28 18:21:57 +0530 | [diff] [blame] | 493 | prev_pwrsave = !!(readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC) & |
| 494 | CORE_CLK_PWRSAVE); |
| 495 | curr_pwrsave = prev_pwrsave; |
Venkat Gopalakrishnan | 7944a37 | 2012-09-11 16:13:31 -0700 | [diff] [blame] | 496 | /* |
| 497 | * Make sure that clock is always enabled when DLL |
| 498 | * tuning is in progress. Keeping PWRSAVE ON may |
| 499 | * turn off the clock. So let's disable the PWRSAVE |
| 500 | * here and re-enable it once tuning is completed. |
| 501 | */ |
Subhash Jadavani | 99bca3b | 2013-05-28 18:21:57 +0530 | [diff] [blame] | 502 | if (prev_pwrsave) { |
| 503 | writel_relaxed((readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC) |
| 504 | & ~CORE_CLK_PWRSAVE), |
| 505 | host->ioaddr + CORE_VENDOR_SPEC); |
| 506 | curr_pwrsave = false; |
| 507 | } |
Venkat Gopalakrishnan | 7944a37 | 2012-09-11 16:13:31 -0700 | [diff] [blame] | 508 | |
| 509 | /* Write 1 to DLL_RST bit of DLL_CONFIG register */ |
| 510 | writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) |
| 511 | | CORE_DLL_RST), host->ioaddr + CORE_DLL_CONFIG); |
| 512 | |
| 513 | /* Write 1 to DLL_PDN bit of DLL_CONFIG register */ |
| 514 | writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) |
| 515 | | CORE_DLL_PDN), host->ioaddr + CORE_DLL_CONFIG); |
| 516 | msm_cm_dll_set_freq(host); |
| 517 | |
| 518 | /* Write 0 to DLL_RST bit of DLL_CONFIG register */ |
| 519 | writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) |
| 520 | & ~CORE_DLL_RST), host->ioaddr + CORE_DLL_CONFIG); |
| 521 | |
| 522 | /* Write 0 to DLL_PDN bit of DLL_CONFIG register */ |
| 523 | writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) |
| 524 | & ~CORE_DLL_PDN), host->ioaddr + CORE_DLL_CONFIG); |
| 525 | |
| 526 | /* Set DLL_EN bit to 1. */ |
| 527 | writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) |
| 528 | | CORE_DLL_EN), host->ioaddr + CORE_DLL_CONFIG); |
| 529 | |
| 530 | /* Set CK_OUT_EN bit to 1. */ |
| 531 | writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) |
| 532 | | CORE_CK_OUT_EN), host->ioaddr + CORE_DLL_CONFIG); |
| 533 | |
| 534 | wait_cnt = 50; |
| 535 | /* Wait until DLL_LOCK bit of DLL_STATUS register becomes '1' */ |
| 536 | while (!(readl_relaxed(host->ioaddr + CORE_DLL_STATUS) & |
| 537 | CORE_DLL_LOCK)) { |
| 538 | /* max. wait for 50us sec for LOCK bit to be set */ |
| 539 | if (--wait_cnt == 0) { |
| 540 | pr_err("%s: %s: DLL failed to LOCK\n", |
| 541 | mmc_hostname(mmc), __func__); |
| 542 | rc = -ETIMEDOUT; |
| 543 | goto out; |
| 544 | } |
| 545 | /* wait for 1us before polling again */ |
| 546 | udelay(1); |
| 547 | } |
| 548 | |
| 549 | out: |
Subhash Jadavani | 99bca3b | 2013-05-28 18:21:57 +0530 | [diff] [blame] | 550 | /* Restore the correct PWRSAVE state */ |
| 551 | if (prev_pwrsave ^ curr_pwrsave) { |
| 552 | u32 reg = readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC); |
| 553 | |
| 554 | if (prev_pwrsave) |
| 555 | reg |= CORE_CLK_PWRSAVE; |
| 556 | else |
| 557 | reg &= ~CORE_CLK_PWRSAVE; |
| 558 | |
| 559 | writel_relaxed(reg, host->ioaddr + CORE_VENDOR_SPEC); |
| 560 | } |
| 561 | |
Venkat Gopalakrishnan | 7944a37 | 2012-09-11 16:13:31 -0700 | [diff] [blame] | 562 | spin_unlock_irqrestore(&host->lock, flags); |
| 563 | pr_debug("%s: Exit %s\n", mmc_hostname(mmc), __func__); |
| 564 | return rc; |
| 565 | } |
| 566 | |
| 567 | int sdhci_msm_execute_tuning(struct sdhci_host *host, u32 opcode) |
| 568 | { |
| 569 | unsigned long flags; |
Sahitya Tummala | 9fe1653 | 2013-06-13 10:36:57 +0530 | [diff] [blame] | 570 | int tuning_seq_cnt = 3; |
Venkat Gopalakrishnan | 7944a37 | 2012-09-11 16:13:31 -0700 | [diff] [blame] | 571 | u8 phase, *data_buf, tuned_phases[16], tuned_phase_cnt = 0; |
| 572 | const u32 *tuning_block_pattern = tuning_block_64; |
| 573 | int size = sizeof(tuning_block_64); /* Tuning pattern size in bytes */ |
| 574 | int rc; |
| 575 | struct mmc_host *mmc = host->mmc; |
Sahitya Tummala | 22dd336 | 2013-02-28 19:50:51 +0530 | [diff] [blame] | 576 | struct mmc_ios ios = host->mmc->ios; |
| 577 | |
| 578 | /* |
Venkat Gopalakrishnan | 7f69157 | 2013-06-23 17:36:46 -0700 | [diff] [blame^] | 579 | * Tuning is required for SDR104, HS200 and HS400 cards and |
| 580 | * if clock frequency is greater than 100MHz in these modes. |
Sahitya Tummala | 22dd336 | 2013-02-28 19:50:51 +0530 | [diff] [blame] | 581 | */ |
Venkat Gopalakrishnan | 7f69157 | 2013-06-23 17:36:46 -0700 | [diff] [blame^] | 582 | if (host->clock <= CORE_FREQ_100MHZ || |
| 583 | !((ios.timing == MMC_TIMING_MMC_HS400) || |
| 584 | (ios.timing == MMC_TIMING_MMC_HS200) || |
| 585 | (ios.timing == MMC_TIMING_UHS_SDR104))) |
Sahitya Tummala | 22dd336 | 2013-02-28 19:50:51 +0530 | [diff] [blame] | 586 | return 0; |
Venkat Gopalakrishnan | 7944a37 | 2012-09-11 16:13:31 -0700 | [diff] [blame] | 587 | |
| 588 | pr_debug("%s: Enter %s\n", mmc_hostname(mmc), __func__); |
Venkat Gopalakrishnan | 7944a37 | 2012-09-11 16:13:31 -0700 | [diff] [blame] | 589 | spin_lock_irqsave(&host->lock, flags); |
| 590 | |
| 591 | if ((opcode == MMC_SEND_TUNING_BLOCK_HS200) && |
| 592 | (mmc->ios.bus_width == MMC_BUS_WIDTH_8)) { |
| 593 | tuning_block_pattern = tuning_block_128; |
| 594 | size = sizeof(tuning_block_128); |
| 595 | } |
| 596 | spin_unlock_irqrestore(&host->lock, flags); |
| 597 | |
Venkat Gopalakrishnan | 7944a37 | 2012-09-11 16:13:31 -0700 | [diff] [blame] | 598 | data_buf = kmalloc(size, GFP_KERNEL); |
| 599 | if (!data_buf) { |
| 600 | rc = -ENOMEM; |
| 601 | goto out; |
| 602 | } |
| 603 | |
Sahitya Tummala | 9fe1653 | 2013-06-13 10:36:57 +0530 | [diff] [blame] | 604 | retry: |
| 605 | /* first of all reset the tuning block */ |
| 606 | rc = msm_init_cm_dll(host); |
| 607 | if (rc) |
| 608 | goto kfree; |
| 609 | |
Venkat Gopalakrishnan | 7944a37 | 2012-09-11 16:13:31 -0700 | [diff] [blame] | 610 | phase = 0; |
| 611 | do { |
| 612 | struct mmc_command cmd = {0}; |
| 613 | struct mmc_data data = {0}; |
| 614 | struct mmc_request mrq = { |
| 615 | .cmd = &cmd, |
| 616 | .data = &data |
| 617 | }; |
| 618 | struct scatterlist sg; |
| 619 | |
| 620 | /* set the phase in delay line hw block */ |
| 621 | rc = msm_config_cm_dll_phase(host, phase); |
| 622 | if (rc) |
| 623 | goto kfree; |
| 624 | |
| 625 | cmd.opcode = opcode; |
| 626 | cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC; |
| 627 | |
| 628 | data.blksz = size; |
| 629 | data.blocks = 1; |
| 630 | data.flags = MMC_DATA_READ; |
| 631 | data.timeout_ns = 1000 * 1000 * 1000; /* 1 sec */ |
| 632 | |
| 633 | data.sg = &sg; |
| 634 | data.sg_len = 1; |
| 635 | sg_init_one(&sg, data_buf, size); |
| 636 | memset(data_buf, 0, size); |
| 637 | mmc_wait_for_req(mmc, &mrq); |
| 638 | |
| 639 | if (!cmd.error && !data.error && |
| 640 | !memcmp(data_buf, tuning_block_pattern, size)) { |
| 641 | /* tuning is successful at this tuning point */ |
| 642 | tuned_phases[tuned_phase_cnt++] = phase; |
| 643 | pr_debug("%s: %s: found good phase = %d\n", |
| 644 | mmc_hostname(mmc), __func__, phase); |
| 645 | } |
| 646 | } while (++phase < 16); |
| 647 | |
| 648 | if (tuned_phase_cnt) { |
| 649 | rc = msm_find_most_appropriate_phase(host, tuned_phases, |
| 650 | tuned_phase_cnt); |
| 651 | if (rc < 0) |
| 652 | goto kfree; |
| 653 | else |
| 654 | phase = (u8)rc; |
| 655 | |
| 656 | /* |
| 657 | * Finally set the selected phase in delay |
| 658 | * line hw block. |
| 659 | */ |
| 660 | rc = msm_config_cm_dll_phase(host, phase); |
| 661 | if (rc) |
| 662 | goto kfree; |
| 663 | pr_debug("%s: %s: finally setting the tuning phase to %d\n", |
| 664 | mmc_hostname(mmc), __func__, phase); |
| 665 | } else { |
Sahitya Tummala | 9fe1653 | 2013-06-13 10:36:57 +0530 | [diff] [blame] | 666 | if (--tuning_seq_cnt) |
| 667 | goto retry; |
Venkat Gopalakrishnan | 7944a37 | 2012-09-11 16:13:31 -0700 | [diff] [blame] | 668 | /* tuning failed */ |
| 669 | pr_err("%s: %s: no tuning point found\n", |
| 670 | mmc_hostname(mmc), __func__); |
Sahitya Tummala | 9fe1653 | 2013-06-13 10:36:57 +0530 | [diff] [blame] | 671 | rc = -EIO; |
Venkat Gopalakrishnan | 7944a37 | 2012-09-11 16:13:31 -0700 | [diff] [blame] | 672 | } |
| 673 | |
| 674 | kfree: |
| 675 | kfree(data_buf); |
| 676 | out: |
| 677 | pr_debug("%s: Exit %s\n", mmc_hostname(mmc), __func__); |
| 678 | return rc; |
| 679 | } |
| 680 | |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 681 | static int sdhci_msm_setup_gpio(struct sdhci_msm_pltfm_data *pdata, bool enable) |
| 682 | { |
| 683 | struct sdhci_msm_gpio_data *curr; |
| 684 | int i, ret = 0; |
| 685 | |
| 686 | curr = pdata->pin_data->gpio_data; |
| 687 | for (i = 0; i < curr->size; i++) { |
| 688 | if (!gpio_is_valid(curr->gpio[i].no)) { |
| 689 | ret = -EINVAL; |
| 690 | pr_err("%s: Invalid gpio = %d\n", __func__, |
| 691 | curr->gpio[i].no); |
| 692 | goto free_gpios; |
| 693 | } |
| 694 | if (enable) { |
| 695 | ret = gpio_request(curr->gpio[i].no, |
| 696 | curr->gpio[i].name); |
| 697 | if (ret) { |
| 698 | pr_err("%s: gpio_request(%d, %s) failed %d\n", |
| 699 | __func__, curr->gpio[i].no, |
| 700 | curr->gpio[i].name, ret); |
| 701 | goto free_gpios; |
| 702 | } |
| 703 | curr->gpio[i].is_enabled = true; |
| 704 | } else { |
| 705 | gpio_free(curr->gpio[i].no); |
| 706 | curr->gpio[i].is_enabled = false; |
| 707 | } |
| 708 | } |
| 709 | return ret; |
| 710 | |
| 711 | free_gpios: |
| 712 | for (i--; i >= 0; i--) { |
| 713 | gpio_free(curr->gpio[i].no); |
| 714 | curr->gpio[i].is_enabled = false; |
| 715 | } |
| 716 | return ret; |
| 717 | } |
| 718 | |
| 719 | static int sdhci_msm_setup_pins(struct sdhci_msm_pltfm_data *pdata, bool enable) |
| 720 | { |
| 721 | int ret = 0; |
| 722 | |
| 723 | if (!pdata->pin_data || (pdata->pin_data->cfg_sts == enable)) |
| 724 | return 0; |
| 725 | |
| 726 | ret = sdhci_msm_setup_gpio(pdata, enable); |
| 727 | if (!ret) |
| 728 | pdata->pin_data->cfg_sts = enable; |
| 729 | |
| 730 | return ret; |
| 731 | } |
| 732 | |
Sahitya Tummala | 8a3e818 | 2013-03-10 14:12:52 +0530 | [diff] [blame] | 733 | static int sdhci_msm_dt_get_array(struct device *dev, const char *prop_name, |
| 734 | u32 **out, int *len, u32 size) |
| 735 | { |
| 736 | int ret = 0; |
| 737 | struct device_node *np = dev->of_node; |
| 738 | size_t sz; |
| 739 | u32 *arr = NULL; |
| 740 | |
| 741 | if (!of_get_property(np, prop_name, len)) { |
| 742 | ret = -EINVAL; |
| 743 | goto out; |
| 744 | } |
| 745 | sz = *len = *len / sizeof(*arr); |
Venkat Gopalakrishnan | 7f69157 | 2013-06-23 17:36:46 -0700 | [diff] [blame^] | 746 | if (sz <= 0 || (size > 0 && (sz > size))) { |
Sahitya Tummala | 8a3e818 | 2013-03-10 14:12:52 +0530 | [diff] [blame] | 747 | dev_err(dev, "%s invalid size\n", prop_name); |
| 748 | ret = -EINVAL; |
| 749 | goto out; |
| 750 | } |
| 751 | |
| 752 | arr = devm_kzalloc(dev, sz * sizeof(*arr), GFP_KERNEL); |
| 753 | if (!arr) { |
| 754 | dev_err(dev, "%s failed allocating memory\n", prop_name); |
| 755 | ret = -ENOMEM; |
| 756 | goto out; |
| 757 | } |
| 758 | |
| 759 | ret = of_property_read_u32_array(np, prop_name, arr, sz); |
| 760 | if (ret < 0) { |
| 761 | dev_err(dev, "%s failed reading array %d\n", prop_name, ret); |
| 762 | goto out; |
| 763 | } |
| 764 | *out = arr; |
| 765 | out: |
| 766 | if (ret) |
| 767 | *len = 0; |
| 768 | return ret; |
| 769 | } |
| 770 | |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 771 | #define MAX_PROP_SIZE 32 |
| 772 | static int sdhci_msm_dt_parse_vreg_info(struct device *dev, |
| 773 | struct sdhci_msm_reg_data **vreg_data, const char *vreg_name) |
| 774 | { |
| 775 | int len, ret = 0; |
| 776 | const __be32 *prop; |
| 777 | char prop_name[MAX_PROP_SIZE]; |
| 778 | struct sdhci_msm_reg_data *vreg; |
| 779 | struct device_node *np = dev->of_node; |
| 780 | |
| 781 | snprintf(prop_name, MAX_PROP_SIZE, "%s-supply", vreg_name); |
| 782 | if (!of_parse_phandle(np, prop_name, 0)) { |
Asutosh Das | c58cc7a | 2013-06-28 15:03:44 +0530 | [diff] [blame] | 783 | dev_info(dev, "No vreg data found for %s\n", vreg_name); |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 784 | return ret; |
| 785 | } |
| 786 | |
| 787 | vreg = devm_kzalloc(dev, sizeof(*vreg), GFP_KERNEL); |
| 788 | if (!vreg) { |
| 789 | dev_err(dev, "No memory for vreg: %s\n", vreg_name); |
| 790 | ret = -ENOMEM; |
| 791 | return ret; |
| 792 | } |
| 793 | |
| 794 | vreg->name = vreg_name; |
| 795 | |
| 796 | snprintf(prop_name, MAX_PROP_SIZE, |
| 797 | "qcom,%s-always-on", vreg_name); |
| 798 | if (of_get_property(np, prop_name, NULL)) |
| 799 | vreg->is_always_on = true; |
| 800 | |
| 801 | snprintf(prop_name, MAX_PROP_SIZE, |
| 802 | "qcom,%s-lpm-sup", vreg_name); |
| 803 | if (of_get_property(np, prop_name, NULL)) |
| 804 | vreg->lpm_sup = true; |
| 805 | |
| 806 | snprintf(prop_name, MAX_PROP_SIZE, |
| 807 | "qcom,%s-voltage-level", vreg_name); |
| 808 | prop = of_get_property(np, prop_name, &len); |
| 809 | if (!prop || (len != (2 * sizeof(__be32)))) { |
| 810 | dev_warn(dev, "%s %s property\n", |
| 811 | prop ? "invalid format" : "no", prop_name); |
| 812 | } else { |
| 813 | vreg->low_vol_level = be32_to_cpup(&prop[0]); |
| 814 | vreg->high_vol_level = be32_to_cpup(&prop[1]); |
| 815 | } |
| 816 | |
| 817 | snprintf(prop_name, MAX_PROP_SIZE, |
| 818 | "qcom,%s-current-level", vreg_name); |
| 819 | prop = of_get_property(np, prop_name, &len); |
| 820 | if (!prop || (len != (2 * sizeof(__be32)))) { |
| 821 | dev_warn(dev, "%s %s property\n", |
| 822 | prop ? "invalid format" : "no", prop_name); |
| 823 | } else { |
| 824 | vreg->lpm_uA = be32_to_cpup(&prop[0]); |
| 825 | vreg->hpm_uA = be32_to_cpup(&prop[1]); |
| 826 | } |
| 827 | |
| 828 | *vreg_data = vreg; |
| 829 | dev_dbg(dev, "%s: %s %s vol=[%d %d]uV, curr=[%d %d]uA\n", |
| 830 | vreg->name, vreg->is_always_on ? "always_on," : "", |
| 831 | vreg->lpm_sup ? "lpm_sup," : "", vreg->low_vol_level, |
| 832 | vreg->high_vol_level, vreg->lpm_uA, vreg->hpm_uA); |
| 833 | |
| 834 | return ret; |
| 835 | } |
| 836 | |
| 837 | #define GPIO_NAME_MAX_LEN 32 |
| 838 | static int sdhci_msm_dt_parse_gpio_info(struct device *dev, |
| 839 | struct sdhci_msm_pltfm_data *pdata) |
| 840 | { |
| 841 | int ret = 0, cnt, i; |
| 842 | struct sdhci_msm_pin_data *pin_data; |
| 843 | struct device_node *np = dev->of_node; |
| 844 | |
| 845 | pin_data = devm_kzalloc(dev, sizeof(*pin_data), GFP_KERNEL); |
| 846 | if (!pin_data) { |
| 847 | dev_err(dev, "No memory for pin_data\n"); |
| 848 | ret = -ENOMEM; |
| 849 | goto out; |
| 850 | } |
| 851 | |
| 852 | cnt = of_gpio_count(np); |
| 853 | if (cnt > 0) { |
| 854 | pin_data->gpio_data = devm_kzalloc(dev, |
| 855 | sizeof(struct sdhci_msm_gpio_data), GFP_KERNEL); |
| 856 | if (!pin_data->gpio_data) { |
| 857 | dev_err(dev, "No memory for gpio_data\n"); |
| 858 | ret = -ENOMEM; |
| 859 | goto out; |
| 860 | } |
| 861 | pin_data->gpio_data->size = cnt; |
| 862 | pin_data->gpio_data->gpio = devm_kzalloc(dev, cnt * |
| 863 | sizeof(struct sdhci_msm_gpio), GFP_KERNEL); |
| 864 | |
| 865 | if (!pin_data->gpio_data->gpio) { |
| 866 | dev_err(dev, "No memory for gpio\n"); |
| 867 | ret = -ENOMEM; |
| 868 | goto out; |
| 869 | } |
| 870 | |
| 871 | for (i = 0; i < cnt; i++) { |
| 872 | const char *name = NULL; |
| 873 | char result[GPIO_NAME_MAX_LEN]; |
| 874 | pin_data->gpio_data->gpio[i].no = of_get_gpio(np, i); |
| 875 | of_property_read_string_index(np, |
| 876 | "qcom,gpio-names", i, &name); |
| 877 | |
| 878 | snprintf(result, GPIO_NAME_MAX_LEN, "%s-%s", |
| 879 | dev_name(dev), name ? name : "?"); |
| 880 | pin_data->gpio_data->gpio[i].name = result; |
| 881 | dev_dbg(dev, "%s: gpio[%s] = %d\n", __func__, |
| 882 | pin_data->gpio_data->gpio[i].name, |
| 883 | pin_data->gpio_data->gpio[i].no); |
| 884 | pdata->pin_data = pin_data; |
| 885 | } |
| 886 | } |
| 887 | |
| 888 | out: |
| 889 | if (ret) |
| 890 | dev_err(dev, "%s failed with err %d\n", __func__, ret); |
| 891 | return ret; |
| 892 | } |
| 893 | |
| 894 | /* Parse platform data */ |
| 895 | static struct sdhci_msm_pltfm_data *sdhci_msm_populate_pdata(struct device *dev) |
| 896 | { |
| 897 | struct sdhci_msm_pltfm_data *pdata = NULL; |
| 898 | struct device_node *np = dev->of_node; |
| 899 | u32 bus_width = 0; |
Sahitya Tummala | c6f48d4 | 2013-03-10 07:03:17 +0530 | [diff] [blame] | 900 | u32 cpu_dma_latency; |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 901 | int len, i; |
Sahitya Tummala | 22dd336 | 2013-02-28 19:50:51 +0530 | [diff] [blame] | 902 | int clk_table_len; |
| 903 | u32 *clk_table = NULL; |
Sujit Reddy Thumma | 1958d3d | 2013-06-03 09:54:32 +0530 | [diff] [blame] | 904 | enum of_gpio_flags flags = OF_GPIO_ACTIVE_LOW; |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 905 | |
| 906 | pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); |
| 907 | if (!pdata) { |
| 908 | dev_err(dev, "failed to allocate memory for platform data\n"); |
| 909 | goto out; |
| 910 | } |
| 911 | |
Sujit Reddy Thumma | 1958d3d | 2013-06-03 09:54:32 +0530 | [diff] [blame] | 912 | pdata->status_gpio = of_get_named_gpio_flags(np, "cd-gpios", 0, &flags); |
| 913 | if (gpio_is_valid(pdata->status_gpio) & !(flags & OF_GPIO_ACTIVE_LOW)) |
| 914 | pdata->caps2 |= MMC_CAP2_CD_ACTIVE_HIGH; |
Sahitya Tummala | 581df13 | 2013-03-12 14:57:46 +0530 | [diff] [blame] | 915 | |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 916 | of_property_read_u32(np, "qcom,bus-width", &bus_width); |
| 917 | if (bus_width == 8) |
| 918 | pdata->mmc_bus_width = MMC_CAP_8_BIT_DATA; |
| 919 | else if (bus_width == 4) |
| 920 | pdata->mmc_bus_width = MMC_CAP_4_BIT_DATA; |
| 921 | else { |
| 922 | dev_notice(dev, "invalid bus-width, default to 1-bit mode\n"); |
| 923 | pdata->mmc_bus_width = 0; |
| 924 | } |
| 925 | |
Sahitya Tummala | c6f48d4 | 2013-03-10 07:03:17 +0530 | [diff] [blame] | 926 | if (!of_property_read_u32(np, "qcom,cpu-dma-latency-us", |
| 927 | &cpu_dma_latency)) |
| 928 | pdata->cpu_dma_latency_us = cpu_dma_latency; |
| 929 | |
Sahitya Tummala | 22dd336 | 2013-02-28 19:50:51 +0530 | [diff] [blame] | 930 | if (sdhci_msm_dt_get_array(dev, "qcom,clk-rates", |
| 931 | &clk_table, &clk_table_len, 0)) { |
| 932 | dev_err(dev, "failed parsing supported clock rates\n"); |
| 933 | goto out; |
| 934 | } |
| 935 | if (!clk_table || !clk_table_len) { |
| 936 | dev_err(dev, "Invalid clock table\n"); |
| 937 | goto out; |
| 938 | } |
| 939 | pdata->sup_clk_table = clk_table; |
| 940 | pdata->sup_clk_cnt = clk_table_len; |
| 941 | |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 942 | pdata->vreg_data = devm_kzalloc(dev, sizeof(struct |
| 943 | sdhci_msm_slot_reg_data), |
| 944 | GFP_KERNEL); |
| 945 | if (!pdata->vreg_data) { |
| 946 | dev_err(dev, "failed to allocate memory for vreg data\n"); |
| 947 | goto out; |
| 948 | } |
| 949 | |
| 950 | if (sdhci_msm_dt_parse_vreg_info(dev, &pdata->vreg_data->vdd_data, |
| 951 | "vdd")) { |
| 952 | dev_err(dev, "failed parsing vdd data\n"); |
| 953 | goto out; |
| 954 | } |
| 955 | if (sdhci_msm_dt_parse_vreg_info(dev, |
| 956 | &pdata->vreg_data->vdd_io_data, |
| 957 | "vdd-io")) { |
| 958 | dev_err(dev, "failed parsing vdd-io data\n"); |
| 959 | goto out; |
| 960 | } |
| 961 | |
| 962 | if (sdhci_msm_dt_parse_gpio_info(dev, pdata)) { |
| 963 | dev_err(dev, "failed parsing gpio data\n"); |
| 964 | goto out; |
| 965 | } |
| 966 | |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 967 | len = of_property_count_strings(np, "qcom,bus-speed-mode"); |
| 968 | |
| 969 | for (i = 0; i < len; i++) { |
| 970 | const char *name = NULL; |
| 971 | |
| 972 | of_property_read_string_index(np, |
| 973 | "qcom,bus-speed-mode", i, &name); |
| 974 | if (!name) |
| 975 | continue; |
| 976 | |
Venkat Gopalakrishnan | 7f69157 | 2013-06-23 17:36:46 -0700 | [diff] [blame^] | 977 | if (!strncmp(name, "HS400_1p8v", sizeof("HS400_1p8v"))) |
| 978 | pdata->caps2 |= MMC_CAP2_HS400_1_8V; |
| 979 | else if (!strncmp(name, "HS400_1p2v", sizeof("HS400_1p2v"))) |
| 980 | pdata->caps2 |= MMC_CAP2_HS400_1_2V; |
| 981 | else if (!strncmp(name, "HS200_1p8v", sizeof("HS200_1p8v"))) |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 982 | pdata->caps2 |= MMC_CAP2_HS200_1_8V_SDR; |
| 983 | else if (!strncmp(name, "HS200_1p2v", sizeof("HS200_1p2v"))) |
| 984 | pdata->caps2 |= MMC_CAP2_HS200_1_2V_SDR; |
| 985 | else if (!strncmp(name, "DDR_1p8v", sizeof("DDR_1p8v"))) |
| 986 | pdata->caps |= MMC_CAP_1_8V_DDR |
| 987 | | MMC_CAP_UHS_DDR50; |
| 988 | else if (!strncmp(name, "DDR_1p2v", sizeof("DDR_1p2v"))) |
| 989 | pdata->caps |= MMC_CAP_1_2V_DDR |
| 990 | | MMC_CAP_UHS_DDR50; |
| 991 | } |
| 992 | |
| 993 | if (of_get_property(np, "qcom,nonremovable", NULL)) |
| 994 | pdata->nonremovable = true; |
| 995 | |
| 996 | return pdata; |
| 997 | out: |
| 998 | return NULL; |
| 999 | } |
| 1000 | |
Sahitya Tummala | 8a3e818 | 2013-03-10 14:12:52 +0530 | [diff] [blame] | 1001 | /* Returns required bandwidth in Bytes per Sec */ |
| 1002 | static unsigned int sdhci_get_bw_required(struct sdhci_host *host, |
| 1003 | struct mmc_ios *ios) |
| 1004 | { |
Sahitya Tummala | 2886c92 | 2013-04-03 18:03:31 +0530 | [diff] [blame] | 1005 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
| 1006 | struct sdhci_msm_host *msm_host = pltfm_host->priv; |
| 1007 | |
Sahitya Tummala | 8a3e818 | 2013-03-10 14:12:52 +0530 | [diff] [blame] | 1008 | unsigned int bw; |
| 1009 | |
Sahitya Tummala | 2886c92 | 2013-04-03 18:03:31 +0530 | [diff] [blame] | 1010 | bw = msm_host->clk_rate; |
Sahitya Tummala | 8a3e818 | 2013-03-10 14:12:52 +0530 | [diff] [blame] | 1011 | /* |
| 1012 | * For DDR mode, SDCC controller clock will be at |
| 1013 | * the double rate than the actual clock that goes to card. |
| 1014 | */ |
| 1015 | if (ios->bus_width == MMC_BUS_WIDTH_4) |
| 1016 | bw /= 2; |
| 1017 | else if (ios->bus_width == MMC_BUS_WIDTH_1) |
| 1018 | bw /= 8; |
| 1019 | |
| 1020 | return bw; |
| 1021 | } |
| 1022 | |
| 1023 | static int sdhci_msm_bus_get_vote_for_bw(struct sdhci_msm_host *host, |
| 1024 | unsigned int bw) |
| 1025 | { |
| 1026 | unsigned int *table = host->pdata->voting_data->bw_vecs; |
| 1027 | unsigned int size = host->pdata->voting_data->bw_vecs_size; |
| 1028 | int i; |
| 1029 | |
| 1030 | if (host->msm_bus_vote.is_max_bw_needed && bw) |
| 1031 | return host->msm_bus_vote.max_bw_vote; |
| 1032 | |
| 1033 | for (i = 0; i < size; i++) { |
| 1034 | if (bw <= table[i]) |
| 1035 | break; |
| 1036 | } |
| 1037 | |
| 1038 | if (i && (i == size)) |
| 1039 | i--; |
| 1040 | |
| 1041 | return i; |
| 1042 | } |
| 1043 | |
| 1044 | /* |
| 1045 | * This function must be called with host lock acquired. |
| 1046 | * Caller of this function should also ensure that msm bus client |
| 1047 | * handle is not null. |
| 1048 | */ |
| 1049 | static inline int sdhci_msm_bus_set_vote(struct sdhci_msm_host *msm_host, |
| 1050 | int vote, |
Sujit Reddy Thumma | 024c058 | 2013-08-06 11:21:33 +0530 | [diff] [blame] | 1051 | unsigned long *flags) |
Sahitya Tummala | 8a3e818 | 2013-03-10 14:12:52 +0530 | [diff] [blame] | 1052 | { |
| 1053 | struct sdhci_host *host = platform_get_drvdata(msm_host->pdev); |
| 1054 | int rc = 0; |
| 1055 | |
Sujit Reddy Thumma | 024c058 | 2013-08-06 11:21:33 +0530 | [diff] [blame] | 1056 | BUG_ON(!flags); |
| 1057 | |
Sahitya Tummala | 8a3e818 | 2013-03-10 14:12:52 +0530 | [diff] [blame] | 1058 | if (vote != msm_host->msm_bus_vote.curr_vote) { |
Sujit Reddy Thumma | 024c058 | 2013-08-06 11:21:33 +0530 | [diff] [blame] | 1059 | spin_unlock_irqrestore(&host->lock, *flags); |
Sahitya Tummala | 8a3e818 | 2013-03-10 14:12:52 +0530 | [diff] [blame] | 1060 | rc = msm_bus_scale_client_update_request( |
| 1061 | msm_host->msm_bus_vote.client_handle, vote); |
Sujit Reddy Thumma | 024c058 | 2013-08-06 11:21:33 +0530 | [diff] [blame] | 1062 | spin_lock_irqsave(&host->lock, *flags); |
Sahitya Tummala | 8a3e818 | 2013-03-10 14:12:52 +0530 | [diff] [blame] | 1063 | if (rc) { |
| 1064 | pr_err("%s: msm_bus_scale_client_update_request() failed: bus_client_handle=0x%x, vote=%d, err=%d\n", |
| 1065 | mmc_hostname(host->mmc), |
| 1066 | msm_host->msm_bus_vote.client_handle, vote, rc); |
| 1067 | goto out; |
| 1068 | } |
| 1069 | msm_host->msm_bus_vote.curr_vote = vote; |
| 1070 | } |
| 1071 | out: |
| 1072 | return rc; |
| 1073 | } |
| 1074 | |
| 1075 | /* |
| 1076 | * Internal work. Work to set 0 bandwidth for msm bus. |
| 1077 | */ |
| 1078 | static void sdhci_msm_bus_work(struct work_struct *work) |
| 1079 | { |
| 1080 | struct sdhci_msm_host *msm_host; |
| 1081 | struct sdhci_host *host; |
| 1082 | unsigned long flags; |
| 1083 | |
| 1084 | msm_host = container_of(work, struct sdhci_msm_host, |
| 1085 | msm_bus_vote.vote_work.work); |
| 1086 | host = platform_get_drvdata(msm_host->pdev); |
| 1087 | |
| 1088 | if (!msm_host->msm_bus_vote.client_handle) |
| 1089 | return; |
| 1090 | |
| 1091 | spin_lock_irqsave(&host->lock, flags); |
| 1092 | /* don't vote for 0 bandwidth if any request is in progress */ |
| 1093 | if (!host->mrq) { |
| 1094 | sdhci_msm_bus_set_vote(msm_host, |
Sujit Reddy Thumma | 024c058 | 2013-08-06 11:21:33 +0530 | [diff] [blame] | 1095 | msm_host->msm_bus_vote.min_bw_vote, &flags); |
Sahitya Tummala | 8a3e818 | 2013-03-10 14:12:52 +0530 | [diff] [blame] | 1096 | } else |
| 1097 | pr_warning("%s: %s: Transfer in progress. skipping bus voting to 0 bandwidth\n", |
| 1098 | mmc_hostname(host->mmc), __func__); |
| 1099 | spin_unlock_irqrestore(&host->lock, flags); |
| 1100 | } |
| 1101 | |
| 1102 | /* |
| 1103 | * This function cancels any scheduled delayed work and sets the bus |
| 1104 | * vote based on bw (bandwidth) argument. |
| 1105 | */ |
| 1106 | static void sdhci_msm_bus_cancel_work_and_set_vote(struct sdhci_host *host, |
| 1107 | unsigned int bw) |
| 1108 | { |
| 1109 | int vote; |
| 1110 | unsigned long flags; |
| 1111 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
| 1112 | struct sdhci_msm_host *msm_host = pltfm_host->priv; |
| 1113 | |
| 1114 | cancel_delayed_work_sync(&msm_host->msm_bus_vote.vote_work); |
| 1115 | spin_lock_irqsave(&host->lock, flags); |
| 1116 | vote = sdhci_msm_bus_get_vote_for_bw(msm_host, bw); |
Sujit Reddy Thumma | 024c058 | 2013-08-06 11:21:33 +0530 | [diff] [blame] | 1117 | sdhci_msm_bus_set_vote(msm_host, vote, &flags); |
Sahitya Tummala | 8a3e818 | 2013-03-10 14:12:52 +0530 | [diff] [blame] | 1118 | spin_unlock_irqrestore(&host->lock, flags); |
| 1119 | } |
| 1120 | |
| 1121 | #define MSM_MMC_BUS_VOTING_DELAY 200 /* msecs */ |
| 1122 | |
| 1123 | /* This function queues a work which will set the bandwidth requiement to 0 */ |
| 1124 | static void sdhci_msm_bus_queue_work(struct sdhci_host *host) |
| 1125 | { |
| 1126 | unsigned long flags; |
| 1127 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
| 1128 | struct sdhci_msm_host *msm_host = pltfm_host->priv; |
| 1129 | |
| 1130 | spin_lock_irqsave(&host->lock, flags); |
| 1131 | if (msm_host->msm_bus_vote.min_bw_vote != |
| 1132 | msm_host->msm_bus_vote.curr_vote) |
| 1133 | queue_delayed_work(system_wq, |
| 1134 | &msm_host->msm_bus_vote.vote_work, |
| 1135 | msecs_to_jiffies(MSM_MMC_BUS_VOTING_DELAY)); |
| 1136 | spin_unlock_irqrestore(&host->lock, flags); |
| 1137 | } |
| 1138 | |
| 1139 | static int sdhci_msm_bus_register(struct sdhci_msm_host *host, |
| 1140 | struct platform_device *pdev) |
| 1141 | { |
| 1142 | int rc = 0; |
| 1143 | struct msm_bus_scale_pdata *bus_pdata; |
| 1144 | |
| 1145 | struct sdhci_msm_bus_voting_data *data; |
| 1146 | struct device *dev = &pdev->dev; |
| 1147 | |
| 1148 | data = devm_kzalloc(dev, |
| 1149 | sizeof(struct sdhci_msm_bus_voting_data), GFP_KERNEL); |
| 1150 | if (!data) { |
| 1151 | dev_err(&pdev->dev, |
| 1152 | "%s: failed to allocate memory\n", __func__); |
| 1153 | rc = -ENOMEM; |
| 1154 | goto out; |
| 1155 | } |
| 1156 | data->bus_pdata = msm_bus_cl_get_pdata(pdev); |
| 1157 | if (data->bus_pdata) { |
| 1158 | rc = sdhci_msm_dt_get_array(dev, "qcom,bus-bw-vectors-bps", |
| 1159 | &data->bw_vecs, &data->bw_vecs_size, 0); |
| 1160 | if (rc) { |
| 1161 | dev_err(&pdev->dev, |
| 1162 | "%s: Failed to get bus-bw-vectors-bps\n", |
| 1163 | __func__); |
| 1164 | goto out; |
| 1165 | } |
| 1166 | host->pdata->voting_data = data; |
| 1167 | } |
| 1168 | if (host->pdata->voting_data && |
| 1169 | host->pdata->voting_data->bus_pdata && |
| 1170 | host->pdata->voting_data->bw_vecs && |
| 1171 | host->pdata->voting_data->bw_vecs_size) { |
| 1172 | |
| 1173 | bus_pdata = host->pdata->voting_data->bus_pdata; |
| 1174 | host->msm_bus_vote.client_handle = |
| 1175 | msm_bus_scale_register_client(bus_pdata); |
| 1176 | if (!host->msm_bus_vote.client_handle) { |
| 1177 | dev_err(&pdev->dev, "msm_bus_scale_register_client()\n"); |
| 1178 | rc = -EFAULT; |
| 1179 | goto out; |
| 1180 | } |
| 1181 | /* cache the vote index for minimum and maximum bandwidth */ |
| 1182 | host->msm_bus_vote.min_bw_vote = |
| 1183 | sdhci_msm_bus_get_vote_for_bw(host, 0); |
| 1184 | host->msm_bus_vote.max_bw_vote = |
| 1185 | sdhci_msm_bus_get_vote_for_bw(host, UINT_MAX); |
| 1186 | } else { |
| 1187 | devm_kfree(dev, data); |
| 1188 | } |
| 1189 | |
| 1190 | out: |
| 1191 | return rc; |
| 1192 | } |
| 1193 | |
| 1194 | static void sdhci_msm_bus_unregister(struct sdhci_msm_host *host) |
| 1195 | { |
| 1196 | if (host->msm_bus_vote.client_handle) |
| 1197 | msm_bus_scale_unregister_client( |
| 1198 | host->msm_bus_vote.client_handle); |
| 1199 | } |
| 1200 | |
| 1201 | static void sdhci_msm_bus_voting(struct sdhci_host *host, u32 enable) |
| 1202 | { |
| 1203 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
| 1204 | struct sdhci_msm_host *msm_host = pltfm_host->priv; |
| 1205 | struct mmc_ios *ios = &host->mmc->ios; |
| 1206 | unsigned int bw; |
| 1207 | |
| 1208 | if (!msm_host->msm_bus_vote.client_handle) |
| 1209 | return; |
| 1210 | |
| 1211 | bw = sdhci_get_bw_required(host, ios); |
Sahitya Tummala | 79edc6a | 2013-05-23 15:59:22 +0530 | [diff] [blame] | 1212 | if (enable) { |
Sahitya Tummala | 8a3e818 | 2013-03-10 14:12:52 +0530 | [diff] [blame] | 1213 | sdhci_msm_bus_cancel_work_and_set_vote(host, bw); |
Sahitya Tummala | 79edc6a | 2013-05-23 15:59:22 +0530 | [diff] [blame] | 1214 | } else { |
| 1215 | /* |
| 1216 | * If clock gating is enabled, then remove the vote |
| 1217 | * immediately because clocks will be disabled only |
| 1218 | * after SDHCI_MSM_MMC_CLK_GATE_DELAY and thus no |
| 1219 | * additional delay is required to remove the bus vote. |
| 1220 | */ |
| 1221 | #ifdef CONFIG_MMC_CLKGATE |
| 1222 | if (host->mmc->clkgate_delay) |
| 1223 | sdhci_msm_bus_cancel_work_and_set_vote(host, 0); |
| 1224 | else |
| 1225 | #endif |
| 1226 | sdhci_msm_bus_queue_work(host); |
| 1227 | } |
Sahitya Tummala | 8a3e818 | 2013-03-10 14:12:52 +0530 | [diff] [blame] | 1228 | } |
| 1229 | |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 1230 | /* Regulator utility functions */ |
| 1231 | static int sdhci_msm_vreg_init_reg(struct device *dev, |
| 1232 | struct sdhci_msm_reg_data *vreg) |
| 1233 | { |
| 1234 | int ret = 0; |
| 1235 | |
| 1236 | /* check if regulator is already initialized? */ |
| 1237 | if (vreg->reg) |
| 1238 | goto out; |
| 1239 | |
| 1240 | /* Get the regulator handle */ |
| 1241 | vreg->reg = devm_regulator_get(dev, vreg->name); |
| 1242 | if (IS_ERR(vreg->reg)) { |
| 1243 | ret = PTR_ERR(vreg->reg); |
| 1244 | pr_err("%s: devm_regulator_get(%s) failed. ret=%d\n", |
| 1245 | __func__, vreg->name, ret); |
| 1246 | goto out; |
| 1247 | } |
| 1248 | |
Asutosh Das | c58cc7a | 2013-06-28 15:03:44 +0530 | [diff] [blame] | 1249 | if (regulator_count_voltages(vreg->reg) > 0) { |
| 1250 | vreg->set_voltage_sup = true; |
| 1251 | /* sanity check */ |
| 1252 | if (!vreg->high_vol_level || !vreg->hpm_uA) { |
| 1253 | pr_err("%s: %s invalid constraints specified\n", |
| 1254 | __func__, vreg->name); |
| 1255 | ret = -EINVAL; |
| 1256 | } |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 1257 | } |
| 1258 | |
| 1259 | out: |
| 1260 | return ret; |
| 1261 | } |
| 1262 | |
| 1263 | static void sdhci_msm_vreg_deinit_reg(struct sdhci_msm_reg_data *vreg) |
| 1264 | { |
| 1265 | if (vreg->reg) |
| 1266 | devm_regulator_put(vreg->reg); |
| 1267 | } |
| 1268 | |
| 1269 | static int sdhci_msm_vreg_set_optimum_mode(struct sdhci_msm_reg_data |
| 1270 | *vreg, int uA_load) |
| 1271 | { |
| 1272 | int ret = 0; |
| 1273 | |
| 1274 | /* |
| 1275 | * regulators that do not support regulator_set_voltage also |
| 1276 | * do not support regulator_set_optimum_mode |
| 1277 | */ |
| 1278 | if (vreg->set_voltage_sup) { |
| 1279 | ret = regulator_set_load(vreg->reg, uA_load); |
| 1280 | if (ret < 0) |
| 1281 | pr_err("%s: regulator_set_load(reg=%s,uA_load=%d) failed. ret=%d\n", |
| 1282 | __func__, vreg->name, uA_load, ret); |
| 1283 | else |
| 1284 | /* |
| 1285 | * regulator_set_load() can return non zero |
| 1286 | * value even for success case. |
| 1287 | */ |
| 1288 | ret = 0; |
| 1289 | } |
| 1290 | return ret; |
| 1291 | } |
| 1292 | |
| 1293 | static int sdhci_msm_vreg_set_voltage(struct sdhci_msm_reg_data *vreg, |
| 1294 | int min_uV, int max_uV) |
| 1295 | { |
| 1296 | int ret = 0; |
Asutosh Das | c58cc7a | 2013-06-28 15:03:44 +0530 | [diff] [blame] | 1297 | if (vreg->set_voltage_sup) { |
| 1298 | ret = regulator_set_voltage(vreg->reg, min_uV, max_uV); |
| 1299 | if (ret) { |
| 1300 | pr_err("%s: regulator_set_voltage(%s)failed. min_uV=%d,max_uV=%d,ret=%d\n", |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 1301 | __func__, vreg->name, min_uV, max_uV, ret); |
| 1302 | } |
Asutosh Das | c58cc7a | 2013-06-28 15:03:44 +0530 | [diff] [blame] | 1303 | } |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 1304 | |
| 1305 | return ret; |
| 1306 | } |
| 1307 | |
| 1308 | static int sdhci_msm_vreg_enable(struct sdhci_msm_reg_data *vreg) |
| 1309 | { |
| 1310 | int ret = 0; |
| 1311 | |
| 1312 | /* Put regulator in HPM (high power mode) */ |
| 1313 | ret = sdhci_msm_vreg_set_optimum_mode(vreg, vreg->hpm_uA); |
| 1314 | if (ret < 0) |
| 1315 | return ret; |
| 1316 | |
| 1317 | if (!vreg->is_enabled) { |
| 1318 | /* Set voltage level */ |
| 1319 | ret = sdhci_msm_vreg_set_voltage(vreg, vreg->high_vol_level, |
| 1320 | vreg->high_vol_level); |
| 1321 | if (ret) |
| 1322 | return ret; |
| 1323 | } |
| 1324 | ret = regulator_enable(vreg->reg); |
| 1325 | if (ret) { |
| 1326 | pr_err("%s: regulator_enable(%s) failed. ret=%d\n", |
| 1327 | __func__, vreg->name, ret); |
| 1328 | return ret; |
| 1329 | } |
| 1330 | vreg->is_enabled = true; |
| 1331 | return ret; |
| 1332 | } |
| 1333 | |
| 1334 | static int sdhci_msm_vreg_disable(struct sdhci_msm_reg_data *vreg) |
| 1335 | { |
| 1336 | int ret = 0; |
| 1337 | |
| 1338 | /* Never disable regulator marked as always_on */ |
| 1339 | if (vreg->is_enabled && !vreg->is_always_on) { |
| 1340 | ret = regulator_disable(vreg->reg); |
| 1341 | if (ret) { |
| 1342 | pr_err("%s: regulator_disable(%s) failed. ret=%d\n", |
| 1343 | __func__, vreg->name, ret); |
| 1344 | goto out; |
| 1345 | } |
| 1346 | vreg->is_enabled = false; |
| 1347 | |
| 1348 | ret = sdhci_msm_vreg_set_optimum_mode(vreg, 0); |
| 1349 | if (ret < 0) |
| 1350 | goto out; |
| 1351 | |
| 1352 | /* Set min. voltage level to 0 */ |
| 1353 | ret = sdhci_msm_vreg_set_voltage(vreg, 0, vreg->high_vol_level); |
| 1354 | if (ret) |
| 1355 | goto out; |
| 1356 | } else if (vreg->is_enabled && vreg->is_always_on) { |
| 1357 | if (vreg->lpm_sup) { |
| 1358 | /* Put always_on regulator in LPM (low power mode) */ |
| 1359 | ret = sdhci_msm_vreg_set_optimum_mode(vreg, |
| 1360 | vreg->lpm_uA); |
| 1361 | if (ret < 0) |
| 1362 | goto out; |
| 1363 | } |
| 1364 | } |
| 1365 | out: |
| 1366 | return ret; |
| 1367 | } |
| 1368 | |
| 1369 | static int sdhci_msm_setup_vreg(struct sdhci_msm_pltfm_data *pdata, |
| 1370 | bool enable, bool is_init) |
| 1371 | { |
| 1372 | int ret = 0, i; |
| 1373 | struct sdhci_msm_slot_reg_data *curr_slot; |
| 1374 | struct sdhci_msm_reg_data *vreg_table[2]; |
| 1375 | |
| 1376 | curr_slot = pdata->vreg_data; |
| 1377 | if (!curr_slot) { |
| 1378 | pr_debug("%s: vreg info unavailable,assuming the slot is powered by always on domain\n", |
| 1379 | __func__); |
| 1380 | goto out; |
| 1381 | } |
| 1382 | |
| 1383 | vreg_table[0] = curr_slot->vdd_data; |
| 1384 | vreg_table[1] = curr_slot->vdd_io_data; |
| 1385 | |
| 1386 | for (i = 0; i < ARRAY_SIZE(vreg_table); i++) { |
| 1387 | if (vreg_table[i]) { |
| 1388 | if (enable) |
| 1389 | ret = sdhci_msm_vreg_enable(vreg_table[i]); |
| 1390 | else |
| 1391 | ret = sdhci_msm_vreg_disable(vreg_table[i]); |
| 1392 | if (ret) |
| 1393 | goto out; |
| 1394 | } |
| 1395 | } |
| 1396 | out: |
| 1397 | return ret; |
| 1398 | } |
| 1399 | |
| 1400 | /* |
| 1401 | * Reset vreg by ensuring it is off during probe. A call |
| 1402 | * to enable vreg is needed to balance disable vreg |
| 1403 | */ |
| 1404 | static int sdhci_msm_vreg_reset(struct sdhci_msm_pltfm_data *pdata) |
| 1405 | { |
| 1406 | int ret; |
| 1407 | |
| 1408 | ret = sdhci_msm_setup_vreg(pdata, 1, true); |
| 1409 | if (ret) |
| 1410 | return ret; |
| 1411 | ret = sdhci_msm_setup_vreg(pdata, 0, true); |
| 1412 | return ret; |
| 1413 | } |
| 1414 | |
| 1415 | /* This init function should be called only once for each SDHC slot */ |
| 1416 | static int sdhci_msm_vreg_init(struct device *dev, |
| 1417 | struct sdhci_msm_pltfm_data *pdata, |
| 1418 | bool is_init) |
| 1419 | { |
| 1420 | int ret = 0; |
| 1421 | struct sdhci_msm_slot_reg_data *curr_slot; |
| 1422 | struct sdhci_msm_reg_data *curr_vdd_reg, *curr_vdd_io_reg; |
| 1423 | |
| 1424 | curr_slot = pdata->vreg_data; |
| 1425 | if (!curr_slot) |
| 1426 | goto out; |
| 1427 | |
| 1428 | curr_vdd_reg = curr_slot->vdd_data; |
| 1429 | curr_vdd_io_reg = curr_slot->vdd_io_data; |
| 1430 | |
| 1431 | if (!is_init) |
| 1432 | /* Deregister all regulators from regulator framework */ |
| 1433 | goto vdd_io_reg_deinit; |
| 1434 | |
| 1435 | /* |
| 1436 | * Get the regulator handle from voltage regulator framework |
| 1437 | * and then try to set the voltage level for the regulator |
| 1438 | */ |
| 1439 | if (curr_vdd_reg) { |
| 1440 | ret = sdhci_msm_vreg_init_reg(dev, curr_vdd_reg); |
| 1441 | if (ret) |
| 1442 | goto out; |
| 1443 | } |
| 1444 | if (curr_vdd_io_reg) { |
| 1445 | ret = sdhci_msm_vreg_init_reg(dev, curr_vdd_io_reg); |
| 1446 | if (ret) |
| 1447 | goto vdd_reg_deinit; |
| 1448 | } |
| 1449 | ret = sdhci_msm_vreg_reset(pdata); |
| 1450 | if (ret) |
| 1451 | dev_err(dev, "vreg reset failed (%d)\n", ret); |
| 1452 | goto out; |
| 1453 | |
| 1454 | vdd_io_reg_deinit: |
| 1455 | if (curr_vdd_io_reg) |
| 1456 | sdhci_msm_vreg_deinit_reg(curr_vdd_io_reg); |
| 1457 | vdd_reg_deinit: |
| 1458 | if (curr_vdd_reg) |
| 1459 | sdhci_msm_vreg_deinit_reg(curr_vdd_reg); |
| 1460 | out: |
| 1461 | return ret; |
| 1462 | } |
| 1463 | |
| 1464 | |
| 1465 | static int sdhci_msm_set_vdd_io_vol(struct sdhci_msm_pltfm_data *pdata, |
| 1466 | enum vdd_io_level level, |
| 1467 | unsigned int voltage_level) |
| 1468 | { |
| 1469 | int ret = 0; |
| 1470 | int set_level; |
| 1471 | struct sdhci_msm_reg_data *vdd_io_reg; |
| 1472 | |
| 1473 | if (!pdata->vreg_data) |
| 1474 | return ret; |
| 1475 | |
| 1476 | vdd_io_reg = pdata->vreg_data->vdd_io_data; |
| 1477 | if (vdd_io_reg && vdd_io_reg->is_enabled) { |
| 1478 | switch (level) { |
| 1479 | case VDD_IO_LOW: |
| 1480 | set_level = vdd_io_reg->low_vol_level; |
| 1481 | break; |
| 1482 | case VDD_IO_HIGH: |
| 1483 | set_level = vdd_io_reg->high_vol_level; |
| 1484 | break; |
| 1485 | case VDD_IO_SET_LEVEL: |
| 1486 | set_level = voltage_level; |
| 1487 | break; |
| 1488 | default: |
| 1489 | pr_err("%s: invalid argument level = %d", |
| 1490 | __func__, level); |
| 1491 | ret = -EINVAL; |
| 1492 | return ret; |
| 1493 | } |
| 1494 | ret = sdhci_msm_vreg_set_voltage(vdd_io_reg, set_level, |
| 1495 | set_level); |
| 1496 | } |
| 1497 | return ret; |
| 1498 | } |
| 1499 | |
| 1500 | static irqreturn_t sdhci_msm_pwr_irq(int irq, void *data) |
| 1501 | { |
Venkat Gopalakrishnan | 7944a37 | 2012-09-11 16:13:31 -0700 | [diff] [blame] | 1502 | struct sdhci_host *host = (struct sdhci_host *)data; |
| 1503 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
| 1504 | struct sdhci_msm_host *msm_host = pltfm_host->priv; |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 1505 | u8 irq_status = 0; |
| 1506 | u8 irq_ack = 0; |
| 1507 | int ret = 0; |
Sahitya Tummala | 1f52eaa | 2013-03-20 19:24:01 +0530 | [diff] [blame] | 1508 | int pwr_state = 0, io_level = 0; |
| 1509 | unsigned long flags; |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 1510 | |
| 1511 | irq_status = readb_relaxed(msm_host->core_mem + CORE_PWRCTL_STATUS); |
| 1512 | pr_debug("%s: Received IRQ(%d), status=0x%x\n", |
| 1513 | mmc_hostname(msm_host->mmc), irq, irq_status); |
| 1514 | |
| 1515 | /* Clear the interrupt */ |
| 1516 | writeb_relaxed(irq_status, (msm_host->core_mem + CORE_PWRCTL_CLEAR)); |
| 1517 | /* |
| 1518 | * SDHC has core_mem and hc_mem device memory and these memory |
| 1519 | * addresses do not fall within 1KB region. Hence, any update to |
| 1520 | * core_mem address space would require an mb() to ensure this gets |
| 1521 | * completed before its next update to registers within hc_mem. |
| 1522 | */ |
| 1523 | mb(); |
| 1524 | |
| 1525 | /* Handle BUS ON/OFF*/ |
| 1526 | if (irq_status & CORE_PWRCTL_BUS_ON) { |
| 1527 | ret = sdhci_msm_setup_vreg(msm_host->pdata, true, false); |
Sahitya Tummala | 1f52eaa | 2013-03-20 19:24:01 +0530 | [diff] [blame] | 1528 | if (!ret) { |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 1529 | ret = sdhci_msm_setup_pins(msm_host->pdata, true); |
Sahitya Tummala | 1f52eaa | 2013-03-20 19:24:01 +0530 | [diff] [blame] | 1530 | ret |= sdhci_msm_set_vdd_io_vol(msm_host->pdata, |
| 1531 | VDD_IO_HIGH, 0); |
| 1532 | } |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 1533 | if (ret) |
| 1534 | irq_ack |= CORE_PWRCTL_BUS_FAIL; |
| 1535 | else |
| 1536 | irq_ack |= CORE_PWRCTL_BUS_SUCCESS; |
Sahitya Tummala | 1f52eaa | 2013-03-20 19:24:01 +0530 | [diff] [blame] | 1537 | |
| 1538 | pwr_state = REQ_BUS_ON; |
| 1539 | io_level = REQ_IO_HIGH; |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 1540 | } |
| 1541 | if (irq_status & CORE_PWRCTL_BUS_OFF) { |
| 1542 | ret = sdhci_msm_setup_vreg(msm_host->pdata, false, false); |
Sahitya Tummala | 1f52eaa | 2013-03-20 19:24:01 +0530 | [diff] [blame] | 1543 | if (!ret) { |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 1544 | ret = sdhci_msm_setup_pins(msm_host->pdata, false); |
Sahitya Tummala | 1f52eaa | 2013-03-20 19:24:01 +0530 | [diff] [blame] | 1545 | ret |= sdhci_msm_set_vdd_io_vol(msm_host->pdata, |
| 1546 | VDD_IO_LOW, 0); |
| 1547 | } |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 1548 | if (ret) |
| 1549 | irq_ack |= CORE_PWRCTL_BUS_FAIL; |
| 1550 | else |
| 1551 | irq_ack |= CORE_PWRCTL_BUS_SUCCESS; |
Sahitya Tummala | 1f52eaa | 2013-03-20 19:24:01 +0530 | [diff] [blame] | 1552 | |
| 1553 | pwr_state = REQ_BUS_OFF; |
| 1554 | io_level = REQ_IO_LOW; |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 1555 | } |
| 1556 | /* Handle IO LOW/HIGH */ |
| 1557 | if (irq_status & CORE_PWRCTL_IO_LOW) { |
| 1558 | /* Switch voltage Low */ |
| 1559 | ret = sdhci_msm_set_vdd_io_vol(msm_host->pdata, VDD_IO_LOW, 0); |
| 1560 | if (ret) |
| 1561 | irq_ack |= CORE_PWRCTL_IO_FAIL; |
| 1562 | else |
| 1563 | irq_ack |= CORE_PWRCTL_IO_SUCCESS; |
Sahitya Tummala | 1f52eaa | 2013-03-20 19:24:01 +0530 | [diff] [blame] | 1564 | |
| 1565 | io_level = REQ_IO_LOW; |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 1566 | } |
| 1567 | if (irq_status & CORE_PWRCTL_IO_HIGH) { |
| 1568 | /* Switch voltage High */ |
| 1569 | ret = sdhci_msm_set_vdd_io_vol(msm_host->pdata, VDD_IO_HIGH, 0); |
| 1570 | if (ret) |
| 1571 | irq_ack |= CORE_PWRCTL_IO_FAIL; |
| 1572 | else |
| 1573 | irq_ack |= CORE_PWRCTL_IO_SUCCESS; |
Sahitya Tummala | 1f52eaa | 2013-03-20 19:24:01 +0530 | [diff] [blame] | 1574 | |
| 1575 | io_level = REQ_IO_HIGH; |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 1576 | } |
| 1577 | |
| 1578 | /* ACK status to the core */ |
| 1579 | writeb_relaxed(irq_ack, (msm_host->core_mem + CORE_PWRCTL_CTL)); |
| 1580 | /* |
| 1581 | * SDHC has core_mem and hc_mem device memory and these memory |
| 1582 | * addresses do not fall within 1KB region. Hence, any update to |
| 1583 | * core_mem address space would require an mb() to ensure this gets |
| 1584 | * completed before its next update to registers within hc_mem. |
| 1585 | */ |
| 1586 | mb(); |
| 1587 | |
Sahitya Tummala | 1f52eaa | 2013-03-20 19:24:01 +0530 | [diff] [blame] | 1588 | if (io_level & REQ_IO_HIGH) |
Venkat Gopalakrishnan | 7944a37 | 2012-09-11 16:13:31 -0700 | [diff] [blame] | 1589 | writel_relaxed((readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC) & |
| 1590 | ~CORE_IO_PAD_PWR_SWITCH), |
| 1591 | host->ioaddr + CORE_VENDOR_SPEC); |
Sahitya Tummala | 1f52eaa | 2013-03-20 19:24:01 +0530 | [diff] [blame] | 1592 | else if (io_level & REQ_IO_LOW) |
Venkat Gopalakrishnan | 7944a37 | 2012-09-11 16:13:31 -0700 | [diff] [blame] | 1593 | writel_relaxed((readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC) | |
| 1594 | CORE_IO_PAD_PWR_SWITCH), |
| 1595 | host->ioaddr + CORE_VENDOR_SPEC); |
| 1596 | mb(); |
| 1597 | |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 1598 | pr_debug("%s: Handled IRQ(%d), ret=%d, ack=0x%x\n", |
| 1599 | mmc_hostname(msm_host->mmc), irq, ret, irq_ack); |
Sahitya Tummala | 1f52eaa | 2013-03-20 19:24:01 +0530 | [diff] [blame] | 1600 | spin_lock_irqsave(&host->lock, flags); |
| 1601 | if (pwr_state) |
| 1602 | msm_host->curr_pwr_state = pwr_state; |
| 1603 | if (io_level) |
| 1604 | msm_host->curr_io_level = io_level; |
| 1605 | complete(&msm_host->pwr_irq_completion); |
| 1606 | spin_unlock_irqrestore(&host->lock, flags); |
| 1607 | |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 1608 | return IRQ_HANDLED; |
| 1609 | } |
| 1610 | |
Sahitya Tummala | 8a3e818 | 2013-03-10 14:12:52 +0530 | [diff] [blame] | 1611 | static ssize_t |
Sahitya Tummala | 5c55b93 | 2013-06-20 14:00:18 +0530 | [diff] [blame] | 1612 | show_polling(struct device *dev, struct device_attribute *attr, char *buf) |
| 1613 | { |
| 1614 | struct sdhci_host *host = dev_get_drvdata(dev); |
| 1615 | int poll; |
| 1616 | unsigned long flags; |
| 1617 | |
| 1618 | spin_lock_irqsave(&host->lock, flags); |
| 1619 | poll = !!(host->mmc->caps & MMC_CAP_NEEDS_POLL); |
| 1620 | spin_unlock_irqrestore(&host->lock, flags); |
| 1621 | |
| 1622 | return snprintf(buf, PAGE_SIZE, "%d\n", poll); |
| 1623 | } |
| 1624 | |
| 1625 | static ssize_t |
| 1626 | store_polling(struct device *dev, struct device_attribute *attr, |
| 1627 | const char *buf, size_t count) |
| 1628 | { |
| 1629 | struct sdhci_host *host = dev_get_drvdata(dev); |
| 1630 | int value; |
| 1631 | unsigned long flags; |
| 1632 | |
| 1633 | if (!kstrtou32(buf, 0, &value)) { |
| 1634 | spin_lock_irqsave(&host->lock, flags); |
| 1635 | if (value) { |
| 1636 | host->mmc->caps |= MMC_CAP_NEEDS_POLL; |
| 1637 | mmc_detect_change(host->mmc, 0); |
| 1638 | } else { |
| 1639 | host->mmc->caps &= ~MMC_CAP_NEEDS_POLL; |
| 1640 | } |
| 1641 | spin_unlock_irqrestore(&host->lock, flags); |
| 1642 | } |
| 1643 | return count; |
| 1644 | } |
| 1645 | |
| 1646 | static ssize_t |
Sahitya Tummala | 8a3e818 | 2013-03-10 14:12:52 +0530 | [diff] [blame] | 1647 | show_sdhci_max_bus_bw(struct device *dev, struct device_attribute *attr, |
| 1648 | char *buf) |
| 1649 | { |
| 1650 | struct sdhci_host *host = dev_get_drvdata(dev); |
| 1651 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
| 1652 | struct sdhci_msm_host *msm_host = pltfm_host->priv; |
| 1653 | |
| 1654 | return snprintf(buf, PAGE_SIZE, "%u\n", |
| 1655 | msm_host->msm_bus_vote.is_max_bw_needed); |
| 1656 | } |
| 1657 | |
| 1658 | static ssize_t |
| 1659 | store_sdhci_max_bus_bw(struct device *dev, struct device_attribute *attr, |
| 1660 | const char *buf, size_t count) |
| 1661 | { |
| 1662 | struct sdhci_host *host = dev_get_drvdata(dev); |
| 1663 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
| 1664 | struct sdhci_msm_host *msm_host = pltfm_host->priv; |
| 1665 | uint32_t value; |
| 1666 | unsigned long flags; |
| 1667 | |
| 1668 | if (!kstrtou32(buf, 0, &value)) { |
| 1669 | spin_lock_irqsave(&host->lock, flags); |
| 1670 | msm_host->msm_bus_vote.is_max_bw_needed = !!value; |
| 1671 | spin_unlock_irqrestore(&host->lock, flags); |
| 1672 | } |
| 1673 | return count; |
| 1674 | } |
| 1675 | |
Sahitya Tummala | 1f52eaa | 2013-03-20 19:24:01 +0530 | [diff] [blame] | 1676 | static void sdhci_msm_check_power_status(struct sdhci_host *host, u32 req_type) |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 1677 | { |
| 1678 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
| 1679 | struct sdhci_msm_host *msm_host = pltfm_host->priv; |
Sahitya Tummala | 1f52eaa | 2013-03-20 19:24:01 +0530 | [diff] [blame] | 1680 | unsigned long flags; |
| 1681 | bool done = false; |
Sahitya Tummala | 481fbb0 | 2013-08-06 15:22:28 +0530 | [diff] [blame] | 1682 | u32 io_sig_sts; |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 1683 | |
Sahitya Tummala | 1f52eaa | 2013-03-20 19:24:01 +0530 | [diff] [blame] | 1684 | spin_lock_irqsave(&host->lock, flags); |
| 1685 | pr_debug("%s: %s: request %d curr_pwr_state %x curr_io_level %x\n", |
| 1686 | mmc_hostname(host->mmc), __func__, req_type, |
| 1687 | msm_host->curr_pwr_state, msm_host->curr_io_level); |
Sahitya Tummala | 481fbb0 | 2013-08-06 15:22:28 +0530 | [diff] [blame] | 1688 | io_sig_sts = readl_relaxed(msm_host->core_mem + CORE_GENERICS); |
| 1689 | /* |
| 1690 | * The IRQ for request type IO High/Low will be generated when - |
| 1691 | * 1. SWITCHABLE_SIGNALLING_VOL is enabled in HW. |
| 1692 | * 2. If 1 is true and when there is a state change in 1.8V enable |
| 1693 | * bit (bit 3) of SDHCI_HOST_CONTROL2 register. The reset state of |
| 1694 | * that bit is 0 which indicates 3.3V IO voltage. So, when MMC core |
| 1695 | * layer tries to set it to 3.3V before card detection happens, the |
| 1696 | * IRQ doesn't get triggered as there is no state change in this bit. |
| 1697 | * The driver already handles this case by changing the IO voltage |
| 1698 | * level to high as part of controller power up sequence. Hence, check |
| 1699 | * for host->pwr to handle a case where IO voltage high request is |
| 1700 | * issued even before controller power up. |
| 1701 | */ |
| 1702 | if (req_type & (REQ_IO_HIGH | REQ_IO_LOW)) { |
| 1703 | if (!(io_sig_sts & SWITCHABLE_SIGNALLING_VOL) || |
| 1704 | ((req_type & REQ_IO_HIGH) && !host->pwr)) { |
| 1705 | pr_debug("%s: do not wait for power IRQ that never comes\n", |
| 1706 | mmc_hostname(host->mmc)); |
| 1707 | spin_unlock_irqrestore(&host->lock, flags); |
| 1708 | return; |
| 1709 | } |
| 1710 | } |
| 1711 | |
Sahitya Tummala | 1f52eaa | 2013-03-20 19:24:01 +0530 | [diff] [blame] | 1712 | if ((req_type & msm_host->curr_pwr_state) || |
| 1713 | (req_type & msm_host->curr_io_level)) |
| 1714 | done = true; |
| 1715 | spin_unlock_irqrestore(&host->lock, flags); |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 1716 | |
Sahitya Tummala | 1f52eaa | 2013-03-20 19:24:01 +0530 | [diff] [blame] | 1717 | /* |
| 1718 | * This is needed here to hanlde a case where IRQ gets |
| 1719 | * triggered even before this function is called so that |
| 1720 | * x->done counter of completion gets reset. Otherwise, |
| 1721 | * next call to wait_for_completion returns immediately |
| 1722 | * without actually waiting for the IRQ to be handled. |
| 1723 | */ |
| 1724 | if (done) |
| 1725 | init_completion(&msm_host->pwr_irq_completion); |
| 1726 | else |
| 1727 | wait_for_completion(&msm_host->pwr_irq_completion); |
| 1728 | |
| 1729 | pr_debug("%s: %s: request %d done\n", mmc_hostname(host->mmc), |
| 1730 | __func__, req_type); |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 1731 | } |
| 1732 | |
Venkat Gopalakrishnan | 7944a37 | 2012-09-11 16:13:31 -0700 | [diff] [blame] | 1733 | static void sdhci_msm_toggle_cdr(struct sdhci_host *host, bool enable) |
| 1734 | { |
| 1735 | if (enable) |
| 1736 | writel_relaxed((readl_relaxed(host->ioaddr + |
| 1737 | CORE_DLL_CONFIG) | CORE_CDR_EN), |
| 1738 | host->ioaddr + CORE_DLL_CONFIG); |
| 1739 | else |
| 1740 | writel_relaxed((readl_relaxed(host->ioaddr + |
| 1741 | CORE_DLL_CONFIG) & ~CORE_CDR_EN), |
| 1742 | host->ioaddr + CORE_DLL_CONFIG); |
| 1743 | } |
| 1744 | |
Asutosh Das | 648f9d1 | 2013-01-10 21:11:04 +0530 | [diff] [blame] | 1745 | static unsigned int sdhci_msm_max_segs(void) |
| 1746 | { |
| 1747 | return SDHCI_MSM_MAX_SEGMENTS; |
| 1748 | } |
| 1749 | |
Sahitya Tummala | 22dd336 | 2013-02-28 19:50:51 +0530 | [diff] [blame] | 1750 | static unsigned int sdhci_msm_get_min_clock(struct sdhci_host *host) |
Sahitya Tummala | a7f3c57 | 2013-01-11 11:30:45 +0530 | [diff] [blame] | 1751 | { |
Sahitya Tummala | a7f3c57 | 2013-01-11 11:30:45 +0530 | [diff] [blame] | 1752 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
| 1753 | struct sdhci_msm_host *msm_host = pltfm_host->priv; |
Sahitya Tummala | a7f3c57 | 2013-01-11 11:30:45 +0530 | [diff] [blame] | 1754 | |
Sahitya Tummala | 22dd336 | 2013-02-28 19:50:51 +0530 | [diff] [blame] | 1755 | return msm_host->pdata->sup_clk_table[0]; |
| 1756 | } |
| 1757 | |
| 1758 | static unsigned int sdhci_msm_get_max_clock(struct sdhci_host *host) |
| 1759 | { |
| 1760 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
| 1761 | struct sdhci_msm_host *msm_host = pltfm_host->priv; |
| 1762 | int max_clk_index = msm_host->pdata->sup_clk_cnt; |
| 1763 | |
| 1764 | return msm_host->pdata->sup_clk_table[max_clk_index - 1]; |
| 1765 | } |
| 1766 | |
| 1767 | static unsigned int sdhci_msm_get_sup_clk_rate(struct sdhci_host *host, |
| 1768 | u32 req_clk) |
| 1769 | { |
| 1770 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
| 1771 | struct sdhci_msm_host *msm_host = pltfm_host->priv; |
| 1772 | unsigned int sel_clk = -1; |
| 1773 | unsigned char cnt; |
| 1774 | |
| 1775 | if (req_clk < sdhci_msm_get_min_clock(host)) { |
| 1776 | sel_clk = sdhci_msm_get_min_clock(host); |
| 1777 | return sel_clk; |
| 1778 | } |
| 1779 | |
| 1780 | for (cnt = 0; cnt < msm_host->pdata->sup_clk_cnt; cnt++) { |
| 1781 | if (msm_host->pdata->sup_clk_table[cnt] > req_clk) { |
| 1782 | break; |
| 1783 | } else if (msm_host->pdata->sup_clk_table[cnt] == req_clk) { |
| 1784 | sel_clk = msm_host->pdata->sup_clk_table[cnt]; |
| 1785 | break; |
| 1786 | } else { |
| 1787 | sel_clk = msm_host->pdata->sup_clk_table[cnt]; |
| 1788 | } |
| 1789 | } |
| 1790 | return sel_clk; |
| 1791 | } |
| 1792 | |
| 1793 | static int sdhci_msm_prepare_clocks(struct sdhci_host *host, bool enable) |
| 1794 | { |
| 1795 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
| 1796 | struct sdhci_msm_host *msm_host = pltfm_host->priv; |
| 1797 | int rc = 0; |
| 1798 | |
| 1799 | if (enable && !atomic_read(&msm_host->clks_on)) { |
| 1800 | pr_debug("%s: request to enable clocks\n", |
| 1801 | mmc_hostname(host->mmc)); |
Sahitya Tummala | 79edc6a | 2013-05-23 15:59:22 +0530 | [diff] [blame] | 1802 | |
| 1803 | sdhci_msm_bus_voting(host, 1); |
| 1804 | |
Sahitya Tummala | a7f3c57 | 2013-01-11 11:30:45 +0530 | [diff] [blame] | 1805 | if (!IS_ERR_OR_NULL(msm_host->bus_clk)) { |
| 1806 | rc = clk_prepare_enable(msm_host->bus_clk); |
| 1807 | if (rc) { |
| 1808 | pr_err("%s: %s: failed to enable the bus-clock with error %d\n", |
| 1809 | mmc_hostname(host->mmc), __func__, rc); |
Sahitya Tummala | 79edc6a | 2013-05-23 15:59:22 +0530 | [diff] [blame] | 1810 | goto remove_vote; |
Sahitya Tummala | a7f3c57 | 2013-01-11 11:30:45 +0530 | [diff] [blame] | 1811 | } |
| 1812 | } |
| 1813 | if (!IS_ERR(msm_host->pclk)) { |
| 1814 | rc = clk_prepare_enable(msm_host->pclk); |
| 1815 | if (rc) { |
| 1816 | pr_err("%s: %s: failed to enable the pclk with error %d\n", |
| 1817 | mmc_hostname(host->mmc), __func__, rc); |
| 1818 | goto disable_bus_clk; |
| 1819 | } |
| 1820 | } |
| 1821 | rc = clk_prepare_enable(msm_host->clk); |
| 1822 | if (rc) { |
| 1823 | pr_err("%s: %s: failed to enable the host-clk with error %d\n", |
| 1824 | mmc_hostname(host->mmc), __func__, rc); |
| 1825 | goto disable_pclk; |
| 1826 | } |
Venkat Gopalakrishnan | 7f69157 | 2013-06-23 17:36:46 -0700 | [diff] [blame^] | 1827 | if (!IS_ERR(msm_host->ff_clk)) { |
| 1828 | rc = clk_prepare_enable(msm_host->ff_clk); |
| 1829 | if (rc) { |
| 1830 | pr_err("%s: %s: failed to enable the ff_clk with error %d\n", |
| 1831 | mmc_hostname(host->mmc), __func__, rc); |
| 1832 | goto disable_clk; |
| 1833 | } |
| 1834 | } |
| 1835 | if (!IS_ERR(msm_host->sleep_clk)) { |
| 1836 | rc = clk_prepare_enable(msm_host->sleep_clk); |
| 1837 | if (rc) { |
| 1838 | pr_err("%s: %s: failed to enable the sleep_clk with error %d\n", |
| 1839 | mmc_hostname(host->mmc), __func__, rc); |
| 1840 | goto disable_ff_clk; |
| 1841 | } |
| 1842 | } |
Sahitya Tummala | a7f3c57 | 2013-01-11 11:30:45 +0530 | [diff] [blame] | 1843 | mb(); |
Sahitya Tummala | a7f3c57 | 2013-01-11 11:30:45 +0530 | [diff] [blame] | 1844 | |
Sahitya Tummala | 22dd336 | 2013-02-28 19:50:51 +0530 | [diff] [blame] | 1845 | } else if (!enable && atomic_read(&msm_host->clks_on)) { |
Sahitya Tummala | a7f3c57 | 2013-01-11 11:30:45 +0530 | [diff] [blame] | 1846 | pr_debug("%s: request to disable clocks\n", |
| 1847 | mmc_hostname(host->mmc)); |
| 1848 | sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); |
| 1849 | mb(); |
Venkat Gopalakrishnan | 7f69157 | 2013-06-23 17:36:46 -0700 | [diff] [blame^] | 1850 | if (!IS_ERR_OR_NULL(msm_host->sleep_clk)) |
| 1851 | clk_disable_unprepare(msm_host->sleep_clk); |
| 1852 | if (!IS_ERR_OR_NULL(msm_host->ff_clk)) |
| 1853 | clk_disable_unprepare(msm_host->ff_clk); |
Sahitya Tummala | a7f3c57 | 2013-01-11 11:30:45 +0530 | [diff] [blame] | 1854 | clk_disable_unprepare(msm_host->clk); |
| 1855 | if (!IS_ERR(msm_host->pclk)) |
| 1856 | clk_disable_unprepare(msm_host->pclk); |
| 1857 | if (!IS_ERR_OR_NULL(msm_host->bus_clk)) |
| 1858 | clk_disable_unprepare(msm_host->bus_clk); |
Sahitya Tummala | 79edc6a | 2013-05-23 15:59:22 +0530 | [diff] [blame] | 1859 | |
| 1860 | sdhci_msm_bus_voting(host, 0); |
Sahitya Tummala | a7f3c57 | 2013-01-11 11:30:45 +0530 | [diff] [blame] | 1861 | } |
Sahitya Tummala | 22dd336 | 2013-02-28 19:50:51 +0530 | [diff] [blame] | 1862 | atomic_set(&msm_host->clks_on, enable); |
Sahitya Tummala | a7f3c57 | 2013-01-11 11:30:45 +0530 | [diff] [blame] | 1863 | goto out; |
Venkat Gopalakrishnan | 7f69157 | 2013-06-23 17:36:46 -0700 | [diff] [blame^] | 1864 | disable_ff_clk: |
| 1865 | if (!IS_ERR_OR_NULL(msm_host->ff_clk)) |
| 1866 | clk_disable_unprepare(msm_host->ff_clk); |
| 1867 | disable_clk: |
| 1868 | if (!IS_ERR_OR_NULL(msm_host->clk)) |
| 1869 | clk_disable_unprepare(msm_host->clk); |
Sahitya Tummala | a7f3c57 | 2013-01-11 11:30:45 +0530 | [diff] [blame] | 1870 | disable_pclk: |
| 1871 | if (!IS_ERR_OR_NULL(msm_host->pclk)) |
| 1872 | clk_disable_unprepare(msm_host->pclk); |
| 1873 | disable_bus_clk: |
| 1874 | if (!IS_ERR_OR_NULL(msm_host->bus_clk)) |
| 1875 | clk_disable_unprepare(msm_host->bus_clk); |
Sahitya Tummala | 79edc6a | 2013-05-23 15:59:22 +0530 | [diff] [blame] | 1876 | remove_vote: |
| 1877 | if (msm_host->msm_bus_vote.client_handle) |
| 1878 | sdhci_msm_bus_cancel_work_and_set_vote(host, 0); |
Sahitya Tummala | a7f3c57 | 2013-01-11 11:30:45 +0530 | [diff] [blame] | 1879 | out: |
Sahitya Tummala | 22dd336 | 2013-02-28 19:50:51 +0530 | [diff] [blame] | 1880 | return rc; |
| 1881 | } |
| 1882 | |
| 1883 | static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock) |
| 1884 | { |
| 1885 | int rc; |
| 1886 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
| 1887 | struct sdhci_msm_host *msm_host = pltfm_host->priv; |
| 1888 | struct mmc_ios curr_ios = host->mmc->ios; |
| 1889 | u32 sup_clock, ddr_clock; |
| 1890 | |
| 1891 | if (!clock) { |
| 1892 | sdhci_msm_prepare_clocks(host, false); |
| 1893 | host->clock = clock; |
| 1894 | goto out; |
| 1895 | } |
| 1896 | |
| 1897 | rc = sdhci_msm_prepare_clocks(host, true); |
| 1898 | if (rc) |
| 1899 | goto out; |
| 1900 | |
| 1901 | sup_clock = sdhci_msm_get_sup_clk_rate(host, clock); |
Venkat Gopalakrishnan | 7f69157 | 2013-06-23 17:36:46 -0700 | [diff] [blame^] | 1902 | if ((curr_ios.timing == MMC_TIMING_UHS_DDR50) || |
| 1903 | (curr_ios.timing == MMC_TIMING_MMC_HS400)) { |
Sahitya Tummala | 22dd336 | 2013-02-28 19:50:51 +0530 | [diff] [blame] | 1904 | /* |
| 1905 | * The SDHC requires internal clock frequency to be double the |
| 1906 | * actual clock that will be set for DDR mode. The controller |
Venkat Gopalakrishnan | 7f69157 | 2013-06-23 17:36:46 -0700 | [diff] [blame^] | 1907 | * uses the faster clock(100/400MHz) for some of its parts and |
| 1908 | * send the actual required clock (50/200MHz) to the card. |
Sahitya Tummala | 22dd336 | 2013-02-28 19:50:51 +0530 | [diff] [blame] | 1909 | */ |
| 1910 | ddr_clock = clock * 2; |
| 1911 | sup_clock = sdhci_msm_get_sup_clk_rate(host, |
| 1912 | ddr_clock); |
| 1913 | } |
Venkat Gopalakrishnan | 7f69157 | 2013-06-23 17:36:46 -0700 | [diff] [blame^] | 1914 | |
| 1915 | /* |
| 1916 | * In general all timing modes are controlled via UHS mode select in |
| 1917 | * Host Control2 register. eMMC specific HS200/HS400 doesn't have |
| 1918 | * their respective modes defined here, hence we use these values. |
| 1919 | * |
| 1920 | * HS200 - SDR104 (Since they both are equivalent in functionality) |
| 1921 | * HS400 - This involves multiple configurations |
| 1922 | * Initially SDR104 - when tuning is required as HS200 |
| 1923 | * Then when switching to DDR @ 400MHz (HS400) we use |
| 1924 | * the vendor specific HC_SELECT_IN to control the mode. |
| 1925 | * |
| 1926 | * In addition to controlling the modes we also need to select the |
| 1927 | * correct input clock for DLL depending on the mode. |
| 1928 | * |
| 1929 | * HS400 - divided clock (free running MCLK/2) |
| 1930 | * All other modes - default (free running MCLK) |
| 1931 | */ |
| 1932 | if (curr_ios.timing == MMC_TIMING_MMC_HS400) { |
| 1933 | /* Select the divided clock (free running MCLK/2) */ |
| 1934 | writel_relaxed(((readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC) |
| 1935 | & ~CORE_HC_MCLK_SEL_MASK) |
| 1936 | | CORE_HC_MCLK_SEL_HS400), |
| 1937 | host->ioaddr + CORE_VENDOR_SPEC); |
| 1938 | /* |
| 1939 | * Select HS400 mode using the HC_SELECT_IN from VENDOR SPEC |
| 1940 | * register |
| 1941 | */ |
| 1942 | if (msm_host->tuning_done && !msm_host->calibration_done) { |
| 1943 | /* |
| 1944 | * Write 0x6 to HC_SELECT_IN and 1 to HC_SELECT_IN_EN |
| 1945 | * field in VENDOR_SPEC_FUNC |
| 1946 | */ |
| 1947 | writel_relaxed((readl_relaxed(host->ioaddr + \ |
| 1948 | CORE_VENDOR_SPEC) |
| 1949 | | CORE_HC_SELECT_IN_HS400 |
| 1950 | | CORE_HC_SELECT_IN_EN), |
| 1951 | host->ioaddr + CORE_VENDOR_SPEC); |
| 1952 | } |
| 1953 | } else { |
| 1954 | /* Select the default clock (free running MCLK) */ |
| 1955 | writel_relaxed(((readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC) |
| 1956 | & ~CORE_HC_MCLK_SEL_MASK) |
| 1957 | | CORE_HC_MCLK_SEL_DFLT), |
| 1958 | host->ioaddr + CORE_VENDOR_SPEC); |
| 1959 | |
| 1960 | /* |
| 1961 | * Disable HC_SELECT_IN to be able to use the UHS mode select |
| 1962 | * configuration from Host Control2 register for all other |
| 1963 | * modes. |
| 1964 | * |
| 1965 | * Write 0 to HC_SELECT_IN and HC_SELECT_IN_EN field |
| 1966 | * in VENDOR_SPEC_FUNC |
| 1967 | */ |
| 1968 | writel_relaxed((readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC) |
| 1969 | & ~CORE_HC_SELECT_IN_EN |
| 1970 | & ~CORE_HC_SELECT_IN_MASK), |
| 1971 | host->ioaddr + CORE_VENDOR_SPEC); |
| 1972 | } |
| 1973 | mb(); |
| 1974 | |
Sahitya Tummala | 22dd336 | 2013-02-28 19:50:51 +0530 | [diff] [blame] | 1975 | if (sup_clock != msm_host->clk_rate) { |
| 1976 | pr_debug("%s: %s: setting clk rate to %u\n", |
| 1977 | mmc_hostname(host->mmc), __func__, sup_clock); |
| 1978 | rc = clk_set_rate(msm_host->clk, sup_clock); |
| 1979 | if (rc) { |
| 1980 | pr_err("%s: %s: Failed to set rate %u for host-clk : %d\n", |
| 1981 | mmc_hostname(host->mmc), __func__, |
| 1982 | sup_clock, rc); |
| 1983 | goto out; |
| 1984 | } |
| 1985 | msm_host->clk_rate = sup_clock; |
| 1986 | host->clock = clock; |
Sahitya Tummala | 79edc6a | 2013-05-23 15:59:22 +0530 | [diff] [blame] | 1987 | /* |
| 1988 | * Update the bus vote in case of frequency change due to |
| 1989 | * clock scaling. |
| 1990 | */ |
| 1991 | sdhci_msm_bus_voting(host, 1); |
Sahitya Tummala | 22dd336 | 2013-02-28 19:50:51 +0530 | [diff] [blame] | 1992 | } |
| 1993 | out: |
| 1994 | sdhci_set_clock(host, clock); |
Sahitya Tummala | a7f3c57 | 2013-01-11 11:30:45 +0530 | [diff] [blame] | 1995 | } |
| 1996 | |
Sahitya Tummala | 1461343 | 2013-03-21 11:13:25 +0530 | [diff] [blame] | 1997 | static void sdhci_msm_set_uhs_signaling(struct sdhci_host *host, |
| 1998 | unsigned int uhs) |
| 1999 | { |
Venkat Gopalakrishnan | 7f69157 | 2013-06-23 17:36:46 -0700 | [diff] [blame^] | 2000 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
| 2001 | struct sdhci_msm_host *msm_host = pltfm_host->priv; |
Sahitya Tummala | 1461343 | 2013-03-21 11:13:25 +0530 | [diff] [blame] | 2002 | u16 ctrl_2; |
| 2003 | |
| 2004 | ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); |
| 2005 | /* Select Bus Speed Mode for host */ |
| 2006 | ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; |
Venkat Gopalakrishnan | 7f69157 | 2013-06-23 17:36:46 -0700 | [diff] [blame^] | 2007 | if (uhs == MMC_TIMING_MMC_HS400) |
| 2008 | ctrl_2 |= SDHCI_CTRL_UHS_SDR104; |
| 2009 | else if (uhs == MMC_TIMING_MMC_HS200) |
Sahitya Tummala | 1461343 | 2013-03-21 11:13:25 +0530 | [diff] [blame] | 2010 | ctrl_2 |= SDHCI_CTRL_UHS_SDR104; |
| 2011 | else if (uhs == MMC_TIMING_UHS_SDR12) |
| 2012 | ctrl_2 |= SDHCI_CTRL_UHS_SDR12; |
| 2013 | else if (uhs == MMC_TIMING_UHS_SDR25) |
| 2014 | ctrl_2 |= SDHCI_CTRL_UHS_SDR25; |
| 2015 | else if (uhs == MMC_TIMING_UHS_SDR50) |
| 2016 | ctrl_2 |= SDHCI_CTRL_UHS_SDR50; |
| 2017 | else if (uhs == MMC_TIMING_UHS_SDR104) |
| 2018 | ctrl_2 |= SDHCI_CTRL_UHS_SDR104; |
| 2019 | else if (uhs == MMC_TIMING_UHS_DDR50) |
| 2020 | ctrl_2 |= SDHCI_CTRL_UHS_DDR50; |
Sahitya Tummala | 22dd336 | 2013-02-28 19:50:51 +0530 | [diff] [blame] | 2021 | /* |
| 2022 | * When clock frquency is less than 100MHz, the feedback clock must be |
| 2023 | * provided and DLL must not be used so that tuning can be skipped. To |
| 2024 | * provide feedback clock, the mode selection can be any value less |
| 2025 | * than 3'b011 in bits [2:0] of HOST CONTROL2 register. |
| 2026 | */ |
Venkat Gopalakrishnan | 7f69157 | 2013-06-23 17:36:46 -0700 | [diff] [blame^] | 2027 | if (host->clock <= CORE_FREQ_100MHZ) { |
| 2028 | if ((uhs == MMC_TIMING_MMC_HS400) || |
| 2029 | (uhs == MMC_TIMING_MMC_HS200) || |
| 2030 | (uhs == MMC_TIMING_UHS_SDR104)) |
| 2031 | ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; |
Sahitya Tummala | 22dd336 | 2013-02-28 19:50:51 +0530 | [diff] [blame] | 2032 | |
Venkat Gopalakrishnan | 7f69157 | 2013-06-23 17:36:46 -0700 | [diff] [blame^] | 2033 | /* |
| 2034 | * Make sure DLL is disabled when not required |
| 2035 | * |
| 2036 | * Write 1 to DLL_RST bit of DLL_CONFIG register |
| 2037 | */ |
| 2038 | writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) |
| 2039 | | CORE_DLL_RST), |
| 2040 | host->ioaddr + CORE_DLL_CONFIG); |
| 2041 | |
| 2042 | /* Write 1 to DLL_PDN bit of DLL_CONFIG register */ |
| 2043 | writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) |
| 2044 | | CORE_DLL_PDN), |
| 2045 | host->ioaddr + CORE_DLL_CONFIG); |
| 2046 | mb(); |
| 2047 | |
| 2048 | /* |
| 2049 | * The DLL needs to be restored and CDCLP533 recalibrated |
| 2050 | * when the clock frequency is set back to 400MHz. |
| 2051 | */ |
| 2052 | msm_host->calibration_done = false; |
| 2053 | } |
| 2054 | |
| 2055 | pr_debug("%s: %s-clock:%u uhs mode:%u ctrl_2:0x%x\n", |
| 2056 | mmc_hostname(host->mmc), __func__, host->clock, uhs, ctrl_2); |
Sahitya Tummala | 1461343 | 2013-03-21 11:13:25 +0530 | [diff] [blame] | 2057 | sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); |
| 2058 | |
| 2059 | } |
| 2060 | |
Sahitya Tummala | 67717bc | 2013-08-02 09:21:37 +0530 | [diff] [blame] | 2061 | #define MAX_TEST_BUS 20 |
| 2062 | |
| 2063 | void sdhci_msm_dump_vendor_regs(struct sdhci_host *host) |
| 2064 | { |
| 2065 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
| 2066 | struct sdhci_msm_host *msm_host = pltfm_host->priv; |
| 2067 | int tbsel, tbsel2; |
| 2068 | int i, index = 0; |
| 2069 | u32 test_bus_val = 0; |
| 2070 | u32 debug_reg[MAX_TEST_BUS] = {0}; |
| 2071 | |
| 2072 | pr_info("----------- VENDOR REGISTER DUMP -----------\n"); |
| 2073 | pr_info("Data cnt: 0x%08x | Fifo cnt: 0x%08x | Int sts: 0x%08x\n", |
| 2074 | readl_relaxed(msm_host->core_mem + CORE_MCI_DATA_CNT), |
| 2075 | readl_relaxed(msm_host->core_mem + CORE_MCI_FIFO_CNT), |
| 2076 | readl_relaxed(msm_host->core_mem + CORE_MCI_STATUS)); |
| 2077 | pr_info("DLL cfg: 0x%08x | DLL sts: 0x%08x | SDCC ver: 0x%08x\n", |
| 2078 | readl_relaxed(host->ioaddr + CORE_DLL_CONFIG), |
| 2079 | readl_relaxed(host->ioaddr + CORE_DLL_STATUS), |
| 2080 | readl_relaxed(msm_host->core_mem + CORE_MCI_VERSION)); |
| 2081 | pr_info("Vndr func: 0x%08x | Vndr adma err : addr0: 0x%08x addr1: 0x%08x\n", |
| 2082 | readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC), |
| 2083 | readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC_ADMA_ERR_ADDR0), |
| 2084 | readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC_ADMA_ERR_ADDR1)); |
| 2085 | |
| 2086 | /* |
| 2087 | * tbsel indicates [2:0] bits and tbsel2 indicates [7:4] bits |
| 2088 | * of CORE_TESTBUS_CONFIG register. |
| 2089 | * |
| 2090 | * To select test bus 0 to 7 use tbsel and to select any test bus |
| 2091 | * above 7 use (tbsel2 | tbsel) to get the test bus number. For eg, |
| 2092 | * to select test bus 14, write 0x1E to CORE_TESTBUS_CONFIG register |
| 2093 | * i.e., tbsel2[7:4] = 0001, tbsel[2:0] = 110. |
| 2094 | */ |
| 2095 | for (tbsel2 = 0; tbsel2 < 3; tbsel2++) { |
| 2096 | for (tbsel = 0; tbsel < 8; tbsel++) { |
| 2097 | if (index >= MAX_TEST_BUS) |
| 2098 | break; |
| 2099 | test_bus_val = (tbsel2 << CORE_TESTBUS_SEL2_BIT) | |
| 2100 | tbsel | CORE_TESTBUS_ENA; |
| 2101 | writel_relaxed(test_bus_val, |
| 2102 | msm_host->core_mem + CORE_TESTBUS_CONFIG); |
| 2103 | debug_reg[index++] = readl_relaxed(msm_host->core_mem + |
| 2104 | CORE_SDCC_DEBUG_REG); |
| 2105 | } |
| 2106 | } |
| 2107 | for (i = 0; i < MAX_TEST_BUS; i = i + 4) |
| 2108 | pr_info(" Test bus[%d to %d]: 0x%08x 0x%08x 0x%08x 0x%08x\n", |
| 2109 | i, i + 3, debug_reg[i], debug_reg[i+1], |
| 2110 | debug_reg[i+2], debug_reg[i+3]); |
| 2111 | /* Disable test bus */ |
| 2112 | writel_relaxed(~CORE_TESTBUS_ENA, msm_host->core_mem + |
| 2113 | CORE_TESTBUS_CONFIG); |
| 2114 | } |
| 2115 | |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 2116 | static struct sdhci_ops sdhci_msm_ops = { |
Sahitya Tummala | 1461343 | 2013-03-21 11:13:25 +0530 | [diff] [blame] | 2117 | .set_uhs_signaling = sdhci_msm_set_uhs_signaling, |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 2118 | .check_power_status = sdhci_msm_check_power_status, |
Venkat Gopalakrishnan | 7944a37 | 2012-09-11 16:13:31 -0700 | [diff] [blame] | 2119 | .platform_execute_tuning = sdhci_msm_execute_tuning, |
| 2120 | .toggle_cdr = sdhci_msm_toggle_cdr, |
Asutosh Das | 648f9d1 | 2013-01-10 21:11:04 +0530 | [diff] [blame] | 2121 | .get_max_segments = sdhci_msm_max_segs, |
Sahitya Tummala | a7f3c57 | 2013-01-11 11:30:45 +0530 | [diff] [blame] | 2122 | .set_clock = sdhci_msm_set_clock, |
Sahitya Tummala | 22dd336 | 2013-02-28 19:50:51 +0530 | [diff] [blame] | 2123 | .get_min_clock = sdhci_msm_get_min_clock, |
| 2124 | .get_max_clock = sdhci_msm_get_max_clock, |
Sahitya Tummala | 67717bc | 2013-08-02 09:21:37 +0530 | [diff] [blame] | 2125 | .dump_vendor_regs = sdhci_msm_dump_vendor_regs, |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 2126 | }; |
| 2127 | |
| 2128 | static int sdhci_msm_probe(struct platform_device *pdev) |
| 2129 | { |
| 2130 | struct sdhci_host *host; |
| 2131 | struct sdhci_pltfm_host *pltfm_host; |
| 2132 | struct sdhci_msm_host *msm_host; |
| 2133 | struct resource *core_memres = NULL; |
| 2134 | int ret = 0, pwr_irq = 0, dead = 0; |
Stephen Boyd | 8dce5c6 | 2013-04-24 14:19:46 -0700 | [diff] [blame] | 2135 | u16 host_version; |
Subhash Jadavani | 2813734 | 2013-05-14 17:46:43 +0530 | [diff] [blame] | 2136 | u32 pwr, irq_status, irq_ctl; |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 2137 | |
| 2138 | pr_debug("%s: Enter %s\n", dev_name(&pdev->dev), __func__); |
| 2139 | msm_host = devm_kzalloc(&pdev->dev, sizeof(struct sdhci_msm_host), |
| 2140 | GFP_KERNEL); |
| 2141 | if (!msm_host) { |
| 2142 | ret = -ENOMEM; |
| 2143 | goto out; |
| 2144 | } |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 2145 | |
| 2146 | msm_host->sdhci_msm_pdata.ops = &sdhci_msm_ops; |
| 2147 | host = sdhci_pltfm_init(pdev, &msm_host->sdhci_msm_pdata, 0); |
| 2148 | if (IS_ERR(host)) { |
| 2149 | ret = PTR_ERR(host); |
| 2150 | goto out; |
| 2151 | } |
| 2152 | |
| 2153 | pltfm_host = sdhci_priv(host); |
| 2154 | pltfm_host->priv = msm_host; |
| 2155 | msm_host->mmc = host->mmc; |
Sahitya Tummala | 8a3e818 | 2013-03-10 14:12:52 +0530 | [diff] [blame] | 2156 | msm_host->pdev = pdev; |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 2157 | |
| 2158 | /* Extract platform data */ |
| 2159 | if (pdev->dev.of_node) { |
Venkat Gopalakrishnan | 270580a | 2013-03-11 12:17:57 -0700 | [diff] [blame] | 2160 | ret = of_alias_get_id(pdev->dev.of_node, "sdhc"); |
| 2161 | if (ret < 0) { |
| 2162 | dev_err(&pdev->dev, "Failed to get slot index %d\n", |
| 2163 | ret); |
| 2164 | goto pltfm_free; |
| 2165 | } |
| 2166 | if (disable_slots & (1 << (ret - 1))) { |
| 2167 | dev_info(&pdev->dev, "%s: Slot %d disabled\n", __func__, |
| 2168 | ret); |
| 2169 | ret = -ENODEV; |
| 2170 | goto pltfm_free; |
| 2171 | } |
| 2172 | |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 2173 | msm_host->pdata = sdhci_msm_populate_pdata(&pdev->dev); |
| 2174 | if (!msm_host->pdata) { |
| 2175 | dev_err(&pdev->dev, "DT parsing error\n"); |
| 2176 | goto pltfm_free; |
| 2177 | } |
| 2178 | } else { |
| 2179 | dev_err(&pdev->dev, "No device tree node\n"); |
| 2180 | goto pltfm_free; |
| 2181 | } |
| 2182 | |
| 2183 | /* Setup Clocks */ |
| 2184 | |
| 2185 | /* Setup SDCC bus voter clock. */ |
| 2186 | msm_host->bus_clk = devm_clk_get(&pdev->dev, "bus_clk"); |
| 2187 | if (!IS_ERR_OR_NULL(msm_host->bus_clk)) { |
| 2188 | /* Vote for max. clk rate for max. performance */ |
| 2189 | ret = clk_set_rate(msm_host->bus_clk, INT_MAX); |
| 2190 | if (ret) |
| 2191 | goto pltfm_free; |
| 2192 | ret = clk_prepare_enable(msm_host->bus_clk); |
| 2193 | if (ret) |
| 2194 | goto pltfm_free; |
| 2195 | } |
| 2196 | |
| 2197 | /* Setup main peripheral bus clock */ |
| 2198 | msm_host->pclk = devm_clk_get(&pdev->dev, "iface_clk"); |
| 2199 | if (!IS_ERR(msm_host->pclk)) { |
| 2200 | ret = clk_prepare_enable(msm_host->pclk); |
| 2201 | if (ret) |
| 2202 | goto bus_clk_disable; |
| 2203 | } |
| 2204 | |
| 2205 | /* Setup SDC MMC clock */ |
| 2206 | msm_host->clk = devm_clk_get(&pdev->dev, "core_clk"); |
| 2207 | if (IS_ERR(msm_host->clk)) { |
| 2208 | ret = PTR_ERR(msm_host->clk); |
| 2209 | goto pclk_disable; |
| 2210 | } |
| 2211 | |
Sahitya Tummala | 22dd336 | 2013-02-28 19:50:51 +0530 | [diff] [blame] | 2212 | /* Set to the minimum supported clock frequency */ |
| 2213 | ret = clk_set_rate(msm_host->clk, sdhci_msm_get_min_clock(host)); |
| 2214 | if (ret) { |
| 2215 | dev_err(&pdev->dev, "MClk rate set failed (%d)\n", ret); |
Sahitya Tummala | 020ede0d | 2013-06-07 13:03:07 +0530 | [diff] [blame] | 2216 | goto pclk_disable; |
Sahitya Tummala | 22dd336 | 2013-02-28 19:50:51 +0530 | [diff] [blame] | 2217 | } |
Sahitya Tummala | 020ede0d | 2013-06-07 13:03:07 +0530 | [diff] [blame] | 2218 | ret = clk_prepare_enable(msm_host->clk); |
| 2219 | if (ret) |
| 2220 | goto pclk_disable; |
| 2221 | |
Sahitya Tummala | 22dd336 | 2013-02-28 19:50:51 +0530 | [diff] [blame] | 2222 | msm_host->clk_rate = sdhci_msm_get_min_clock(host); |
Sahitya Tummala | a7f3c57 | 2013-01-11 11:30:45 +0530 | [diff] [blame] | 2223 | atomic_set(&msm_host->clks_on, 1); |
Sahitya Tummala | 22dd336 | 2013-02-28 19:50:51 +0530 | [diff] [blame] | 2224 | |
Venkat Gopalakrishnan | 7f69157 | 2013-06-23 17:36:46 -0700 | [diff] [blame^] | 2225 | /* Setup CDC calibration fixed feedback clock */ |
| 2226 | msm_host->ff_clk = devm_clk_get(&pdev->dev, "cal_clk"); |
| 2227 | if (!IS_ERR(msm_host->ff_clk)) { |
| 2228 | ret = clk_prepare_enable(msm_host->ff_clk); |
| 2229 | if (ret) |
| 2230 | goto clk_disable; |
| 2231 | } |
| 2232 | |
| 2233 | /* Setup CDC calibration sleep clock */ |
| 2234 | msm_host->sleep_clk = devm_clk_get(&pdev->dev, "sleep_clk"); |
| 2235 | if (!IS_ERR(msm_host->sleep_clk)) { |
| 2236 | ret = clk_prepare_enable(msm_host->sleep_clk); |
| 2237 | if (ret) |
| 2238 | goto ff_clk_disable; |
| 2239 | } |
| 2240 | |
Sahitya Tummala | 79edc6a | 2013-05-23 15:59:22 +0530 | [diff] [blame] | 2241 | ret = sdhci_msm_bus_register(msm_host, pdev); |
| 2242 | if (ret) |
Venkat Gopalakrishnan | 7f69157 | 2013-06-23 17:36:46 -0700 | [diff] [blame^] | 2243 | goto sleep_clk_disable; |
Sahitya Tummala | 79edc6a | 2013-05-23 15:59:22 +0530 | [diff] [blame] | 2244 | |
| 2245 | if (msm_host->msm_bus_vote.client_handle) |
| 2246 | INIT_DELAYED_WORK(&msm_host->msm_bus_vote.vote_work, |
| 2247 | sdhci_msm_bus_work); |
| 2248 | sdhci_msm_bus_voting(host, 1); |
| 2249 | |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 2250 | /* Setup regulators */ |
| 2251 | ret = sdhci_msm_vreg_init(&pdev->dev, msm_host->pdata, true); |
| 2252 | if (ret) { |
| 2253 | dev_err(&pdev->dev, "Regulator setup failed (%d)\n", ret); |
Sahitya Tummala | 79edc6a | 2013-05-23 15:59:22 +0530 | [diff] [blame] | 2254 | goto bus_unregister; |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 2255 | } |
| 2256 | |
| 2257 | /* Reset the core and Enable SDHC mode */ |
| 2258 | core_memres = platform_get_resource_byname(pdev, |
| 2259 | IORESOURCE_MEM, "core_mem"); |
| 2260 | msm_host->core_mem = devm_ioremap(&pdev->dev, core_memres->start, |
| 2261 | resource_size(core_memres)); |
| 2262 | |
| 2263 | if (!msm_host->core_mem) { |
| 2264 | dev_err(&pdev->dev, "Failed to remap registers\n"); |
| 2265 | ret = -ENOMEM; |
| 2266 | goto vreg_deinit; |
| 2267 | } |
| 2268 | |
| 2269 | /* Set SW_RST bit in POWER register (Offset 0x0) */ |
Sahitya Tummala | 66b0fe3 | 2013-04-25 11:50:56 +0530 | [diff] [blame] | 2270 | writel_relaxed(readl_relaxed(msm_host->core_mem + CORE_POWER) | |
| 2271 | CORE_SW_RST, msm_host->core_mem + CORE_POWER); |
| 2272 | /* |
| 2273 | * SW reset can take upto 10HCLK + 15MCLK cycles. |
| 2274 | * Calculating based on min clk rates (hclk = 27MHz, |
| 2275 | * mclk = 400KHz) it comes to ~40us. Let's poll for |
| 2276 | * max. 1ms for reset completion. |
| 2277 | */ |
| 2278 | ret = readl_poll_timeout(msm_host->core_mem + CORE_POWER, |
| 2279 | pwr, !(pwr & CORE_SW_RST), 100, 10); |
| 2280 | |
| 2281 | if (ret) { |
| 2282 | dev_err(&pdev->dev, "reset failed (%d)\n", ret); |
| 2283 | goto vreg_deinit; |
| 2284 | } |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 2285 | /* Set HC_MODE_EN bit in HC_MODE register */ |
| 2286 | writel_relaxed(HC_MODE_EN, (msm_host->core_mem + CORE_HC_MODE)); |
| 2287 | |
Venkat Gopalakrishnan | 7f69157 | 2013-06-23 17:36:46 -0700 | [diff] [blame^] | 2288 | /* Set FF_CLK_SW_RST_DIS bit in HC_MODE register */ |
| 2289 | writel_relaxed(readl_relaxed(msm_host->core_mem + CORE_HC_MODE) | |
| 2290 | FF_CLK_SW_RST_DIS, msm_host->core_mem + CORE_HC_MODE); |
| 2291 | |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 2292 | /* |
Subhash Jadavani | 2813734 | 2013-05-14 17:46:43 +0530 | [diff] [blame] | 2293 | * CORE_SW_RST above may trigger power irq if previous status of PWRCTL |
| 2294 | * was either BUS_ON or IO_HIGH_V. So before we enable the power irq |
| 2295 | * interrupt in GIC (by registering the interrupt handler), we need to |
| 2296 | * ensure that any pending power irq interrupt status is acknowledged |
| 2297 | * otherwise power irq interrupt handler would be fired prematurely. |
| 2298 | */ |
| 2299 | irq_status = readl_relaxed(msm_host->core_mem + CORE_PWRCTL_STATUS); |
| 2300 | writel_relaxed(irq_status, (msm_host->core_mem + CORE_PWRCTL_CLEAR)); |
| 2301 | irq_ctl = readl_relaxed(msm_host->core_mem + CORE_PWRCTL_CTL); |
| 2302 | if (irq_status & (CORE_PWRCTL_BUS_ON | CORE_PWRCTL_BUS_OFF)) |
| 2303 | irq_ctl |= CORE_PWRCTL_BUS_SUCCESS; |
| 2304 | if (irq_status & (CORE_PWRCTL_IO_HIGH | CORE_PWRCTL_IO_LOW)) |
| 2305 | irq_ctl |= CORE_PWRCTL_IO_SUCCESS; |
| 2306 | writel_relaxed(irq_ctl, (msm_host->core_mem + CORE_PWRCTL_CTL)); |
| 2307 | /* |
| 2308 | * Ensure that above writes are propogated before interrupt enablement |
| 2309 | * in GIC. |
| 2310 | */ |
| 2311 | mb(); |
| 2312 | |
| 2313 | /* |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 2314 | * Following are the deviations from SDHC spec v3.0 - |
| 2315 | * 1. Card detection is handled using separate GPIO. |
| 2316 | * 2. Bus power control is handled by interacting with PMIC. |
| 2317 | */ |
| 2318 | host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION; |
| 2319 | host->quirks |= SDHCI_QUIRK_SINGLE_POWER_WRITE; |
Sahitya Tummala | 22dd336 | 2013-02-28 19:50:51 +0530 | [diff] [blame] | 2320 | host->quirks |= SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN; |
| 2321 | host->quirks2 |= SDHCI_QUIRK2_ALWAYS_USE_BASE_CLOCK; |
Sahitya Tummala | 87d4394 | 2013-04-12 11:49:11 +0530 | [diff] [blame] | 2322 | host->quirks2 |= SDHCI_QUIRK2_IGNORE_DATATOUT_FOR_R1BCMD; |
Sahitya Tummala | 314162c | 2013-04-12 12:11:20 +0530 | [diff] [blame] | 2323 | host->quirks2 |= SDHCI_QUIRK2_BROKEN_PRESET_VALUE; |
Sahitya Tummala | 7c9780d | 2013-04-12 11:59:25 +0530 | [diff] [blame] | 2324 | host->quirks2 |= SDHCI_QUIRK2_USE_RESERVED_MAX_TIMEOUT; |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 2325 | |
Sahitya Tummala | a5733ab5 | 2013-06-10 16:32:51 +0530 | [diff] [blame] | 2326 | if (host->quirks2 & SDHCI_QUIRK2_ALWAYS_USE_BASE_CLOCK) |
| 2327 | host->quirks2 |= SDHCI_QUIRK2_DIVIDE_TOUT_BY_4; |
| 2328 | |
Stephen Boyd | 8dce5c6 | 2013-04-24 14:19:46 -0700 | [diff] [blame] | 2329 | host_version = readw_relaxed((host->ioaddr + SDHCI_HOST_VERSION)); |
Venkat Gopalakrishnan | a58f91f | 2012-09-17 16:00:15 -0700 | [diff] [blame] | 2330 | dev_dbg(&pdev->dev, "Host Version: 0x%x Vendor Version 0x%x\n", |
| 2331 | host_version, ((host_version & SDHCI_VENDOR_VER_MASK) >> |
| 2332 | SDHCI_VENDOR_VER_SHIFT)); |
| 2333 | if (((host_version & SDHCI_VENDOR_VER_MASK) >> |
| 2334 | SDHCI_VENDOR_VER_SHIFT) == SDHCI_VER_100) { |
| 2335 | /* |
| 2336 | * Add 40us delay in interrupt handler when |
| 2337 | * operating at initialization frequency(400KHz). |
| 2338 | */ |
| 2339 | host->quirks2 |= SDHCI_QUIRK2_SLOW_INT_CLR; |
| 2340 | /* |
| 2341 | * Set Software Reset for DAT line in Software |
| 2342 | * Reset Register (Bit 2). |
| 2343 | */ |
| 2344 | host->quirks2 |= SDHCI_QUIRK2_RDWR_TX_ACTIVE_EOT; |
| 2345 | } |
| 2346 | |
Asutosh Das | 214b966 | 2013-06-13 14:27:42 +0530 | [diff] [blame] | 2347 | host->quirks2 |= SDHCI_QUIRK2_IGN_DATA_END_BIT_ERROR; |
| 2348 | |
Venkat Gopalakrishnan | a58f91f | 2012-09-17 16:00:15 -0700 | [diff] [blame] | 2349 | /* Setup PWRCTL irq */ |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 2350 | pwr_irq = platform_get_irq_byname(pdev, "pwr_irq"); |
| 2351 | if (pwr_irq < 0) { |
| 2352 | dev_err(&pdev->dev, "Failed to get pwr_irq by name (%d)\n", |
| 2353 | pwr_irq); |
| 2354 | goto vreg_deinit; |
| 2355 | } |
| 2356 | ret = devm_request_threaded_irq(&pdev->dev, pwr_irq, NULL, |
| 2357 | sdhci_msm_pwr_irq, IRQF_ONESHOT, |
Venkat Gopalakrishnan | 7944a37 | 2012-09-11 16:13:31 -0700 | [diff] [blame] | 2358 | dev_name(&pdev->dev), host); |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 2359 | if (ret) { |
| 2360 | dev_err(&pdev->dev, "Request threaded irq(%d) failed (%d)\n", |
| 2361 | pwr_irq, ret); |
| 2362 | goto vreg_deinit; |
| 2363 | } |
| 2364 | |
| 2365 | /* Enable pwr irq interrupts */ |
| 2366 | writel_relaxed(INT_MASK, (msm_host->core_mem + CORE_PWRCTL_MASK)); |
| 2367 | |
Sahitya Tummala | a7f3c57 | 2013-01-11 11:30:45 +0530 | [diff] [blame] | 2368 | #ifdef CONFIG_MMC_CLKGATE |
| 2369 | /* Set clock gating delay to be used when CONFIG_MMC_CLKGATE is set */ |
| 2370 | msm_host->mmc->clkgate_delay = SDHCI_MSM_MMC_CLK_GATE_DELAY; |
| 2371 | #endif |
| 2372 | |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 2373 | /* Set host capabilities */ |
| 2374 | msm_host->mmc->caps |= msm_host->pdata->mmc_bus_width; |
| 2375 | msm_host->mmc->caps |= msm_host->pdata->caps; |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 2376 | msm_host->mmc->caps2 |= msm_host->pdata->caps2; |
| 2377 | msm_host->mmc->caps2 |= MMC_CAP2_PACKED_WR; |
| 2378 | msm_host->mmc->caps2 |= MMC_CAP2_PACKED_WR_CONTROL; |
Sahitya Tummala | 22dd336 | 2013-02-28 19:50:51 +0530 | [diff] [blame] | 2379 | msm_host->mmc->caps2 |= MMC_CAP2_CLK_SCALE; |
Subhash Jadavani | 6d472b2 | 2013-05-29 15:52:10 +0530 | [diff] [blame] | 2380 | msm_host->mmc->caps2 |= MMC_CAP2_ASYNC_SDIO_IRQ_4BIT_MODE; |
Asutosh Das | bea115d | 2013-06-24 18:20:45 +0530 | [diff] [blame] | 2381 | msm_host->mmc->pm_caps |= MMC_PM_KEEP_POWER; |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 2382 | |
| 2383 | if (msm_host->pdata->nonremovable) |
| 2384 | msm_host->mmc->caps |= MMC_CAP_NONREMOVABLE; |
| 2385 | |
Sahitya Tummala | c6f48d4 | 2013-03-10 07:03:17 +0530 | [diff] [blame] | 2386 | host->cpu_dma_latency_us = msm_host->pdata->cpu_dma_latency_us; |
| 2387 | |
Sahitya Tummala | 1f52eaa | 2013-03-20 19:24:01 +0530 | [diff] [blame] | 2388 | init_completion(&msm_host->pwr_irq_completion); |
| 2389 | |
Sahitya Tummala | 581df13 | 2013-03-12 14:57:46 +0530 | [diff] [blame] | 2390 | if (gpio_is_valid(msm_host->pdata->status_gpio)) { |
| 2391 | ret = mmc_gpio_request_cd(msm_host->mmc, |
| 2392 | msm_host->pdata->status_gpio, 0); |
| 2393 | if (ret) { |
| 2394 | dev_err(&pdev->dev, "%s: Failed to request card detection IRQ %d\n", |
| 2395 | __func__, ret); |
Sahitya Tummala | 79edc6a | 2013-05-23 15:59:22 +0530 | [diff] [blame] | 2396 | goto vreg_deinit; |
Sahitya Tummala | 581df13 | 2013-03-12 14:57:46 +0530 | [diff] [blame] | 2397 | } |
| 2398 | } |
| 2399 | |
Sahitya Tummala | eaa2186 | 2013-03-20 19:34:59 +0530 | [diff] [blame] | 2400 | if (dma_supported(mmc_dev(host->mmc), DMA_BIT_MASK(32))) { |
| 2401 | host->dma_mask = DMA_BIT_MASK(32); |
| 2402 | mmc_dev(host->mmc)->dma_mask = &host->dma_mask; |
| 2403 | } else { |
| 2404 | dev_err(&pdev->dev, "%s: Failed to set dma mask\n", __func__); |
| 2405 | } |
| 2406 | |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 2407 | ret = sdhci_add_host(host); |
| 2408 | if (ret) { |
| 2409 | dev_err(&pdev->dev, "Add host failed (%d)\n", ret); |
Sahitya Tummala | 581df13 | 2013-03-12 14:57:46 +0530 | [diff] [blame] | 2410 | goto vreg_deinit; |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 2411 | } |
| 2412 | |
Sahitya Tummala | 8a3e818 | 2013-03-10 14:12:52 +0530 | [diff] [blame] | 2413 | msm_host->msm_bus_vote.max_bus_bw.show = show_sdhci_max_bus_bw; |
| 2414 | msm_host->msm_bus_vote.max_bus_bw.store = store_sdhci_max_bus_bw; |
| 2415 | sysfs_attr_init(&msm_host->msm_bus_vote.max_bus_bw.attr); |
| 2416 | msm_host->msm_bus_vote.max_bus_bw.attr.name = "max_bus_bw"; |
| 2417 | msm_host->msm_bus_vote.max_bus_bw.attr.mode = S_IRUGO | S_IWUSR; |
| 2418 | ret = device_create_file(&pdev->dev, |
| 2419 | &msm_host->msm_bus_vote.max_bus_bw); |
| 2420 | if (ret) |
| 2421 | goto remove_host; |
| 2422 | |
Sahitya Tummala | 5c55b93 | 2013-06-20 14:00:18 +0530 | [diff] [blame] | 2423 | if (!gpio_is_valid(msm_host->pdata->status_gpio)) { |
| 2424 | msm_host->polling.show = show_polling; |
| 2425 | msm_host->polling.store = store_polling; |
| 2426 | sysfs_attr_init(&msm_host->polling.attr); |
| 2427 | msm_host->polling.attr.name = "polling"; |
| 2428 | msm_host->polling.attr.mode = S_IRUGO | S_IWUSR; |
| 2429 | ret = device_create_file(&pdev->dev, &msm_host->polling); |
| 2430 | if (ret) |
| 2431 | goto remove_max_bus_bw_file; |
| 2432 | } |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 2433 | /* Successful initialization */ |
| 2434 | goto out; |
| 2435 | |
Sahitya Tummala | 5c55b93 | 2013-06-20 14:00:18 +0530 | [diff] [blame] | 2436 | remove_max_bus_bw_file: |
| 2437 | device_remove_file(&pdev->dev, &msm_host->msm_bus_vote.max_bus_bw); |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 2438 | remove_host: |
| 2439 | dead = (readl_relaxed(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff); |
| 2440 | sdhci_remove_host(host, dead); |
| 2441 | vreg_deinit: |
| 2442 | sdhci_msm_vreg_init(&pdev->dev, msm_host->pdata, false); |
Sahitya Tummala | 79edc6a | 2013-05-23 15:59:22 +0530 | [diff] [blame] | 2443 | bus_unregister: |
| 2444 | if (msm_host->msm_bus_vote.client_handle) |
| 2445 | sdhci_msm_bus_cancel_work_and_set_vote(host, 0); |
| 2446 | sdhci_msm_bus_unregister(msm_host); |
Venkat Gopalakrishnan | 7f69157 | 2013-06-23 17:36:46 -0700 | [diff] [blame^] | 2447 | sleep_clk_disable: |
| 2448 | if (!IS_ERR(msm_host->sleep_clk)) |
| 2449 | clk_disable_unprepare(msm_host->sleep_clk); |
| 2450 | ff_clk_disable: |
| 2451 | if (!IS_ERR(msm_host->ff_clk)) |
| 2452 | clk_disable_unprepare(msm_host->ff_clk); |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 2453 | clk_disable: |
| 2454 | if (!IS_ERR(msm_host->clk)) |
| 2455 | clk_disable_unprepare(msm_host->clk); |
| 2456 | pclk_disable: |
| 2457 | if (!IS_ERR(msm_host->pclk)) |
| 2458 | clk_disable_unprepare(msm_host->pclk); |
| 2459 | bus_clk_disable: |
| 2460 | if (!IS_ERR_OR_NULL(msm_host->bus_clk)) |
| 2461 | clk_disable_unprepare(msm_host->bus_clk); |
| 2462 | pltfm_free: |
| 2463 | sdhci_pltfm_free(pdev); |
| 2464 | out: |
| 2465 | pr_debug("%s: Exit %s\n", dev_name(&pdev->dev), __func__); |
| 2466 | return ret; |
| 2467 | } |
| 2468 | |
| 2469 | static int sdhci_msm_remove(struct platform_device *pdev) |
| 2470 | { |
| 2471 | struct sdhci_host *host = platform_get_drvdata(pdev); |
| 2472 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
| 2473 | struct sdhci_msm_host *msm_host = pltfm_host->priv; |
| 2474 | struct sdhci_msm_pltfm_data *pdata = msm_host->pdata; |
| 2475 | int dead = (readl_relaxed(host->ioaddr + SDHCI_INT_STATUS) == |
| 2476 | 0xffffffff); |
| 2477 | |
| 2478 | pr_debug("%s: %s\n", dev_name(&pdev->dev), __func__); |
Sahitya Tummala | 5c55b93 | 2013-06-20 14:00:18 +0530 | [diff] [blame] | 2479 | if (!gpio_is_valid(msm_host->pdata->status_gpio)) |
| 2480 | device_remove_file(&pdev->dev, &msm_host->polling); |
Sahitya Tummala | 8a3e818 | 2013-03-10 14:12:52 +0530 | [diff] [blame] | 2481 | device_remove_file(&pdev->dev, &msm_host->msm_bus_vote.max_bus_bw); |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 2482 | sdhci_remove_host(host, dead); |
| 2483 | sdhci_pltfm_free(pdev); |
Sahitya Tummala | 581df13 | 2013-03-12 14:57:46 +0530 | [diff] [blame] | 2484 | |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 2485 | sdhci_msm_vreg_init(&pdev->dev, msm_host->pdata, false); |
Sahitya Tummala | a7f3c57 | 2013-01-11 11:30:45 +0530 | [diff] [blame] | 2486 | |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 2487 | if (pdata->pin_data) |
| 2488 | sdhci_msm_setup_gpio(pdata, false); |
Sahitya Tummala | 8a3e818 | 2013-03-10 14:12:52 +0530 | [diff] [blame] | 2489 | |
| 2490 | if (msm_host->msm_bus_vote.client_handle) { |
| 2491 | sdhci_msm_bus_cancel_work_and_set_vote(host, 0); |
| 2492 | sdhci_msm_bus_unregister(msm_host); |
| 2493 | } |
Asutosh Das | 0ef2481 | 2012-12-18 16:14:02 +0530 | [diff] [blame] | 2494 | return 0; |
| 2495 | } |
| 2496 | |
| 2497 | static const struct of_device_id sdhci_msm_dt_match[] = { |
| 2498 | {.compatible = "qcom,sdhci-msm"}, |
| 2499 | }; |
| 2500 | MODULE_DEVICE_TABLE(of, sdhci_msm_dt_match); |
| 2501 | |
| 2502 | static struct platform_driver sdhci_msm_driver = { |
| 2503 | .probe = sdhci_msm_probe, |
| 2504 | .remove = sdhci_msm_remove, |
| 2505 | .driver = { |
| 2506 | .name = "sdhci_msm", |
| 2507 | .owner = THIS_MODULE, |
| 2508 | .of_match_table = sdhci_msm_dt_match, |
| 2509 | }, |
| 2510 | }; |
| 2511 | |
| 2512 | module_platform_driver(sdhci_msm_driver); |
| 2513 | |
| 2514 | MODULE_DESCRIPTION("Qualcomm Technologies, Inc. Secure Digital Host Controller Interface driver"); |
| 2515 | MODULE_LICENSE("GPL v2"); |