blob: 1bb59ae2d586ad1ea6c55d62ac0e52443880bdab [file] [log] [blame]
Joerg Roedelb6c02712008-06-26 21:27:53 +02001/*
Joerg Roedel5d0d7152010-10-13 11:13:21 +02002 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
Joerg Roedel63ce3ae2015-02-04 16:12:55 +01003 * Author: Joerg Roedel <jroedel@suse.de>
Joerg Roedelb6c02712008-06-26 21:27:53 +02004 * Leo Duran <leo.duran@amd.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
Joerg Roedel72e1dcc2011-11-10 19:13:51 +010020#include <linux/ratelimit.h>
Joerg Roedelb6c02712008-06-26 21:27:53 +020021#include <linux/pci.h>
Wan Zongshun2bf9a0a2016-04-01 09:06:03 -040022#include <linux/acpi.h>
Wan Zongshun9a4d3bf52016-04-01 09:06:05 -040023#include <linux/amba/bus.h>
Wan Zongshun0076cd32016-05-10 09:21:01 -040024#include <linux/platform_device.h>
Joerg Roedelcb41ed82011-04-05 11:00:53 +020025#include <linux/pci-ats.h>
Akinobu Mitaa66022c2009-12-15 16:48:28 -080026#include <linux/bitmap.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090027#include <linux/slab.h>
Joerg Roedel7f265082008-12-12 13:50:21 +010028#include <linux/debugfs.h>
Joerg Roedelb6c02712008-06-26 21:27:53 +020029#include <linux/scatterlist.h>
FUJITA Tomonori51491362009-01-05 23:47:25 +090030#include <linux/dma-mapping.h>
Joerg Roedelb6c02712008-06-26 21:27:53 +020031#include <linux/iommu-helper.h>
Joerg Roedelc156e342008-12-02 18:13:27 +010032#include <linux/iommu.h>
Joerg Roedel815b33f2011-04-06 17:26:49 +020033#include <linux/delay.h>
Joerg Roedel403f81d2011-06-14 16:44:25 +020034#include <linux/amd-iommu.h>
Joerg Roedel72e1dcc2011-11-10 19:13:51 +010035#include <linux/notifier.h>
36#include <linux/export.h>
Joerg Roedel2b324502012-06-21 16:29:10 +020037#include <linux/irq.h>
38#include <linux/msi.h>
Joerg Roedel3b839a52015-04-01 14:58:47 +020039#include <linux/dma-contiguous.h>
Jiang Liu7c71d302015-04-13 14:11:33 +080040#include <linux/irqdomain.h>
Joerg Roedel5f6bed52015-12-22 13:34:22 +010041#include <linux/percpu.h>
Joerg Roedel307d5852016-07-05 11:54:04 +020042#include <linux/iova.h>
Joerg Roedel2b324502012-06-21 16:29:10 +020043#include <asm/irq_remapping.h>
44#include <asm/io_apic.h>
45#include <asm/apic.h>
46#include <asm/hw_irq.h>
Joerg Roedel17f5b562011-07-06 17:14:44 +020047#include <asm/msidef.h>
Joerg Roedelb6c02712008-06-26 21:27:53 +020048#include <asm/proto.h>
FUJITA Tomonori46a7fa22008-07-11 10:23:42 +090049#include <asm/iommu.h>
Joerg Roedel1d9b16d2008-11-27 18:39:15 +010050#include <asm/gart.h>
Joerg Roedel27c21272011-05-30 15:56:24 +020051#include <asm/dma.h>
Joerg Roedel403f81d2011-06-14 16:44:25 +020052
53#include "amd_iommu_proto.h"
54#include "amd_iommu_types.h"
Joerg Roedel6b474b82012-06-26 16:46:04 +020055#include "irq_remapping.h"
Joerg Roedelb6c02712008-06-26 21:27:53 +020056
57#define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
58
Joerg Roedel815b33f2011-04-06 17:26:49 +020059#define LOOP_TIMEOUT 100000
Joerg Roedel136f78a2008-07-11 17:14:27 +020060
Joerg Roedel307d5852016-07-05 11:54:04 +020061/* IO virtual address start page frame number */
62#define IOVA_START_PFN (1)
63#define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT)
64#define DMA_32BIT_PFN IOVA_PFN(DMA_BIT_MASK(32))
65
Joerg Roedel81cd07b2016-07-07 18:01:10 +020066/* Reserved IOVA ranges */
67#define MSI_RANGE_START (0xfee00000)
68#define MSI_RANGE_END (0xfeefffff)
69#define HT_RANGE_START (0xfd00000000ULL)
70#define HT_RANGE_END (0xffffffffffULL)
71
Ohad Ben-Cohenaa3de9c2011-11-10 11:32:29 +020072/*
73 * This bitmap is used to advertise the page sizes our hardware support
74 * to the IOMMU core, which will then use this information to split
75 * physically contiguous memory regions it is mapping into page sizes
76 * that we support.
77 *
Joerg Roedel954e3dd2012-12-02 15:35:37 +010078 * 512GB Pages are not supported due to a hardware bug
Ohad Ben-Cohenaa3de9c2011-11-10 11:32:29 +020079 */
Joerg Roedel954e3dd2012-12-02 15:35:37 +010080#define AMD_IOMMU_PGSIZES ((~0xFFFUL) & ~(2ULL << 38))
Ohad Ben-Cohenaa3de9c2011-11-10 11:32:29 +020081
Joerg Roedelb6c02712008-06-26 21:27:53 +020082static DEFINE_RWLOCK(amd_iommu_devtable_lock);
83
Joerg Roedel8fa5f802011-06-09 12:24:45 +020084/* List of all available dev_data structures */
85static LIST_HEAD(dev_data_list);
86static DEFINE_SPINLOCK(dev_data_list_lock);
87
Joerg Roedel6efed632012-06-14 15:52:58 +020088LIST_HEAD(ioapic_map);
89LIST_HEAD(hpet_map);
Wan Zongshun2a0cb4e2016-04-01 09:06:00 -040090LIST_HEAD(acpihid_map);
Joerg Roedel6efed632012-06-14 15:52:58 +020091
Joerg Roedel0feae532009-08-26 15:26:30 +020092/*
93 * Domain for untranslated devices - only allocated
94 * if iommu=pt passed on kernel cmd line.
95 */
Thierry Redingb22f6432014-06-27 09:03:12 +020096static const struct iommu_ops amd_iommu_ops;
Joerg Roedel26961ef2008-12-03 17:00:17 +010097
Joerg Roedel72e1dcc2011-11-10 19:13:51 +010098static ATOMIC_NOTIFIER_HEAD(ppr_notifier);
Joerg Roedel52815b72011-11-17 17:24:28 +010099int amd_iommu_max_glx_val = -1;
Joerg Roedel72e1dcc2011-11-10 19:13:51 +0100100
Joerg Roedelac1534a2012-06-21 14:52:40 +0200101static struct dma_map_ops amd_iommu_dma_ops;
102
Joerg Roedel431b2a22008-07-11 17:14:22 +0200103/*
Joerg Roedel50917e22014-08-05 16:38:38 +0200104 * This struct contains device specific data for the IOMMU
105 */
106struct iommu_dev_data {
107 struct list_head list; /* For domain->dev_list */
108 struct list_head dev_data_list; /* For global dev_data_list */
Joerg Roedel50917e22014-08-05 16:38:38 +0200109 struct protection_domain *domain; /* Domain the device is bound to */
Joerg Roedel50917e22014-08-05 16:38:38 +0200110 u16 devid; /* PCI Device ID */
Joerg Roedele3156042016-04-08 15:12:24 +0200111 u16 alias; /* Alias Device ID */
Joerg Roedel50917e22014-08-05 16:38:38 +0200112 bool iommu_v2; /* Device can make use of IOMMUv2 */
Joerg Roedel1e6a7b02015-07-28 16:58:48 +0200113 bool passthrough; /* Device is identity mapped */
Joerg Roedel50917e22014-08-05 16:38:38 +0200114 struct {
115 bool enabled;
116 int qdep;
117 } ats; /* ATS state */
118 bool pri_tlp; /* PASID TLB required for
119 PPR completions */
120 u32 errata; /* Bitmap for errata to apply */
121};
122
123/*
Joerg Roedel431b2a22008-07-11 17:14:22 +0200124 * general struct to manage commands send to an IOMMU
125 */
Joerg Roedeld6449532008-07-11 17:14:28 +0200126struct iommu_cmd {
Joerg Roedelb6c02712008-06-26 21:27:53 +0200127 u32 data[4];
128};
129
Joerg Roedel05152a02012-06-15 16:53:51 +0200130struct kmem_cache *amd_iommu_irq_cache;
131
Joerg Roedel04bfdd82009-09-02 16:00:23 +0200132static void update_domain(struct protection_domain *domain);
Joerg Roedel7a5a5662015-06-30 08:56:11 +0200133static int protection_domain_init(struct protection_domain *domain);
Joerg Roedelb6809ee2016-02-26 16:48:59 +0100134static void detach_device(struct device *dev);
Chris Wrightc1eee672009-05-21 00:56:58 -0700135
Joerg Roedel007b74b2015-12-21 12:53:54 +0100136/*
137 * For dynamic growth the aperture size is split into ranges of 128MB of
138 * DMA address space each. This struct represents one such range.
139 */
140struct aperture_range {
141
Joerg Roedel08c5fb92015-12-21 13:04:49 +0100142 spinlock_t bitmap_lock;
143
Joerg Roedel007b74b2015-12-21 12:53:54 +0100144 /* address allocation bitmap */
145 unsigned long *bitmap;
Joerg Roedelae62d492015-12-21 16:28:45 +0100146 unsigned long offset;
Joerg Roedel60e6a7c2015-12-21 16:53:17 +0100147 unsigned long next_bit;
Joerg Roedel007b74b2015-12-21 12:53:54 +0100148
149 /*
150 * Array of PTE pages for the aperture. In this array we save all the
151 * leaf pages of the domain page table used for the aperture. This way
152 * we don't need to walk the page table to find a specific PTE. We can
153 * just calculate its address in constant time.
154 */
155 u64 *pte_pages[64];
Joerg Roedel007b74b2015-12-21 12:53:54 +0100156};
157
158/*
159 * Data container for a dma_ops specific protection domain
160 */
161struct dma_ops_domain {
162 /* generic protection domain information */
163 struct protection_domain domain;
164
165 /* size of the aperture for the mappings */
166 unsigned long aperture_size;
167
Joerg Roedelebaecb42015-12-21 18:11:32 +0100168 /* aperture index we start searching for free addresses */
Joerg Roedel5f6bed52015-12-22 13:34:22 +0100169 u32 __percpu *next_index;
Joerg Roedel007b74b2015-12-21 12:53:54 +0100170
171 /* address space relevant data */
172 struct aperture_range *aperture[APERTURE_MAX_RANGES];
Joerg Roedel307d5852016-07-05 11:54:04 +0200173
174 /* IOVA RB-Tree */
175 struct iova_domain iovad;
Joerg Roedel007b74b2015-12-21 12:53:54 +0100176};
177
Joerg Roedel81cd07b2016-07-07 18:01:10 +0200178static struct iova_domain reserved_iova_ranges;
179static struct lock_class_key reserved_rbtree_key;
180
Joerg Roedel15898bb2009-11-24 15:39:42 +0100181/****************************************************************************
182 *
183 * Helper functions
184 *
185 ****************************************************************************/
186
Wan Zongshun2bf9a0a2016-04-01 09:06:03 -0400187static inline int match_hid_uid(struct device *dev,
188 struct acpihid_map_entry *entry)
Joerg Roedel3f4b87b2015-03-26 13:43:07 +0100189{
Wan Zongshun2bf9a0a2016-04-01 09:06:03 -0400190 const char *hid, *uid;
191
192 hid = acpi_device_hid(ACPI_COMPANION(dev));
193 uid = acpi_device_uid(ACPI_COMPANION(dev));
194
195 if (!hid || !(*hid))
196 return -ENODEV;
197
198 if (!uid || !(*uid))
199 return strcmp(hid, entry->hid);
200
201 if (!(*entry->uid))
202 return strcmp(hid, entry->hid);
203
204 return (strcmp(hid, entry->hid) || strcmp(uid, entry->uid));
Joerg Roedel3f4b87b2015-03-26 13:43:07 +0100205}
206
Wan Zongshun2bf9a0a2016-04-01 09:06:03 -0400207static inline u16 get_pci_device_id(struct device *dev)
Joerg Roedele3156042016-04-08 15:12:24 +0200208{
209 struct pci_dev *pdev = to_pci_dev(dev);
210
211 return PCI_DEVID(pdev->bus->number, pdev->devfn);
212}
213
Wan Zongshun2bf9a0a2016-04-01 09:06:03 -0400214static inline int get_acpihid_device_id(struct device *dev,
215 struct acpihid_map_entry **entry)
216{
217 struct acpihid_map_entry *p;
218
219 list_for_each_entry(p, &acpihid_map, list) {
220 if (!match_hid_uid(dev, p)) {
221 if (entry)
222 *entry = p;
223 return p->devid;
224 }
225 }
226 return -EINVAL;
227}
228
229static inline int get_device_id(struct device *dev)
230{
231 int devid;
232
233 if (dev_is_pci(dev))
234 devid = get_pci_device_id(dev);
235 else
236 devid = get_acpihid_device_id(dev, NULL);
237
238 return devid;
239}
240
Joerg Roedel15898bb2009-11-24 15:39:42 +0100241static struct protection_domain *to_pdomain(struct iommu_domain *dom)
242{
243 return container_of(dom, struct protection_domain, domain);
244}
245
Joerg Roedelf62dda62011-06-09 12:55:35 +0200246static struct iommu_dev_data *alloc_dev_data(u16 devid)
Joerg Roedel8fa5f802011-06-09 12:24:45 +0200247{
248 struct iommu_dev_data *dev_data;
249 unsigned long flags;
250
251 dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL);
252 if (!dev_data)
253 return NULL;
254
Joerg Roedelf62dda62011-06-09 12:55:35 +0200255 dev_data->devid = devid;
Joerg Roedel8fa5f802011-06-09 12:24:45 +0200256
257 spin_lock_irqsave(&dev_data_list_lock, flags);
258 list_add_tail(&dev_data->dev_data_list, &dev_data_list);
259 spin_unlock_irqrestore(&dev_data_list_lock, flags);
260
261 return dev_data;
262}
263
Joerg Roedel3b03bb72011-06-09 18:53:25 +0200264static struct iommu_dev_data *search_dev_data(u16 devid)
265{
266 struct iommu_dev_data *dev_data;
267 unsigned long flags;
268
269 spin_lock_irqsave(&dev_data_list_lock, flags);
270 list_for_each_entry(dev_data, &dev_data_list, dev_data_list) {
271 if (dev_data->devid == devid)
272 goto out_unlock;
273 }
274
275 dev_data = NULL;
276
277out_unlock:
278 spin_unlock_irqrestore(&dev_data_list_lock, flags);
279
280 return dev_data;
281}
282
Joerg Roedele3156042016-04-08 15:12:24 +0200283static int __last_alias(struct pci_dev *pdev, u16 alias, void *data)
284{
285 *(u16 *)data = alias;
286 return 0;
287}
288
289static u16 get_alias(struct device *dev)
290{
291 struct pci_dev *pdev = to_pci_dev(dev);
292 u16 devid, ivrs_alias, pci_alias;
293
Joerg Roedel6c0b43d2016-05-09 19:39:17 +0200294 /* The callers make sure that get_device_id() does not fail here */
Joerg Roedele3156042016-04-08 15:12:24 +0200295 devid = get_device_id(dev);
296 ivrs_alias = amd_iommu_alias_table[devid];
297 pci_for_each_dma_alias(pdev, __last_alias, &pci_alias);
298
299 if (ivrs_alias == pci_alias)
300 return ivrs_alias;
301
302 /*
303 * DMA alias showdown
304 *
305 * The IVRS is fairly reliable in telling us about aliases, but it
306 * can't know about every screwy device. If we don't have an IVRS
307 * reported alias, use the PCI reported alias. In that case we may
308 * still need to initialize the rlookup and dev_table entries if the
309 * alias is to a non-existent device.
310 */
311 if (ivrs_alias == devid) {
312 if (!amd_iommu_rlookup_table[pci_alias]) {
313 amd_iommu_rlookup_table[pci_alias] =
314 amd_iommu_rlookup_table[devid];
315 memcpy(amd_iommu_dev_table[pci_alias].data,
316 amd_iommu_dev_table[devid].data,
317 sizeof(amd_iommu_dev_table[pci_alias].data));
318 }
319
320 return pci_alias;
321 }
322
323 pr_info("AMD-Vi: Using IVRS reported alias %02x:%02x.%d "
324 "for device %s[%04x:%04x], kernel reported alias "
325 "%02x:%02x.%d\n", PCI_BUS_NUM(ivrs_alias), PCI_SLOT(ivrs_alias),
326 PCI_FUNC(ivrs_alias), dev_name(dev), pdev->vendor, pdev->device,
327 PCI_BUS_NUM(pci_alias), PCI_SLOT(pci_alias),
328 PCI_FUNC(pci_alias));
329
330 /*
331 * If we don't have a PCI DMA alias and the IVRS alias is on the same
332 * bus, then the IVRS table may know about a quirk that we don't.
333 */
334 if (pci_alias == devid &&
335 PCI_BUS_NUM(ivrs_alias) == pdev->bus->number) {
Linus Torvalds7afd16f2016-05-19 13:10:54 -0700336 pci_add_dma_alias(pdev, ivrs_alias & 0xff);
Joerg Roedele3156042016-04-08 15:12:24 +0200337 pr_info("AMD-Vi: Added PCI DMA alias %02x.%d for %s\n",
338 PCI_SLOT(ivrs_alias), PCI_FUNC(ivrs_alias),
339 dev_name(dev));
340 }
341
342 return ivrs_alias;
343}
344
Joerg Roedel3b03bb72011-06-09 18:53:25 +0200345static struct iommu_dev_data *find_dev_data(u16 devid)
346{
347 struct iommu_dev_data *dev_data;
348
349 dev_data = search_dev_data(devid);
350
351 if (dev_data == NULL)
352 dev_data = alloc_dev_data(devid);
353
354 return dev_data;
355}
356
Joerg Roedel657cbb62009-11-23 15:26:46 +0100357static struct iommu_dev_data *get_dev_data(struct device *dev)
358{
359 return dev->archdata.iommu;
360}
361
Wan Zongshunb097d112016-04-01 09:06:04 -0400362/*
363* Find or create an IOMMU group for a acpihid device.
364*/
365static struct iommu_group *acpihid_device_group(struct device *dev)
366{
367 struct acpihid_map_entry *p, *entry = NULL;
Dan Carpenter2d8e1f02016-04-11 10:14:46 +0300368 int devid;
Wan Zongshunb097d112016-04-01 09:06:04 -0400369
370 devid = get_acpihid_device_id(dev, &entry);
371 if (devid < 0)
372 return ERR_PTR(devid);
373
374 list_for_each_entry(p, &acpihid_map, list) {
375 if ((devid == p->devid) && p->group)
376 entry->group = p->group;
377 }
378
379 if (!entry->group)
380 entry->group = generic_device_group(dev);
381
382 return entry->group;
383}
384
Joerg Roedel5abcdba2011-12-01 15:49:45 +0100385static bool pci_iommuv2_capable(struct pci_dev *pdev)
386{
387 static const int caps[] = {
388 PCI_EXT_CAP_ID_ATS,
Joerg Roedel46277b72011-12-07 14:34:02 +0100389 PCI_EXT_CAP_ID_PRI,
390 PCI_EXT_CAP_ID_PASID,
Joerg Roedel5abcdba2011-12-01 15:49:45 +0100391 };
392 int i, pos;
393
394 for (i = 0; i < 3; ++i) {
395 pos = pci_find_ext_capability(pdev, caps[i]);
396 if (pos == 0)
397 return false;
398 }
399
400 return true;
401}
402
Joerg Roedel6a113dd2011-12-01 12:04:58 +0100403static bool pdev_pri_erratum(struct pci_dev *pdev, u32 erratum)
404{
405 struct iommu_dev_data *dev_data;
406
407 dev_data = get_dev_data(&pdev->dev);
408
409 return dev_data->errata & (1 << erratum) ? true : false;
410}
411
Joerg Roedel71c70982009-11-24 16:43:06 +0100412/*
Joerg Roedel0bb6e242015-05-28 18:41:40 +0200413 * This function actually applies the mapping to the page table of the
414 * dma_ops domain.
Joerg Roedel71c70982009-11-24 16:43:06 +0100415 */
Joerg Roedel0bb6e242015-05-28 18:41:40 +0200416static void alloc_unity_mapping(struct dma_ops_domain *dma_dom,
417 struct unity_map_entry *e)
Joerg Roedel71c70982009-11-24 16:43:06 +0100418{
Joerg Roedel0bb6e242015-05-28 18:41:40 +0200419 u64 addr;
Joerg Roedel71c70982009-11-24 16:43:06 +0100420
Joerg Roedel0bb6e242015-05-28 18:41:40 +0200421 for (addr = e->address_start; addr < e->address_end;
422 addr += PAGE_SIZE) {
423 if (addr < dma_dom->aperture_size)
424 __set_bit(addr >> PAGE_SHIFT,
425 dma_dom->aperture[0]->bitmap);
Joerg Roedel71c70982009-11-24 16:43:06 +0100426 }
Joerg Roedel0bb6e242015-05-28 18:41:40 +0200427}
Joerg Roedel71c70982009-11-24 16:43:06 +0100428
Joerg Roedel0bb6e242015-05-28 18:41:40 +0200429/*
430 * Inits the unity mappings required for a specific device
431 */
432static void init_unity_mappings_for_device(struct device *dev,
433 struct dma_ops_domain *dma_dom)
434{
435 struct unity_map_entry *e;
Wan Zongshun7aba6cb2016-04-01 09:06:02 -0400436 int devid;
Joerg Roedel71c70982009-11-24 16:43:06 +0100437
Joerg Roedel0bb6e242015-05-28 18:41:40 +0200438 devid = get_device_id(dev);
Joerg Roedel9ee35e42016-04-21 18:21:31 +0200439 if (devid < 0)
Wan Zongshun7aba6cb2016-04-01 09:06:02 -0400440 return;
Joerg Roedel0bb6e242015-05-28 18:41:40 +0200441
442 list_for_each_entry(e, &amd_iommu_unity_map, list) {
443 if (!(devid >= e->devid_start && devid <= e->devid_end))
444 continue;
445 alloc_unity_mapping(dma_dom, e);
446 }
Joerg Roedel71c70982009-11-24 16:43:06 +0100447}
448
Joerg Roedel98fc5a62009-11-24 17:19:23 +0100449/*
450 * This function checks if the driver got a valid device from the caller to
451 * avoid dereferencing invalid pointers.
452 */
453static bool check_device(struct device *dev)
454{
Wan Zongshun7aba6cb2016-04-01 09:06:02 -0400455 int devid;
Joerg Roedel98fc5a62009-11-24 17:19:23 +0100456
457 if (!dev || !dev->dma_mask)
458 return false;
459
Joerg Roedel98fc5a62009-11-24 17:19:23 +0100460 devid = get_device_id(dev);
Joerg Roedel9ee35e42016-04-21 18:21:31 +0200461 if (devid < 0)
Wan Zongshun7aba6cb2016-04-01 09:06:02 -0400462 return false;
Joerg Roedel98fc5a62009-11-24 17:19:23 +0100463
464 /* Out of our scope? */
465 if (devid > amd_iommu_last_bdf)
466 return false;
467
468 if (amd_iommu_rlookup_table[devid] == NULL)
469 return false;
470
471 return true;
472}
473
Alex Williamson25b11ce2014-09-19 10:03:13 -0600474static void init_iommu_group(struct device *dev)
Alex Williamson2851db22012-10-08 22:49:41 -0600475{
Joerg Roedel0bb6e242015-05-28 18:41:40 +0200476 struct dma_ops_domain *dma_domain;
477 struct iommu_domain *domain;
Alex Williamson2851db22012-10-08 22:49:41 -0600478 struct iommu_group *group;
Alex Williamson2851db22012-10-08 22:49:41 -0600479
Alex Williamson65d53522014-07-03 09:51:30 -0600480 group = iommu_group_get_for_dev(dev);
Joerg Roedel0bb6e242015-05-28 18:41:40 +0200481 if (IS_ERR(group))
482 return;
483
484 domain = iommu_group_default_domain(group);
485 if (!domain)
486 goto out;
487
Joerg Roedelb548e782016-07-13 12:35:24 +0200488 if (to_pdomain(domain)->flags == PD_DMA_OPS_MASK) {
489 dma_domain = to_pdomain(domain)->priv;
490 init_unity_mappings_for_device(dev, dma_domain);
491 }
Joerg Roedel0bb6e242015-05-28 18:41:40 +0200492
Joerg Roedel0bb6e242015-05-28 18:41:40 +0200493out:
494 iommu_group_put(group);
Alex Williamsoneb9c9522012-10-08 22:49:35 -0600495}
496
497static int iommu_init_device(struct device *dev)
498{
Alex Williamsoneb9c9522012-10-08 22:49:35 -0600499 struct iommu_dev_data *dev_data;
Wan Zongshun7aba6cb2016-04-01 09:06:02 -0400500 int devid;
Alex Williamsoneb9c9522012-10-08 22:49:35 -0600501
502 if (dev->archdata.iommu)
503 return 0;
504
Wan Zongshun7aba6cb2016-04-01 09:06:02 -0400505 devid = get_device_id(dev);
Joerg Roedel9ee35e42016-04-21 18:21:31 +0200506 if (devid < 0)
Wan Zongshun7aba6cb2016-04-01 09:06:02 -0400507 return devid;
508
509 dev_data = find_dev_data(devid);
Alex Williamsoneb9c9522012-10-08 22:49:35 -0600510 if (!dev_data)
511 return -ENOMEM;
512
Joerg Roedele3156042016-04-08 15:12:24 +0200513 dev_data->alias = get_alias(dev);
514
Wan Zongshun2bf9a0a2016-04-01 09:06:03 -0400515 if (dev_is_pci(dev) && pci_iommuv2_capable(to_pci_dev(dev))) {
Joerg Roedel5abcdba2011-12-01 15:49:45 +0100516 struct amd_iommu *iommu;
517
Wan Zongshun2bf9a0a2016-04-01 09:06:03 -0400518 iommu = amd_iommu_rlookup_table[dev_data->devid];
Joerg Roedel5abcdba2011-12-01 15:49:45 +0100519 dev_data->iommu_v2 = iommu->is_iommu_v2;
520 }
521
Joerg Roedel657cbb62009-11-23 15:26:46 +0100522 dev->archdata.iommu = dev_data;
523
Alex Williamson066f2e92014-06-12 16:12:37 -0600524 iommu_device_link(amd_iommu_rlookup_table[dev_data->devid]->iommu_dev,
525 dev);
526
Joerg Roedel657cbb62009-11-23 15:26:46 +0100527 return 0;
528}
529
Joerg Roedel26018872011-06-06 16:50:14 +0200530static void iommu_ignore_device(struct device *dev)
531{
Wan Zongshun7aba6cb2016-04-01 09:06:02 -0400532 u16 alias;
533 int devid;
Joerg Roedel26018872011-06-06 16:50:14 +0200534
535 devid = get_device_id(dev);
Joerg Roedel9ee35e42016-04-21 18:21:31 +0200536 if (devid < 0)
Wan Zongshun7aba6cb2016-04-01 09:06:02 -0400537 return;
538
Joerg Roedele3156042016-04-08 15:12:24 +0200539 alias = get_alias(dev);
Joerg Roedel26018872011-06-06 16:50:14 +0200540
541 memset(&amd_iommu_dev_table[devid], 0, sizeof(struct dev_table_entry));
542 memset(&amd_iommu_dev_table[alias], 0, sizeof(struct dev_table_entry));
543
544 amd_iommu_rlookup_table[devid] = NULL;
545 amd_iommu_rlookup_table[alias] = NULL;
546}
547
Joerg Roedel657cbb62009-11-23 15:26:46 +0100548static void iommu_uninit_device(struct device *dev)
549{
Wan Zongshun7aba6cb2016-04-01 09:06:02 -0400550 int devid;
551 struct iommu_dev_data *dev_data;
Alex Williamsonc1931092014-07-03 09:51:24 -0600552
Wan Zongshun7aba6cb2016-04-01 09:06:02 -0400553 devid = get_device_id(dev);
Joerg Roedel9ee35e42016-04-21 18:21:31 +0200554 if (devid < 0)
Wan Zongshun7aba6cb2016-04-01 09:06:02 -0400555 return;
556
557 dev_data = search_dev_data(devid);
Alex Williamsonc1931092014-07-03 09:51:24 -0600558 if (!dev_data)
559 return;
560
Joerg Roedelb6809ee2016-02-26 16:48:59 +0100561 if (dev_data->domain)
562 detach_device(dev);
563
Alex Williamson066f2e92014-06-12 16:12:37 -0600564 iommu_device_unlink(amd_iommu_rlookup_table[dev_data->devid]->iommu_dev,
565 dev);
566
Alex Williamson9dcd6132012-05-30 14:19:07 -0600567 iommu_group_remove_device(dev);
568
Joerg Roedelaafd8ba2015-05-28 18:41:39 +0200569 /* Remove dma-ops */
570 dev->archdata.dma_ops = NULL;
571
Joerg Roedel8fa5f802011-06-09 12:24:45 +0200572 /*
Alex Williamsonc1931092014-07-03 09:51:24 -0600573 * We keep dev_data around for unplugged devices and reuse it when the
574 * device is re-plugged - not doing so would introduce a ton of races.
Joerg Roedel8fa5f802011-06-09 12:24:45 +0200575 */
Joerg Roedel657cbb62009-11-23 15:26:46 +0100576}
Joerg Roedelb7cc9552009-12-10 11:03:39 +0100577
Joerg Roedel431b2a22008-07-11 17:14:22 +0200578/****************************************************************************
579 *
Joerg Roedela80dc3e2008-09-11 16:51:41 +0200580 * Interrupt handling functions
581 *
582 ****************************************************************************/
583
Joerg Roedele3e59872009-09-03 14:02:10 +0200584static void dump_dte_entry(u16 devid)
585{
586 int i;
587
Joerg Roedelee6c2862011-11-09 12:06:03 +0100588 for (i = 0; i < 4; ++i)
589 pr_err("AMD-Vi: DTE[%d]: %016llx\n", i,
Joerg Roedele3e59872009-09-03 14:02:10 +0200590 amd_iommu_dev_table[devid].data[i]);
591}
592
Joerg Roedel945b4ac2009-09-03 14:25:02 +0200593static void dump_command(unsigned long phys_addr)
594{
595 struct iommu_cmd *cmd = phys_to_virt(phys_addr);
596 int i;
597
598 for (i = 0; i < 4; ++i)
599 pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]);
600}
601
Joerg Roedela345b232009-09-03 15:01:43 +0200602static void iommu_print_event(struct amd_iommu *iommu, void *__evt)
Joerg Roedel90008ee2008-09-09 16:41:05 +0200603{
Joerg Roedel3d06fca2012-04-12 14:12:00 +0200604 int type, devid, domid, flags;
605 volatile u32 *event = __evt;
606 int count = 0;
607 u64 address;
608
609retry:
610 type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
611 devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
612 domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK;
613 flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
614 address = (u64)(((u64)event[3]) << 32) | event[2];
615
616 if (type == 0) {
617 /* Did we hit the erratum? */
618 if (++count == LOOP_TIMEOUT) {
619 pr_err("AMD-Vi: No event written to event log\n");
620 return;
621 }
622 udelay(1);
623 goto retry;
624 }
Joerg Roedel90008ee2008-09-09 16:41:05 +0200625
Joerg Roedel4c6f40d2009-09-01 16:43:58 +0200626 printk(KERN_ERR "AMD-Vi: Event logged [");
Joerg Roedel90008ee2008-09-09 16:41:05 +0200627
628 switch (type) {
629 case EVENT_TYPE_ILL_DEV:
630 printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x "
631 "address=0x%016llx flags=0x%04x]\n",
Shuah Khanc5081cd2013-02-27 17:07:19 -0700632 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
Joerg Roedel90008ee2008-09-09 16:41:05 +0200633 address, flags);
Joerg Roedele3e59872009-09-03 14:02:10 +0200634 dump_dte_entry(devid);
Joerg Roedel90008ee2008-09-09 16:41:05 +0200635 break;
636 case EVENT_TYPE_IO_FAULT:
637 printk("IO_PAGE_FAULT device=%02x:%02x.%x "
638 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
Shuah Khanc5081cd2013-02-27 17:07:19 -0700639 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
Joerg Roedel90008ee2008-09-09 16:41:05 +0200640 domid, address, flags);
641 break;
642 case EVENT_TYPE_DEV_TAB_ERR:
643 printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
644 "address=0x%016llx flags=0x%04x]\n",
Shuah Khanc5081cd2013-02-27 17:07:19 -0700645 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
Joerg Roedel90008ee2008-09-09 16:41:05 +0200646 address, flags);
647 break;
648 case EVENT_TYPE_PAGE_TAB_ERR:
649 printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
650 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
Shuah Khanc5081cd2013-02-27 17:07:19 -0700651 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
Joerg Roedel90008ee2008-09-09 16:41:05 +0200652 domid, address, flags);
653 break;
654 case EVENT_TYPE_ILL_CMD:
655 printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address);
Joerg Roedel945b4ac2009-09-03 14:25:02 +0200656 dump_command(address);
Joerg Roedel90008ee2008-09-09 16:41:05 +0200657 break;
658 case EVENT_TYPE_CMD_HARD_ERR:
659 printk("COMMAND_HARDWARE_ERROR address=0x%016llx "
660 "flags=0x%04x]\n", address, flags);
661 break;
662 case EVENT_TYPE_IOTLB_INV_TO:
663 printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x "
664 "address=0x%016llx]\n",
Shuah Khanc5081cd2013-02-27 17:07:19 -0700665 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
Joerg Roedel90008ee2008-09-09 16:41:05 +0200666 address);
667 break;
668 case EVENT_TYPE_INV_DEV_REQ:
669 printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x "
670 "address=0x%016llx flags=0x%04x]\n",
Shuah Khanc5081cd2013-02-27 17:07:19 -0700671 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
Joerg Roedel90008ee2008-09-09 16:41:05 +0200672 address, flags);
673 break;
674 default:
675 printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type);
676 }
Joerg Roedel3d06fca2012-04-12 14:12:00 +0200677
678 memset(__evt, 0, 4 * sizeof(u32));
Joerg Roedel90008ee2008-09-09 16:41:05 +0200679}
680
681static void iommu_poll_events(struct amd_iommu *iommu)
682{
683 u32 head, tail;
Joerg Roedel90008ee2008-09-09 16:41:05 +0200684
685 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
686 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
687
688 while (head != tail) {
Joerg Roedela345b232009-09-03 15:01:43 +0200689 iommu_print_event(iommu, iommu->evt_buf + head);
Joerg Roedeldeba4bc2015-10-20 17:33:41 +0200690 head = (head + EVENT_ENTRY_SIZE) % EVT_BUFFER_SIZE;
Joerg Roedel90008ee2008-09-09 16:41:05 +0200691 }
692
693 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
Joerg Roedel90008ee2008-09-09 16:41:05 +0200694}
695
Joerg Roedeleee53532012-06-01 15:20:23 +0200696static void iommu_handle_ppr_entry(struct amd_iommu *iommu, u64 *raw)
Joerg Roedel72e1dcc2011-11-10 19:13:51 +0100697{
698 struct amd_iommu_fault fault;
Joerg Roedel72e1dcc2011-11-10 19:13:51 +0100699
Joerg Roedel72e1dcc2011-11-10 19:13:51 +0100700 if (PPR_REQ_TYPE(raw[0]) != PPR_REQ_FAULT) {
701 pr_err_ratelimited("AMD-Vi: Unknown PPR request received\n");
702 return;
703 }
704
705 fault.address = raw[1];
706 fault.pasid = PPR_PASID(raw[0]);
707 fault.device_id = PPR_DEVID(raw[0]);
708 fault.tag = PPR_TAG(raw[0]);
709 fault.flags = PPR_FLAGS(raw[0]);
710
Joerg Roedel72e1dcc2011-11-10 19:13:51 +0100711 atomic_notifier_call_chain(&ppr_notifier, 0, &fault);
712}
713
714static void iommu_poll_ppr_log(struct amd_iommu *iommu)
715{
Joerg Roedel72e1dcc2011-11-10 19:13:51 +0100716 u32 head, tail;
717
718 if (iommu->ppr_log == NULL)
719 return;
720
Joerg Roedel72e1dcc2011-11-10 19:13:51 +0100721 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
722 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
723
724 while (head != tail) {
Joerg Roedeleee53532012-06-01 15:20:23 +0200725 volatile u64 *raw;
726 u64 entry[2];
727 int i;
Joerg Roedel72e1dcc2011-11-10 19:13:51 +0100728
Joerg Roedeleee53532012-06-01 15:20:23 +0200729 raw = (u64 *)(iommu->ppr_log + head);
Joerg Roedel72e1dcc2011-11-10 19:13:51 +0100730
Joerg Roedeleee53532012-06-01 15:20:23 +0200731 /*
732 * Hardware bug: Interrupt may arrive before the entry is
733 * written to memory. If this happens we need to wait for the
734 * entry to arrive.
735 */
736 for (i = 0; i < LOOP_TIMEOUT; ++i) {
737 if (PPR_REQ_TYPE(raw[0]) != 0)
738 break;
739 udelay(1);
740 }
741
742 /* Avoid memcpy function-call overhead */
743 entry[0] = raw[0];
744 entry[1] = raw[1];
745
746 /*
747 * To detect the hardware bug we need to clear the entry
748 * back to zero.
749 */
750 raw[0] = raw[1] = 0UL;
751
752 /* Update head pointer of hardware ring-buffer */
Joerg Roedel72e1dcc2011-11-10 19:13:51 +0100753 head = (head + PPR_ENTRY_SIZE) % PPR_LOG_SIZE;
754 writel(head, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
Joerg Roedeleee53532012-06-01 15:20:23 +0200755
Joerg Roedeleee53532012-06-01 15:20:23 +0200756 /* Handle PPR entry */
757 iommu_handle_ppr_entry(iommu, entry);
758
Joerg Roedeleee53532012-06-01 15:20:23 +0200759 /* Refresh ring-buffer information */
760 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
Joerg Roedel72e1dcc2011-11-10 19:13:51 +0100761 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
762 }
Joerg Roedel72e1dcc2011-11-10 19:13:51 +0100763}
764
Joerg Roedel72fe00f2011-05-10 10:50:42 +0200765irqreturn_t amd_iommu_int_thread(int irq, void *data)
Joerg Roedela80dc3e2008-09-11 16:51:41 +0200766{
Suravee Suthikulpanit3f398bc2013-04-22 16:32:34 -0500767 struct amd_iommu *iommu = (struct amd_iommu *) data;
768 u32 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
Joerg Roedel90008ee2008-09-09 16:41:05 +0200769
Suravee Suthikulpanit3f398bc2013-04-22 16:32:34 -0500770 while (status & (MMIO_STATUS_EVT_INT_MASK | MMIO_STATUS_PPR_INT_MASK)) {
771 /* Enable EVT and PPR interrupts again */
772 writel((MMIO_STATUS_EVT_INT_MASK | MMIO_STATUS_PPR_INT_MASK),
773 iommu->mmio_base + MMIO_STATUS_OFFSET);
774
775 if (status & MMIO_STATUS_EVT_INT_MASK) {
776 pr_devel("AMD-Vi: Processing IOMMU Event Log\n");
777 iommu_poll_events(iommu);
778 }
779
780 if (status & MMIO_STATUS_PPR_INT_MASK) {
781 pr_devel("AMD-Vi: Processing IOMMU PPR Log\n");
782 iommu_poll_ppr_log(iommu);
783 }
784
785 /*
786 * Hardware bug: ERBT1312
787 * When re-enabling interrupt (by writing 1
788 * to clear the bit), the hardware might also try to set
789 * the interrupt bit in the event status register.
790 * In this scenario, the bit will be set, and disable
791 * subsequent interrupts.
792 *
793 * Workaround: The IOMMU driver should read back the
794 * status register and check if the interrupt bits are cleared.
795 * If not, driver will need to go through the interrupt handler
796 * again and re-clear the bits
797 */
798 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
Joerg Roedel72e1dcc2011-11-10 19:13:51 +0100799 }
Joerg Roedel90008ee2008-09-09 16:41:05 +0200800 return IRQ_HANDLED;
Joerg Roedela80dc3e2008-09-11 16:51:41 +0200801}
802
Joerg Roedel72fe00f2011-05-10 10:50:42 +0200803irqreturn_t amd_iommu_int_handler(int irq, void *data)
804{
805 return IRQ_WAKE_THREAD;
806}
807
Joerg Roedela80dc3e2008-09-11 16:51:41 +0200808/****************************************************************************
809 *
Joerg Roedel431b2a22008-07-11 17:14:22 +0200810 * IOMMU command queuing functions
811 *
812 ****************************************************************************/
813
Joerg Roedelac0ea6e2011-04-06 18:38:20 +0200814static int wait_on_sem(volatile u64 *sem)
Joerg Roedela19ae1e2008-06-26 21:27:55 +0200815{
Joerg Roedelac0ea6e2011-04-06 18:38:20 +0200816 int i = 0;
Joerg Roedela19ae1e2008-06-26 21:27:55 +0200817
Joerg Roedelac0ea6e2011-04-06 18:38:20 +0200818 while (*sem == 0 && i < LOOP_TIMEOUT) {
819 udelay(1);
820 i += 1;
821 }
822
823 if (i == LOOP_TIMEOUT) {
824 pr_alert("AMD-Vi: Completion-Wait loop timed out\n");
825 return -EIO;
826 }
Joerg Roedela19ae1e2008-06-26 21:27:55 +0200827
828 return 0;
829}
830
Joerg Roedelac0ea6e2011-04-06 18:38:20 +0200831static void copy_cmd_to_buffer(struct amd_iommu *iommu,
832 struct iommu_cmd *cmd,
833 u32 tail)
Joerg Roedela19ae1e2008-06-26 21:27:55 +0200834{
Joerg Roedelac0ea6e2011-04-06 18:38:20 +0200835 u8 *target;
Joerg Roedela19ae1e2008-06-26 21:27:55 +0200836
Joerg Roedelac0ea6e2011-04-06 18:38:20 +0200837 target = iommu->cmd_buf + tail;
Joerg Roedeldeba4bc2015-10-20 17:33:41 +0200838 tail = (tail + sizeof(*cmd)) % CMD_BUFFER_SIZE;
Joerg Roedela19ae1e2008-06-26 21:27:55 +0200839
Joerg Roedelac0ea6e2011-04-06 18:38:20 +0200840 /* Copy command to buffer */
841 memcpy(target, cmd, sizeof(*cmd));
842
843 /* Tell the IOMMU about it */
844 writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
845}
846
Joerg Roedel815b33f2011-04-06 17:26:49 +0200847static void build_completion_wait(struct iommu_cmd *cmd, u64 address)
Joerg Roedelded46732011-04-06 10:53:48 +0200848{
Joerg Roedel815b33f2011-04-06 17:26:49 +0200849 WARN_ON(address & 0x7ULL);
850
Joerg Roedelded46732011-04-06 10:53:48 +0200851 memset(cmd, 0, sizeof(*cmd));
Joerg Roedel815b33f2011-04-06 17:26:49 +0200852 cmd->data[0] = lower_32_bits(__pa(address)) | CMD_COMPL_WAIT_STORE_MASK;
853 cmd->data[1] = upper_32_bits(__pa(address));
854 cmd->data[2] = 1;
Joerg Roedelded46732011-04-06 10:53:48 +0200855 CMD_SET_TYPE(cmd, CMD_COMPL_WAIT);
856}
857
Joerg Roedel94fe79e2011-04-06 11:07:21 +0200858static void build_inv_dte(struct iommu_cmd *cmd, u16 devid)
859{
860 memset(cmd, 0, sizeof(*cmd));
861 cmd->data[0] = devid;
862 CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY);
863}
864
Joerg Roedel11b64022011-04-06 11:49:28 +0200865static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
866 size_t size, u16 domid, int pde)
867{
868 u64 pages;
Quentin Lambertae0cbbb2015-02-04 11:40:07 +0100869 bool s;
Joerg Roedel11b64022011-04-06 11:49:28 +0200870
871 pages = iommu_num_pages(address, size, PAGE_SIZE);
Quentin Lambertae0cbbb2015-02-04 11:40:07 +0100872 s = false;
Joerg Roedel11b64022011-04-06 11:49:28 +0200873
874 if (pages > 1) {
875 /*
876 * If we have to flush more than one page, flush all
877 * TLB entries for this domain
878 */
879 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
Quentin Lambertae0cbbb2015-02-04 11:40:07 +0100880 s = true;
Joerg Roedel11b64022011-04-06 11:49:28 +0200881 }
882
883 address &= PAGE_MASK;
884
885 memset(cmd, 0, sizeof(*cmd));
886 cmd->data[1] |= domid;
887 cmd->data[2] = lower_32_bits(address);
888 cmd->data[3] = upper_32_bits(address);
889 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
890 if (s) /* size bit - we flush more than one 4kb page */
891 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
Frank Arnolddf805ab2012-08-27 19:21:04 +0200892 if (pde) /* PDE bit - we want to flush everything, not only the PTEs */
Joerg Roedel11b64022011-04-06 11:49:28 +0200893 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
894}
895
Joerg Roedelcb41ed82011-04-05 11:00:53 +0200896static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep,
897 u64 address, size_t size)
898{
899 u64 pages;
Quentin Lambertae0cbbb2015-02-04 11:40:07 +0100900 bool s;
Joerg Roedelcb41ed82011-04-05 11:00:53 +0200901
902 pages = iommu_num_pages(address, size, PAGE_SIZE);
Quentin Lambertae0cbbb2015-02-04 11:40:07 +0100903 s = false;
Joerg Roedelcb41ed82011-04-05 11:00:53 +0200904
905 if (pages > 1) {
906 /*
907 * If we have to flush more than one page, flush all
908 * TLB entries for this domain
909 */
910 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
Quentin Lambertae0cbbb2015-02-04 11:40:07 +0100911 s = true;
Joerg Roedelcb41ed82011-04-05 11:00:53 +0200912 }
913
914 address &= PAGE_MASK;
915
916 memset(cmd, 0, sizeof(*cmd));
917 cmd->data[0] = devid;
918 cmd->data[0] |= (qdep & 0xff) << 24;
919 cmd->data[1] = devid;
920 cmd->data[2] = lower_32_bits(address);
921 cmd->data[3] = upper_32_bits(address);
922 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
923 if (s)
924 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
925}
926
Joerg Roedel22e266c2011-11-21 15:59:08 +0100927static void build_inv_iommu_pasid(struct iommu_cmd *cmd, u16 domid, int pasid,
928 u64 address, bool size)
929{
930 memset(cmd, 0, sizeof(*cmd));
931
932 address &= ~(0xfffULL);
933
Suravee Suthikulpanita919a012014-03-05 18:54:18 -0600934 cmd->data[0] = pasid;
Joerg Roedel22e266c2011-11-21 15:59:08 +0100935 cmd->data[1] = domid;
936 cmd->data[2] = lower_32_bits(address);
937 cmd->data[3] = upper_32_bits(address);
938 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
939 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
940 if (size)
941 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
942 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
943}
944
945static void build_inv_iotlb_pasid(struct iommu_cmd *cmd, u16 devid, int pasid,
946 int qdep, u64 address, bool size)
947{
948 memset(cmd, 0, sizeof(*cmd));
949
950 address &= ~(0xfffULL);
951
952 cmd->data[0] = devid;
Jay Cornwalle8d2d822014-02-26 15:49:31 -0600953 cmd->data[0] |= ((pasid >> 8) & 0xff) << 16;
Joerg Roedel22e266c2011-11-21 15:59:08 +0100954 cmd->data[0] |= (qdep & 0xff) << 24;
955 cmd->data[1] = devid;
Jay Cornwalle8d2d822014-02-26 15:49:31 -0600956 cmd->data[1] |= (pasid & 0xff) << 16;
Joerg Roedel22e266c2011-11-21 15:59:08 +0100957 cmd->data[2] = lower_32_bits(address);
958 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
959 cmd->data[3] = upper_32_bits(address);
960 if (size)
961 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
962 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
963}
964
Joerg Roedelc99afa22011-11-21 18:19:25 +0100965static void build_complete_ppr(struct iommu_cmd *cmd, u16 devid, int pasid,
966 int status, int tag, bool gn)
967{
968 memset(cmd, 0, sizeof(*cmd));
969
970 cmd->data[0] = devid;
971 if (gn) {
Suravee Suthikulpanita919a012014-03-05 18:54:18 -0600972 cmd->data[1] = pasid;
Joerg Roedelc99afa22011-11-21 18:19:25 +0100973 cmd->data[2] = CMD_INV_IOMMU_PAGES_GN_MASK;
974 }
975 cmd->data[3] = tag & 0x1ff;
976 cmd->data[3] |= (status & PPR_STATUS_MASK) << PPR_STATUS_SHIFT;
977
978 CMD_SET_TYPE(cmd, CMD_COMPLETE_PPR);
979}
980
Joerg Roedel58fc7f12011-04-11 11:13:24 +0200981static void build_inv_all(struct iommu_cmd *cmd)
982{
983 memset(cmd, 0, sizeof(*cmd));
984 CMD_SET_TYPE(cmd, CMD_INV_ALL);
Joerg Roedela19ae1e2008-06-26 21:27:55 +0200985}
986
Joerg Roedel7ef27982012-06-21 16:46:04 +0200987static void build_inv_irt(struct iommu_cmd *cmd, u16 devid)
988{
989 memset(cmd, 0, sizeof(*cmd));
990 cmd->data[0] = devid;
991 CMD_SET_TYPE(cmd, CMD_INV_IRT);
992}
993
Joerg Roedel431b2a22008-07-11 17:14:22 +0200994/*
Joerg Roedelb6c02712008-06-26 21:27:53 +0200995 * Writes the command to the IOMMUs command buffer and informs the
Joerg Roedelac0ea6e2011-04-06 18:38:20 +0200996 * hardware about the new command.
Joerg Roedel431b2a22008-07-11 17:14:22 +0200997 */
Joerg Roedelf1ca1512011-09-02 14:10:32 +0200998static int iommu_queue_command_sync(struct amd_iommu *iommu,
999 struct iommu_cmd *cmd,
1000 bool sync)
Joerg Roedela19ae1e2008-06-26 21:27:55 +02001001{
Joerg Roedelac0ea6e2011-04-06 18:38:20 +02001002 u32 left, tail, head, next_tail;
Joerg Roedel815b33f2011-04-06 17:26:49 +02001003 unsigned long flags;
Joerg Roedela19ae1e2008-06-26 21:27:55 +02001004
Joerg Roedelac0ea6e2011-04-06 18:38:20 +02001005again:
Joerg Roedel815b33f2011-04-06 17:26:49 +02001006 spin_lock_irqsave(&iommu->lock, flags);
Joerg Roedelac0ea6e2011-04-06 18:38:20 +02001007
1008 head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
1009 tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
Joerg Roedeldeba4bc2015-10-20 17:33:41 +02001010 next_tail = (tail + sizeof(*cmd)) % CMD_BUFFER_SIZE;
1011 left = (head - next_tail) % CMD_BUFFER_SIZE;
Joerg Roedelac0ea6e2011-04-06 18:38:20 +02001012
1013 if (left <= 2) {
1014 struct iommu_cmd sync_cmd;
1015 volatile u64 sem = 0;
1016 int ret;
1017
1018 build_completion_wait(&sync_cmd, (u64)&sem);
1019 copy_cmd_to_buffer(iommu, &sync_cmd, tail);
1020
1021 spin_unlock_irqrestore(&iommu->lock, flags);
1022
1023 if ((ret = wait_on_sem(&sem)) != 0)
1024 return ret;
1025
1026 goto again;
Joerg Roedel136f78a2008-07-11 17:14:27 +02001027 }
1028
Joerg Roedelac0ea6e2011-04-06 18:38:20 +02001029 copy_cmd_to_buffer(iommu, cmd, tail);
Joerg Roedel519c31b2008-08-14 19:55:15 +02001030
Joerg Roedelac0ea6e2011-04-06 18:38:20 +02001031 /* We need to sync now to make sure all commands are processed */
Joerg Roedelf1ca1512011-09-02 14:10:32 +02001032 iommu->need_sync = sync;
Joerg Roedelac0ea6e2011-04-06 18:38:20 +02001033
Joerg Roedela19ae1e2008-06-26 21:27:55 +02001034 spin_unlock_irqrestore(&iommu->lock, flags);
1035
Joerg Roedel815b33f2011-04-06 17:26:49 +02001036 return 0;
Joerg Roedel8d201962008-12-02 20:34:41 +01001037}
1038
Joerg Roedelf1ca1512011-09-02 14:10:32 +02001039static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
1040{
1041 return iommu_queue_command_sync(iommu, cmd, true);
1042}
1043
Joerg Roedel8d201962008-12-02 20:34:41 +01001044/*
1045 * This function queues a completion wait command into the command
1046 * buffer of an IOMMU
1047 */
Joerg Roedel8d201962008-12-02 20:34:41 +01001048static int iommu_completion_wait(struct amd_iommu *iommu)
1049{
Joerg Roedel815b33f2011-04-06 17:26:49 +02001050 struct iommu_cmd cmd;
1051 volatile u64 sem = 0;
Joerg Roedelac0ea6e2011-04-06 18:38:20 +02001052 int ret;
Joerg Roedel8d201962008-12-02 20:34:41 +01001053
1054 if (!iommu->need_sync)
Joerg Roedel815b33f2011-04-06 17:26:49 +02001055 return 0;
Joerg Roedel8d201962008-12-02 20:34:41 +01001056
Joerg Roedel815b33f2011-04-06 17:26:49 +02001057 build_completion_wait(&cmd, (u64)&sem);
Joerg Roedel8d201962008-12-02 20:34:41 +01001058
Joerg Roedelf1ca1512011-09-02 14:10:32 +02001059 ret = iommu_queue_command_sync(iommu, &cmd, false);
Joerg Roedel8d201962008-12-02 20:34:41 +01001060 if (ret)
Joerg Roedel815b33f2011-04-06 17:26:49 +02001061 return ret;
Joerg Roedel8d201962008-12-02 20:34:41 +01001062
Joerg Roedelac0ea6e2011-04-06 18:38:20 +02001063 return wait_on_sem(&sem);
Joerg Roedela19ae1e2008-06-26 21:27:55 +02001064}
1065
Joerg Roedeld8c13082011-04-06 18:51:26 +02001066static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid)
Joerg Roedela19ae1e2008-06-26 21:27:55 +02001067{
1068 struct iommu_cmd cmd;
1069
Joerg Roedeld8c13082011-04-06 18:51:26 +02001070 build_inv_dte(&cmd, devid);
Joerg Roedela19ae1e2008-06-26 21:27:55 +02001071
Joerg Roedeld8c13082011-04-06 18:51:26 +02001072 return iommu_queue_command(iommu, &cmd);
1073}
1074
Joerg Roedel7d0c5cc2011-04-07 08:16:10 +02001075static void iommu_flush_dte_all(struct amd_iommu *iommu)
1076{
1077 u32 devid;
1078
1079 for (devid = 0; devid <= 0xffff; ++devid)
1080 iommu_flush_dte(iommu, devid);
1081
1082 iommu_completion_wait(iommu);
Joerg Roedela19ae1e2008-06-26 21:27:55 +02001083}
1084
1085/*
Joerg Roedel7d0c5cc2011-04-07 08:16:10 +02001086 * This function uses heavy locking and may disable irqs for some time. But
1087 * this is no issue because it is only called during resume.
Joerg Roedela19ae1e2008-06-26 21:27:55 +02001088 */
Joerg Roedel7d0c5cc2011-04-07 08:16:10 +02001089static void iommu_flush_tlb_all(struct amd_iommu *iommu)
Joerg Roedela19ae1e2008-06-26 21:27:55 +02001090{
Joerg Roedel7d0c5cc2011-04-07 08:16:10 +02001091 u32 dom_id;
Joerg Roedela19ae1e2008-06-26 21:27:55 +02001092
Joerg Roedel7d0c5cc2011-04-07 08:16:10 +02001093 for (dom_id = 0; dom_id <= 0xffff; ++dom_id) {
1094 struct iommu_cmd cmd;
1095 build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
1096 dom_id, 1);
1097 iommu_queue_command(iommu, &cmd);
1098 }
Joerg Roedel431b2a22008-07-11 17:14:22 +02001099
Joerg Roedel7d0c5cc2011-04-07 08:16:10 +02001100 iommu_completion_wait(iommu);
Joerg Roedela19ae1e2008-06-26 21:27:55 +02001101}
1102
Joerg Roedel58fc7f12011-04-11 11:13:24 +02001103static void iommu_flush_all(struct amd_iommu *iommu)
1104{
1105 struct iommu_cmd cmd;
1106
1107 build_inv_all(&cmd);
1108
1109 iommu_queue_command(iommu, &cmd);
1110 iommu_completion_wait(iommu);
1111}
1112
Joerg Roedel7ef27982012-06-21 16:46:04 +02001113static void iommu_flush_irt(struct amd_iommu *iommu, u16 devid)
1114{
1115 struct iommu_cmd cmd;
1116
1117 build_inv_irt(&cmd, devid);
1118
1119 iommu_queue_command(iommu, &cmd);
1120}
1121
1122static void iommu_flush_irt_all(struct amd_iommu *iommu)
1123{
1124 u32 devid;
1125
1126 for (devid = 0; devid <= MAX_DEV_TABLE_ENTRIES; devid++)
1127 iommu_flush_irt(iommu, devid);
1128
1129 iommu_completion_wait(iommu);
1130}
1131
Joerg Roedel7d0c5cc2011-04-07 08:16:10 +02001132void iommu_flush_all_caches(struct amd_iommu *iommu)
1133{
Joerg Roedel58fc7f12011-04-11 11:13:24 +02001134 if (iommu_feature(iommu, FEATURE_IA)) {
1135 iommu_flush_all(iommu);
1136 } else {
1137 iommu_flush_dte_all(iommu);
Joerg Roedel7ef27982012-06-21 16:46:04 +02001138 iommu_flush_irt_all(iommu);
Joerg Roedel58fc7f12011-04-11 11:13:24 +02001139 iommu_flush_tlb_all(iommu);
1140 }
Joerg Roedel7d0c5cc2011-04-07 08:16:10 +02001141}
1142
Joerg Roedel431b2a22008-07-11 17:14:22 +02001143/*
Joerg Roedelcb41ed82011-04-05 11:00:53 +02001144 * Command send function for flushing on-device TLB
1145 */
Joerg Roedel6c542042011-06-09 17:07:31 +02001146static int device_flush_iotlb(struct iommu_dev_data *dev_data,
1147 u64 address, size_t size)
Joerg Roedelcb41ed82011-04-05 11:00:53 +02001148{
Joerg Roedelcb41ed82011-04-05 11:00:53 +02001149 struct amd_iommu *iommu;
1150 struct iommu_cmd cmd;
Joerg Roedelcb41ed82011-04-05 11:00:53 +02001151 int qdep;
1152
Joerg Roedelea61cdd2011-06-09 12:56:30 +02001153 qdep = dev_data->ats.qdep;
1154 iommu = amd_iommu_rlookup_table[dev_data->devid];
Joerg Roedelcb41ed82011-04-05 11:00:53 +02001155
Joerg Roedelea61cdd2011-06-09 12:56:30 +02001156 build_inv_iotlb_pages(&cmd, dev_data->devid, qdep, address, size);
Joerg Roedelcb41ed82011-04-05 11:00:53 +02001157
1158 return iommu_queue_command(iommu, &cmd);
1159}
1160
1161/*
Joerg Roedel431b2a22008-07-11 17:14:22 +02001162 * Command send function for invalidating a device table entry
1163 */
Joerg Roedel6c542042011-06-09 17:07:31 +02001164static int device_flush_dte(struct iommu_dev_data *dev_data)
Joerg Roedel3fa43652009-11-26 15:04:38 +01001165{
1166 struct amd_iommu *iommu;
Joerg Roedele25bfb52015-10-20 17:33:38 +02001167 u16 alias;
Joerg Roedelcb41ed82011-04-05 11:00:53 +02001168 int ret;
Joerg Roedel3fa43652009-11-26 15:04:38 +01001169
Joerg Roedel6c542042011-06-09 17:07:31 +02001170 iommu = amd_iommu_rlookup_table[dev_data->devid];
Joerg Roedele3156042016-04-08 15:12:24 +02001171 alias = dev_data->alias;
Joerg Roedel3fa43652009-11-26 15:04:38 +01001172
Joerg Roedelf62dda62011-06-09 12:55:35 +02001173 ret = iommu_flush_dte(iommu, dev_data->devid);
Joerg Roedele25bfb52015-10-20 17:33:38 +02001174 if (!ret && alias != dev_data->devid)
1175 ret = iommu_flush_dte(iommu, alias);
Joerg Roedelcb41ed82011-04-05 11:00:53 +02001176 if (ret)
1177 return ret;
1178
Joerg Roedelea61cdd2011-06-09 12:56:30 +02001179 if (dev_data->ats.enabled)
Joerg Roedel6c542042011-06-09 17:07:31 +02001180 ret = device_flush_iotlb(dev_data, 0, ~0UL);
Joerg Roedelcb41ed82011-04-05 11:00:53 +02001181
1182 return ret;
Joerg Roedel3fa43652009-11-26 15:04:38 +01001183}
1184
Joerg Roedel431b2a22008-07-11 17:14:22 +02001185/*
1186 * TLB invalidation function which is called from the mapping functions.
1187 * It invalidates a single PTE if the range to flush is within a single
1188 * page. Otherwise it flushes the whole TLB of the IOMMU.
1189 */
Joerg Roedel17b124b2011-04-06 18:01:35 +02001190static void __domain_flush_pages(struct protection_domain *domain,
1191 u64 address, size_t size, int pde)
Joerg Roedela19ae1e2008-06-26 21:27:55 +02001192{
Joerg Roedelcb41ed82011-04-05 11:00:53 +02001193 struct iommu_dev_data *dev_data;
Joerg Roedel11b64022011-04-06 11:49:28 +02001194 struct iommu_cmd cmd;
1195 int ret = 0, i;
Joerg Roedela19ae1e2008-06-26 21:27:55 +02001196
Joerg Roedel11b64022011-04-06 11:49:28 +02001197 build_inv_iommu_pages(&cmd, address, size, domain->id, pde);
Joerg Roedel999ba412008-07-03 19:35:08 +02001198
Joerg Roedel6de8ad92009-11-23 18:30:32 +01001199 for (i = 0; i < amd_iommus_present; ++i) {
1200 if (!domain->dev_iommu[i])
1201 continue;
1202
1203 /*
1204 * Devices of this domain are behind this IOMMU
1205 * We need a TLB flush
1206 */
Joerg Roedel11b64022011-04-06 11:49:28 +02001207 ret |= iommu_queue_command(amd_iommus[i], &cmd);
Joerg Roedel6de8ad92009-11-23 18:30:32 +01001208 }
1209
Joerg Roedelcb41ed82011-04-05 11:00:53 +02001210 list_for_each_entry(dev_data, &domain->dev_list, list) {
Joerg Roedelcb41ed82011-04-05 11:00:53 +02001211
Joerg Roedelea61cdd2011-06-09 12:56:30 +02001212 if (!dev_data->ats.enabled)
Joerg Roedelcb41ed82011-04-05 11:00:53 +02001213 continue;
1214
Joerg Roedel6c542042011-06-09 17:07:31 +02001215 ret |= device_flush_iotlb(dev_data, address, size);
Joerg Roedelcb41ed82011-04-05 11:00:53 +02001216 }
1217
Joerg Roedel11b64022011-04-06 11:49:28 +02001218 WARN_ON(ret);
Joerg Roedel6de8ad92009-11-23 18:30:32 +01001219}
1220
Joerg Roedel17b124b2011-04-06 18:01:35 +02001221static void domain_flush_pages(struct protection_domain *domain,
1222 u64 address, size_t size)
Joerg Roedel6de8ad92009-11-23 18:30:32 +01001223{
Joerg Roedel17b124b2011-04-06 18:01:35 +02001224 __domain_flush_pages(domain, address, size, 0);
Joerg Roedela19ae1e2008-06-26 21:27:55 +02001225}
Joerg Roedelb6c02712008-06-26 21:27:53 +02001226
Joerg Roedel1c655772008-09-04 18:40:05 +02001227/* Flush the whole IO/TLB for a given protection domain */
Joerg Roedel17b124b2011-04-06 18:01:35 +02001228static void domain_flush_tlb(struct protection_domain *domain)
Joerg Roedel1c655772008-09-04 18:40:05 +02001229{
Joerg Roedel17b124b2011-04-06 18:01:35 +02001230 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0);
Joerg Roedel1c655772008-09-04 18:40:05 +02001231}
1232
Chris Wright42a49f92009-06-15 15:42:00 +02001233/* Flush the whole IO/TLB for a given protection domain - including PDE */
Joerg Roedel17b124b2011-04-06 18:01:35 +02001234static void domain_flush_tlb_pde(struct protection_domain *domain)
Chris Wright42a49f92009-06-15 15:42:00 +02001235{
Joerg Roedel17b124b2011-04-06 18:01:35 +02001236 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1);
1237}
1238
1239static void domain_flush_complete(struct protection_domain *domain)
Joerg Roedelb6c02712008-06-26 21:27:53 +02001240{
1241 int i;
1242
1243 for (i = 0; i < amd_iommus_present; ++i) {
1244 if (!domain->dev_iommu[i])
1245 continue;
1246
1247 /*
1248 * Devices of this domain are behind this IOMMU
1249 * We need to wait for completion of all commands.
1250 */
1251 iommu_completion_wait(amd_iommus[i]);
1252 }
1253}
1254
Joerg Roedelb00d3bc2009-11-26 15:35:33 +01001255
Joerg Roedel43f49602008-12-02 21:01:12 +01001256/*
Joerg Roedelb00d3bc2009-11-26 15:35:33 +01001257 * This function flushes the DTEs for all devices in domain
Joerg Roedel43f49602008-12-02 21:01:12 +01001258 */
Joerg Roedel17b124b2011-04-06 18:01:35 +02001259static void domain_flush_devices(struct protection_domain *domain)
Joerg Roedelbfd1be12009-05-05 15:33:57 +02001260{
Joerg Roedelb00d3bc2009-11-26 15:35:33 +01001261 struct iommu_dev_data *dev_data;
Joerg Roedelb00d3bc2009-11-26 15:35:33 +01001262
1263 list_for_each_entry(dev_data, &domain->dev_list, list)
Joerg Roedel6c542042011-06-09 17:07:31 +02001264 device_flush_dte(dev_data);
Joerg Roedelb00d3bc2009-11-26 15:35:33 +01001265}
1266
Joerg Roedel431b2a22008-07-11 17:14:22 +02001267/****************************************************************************
1268 *
1269 * The functions below are used the create the page table mappings for
1270 * unity mapped regions.
1271 *
1272 ****************************************************************************/
1273
1274/*
Joerg Roedel308973d2009-11-24 17:43:32 +01001275 * This function is used to add another level to an IO page table. Adding
1276 * another level increases the size of the address space by 9 bits to a size up
1277 * to 64 bits.
1278 */
1279static bool increase_address_space(struct protection_domain *domain,
1280 gfp_t gfp)
1281{
1282 u64 *pte;
1283
1284 if (domain->mode == PAGE_MODE_6_LEVEL)
1285 /* address space already 64 bit large */
1286 return false;
1287
1288 pte = (void *)get_zeroed_page(gfp);
1289 if (!pte)
1290 return false;
1291
1292 *pte = PM_LEVEL_PDE(domain->mode,
1293 virt_to_phys(domain->pt_root));
1294 domain->pt_root = pte;
1295 domain->mode += 1;
1296 domain->updated = true;
1297
1298 return true;
1299}
1300
1301static u64 *alloc_pte(struct protection_domain *domain,
1302 unsigned long address,
Joerg Roedelcbb9d722010-01-15 14:41:15 +01001303 unsigned long page_size,
Joerg Roedel308973d2009-11-24 17:43:32 +01001304 u64 **pte_page,
1305 gfp_t gfp)
1306{
Joerg Roedelcbb9d722010-01-15 14:41:15 +01001307 int level, end_lvl;
Joerg Roedel308973d2009-11-24 17:43:32 +01001308 u64 *pte, *page;
Joerg Roedelcbb9d722010-01-15 14:41:15 +01001309
1310 BUG_ON(!is_power_of_2(page_size));
Joerg Roedel308973d2009-11-24 17:43:32 +01001311
1312 while (address > PM_LEVEL_SIZE(domain->mode))
1313 increase_address_space(domain, gfp);
1314
Joerg Roedelcbb9d722010-01-15 14:41:15 +01001315 level = domain->mode - 1;
1316 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1317 address = PAGE_SIZE_ALIGN(address, page_size);
1318 end_lvl = PAGE_SIZE_LEVEL(page_size);
Joerg Roedel308973d2009-11-24 17:43:32 +01001319
1320 while (level > end_lvl) {
Joerg Roedel7bfa5bd2015-12-21 19:07:50 +01001321 u64 __pte, __npte;
1322
1323 __pte = *pte;
1324
1325 if (!IOMMU_PTE_PRESENT(__pte)) {
Joerg Roedel308973d2009-11-24 17:43:32 +01001326 page = (u64 *)get_zeroed_page(gfp);
1327 if (!page)
1328 return NULL;
Joerg Roedel7bfa5bd2015-12-21 19:07:50 +01001329
1330 __npte = PM_LEVEL_PDE(level, virt_to_phys(page));
1331
1332 if (cmpxchg64(pte, __pte, __npte)) {
1333 free_page((unsigned long)page);
1334 continue;
1335 }
Joerg Roedel308973d2009-11-24 17:43:32 +01001336 }
1337
Joerg Roedelcbb9d722010-01-15 14:41:15 +01001338 /* No level skipping support yet */
1339 if (PM_PTE_LEVEL(*pte) != level)
1340 return NULL;
1341
Joerg Roedel308973d2009-11-24 17:43:32 +01001342 level -= 1;
1343
1344 pte = IOMMU_PTE_PAGE(*pte);
1345
1346 if (pte_page && level == end_lvl)
1347 *pte_page = pte;
1348
1349 pte = &pte[PM_LEVEL_INDEX(level, address)];
1350 }
1351
1352 return pte;
1353}
1354
1355/*
1356 * This function checks if there is a PTE for a given dma address. If
1357 * there is one, it returns the pointer to it.
1358 */
Joerg Roedel3039ca12015-04-01 14:58:48 +02001359static u64 *fetch_pte(struct protection_domain *domain,
1360 unsigned long address,
1361 unsigned long *page_size)
Joerg Roedel308973d2009-11-24 17:43:32 +01001362{
1363 int level;
1364 u64 *pte;
1365
Joerg Roedel24cd7722010-01-19 17:27:39 +01001366 if (address > PM_LEVEL_SIZE(domain->mode))
1367 return NULL;
Joerg Roedel308973d2009-11-24 17:43:32 +01001368
Joerg Roedel3039ca12015-04-01 14:58:48 +02001369 level = domain->mode - 1;
1370 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1371 *page_size = PTE_LEVEL_PAGE_SIZE(level);
Joerg Roedel24cd7722010-01-19 17:27:39 +01001372
1373 while (level > 0) {
1374
1375 /* Not Present */
Joerg Roedel308973d2009-11-24 17:43:32 +01001376 if (!IOMMU_PTE_PRESENT(*pte))
1377 return NULL;
1378
Joerg Roedel24cd7722010-01-19 17:27:39 +01001379 /* Large PTE */
Joerg Roedel3039ca12015-04-01 14:58:48 +02001380 if (PM_PTE_LEVEL(*pte) == 7 ||
1381 PM_PTE_LEVEL(*pte) == 0)
1382 break;
Joerg Roedel24cd7722010-01-19 17:27:39 +01001383
1384 /* No level skipping support yet */
1385 if (PM_PTE_LEVEL(*pte) != level)
1386 return NULL;
1387
Joerg Roedel308973d2009-11-24 17:43:32 +01001388 level -= 1;
1389
Joerg Roedel24cd7722010-01-19 17:27:39 +01001390 /* Walk to the next level */
Joerg Roedel3039ca12015-04-01 14:58:48 +02001391 pte = IOMMU_PTE_PAGE(*pte);
1392 pte = &pte[PM_LEVEL_INDEX(level, address)];
1393 *page_size = PTE_LEVEL_PAGE_SIZE(level);
1394 }
1395
1396 if (PM_PTE_LEVEL(*pte) == 0x07) {
1397 unsigned long pte_mask;
1398
1399 /*
1400 * If we have a series of large PTEs, make
1401 * sure to return a pointer to the first one.
1402 */
1403 *page_size = pte_mask = PTE_PAGE_SIZE(*pte);
1404 pte_mask = ~((PAGE_SIZE_PTE_COUNT(pte_mask) << 3) - 1);
1405 pte = (u64 *)(((unsigned long)pte) & pte_mask);
Joerg Roedel308973d2009-11-24 17:43:32 +01001406 }
1407
1408 return pte;
1409}
1410
1411/*
Joerg Roedel431b2a22008-07-11 17:14:22 +02001412 * Generic mapping functions. It maps a physical address into a DMA
1413 * address space. It allocates the page table pages if necessary.
1414 * In the future it can be extended to a generic mapping function
1415 * supporting all features of AMD IOMMU page tables like level skipping
1416 * and full 64 bit address spaces.
1417 */
Joerg Roedel38e817f2008-12-02 17:27:52 +01001418static int iommu_map_page(struct protection_domain *dom,
1419 unsigned long bus_addr,
1420 unsigned long phys_addr,
Joerg Roedelabdc5eb2009-09-03 11:33:51 +02001421 int prot,
Joerg Roedelcbb9d722010-01-15 14:41:15 +01001422 unsigned long page_size)
Joerg Roedelbd0e5212008-06-26 21:27:56 +02001423{
Joerg Roedel8bda3092009-05-12 12:02:46 +02001424 u64 __pte, *pte;
Joerg Roedelcbb9d722010-01-15 14:41:15 +01001425 int i, count;
Joerg Roedelabdc5eb2009-09-03 11:33:51 +02001426
Joerg Roedeld4b03662015-04-01 14:58:52 +02001427 BUG_ON(!IS_ALIGNED(bus_addr, page_size));
1428 BUG_ON(!IS_ALIGNED(phys_addr, page_size));
1429
Joerg Roedelbad1cac2009-09-02 16:52:23 +02001430 if (!(prot & IOMMU_PROT_MASK))
Joerg Roedelbd0e5212008-06-26 21:27:56 +02001431 return -EINVAL;
1432
Joerg Roedeld4b03662015-04-01 14:58:52 +02001433 count = PAGE_SIZE_PTE_COUNT(page_size);
1434 pte = alloc_pte(dom, bus_addr, page_size, NULL, GFP_KERNEL);
Joerg Roedelbd0e5212008-06-26 21:27:56 +02001435
Maurizio Lombardi63eaa752014-09-11 12:28:03 +02001436 if (!pte)
1437 return -ENOMEM;
1438
Joerg Roedelcbb9d722010-01-15 14:41:15 +01001439 for (i = 0; i < count; ++i)
1440 if (IOMMU_PTE_PRESENT(pte[i]))
1441 return -EBUSY;
Joerg Roedelbd0e5212008-06-26 21:27:56 +02001442
Joerg Roedeld4b03662015-04-01 14:58:52 +02001443 if (count > 1) {
Joerg Roedelcbb9d722010-01-15 14:41:15 +01001444 __pte = PAGE_SIZE_PTE(phys_addr, page_size);
1445 __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_P | IOMMU_PTE_FC;
1446 } else
1447 __pte = phys_addr | IOMMU_PTE_P | IOMMU_PTE_FC;
1448
Joerg Roedelbd0e5212008-06-26 21:27:56 +02001449 if (prot & IOMMU_PROT_IR)
1450 __pte |= IOMMU_PTE_IR;
1451 if (prot & IOMMU_PROT_IW)
1452 __pte |= IOMMU_PTE_IW;
1453
Joerg Roedelcbb9d722010-01-15 14:41:15 +01001454 for (i = 0; i < count; ++i)
1455 pte[i] = __pte;
Joerg Roedelbd0e5212008-06-26 21:27:56 +02001456
Joerg Roedel04bfdd82009-09-02 16:00:23 +02001457 update_domain(dom);
1458
Joerg Roedelbd0e5212008-06-26 21:27:56 +02001459 return 0;
1460}
1461
Joerg Roedel24cd7722010-01-19 17:27:39 +01001462static unsigned long iommu_unmap_page(struct protection_domain *dom,
1463 unsigned long bus_addr,
1464 unsigned long page_size)
Joerg Roedeleb74ff62008-12-02 19:59:10 +01001465{
Joerg Roedel71b390e2015-04-01 14:58:49 +02001466 unsigned long long unmapped;
1467 unsigned long unmap_size;
Joerg Roedel24cd7722010-01-19 17:27:39 +01001468 u64 *pte;
Joerg Roedeleb74ff62008-12-02 19:59:10 +01001469
Joerg Roedel24cd7722010-01-19 17:27:39 +01001470 BUG_ON(!is_power_of_2(page_size));
1471
1472 unmapped = 0;
1473
1474 while (unmapped < page_size) {
1475
Joerg Roedel71b390e2015-04-01 14:58:49 +02001476 pte = fetch_pte(dom, bus_addr, &unmap_size);
Joerg Roedel24cd7722010-01-19 17:27:39 +01001477
Joerg Roedel71b390e2015-04-01 14:58:49 +02001478 if (pte) {
1479 int i, count;
Joerg Roedel24cd7722010-01-19 17:27:39 +01001480
Joerg Roedel71b390e2015-04-01 14:58:49 +02001481 count = PAGE_SIZE_PTE_COUNT(unmap_size);
Joerg Roedel24cd7722010-01-19 17:27:39 +01001482 for (i = 0; i < count; i++)
1483 pte[i] = 0ULL;
1484 }
1485
1486 bus_addr = (bus_addr & ~(unmap_size - 1)) + unmap_size;
1487 unmapped += unmap_size;
1488 }
1489
Alex Williamson60d0ca32013-06-21 14:33:19 -06001490 BUG_ON(unmapped && !is_power_of_2(unmapped));
Joerg Roedel24cd7722010-01-19 17:27:39 +01001491
1492 return unmapped;
Joerg Roedeleb74ff62008-12-02 19:59:10 +01001493}
Joerg Roedeleb74ff62008-12-02 19:59:10 +01001494
Joerg Roedel431b2a22008-07-11 17:14:22 +02001495/****************************************************************************
1496 *
1497 * The next functions belong to the address allocator for the dma_ops
1498 * interface functions. They work like the allocators in the other IOMMU
1499 * drivers. Its basically a bitmap which marks the allocated pages in
1500 * the aperture. Maybe it could be enhanced in the future to a more
1501 * efficient allocator.
1502 *
1503 ****************************************************************************/
Joerg Roedeld3086442008-06-26 21:27:57 +02001504
Joerg Roedel431b2a22008-07-11 17:14:22 +02001505/*
Joerg Roedel384de722009-05-15 12:30:05 +02001506 * The address allocator core functions.
Joerg Roedel431b2a22008-07-11 17:14:22 +02001507 *
1508 * called with domain->lock held
1509 */
Joerg Roedel384de722009-05-15 12:30:05 +02001510
Joerg Roedel9cabe892009-05-18 16:38:55 +02001511/*
Joerg Roedel171e7b32009-11-24 17:47:56 +01001512 * Used to reserve address ranges in the aperture (e.g. for exclusion
1513 * ranges.
1514 */
1515static void dma_ops_reserve_addresses(struct dma_ops_domain *dom,
1516 unsigned long start_page,
1517 unsigned int pages)
1518{
1519 unsigned int i, last_page = dom->aperture_size >> PAGE_SHIFT;
1520
1521 if (start_page + pages > last_page)
1522 pages = last_page - start_page;
1523
1524 for (i = start_page; i < start_page + pages; ++i) {
1525 int index = i / APERTURE_RANGE_PAGES;
1526 int page = i % APERTURE_RANGE_PAGES;
1527 __set_bit(page, dom->aperture[index]->bitmap);
1528 }
1529}
1530
1531/*
Joerg Roedel9cabe892009-05-18 16:38:55 +02001532 * This function is used to add a new aperture range to an existing
1533 * aperture in case of dma_ops domain allocation or address allocation
1534 * failure.
1535 */
Joerg Roedel576175c2009-11-23 19:08:46 +01001536static int alloc_new_range(struct dma_ops_domain *dma_dom,
Joerg Roedel9cabe892009-05-18 16:38:55 +02001537 bool populate, gfp_t gfp)
1538{
1539 int index = dma_dom->aperture_size >> APERTURE_RANGE_SHIFT;
Joerg Roedel5d7c94c2015-04-01 14:58:50 +02001540 unsigned long i, old_size, pte_pgsize;
Joerg Roedela73c1562015-12-21 19:25:56 +01001541 struct aperture_range *range;
1542 struct amd_iommu *iommu;
1543 unsigned long flags;
Joerg Roedel9cabe892009-05-18 16:38:55 +02001544
Joerg Roedelf5e97052009-05-22 12:31:53 +02001545#ifdef CONFIG_IOMMU_STRESS
1546 populate = false;
1547#endif
1548
Joerg Roedel9cabe892009-05-18 16:38:55 +02001549 if (index >= APERTURE_MAX_RANGES)
1550 return -ENOMEM;
1551
Joerg Roedela73c1562015-12-21 19:25:56 +01001552 range = kzalloc(sizeof(struct aperture_range), gfp);
1553 if (!range)
Joerg Roedel9cabe892009-05-18 16:38:55 +02001554 return -ENOMEM;
1555
Joerg Roedela73c1562015-12-21 19:25:56 +01001556 range->bitmap = (void *)get_zeroed_page(gfp);
1557 if (!range->bitmap)
Joerg Roedel9cabe892009-05-18 16:38:55 +02001558 goto out_free;
1559
Joerg Roedela73c1562015-12-21 19:25:56 +01001560 range->offset = dma_dom->aperture_size;
Joerg Roedel9cabe892009-05-18 16:38:55 +02001561
Joerg Roedela73c1562015-12-21 19:25:56 +01001562 spin_lock_init(&range->bitmap_lock);
Joerg Roedel08c5fb92015-12-21 13:04:49 +01001563
Joerg Roedel9cabe892009-05-18 16:38:55 +02001564 if (populate) {
1565 unsigned long address = dma_dom->aperture_size;
1566 int i, num_ptes = APERTURE_RANGE_PAGES / 512;
1567 u64 *pte, *pte_page;
1568
1569 for (i = 0; i < num_ptes; ++i) {
Joerg Roedelcbb9d722010-01-15 14:41:15 +01001570 pte = alloc_pte(&dma_dom->domain, address, PAGE_SIZE,
Joerg Roedel9cabe892009-05-18 16:38:55 +02001571 &pte_page, gfp);
1572 if (!pte)
1573 goto out_free;
1574
Joerg Roedela73c1562015-12-21 19:25:56 +01001575 range->pte_pages[i] = pte_page;
Joerg Roedel9cabe892009-05-18 16:38:55 +02001576
1577 address += APERTURE_RANGE_SIZE / 64;
1578 }
1579 }
1580
Joerg Roedel92d420e2015-12-21 19:31:33 +01001581 spin_lock_irqsave(&dma_dom->domain.lock, flags);
1582
Joerg Roedela73c1562015-12-21 19:25:56 +01001583 /* First take the bitmap_lock and then publish the range */
Joerg Roedel92d420e2015-12-21 19:31:33 +01001584 spin_lock(&range->bitmap_lock);
Joerg Roedela73c1562015-12-21 19:25:56 +01001585
1586 old_size = dma_dom->aperture_size;
1587 dma_dom->aperture[index] = range;
1588 dma_dom->aperture_size += APERTURE_RANGE_SIZE;
Joerg Roedel9cabe892009-05-18 16:38:55 +02001589
Joerg Roedel17f5b562011-07-06 17:14:44 +02001590 /* Reserve address range used for MSI messages */
1591 if (old_size < MSI_ADDR_BASE_LO &&
1592 dma_dom->aperture_size > MSI_ADDR_BASE_LO) {
1593 unsigned long spage;
1594 int pages;
1595
1596 pages = iommu_num_pages(MSI_ADDR_BASE_LO, 0x10000, PAGE_SIZE);
1597 spage = MSI_ADDR_BASE_LO >> PAGE_SHIFT;
1598
1599 dma_ops_reserve_addresses(dma_dom, spage, pages);
1600 }
1601
Uwe Kleine-Königb5950762010-11-01 15:38:34 -04001602 /* Initialize the exclusion range if necessary */
Joerg Roedel576175c2009-11-23 19:08:46 +01001603 for_each_iommu(iommu) {
1604 if (iommu->exclusion_start &&
1605 iommu->exclusion_start >= dma_dom->aperture[index]->offset
1606 && iommu->exclusion_start < dma_dom->aperture_size) {
1607 unsigned long startpage;
1608 int pages = iommu_num_pages(iommu->exclusion_start,
1609 iommu->exclusion_length,
1610 PAGE_SIZE);
1611 startpage = iommu->exclusion_start >> PAGE_SHIFT;
1612 dma_ops_reserve_addresses(dma_dom, startpage, pages);
1613 }
Joerg Roedel00cd1222009-05-19 09:52:40 +02001614 }
1615
1616 /*
1617 * Check for areas already mapped as present in the new aperture
1618 * range and mark those pages as reserved in the allocator. Such
1619 * mappings may already exist as a result of requested unity
1620 * mappings for devices.
1621 */
1622 for (i = dma_dom->aperture[index]->offset;
1623 i < dma_dom->aperture_size;
Joerg Roedel5d7c94c2015-04-01 14:58:50 +02001624 i += pte_pgsize) {
Joerg Roedel3039ca12015-04-01 14:58:48 +02001625 u64 *pte = fetch_pte(&dma_dom->domain, i, &pte_pgsize);
Joerg Roedel00cd1222009-05-19 09:52:40 +02001626 if (!pte || !IOMMU_PTE_PRESENT(*pte))
1627 continue;
1628
Joerg Roedel5d7c94c2015-04-01 14:58:50 +02001629 dma_ops_reserve_addresses(dma_dom, i >> PAGE_SHIFT,
1630 pte_pgsize >> 12);
Joerg Roedel00cd1222009-05-19 09:52:40 +02001631 }
1632
Joerg Roedel04bfdd82009-09-02 16:00:23 +02001633 update_domain(&dma_dom->domain);
1634
Joerg Roedel92d420e2015-12-21 19:31:33 +01001635 spin_unlock(&range->bitmap_lock);
1636
1637 spin_unlock_irqrestore(&dma_dom->domain.lock, flags);
Joerg Roedela73c1562015-12-21 19:25:56 +01001638
Joerg Roedel9cabe892009-05-18 16:38:55 +02001639 return 0;
1640
1641out_free:
Joerg Roedel04bfdd82009-09-02 16:00:23 +02001642 update_domain(&dma_dom->domain);
1643
Joerg Roedela73c1562015-12-21 19:25:56 +01001644 free_page((unsigned long)range->bitmap);
Joerg Roedel9cabe892009-05-18 16:38:55 +02001645
Joerg Roedela73c1562015-12-21 19:25:56 +01001646 kfree(range);
Joerg Roedel9cabe892009-05-18 16:38:55 +02001647
1648 return -ENOMEM;
1649}
1650
Joerg Roedelccb50e02015-12-21 17:49:34 +01001651static dma_addr_t dma_ops_aperture_alloc(struct dma_ops_domain *dom,
1652 struct aperture_range *range,
Joerg Roedela0f51442015-12-21 16:20:09 +01001653 unsigned long pages,
Joerg Roedela0f51442015-12-21 16:20:09 +01001654 unsigned long dma_mask,
1655 unsigned long boundary_size,
Joerg Roedel7b5e25b2015-12-22 13:38:12 +01001656 unsigned long align_mask,
1657 bool trylock)
Joerg Roedela0f51442015-12-21 16:20:09 +01001658{
1659 unsigned long offset, limit, flags;
1660 dma_addr_t address;
Joerg Roedelccb50e02015-12-21 17:49:34 +01001661 bool flush = false;
Joerg Roedela0f51442015-12-21 16:20:09 +01001662
1663 offset = range->offset >> PAGE_SHIFT;
1664 limit = iommu_device_max_index(APERTURE_RANGE_PAGES, offset,
1665 dma_mask >> PAGE_SHIFT);
1666
Joerg Roedel7b5e25b2015-12-22 13:38:12 +01001667 if (trylock) {
1668 if (!spin_trylock_irqsave(&range->bitmap_lock, flags))
1669 return -1;
1670 } else {
1671 spin_lock_irqsave(&range->bitmap_lock, flags);
1672 }
1673
Joerg Roedel60e6a7c2015-12-21 16:53:17 +01001674 address = iommu_area_alloc(range->bitmap, limit, range->next_bit,
1675 pages, offset, boundary_size, align_mask);
Joerg Roedelccb50e02015-12-21 17:49:34 +01001676 if (address == -1) {
Joerg Roedel60e6a7c2015-12-21 16:53:17 +01001677 /* Nothing found, retry one time */
1678 address = iommu_area_alloc(range->bitmap, limit,
1679 0, pages, offset, boundary_size,
1680 align_mask);
Joerg Roedelccb50e02015-12-21 17:49:34 +01001681 flush = true;
1682 }
Joerg Roedel60e6a7c2015-12-21 16:53:17 +01001683
1684 if (address != -1)
1685 range->next_bit = address + pages;
1686
Joerg Roedela0f51442015-12-21 16:20:09 +01001687 spin_unlock_irqrestore(&range->bitmap_lock, flags);
1688
Joerg Roedelccb50e02015-12-21 17:49:34 +01001689 if (flush) {
1690 domain_flush_tlb(&dom->domain);
1691 domain_flush_complete(&dom->domain);
1692 }
1693
Joerg Roedela0f51442015-12-21 16:20:09 +01001694 return address;
1695}
1696
Joerg Roedel384de722009-05-15 12:30:05 +02001697static unsigned long dma_ops_area_alloc(struct device *dev,
1698 struct dma_ops_domain *dom,
1699 unsigned int pages,
1700 unsigned long align_mask,
Joerg Roedel05ab49e2015-12-21 17:58:26 +01001701 u64 dma_mask)
Joerg Roedel384de722009-05-15 12:30:05 +02001702{
Joerg Roedelab7032b2015-12-21 18:47:11 +01001703 unsigned long boundary_size, mask;
Joerg Roedel384de722009-05-15 12:30:05 +02001704 unsigned long address = -1;
Joerg Roedel7b5e25b2015-12-22 13:38:12 +01001705 bool first = true;
Joerg Roedel5f6bed52015-12-22 13:34:22 +01001706 u32 start, i;
1707
1708 preempt_disable();
Joerg Roedel384de722009-05-15 12:30:05 +02001709
Joerg Roedele6aabee2015-05-27 09:26:09 +02001710 mask = dma_get_seg_boundary(dev);
1711
Joerg Roedel7b5e25b2015-12-22 13:38:12 +01001712again:
Joerg Roedel5f6bed52015-12-22 13:34:22 +01001713 start = this_cpu_read(*dom->next_index);
1714
1715 /* Sanity check - is it really necessary? */
1716 if (unlikely(start > APERTURE_MAX_RANGES)) {
1717 start = 0;
1718 this_cpu_write(*dom->next_index, 0);
1719 }
1720
Joerg Roedele6aabee2015-05-27 09:26:09 +02001721 boundary_size = mask + 1 ? ALIGN(mask + 1, PAGE_SIZE) >> PAGE_SHIFT :
1722 1UL << (BITS_PER_LONG - PAGE_SHIFT);
Joerg Roedel384de722009-05-15 12:30:05 +02001723
Joerg Roedel2a874422015-12-21 18:34:47 +01001724 for (i = 0; i < APERTURE_MAX_RANGES; ++i) {
1725 struct aperture_range *range;
Joerg Roedel5f6bed52015-12-22 13:34:22 +01001726 int index;
Joerg Roedelccb50e02015-12-21 17:49:34 +01001727
Joerg Roedel5f6bed52015-12-22 13:34:22 +01001728 index = (start + i) % APERTURE_MAX_RANGES;
1729
1730 range = dom->aperture[index];
Joerg Roedel2a874422015-12-21 18:34:47 +01001731
1732 if (!range || range->offset >= dma_mask)
1733 continue;
Joerg Roedel384de722009-05-15 12:30:05 +02001734
Joerg Roedel2a874422015-12-21 18:34:47 +01001735 address = dma_ops_aperture_alloc(dom, range, pages,
Joerg Roedel60e6a7c2015-12-21 16:53:17 +01001736 dma_mask, boundary_size,
Joerg Roedel7b5e25b2015-12-22 13:38:12 +01001737 align_mask, first);
Joerg Roedel384de722009-05-15 12:30:05 +02001738 if (address != -1) {
Joerg Roedel2a874422015-12-21 18:34:47 +01001739 address = range->offset + (address << PAGE_SHIFT);
Joerg Roedel5f6bed52015-12-22 13:34:22 +01001740 this_cpu_write(*dom->next_index, index);
Joerg Roedel384de722009-05-15 12:30:05 +02001741 break;
1742 }
Joerg Roedel384de722009-05-15 12:30:05 +02001743 }
1744
Joerg Roedel7b5e25b2015-12-22 13:38:12 +01001745 if (address == -1 && first) {
1746 first = false;
1747 goto again;
1748 }
1749
Joerg Roedel5f6bed52015-12-22 13:34:22 +01001750 preempt_enable();
1751
Joerg Roedel384de722009-05-15 12:30:05 +02001752 return address;
1753}
1754
Joerg Roedeld3086442008-06-26 21:27:57 +02001755static unsigned long dma_ops_alloc_addresses(struct device *dev,
1756 struct dma_ops_domain *dom,
Joerg Roedel6d4f3432008-09-04 19:18:02 +02001757 unsigned int pages,
Joerg Roedel832a90c2008-09-18 15:54:23 +02001758 unsigned long align_mask,
1759 u64 dma_mask)
Joerg Roedeld3086442008-06-26 21:27:57 +02001760{
Joerg Roedel266a3bd2015-12-21 18:54:24 +01001761 unsigned long address = -1;
Joerg Roedeld3086442008-06-26 21:27:57 +02001762
Joerg Roedel266a3bd2015-12-21 18:54:24 +01001763 while (address == -1) {
1764 address = dma_ops_area_alloc(dev, dom, pages,
1765 align_mask, dma_mask);
1766
Joerg Roedel7bfa5bd2015-12-21 19:07:50 +01001767 if (address == -1 && alloc_new_range(dom, false, GFP_ATOMIC))
Joerg Roedel266a3bd2015-12-21 18:54:24 +01001768 break;
1769 }
Joerg Roedeld3086442008-06-26 21:27:57 +02001770
Joerg Roedel384de722009-05-15 12:30:05 +02001771 if (unlikely(address == -1))
FUJITA Tomonori8fd524b2009-11-15 21:19:53 +09001772 address = DMA_ERROR_CODE;
Joerg Roedeld3086442008-06-26 21:27:57 +02001773
1774 WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size);
1775
1776 return address;
1777}
1778
Joerg Roedel431b2a22008-07-11 17:14:22 +02001779/*
1780 * The address free function.
1781 *
1782 * called with domain->lock held
1783 */
Joerg Roedeld3086442008-06-26 21:27:57 +02001784static void dma_ops_free_addresses(struct dma_ops_domain *dom,
1785 unsigned long address,
1786 unsigned int pages)
1787{
Joerg Roedel384de722009-05-15 12:30:05 +02001788 unsigned i = address >> APERTURE_RANGE_SHIFT;
1789 struct aperture_range *range = dom->aperture[i];
Joerg Roedel08c5fb92015-12-21 13:04:49 +01001790 unsigned long flags;
Joerg Roedel80be3082008-11-06 14:59:05 +01001791
Joerg Roedel384de722009-05-15 12:30:05 +02001792 BUG_ON(i >= APERTURE_MAX_RANGES || range == NULL);
1793
Joerg Roedel47bccd62009-05-22 12:40:54 +02001794#ifdef CONFIG_IOMMU_STRESS
1795 if (i < 4)
1796 return;
1797#endif
1798
Joerg Roedel4eeca8c2015-12-22 12:15:35 +01001799 if (amd_iommu_unmap_flush) {
Joerg Roedeld41ab092015-12-21 18:20:03 +01001800 domain_flush_tlb(&dom->domain);
1801 domain_flush_complete(&dom->domain);
1802 }
Joerg Roedel384de722009-05-15 12:30:05 +02001803
1804 address = (address % APERTURE_RANGE_SIZE) >> PAGE_SHIFT;
Joerg Roedel803b8cb2009-05-18 15:32:48 +02001805
Joerg Roedel08c5fb92015-12-21 13:04:49 +01001806 spin_lock_irqsave(&range->bitmap_lock, flags);
Joerg Roedel4eeca8c2015-12-22 12:15:35 +01001807 if (address + pages > range->next_bit)
1808 range->next_bit = address + pages;
Akinobu Mitaa66022c2009-12-15 16:48:28 -08001809 bitmap_clear(range->bitmap, address, pages);
Joerg Roedel08c5fb92015-12-21 13:04:49 +01001810 spin_unlock_irqrestore(&range->bitmap_lock, flags);
Joerg Roedel384de722009-05-15 12:30:05 +02001811
Joerg Roedeld3086442008-06-26 21:27:57 +02001812}
1813
Joerg Roedel431b2a22008-07-11 17:14:22 +02001814/****************************************************************************
1815 *
1816 * The next functions belong to the domain allocation. A domain is
1817 * allocated for every IOMMU as the default domain. If device isolation
1818 * is enabled, every device get its own domain. The most important thing
1819 * about domains is the page table mapping the DMA address space they
1820 * contain.
1821 *
1822 ****************************************************************************/
1823
Joerg Roedelaeb26f52009-11-20 16:44:01 +01001824/*
1825 * This function adds a protection domain to the global protection domain list
1826 */
1827static void add_domain_to_list(struct protection_domain *domain)
1828{
1829 unsigned long flags;
1830
1831 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1832 list_add(&domain->list, &amd_iommu_pd_list);
1833 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1834}
1835
1836/*
1837 * This function removes a protection domain to the global
1838 * protection domain list
1839 */
1840static void del_domain_from_list(struct protection_domain *domain)
1841{
1842 unsigned long flags;
1843
1844 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1845 list_del(&domain->list);
1846 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1847}
1848
Joerg Roedelec487d12008-06-26 21:27:58 +02001849static u16 domain_id_alloc(void)
1850{
1851 unsigned long flags;
1852 int id;
1853
1854 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1855 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
1856 BUG_ON(id == 0);
1857 if (id > 0 && id < MAX_DOMAIN_ID)
1858 __set_bit(id, amd_iommu_pd_alloc_bitmap);
1859 else
1860 id = 0;
1861 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1862
1863 return id;
1864}
1865
Joerg Roedela2acfb72008-12-02 18:28:53 +01001866static void domain_id_free(int id)
1867{
1868 unsigned long flags;
1869
1870 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1871 if (id > 0 && id < MAX_DOMAIN_ID)
1872 __clear_bit(id, amd_iommu_pd_alloc_bitmap);
1873 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1874}
Joerg Roedela2acfb72008-12-02 18:28:53 +01001875
Joerg Roedel5c34c402013-06-20 20:22:58 +02001876#define DEFINE_FREE_PT_FN(LVL, FN) \
1877static void free_pt_##LVL (unsigned long __pt) \
1878{ \
1879 unsigned long p; \
1880 u64 *pt; \
1881 int i; \
1882 \
1883 pt = (u64 *)__pt; \
1884 \
1885 for (i = 0; i < 512; ++i) { \
Joerg Roedel0b3fff52015-06-18 10:48:34 +02001886 /* PTE present? */ \
Joerg Roedel5c34c402013-06-20 20:22:58 +02001887 if (!IOMMU_PTE_PRESENT(pt[i])) \
1888 continue; \
1889 \
Joerg Roedel0b3fff52015-06-18 10:48:34 +02001890 /* Large PTE? */ \
1891 if (PM_PTE_LEVEL(pt[i]) == 0 || \
1892 PM_PTE_LEVEL(pt[i]) == 7) \
1893 continue; \
1894 \
Joerg Roedel5c34c402013-06-20 20:22:58 +02001895 p = (unsigned long)IOMMU_PTE_PAGE(pt[i]); \
1896 FN(p); \
1897 } \
1898 free_page((unsigned long)pt); \
1899}
1900
1901DEFINE_FREE_PT_FN(l2, free_page)
1902DEFINE_FREE_PT_FN(l3, free_pt_l2)
1903DEFINE_FREE_PT_FN(l4, free_pt_l3)
1904DEFINE_FREE_PT_FN(l5, free_pt_l4)
1905DEFINE_FREE_PT_FN(l6, free_pt_l5)
1906
Joerg Roedel86db2e52008-12-02 18:20:21 +01001907static void free_pagetable(struct protection_domain *domain)
Joerg Roedelec487d12008-06-26 21:27:58 +02001908{
Joerg Roedel5c34c402013-06-20 20:22:58 +02001909 unsigned long root = (unsigned long)domain->pt_root;
Joerg Roedelec487d12008-06-26 21:27:58 +02001910
Joerg Roedel5c34c402013-06-20 20:22:58 +02001911 switch (domain->mode) {
1912 case PAGE_MODE_NONE:
1913 break;
1914 case PAGE_MODE_1_LEVEL:
1915 free_page(root);
1916 break;
1917 case PAGE_MODE_2_LEVEL:
1918 free_pt_l2(root);
1919 break;
1920 case PAGE_MODE_3_LEVEL:
1921 free_pt_l3(root);
1922 break;
1923 case PAGE_MODE_4_LEVEL:
1924 free_pt_l4(root);
1925 break;
1926 case PAGE_MODE_5_LEVEL:
1927 free_pt_l5(root);
1928 break;
1929 case PAGE_MODE_6_LEVEL:
1930 free_pt_l6(root);
1931 break;
1932 default:
1933 BUG();
Joerg Roedelec487d12008-06-26 21:27:58 +02001934 }
Joerg Roedelec487d12008-06-26 21:27:58 +02001935}
1936
Joerg Roedelb16137b2011-11-21 16:50:23 +01001937static void free_gcr3_tbl_level1(u64 *tbl)
1938{
1939 u64 *ptr;
1940 int i;
1941
1942 for (i = 0; i < 512; ++i) {
1943 if (!(tbl[i] & GCR3_VALID))
1944 continue;
1945
1946 ptr = __va(tbl[i] & PAGE_MASK);
1947
1948 free_page((unsigned long)ptr);
1949 }
1950}
1951
1952static void free_gcr3_tbl_level2(u64 *tbl)
1953{
1954 u64 *ptr;
1955 int i;
1956
1957 for (i = 0; i < 512; ++i) {
1958 if (!(tbl[i] & GCR3_VALID))
1959 continue;
1960
1961 ptr = __va(tbl[i] & PAGE_MASK);
1962
1963 free_gcr3_tbl_level1(ptr);
1964 }
1965}
1966
Joerg Roedel52815b72011-11-17 17:24:28 +01001967static void free_gcr3_table(struct protection_domain *domain)
1968{
Joerg Roedelb16137b2011-11-21 16:50:23 +01001969 if (domain->glx == 2)
1970 free_gcr3_tbl_level2(domain->gcr3_tbl);
1971 else if (domain->glx == 1)
1972 free_gcr3_tbl_level1(domain->gcr3_tbl);
Joerg Roedel23d3a982015-08-13 11:15:13 +02001973 else
1974 BUG_ON(domain->glx != 0);
Joerg Roedelb16137b2011-11-21 16:50:23 +01001975
Joerg Roedel52815b72011-11-17 17:24:28 +01001976 free_page((unsigned long)domain->gcr3_tbl);
1977}
1978
Joerg Roedel431b2a22008-07-11 17:14:22 +02001979/*
1980 * Free a domain, only used if something went wrong in the
1981 * allocation path and we need to free an already allocated page table
1982 */
Joerg Roedelec487d12008-06-26 21:27:58 +02001983static void dma_ops_domain_free(struct dma_ops_domain *dom)
1984{
Joerg Roedel384de722009-05-15 12:30:05 +02001985 int i;
1986
Joerg Roedelec487d12008-06-26 21:27:58 +02001987 if (!dom)
1988 return;
1989
Joerg Roedel307d5852016-07-05 11:54:04 +02001990 put_iova_domain(&dom->iovad);
1991
Joerg Roedel5f6bed52015-12-22 13:34:22 +01001992 free_percpu(dom->next_index);
1993
Joerg Roedelaeb26f52009-11-20 16:44:01 +01001994 del_domain_from_list(&dom->domain);
1995
Joerg Roedel86db2e52008-12-02 18:20:21 +01001996 free_pagetable(&dom->domain);
Joerg Roedelec487d12008-06-26 21:27:58 +02001997
Joerg Roedel384de722009-05-15 12:30:05 +02001998 for (i = 0; i < APERTURE_MAX_RANGES; ++i) {
1999 if (!dom->aperture[i])
2000 continue;
2001 free_page((unsigned long)dom->aperture[i]->bitmap);
2002 kfree(dom->aperture[i]);
2003 }
Joerg Roedelec487d12008-06-26 21:27:58 +02002004
2005 kfree(dom);
2006}
2007
Joerg Roedela639a8e2015-12-22 16:06:49 +01002008static int dma_ops_domain_alloc_apertures(struct dma_ops_domain *dma_dom,
2009 int max_apertures)
2010{
2011 int ret, i, apertures;
2012
2013 apertures = dma_dom->aperture_size >> APERTURE_RANGE_SHIFT;
2014 ret = 0;
2015
2016 for (i = apertures; i < max_apertures; ++i) {
2017 ret = alloc_new_range(dma_dom, false, GFP_KERNEL);
2018 if (ret)
2019 break;
2020 }
2021
2022 return ret;
2023}
2024
Joerg Roedel431b2a22008-07-11 17:14:22 +02002025/*
2026 * Allocates a new protection domain usable for the dma_ops functions.
Uwe Kleine-Königb5950762010-11-01 15:38:34 -04002027 * It also initializes the page table and the address allocator data
Joerg Roedel431b2a22008-07-11 17:14:22 +02002028 * structures required for the dma_ops interface
2029 */
Joerg Roedel87a64d52009-11-24 17:26:43 +01002030static struct dma_ops_domain *dma_ops_domain_alloc(void)
Joerg Roedelec487d12008-06-26 21:27:58 +02002031{
2032 struct dma_ops_domain *dma_dom;
Joerg Roedel5f6bed52015-12-22 13:34:22 +01002033 int cpu;
Joerg Roedelec487d12008-06-26 21:27:58 +02002034
2035 dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL);
2036 if (!dma_dom)
2037 return NULL;
2038
Joerg Roedel7a5a5662015-06-30 08:56:11 +02002039 if (protection_domain_init(&dma_dom->domain))
Joerg Roedelec487d12008-06-26 21:27:58 +02002040 goto free_dma_dom;
Joerg Roedel7a5a5662015-06-30 08:56:11 +02002041
Joerg Roedel5f6bed52015-12-22 13:34:22 +01002042 dma_dom->next_index = alloc_percpu(u32);
2043 if (!dma_dom->next_index)
2044 goto free_dma_dom;
2045
Joerg Roedel8f7a0172009-09-02 16:55:24 +02002046 dma_dom->domain.mode = PAGE_MODE_2_LEVEL;
Joerg Roedelec487d12008-06-26 21:27:58 +02002047 dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
Joerg Roedel9fdb19d2008-12-02 17:46:25 +01002048 dma_dom->domain.flags = PD_DMA_OPS_MASK;
Joerg Roedelec487d12008-06-26 21:27:58 +02002049 dma_dom->domain.priv = dma_dom;
2050 if (!dma_dom->domain.pt_root)
2051 goto free_dma_dom;
Joerg Roedelec487d12008-06-26 21:27:58 +02002052
Joerg Roedelaeb26f52009-11-20 16:44:01 +01002053 add_domain_to_list(&dma_dom->domain);
2054
Joerg Roedel576175c2009-11-23 19:08:46 +01002055 if (alloc_new_range(dma_dom, true, GFP_KERNEL))
Joerg Roedelec487d12008-06-26 21:27:58 +02002056 goto free_dma_dom;
Joerg Roedelec487d12008-06-26 21:27:58 +02002057
Joerg Roedel431b2a22008-07-11 17:14:22 +02002058 /*
Joerg Roedelec487d12008-06-26 21:27:58 +02002059 * mark the first page as allocated so we never return 0 as
2060 * a valid dma-address. So we can use 0 as error value
Joerg Roedel431b2a22008-07-11 17:14:22 +02002061 */
Joerg Roedel384de722009-05-15 12:30:05 +02002062 dma_dom->aperture[0]->bitmap[0] = 1;
Joerg Roedelec487d12008-06-26 21:27:58 +02002063
Joerg Roedel5f6bed52015-12-22 13:34:22 +01002064 for_each_possible_cpu(cpu)
2065 *per_cpu_ptr(dma_dom->next_index, cpu) = 0;
Joerg Roedelec487d12008-06-26 21:27:58 +02002066
Joerg Roedel307d5852016-07-05 11:54:04 +02002067 init_iova_domain(&dma_dom->iovad, PAGE_SIZE,
2068 IOVA_START_PFN, DMA_32BIT_PFN);
2069
Joerg Roedel81cd07b2016-07-07 18:01:10 +02002070 /* Initialize reserved ranges */
2071 copy_reserved_iova(&reserved_iova_ranges, &dma_dom->iovad);
2072
Joerg Roedelec487d12008-06-26 21:27:58 +02002073 return dma_dom;
2074
2075free_dma_dom:
2076 dma_ops_domain_free(dma_dom);
2077
2078 return NULL;
2079}
2080
Joerg Roedel431b2a22008-07-11 17:14:22 +02002081/*
Joerg Roedel5b28df62008-12-02 17:49:42 +01002082 * little helper function to check whether a given protection domain is a
2083 * dma_ops domain
2084 */
2085static bool dma_ops_domain(struct protection_domain *domain)
2086{
2087 return domain->flags & PD_DMA_OPS_MASK;
2088}
2089
Joerg Roedelfd7b5532011-04-05 15:31:08 +02002090static void set_dte_entry(u16 devid, struct protection_domain *domain, bool ats)
Joerg Roedelb20ac0d2008-06-26 21:27:59 +02002091{
Joerg Roedel132bd682011-11-17 14:18:46 +01002092 u64 pte_root = 0;
Joerg Roedelee6c2862011-11-09 12:06:03 +01002093 u64 flags = 0;
Joerg Roedel863c74e2008-12-02 17:56:36 +01002094
Joerg Roedel132bd682011-11-17 14:18:46 +01002095 if (domain->mode != PAGE_MODE_NONE)
2096 pte_root = virt_to_phys(domain->pt_root);
2097
Joerg Roedel38ddf412008-09-11 10:38:32 +02002098 pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
2099 << DEV_ENTRY_MODE_SHIFT;
2100 pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV;
Joerg Roedelb20ac0d2008-06-26 21:27:59 +02002101
Joerg Roedelee6c2862011-11-09 12:06:03 +01002102 flags = amd_iommu_dev_table[devid].data[1];
2103
Joerg Roedelfd7b5532011-04-05 15:31:08 +02002104 if (ats)
2105 flags |= DTE_FLAG_IOTLB;
2106
Joerg Roedel52815b72011-11-17 17:24:28 +01002107 if (domain->flags & PD_IOMMUV2_MASK) {
2108 u64 gcr3 = __pa(domain->gcr3_tbl);
2109 u64 glx = domain->glx;
2110 u64 tmp;
2111
2112 pte_root |= DTE_FLAG_GV;
2113 pte_root |= (glx & DTE_GLX_MASK) << DTE_GLX_SHIFT;
2114
2115 /* First mask out possible old values for GCR3 table */
2116 tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B;
2117 flags &= ~tmp;
2118
2119 tmp = DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C;
2120 flags &= ~tmp;
2121
2122 /* Encode GCR3 table into DTE */
2123 tmp = DTE_GCR3_VAL_A(gcr3) << DTE_GCR3_SHIFT_A;
2124 pte_root |= tmp;
2125
2126 tmp = DTE_GCR3_VAL_B(gcr3) << DTE_GCR3_SHIFT_B;
2127 flags |= tmp;
2128
2129 tmp = DTE_GCR3_VAL_C(gcr3) << DTE_GCR3_SHIFT_C;
2130 flags |= tmp;
2131 }
2132
Joerg Roedelee6c2862011-11-09 12:06:03 +01002133 flags &= ~(0xffffUL);
2134 flags |= domain->id;
2135
2136 amd_iommu_dev_table[devid].data[1] = flags;
2137 amd_iommu_dev_table[devid].data[0] = pte_root;
Joerg Roedelb20ac0d2008-06-26 21:27:59 +02002138}
2139
Joerg Roedel15898bb2009-11-24 15:39:42 +01002140static void clear_dte_entry(u16 devid)
Joerg Roedel355bf552008-12-08 12:02:41 +01002141{
Joerg Roedel355bf552008-12-08 12:02:41 +01002142 /* remove entry from the device table seen by the hardware */
Joerg Roedelcbf3ccd2015-10-20 14:59:36 +02002143 amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV;
2144 amd_iommu_dev_table[devid].data[1] &= DTE_FLAG_MASK;
Joerg Roedel355bf552008-12-08 12:02:41 +01002145
Joerg Roedelc5cca142009-10-09 18:31:20 +02002146 amd_iommu_apply_erratum_63(devid);
Joerg Roedel7f760dd2009-11-26 14:49:59 +01002147}
2148
Joerg Roedelec9e79e2011-06-09 17:25:50 +02002149static void do_attach(struct iommu_dev_data *dev_data,
2150 struct protection_domain *domain)
Joerg Roedel7f760dd2009-11-26 14:49:59 +01002151{
Joerg Roedel7f760dd2009-11-26 14:49:59 +01002152 struct amd_iommu *iommu;
Joerg Roedele25bfb52015-10-20 17:33:38 +02002153 u16 alias;
Joerg Roedelec9e79e2011-06-09 17:25:50 +02002154 bool ats;
Joerg Roedel7f760dd2009-11-26 14:49:59 +01002155
Joerg Roedelec9e79e2011-06-09 17:25:50 +02002156 iommu = amd_iommu_rlookup_table[dev_data->devid];
Joerg Roedele3156042016-04-08 15:12:24 +02002157 alias = dev_data->alias;
Joerg Roedelec9e79e2011-06-09 17:25:50 +02002158 ats = dev_data->ats.enabled;
Joerg Roedel7f760dd2009-11-26 14:49:59 +01002159
2160 /* Update data structures */
2161 dev_data->domain = domain;
2162 list_add(&dev_data->list, &domain->dev_list);
Joerg Roedel7f760dd2009-11-26 14:49:59 +01002163
2164 /* Do reference counting */
2165 domain->dev_iommu[iommu->index] += 1;
2166 domain->dev_cnt += 1;
2167
Joerg Roedele25bfb52015-10-20 17:33:38 +02002168 /* Update device table */
2169 set_dte_entry(dev_data->devid, domain, ats);
2170 if (alias != dev_data->devid)
Baoquan He9b1a12d2016-01-20 22:01:19 +08002171 set_dte_entry(alias, domain, ats);
Joerg Roedele25bfb52015-10-20 17:33:38 +02002172
Joerg Roedel6c542042011-06-09 17:07:31 +02002173 device_flush_dte(dev_data);
Joerg Roedel7f760dd2009-11-26 14:49:59 +01002174}
2175
Joerg Roedelec9e79e2011-06-09 17:25:50 +02002176static void do_detach(struct iommu_dev_data *dev_data)
Joerg Roedel7f760dd2009-11-26 14:49:59 +01002177{
Joerg Roedel7f760dd2009-11-26 14:49:59 +01002178 struct amd_iommu *iommu;
Joerg Roedele25bfb52015-10-20 17:33:38 +02002179 u16 alias;
Joerg Roedel7f760dd2009-11-26 14:49:59 +01002180
Joerg Roedel5adad992015-10-09 16:23:33 +02002181 /*
2182 * First check if the device is still attached. It might already
2183 * be detached from its domain because the generic
2184 * iommu_detach_group code detached it and we try again here in
2185 * our alias handling.
2186 */
2187 if (!dev_data->domain)
2188 return;
2189
Joerg Roedelec9e79e2011-06-09 17:25:50 +02002190 iommu = amd_iommu_rlookup_table[dev_data->devid];
Joerg Roedele3156042016-04-08 15:12:24 +02002191 alias = dev_data->alias;
Joerg Roedelc5cca142009-10-09 18:31:20 +02002192
Joerg Roedelc4596112009-11-20 14:57:32 +01002193 /* decrease reference counters */
Joerg Roedel7f760dd2009-11-26 14:49:59 +01002194 dev_data->domain->dev_iommu[iommu->index] -= 1;
2195 dev_data->domain->dev_cnt -= 1;
Joerg Roedel355bf552008-12-08 12:02:41 +01002196
Joerg Roedel7f760dd2009-11-26 14:49:59 +01002197 /* Update data structures */
2198 dev_data->domain = NULL;
2199 list_del(&dev_data->list);
Joerg Roedelf62dda62011-06-09 12:55:35 +02002200 clear_dte_entry(dev_data->devid);
Joerg Roedele25bfb52015-10-20 17:33:38 +02002201 if (alias != dev_data->devid)
2202 clear_dte_entry(alias);
Joerg Roedel7f760dd2009-11-26 14:49:59 +01002203
2204 /* Flush the DTE entry */
Joerg Roedel6c542042011-06-09 17:07:31 +02002205 device_flush_dte(dev_data);
Joerg Roedel15898bb2009-11-24 15:39:42 +01002206}
2207
2208/*
2209 * If a device is not yet associated with a domain, this function does
2210 * assigns it visible for the hardware
2211 */
Joerg Roedelec9e79e2011-06-09 17:25:50 +02002212static int __attach_device(struct iommu_dev_data *dev_data,
Joerg Roedel15898bb2009-11-24 15:39:42 +01002213 struct protection_domain *domain)
2214{
Julia Lawall84fe6c12010-05-27 12:31:51 +02002215 int ret;
Joerg Roedel657cbb62009-11-23 15:26:46 +01002216
Joerg Roedel272e4f92015-10-20 17:33:37 +02002217 /*
2218 * Must be called with IRQs disabled. Warn here to detect early
2219 * when its not.
2220 */
2221 WARN_ON(!irqs_disabled());
2222
Joerg Roedel15898bb2009-11-24 15:39:42 +01002223 /* lock domain */
2224 spin_lock(&domain->lock);
2225
Joerg Roedel397111a2014-08-05 17:31:51 +02002226 ret = -EBUSY;
Joerg Roedel150952f2015-10-20 17:33:35 +02002227 if (dev_data->domain != NULL)
Joerg Roedel397111a2014-08-05 17:31:51 +02002228 goto out_unlock;
Joerg Roedel24100052009-11-25 15:59:57 +01002229
Joerg Roedel397111a2014-08-05 17:31:51 +02002230 /* Attach alias group root */
Joerg Roedel150952f2015-10-20 17:33:35 +02002231 do_attach(dev_data, domain);
Joerg Roedel24100052009-11-25 15:59:57 +01002232
Julia Lawall84fe6c12010-05-27 12:31:51 +02002233 ret = 0;
2234
2235out_unlock:
2236
Joerg Roedel355bf552008-12-08 12:02:41 +01002237 /* ready */
2238 spin_unlock(&domain->lock);
Joerg Roedel21129f72009-09-01 11:59:42 +02002239
Julia Lawall84fe6c12010-05-27 12:31:51 +02002240 return ret;
Joerg Roedel15898bb2009-11-24 15:39:42 +01002241}
2242
Joerg Roedel52815b72011-11-17 17:24:28 +01002243
2244static void pdev_iommuv2_disable(struct pci_dev *pdev)
2245{
2246 pci_disable_ats(pdev);
2247 pci_disable_pri(pdev);
2248 pci_disable_pasid(pdev);
2249}
2250
Joerg Roedel6a113dd2011-12-01 12:04:58 +01002251/* FIXME: Change generic reset-function to do the same */
2252static int pri_reset_while_enabled(struct pci_dev *pdev)
2253{
2254 u16 control;
2255 int pos;
2256
Joerg Roedel46277b72011-12-07 14:34:02 +01002257 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
Joerg Roedel6a113dd2011-12-01 12:04:58 +01002258 if (!pos)
2259 return -EINVAL;
2260
Joerg Roedel46277b72011-12-07 14:34:02 +01002261 pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control);
2262 control |= PCI_PRI_CTRL_RESET;
2263 pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);
Joerg Roedel6a113dd2011-12-01 12:04:58 +01002264
2265 return 0;
2266}
2267
Joerg Roedel52815b72011-11-17 17:24:28 +01002268static int pdev_iommuv2_enable(struct pci_dev *pdev)
2269{
Joerg Roedel6a113dd2011-12-01 12:04:58 +01002270 bool reset_enable;
2271 int reqs, ret;
2272
2273 /* FIXME: Hardcode number of outstanding requests for now */
2274 reqs = 32;
2275 if (pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE))
2276 reqs = 1;
2277 reset_enable = pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_ENABLE_RESET);
Joerg Roedel52815b72011-11-17 17:24:28 +01002278
2279 /* Only allow access to user-accessible pages */
2280 ret = pci_enable_pasid(pdev, 0);
2281 if (ret)
2282 goto out_err;
2283
2284 /* First reset the PRI state of the device */
2285 ret = pci_reset_pri(pdev);
2286 if (ret)
2287 goto out_err;
2288
Joerg Roedel6a113dd2011-12-01 12:04:58 +01002289 /* Enable PRI */
2290 ret = pci_enable_pri(pdev, reqs);
Joerg Roedel52815b72011-11-17 17:24:28 +01002291 if (ret)
2292 goto out_err;
2293
Joerg Roedel6a113dd2011-12-01 12:04:58 +01002294 if (reset_enable) {
2295 ret = pri_reset_while_enabled(pdev);
2296 if (ret)
2297 goto out_err;
2298 }
2299
Joerg Roedel52815b72011-11-17 17:24:28 +01002300 ret = pci_enable_ats(pdev, PAGE_SHIFT);
2301 if (ret)
2302 goto out_err;
2303
2304 return 0;
2305
2306out_err:
2307 pci_disable_pri(pdev);
2308 pci_disable_pasid(pdev);
2309
2310 return ret;
2311}
2312
Joerg Roedelc99afa22011-11-21 18:19:25 +01002313/* FIXME: Move this to PCI code */
Joerg Roedela3b93122012-04-12 12:49:26 +02002314#define PCI_PRI_TLP_OFF (1 << 15)
Joerg Roedelc99afa22011-11-21 18:19:25 +01002315
Joerg Roedel98f1ad22012-07-06 13:28:37 +02002316static bool pci_pri_tlp_required(struct pci_dev *pdev)
Joerg Roedelc99afa22011-11-21 18:19:25 +01002317{
Joerg Roedela3b93122012-04-12 12:49:26 +02002318 u16 status;
Joerg Roedelc99afa22011-11-21 18:19:25 +01002319 int pos;
2320
Joerg Roedel46277b72011-12-07 14:34:02 +01002321 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
Joerg Roedelc99afa22011-11-21 18:19:25 +01002322 if (!pos)
2323 return false;
2324
Joerg Roedela3b93122012-04-12 12:49:26 +02002325 pci_read_config_word(pdev, pos + PCI_PRI_STATUS, &status);
Joerg Roedelc99afa22011-11-21 18:19:25 +01002326
Joerg Roedela3b93122012-04-12 12:49:26 +02002327 return (status & PCI_PRI_TLP_OFF) ? true : false;
Joerg Roedelc99afa22011-11-21 18:19:25 +01002328}
2329
Joerg Roedel15898bb2009-11-24 15:39:42 +01002330/*
Frank Arnolddf805ab2012-08-27 19:21:04 +02002331 * If a device is not yet associated with a domain, this function
Joerg Roedel15898bb2009-11-24 15:39:42 +01002332 * assigns it visible for the hardware
2333 */
2334static int attach_device(struct device *dev,
2335 struct protection_domain *domain)
2336{
Wan Zongshun2bf9a0a2016-04-01 09:06:03 -04002337 struct pci_dev *pdev;
Joerg Roedelea61cdd2011-06-09 12:56:30 +02002338 struct iommu_dev_data *dev_data;
Joerg Roedel15898bb2009-11-24 15:39:42 +01002339 unsigned long flags;
2340 int ret;
2341
Joerg Roedelea61cdd2011-06-09 12:56:30 +02002342 dev_data = get_dev_data(dev);
2343
Wan Zongshun2bf9a0a2016-04-01 09:06:03 -04002344 if (!dev_is_pci(dev))
2345 goto skip_ats_check;
2346
2347 pdev = to_pci_dev(dev);
Joerg Roedel52815b72011-11-17 17:24:28 +01002348 if (domain->flags & PD_IOMMUV2_MASK) {
Joerg Roedel02ca2022015-07-28 16:58:49 +02002349 if (!dev_data->passthrough)
Joerg Roedel52815b72011-11-17 17:24:28 +01002350 return -EINVAL;
2351
Joerg Roedel02ca2022015-07-28 16:58:49 +02002352 if (dev_data->iommu_v2) {
2353 if (pdev_iommuv2_enable(pdev) != 0)
2354 return -EINVAL;
Joerg Roedel52815b72011-11-17 17:24:28 +01002355
Joerg Roedel02ca2022015-07-28 16:58:49 +02002356 dev_data->ats.enabled = true;
2357 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
2358 dev_data->pri_tlp = pci_pri_tlp_required(pdev);
2359 }
Joerg Roedel52815b72011-11-17 17:24:28 +01002360 } else if (amd_iommu_iotlb_sup &&
2361 pci_enable_ats(pdev, PAGE_SHIFT) == 0) {
Joerg Roedelea61cdd2011-06-09 12:56:30 +02002362 dev_data->ats.enabled = true;
2363 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
2364 }
Joerg Roedelfd7b5532011-04-05 15:31:08 +02002365
Wan Zongshun2bf9a0a2016-04-01 09:06:03 -04002366skip_ats_check:
Joerg Roedel15898bb2009-11-24 15:39:42 +01002367 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
Joerg Roedelec9e79e2011-06-09 17:25:50 +02002368 ret = __attach_device(dev_data, domain);
Joerg Roedel15898bb2009-11-24 15:39:42 +01002369 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2370
2371 /*
2372 * We might boot into a crash-kernel here. The crashed kernel
2373 * left the caches in the IOMMU dirty. So we have to flush
2374 * here to evict all dirty stuff.
2375 */
Joerg Roedel17b124b2011-04-06 18:01:35 +02002376 domain_flush_tlb_pde(domain);
Joerg Roedel15898bb2009-11-24 15:39:42 +01002377
2378 return ret;
2379}
2380
2381/*
2382 * Removes a device from a protection domain (unlocked)
2383 */
Joerg Roedelec9e79e2011-06-09 17:25:50 +02002384static void __detach_device(struct iommu_dev_data *dev_data)
Joerg Roedel15898bb2009-11-24 15:39:42 +01002385{
Joerg Roedel2ca76272010-01-22 16:45:31 +01002386 struct protection_domain *domain;
Joerg Roedel15898bb2009-11-24 15:39:42 +01002387
Joerg Roedel272e4f92015-10-20 17:33:37 +02002388 /*
2389 * Must be called with IRQs disabled. Warn here to detect early
2390 * when its not.
2391 */
2392 WARN_ON(!irqs_disabled());
2393
Joerg Roedelf34c73f2015-10-20 17:33:34 +02002394 if (WARN_ON(!dev_data->domain))
2395 return;
Joerg Roedel15898bb2009-11-24 15:39:42 +01002396
Joerg Roedel2ca76272010-01-22 16:45:31 +01002397 domain = dev_data->domain;
2398
Joerg Roedelf1dd0a82015-10-20 17:33:36 +02002399 spin_lock(&domain->lock);
Joerg Roedel24100052009-11-25 15:59:57 +01002400
Joerg Roedel150952f2015-10-20 17:33:35 +02002401 do_detach(dev_data);
Joerg Roedel71f77582011-06-09 19:03:15 +02002402
Joerg Roedelf1dd0a82015-10-20 17:33:36 +02002403 spin_unlock(&domain->lock);
Joerg Roedel355bf552008-12-08 12:02:41 +01002404}
2405
2406/*
2407 * Removes a device from a protection domain (with devtable_lock held)
2408 */
Joerg Roedel15898bb2009-11-24 15:39:42 +01002409static void detach_device(struct device *dev)
Joerg Roedel355bf552008-12-08 12:02:41 +01002410{
Joerg Roedel52815b72011-11-17 17:24:28 +01002411 struct protection_domain *domain;
Joerg Roedelea61cdd2011-06-09 12:56:30 +02002412 struct iommu_dev_data *dev_data;
Joerg Roedel355bf552008-12-08 12:02:41 +01002413 unsigned long flags;
2414
Joerg Roedelec9e79e2011-06-09 17:25:50 +02002415 dev_data = get_dev_data(dev);
Joerg Roedel52815b72011-11-17 17:24:28 +01002416 domain = dev_data->domain;
Joerg Roedelec9e79e2011-06-09 17:25:50 +02002417
Joerg Roedel355bf552008-12-08 12:02:41 +01002418 /* lock device table */
2419 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
Joerg Roedelec9e79e2011-06-09 17:25:50 +02002420 __detach_device(dev_data);
Joerg Roedel355bf552008-12-08 12:02:41 +01002421 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
Joerg Roedelfd7b5532011-04-05 15:31:08 +02002422
Wan Zongshun2bf9a0a2016-04-01 09:06:03 -04002423 if (!dev_is_pci(dev))
2424 return;
2425
Joerg Roedel02ca2022015-07-28 16:58:49 +02002426 if (domain->flags & PD_IOMMUV2_MASK && dev_data->iommu_v2)
Joerg Roedel52815b72011-11-17 17:24:28 +01002427 pdev_iommuv2_disable(to_pci_dev(dev));
2428 else if (dev_data->ats.enabled)
Joerg Roedelea61cdd2011-06-09 12:56:30 +02002429 pci_disable_ats(to_pci_dev(dev));
Joerg Roedel52815b72011-11-17 17:24:28 +01002430
2431 dev_data->ats.enabled = false;
Joerg Roedel355bf552008-12-08 12:02:41 +01002432}
Joerg Roedele275a2a2008-12-10 18:27:25 +01002433
Joerg Roedelaafd8ba2015-05-28 18:41:39 +02002434static int amd_iommu_add_device(struct device *dev)
Joerg Roedel15898bb2009-11-24 15:39:42 +01002435{
Joerg Roedel71f77582011-06-09 19:03:15 +02002436 struct iommu_dev_data *dev_data;
Joerg Roedel07ee8692015-05-28 18:41:42 +02002437 struct iommu_domain *domain;
Joerg Roedele275a2a2008-12-10 18:27:25 +01002438 struct amd_iommu *iommu;
Wan Zongshun7aba6cb2016-04-01 09:06:02 -04002439 int ret, devid;
Joerg Roedele275a2a2008-12-10 18:27:25 +01002440
Joerg Roedelaafd8ba2015-05-28 18:41:39 +02002441 if (!check_device(dev) || get_dev_data(dev))
Joerg Roedel98fc5a62009-11-24 17:19:23 +01002442 return 0;
Joerg Roedele275a2a2008-12-10 18:27:25 +01002443
Joerg Roedelaafd8ba2015-05-28 18:41:39 +02002444 devid = get_device_id(dev);
Joerg Roedel9ee35e42016-04-21 18:21:31 +02002445 if (devid < 0)
Wan Zongshun7aba6cb2016-04-01 09:06:02 -04002446 return devid;
2447
Joerg Roedelaafd8ba2015-05-28 18:41:39 +02002448 iommu = amd_iommu_rlookup_table[devid];
Joerg Roedele275a2a2008-12-10 18:27:25 +01002449
Joerg Roedelaafd8ba2015-05-28 18:41:39 +02002450 ret = iommu_init_device(dev);
Joerg Roedel4d58b8a2015-06-11 09:21:39 +02002451 if (ret) {
2452 if (ret != -ENOTSUPP)
2453 pr_err("Failed to initialize device %s - trying to proceed anyway\n",
2454 dev_name(dev));
Joerg Roedel657cbb62009-11-23 15:26:46 +01002455
Joerg Roedelaafd8ba2015-05-28 18:41:39 +02002456 iommu_ignore_device(dev);
Joerg Roedel343e9ca2015-05-28 18:41:43 +02002457 dev->archdata.dma_ops = &nommu_dma_ops;
Joerg Roedele275a2a2008-12-10 18:27:25 +01002458 goto out;
2459 }
Joerg Roedelaafd8ba2015-05-28 18:41:39 +02002460 init_iommu_group(dev);
Joerg Roedele275a2a2008-12-10 18:27:25 +01002461
Joerg Roedel07ee8692015-05-28 18:41:42 +02002462 dev_data = get_dev_data(dev);
Joerg Roedel4d58b8a2015-06-11 09:21:39 +02002463
2464 BUG_ON(!dev_data);
2465
Joerg Roedel1e6a7b02015-07-28 16:58:48 +02002466 if (iommu_pass_through || dev_data->iommu_v2)
Joerg Roedel07ee8692015-05-28 18:41:42 +02002467 iommu_request_dm_for_dev(dev);
2468
2469 /* Domains are initialized for this device - have a look what we ended up with */
2470 domain = iommu_get_domain_for_dev(dev);
Joerg Roedel32302322015-07-28 16:58:50 +02002471 if (domain->type == IOMMU_DOMAIN_IDENTITY)
Joerg Roedel07ee8692015-05-28 18:41:42 +02002472 dev_data->passthrough = true;
Joerg Roedel32302322015-07-28 16:58:50 +02002473 else
Joerg Roedel07ee8692015-05-28 18:41:42 +02002474 dev->archdata.dma_ops = &amd_iommu_dma_ops;
Joerg Roedele275a2a2008-12-10 18:27:25 +01002475
2476out:
Joerg Roedelaafd8ba2015-05-28 18:41:39 +02002477 iommu_completion_wait(iommu);
2478
Joerg Roedele275a2a2008-12-10 18:27:25 +01002479 return 0;
2480}
2481
Joerg Roedelaafd8ba2015-05-28 18:41:39 +02002482static void amd_iommu_remove_device(struct device *dev)
Joerg Roedel8638c492009-12-10 11:12:25 +01002483{
Joerg Roedelaafd8ba2015-05-28 18:41:39 +02002484 struct amd_iommu *iommu;
Wan Zongshun7aba6cb2016-04-01 09:06:02 -04002485 int devid;
Joerg Roedelaafd8ba2015-05-28 18:41:39 +02002486
2487 if (!check_device(dev))
2488 return;
2489
2490 devid = get_device_id(dev);
Joerg Roedel9ee35e42016-04-21 18:21:31 +02002491 if (devid < 0)
Wan Zongshun7aba6cb2016-04-01 09:06:02 -04002492 return;
2493
Joerg Roedelaafd8ba2015-05-28 18:41:39 +02002494 iommu = amd_iommu_rlookup_table[devid];
2495
2496 iommu_uninit_device(dev);
2497 iommu_completion_wait(iommu);
Joerg Roedel8638c492009-12-10 11:12:25 +01002498}
2499
Wan Zongshunb097d112016-04-01 09:06:04 -04002500static struct iommu_group *amd_iommu_device_group(struct device *dev)
2501{
2502 if (dev_is_pci(dev))
2503 return pci_device_group(dev);
2504
2505 return acpihid_device_group(dev);
2506}
2507
Joerg Roedel431b2a22008-07-11 17:14:22 +02002508/*****************************************************************************
2509 *
2510 * The next functions belong to the dma_ops mapping/unmapping code.
2511 *
2512 *****************************************************************************/
2513
2514/*
2515 * In the dma_ops path we only have the struct device. This function
2516 * finds the corresponding IOMMU, the protection domain and the
2517 * requestor id for a given device.
2518 * If the device is not yet associated with a domain this is also done
2519 * in this function.
2520 */
Joerg Roedel94f6d192009-11-24 16:40:02 +01002521static struct protection_domain *get_domain(struct device *dev)
Joerg Roedelb20ac0d2008-06-26 21:27:59 +02002522{
Joerg Roedel94f6d192009-11-24 16:40:02 +01002523 struct protection_domain *domain;
Joerg Roedel063071d2015-05-28 18:41:38 +02002524 struct iommu_domain *io_domain;
Joerg Roedelb20ac0d2008-06-26 21:27:59 +02002525
Joerg Roedelf99c0f12009-11-23 16:52:56 +01002526 if (!check_device(dev))
Joerg Roedel94f6d192009-11-24 16:40:02 +01002527 return ERR_PTR(-EINVAL);
Joerg Roedeldbcc1122008-09-04 15:04:26 +02002528
Joerg Roedel063071d2015-05-28 18:41:38 +02002529 io_domain = iommu_get_domain_for_dev(dev);
Joerg Roedel0bb6e242015-05-28 18:41:40 +02002530 if (!io_domain)
2531 return NULL;
Joerg Roedel063071d2015-05-28 18:41:38 +02002532
Joerg Roedel0bb6e242015-05-28 18:41:40 +02002533 domain = to_pdomain(io_domain);
2534 if (!dma_ops_domain(domain))
Joerg Roedel94f6d192009-11-24 16:40:02 +01002535 return ERR_PTR(-EBUSY);
Joerg Roedelf99c0f12009-11-23 16:52:56 +01002536
Joerg Roedel0bb6e242015-05-28 18:41:40 +02002537 return domain;
Joerg Roedelb20ac0d2008-06-26 21:27:59 +02002538}
2539
Joerg Roedel04bfdd82009-09-02 16:00:23 +02002540static void update_device_table(struct protection_domain *domain)
2541{
Joerg Roedel492667d2009-11-27 13:25:47 +01002542 struct iommu_dev_data *dev_data;
Joerg Roedel04bfdd82009-09-02 16:00:23 +02002543
Joerg Roedelea61cdd2011-06-09 12:56:30 +02002544 list_for_each_entry(dev_data, &domain->dev_list, list)
2545 set_dte_entry(dev_data->devid, domain, dev_data->ats.enabled);
Joerg Roedel04bfdd82009-09-02 16:00:23 +02002546}
2547
2548static void update_domain(struct protection_domain *domain)
2549{
2550 if (!domain->updated)
2551 return;
2552
2553 update_device_table(domain);
Joerg Roedel17b124b2011-04-06 18:01:35 +02002554
2555 domain_flush_devices(domain);
2556 domain_flush_tlb_pde(domain);
Joerg Roedel04bfdd82009-09-02 16:00:23 +02002557
2558 domain->updated = false;
2559}
2560
Joerg Roedel431b2a22008-07-11 17:14:22 +02002561/*
Joerg Roedel8bda3092009-05-12 12:02:46 +02002562 * This function fetches the PTE for a given address in the aperture
2563 */
2564static u64* dma_ops_get_pte(struct dma_ops_domain *dom,
2565 unsigned long address)
2566{
Joerg Roedel384de722009-05-15 12:30:05 +02002567 struct aperture_range *aperture;
Joerg Roedel8bda3092009-05-12 12:02:46 +02002568 u64 *pte, *pte_page;
2569
Joerg Roedel384de722009-05-15 12:30:05 +02002570 aperture = dom->aperture[APERTURE_RANGE_INDEX(address)];
2571 if (!aperture)
2572 return NULL;
2573
2574 pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
Joerg Roedel8bda3092009-05-12 12:02:46 +02002575 if (!pte) {
Joerg Roedelcbb9d722010-01-15 14:41:15 +01002576 pte = alloc_pte(&dom->domain, address, PAGE_SIZE, &pte_page,
Joerg Roedelabdc5eb2009-09-03 11:33:51 +02002577 GFP_ATOMIC);
Joerg Roedel384de722009-05-15 12:30:05 +02002578 aperture->pte_pages[APERTURE_PAGE_INDEX(address)] = pte_page;
2579 } else
Joerg Roedel8c8c1432009-09-02 17:30:00 +02002580 pte += PM_LEVEL_INDEX(0, address);
Joerg Roedel8bda3092009-05-12 12:02:46 +02002581
Joerg Roedel04bfdd82009-09-02 16:00:23 +02002582 update_domain(&dom->domain);
Joerg Roedel8bda3092009-05-12 12:02:46 +02002583
2584 return pte;
2585}
2586
2587/*
Joerg Roedel431b2a22008-07-11 17:14:22 +02002588 * This is the generic map function. It maps one 4kb page at paddr to
2589 * the given address in the DMA address space for the domain.
2590 */
Joerg Roedel680525e2009-11-23 18:44:42 +01002591static dma_addr_t dma_ops_domain_map(struct dma_ops_domain *dom,
Joerg Roedelcb76c322008-06-26 21:28:00 +02002592 unsigned long address,
2593 phys_addr_t paddr,
2594 int direction)
2595{
2596 u64 *pte, __pte;
2597
2598 WARN_ON(address > dom->aperture_size);
2599
2600 paddr &= PAGE_MASK;
2601
Joerg Roedel8bda3092009-05-12 12:02:46 +02002602 pte = dma_ops_get_pte(dom, address);
Joerg Roedel53812c12009-05-12 12:17:38 +02002603 if (!pte)
FUJITA Tomonori8fd524b2009-11-15 21:19:53 +09002604 return DMA_ERROR_CODE;
Joerg Roedelcb76c322008-06-26 21:28:00 +02002605
2606 __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC;
2607
2608 if (direction == DMA_TO_DEVICE)
2609 __pte |= IOMMU_PTE_IR;
2610 else if (direction == DMA_FROM_DEVICE)
2611 __pte |= IOMMU_PTE_IW;
2612 else if (direction == DMA_BIDIRECTIONAL)
2613 __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW;
2614
Joerg Roedela7fb6682015-12-21 12:50:54 +01002615 WARN_ON_ONCE(*pte);
Joerg Roedelcb76c322008-06-26 21:28:00 +02002616
2617 *pte = __pte;
2618
2619 return (dma_addr_t)address;
2620}
2621
Joerg Roedel431b2a22008-07-11 17:14:22 +02002622/*
2623 * The generic unmapping function for on page in the DMA address space.
2624 */
Joerg Roedel680525e2009-11-23 18:44:42 +01002625static void dma_ops_domain_unmap(struct dma_ops_domain *dom,
Joerg Roedelcb76c322008-06-26 21:28:00 +02002626 unsigned long address)
2627{
Joerg Roedel384de722009-05-15 12:30:05 +02002628 struct aperture_range *aperture;
Joerg Roedelcb76c322008-06-26 21:28:00 +02002629 u64 *pte;
2630
2631 if (address >= dom->aperture_size)
2632 return;
2633
Joerg Roedel384de722009-05-15 12:30:05 +02002634 aperture = dom->aperture[APERTURE_RANGE_INDEX(address)];
2635 if (!aperture)
2636 return;
Joerg Roedelcb76c322008-06-26 21:28:00 +02002637
Joerg Roedel384de722009-05-15 12:30:05 +02002638 pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
2639 if (!pte)
2640 return;
2641
Joerg Roedel8c8c1432009-09-02 17:30:00 +02002642 pte += PM_LEVEL_INDEX(0, address);
Joerg Roedelcb76c322008-06-26 21:28:00 +02002643
Joerg Roedela7fb6682015-12-21 12:50:54 +01002644 WARN_ON_ONCE(!*pte);
Joerg Roedelcb76c322008-06-26 21:28:00 +02002645
2646 *pte = 0ULL;
2647}
2648
Joerg Roedel431b2a22008-07-11 17:14:22 +02002649/*
2650 * This function contains common code for mapping of a physically
Joerg Roedel24f81162008-12-08 14:25:39 +01002651 * contiguous memory region into DMA address space. It is used by all
2652 * mapping functions provided with this IOMMU driver.
Joerg Roedel431b2a22008-07-11 17:14:22 +02002653 * Must be called with the domain lock held.
2654 */
Joerg Roedelcb76c322008-06-26 21:28:00 +02002655static dma_addr_t __map_single(struct device *dev,
Joerg Roedelcb76c322008-06-26 21:28:00 +02002656 struct dma_ops_domain *dma_dom,
2657 phys_addr_t paddr,
2658 size_t size,
Joerg Roedel6d4f3432008-09-04 19:18:02 +02002659 int dir,
Joerg Roedel832a90c2008-09-18 15:54:23 +02002660 bool align,
2661 u64 dma_mask)
Joerg Roedelcb76c322008-06-26 21:28:00 +02002662{
2663 dma_addr_t offset = paddr & ~PAGE_MASK;
Joerg Roedel53812c12009-05-12 12:17:38 +02002664 dma_addr_t address, start, ret;
Joerg Roedelcb76c322008-06-26 21:28:00 +02002665 unsigned int pages;
Joerg Roedel6d4f3432008-09-04 19:18:02 +02002666 unsigned long align_mask = 0;
Joerg Roedelcb76c322008-06-26 21:28:00 +02002667 int i;
2668
Joerg Roedele3c449f2008-10-15 22:02:11 -07002669 pages = iommu_num_pages(paddr, size, PAGE_SIZE);
Joerg Roedelcb76c322008-06-26 21:28:00 +02002670 paddr &= PAGE_MASK;
2671
Joerg Roedel6d4f3432008-09-04 19:18:02 +02002672 if (align)
2673 align_mask = (1UL << get_order(size)) - 1;
2674
Joerg Roedel832a90c2008-09-18 15:54:23 +02002675 address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask,
2676 dma_mask);
Joerg Roedelebaecb42015-12-21 18:11:32 +01002677
Joerg Roedel266a3bd2015-12-21 18:54:24 +01002678 if (address == DMA_ERROR_CODE)
2679 goto out;
Joerg Roedelcb76c322008-06-26 21:28:00 +02002680
2681 start = address;
2682 for (i = 0; i < pages; ++i) {
Joerg Roedel680525e2009-11-23 18:44:42 +01002683 ret = dma_ops_domain_map(dma_dom, start, paddr, dir);
FUJITA Tomonori8fd524b2009-11-15 21:19:53 +09002684 if (ret == DMA_ERROR_CODE)
Joerg Roedel53812c12009-05-12 12:17:38 +02002685 goto out_unmap;
2686
Joerg Roedelcb76c322008-06-26 21:28:00 +02002687 paddr += PAGE_SIZE;
2688 start += PAGE_SIZE;
2689 }
2690 address += offset;
2691
Joerg Roedelab7032b2015-12-21 18:47:11 +01002692 if (unlikely(amd_iommu_np_cache)) {
Joerg Roedel17b124b2011-04-06 18:01:35 +02002693 domain_flush_pages(&dma_dom->domain, address, size);
Joerg Roedelab7032b2015-12-21 18:47:11 +01002694 domain_flush_complete(&dma_dom->domain);
2695 }
Joerg Roedel270cab242008-09-04 15:49:46 +02002696
Joerg Roedelcb76c322008-06-26 21:28:00 +02002697out:
2698 return address;
Joerg Roedel53812c12009-05-12 12:17:38 +02002699
2700out_unmap:
2701
2702 for (--i; i >= 0; --i) {
2703 start -= PAGE_SIZE;
Joerg Roedel680525e2009-11-23 18:44:42 +01002704 dma_ops_domain_unmap(dma_dom, start);
Joerg Roedel53812c12009-05-12 12:17:38 +02002705 }
2706
2707 dma_ops_free_addresses(dma_dom, address, pages);
2708
FUJITA Tomonori8fd524b2009-11-15 21:19:53 +09002709 return DMA_ERROR_CODE;
Joerg Roedelcb76c322008-06-26 21:28:00 +02002710}
2711
Joerg Roedel431b2a22008-07-11 17:14:22 +02002712/*
2713 * Does the reverse of the __map_single function. Must be called with
2714 * the domain lock held too
2715 */
Joerg Roedelcd8c82e2009-11-23 19:33:56 +01002716static void __unmap_single(struct dma_ops_domain *dma_dom,
Joerg Roedelcb76c322008-06-26 21:28:00 +02002717 dma_addr_t dma_addr,
2718 size_t size,
2719 int dir)
2720{
Joerg Roedel04e04632010-09-23 16:12:48 +02002721 dma_addr_t flush_addr;
Joerg Roedelcb76c322008-06-26 21:28:00 +02002722 dma_addr_t i, start;
2723 unsigned int pages;
2724
FUJITA Tomonori8fd524b2009-11-15 21:19:53 +09002725 if ((dma_addr == DMA_ERROR_CODE) ||
Joerg Roedelb8d99052008-12-08 14:40:26 +01002726 (dma_addr + size > dma_dom->aperture_size))
Joerg Roedelcb76c322008-06-26 21:28:00 +02002727 return;
2728
Joerg Roedel04e04632010-09-23 16:12:48 +02002729 flush_addr = dma_addr;
Joerg Roedele3c449f2008-10-15 22:02:11 -07002730 pages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
Joerg Roedelcb76c322008-06-26 21:28:00 +02002731 dma_addr &= PAGE_MASK;
2732 start = dma_addr;
2733
2734 for (i = 0; i < pages; ++i) {
Joerg Roedel680525e2009-11-23 18:44:42 +01002735 dma_ops_domain_unmap(dma_dom, start);
Joerg Roedelcb76c322008-06-26 21:28:00 +02002736 start += PAGE_SIZE;
2737 }
2738
Joerg Roedel84b3a0b2015-12-21 13:23:59 +01002739 dma_ops_free_addresses(dma_dom, dma_addr, pages);
Joerg Roedelcb76c322008-06-26 21:28:00 +02002740}
2741
Joerg Roedel431b2a22008-07-11 17:14:22 +02002742/*
2743 * The exported map_single function for dma_ops.
2744 */
FUJITA Tomonori51491362009-01-05 23:47:25 +09002745static dma_addr_t map_page(struct device *dev, struct page *page,
2746 unsigned long offset, size_t size,
2747 enum dma_data_direction dir,
2748 struct dma_attrs *attrs)
Joerg Roedel4da70b92008-06-26 21:28:01 +02002749{
FUJITA Tomonori51491362009-01-05 23:47:25 +09002750 phys_addr_t paddr = page_to_phys(page) + offset;
Joerg Roedel92d420e2015-12-21 19:31:33 +01002751 struct protection_domain *domain;
2752 u64 dma_mask;
Joerg Roedel4da70b92008-06-26 21:28:01 +02002753
Joerg Roedel94f6d192009-11-24 16:40:02 +01002754 domain = get_domain(dev);
2755 if (PTR_ERR(domain) == -EINVAL)
Joerg Roedel4da70b92008-06-26 21:28:01 +02002756 return (dma_addr_t)paddr;
Joerg Roedel94f6d192009-11-24 16:40:02 +01002757 else if (IS_ERR(domain))
2758 return DMA_ERROR_CODE;
Joerg Roedel4da70b92008-06-26 21:28:01 +02002759
Joerg Roedelf99c0f12009-11-23 16:52:56 +01002760 dma_mask = *dev->dma_mask;
2761
Joerg Roedel92d420e2015-12-21 19:31:33 +01002762 return __map_single(dev, domain->priv, paddr, size, dir, false,
Joerg Roedel832a90c2008-09-18 15:54:23 +02002763 dma_mask);
Joerg Roedel4da70b92008-06-26 21:28:01 +02002764}
2765
Joerg Roedel431b2a22008-07-11 17:14:22 +02002766/*
2767 * The exported unmap_single function for dma_ops.
2768 */
FUJITA Tomonori51491362009-01-05 23:47:25 +09002769static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size,
2770 enum dma_data_direction dir, struct dma_attrs *attrs)
Joerg Roedel4da70b92008-06-26 21:28:01 +02002771{
Joerg Roedel4da70b92008-06-26 21:28:01 +02002772 struct protection_domain *domain;
Joerg Roedel4da70b92008-06-26 21:28:01 +02002773
Joerg Roedel94f6d192009-11-24 16:40:02 +01002774 domain = get_domain(dev);
2775 if (IS_ERR(domain))
Joerg Roedel5b28df62008-12-02 17:49:42 +01002776 return;
2777
Joerg Roedelcd8c82e2009-11-23 19:33:56 +01002778 __unmap_single(domain->priv, dma_addr, size, dir);
Joerg Roedel4da70b92008-06-26 21:28:01 +02002779}
2780
Joerg Roedel431b2a22008-07-11 17:14:22 +02002781/*
Joerg Roedel431b2a22008-07-11 17:14:22 +02002782 * The exported map_sg function for dma_ops (handles scatter-gather
2783 * lists).
2784 */
Joerg Roedel65b050a2008-06-26 21:28:02 +02002785static int map_sg(struct device *dev, struct scatterlist *sglist,
FUJITA Tomonori160c1d82009-01-05 23:59:02 +09002786 int nelems, enum dma_data_direction dir,
2787 struct dma_attrs *attrs)
Joerg Roedel65b050a2008-06-26 21:28:02 +02002788{
Joerg Roedel65b050a2008-06-26 21:28:02 +02002789 struct protection_domain *domain;
Joerg Roedel65b050a2008-06-26 21:28:02 +02002790 int i;
2791 struct scatterlist *s;
2792 phys_addr_t paddr;
2793 int mapped_elems = 0;
Joerg Roedel832a90c2008-09-18 15:54:23 +02002794 u64 dma_mask;
Joerg Roedel65b050a2008-06-26 21:28:02 +02002795
Joerg Roedel94f6d192009-11-24 16:40:02 +01002796 domain = get_domain(dev);
Joerg Roedela0e191b2013-04-09 15:04:36 +02002797 if (IS_ERR(domain))
Joerg Roedel94f6d192009-11-24 16:40:02 +01002798 return 0;
Joerg Roedeldbcc1122008-09-04 15:04:26 +02002799
Joerg Roedel832a90c2008-09-18 15:54:23 +02002800 dma_mask = *dev->dma_mask;
Joerg Roedel65b050a2008-06-26 21:28:02 +02002801
Joerg Roedel65b050a2008-06-26 21:28:02 +02002802 for_each_sg(sglist, s, nelems, i) {
2803 paddr = sg_phys(s);
2804
Joerg Roedelcd8c82e2009-11-23 19:33:56 +01002805 s->dma_address = __map_single(dev, domain->priv,
Joerg Roedel832a90c2008-09-18 15:54:23 +02002806 paddr, s->length, dir, false,
2807 dma_mask);
Joerg Roedel65b050a2008-06-26 21:28:02 +02002808
2809 if (s->dma_address) {
2810 s->dma_length = s->length;
2811 mapped_elems++;
2812 } else
2813 goto unmap;
Joerg Roedel65b050a2008-06-26 21:28:02 +02002814 }
2815
Joerg Roedel65b050a2008-06-26 21:28:02 +02002816 return mapped_elems;
Joerg Roedel92d420e2015-12-21 19:31:33 +01002817
Joerg Roedel65b050a2008-06-26 21:28:02 +02002818unmap:
2819 for_each_sg(sglist, s, mapped_elems, i) {
2820 if (s->dma_address)
Joerg Roedelcd8c82e2009-11-23 19:33:56 +01002821 __unmap_single(domain->priv, s->dma_address,
Joerg Roedel65b050a2008-06-26 21:28:02 +02002822 s->dma_length, dir);
2823 s->dma_address = s->dma_length = 0;
2824 }
2825
Joerg Roedel92d420e2015-12-21 19:31:33 +01002826 return 0;
Joerg Roedel65b050a2008-06-26 21:28:02 +02002827}
2828
Joerg Roedel431b2a22008-07-11 17:14:22 +02002829/*
2830 * The exported map_sg function for dma_ops (handles scatter-gather
2831 * lists).
2832 */
Joerg Roedel65b050a2008-06-26 21:28:02 +02002833static void unmap_sg(struct device *dev, struct scatterlist *sglist,
FUJITA Tomonori160c1d82009-01-05 23:59:02 +09002834 int nelems, enum dma_data_direction dir,
2835 struct dma_attrs *attrs)
Joerg Roedel65b050a2008-06-26 21:28:02 +02002836{
Joerg Roedel65b050a2008-06-26 21:28:02 +02002837 struct protection_domain *domain;
2838 struct scatterlist *s;
Joerg Roedel65b050a2008-06-26 21:28:02 +02002839 int i;
2840
Joerg Roedel94f6d192009-11-24 16:40:02 +01002841 domain = get_domain(dev);
2842 if (IS_ERR(domain))
Joerg Roedel5b28df62008-12-02 17:49:42 +01002843 return;
2844
Joerg Roedel65b050a2008-06-26 21:28:02 +02002845 for_each_sg(sglist, s, nelems, i) {
Joerg Roedelcd8c82e2009-11-23 19:33:56 +01002846 __unmap_single(domain->priv, s->dma_address,
Joerg Roedel65b050a2008-06-26 21:28:02 +02002847 s->dma_length, dir);
Joerg Roedel65b050a2008-06-26 21:28:02 +02002848 s->dma_address = s->dma_length = 0;
2849 }
Joerg Roedel65b050a2008-06-26 21:28:02 +02002850}
2851
Joerg Roedel431b2a22008-07-11 17:14:22 +02002852/*
2853 * The exported alloc_coherent function for dma_ops.
2854 */
Joerg Roedel5d8b53c2008-06-26 21:28:03 +02002855static void *alloc_coherent(struct device *dev, size_t size,
Andrzej Pietrasiewiczbaa676f2012-03-27 14:28:18 +02002856 dma_addr_t *dma_addr, gfp_t flag,
2857 struct dma_attrs *attrs)
Joerg Roedel5d8b53c2008-06-26 21:28:03 +02002858{
Joerg Roedel832a90c2008-09-18 15:54:23 +02002859 u64 dma_mask = dev->coherent_dma_mask;
Joerg Roedel3b839a52015-04-01 14:58:47 +02002860 struct protection_domain *domain;
Joerg Roedel3b839a52015-04-01 14:58:47 +02002861 struct page *page;
Joerg Roedel5d8b53c2008-06-26 21:28:03 +02002862
Joerg Roedel94f6d192009-11-24 16:40:02 +01002863 domain = get_domain(dev);
2864 if (PTR_ERR(domain) == -EINVAL) {
Joerg Roedel3b839a52015-04-01 14:58:47 +02002865 page = alloc_pages(flag, get_order(size));
2866 *dma_addr = page_to_phys(page);
2867 return page_address(page);
Joerg Roedel94f6d192009-11-24 16:40:02 +01002868 } else if (IS_ERR(domain))
2869 return NULL;
Joerg Roedeldbcc1122008-09-04 15:04:26 +02002870
Joerg Roedel3b839a52015-04-01 14:58:47 +02002871 size = PAGE_ALIGN(size);
Joerg Roedelf99c0f12009-11-23 16:52:56 +01002872 dma_mask = dev->coherent_dma_mask;
2873 flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
Joerg Roedel2d0ec7a2015-06-01 17:30:57 +02002874 flag |= __GFP_ZERO;
FUJITA Tomonori13d9fea2008-09-10 20:19:40 +09002875
Joerg Roedel3b839a52015-04-01 14:58:47 +02002876 page = alloc_pages(flag | __GFP_NOWARN, get_order(size));
2877 if (!page) {
Mel Gormand0164ad2015-11-06 16:28:21 -08002878 if (!gfpflags_allow_blocking(flag))
Joerg Roedel3b839a52015-04-01 14:58:47 +02002879 return NULL;
Joerg Roedel5d8b53c2008-06-26 21:28:03 +02002880
Joerg Roedel3b839a52015-04-01 14:58:47 +02002881 page = dma_alloc_from_contiguous(dev, size >> PAGE_SHIFT,
2882 get_order(size));
2883 if (!page)
2884 return NULL;
2885 }
Joerg Roedel5d8b53c2008-06-26 21:28:03 +02002886
Joerg Roedel832a90c2008-09-18 15:54:23 +02002887 if (!dma_mask)
2888 dma_mask = *dev->dma_mask;
2889
Joerg Roedel3b839a52015-04-01 14:58:47 +02002890 *dma_addr = __map_single(dev, domain->priv, page_to_phys(page),
Joerg Roedel832a90c2008-09-18 15:54:23 +02002891 size, DMA_BIDIRECTIONAL, true, dma_mask);
Joerg Roedel5d8b53c2008-06-26 21:28:03 +02002892
Joerg Roedel92d420e2015-12-21 19:31:33 +01002893 if (*dma_addr == DMA_ERROR_CODE)
Joerg Roedel5b28df62008-12-02 17:49:42 +01002894 goto out_free;
Joerg Roedel5d8b53c2008-06-26 21:28:03 +02002895
Joerg Roedel3b839a52015-04-01 14:58:47 +02002896 return page_address(page);
Joerg Roedel5b28df62008-12-02 17:49:42 +01002897
2898out_free:
2899
Joerg Roedel3b839a52015-04-01 14:58:47 +02002900 if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT))
2901 __free_pages(page, get_order(size));
Joerg Roedel5b28df62008-12-02 17:49:42 +01002902
2903 return NULL;
Joerg Roedel5d8b53c2008-06-26 21:28:03 +02002904}
2905
Joerg Roedel431b2a22008-07-11 17:14:22 +02002906/*
2907 * The exported free_coherent function for dma_ops.
Joerg Roedel431b2a22008-07-11 17:14:22 +02002908 */
Joerg Roedel5d8b53c2008-06-26 21:28:03 +02002909static void free_coherent(struct device *dev, size_t size,
Andrzej Pietrasiewiczbaa676f2012-03-27 14:28:18 +02002910 void *virt_addr, dma_addr_t dma_addr,
2911 struct dma_attrs *attrs)
Joerg Roedel5d8b53c2008-06-26 21:28:03 +02002912{
Joerg Roedel5d8b53c2008-06-26 21:28:03 +02002913 struct protection_domain *domain;
Joerg Roedel3b839a52015-04-01 14:58:47 +02002914 struct page *page;
Joerg Roedel5d8b53c2008-06-26 21:28:03 +02002915
Joerg Roedel3b839a52015-04-01 14:58:47 +02002916 page = virt_to_page(virt_addr);
2917 size = PAGE_ALIGN(size);
2918
Joerg Roedel94f6d192009-11-24 16:40:02 +01002919 domain = get_domain(dev);
2920 if (IS_ERR(domain))
Joerg Roedel5b28df62008-12-02 17:49:42 +01002921 goto free_mem;
2922
Joerg Roedelcd8c82e2009-11-23 19:33:56 +01002923 __unmap_single(domain->priv, dma_addr, size, DMA_BIDIRECTIONAL);
Joerg Roedel5d8b53c2008-06-26 21:28:03 +02002924
Joerg Roedel5d8b53c2008-06-26 21:28:03 +02002925free_mem:
Joerg Roedel3b839a52015-04-01 14:58:47 +02002926 if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT))
2927 __free_pages(page, get_order(size));
Joerg Roedel5d8b53c2008-06-26 21:28:03 +02002928}
2929
Joerg Roedelc432f3d2008-06-26 21:28:04 +02002930/*
Joerg Roedelb39ba6a2008-09-09 18:40:46 +02002931 * This function is called by the DMA layer to find out if we can handle a
2932 * particular device. It is part of the dma_ops.
2933 */
2934static int amd_iommu_dma_supported(struct device *dev, u64 mask)
2935{
Joerg Roedel420aef82009-11-23 16:14:57 +01002936 return check_device(dev);
Joerg Roedelb39ba6a2008-09-09 18:40:46 +02002937}
2938
Joerg Roedela639a8e2015-12-22 16:06:49 +01002939static int set_dma_mask(struct device *dev, u64 mask)
2940{
2941 struct protection_domain *domain;
2942 int max_apertures = 1;
2943
2944 domain = get_domain(dev);
2945 if (IS_ERR(domain))
2946 return PTR_ERR(domain);
2947
2948 if (mask == DMA_BIT_MASK(64))
2949 max_apertures = 8;
2950 else if (mask > DMA_BIT_MASK(32))
2951 max_apertures = 4;
2952
2953 /*
2954 * To prevent lock contention it doesn't make sense to allocate more
2955 * apertures than online cpus
2956 */
2957 if (max_apertures > num_online_cpus())
2958 max_apertures = num_online_cpus();
2959
2960 if (dma_ops_domain_alloc_apertures(domain->priv, max_apertures))
2961 dev_err(dev, "Can't allocate %d iommu apertures\n",
2962 max_apertures);
2963
2964 return 0;
2965}
2966
FUJITA Tomonori160c1d82009-01-05 23:59:02 +09002967static struct dma_map_ops amd_iommu_dma_ops = {
Joerg Roedela639a8e2015-12-22 16:06:49 +01002968 .alloc = alloc_coherent,
2969 .free = free_coherent,
2970 .map_page = map_page,
2971 .unmap_page = unmap_page,
2972 .map_sg = map_sg,
2973 .unmap_sg = unmap_sg,
2974 .dma_supported = amd_iommu_dma_supported,
2975 .set_dma_mask = set_dma_mask,
Joerg Roedel6631ee92008-06-26 21:28:05 +02002976};
2977
Joerg Roedel81cd07b2016-07-07 18:01:10 +02002978static int init_reserved_iova_ranges(void)
2979{
2980 struct pci_dev *pdev = NULL;
2981 struct iova *val;
2982
2983 init_iova_domain(&reserved_iova_ranges, PAGE_SIZE,
2984 IOVA_START_PFN, DMA_32BIT_PFN);
2985
2986 lockdep_set_class(&reserved_iova_ranges.iova_rbtree_lock,
2987 &reserved_rbtree_key);
2988
2989 /* MSI memory range */
2990 val = reserve_iova(&reserved_iova_ranges,
2991 IOVA_PFN(MSI_RANGE_START), IOVA_PFN(MSI_RANGE_END));
2992 if (!val) {
2993 pr_err("Reserving MSI range failed\n");
2994 return -ENOMEM;
2995 }
2996
2997 /* HT memory range */
2998 val = reserve_iova(&reserved_iova_ranges,
2999 IOVA_PFN(HT_RANGE_START), IOVA_PFN(HT_RANGE_END));
3000 if (!val) {
3001 pr_err("Reserving HT range failed\n");
3002 return -ENOMEM;
3003 }
3004
3005 /*
3006 * Memory used for PCI resources
3007 * FIXME: Check whether we can reserve the PCI-hole completly
3008 */
3009 for_each_pci_dev(pdev) {
3010 int i;
3011
3012 for (i = 0; i < PCI_NUM_RESOURCES; ++i) {
3013 struct resource *r = &pdev->resource[i];
3014
3015 if (!(r->flags & IORESOURCE_MEM))
3016 continue;
3017
3018 val = reserve_iova(&reserved_iova_ranges,
3019 IOVA_PFN(r->start),
3020 IOVA_PFN(r->end));
3021 if (!val) {
3022 pr_err("Reserve pci-resource range failed\n");
3023 return -ENOMEM;
3024 }
3025 }
3026 }
3027
3028 return 0;
3029}
3030
Joerg Roedel3a18404c2015-05-28 18:41:45 +02003031int __init amd_iommu_init_api(void)
Joerg Roedel27c21272011-05-30 15:56:24 +02003032{
Joerg Roedel307d5852016-07-05 11:54:04 +02003033 int ret, err = 0;
3034
3035 ret = iova_cache_get();
3036 if (ret)
3037 return ret;
Wan Zongshun9a4d3bf52016-04-01 09:06:05 -04003038
Joerg Roedel81cd07b2016-07-07 18:01:10 +02003039 ret = init_reserved_iova_ranges();
3040 if (ret)
3041 return ret;
3042
Wan Zongshun9a4d3bf52016-04-01 09:06:05 -04003043 err = bus_set_iommu(&pci_bus_type, &amd_iommu_ops);
3044 if (err)
3045 return err;
3046#ifdef CONFIG_ARM_AMBA
3047 err = bus_set_iommu(&amba_bustype, &amd_iommu_ops);
3048 if (err)
3049 return err;
3050#endif
Wan Zongshun0076cd32016-05-10 09:21:01 -04003051 err = bus_set_iommu(&platform_bus_type, &amd_iommu_ops);
3052 if (err)
3053 return err;
Wan Zongshun9a4d3bf52016-04-01 09:06:05 -04003054 return 0;
Joerg Roedelf5325092010-01-22 17:44:35 +01003055}
3056
Joerg Roedel6631ee92008-06-26 21:28:05 +02003057int __init amd_iommu_init_dma_ops(void)
3058{
Joerg Roedel32302322015-07-28 16:58:50 +02003059 swiotlb = iommu_pass_through ? 1 : 0;
Joerg Roedel6631ee92008-06-26 21:28:05 +02003060 iommu_detected = 1;
Joerg Roedel6631ee92008-06-26 21:28:05 +02003061
Joerg Roedel52717822015-07-28 16:58:51 +02003062 /*
3063 * In case we don't initialize SWIOTLB (actually the common case
3064 * when AMD IOMMU is enabled), make sure there are global
3065 * dma_ops set as a fall-back for devices not handled by this
3066 * driver (for example non-PCI devices).
3067 */
3068 if (!swiotlb)
3069 dma_ops = &nommu_dma_ops;
3070
Joerg Roedel62410ee2012-06-12 16:42:43 +02003071 if (amd_iommu_unmap_flush)
3072 pr_info("AMD-Vi: IO/TLB flush on unmap enabled\n");
3073 else
3074 pr_info("AMD-Vi: Lazy IO/TLB flushing enabled\n");
3075
Joerg Roedel6631ee92008-06-26 21:28:05 +02003076 return 0;
Joerg Roedel6631ee92008-06-26 21:28:05 +02003077}
Joerg Roedel6d98cd82008-12-08 12:05:55 +01003078
3079/*****************************************************************************
3080 *
3081 * The following functions belong to the exported interface of AMD IOMMU
3082 *
3083 * This interface allows access to lower level functions of the IOMMU
3084 * like protection domain handling and assignement of devices to domains
3085 * which is not possible with the dma_ops interface.
3086 *
3087 *****************************************************************************/
3088
Joerg Roedel6d98cd82008-12-08 12:05:55 +01003089static void cleanup_domain(struct protection_domain *domain)
3090{
Joerg Roedel9b29d3c2014-08-05 17:50:15 +02003091 struct iommu_dev_data *entry;
Joerg Roedel6d98cd82008-12-08 12:05:55 +01003092 unsigned long flags;
Joerg Roedel6d98cd82008-12-08 12:05:55 +01003093
3094 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
3095
Joerg Roedel9b29d3c2014-08-05 17:50:15 +02003096 while (!list_empty(&domain->dev_list)) {
3097 entry = list_first_entry(&domain->dev_list,
3098 struct iommu_dev_data, list);
3099 __detach_device(entry);
Joerg Roedel492667d2009-11-27 13:25:47 +01003100 }
Joerg Roedel6d98cd82008-12-08 12:05:55 +01003101
3102 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
3103}
3104
Joerg Roedel26508152009-08-26 16:52:40 +02003105static void protection_domain_free(struct protection_domain *domain)
3106{
3107 if (!domain)
3108 return;
3109
Joerg Roedelaeb26f52009-11-20 16:44:01 +01003110 del_domain_from_list(domain);
3111
Joerg Roedel26508152009-08-26 16:52:40 +02003112 if (domain->id)
3113 domain_id_free(domain->id);
3114
3115 kfree(domain);
3116}
3117
Joerg Roedel7a5a5662015-06-30 08:56:11 +02003118static int protection_domain_init(struct protection_domain *domain)
3119{
3120 spin_lock_init(&domain->lock);
3121 mutex_init(&domain->api_lock);
3122 domain->id = domain_id_alloc();
3123 if (!domain->id)
3124 return -ENOMEM;
3125 INIT_LIST_HEAD(&domain->dev_list);
3126
3127 return 0;
3128}
3129
Joerg Roedel26508152009-08-26 16:52:40 +02003130static struct protection_domain *protection_domain_alloc(void)
Joerg Roedelc156e342008-12-02 18:13:27 +01003131{
3132 struct protection_domain *domain;
3133
3134 domain = kzalloc(sizeof(*domain), GFP_KERNEL);
3135 if (!domain)
Joerg Roedel26508152009-08-26 16:52:40 +02003136 return NULL;
Joerg Roedelc156e342008-12-02 18:13:27 +01003137
Joerg Roedel7a5a5662015-06-30 08:56:11 +02003138 if (protection_domain_init(domain))
Joerg Roedel26508152009-08-26 16:52:40 +02003139 goto out_err;
3140
Joerg Roedelaeb26f52009-11-20 16:44:01 +01003141 add_domain_to_list(domain);
3142
Joerg Roedel26508152009-08-26 16:52:40 +02003143 return domain;
3144
3145out_err:
3146 kfree(domain);
3147
3148 return NULL;
3149}
3150
Joerg Roedel3f4b87b2015-03-26 13:43:07 +01003151static struct iommu_domain *amd_iommu_domain_alloc(unsigned type)
3152{
3153 struct protection_domain *pdomain;
Joerg Roedel0bb6e242015-05-28 18:41:40 +02003154 struct dma_ops_domain *dma_domain;
Joerg Roedel3f4b87b2015-03-26 13:43:07 +01003155
Joerg Roedel0bb6e242015-05-28 18:41:40 +02003156 switch (type) {
3157 case IOMMU_DOMAIN_UNMANAGED:
3158 pdomain = protection_domain_alloc();
3159 if (!pdomain)
3160 return NULL;
3161
3162 pdomain->mode = PAGE_MODE_3_LEVEL;
3163 pdomain->pt_root = (void *)get_zeroed_page(GFP_KERNEL);
3164 if (!pdomain->pt_root) {
3165 protection_domain_free(pdomain);
3166 return NULL;
3167 }
3168
3169 pdomain->domain.geometry.aperture_start = 0;
3170 pdomain->domain.geometry.aperture_end = ~0ULL;
3171 pdomain->domain.geometry.force_aperture = true;
3172
3173 break;
3174 case IOMMU_DOMAIN_DMA:
3175 dma_domain = dma_ops_domain_alloc();
3176 if (!dma_domain) {
3177 pr_err("AMD-Vi: Failed to allocate\n");
3178 return NULL;
3179 }
3180 pdomain = &dma_domain->domain;
3181 break;
Joerg Roedel07f643a2015-05-28 18:41:41 +02003182 case IOMMU_DOMAIN_IDENTITY:
3183 pdomain = protection_domain_alloc();
3184 if (!pdomain)
3185 return NULL;
3186
3187 pdomain->mode = PAGE_MODE_NONE;
3188 break;
Joerg Roedel0bb6e242015-05-28 18:41:40 +02003189 default:
Joerg Roedel3f4b87b2015-03-26 13:43:07 +01003190 return NULL;
Joerg Roedel0bb6e242015-05-28 18:41:40 +02003191 }
Joerg Roedel3f4b87b2015-03-26 13:43:07 +01003192
3193 return &pdomain->domain;
Joerg Roedel3f4b87b2015-03-26 13:43:07 +01003194}
3195
3196static void amd_iommu_domain_free(struct iommu_domain *dom)
Joerg Roedel26508152009-08-26 16:52:40 +02003197{
3198 struct protection_domain *domain;
3199
Joerg Roedel3f4b87b2015-03-26 13:43:07 +01003200 if (!dom)
Joerg Roedel98383fc2008-12-02 18:34:12 +01003201 return;
3202
Joerg Roedel3f4b87b2015-03-26 13:43:07 +01003203 domain = to_pdomain(dom);
3204
Joerg Roedel98383fc2008-12-02 18:34:12 +01003205 if (domain->dev_cnt > 0)
3206 cleanup_domain(domain);
3207
3208 BUG_ON(domain->dev_cnt != 0);
3209
Joerg Roedel132bd682011-11-17 14:18:46 +01003210 if (domain->mode != PAGE_MODE_NONE)
3211 free_pagetable(domain);
Joerg Roedel98383fc2008-12-02 18:34:12 +01003212
Joerg Roedel52815b72011-11-17 17:24:28 +01003213 if (domain->flags & PD_IOMMUV2_MASK)
3214 free_gcr3_table(domain);
3215
Joerg Roedel8b408fe2010-03-08 14:20:07 +01003216 protection_domain_free(domain);
Joerg Roedel98383fc2008-12-02 18:34:12 +01003217}
3218
Joerg Roedel684f2882008-12-08 12:07:44 +01003219static void amd_iommu_detach_device(struct iommu_domain *dom,
3220 struct device *dev)
3221{
Joerg Roedel657cbb62009-11-23 15:26:46 +01003222 struct iommu_dev_data *dev_data = dev->archdata.iommu;
Joerg Roedel684f2882008-12-08 12:07:44 +01003223 struct amd_iommu *iommu;
Wan Zongshun7aba6cb2016-04-01 09:06:02 -04003224 int devid;
Joerg Roedel684f2882008-12-08 12:07:44 +01003225
Joerg Roedel98fc5a62009-11-24 17:19:23 +01003226 if (!check_device(dev))
Joerg Roedel684f2882008-12-08 12:07:44 +01003227 return;
3228
Joerg Roedel98fc5a62009-11-24 17:19:23 +01003229 devid = get_device_id(dev);
Joerg Roedel9ee35e42016-04-21 18:21:31 +02003230 if (devid < 0)
Wan Zongshun7aba6cb2016-04-01 09:06:02 -04003231 return;
Joerg Roedel684f2882008-12-08 12:07:44 +01003232
Joerg Roedel657cbb62009-11-23 15:26:46 +01003233 if (dev_data->domain != NULL)
Joerg Roedel15898bb2009-11-24 15:39:42 +01003234 detach_device(dev);
Joerg Roedel684f2882008-12-08 12:07:44 +01003235
3236 iommu = amd_iommu_rlookup_table[devid];
3237 if (!iommu)
3238 return;
3239
Joerg Roedel684f2882008-12-08 12:07:44 +01003240 iommu_completion_wait(iommu);
3241}
3242
Joerg Roedel01106062008-12-02 19:34:11 +01003243static int amd_iommu_attach_device(struct iommu_domain *dom,
3244 struct device *dev)
3245{
Joerg Roedel3f4b87b2015-03-26 13:43:07 +01003246 struct protection_domain *domain = to_pdomain(dom);
Joerg Roedel657cbb62009-11-23 15:26:46 +01003247 struct iommu_dev_data *dev_data;
Joerg Roedel01106062008-12-02 19:34:11 +01003248 struct amd_iommu *iommu;
Joerg Roedel15898bb2009-11-24 15:39:42 +01003249 int ret;
Joerg Roedel01106062008-12-02 19:34:11 +01003250
Joerg Roedel98fc5a62009-11-24 17:19:23 +01003251 if (!check_device(dev))
Joerg Roedel01106062008-12-02 19:34:11 +01003252 return -EINVAL;
3253
Joerg Roedel657cbb62009-11-23 15:26:46 +01003254 dev_data = dev->archdata.iommu;
3255
Joerg Roedelf62dda62011-06-09 12:55:35 +02003256 iommu = amd_iommu_rlookup_table[dev_data->devid];
Joerg Roedel01106062008-12-02 19:34:11 +01003257 if (!iommu)
3258 return -EINVAL;
3259
Joerg Roedel657cbb62009-11-23 15:26:46 +01003260 if (dev_data->domain)
Joerg Roedel15898bb2009-11-24 15:39:42 +01003261 detach_device(dev);
Joerg Roedel01106062008-12-02 19:34:11 +01003262
Joerg Roedel15898bb2009-11-24 15:39:42 +01003263 ret = attach_device(dev, domain);
Joerg Roedel01106062008-12-02 19:34:11 +01003264
3265 iommu_completion_wait(iommu);
3266
Joerg Roedel15898bb2009-11-24 15:39:42 +01003267 return ret;
Joerg Roedel01106062008-12-02 19:34:11 +01003268}
3269
Joerg Roedel468e2362010-01-21 16:37:36 +01003270static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova,
Ohad Ben-Cohen50090652011-11-10 11:32:25 +02003271 phys_addr_t paddr, size_t page_size, int iommu_prot)
Joerg Roedelc6229ca2008-12-02 19:48:43 +01003272{
Joerg Roedel3f4b87b2015-03-26 13:43:07 +01003273 struct protection_domain *domain = to_pdomain(dom);
Joerg Roedelc6229ca2008-12-02 19:48:43 +01003274 int prot = 0;
3275 int ret;
3276
Joerg Roedel132bd682011-11-17 14:18:46 +01003277 if (domain->mode == PAGE_MODE_NONE)
3278 return -EINVAL;
3279
Joerg Roedelc6229ca2008-12-02 19:48:43 +01003280 if (iommu_prot & IOMMU_READ)
3281 prot |= IOMMU_PROT_IR;
3282 if (iommu_prot & IOMMU_WRITE)
3283 prot |= IOMMU_PROT_IW;
3284
Joerg Roedel5d214fe2010-02-08 14:44:49 +01003285 mutex_lock(&domain->api_lock);
Joerg Roedel795e74f2010-05-11 17:40:57 +02003286 ret = iommu_map_page(domain, iova, paddr, prot, page_size);
Joerg Roedel5d214fe2010-02-08 14:44:49 +01003287 mutex_unlock(&domain->api_lock);
3288
Joerg Roedel795e74f2010-05-11 17:40:57 +02003289 return ret;
Joerg Roedelc6229ca2008-12-02 19:48:43 +01003290}
3291
Ohad Ben-Cohen50090652011-11-10 11:32:25 +02003292static size_t amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova,
3293 size_t page_size)
Joerg Roedeleb74ff62008-12-02 19:59:10 +01003294{
Joerg Roedel3f4b87b2015-03-26 13:43:07 +01003295 struct protection_domain *domain = to_pdomain(dom);
Ohad Ben-Cohen50090652011-11-10 11:32:25 +02003296 size_t unmap_size;
Joerg Roedeleb74ff62008-12-02 19:59:10 +01003297
Joerg Roedel132bd682011-11-17 14:18:46 +01003298 if (domain->mode == PAGE_MODE_NONE)
3299 return -EINVAL;
3300
Joerg Roedel5d214fe2010-02-08 14:44:49 +01003301 mutex_lock(&domain->api_lock);
Joerg Roedel468e2362010-01-21 16:37:36 +01003302 unmap_size = iommu_unmap_page(domain, iova, page_size);
Joerg Roedel795e74f2010-05-11 17:40:57 +02003303 mutex_unlock(&domain->api_lock);
Joerg Roedeleb74ff62008-12-02 19:59:10 +01003304
Joerg Roedel17b124b2011-04-06 18:01:35 +02003305 domain_flush_tlb_pde(domain);
Joerg Roedel5d214fe2010-02-08 14:44:49 +01003306
Ohad Ben-Cohen50090652011-11-10 11:32:25 +02003307 return unmap_size;
Joerg Roedeleb74ff62008-12-02 19:59:10 +01003308}
3309
Joerg Roedel645c4c82008-12-02 20:05:50 +01003310static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
Varun Sethibb5547ac2013-03-29 01:23:58 +05303311 dma_addr_t iova)
Joerg Roedel645c4c82008-12-02 20:05:50 +01003312{
Joerg Roedel3f4b87b2015-03-26 13:43:07 +01003313 struct protection_domain *domain = to_pdomain(dom);
Joerg Roedel3039ca12015-04-01 14:58:48 +02003314 unsigned long offset_mask, pte_pgsize;
Joerg Roedelf03152b2010-01-21 16:15:24 +01003315 u64 *pte, __pte;
Joerg Roedel645c4c82008-12-02 20:05:50 +01003316
Joerg Roedel132bd682011-11-17 14:18:46 +01003317 if (domain->mode == PAGE_MODE_NONE)
3318 return iova;
3319
Joerg Roedel3039ca12015-04-01 14:58:48 +02003320 pte = fetch_pte(domain, iova, &pte_pgsize);
Joerg Roedel645c4c82008-12-02 20:05:50 +01003321
Joerg Roedela6d41a42009-09-02 17:08:55 +02003322 if (!pte || !IOMMU_PTE_PRESENT(*pte))
Joerg Roedel645c4c82008-12-02 20:05:50 +01003323 return 0;
3324
Joerg Roedelb24b1b62015-04-01 14:58:51 +02003325 offset_mask = pte_pgsize - 1;
3326 __pte = *pte & PM_ADDR_MASK;
Joerg Roedelf03152b2010-01-21 16:15:24 +01003327
Joerg Roedelb24b1b62015-04-01 14:58:51 +02003328 return (__pte & ~offset_mask) | (iova & offset_mask);
Joerg Roedel645c4c82008-12-02 20:05:50 +01003329}
3330
Joerg Roedelab636482014-09-05 10:48:21 +02003331static bool amd_iommu_capable(enum iommu_cap cap)
Sheng Yangdbb9fd82009-03-18 15:33:06 +08003332{
Joerg Roedel80a506b2010-07-27 17:14:24 +02003333 switch (cap) {
3334 case IOMMU_CAP_CACHE_COHERENCY:
Joerg Roedelab636482014-09-05 10:48:21 +02003335 return true;
Joerg Roedelbdddadc2012-07-02 18:38:13 +02003336 case IOMMU_CAP_INTR_REMAP:
Joerg Roedelab636482014-09-05 10:48:21 +02003337 return (irq_remapping_enabled == 1);
Will Deaconcfdeec22014-10-27 11:24:48 +00003338 case IOMMU_CAP_NOEXEC:
3339 return false;
Joerg Roedel80a506b2010-07-27 17:14:24 +02003340 }
3341
Joerg Roedelab636482014-09-05 10:48:21 +02003342 return false;
Sheng Yangdbb9fd82009-03-18 15:33:06 +08003343}
3344
Joerg Roedel35cf2482015-05-28 18:41:37 +02003345static void amd_iommu_get_dm_regions(struct device *dev,
3346 struct list_head *head)
3347{
3348 struct unity_map_entry *entry;
Wan Zongshun7aba6cb2016-04-01 09:06:02 -04003349 int devid;
Joerg Roedel35cf2482015-05-28 18:41:37 +02003350
3351 devid = get_device_id(dev);
Joerg Roedel9ee35e42016-04-21 18:21:31 +02003352 if (devid < 0)
Wan Zongshun7aba6cb2016-04-01 09:06:02 -04003353 return;
Joerg Roedel35cf2482015-05-28 18:41:37 +02003354
3355 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
3356 struct iommu_dm_region *region;
3357
3358 if (devid < entry->devid_start || devid > entry->devid_end)
3359 continue;
3360
3361 region = kzalloc(sizeof(*region), GFP_KERNEL);
3362 if (!region) {
3363 pr_err("Out of memory allocating dm-regions for %s\n",
3364 dev_name(dev));
3365 return;
3366 }
3367
3368 region->start = entry->address_start;
3369 region->length = entry->address_end - entry->address_start;
3370 if (entry->prot & IOMMU_PROT_IR)
3371 region->prot |= IOMMU_READ;
3372 if (entry->prot & IOMMU_PROT_IW)
3373 region->prot |= IOMMU_WRITE;
3374
3375 list_add_tail(&region->list, head);
3376 }
3377}
3378
3379static void amd_iommu_put_dm_regions(struct device *dev,
3380 struct list_head *head)
3381{
3382 struct iommu_dm_region *entry, *next;
3383
3384 list_for_each_entry_safe(entry, next, head, list)
3385 kfree(entry);
3386}
3387
Thierry Redingb22f6432014-06-27 09:03:12 +02003388static const struct iommu_ops amd_iommu_ops = {
Joerg Roedelab636482014-09-05 10:48:21 +02003389 .capable = amd_iommu_capable,
Joerg Roedel3f4b87b2015-03-26 13:43:07 +01003390 .domain_alloc = amd_iommu_domain_alloc,
3391 .domain_free = amd_iommu_domain_free,
Joerg Roedel26961ef2008-12-03 17:00:17 +01003392 .attach_dev = amd_iommu_attach_device,
3393 .detach_dev = amd_iommu_detach_device,
Joerg Roedel468e2362010-01-21 16:37:36 +01003394 .map = amd_iommu_map,
3395 .unmap = amd_iommu_unmap,
Olav Haugan315786e2014-10-25 09:55:16 -07003396 .map_sg = default_iommu_map_sg,
Joerg Roedel26961ef2008-12-03 17:00:17 +01003397 .iova_to_phys = amd_iommu_iova_to_phys,
Joerg Roedelaafd8ba2015-05-28 18:41:39 +02003398 .add_device = amd_iommu_add_device,
3399 .remove_device = amd_iommu_remove_device,
Wan Zongshunb097d112016-04-01 09:06:04 -04003400 .device_group = amd_iommu_device_group,
Joerg Roedel35cf2482015-05-28 18:41:37 +02003401 .get_dm_regions = amd_iommu_get_dm_regions,
3402 .put_dm_regions = amd_iommu_put_dm_regions,
Ohad Ben-Cohenaa3de9c2011-11-10 11:32:29 +02003403 .pgsize_bitmap = AMD_IOMMU_PGSIZES,
Joerg Roedel26961ef2008-12-03 17:00:17 +01003404};
3405
Joerg Roedel0feae532009-08-26 15:26:30 +02003406/*****************************************************************************
3407 *
3408 * The next functions do a basic initialization of IOMMU for pass through
3409 * mode
3410 *
3411 * In passthrough mode the IOMMU is initialized and enabled but not used for
3412 * DMA-API translation.
3413 *
3414 *****************************************************************************/
3415
Joerg Roedel72e1dcc2011-11-10 19:13:51 +01003416/* IOMMUv2 specific functions */
3417int amd_iommu_register_ppr_notifier(struct notifier_block *nb)
3418{
3419 return atomic_notifier_chain_register(&ppr_notifier, nb);
3420}
3421EXPORT_SYMBOL(amd_iommu_register_ppr_notifier);
3422
3423int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb)
3424{
3425 return atomic_notifier_chain_unregister(&ppr_notifier, nb);
3426}
3427EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier);
Joerg Roedel132bd682011-11-17 14:18:46 +01003428
3429void amd_iommu_domain_direct_map(struct iommu_domain *dom)
3430{
Joerg Roedel3f4b87b2015-03-26 13:43:07 +01003431 struct protection_domain *domain = to_pdomain(dom);
Joerg Roedel132bd682011-11-17 14:18:46 +01003432 unsigned long flags;
3433
3434 spin_lock_irqsave(&domain->lock, flags);
3435
3436 /* Update data structure */
3437 domain->mode = PAGE_MODE_NONE;
3438 domain->updated = true;
3439
3440 /* Make changes visible to IOMMUs */
3441 update_domain(domain);
3442
3443 /* Page-table is not visible to IOMMU anymore, so free it */
3444 free_pagetable(domain);
3445
3446 spin_unlock_irqrestore(&domain->lock, flags);
3447}
3448EXPORT_SYMBOL(amd_iommu_domain_direct_map);
Joerg Roedel52815b72011-11-17 17:24:28 +01003449
3450int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids)
3451{
Joerg Roedel3f4b87b2015-03-26 13:43:07 +01003452 struct protection_domain *domain = to_pdomain(dom);
Joerg Roedel52815b72011-11-17 17:24:28 +01003453 unsigned long flags;
3454 int levels, ret;
3455
3456 if (pasids <= 0 || pasids > (PASID_MASK + 1))
3457 return -EINVAL;
3458
3459 /* Number of GCR3 table levels required */
3460 for (levels = 0; (pasids - 1) & ~0x1ff; pasids >>= 9)
3461 levels += 1;
3462
3463 if (levels > amd_iommu_max_glx_val)
3464 return -EINVAL;
3465
3466 spin_lock_irqsave(&domain->lock, flags);
3467
3468 /*
3469 * Save us all sanity checks whether devices already in the
3470 * domain support IOMMUv2. Just force that the domain has no
3471 * devices attached when it is switched into IOMMUv2 mode.
3472 */
3473 ret = -EBUSY;
3474 if (domain->dev_cnt > 0 || domain->flags & PD_IOMMUV2_MASK)
3475 goto out;
3476
3477 ret = -ENOMEM;
3478 domain->gcr3_tbl = (void *)get_zeroed_page(GFP_ATOMIC);
3479 if (domain->gcr3_tbl == NULL)
3480 goto out;
3481
3482 domain->glx = levels;
3483 domain->flags |= PD_IOMMUV2_MASK;
3484 domain->updated = true;
3485
3486 update_domain(domain);
3487
3488 ret = 0;
3489
3490out:
3491 spin_unlock_irqrestore(&domain->lock, flags);
3492
3493 return ret;
3494}
3495EXPORT_SYMBOL(amd_iommu_domain_enable_v2);
Joerg Roedel22e266c2011-11-21 15:59:08 +01003496
3497static int __flush_pasid(struct protection_domain *domain, int pasid,
3498 u64 address, bool size)
3499{
3500 struct iommu_dev_data *dev_data;
3501 struct iommu_cmd cmd;
3502 int i, ret;
3503
3504 if (!(domain->flags & PD_IOMMUV2_MASK))
3505 return -EINVAL;
3506
3507 build_inv_iommu_pasid(&cmd, domain->id, pasid, address, size);
3508
3509 /*
3510 * IOMMU TLB needs to be flushed before Device TLB to
3511 * prevent device TLB refill from IOMMU TLB
3512 */
3513 for (i = 0; i < amd_iommus_present; ++i) {
3514 if (domain->dev_iommu[i] == 0)
3515 continue;
3516
3517 ret = iommu_queue_command(amd_iommus[i], &cmd);
3518 if (ret != 0)
3519 goto out;
3520 }
3521
3522 /* Wait until IOMMU TLB flushes are complete */
3523 domain_flush_complete(domain);
3524
3525 /* Now flush device TLBs */
3526 list_for_each_entry(dev_data, &domain->dev_list, list) {
3527 struct amd_iommu *iommu;
3528 int qdep;
3529
Joerg Roedel1c1cc452015-07-30 11:24:45 +02003530 /*
3531 There might be non-IOMMUv2 capable devices in an IOMMUv2
3532 * domain.
3533 */
3534 if (!dev_data->ats.enabled)
3535 continue;
Joerg Roedel22e266c2011-11-21 15:59:08 +01003536
3537 qdep = dev_data->ats.qdep;
3538 iommu = amd_iommu_rlookup_table[dev_data->devid];
3539
3540 build_inv_iotlb_pasid(&cmd, dev_data->devid, pasid,
3541 qdep, address, size);
3542
3543 ret = iommu_queue_command(iommu, &cmd);
3544 if (ret != 0)
3545 goto out;
3546 }
3547
3548 /* Wait until all device TLBs are flushed */
3549 domain_flush_complete(domain);
3550
3551 ret = 0;
3552
3553out:
3554
3555 return ret;
3556}
3557
3558static int __amd_iommu_flush_page(struct protection_domain *domain, int pasid,
3559 u64 address)
3560{
3561 return __flush_pasid(domain, pasid, address, false);
3562}
3563
3564int amd_iommu_flush_page(struct iommu_domain *dom, int pasid,
3565 u64 address)
3566{
Joerg Roedel3f4b87b2015-03-26 13:43:07 +01003567 struct protection_domain *domain = to_pdomain(dom);
Joerg Roedel22e266c2011-11-21 15:59:08 +01003568 unsigned long flags;
3569 int ret;
3570
3571 spin_lock_irqsave(&domain->lock, flags);
3572 ret = __amd_iommu_flush_page(domain, pasid, address);
3573 spin_unlock_irqrestore(&domain->lock, flags);
3574
3575 return ret;
3576}
3577EXPORT_SYMBOL(amd_iommu_flush_page);
3578
3579static int __amd_iommu_flush_tlb(struct protection_domain *domain, int pasid)
3580{
3581 return __flush_pasid(domain, pasid, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
3582 true);
3583}
3584
3585int amd_iommu_flush_tlb(struct iommu_domain *dom, int pasid)
3586{
Joerg Roedel3f4b87b2015-03-26 13:43:07 +01003587 struct protection_domain *domain = to_pdomain(dom);
Joerg Roedel22e266c2011-11-21 15:59:08 +01003588 unsigned long flags;
3589 int ret;
3590
3591 spin_lock_irqsave(&domain->lock, flags);
3592 ret = __amd_iommu_flush_tlb(domain, pasid);
3593 spin_unlock_irqrestore(&domain->lock, flags);
3594
3595 return ret;
3596}
3597EXPORT_SYMBOL(amd_iommu_flush_tlb);
3598
Joerg Roedelb16137b2011-11-21 16:50:23 +01003599static u64 *__get_gcr3_pte(u64 *root, int level, int pasid, bool alloc)
3600{
3601 int index;
3602 u64 *pte;
3603
3604 while (true) {
3605
3606 index = (pasid >> (9 * level)) & 0x1ff;
3607 pte = &root[index];
3608
3609 if (level == 0)
3610 break;
3611
3612 if (!(*pte & GCR3_VALID)) {
3613 if (!alloc)
3614 return NULL;
3615
3616 root = (void *)get_zeroed_page(GFP_ATOMIC);
3617 if (root == NULL)
3618 return NULL;
3619
3620 *pte = __pa(root) | GCR3_VALID;
3621 }
3622
3623 root = __va(*pte & PAGE_MASK);
3624
3625 level -= 1;
3626 }
3627
3628 return pte;
3629}
3630
3631static int __set_gcr3(struct protection_domain *domain, int pasid,
3632 unsigned long cr3)
3633{
3634 u64 *pte;
3635
3636 if (domain->mode != PAGE_MODE_NONE)
3637 return -EINVAL;
3638
3639 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, true);
3640 if (pte == NULL)
3641 return -ENOMEM;
3642
3643 *pte = (cr3 & PAGE_MASK) | GCR3_VALID;
3644
3645 return __amd_iommu_flush_tlb(domain, pasid);
3646}
3647
3648static int __clear_gcr3(struct protection_domain *domain, int pasid)
3649{
3650 u64 *pte;
3651
3652 if (domain->mode != PAGE_MODE_NONE)
3653 return -EINVAL;
3654
3655 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, false);
3656 if (pte == NULL)
3657 return 0;
3658
3659 *pte = 0;
3660
3661 return __amd_iommu_flush_tlb(domain, pasid);
3662}
3663
3664int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, int pasid,
3665 unsigned long cr3)
3666{
Joerg Roedel3f4b87b2015-03-26 13:43:07 +01003667 struct protection_domain *domain = to_pdomain(dom);
Joerg Roedelb16137b2011-11-21 16:50:23 +01003668 unsigned long flags;
3669 int ret;
3670
3671 spin_lock_irqsave(&domain->lock, flags);
3672 ret = __set_gcr3(domain, pasid, cr3);
3673 spin_unlock_irqrestore(&domain->lock, flags);
3674
3675 return ret;
3676}
3677EXPORT_SYMBOL(amd_iommu_domain_set_gcr3);
3678
3679int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, int pasid)
3680{
Joerg Roedel3f4b87b2015-03-26 13:43:07 +01003681 struct protection_domain *domain = to_pdomain(dom);
Joerg Roedelb16137b2011-11-21 16:50:23 +01003682 unsigned long flags;
3683 int ret;
3684
3685 spin_lock_irqsave(&domain->lock, flags);
3686 ret = __clear_gcr3(domain, pasid);
3687 spin_unlock_irqrestore(&domain->lock, flags);
3688
3689 return ret;
3690}
3691EXPORT_SYMBOL(amd_iommu_domain_clear_gcr3);
Joerg Roedelc99afa22011-11-21 18:19:25 +01003692
3693int amd_iommu_complete_ppr(struct pci_dev *pdev, int pasid,
3694 int status, int tag)
3695{
3696 struct iommu_dev_data *dev_data;
3697 struct amd_iommu *iommu;
3698 struct iommu_cmd cmd;
3699
3700 dev_data = get_dev_data(&pdev->dev);
3701 iommu = amd_iommu_rlookup_table[dev_data->devid];
3702
3703 build_complete_ppr(&cmd, dev_data->devid, pasid, status,
3704 tag, dev_data->pri_tlp);
3705
3706 return iommu_queue_command(iommu, &cmd);
3707}
3708EXPORT_SYMBOL(amd_iommu_complete_ppr);
Joerg Roedelf3572db2011-11-23 12:36:25 +01003709
3710struct iommu_domain *amd_iommu_get_v2_domain(struct pci_dev *pdev)
3711{
Joerg Roedel3f4b87b2015-03-26 13:43:07 +01003712 struct protection_domain *pdomain;
Joerg Roedelf3572db2011-11-23 12:36:25 +01003713
Joerg Roedel3f4b87b2015-03-26 13:43:07 +01003714 pdomain = get_domain(&pdev->dev);
3715 if (IS_ERR(pdomain))
Joerg Roedelf3572db2011-11-23 12:36:25 +01003716 return NULL;
3717
3718 /* Only return IOMMUv2 domains */
Joerg Roedel3f4b87b2015-03-26 13:43:07 +01003719 if (!(pdomain->flags & PD_IOMMUV2_MASK))
Joerg Roedelf3572db2011-11-23 12:36:25 +01003720 return NULL;
3721
Joerg Roedel3f4b87b2015-03-26 13:43:07 +01003722 return &pdomain->domain;
Joerg Roedelf3572db2011-11-23 12:36:25 +01003723}
3724EXPORT_SYMBOL(amd_iommu_get_v2_domain);
Joerg Roedel6a113dd2011-12-01 12:04:58 +01003725
3726void amd_iommu_enable_device_erratum(struct pci_dev *pdev, u32 erratum)
3727{
3728 struct iommu_dev_data *dev_data;
3729
3730 if (!amd_iommu_v2_supported())
3731 return;
3732
3733 dev_data = get_dev_data(&pdev->dev);
3734 dev_data->errata |= (1 << erratum);
3735}
3736EXPORT_SYMBOL(amd_iommu_enable_device_erratum);
Joerg Roedel52efdb82011-12-07 12:01:36 +01003737
3738int amd_iommu_device_info(struct pci_dev *pdev,
3739 struct amd_iommu_device_info *info)
3740{
3741 int max_pasids;
3742 int pos;
3743
3744 if (pdev == NULL || info == NULL)
3745 return -EINVAL;
3746
3747 if (!amd_iommu_v2_supported())
3748 return -EINVAL;
3749
3750 memset(info, 0, sizeof(*info));
3751
3752 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ATS);
3753 if (pos)
3754 info->flags |= AMD_IOMMU_DEVICE_FLAG_ATS_SUP;
3755
3756 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
3757 if (pos)
3758 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRI_SUP;
3759
3760 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
3761 if (pos) {
3762 int features;
3763
3764 max_pasids = 1 << (9 * (amd_iommu_max_glx_val + 1));
3765 max_pasids = min(max_pasids, (1 << 20));
3766
3767 info->flags |= AMD_IOMMU_DEVICE_FLAG_PASID_SUP;
3768 info->max_pasids = min(pci_max_pasids(pdev), max_pasids);
3769
3770 features = pci_pasid_features(pdev);
3771 if (features & PCI_PASID_CAP_EXEC)
3772 info->flags |= AMD_IOMMU_DEVICE_FLAG_EXEC_SUP;
3773 if (features & PCI_PASID_CAP_PRIV)
3774 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRIV_SUP;
3775 }
3776
3777 return 0;
3778}
3779EXPORT_SYMBOL(amd_iommu_device_info);
Joerg Roedel2b324502012-06-21 16:29:10 +02003780
3781#ifdef CONFIG_IRQ_REMAP
3782
3783/*****************************************************************************
3784 *
3785 * Interrupt Remapping Implementation
3786 *
3787 *****************************************************************************/
3788
3789union irte {
3790 u32 val;
3791 struct {
3792 u32 valid : 1,
3793 no_fault : 1,
3794 int_type : 3,
3795 rq_eoi : 1,
3796 dm : 1,
3797 rsvd_1 : 1,
3798 destination : 8,
3799 vector : 8,
3800 rsvd_2 : 8;
3801 } fields;
3802};
3803
Jiang Liu9c724962015-04-14 10:29:52 +08003804struct irq_2_irte {
3805 u16 devid; /* Device ID for IRTE table */
3806 u16 index; /* Index into IRTE table*/
3807};
3808
Jiang Liu7c71d302015-04-13 14:11:33 +08003809struct amd_ir_data {
3810 struct irq_2_irte irq_2_irte;
3811 union irte irte_entry;
3812 union {
3813 struct msi_msg msi_entry;
3814 };
3815};
3816
3817static struct irq_chip amd_ir_chip;
3818
Joerg Roedel2b324502012-06-21 16:29:10 +02003819#define DTE_IRQ_PHYS_ADDR_MASK (((1ULL << 45)-1) << 6)
3820#define DTE_IRQ_REMAP_INTCTL (2ULL << 60)
3821#define DTE_IRQ_TABLE_LEN (8ULL << 1)
3822#define DTE_IRQ_REMAP_ENABLE 1ULL
3823
3824static void set_dte_irq_entry(u16 devid, struct irq_remap_table *table)
3825{
3826 u64 dte;
3827
3828 dte = amd_iommu_dev_table[devid].data[2];
3829 dte &= ~DTE_IRQ_PHYS_ADDR_MASK;
3830 dte |= virt_to_phys(table->table);
3831 dte |= DTE_IRQ_REMAP_INTCTL;
3832 dte |= DTE_IRQ_TABLE_LEN;
3833 dte |= DTE_IRQ_REMAP_ENABLE;
3834
3835 amd_iommu_dev_table[devid].data[2] = dte;
3836}
3837
3838#define IRTE_ALLOCATED (~1U)
3839
3840static struct irq_remap_table *get_irq_table(u16 devid, bool ioapic)
3841{
3842 struct irq_remap_table *table = NULL;
3843 struct amd_iommu *iommu;
3844 unsigned long flags;
3845 u16 alias;
3846
3847 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
3848
3849 iommu = amd_iommu_rlookup_table[devid];
3850 if (!iommu)
3851 goto out_unlock;
3852
3853 table = irq_lookup_table[devid];
3854 if (table)
3855 goto out;
3856
3857 alias = amd_iommu_alias_table[devid];
3858 table = irq_lookup_table[alias];
3859 if (table) {
3860 irq_lookup_table[devid] = table;
3861 set_dte_irq_entry(devid, table);
3862 iommu_flush_dte(iommu, devid);
3863 goto out;
3864 }
3865
3866 /* Nothing there yet, allocate new irq remapping table */
3867 table = kzalloc(sizeof(*table), GFP_ATOMIC);
3868 if (!table)
3869 goto out;
3870
Joerg Roedel197887f2013-04-09 21:14:08 +02003871 /* Initialize table spin-lock */
3872 spin_lock_init(&table->lock);
3873
Joerg Roedel2b324502012-06-21 16:29:10 +02003874 if (ioapic)
3875 /* Keep the first 32 indexes free for IOAPIC interrupts */
3876 table->min_index = 32;
3877
3878 table->table = kmem_cache_alloc(amd_iommu_irq_cache, GFP_ATOMIC);
3879 if (!table->table) {
3880 kfree(table);
Dan Carpenter821f0f62012-10-02 11:34:40 +03003881 table = NULL;
Joerg Roedel2b324502012-06-21 16:29:10 +02003882 goto out;
3883 }
3884
3885 memset(table->table, 0, MAX_IRQS_PER_TABLE * sizeof(u32));
3886
3887 if (ioapic) {
3888 int i;
3889
3890 for (i = 0; i < 32; ++i)
3891 table->table[i] = IRTE_ALLOCATED;
3892 }
3893
3894 irq_lookup_table[devid] = table;
3895 set_dte_irq_entry(devid, table);
3896 iommu_flush_dte(iommu, devid);
3897 if (devid != alias) {
3898 irq_lookup_table[alias] = table;
Alex Williamsone028a9e2014-04-22 10:08:40 -06003899 set_dte_irq_entry(alias, table);
Joerg Roedel2b324502012-06-21 16:29:10 +02003900 iommu_flush_dte(iommu, alias);
3901 }
3902
3903out:
3904 iommu_completion_wait(iommu);
3905
3906out_unlock:
3907 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
3908
3909 return table;
3910}
3911
Jiang Liu3c3d4f92015-04-13 14:11:38 +08003912static int alloc_irq_index(u16 devid, int count)
Joerg Roedel2b324502012-06-21 16:29:10 +02003913{
3914 struct irq_remap_table *table;
3915 unsigned long flags;
3916 int index, c;
3917
3918 table = get_irq_table(devid, false);
3919 if (!table)
3920 return -ENODEV;
3921
3922 spin_lock_irqsave(&table->lock, flags);
3923
3924 /* Scan table for free entries */
3925 for (c = 0, index = table->min_index;
3926 index < MAX_IRQS_PER_TABLE;
3927 ++index) {
3928 if (table->table[index] == 0)
3929 c += 1;
3930 else
3931 c = 0;
3932
3933 if (c == count) {
Joerg Roedel2b324502012-06-21 16:29:10 +02003934 for (; c != 0; --c)
3935 table->table[index - c + 1] = IRTE_ALLOCATED;
3936
3937 index -= count - 1;
Joerg Roedel2b324502012-06-21 16:29:10 +02003938 goto out;
3939 }
3940 }
3941
3942 index = -ENOSPC;
3943
3944out:
3945 spin_unlock_irqrestore(&table->lock, flags);
3946
3947 return index;
3948}
3949
Joerg Roedel2b324502012-06-21 16:29:10 +02003950static int modify_irte(u16 devid, int index, union irte irte)
3951{
3952 struct irq_remap_table *table;
3953 struct amd_iommu *iommu;
3954 unsigned long flags;
3955
3956 iommu = amd_iommu_rlookup_table[devid];
3957 if (iommu == NULL)
3958 return -EINVAL;
3959
3960 table = get_irq_table(devid, false);
3961 if (!table)
3962 return -ENOMEM;
3963
3964 spin_lock_irqsave(&table->lock, flags);
3965 table->table[index] = irte.val;
3966 spin_unlock_irqrestore(&table->lock, flags);
3967
3968 iommu_flush_irt(iommu, devid);
3969 iommu_completion_wait(iommu);
3970
3971 return 0;
3972}
3973
3974static void free_irte(u16 devid, int index)
3975{
3976 struct irq_remap_table *table;
3977 struct amd_iommu *iommu;
3978 unsigned long flags;
3979
3980 iommu = amd_iommu_rlookup_table[devid];
3981 if (iommu == NULL)
3982 return;
3983
3984 table = get_irq_table(devid, false);
3985 if (!table)
3986 return;
3987
3988 spin_lock_irqsave(&table->lock, flags);
3989 table->table[index] = 0;
3990 spin_unlock_irqrestore(&table->lock, flags);
3991
3992 iommu_flush_irt(iommu, devid);
3993 iommu_completion_wait(iommu);
3994}
3995
Jiang Liu7c71d302015-04-13 14:11:33 +08003996static int get_devid(struct irq_alloc_info *info)
Joerg Roedel5527de72012-06-26 11:17:32 +02003997{
Jiang Liu7c71d302015-04-13 14:11:33 +08003998 int devid = -1;
Joerg Roedel5527de72012-06-26 11:17:32 +02003999
Jiang Liu7c71d302015-04-13 14:11:33 +08004000 switch (info->type) {
4001 case X86_IRQ_ALLOC_TYPE_IOAPIC:
4002 devid = get_ioapic_devid(info->ioapic_id);
4003 break;
4004 case X86_IRQ_ALLOC_TYPE_HPET:
4005 devid = get_hpet_devid(info->hpet_id);
4006 break;
4007 case X86_IRQ_ALLOC_TYPE_MSI:
4008 case X86_IRQ_ALLOC_TYPE_MSIX:
4009 devid = get_device_id(&info->msi_dev->dev);
4010 break;
4011 default:
4012 BUG_ON(1);
4013 break;
Joerg Roedel5527de72012-06-26 11:17:32 +02004014 }
4015
Jiang Liu7c71d302015-04-13 14:11:33 +08004016 return devid;
Joerg Roedel5527de72012-06-26 11:17:32 +02004017}
4018
Jiang Liu7c71d302015-04-13 14:11:33 +08004019static struct irq_domain *get_ir_irq_domain(struct irq_alloc_info *info)
Joerg Roedel5527de72012-06-26 11:17:32 +02004020{
Jiang Liu7c71d302015-04-13 14:11:33 +08004021 struct amd_iommu *iommu;
4022 int devid;
Joerg Roedel5527de72012-06-26 11:17:32 +02004023
Jiang Liu7c71d302015-04-13 14:11:33 +08004024 if (!info)
4025 return NULL;
Joerg Roedel5527de72012-06-26 11:17:32 +02004026
Jiang Liu7c71d302015-04-13 14:11:33 +08004027 devid = get_devid(info);
4028 if (devid >= 0) {
4029 iommu = amd_iommu_rlookup_table[devid];
4030 if (iommu)
4031 return iommu->ir_domain;
4032 }
Joerg Roedel5527de72012-06-26 11:17:32 +02004033
Jiang Liu7c71d302015-04-13 14:11:33 +08004034 return NULL;
Joerg Roedel5527de72012-06-26 11:17:32 +02004035}
4036
Jiang Liu7c71d302015-04-13 14:11:33 +08004037static struct irq_domain *get_irq_domain(struct irq_alloc_info *info)
Joerg Roedel0b4d48c2012-06-26 14:54:17 +02004038{
Jiang Liu7c71d302015-04-13 14:11:33 +08004039 struct amd_iommu *iommu;
4040 int devid;
Joerg Roedel0b4d48c2012-06-26 14:54:17 +02004041
Jiang Liu7c71d302015-04-13 14:11:33 +08004042 if (!info)
4043 return NULL;
Joerg Roedel0b4d48c2012-06-26 14:54:17 +02004044
Jiang Liu7c71d302015-04-13 14:11:33 +08004045 switch (info->type) {
4046 case X86_IRQ_ALLOC_TYPE_MSI:
4047 case X86_IRQ_ALLOC_TYPE_MSIX:
4048 devid = get_device_id(&info->msi_dev->dev);
Joerg Roedel9ee35e42016-04-21 18:21:31 +02004049 if (devid < 0)
Wan Zongshun7aba6cb2016-04-01 09:06:02 -04004050 return NULL;
4051
Dan Carpenter1fb260b2016-01-07 12:36:06 +03004052 iommu = amd_iommu_rlookup_table[devid];
4053 if (iommu)
4054 return iommu->msi_domain;
Jiang Liu7c71d302015-04-13 14:11:33 +08004055 break;
4056 default:
4057 break;
4058 }
Joerg Roedel0b4d48c2012-06-26 14:54:17 +02004059
Jiang Liu7c71d302015-04-13 14:11:33 +08004060 return NULL;
Joerg Roedeld9761952012-06-26 16:00:08 +02004061}
4062
Joerg Roedel6b474b82012-06-26 16:46:04 +02004063struct irq_remap_ops amd_iommu_irq_ops = {
Joerg Roedel6b474b82012-06-26 16:46:04 +02004064 .prepare = amd_iommu_prepare,
4065 .enable = amd_iommu_enable,
4066 .disable = amd_iommu_disable,
4067 .reenable = amd_iommu_reenable,
4068 .enable_faulting = amd_iommu_enable_faulting,
Jiang Liu7c71d302015-04-13 14:11:33 +08004069 .get_ir_irq_domain = get_ir_irq_domain,
4070 .get_irq_domain = get_irq_domain,
Joerg Roedel6b474b82012-06-26 16:46:04 +02004071};
Jiang Liu7c71d302015-04-13 14:11:33 +08004072
4073static void irq_remapping_prepare_irte(struct amd_ir_data *data,
4074 struct irq_cfg *irq_cfg,
4075 struct irq_alloc_info *info,
4076 int devid, int index, int sub_handle)
4077{
4078 struct irq_2_irte *irte_info = &data->irq_2_irte;
4079 struct msi_msg *msg = &data->msi_entry;
4080 union irte *irte = &data->irte_entry;
4081 struct IO_APIC_route_entry *entry;
4082
Jiang Liu7c71d302015-04-13 14:11:33 +08004083 data->irq_2_irte.devid = devid;
4084 data->irq_2_irte.index = index + sub_handle;
4085
4086 /* Setup IRTE for IOMMU */
4087 irte->val = 0;
4088 irte->fields.vector = irq_cfg->vector;
4089 irte->fields.int_type = apic->irq_delivery_mode;
4090 irte->fields.destination = irq_cfg->dest_apicid;
4091 irte->fields.dm = apic->irq_dest_mode;
4092 irte->fields.valid = 1;
4093
4094 switch (info->type) {
4095 case X86_IRQ_ALLOC_TYPE_IOAPIC:
4096 /* Setup IOAPIC entry */
4097 entry = info->ioapic_entry;
4098 info->ioapic_entry = NULL;
4099 memset(entry, 0, sizeof(*entry));
4100 entry->vector = index;
4101 entry->mask = 0;
4102 entry->trigger = info->ioapic_trigger;
4103 entry->polarity = info->ioapic_polarity;
4104 /* Mask level triggered irqs. */
4105 if (info->ioapic_trigger)
4106 entry->mask = 1;
4107 break;
4108
4109 case X86_IRQ_ALLOC_TYPE_HPET:
4110 case X86_IRQ_ALLOC_TYPE_MSI:
4111 case X86_IRQ_ALLOC_TYPE_MSIX:
4112 msg->address_hi = MSI_ADDR_BASE_HI;
4113 msg->address_lo = MSI_ADDR_BASE_LO;
4114 msg->data = irte_info->index;
4115 break;
4116
4117 default:
4118 BUG_ON(1);
4119 break;
4120 }
4121}
4122
4123static int irq_remapping_alloc(struct irq_domain *domain, unsigned int virq,
4124 unsigned int nr_irqs, void *arg)
4125{
4126 struct irq_alloc_info *info = arg;
4127 struct irq_data *irq_data;
4128 struct amd_ir_data *data;
4129 struct irq_cfg *cfg;
4130 int i, ret, devid;
4131 int index = -1;
4132
4133 if (!info)
4134 return -EINVAL;
4135 if (nr_irqs > 1 && info->type != X86_IRQ_ALLOC_TYPE_MSI &&
4136 info->type != X86_IRQ_ALLOC_TYPE_MSIX)
4137 return -EINVAL;
4138
4139 /*
4140 * With IRQ remapping enabled, don't need contiguous CPU vectors
4141 * to support multiple MSI interrupts.
4142 */
4143 if (info->type == X86_IRQ_ALLOC_TYPE_MSI)
4144 info->flags &= ~X86_IRQ_ALLOC_CONTIGUOUS_VECTORS;
4145
4146 devid = get_devid(info);
4147 if (devid < 0)
4148 return -EINVAL;
4149
4150 ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg);
4151 if (ret < 0)
4152 return ret;
4153
Jiang Liu7c71d302015-04-13 14:11:33 +08004154 if (info->type == X86_IRQ_ALLOC_TYPE_IOAPIC) {
4155 if (get_irq_table(devid, true))
4156 index = info->ioapic_pin;
4157 else
4158 ret = -ENOMEM;
4159 } else {
Jiang Liu3c3d4f92015-04-13 14:11:38 +08004160 index = alloc_irq_index(devid, nr_irqs);
Jiang Liu7c71d302015-04-13 14:11:33 +08004161 }
4162 if (index < 0) {
4163 pr_warn("Failed to allocate IRTE\n");
Jiang Liu7c71d302015-04-13 14:11:33 +08004164 goto out_free_parent;
4165 }
4166
4167 for (i = 0; i < nr_irqs; i++) {
4168 irq_data = irq_domain_get_irq_data(domain, virq + i);
4169 cfg = irqd_cfg(irq_data);
4170 if (!irq_data || !cfg) {
4171 ret = -EINVAL;
4172 goto out_free_data;
4173 }
4174
Joerg Roedela130e692015-08-13 11:07:25 +02004175 ret = -ENOMEM;
4176 data = kzalloc(sizeof(*data), GFP_KERNEL);
4177 if (!data)
4178 goto out_free_data;
4179
Jiang Liu7c71d302015-04-13 14:11:33 +08004180 irq_data->hwirq = (devid << 16) + i;
4181 irq_data->chip_data = data;
4182 irq_data->chip = &amd_ir_chip;
4183 irq_remapping_prepare_irte(data, cfg, info, devid, index, i);
4184 irq_set_status_flags(virq + i, IRQ_MOVE_PCNTXT);
4185 }
Joerg Roedela130e692015-08-13 11:07:25 +02004186
Jiang Liu7c71d302015-04-13 14:11:33 +08004187 return 0;
4188
4189out_free_data:
4190 for (i--; i >= 0; i--) {
4191 irq_data = irq_domain_get_irq_data(domain, virq + i);
4192 if (irq_data)
4193 kfree(irq_data->chip_data);
4194 }
4195 for (i = 0; i < nr_irqs; i++)
4196 free_irte(devid, index + i);
4197out_free_parent:
4198 irq_domain_free_irqs_common(domain, virq, nr_irqs);
4199 return ret;
4200}
4201
4202static void irq_remapping_free(struct irq_domain *domain, unsigned int virq,
4203 unsigned int nr_irqs)
4204{
4205 struct irq_2_irte *irte_info;
4206 struct irq_data *irq_data;
4207 struct amd_ir_data *data;
4208 int i;
4209
4210 for (i = 0; i < nr_irqs; i++) {
4211 irq_data = irq_domain_get_irq_data(domain, virq + i);
4212 if (irq_data && irq_data->chip_data) {
4213 data = irq_data->chip_data;
4214 irte_info = &data->irq_2_irte;
4215 free_irte(irte_info->devid, irte_info->index);
4216 kfree(data);
4217 }
4218 }
4219 irq_domain_free_irqs_common(domain, virq, nr_irqs);
4220}
4221
4222static void irq_remapping_activate(struct irq_domain *domain,
4223 struct irq_data *irq_data)
4224{
4225 struct amd_ir_data *data = irq_data->chip_data;
4226 struct irq_2_irte *irte_info = &data->irq_2_irte;
4227
4228 modify_irte(irte_info->devid, irte_info->index, data->irte_entry);
4229}
4230
4231static void irq_remapping_deactivate(struct irq_domain *domain,
4232 struct irq_data *irq_data)
4233{
4234 struct amd_ir_data *data = irq_data->chip_data;
4235 struct irq_2_irte *irte_info = &data->irq_2_irte;
4236 union irte entry;
4237
4238 entry.val = 0;
4239 modify_irte(irte_info->devid, irte_info->index, data->irte_entry);
4240}
4241
4242static struct irq_domain_ops amd_ir_domain_ops = {
4243 .alloc = irq_remapping_alloc,
4244 .free = irq_remapping_free,
4245 .activate = irq_remapping_activate,
4246 .deactivate = irq_remapping_deactivate,
4247};
4248
4249static int amd_ir_set_affinity(struct irq_data *data,
4250 const struct cpumask *mask, bool force)
4251{
4252 struct amd_ir_data *ir_data = data->chip_data;
4253 struct irq_2_irte *irte_info = &ir_data->irq_2_irte;
4254 struct irq_cfg *cfg = irqd_cfg(data);
4255 struct irq_data *parent = data->parent_data;
4256 int ret;
4257
4258 ret = parent->chip->irq_set_affinity(parent, mask, force);
4259 if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE)
4260 return ret;
4261
4262 /*
4263 * Atomically updates the IRTE with the new destination, vector
4264 * and flushes the interrupt entry cache.
4265 */
4266 ir_data->irte_entry.fields.vector = cfg->vector;
4267 ir_data->irte_entry.fields.destination = cfg->dest_apicid;
4268 modify_irte(irte_info->devid, irte_info->index, ir_data->irte_entry);
4269
4270 /*
4271 * After this point, all the interrupts will start arriving
4272 * at the new destination. So, time to cleanup the previous
4273 * vector allocation.
4274 */
Jiang Liuc6c20022015-04-14 10:30:02 +08004275 send_cleanup_vector(cfg);
Jiang Liu7c71d302015-04-13 14:11:33 +08004276
4277 return IRQ_SET_MASK_OK_DONE;
4278}
4279
4280static void ir_compose_msi_msg(struct irq_data *irq_data, struct msi_msg *msg)
4281{
4282 struct amd_ir_data *ir_data = irq_data->chip_data;
4283
4284 *msg = ir_data->msi_entry;
4285}
4286
4287static struct irq_chip amd_ir_chip = {
4288 .irq_ack = ir_ack_apic_edge,
4289 .irq_set_affinity = amd_ir_set_affinity,
4290 .irq_compose_msi_msg = ir_compose_msi_msg,
4291};
4292
4293int amd_iommu_create_irq_domain(struct amd_iommu *iommu)
4294{
4295 iommu->ir_domain = irq_domain_add_tree(NULL, &amd_ir_domain_ops, iommu);
4296 if (!iommu->ir_domain)
4297 return -ENOMEM;
4298
4299 iommu->ir_domain->parent = arch_get_ir_parent_domain();
4300 iommu->msi_domain = arch_create_msi_irq_domain(iommu->ir_domain);
4301
4302 return 0;
4303}
Joerg Roedel2b324502012-06-21 16:29:10 +02004304#endif