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Changhwan Younc8bef142010-07-27 17:52:39 +09001/* linux/arch/arm/mach-s5pv310/include/mach/regs-clock.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5PV310 - Clock register definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_REGS_CLOCK_H
14#define __ASM_ARCH_REGS_CLOCK_H __FILE__
15
16#include <mach/map.h>
17
Kukjin Kimc598c472010-08-18 21:45:49 +090018#define S5P_CLKREG(x) (S5P_VA_CMU + (x))
Changhwan Younc8bef142010-07-27 17:52:39 +090019
20#define S5P_INFORM0 S5P_CLKREG(0x800)
21
Kukjin Kimc598c472010-08-18 21:45:49 +090022#define S5P_EPLL_CON0 S5P_CLKREG(0x0C110)
23#define S5P_EPLL_CON1 S5P_CLKREG(0x0C114)
24#define S5P_VPLL_CON0 S5P_CLKREG(0x0C120)
25#define S5P_VPLL_CON1 S5P_CLKREG(0x0C124)
Changhwan Younc8bef142010-07-27 17:52:39 +090026
Kukjin Kimc598c472010-08-18 21:45:49 +090027#define S5P_CLKSRC_TOP0 S5P_CLKREG(0x0C210)
28#define S5P_CLKSRC_TOP1 S5P_CLKREG(0x0C214)
Kukjin Kime33ed872010-08-18 21:59:01 +090029#define S5P_CLKSRC_CAM S5P_CLKREG(0x0C220)
30#define S5P_CLKSRC_IMAGE S5P_CLKREG(0x0C230)
31#define S5P_CLKSRC_LCD0 S5P_CLKREG(0x0C234)
32#define S5P_CLKSRC_LCD1 S5P_CLKREG(0x0C238)
33#define S5P_CLKSRC_FSYS S5P_CLKREG(0x0C240)
Kukjin Kimc598c472010-08-18 21:45:49 +090034#define S5P_CLKSRC_PERIL0 S5P_CLKREG(0x0C250)
Kukjin Kime33ed872010-08-18 21:59:01 +090035#define S5P_CLKSRC_PERIL1 S5P_CLKREG(0x0C254)
Changhwan Younc8bef142010-07-27 17:52:39 +090036
Kukjin Kimc598c472010-08-18 21:45:49 +090037#define S5P_CLKDIV_TOP S5P_CLKREG(0x0C510)
Kukjin Kime33ed872010-08-18 21:59:01 +090038#define S5P_CLKDIV_CAM S5P_CLKREG(0x0C520)
39#define S5P_CLKDIV_IMAGE S5P_CLKREG(0x0C530)
40#define S5P_CLKDIV_LCD0 S5P_CLKREG(0x0C534)
41#define S5P_CLKDIV_LCD1 S5P_CLKREG(0x0C538)
42#define S5P_CLKDIV_FSYS0 S5P_CLKREG(0x0C540)
43#define S5P_CLKDIV_FSYS1 S5P_CLKREG(0x0C544)
44#define S5P_CLKDIV_FSYS2 S5P_CLKREG(0x0C548)
45#define S5P_CLKDIV_FSYS3 S5P_CLKREG(0x0C54C)
Kukjin Kimc598c472010-08-18 21:45:49 +090046#define S5P_CLKDIV_PERIL0 S5P_CLKREG(0x0C550)
47#define S5P_CLKDIV_PERIL1 S5P_CLKREG(0x0C554)
48#define S5P_CLKDIV_PERIL2 S5P_CLKREG(0x0C558)
49#define S5P_CLKDIV_PERIL3 S5P_CLKREG(0x0C55C)
50#define S5P_CLKDIV_PERIL4 S5P_CLKREG(0x0C560)
51#define S5P_CLKDIV_PERIL5 S5P_CLKREG(0x0C564)
Changhwan Younc8bef142010-07-27 17:52:39 +090052
Kukjin Kime33ed872010-08-18 21:59:01 +090053#define S5P_CLKSRC_MASK_TOP S5P_CLKREG(0x0C310)
54#define S5P_CLKSRC_MASK_CAM S5P_CLKREG(0x0C320)
55#define S5P_CLKSRC_MASK_LCD0 S5P_CLKREG(0x0C334)
56#define S5P_CLKSRC_MASK_LCD1 S5P_CLKREG(0x0C338)
57#define S5P_CLKSRC_MASK_FSYS S5P_CLKREG(0x0C340)
Jongpill Lee3297c2e2010-08-27 17:53:26 +090058#define S5P_CLKSRC_MASK_PERIL0 S5P_CLKREG(0x0C350)
Kukjin Kime33ed872010-08-18 21:59:01 +090059#define S5P_CLKSRC_MASK_PERIL1 S5P_CLKREG(0x0C354)
Jongpill Lee3297c2e2010-08-27 17:53:26 +090060
Kukjin Kime33ed872010-08-18 21:59:01 +090061#define S5P_CLKGATE_IP_CAM S5P_CLKREG(0x0C920)
62#define S5P_CLKGATE_IP_IMAGE S5P_CLKREG(0x0C930)
63#define S5P_CLKGATE_IP_LCD0 S5P_CLKREG(0x0C934)
64#define S5P_CLKGATE_IP_LCD1 S5P_CLKREG(0x0C938)
65#define S5P_CLKGATE_IP_FSYS S5P_CLKREG(0x0C940)
Kukjin Kimc598c472010-08-18 21:45:49 +090066#define S5P_CLKGATE_IP_PERIL S5P_CLKREG(0x0C950)
Jongpill Lee82260bf2010-08-18 22:49:24 +090067#define S5P_CLKGATE_IP_PERIR S5P_CLKREG(0x0C960)
Changhwan Younc8bef142010-07-27 17:52:39 +090068
Kukjin Kimc598c472010-08-18 21:45:49 +090069#define S5P_CLKSRC_CORE S5P_CLKREG(0x10200)
70#define S5P_CLKDIV_CORE0 S5P_CLKREG(0x10500)
Changhwan Younc8bef142010-07-27 17:52:39 +090071
Kukjin Kimc598c472010-08-18 21:45:49 +090072#define S5P_APLL_LOCK S5P_CLKREG(0x14000)
73#define S5P_MPLL_LOCK S5P_CLKREG(0x14004)
74#define S5P_APLL_CON0 S5P_CLKREG(0x14100)
75#define S5P_APLL_CON1 S5P_CLKREG(0x14104)
76#define S5P_MPLL_CON0 S5P_CLKREG(0x14108)
77#define S5P_MPLL_CON1 S5P_CLKREG(0x1410C)
Changhwan Younc8bef142010-07-27 17:52:39 +090078
Kukjin Kimc598c472010-08-18 21:45:49 +090079#define S5P_CLKSRC_CPU S5P_CLKREG(0x14200)
80#define S5P_CLKMUX_STATCPU S5P_CLKREG(0x14400)
Changhwan Younc8bef142010-07-27 17:52:39 +090081
Kukjin Kimc598c472010-08-18 21:45:49 +090082#define S5P_CLKDIV_CPU S5P_CLKREG(0x14500)
83#define S5P_CLKDIV_STATCPU S5P_CLKREG(0x14600)
Changhwan Younc8bef142010-07-27 17:52:39 +090084
Kukjin Kimc598c472010-08-18 21:45:49 +090085#define S5P_CLKGATE_SCLKCPU S5P_CLKREG(0x14800)
Changhwan Younc8bef142010-07-27 17:52:39 +090086
87#endif /* __ASM_ARCH_REGS_CLOCK_H */