blob: 2ef0e7d02991665fc81b77a2664dcbc2a0cf8dcd [file] [log] [blame]
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09001/*
2 *Copyright (C) 2010 OKI SEMICONDUCTOR CO., LTD.
3 *
4 *This program is free software; you can redistribute it and/or modify
5 *it under the terms of the GNU General Public License as published by
6 *the Free Software Foundation; version 2 of the License.
7 *
8 *This program is distributed in the hope that it will be useful,
9 *but WITHOUT ANY WARRANTY; without even the implied warranty of
10 *MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 *GNU General Public License for more details.
12 *
13 *You should have received a copy of the GNU General Public License
14 *along with this program; if not, write to the Free Software
15 *Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
16 */
Uwe Kleine-König0e2adc02011-05-26 10:41:17 +020017#include <linux/kernel.h>
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +090018#include <linux/serial_reg.h>
Andrew Morton023bc8e2011-05-24 17:13:44 -070019#include <linux/slab.h>
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +090020#include <linux/module.h>
21#include <linux/pci.h>
22#include <linux/serial_core.h>
Jiri Slabyee160a32011-09-01 16:20:57 +020023#include <linux/tty.h>
24#include <linux/tty_flip.h>
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +090025#include <linux/interrupt.h>
26#include <linux/io.h>
Denis Turischev6ae705b2011-03-10 15:14:00 +020027#include <linux/dmi.h>
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +090028
29#include <linux/dmaengine.h>
30#include <linux/pch_dma.h>
31
32enum {
33 PCH_UART_HANDLED_RX_INT_SHIFT,
34 PCH_UART_HANDLED_TX_INT_SHIFT,
35 PCH_UART_HANDLED_RX_ERR_INT_SHIFT,
36 PCH_UART_HANDLED_RX_TRG_INT_SHIFT,
37 PCH_UART_HANDLED_MS_INT_SHIFT,
38};
39
40enum {
41 PCH_UART_8LINE,
42 PCH_UART_2LINE,
43};
44
45#define PCH_UART_DRIVER_DEVICE "ttyPCH"
46
Tomoya MORINAGA4564e1e2011-01-28 18:00:01 +090047/* Set the max number of UART port
48 * Intel EG20T PCH: 4 port
49 * OKI SEMICONDUCTOR ML7213 IOH: 3 port
Alexander Steinbff52fd2011-07-04 15:35:51 +020050 * OKI SEMICONDUCTOR ML7223 IOH: 2 port
Tomoya MORINAGA4564e1e2011-01-28 18:00:01 +090051*/
52#define PCH_UART_NR 4
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +090053
54#define PCH_UART_HANDLED_RX_INT (1<<((PCH_UART_HANDLED_RX_INT_SHIFT)<<1))
55#define PCH_UART_HANDLED_TX_INT (1<<((PCH_UART_HANDLED_TX_INT_SHIFT)<<1))
56#define PCH_UART_HANDLED_RX_ERR_INT (1<<((\
57 PCH_UART_HANDLED_RX_ERR_INT_SHIFT)<<1))
58#define PCH_UART_HANDLED_RX_TRG_INT (1<<((\
59 PCH_UART_HANDLED_RX_TRG_INT_SHIFT)<<1))
60#define PCH_UART_HANDLED_MS_INT (1<<((PCH_UART_HANDLED_MS_INT_SHIFT)<<1))
61
62#define PCH_UART_RBR 0x00
63#define PCH_UART_THR 0x00
64
65#define PCH_UART_IER_MASK (PCH_UART_IER_ERBFI|PCH_UART_IER_ETBEI|\
66 PCH_UART_IER_ELSI|PCH_UART_IER_EDSSI)
67#define PCH_UART_IER_ERBFI 0x00000001
68#define PCH_UART_IER_ETBEI 0x00000002
69#define PCH_UART_IER_ELSI 0x00000004
70#define PCH_UART_IER_EDSSI 0x00000008
71
72#define PCH_UART_IIR_IP 0x00000001
73#define PCH_UART_IIR_IID 0x00000006
74#define PCH_UART_IIR_MSI 0x00000000
75#define PCH_UART_IIR_TRI 0x00000002
76#define PCH_UART_IIR_RRI 0x00000004
77#define PCH_UART_IIR_REI 0x00000006
78#define PCH_UART_IIR_TOI 0x00000008
79#define PCH_UART_IIR_FIFO256 0x00000020
80#define PCH_UART_IIR_FIFO64 PCH_UART_IIR_FIFO256
81#define PCH_UART_IIR_FE 0x000000C0
82
83#define PCH_UART_FCR_FIFOE 0x00000001
84#define PCH_UART_FCR_RFR 0x00000002
85#define PCH_UART_FCR_TFR 0x00000004
86#define PCH_UART_FCR_DMS 0x00000008
87#define PCH_UART_FCR_FIFO256 0x00000020
88#define PCH_UART_FCR_RFTL 0x000000C0
89
90#define PCH_UART_FCR_RFTL1 0x00000000
91#define PCH_UART_FCR_RFTL64 0x00000040
92#define PCH_UART_FCR_RFTL128 0x00000080
93#define PCH_UART_FCR_RFTL224 0x000000C0
94#define PCH_UART_FCR_RFTL16 PCH_UART_FCR_RFTL64
95#define PCH_UART_FCR_RFTL32 PCH_UART_FCR_RFTL128
96#define PCH_UART_FCR_RFTL56 PCH_UART_FCR_RFTL224
97#define PCH_UART_FCR_RFTL4 PCH_UART_FCR_RFTL64
98#define PCH_UART_FCR_RFTL8 PCH_UART_FCR_RFTL128
99#define PCH_UART_FCR_RFTL14 PCH_UART_FCR_RFTL224
100#define PCH_UART_FCR_RFTL_SHIFT 6
101
102#define PCH_UART_LCR_WLS 0x00000003
103#define PCH_UART_LCR_STB 0x00000004
104#define PCH_UART_LCR_PEN 0x00000008
105#define PCH_UART_LCR_EPS 0x00000010
106#define PCH_UART_LCR_SP 0x00000020
107#define PCH_UART_LCR_SB 0x00000040
108#define PCH_UART_LCR_DLAB 0x00000080
109#define PCH_UART_LCR_NP 0x00000000
110#define PCH_UART_LCR_OP PCH_UART_LCR_PEN
111#define PCH_UART_LCR_EP (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS)
112#define PCH_UART_LCR_1P (PCH_UART_LCR_PEN | PCH_UART_LCR_SP)
113#define PCH_UART_LCR_0P (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS |\
114 PCH_UART_LCR_SP)
115
116#define PCH_UART_LCR_5BIT 0x00000000
117#define PCH_UART_LCR_6BIT 0x00000001
118#define PCH_UART_LCR_7BIT 0x00000002
119#define PCH_UART_LCR_8BIT 0x00000003
120
121#define PCH_UART_MCR_DTR 0x00000001
122#define PCH_UART_MCR_RTS 0x00000002
123#define PCH_UART_MCR_OUT 0x0000000C
124#define PCH_UART_MCR_LOOP 0x00000010
125#define PCH_UART_MCR_AFE 0x00000020
126
127#define PCH_UART_LSR_DR 0x00000001
128#define PCH_UART_LSR_ERR (1<<7)
129
130#define PCH_UART_MSR_DCTS 0x00000001
131#define PCH_UART_MSR_DDSR 0x00000002
132#define PCH_UART_MSR_TERI 0x00000004
133#define PCH_UART_MSR_DDCD 0x00000008
134#define PCH_UART_MSR_CTS 0x00000010
135#define PCH_UART_MSR_DSR 0x00000020
136#define PCH_UART_MSR_RI 0x00000040
137#define PCH_UART_MSR_DCD 0x00000080
138#define PCH_UART_MSR_DELTA (PCH_UART_MSR_DCTS | PCH_UART_MSR_DDSR |\
139 PCH_UART_MSR_TERI | PCH_UART_MSR_DDCD)
140
141#define PCH_UART_DLL 0x00
142#define PCH_UART_DLM 0x01
143
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900144#define PCH_UART_IID_RLS (PCH_UART_IIR_REI)
145#define PCH_UART_IID_RDR (PCH_UART_IIR_RRI)
146#define PCH_UART_IID_RDR_TO (PCH_UART_IIR_RRI | PCH_UART_IIR_TOI)
147#define PCH_UART_IID_THRE (PCH_UART_IIR_TRI)
148#define PCH_UART_IID_MS (PCH_UART_IIR_MSI)
149
150#define PCH_UART_HAL_PARITY_NONE (PCH_UART_LCR_NP)
151#define PCH_UART_HAL_PARITY_ODD (PCH_UART_LCR_OP)
152#define PCH_UART_HAL_PARITY_EVEN (PCH_UART_LCR_EP)
153#define PCH_UART_HAL_PARITY_FIX1 (PCH_UART_LCR_1P)
154#define PCH_UART_HAL_PARITY_FIX0 (PCH_UART_LCR_0P)
155#define PCH_UART_HAL_5BIT (PCH_UART_LCR_5BIT)
156#define PCH_UART_HAL_6BIT (PCH_UART_LCR_6BIT)
157#define PCH_UART_HAL_7BIT (PCH_UART_LCR_7BIT)
158#define PCH_UART_HAL_8BIT (PCH_UART_LCR_8BIT)
159#define PCH_UART_HAL_STB1 0
160#define PCH_UART_HAL_STB2 (PCH_UART_LCR_STB)
161
162#define PCH_UART_HAL_CLR_TX_FIFO (PCH_UART_FCR_TFR)
163#define PCH_UART_HAL_CLR_RX_FIFO (PCH_UART_FCR_RFR)
164#define PCH_UART_HAL_CLR_ALL_FIFO (PCH_UART_HAL_CLR_TX_FIFO | \
165 PCH_UART_HAL_CLR_RX_FIFO)
166
167#define PCH_UART_HAL_DMA_MODE0 0
168#define PCH_UART_HAL_FIFO_DIS 0
169#define PCH_UART_HAL_FIFO16 (PCH_UART_FCR_FIFOE)
170#define PCH_UART_HAL_FIFO256 (PCH_UART_FCR_FIFOE | \
171 PCH_UART_FCR_FIFO256)
172#define PCH_UART_HAL_FIFO64 (PCH_UART_HAL_FIFO256)
173#define PCH_UART_HAL_TRIGGER1 (PCH_UART_FCR_RFTL1)
174#define PCH_UART_HAL_TRIGGER64 (PCH_UART_FCR_RFTL64)
175#define PCH_UART_HAL_TRIGGER128 (PCH_UART_FCR_RFTL128)
176#define PCH_UART_HAL_TRIGGER224 (PCH_UART_FCR_RFTL224)
177#define PCH_UART_HAL_TRIGGER16 (PCH_UART_FCR_RFTL16)
178#define PCH_UART_HAL_TRIGGER32 (PCH_UART_FCR_RFTL32)
179#define PCH_UART_HAL_TRIGGER56 (PCH_UART_FCR_RFTL56)
180#define PCH_UART_HAL_TRIGGER4 (PCH_UART_FCR_RFTL4)
181#define PCH_UART_HAL_TRIGGER8 (PCH_UART_FCR_RFTL8)
182#define PCH_UART_HAL_TRIGGER14 (PCH_UART_FCR_RFTL14)
183#define PCH_UART_HAL_TRIGGER_L (PCH_UART_FCR_RFTL64)
184#define PCH_UART_HAL_TRIGGER_M (PCH_UART_FCR_RFTL128)
185#define PCH_UART_HAL_TRIGGER_H (PCH_UART_FCR_RFTL224)
186
187#define PCH_UART_HAL_RX_INT (PCH_UART_IER_ERBFI)
188#define PCH_UART_HAL_TX_INT (PCH_UART_IER_ETBEI)
189#define PCH_UART_HAL_RX_ERR_INT (PCH_UART_IER_ELSI)
190#define PCH_UART_HAL_MS_INT (PCH_UART_IER_EDSSI)
191#define PCH_UART_HAL_ALL_INT (PCH_UART_IER_MASK)
192
193#define PCH_UART_HAL_DTR (PCH_UART_MCR_DTR)
194#define PCH_UART_HAL_RTS (PCH_UART_MCR_RTS)
195#define PCH_UART_HAL_OUT (PCH_UART_MCR_OUT)
196#define PCH_UART_HAL_LOOP (PCH_UART_MCR_LOOP)
197#define PCH_UART_HAL_AFE (PCH_UART_MCR_AFE)
198
Tomoya MORINAGA4564e1e2011-01-28 18:00:01 +0900199#define PCI_VENDOR_ID_ROHM 0x10DB
200
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900201struct pch_uart_buffer {
202 unsigned char *buf;
203 int size;
204};
205
206struct eg20t_port {
207 struct uart_port port;
208 int port_type;
209 void __iomem *membase;
210 resource_size_t mapbase;
211 unsigned int iobase;
212 struct pci_dev *pdev;
213 int fifo_size;
214 int base_baud;
215 int start_tx;
216 int start_rx;
217 int tx_empty;
218 int int_dis_flag;
219 int trigger;
220 int trigger_level;
221 struct pch_uart_buffer rxbuf;
222 unsigned int dmsr;
223 unsigned int fcr;
Tomoya MORINAGA9af71552011-02-23 10:03:17 +0900224 unsigned int mcr;
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900225 unsigned int use_dma;
226 unsigned int use_dma_flag;
227 struct dma_async_tx_descriptor *desc_tx;
228 struct dma_async_tx_descriptor *desc_rx;
229 struct pch_dma_slave param_tx;
230 struct pch_dma_slave param_rx;
231 struct dma_chan *chan_tx;
232 struct dma_chan *chan_rx;
Tomoya MORINAGAda3564e2011-02-23 10:03:12 +0900233 struct scatterlist *sg_tx_p;
234 int nent;
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900235 struct scatterlist sg_rx;
236 int tx_dma_use;
237 void *rx_buf_virt;
238 dma_addr_t rx_buf_dma;
239};
240
Tomoya MORINAGAfec38d12011-02-23 10:03:19 +0900241/**
242 * struct pch_uart_driver_data - private data structure for UART-DMA
243 * @port_type: The number of DMA channel
244 * @line_no: UART port line number (0, 1, 2...)
245 */
246struct pch_uart_driver_data {
247 int port_type;
248 int line_no;
249};
250
251enum pch_uart_num_t {
252 pch_et20t_uart0 = 0,
253 pch_et20t_uart1,
254 pch_et20t_uart2,
255 pch_et20t_uart3,
256 pch_ml7213_uart0,
257 pch_ml7213_uart1,
258 pch_ml7213_uart2,
Tomoya MORINAGA177c2cb2011-05-09 17:25:20 +0900259 pch_ml7223_uart0,
260 pch_ml7223_uart1,
Tomoya MORINAGA8249f742011-10-28 09:38:49 +0900261 pch_ml7831_uart0,
262 pch_ml7831_uart1,
Tomoya MORINAGAfec38d12011-02-23 10:03:19 +0900263};
264
265static struct pch_uart_driver_data drv_dat[] = {
266 [pch_et20t_uart0] = {PCH_UART_8LINE, 0},
267 [pch_et20t_uart1] = {PCH_UART_2LINE, 1},
268 [pch_et20t_uart2] = {PCH_UART_2LINE, 2},
269 [pch_et20t_uart3] = {PCH_UART_2LINE, 3},
270 [pch_ml7213_uart0] = {PCH_UART_8LINE, 0},
271 [pch_ml7213_uart1] = {PCH_UART_2LINE, 1},
272 [pch_ml7213_uart2] = {PCH_UART_2LINE, 2},
Tomoya MORINAGA177c2cb2011-05-09 17:25:20 +0900273 [pch_ml7223_uart0] = {PCH_UART_8LINE, 0},
274 [pch_ml7223_uart1] = {PCH_UART_2LINE, 1},
Tomoya MORINAGA8249f742011-10-28 09:38:49 +0900275 [pch_ml7831_uart0] = {PCH_UART_8LINE, 0},
276 [pch_ml7831_uart1] = {PCH_UART_2LINE, 1},
Tomoya MORINAGAfec38d12011-02-23 10:03:19 +0900277};
278
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900279static unsigned int default_baud = 9600;
280static const int trigger_level_256[4] = { 1, 64, 128, 224 };
281static const int trigger_level_64[4] = { 1, 16, 32, 56 };
282static const int trigger_level_16[4] = { 1, 4, 8, 14 };
283static const int trigger_level_1[4] = { 1, 1, 1, 1 };
284
285static void pch_uart_hal_request(struct pci_dev *pdev, int fifosize,
286 int base_baud)
287{
288 struct eg20t_port *priv = pci_get_drvdata(pdev);
289
290 priv->trigger_level = 1;
291 priv->fcr = 0;
292}
293
294static unsigned int get_msr(struct eg20t_port *priv, void __iomem *base)
295{
296 unsigned int msr = ioread8(base + UART_MSR);
297 priv->dmsr |= msr & PCH_UART_MSR_DELTA;
298
299 return msr;
300}
301
302static void pch_uart_hal_enable_interrupt(struct eg20t_port *priv,
303 unsigned int flag)
304{
305 u8 ier = ioread8(priv->membase + UART_IER);
306 ier |= flag & PCH_UART_IER_MASK;
307 iowrite8(ier, priv->membase + UART_IER);
308}
309
310static void pch_uart_hal_disable_interrupt(struct eg20t_port *priv,
311 unsigned int flag)
312{
313 u8 ier = ioread8(priv->membase + UART_IER);
314 ier &= ~(flag & PCH_UART_IER_MASK);
315 iowrite8(ier, priv->membase + UART_IER);
316}
317
318static int pch_uart_hal_set_line(struct eg20t_port *priv, int baud,
319 unsigned int parity, unsigned int bits,
320 unsigned int stb)
321{
322 unsigned int dll, dlm, lcr;
323 int div;
324
Uwe Kleine-König0e2adc02011-05-26 10:41:17 +0200325 div = DIV_ROUND_CLOSEST(priv->base_baud / 16, baud);
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900326 if (div < 0 || USHRT_MAX <= div) {
Tomoya MORINAGA23877fd2011-02-23 10:03:15 +0900327 dev_err(priv->port.dev, "Invalid Baud(div=0x%x)\n", div);
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900328 return -EINVAL;
329 }
330
331 dll = (unsigned int)div & 0x00FFU;
332 dlm = ((unsigned int)div >> 8) & 0x00FFU;
333
334 if (parity & ~(PCH_UART_LCR_PEN | PCH_UART_LCR_EPS | PCH_UART_LCR_SP)) {
Tomoya MORINAGA23877fd2011-02-23 10:03:15 +0900335 dev_err(priv->port.dev, "Invalid parity(0x%x)\n", parity);
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900336 return -EINVAL;
337 }
338
339 if (bits & ~PCH_UART_LCR_WLS) {
Tomoya MORINAGA23877fd2011-02-23 10:03:15 +0900340 dev_err(priv->port.dev, "Invalid bits(0x%x)\n", bits);
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900341 return -EINVAL;
342 }
343
344 if (stb & ~PCH_UART_LCR_STB) {
Tomoya MORINAGA23877fd2011-02-23 10:03:15 +0900345 dev_err(priv->port.dev, "Invalid STB(0x%x)\n", stb);
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900346 return -EINVAL;
347 }
348
349 lcr = parity;
350 lcr |= bits;
351 lcr |= stb;
352
Tomoya MORINAGA23877fd2011-02-23 10:03:15 +0900353 dev_dbg(priv->port.dev, "%s:baud = %d, div = %04x, lcr = %02x (%lu)\n",
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900354 __func__, baud, div, lcr, jiffies);
355 iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR);
356 iowrite8(dll, priv->membase + PCH_UART_DLL);
357 iowrite8(dlm, priv->membase + PCH_UART_DLM);
358 iowrite8(lcr, priv->membase + UART_LCR);
359
360 return 0;
361}
362
363static int pch_uart_hal_fifo_reset(struct eg20t_port *priv,
364 unsigned int flag)
365{
366 if (flag & ~(PCH_UART_FCR_TFR | PCH_UART_FCR_RFR)) {
Tomoya MORINAGA23877fd2011-02-23 10:03:15 +0900367 dev_err(priv->port.dev, "%s:Invalid flag(0x%x)\n",
368 __func__, flag);
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900369 return -EINVAL;
370 }
371
372 iowrite8(PCH_UART_FCR_FIFOE | priv->fcr, priv->membase + UART_FCR);
373 iowrite8(PCH_UART_FCR_FIFOE | priv->fcr | flag,
374 priv->membase + UART_FCR);
375 iowrite8(priv->fcr, priv->membase + UART_FCR);
376
377 return 0;
378}
379
380static int pch_uart_hal_set_fifo(struct eg20t_port *priv,
381 unsigned int dmamode,
382 unsigned int fifo_size, unsigned int trigger)
383{
384 u8 fcr;
385
386 if (dmamode & ~PCH_UART_FCR_DMS) {
Tomoya MORINAGA23877fd2011-02-23 10:03:15 +0900387 dev_err(priv->port.dev, "%s:Invalid DMA Mode(0x%x)\n",
388 __func__, dmamode);
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900389 return -EINVAL;
390 }
391
392 if (fifo_size & ~(PCH_UART_FCR_FIFOE | PCH_UART_FCR_FIFO256)) {
Tomoya MORINAGA23877fd2011-02-23 10:03:15 +0900393 dev_err(priv->port.dev, "%s:Invalid FIFO SIZE(0x%x)\n",
394 __func__, fifo_size);
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900395 return -EINVAL;
396 }
397
398 if (trigger & ~PCH_UART_FCR_RFTL) {
Tomoya MORINAGA23877fd2011-02-23 10:03:15 +0900399 dev_err(priv->port.dev, "%s:Invalid TRIGGER(0x%x)\n",
400 __func__, trigger);
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900401 return -EINVAL;
402 }
403
404 switch (priv->fifo_size) {
405 case 256:
406 priv->trigger_level =
407 trigger_level_256[trigger >> PCH_UART_FCR_RFTL_SHIFT];
408 break;
409 case 64:
410 priv->trigger_level =
411 trigger_level_64[trigger >> PCH_UART_FCR_RFTL_SHIFT];
412 break;
413 case 16:
414 priv->trigger_level =
415 trigger_level_16[trigger >> PCH_UART_FCR_RFTL_SHIFT];
416 break;
417 default:
418 priv->trigger_level =
419 trigger_level_1[trigger >> PCH_UART_FCR_RFTL_SHIFT];
420 break;
421 }
422 fcr =
423 dmamode | fifo_size | trigger | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR;
424 iowrite8(PCH_UART_FCR_FIFOE, priv->membase + UART_FCR);
425 iowrite8(PCH_UART_FCR_FIFOE | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR,
426 priv->membase + UART_FCR);
427 iowrite8(fcr, priv->membase + UART_FCR);
428 priv->fcr = fcr;
429
430 return 0;
431}
432
433static u8 pch_uart_hal_get_modem(struct eg20t_port *priv)
434{
435 priv->dmsr = 0;
436 return get_msr(priv, priv->membase);
437}
438
Tomoya MORINAGA18220762011-02-23 10:03:14 +0900439static void pch_uart_hal_write(struct eg20t_port *priv,
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900440 const unsigned char *buf, int tx_size)
441{
442 int i;
443 unsigned int thr;
444
445 for (i = 0; i < tx_size;) {
446 thr = buf[i++];
447 iowrite8(thr, priv->membase + PCH_UART_THR);
448 }
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900449}
450
451static int pch_uart_hal_read(struct eg20t_port *priv, unsigned char *buf,
452 int rx_size)
453{
454 int i;
455 u8 rbr, lsr;
456
457 lsr = ioread8(priv->membase + UART_LSR);
458 for (i = 0, lsr = ioread8(priv->membase + UART_LSR);
459 i < rx_size && lsr & UART_LSR_DR;
460 lsr = ioread8(priv->membase + UART_LSR)) {
461 rbr = ioread8(priv->membase + PCH_UART_RBR);
462 buf[i++] = rbr;
463 }
464 return i;
465}
466
467static unsigned int pch_uart_hal_get_iid(struct eg20t_port *priv)
468{
469 unsigned int iir;
470 int ret;
471
472 iir = ioread8(priv->membase + UART_IIR);
473 ret = (iir & (PCH_UART_IIR_IID | PCH_UART_IIR_TOI | PCH_UART_IIR_IP));
474 return ret;
475}
476
477static u8 pch_uart_hal_get_line_status(struct eg20t_port *priv)
478{
479 return ioread8(priv->membase + UART_LSR);
480}
481
482static void pch_uart_hal_set_break(struct eg20t_port *priv, int on)
483{
484 unsigned int lcr;
485
486 lcr = ioread8(priv->membase + UART_LCR);
487 if (on)
488 lcr |= PCH_UART_LCR_SB;
489 else
490 lcr &= ~PCH_UART_LCR_SB;
491
492 iowrite8(lcr, priv->membase + UART_LCR);
493}
494
495static int push_rx(struct eg20t_port *priv, const unsigned char *buf,
496 int size)
497{
498 struct uart_port *port;
499 struct tty_struct *tty;
500
501 port = &priv->port;
502 tty = tty_port_tty_get(&port->state->port);
503 if (!tty) {
Tomoya MORINAGA23877fd2011-02-23 10:03:15 +0900504 dev_dbg(priv->port.dev, "%s:tty is busy now", __func__);
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900505 return -EBUSY;
506 }
507
508 tty_insert_flip_string(tty, buf, size);
509 tty_flip_buffer_push(tty);
510 tty_kref_put(tty);
511
512 return 0;
513}
514
515static int pop_tx_x(struct eg20t_port *priv, unsigned char *buf)
516{
517 int ret;
518 struct uart_port *port = &priv->port;
519
520 if (port->x_char) {
Tomoya MORINAGA23877fd2011-02-23 10:03:15 +0900521 dev_dbg(priv->port.dev, "%s:X character send %02x (%lu)\n",
522 __func__, port->x_char, jiffies);
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900523 buf[0] = port->x_char;
524 port->x_char = 0;
525 ret = 1;
526 } else {
527 ret = 0;
528 }
529
530 return ret;
531}
532
533static int dma_push_rx(struct eg20t_port *priv, int size)
534{
535 struct tty_struct *tty;
536 int room;
537 struct uart_port *port = &priv->port;
538
539 port = &priv->port;
540 tty = tty_port_tty_get(&port->state->port);
541 if (!tty) {
Tomoya MORINAGA23877fd2011-02-23 10:03:15 +0900542 dev_dbg(priv->port.dev, "%s:tty is busy now", __func__);
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900543 return 0;
544 }
545
546 room = tty_buffer_request_room(tty, size);
547
548 if (room < size)
549 dev_warn(port->dev, "Rx overrun: dropping %u bytes\n",
550 size - room);
551 if (!room)
552 return room;
553
554 tty_insert_flip_string(tty, sg_virt(&priv->sg_rx), size);
555
556 port->icount.rx += room;
557 tty_kref_put(tty);
558
559 return room;
560}
561
562static void pch_free_dma(struct uart_port *port)
563{
564 struct eg20t_port *priv;
565 priv = container_of(port, struct eg20t_port, port);
566
567 if (priv->chan_tx) {
568 dma_release_channel(priv->chan_tx);
569 priv->chan_tx = NULL;
570 }
571 if (priv->chan_rx) {
572 dma_release_channel(priv->chan_rx);
573 priv->chan_rx = NULL;
574 }
575 if (sg_dma_address(&priv->sg_rx))
576 dma_free_coherent(port->dev, port->fifosize,
577 sg_virt(&priv->sg_rx),
578 sg_dma_address(&priv->sg_rx));
579
580 return;
581}
582
583static bool filter(struct dma_chan *chan, void *slave)
584{
585 struct pch_dma_slave *param = slave;
586
587 if ((chan->chan_id == param->chan_id) && (param->dma_dev ==
588 chan->device->dev)) {
589 chan->private = param;
590 return true;
591 } else {
592 return false;
593 }
594}
595
596static void pch_request_dma(struct uart_port *port)
597{
598 dma_cap_mask_t mask;
599 struct dma_chan *chan;
600 struct pci_dev *dma_dev;
601 struct pch_dma_slave *param;
602 struct eg20t_port *priv =
603 container_of(port, struct eg20t_port, port);
604 dma_cap_zero(mask);
605 dma_cap_set(DMA_SLAVE, mask);
606
Tomoya MORINAGA6c4b47d2011-07-20 20:17:49 +0900607 dma_dev = pci_get_bus_and_slot(priv->pdev->bus->number,
608 PCI_DEVFN(0xa, 0)); /* Get DMA's dev
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900609 information */
610 /* Set Tx DMA */
611 param = &priv->param_tx;
612 param->dma_dev = &dma_dev->dev;
Tomoya MORINAGAfec38d12011-02-23 10:03:19 +0900613 param->chan_id = priv->port.line * 2; /* Tx = 0, 2, 4, ... */
614
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900615 param->tx_reg = port->mapbase + UART_TX;
616 chan = dma_request_channel(mask, filter, param);
617 if (!chan) {
Tomoya MORINAGA23877fd2011-02-23 10:03:15 +0900618 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Tx)\n",
619 __func__);
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900620 return;
621 }
622 priv->chan_tx = chan;
623
624 /* Set Rx DMA */
625 param = &priv->param_rx;
626 param->dma_dev = &dma_dev->dev;
Tomoya MORINAGAfec38d12011-02-23 10:03:19 +0900627 param->chan_id = priv->port.line * 2 + 1; /* Rx = Tx + 1 */
628
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900629 param->rx_reg = port->mapbase + UART_RX;
630 chan = dma_request_channel(mask, filter, param);
631 if (!chan) {
Tomoya MORINAGA23877fd2011-02-23 10:03:15 +0900632 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Rx)\n",
633 __func__);
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900634 dma_release_channel(priv->chan_tx);
635 return;
636 }
637
638 /* Get Consistent memory for DMA */
639 priv->rx_buf_virt = dma_alloc_coherent(port->dev, port->fifosize,
640 &priv->rx_buf_dma, GFP_KERNEL);
641 priv->chan_rx = chan;
642}
643
644static void pch_dma_rx_complete(void *arg)
645{
646 struct eg20t_port *priv = arg;
647 struct uart_port *port = &priv->port;
648 struct tty_struct *tty = tty_port_tty_get(&port->state->port);
Tomoya MORINAGAda3564e2011-02-23 10:03:12 +0900649 int count;
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900650
651 if (!tty) {
Tomoya MORINAGA23877fd2011-02-23 10:03:15 +0900652 dev_dbg(priv->port.dev, "%s:tty is busy now", __func__);
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900653 return;
654 }
655
Tomoya MORINAGAda3564e2011-02-23 10:03:12 +0900656 dma_sync_sg_for_cpu(port->dev, &priv->sg_rx, 1, DMA_FROM_DEVICE);
657 count = dma_push_rx(priv, priv->trigger_level);
658 if (count)
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900659 tty_flip_buffer_push(tty);
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900660 tty_kref_put(tty);
Tomoya MORINAGAda3564e2011-02-23 10:03:12 +0900661 async_tx_ack(priv->desc_rx);
662 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT);
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900663}
664
665static void pch_dma_tx_complete(void *arg)
666{
667 struct eg20t_port *priv = arg;
668 struct uart_port *port = &priv->port;
669 struct circ_buf *xmit = &port->state->xmit;
Tomoya MORINAGAda3564e2011-02-23 10:03:12 +0900670 struct scatterlist *sg = priv->sg_tx_p;
671 int i;
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900672
Tomoya MORINAGAda3564e2011-02-23 10:03:12 +0900673 for (i = 0; i < priv->nent; i++, sg++) {
674 xmit->tail += sg_dma_len(sg);
675 port->icount.tx += sg_dma_len(sg);
676 }
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900677 xmit->tail &= UART_XMIT_SIZE - 1;
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900678 async_tx_ack(priv->desc_tx);
Tomoya MORINAGAda3564e2011-02-23 10:03:12 +0900679 dma_unmap_sg(port->dev, sg, priv->nent, DMA_TO_DEVICE);
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900680 priv->tx_dma_use = 0;
Tomoya MORINAGAda3564e2011-02-23 10:03:12 +0900681 priv->nent = 0;
682 kfree(priv->sg_tx_p);
Tomoya MORINAGA60d10312011-02-23 10:03:18 +0900683 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT);
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900684}
685
Tomoya MORINAGA18220762011-02-23 10:03:14 +0900686static int pop_tx(struct eg20t_port *priv, int size)
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900687{
688 int count = 0;
689 struct uart_port *port = &priv->port;
690 struct circ_buf *xmit = &port->state->xmit;
691
692 if (uart_tx_stopped(port) || uart_circ_empty(xmit) || count >= size)
693 goto pop_tx_end;
694
695 do {
696 int cnt_to_end =
697 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
698 int sz = min(size - count, cnt_to_end);
Tomoya MORINAGA18220762011-02-23 10:03:14 +0900699 pch_uart_hal_write(priv, &xmit->buf[xmit->tail], sz);
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900700 xmit->tail = (xmit->tail + sz) & (UART_XMIT_SIZE - 1);
701 count += sz;
702 } while (!uart_circ_empty(xmit) && count < size);
703
704pop_tx_end:
Tomoya MORINAGA23877fd2011-02-23 10:03:15 +0900705 dev_dbg(priv->port.dev, "%d characters. Remained %d characters.(%lu)\n",
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900706 count, size - count, jiffies);
707
708 return count;
709}
710
711static int handle_rx_to(struct eg20t_port *priv)
712{
713 struct pch_uart_buffer *buf;
714 int rx_size;
715 int ret;
716 if (!priv->start_rx) {
717 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT);
718 return 0;
719 }
720 buf = &priv->rxbuf;
721 do {
722 rx_size = pch_uart_hal_read(priv, buf->buf, buf->size);
723 ret = push_rx(priv, buf->buf, rx_size);
724 if (ret)
725 return 0;
726 } while (rx_size == buf->size);
727
728 return PCH_UART_HANDLED_RX_INT;
729}
730
731static int handle_rx(struct eg20t_port *priv)
732{
733 return handle_rx_to(priv);
734}
735
736static int dma_handle_rx(struct eg20t_port *priv)
737{
738 struct uart_port *port = &priv->port;
739 struct dma_async_tx_descriptor *desc;
740 struct scatterlist *sg;
741
742 priv = container_of(port, struct eg20t_port, port);
743 sg = &priv->sg_rx;
744
745 sg_init_table(&priv->sg_rx, 1); /* Initialize SG table */
746
Tomoya MORINAGAda3564e2011-02-23 10:03:12 +0900747 sg_dma_len(sg) = priv->trigger_level;
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900748
749 sg_set_page(&priv->sg_rx, virt_to_page(priv->rx_buf_virt),
Tomoya MORINAGA1c518992010-12-16 16:13:29 +0900750 sg_dma_len(sg), (unsigned long)priv->rx_buf_virt &
751 ~PAGE_MASK);
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900752
753 sg_dma_address(sg) = priv->rx_buf_dma;
754
755 desc = priv->chan_rx->device->device_prep_slave_sg(priv->chan_rx,
756 sg, 1, DMA_FROM_DEVICE,
Tomoya MORINAGAda3564e2011-02-23 10:03:12 +0900757 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
758
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900759 if (!desc)
760 return 0;
761
762 priv->desc_rx = desc;
763 desc->callback = pch_dma_rx_complete;
764 desc->callback_param = priv;
765 desc->tx_submit(desc);
766 dma_async_issue_pending(priv->chan_rx);
767
768 return PCH_UART_HANDLED_RX_INT;
769}
770
771static unsigned int handle_tx(struct eg20t_port *priv)
772{
773 struct uart_port *port = &priv->port;
774 struct circ_buf *xmit = &port->state->xmit;
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900775 int fifo_size;
776 int tx_size;
777 int size;
778 int tx_empty;
779
780 if (!priv->start_tx) {
Tomoya MORINAGA23877fd2011-02-23 10:03:15 +0900781 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n",
782 __func__, jiffies);
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900783 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
784 priv->tx_empty = 1;
785 return 0;
786 }
787
788 fifo_size = max(priv->fifo_size, 1);
789 tx_empty = 1;
790 if (pop_tx_x(priv, xmit->buf)) {
791 pch_uart_hal_write(priv, xmit->buf, 1);
792 port->icount.tx++;
793 tx_empty = 0;
794 fifo_size--;
795 }
796 size = min(xmit->head - xmit->tail, fifo_size);
Tomoya MORINAGAda3564e2011-02-23 10:03:12 +0900797 if (size < 0)
798 size = fifo_size;
799
Tomoya MORINAGA18220762011-02-23 10:03:14 +0900800 tx_size = pop_tx(priv, size);
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900801 if (tx_size > 0) {
Tomoya MORINAGA18220762011-02-23 10:03:14 +0900802 port->icount.tx += tx_size;
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900803 tx_empty = 0;
804 }
805
806 priv->tx_empty = tx_empty;
807
Tomoya MORINAGAda3564e2011-02-23 10:03:12 +0900808 if (tx_empty) {
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900809 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
Tomoya MORINAGAda3564e2011-02-23 10:03:12 +0900810 uart_write_wakeup(port);
811 }
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900812
813 return PCH_UART_HANDLED_TX_INT;
814}
815
816static unsigned int dma_handle_tx(struct eg20t_port *priv)
817{
818 struct uart_port *port = &priv->port;
819 struct circ_buf *xmit = &port->state->xmit;
Tomoya MORINAGAda3564e2011-02-23 10:03:12 +0900820 struct scatterlist *sg;
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900821 int nent;
822 int fifo_size;
823 int tx_empty;
824 struct dma_async_tx_descriptor *desc;
Tomoya MORINAGAda3564e2011-02-23 10:03:12 +0900825 int num;
826 int i;
827 int bytes;
828 int size;
829 int rem;
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900830
831 if (!priv->start_tx) {
Tomoya MORINAGA23877fd2011-02-23 10:03:15 +0900832 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n",
833 __func__, jiffies);
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900834 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
835 priv->tx_empty = 1;
836 return 0;
837 }
838
Tomoya MORINAGA60d10312011-02-23 10:03:18 +0900839 if (priv->tx_dma_use) {
840 dev_dbg(priv->port.dev, "%s:Tx is not completed. (%lu)\n",
841 __func__, jiffies);
842 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
843 priv->tx_empty = 1;
844 return 0;
845 }
846
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900847 fifo_size = max(priv->fifo_size, 1);
848 tx_empty = 1;
849 if (pop_tx_x(priv, xmit->buf)) {
850 pch_uart_hal_write(priv, xmit->buf, 1);
851 port->icount.tx++;
852 tx_empty = 0;
853 fifo_size--;
854 }
855
Tomoya MORINAGAda3564e2011-02-23 10:03:12 +0900856 bytes = min((int)CIRC_CNT(xmit->head, xmit->tail,
857 UART_XMIT_SIZE), CIRC_CNT_TO_END(xmit->head,
858 xmit->tail, UART_XMIT_SIZE));
859 if (!bytes) {
Tomoya MORINAGA23877fd2011-02-23 10:03:15 +0900860 dev_dbg(priv->port.dev, "%s 0 bytes return\n", __func__);
Tomoya MORINAGAda3564e2011-02-23 10:03:12 +0900861 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
862 uart_write_wakeup(port);
863 return 0;
864 }
865
866 if (bytes > fifo_size) {
867 num = bytes / fifo_size + 1;
868 size = fifo_size;
869 rem = bytes % fifo_size;
870 } else {
871 num = 1;
872 size = bytes;
873 rem = bytes;
874 }
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900875
Tomoya MORINAGA23877fd2011-02-23 10:03:15 +0900876 dev_dbg(priv->port.dev, "%s num=%d size=%d rem=%d\n",
877 __func__, num, size, rem);
878
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900879 priv->tx_dma_use = 1;
880
Tomoya MORINAGAda3564e2011-02-23 10:03:12 +0900881 priv->sg_tx_p = kzalloc(sizeof(struct scatterlist)*num, GFP_ATOMIC);
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900882
Tomoya MORINAGAda3564e2011-02-23 10:03:12 +0900883 sg_init_table(priv->sg_tx_p, num); /* Initialize SG table */
884 sg = priv->sg_tx_p;
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900885
Tomoya MORINAGAda3564e2011-02-23 10:03:12 +0900886 for (i = 0; i < num; i++, sg++) {
887 if (i == (num - 1))
888 sg_set_page(sg, virt_to_page(xmit->buf),
889 rem, fifo_size * i);
890 else
891 sg_set_page(sg, virt_to_page(xmit->buf),
892 size, fifo_size * i);
893 }
894
895 sg = priv->sg_tx_p;
896 nent = dma_map_sg(port->dev, sg, num, DMA_TO_DEVICE);
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900897 if (!nent) {
Tomoya MORINAGA23877fd2011-02-23 10:03:15 +0900898 dev_err(priv->port.dev, "%s:dma_map_sg Failed\n", __func__);
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900899 return 0;
900 }
Tomoya MORINAGAda3564e2011-02-23 10:03:12 +0900901 priv->nent = nent;
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900902
Tomoya MORINAGAda3564e2011-02-23 10:03:12 +0900903 for (i = 0; i < nent; i++, sg++) {
904 sg->offset = (xmit->tail & (UART_XMIT_SIZE - 1)) +
905 fifo_size * i;
906 sg_dma_address(sg) = (sg_dma_address(sg) &
907 ~(UART_XMIT_SIZE - 1)) + sg->offset;
908 if (i == (nent - 1))
909 sg_dma_len(sg) = rem;
910 else
911 sg_dma_len(sg) = size;
912 }
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900913
914 desc = priv->chan_tx->device->device_prep_slave_sg(priv->chan_tx,
Tomoya MORINAGAda3564e2011-02-23 10:03:12 +0900915 priv->sg_tx_p, nent, DMA_TO_DEVICE,
916 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900917 if (!desc) {
Tomoya MORINAGA23877fd2011-02-23 10:03:15 +0900918 dev_err(priv->port.dev, "%s:device_prep_slave_sg Failed\n",
919 __func__);
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900920 return 0;
921 }
Tomoya MORINAGAda3564e2011-02-23 10:03:12 +0900922 dma_sync_sg_for_device(port->dev, priv->sg_tx_p, nent, DMA_TO_DEVICE);
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900923 priv->desc_tx = desc;
924 desc->callback = pch_dma_tx_complete;
925 desc->callback_param = priv;
926
927 desc->tx_submit(desc);
928
929 dma_async_issue_pending(priv->chan_tx);
930
931 return PCH_UART_HANDLED_TX_INT;
932}
933
934static void pch_uart_err_ir(struct eg20t_port *priv, unsigned int lsr)
935{
936 u8 fcr = ioread8(priv->membase + UART_FCR);
937
938 /* Reset FIFO */
939 fcr |= UART_FCR_CLEAR_RCVR;
940 iowrite8(fcr, priv->membase + UART_FCR);
941
942 if (lsr & PCH_UART_LSR_ERR)
943 dev_err(&priv->pdev->dev, "Error data in FIFO\n");
944
945 if (lsr & UART_LSR_FE)
946 dev_err(&priv->pdev->dev, "Framing Error\n");
947
948 if (lsr & UART_LSR_PE)
949 dev_err(&priv->pdev->dev, "Parity Error\n");
950
951 if (lsr & UART_LSR_OE)
952 dev_err(&priv->pdev->dev, "Overrun Error\n");
953}
954
955static irqreturn_t pch_uart_interrupt(int irq, void *dev_id)
956{
957 struct eg20t_port *priv = dev_id;
958 unsigned int handled;
959 u8 lsr;
960 int ret = 0;
961 unsigned int iid;
962 unsigned long flags;
963
964 spin_lock_irqsave(&priv->port.lock, flags);
965 handled = 0;
966 while ((iid = pch_uart_hal_get_iid(priv)) > 1) {
967 switch (iid) {
968 case PCH_UART_IID_RLS: /* Receiver Line Status */
969 lsr = pch_uart_hal_get_line_status(priv);
970 if (lsr & (PCH_UART_LSR_ERR | UART_LSR_FE |
971 UART_LSR_PE | UART_LSR_OE)) {
972 pch_uart_err_ir(priv, lsr);
973 ret = PCH_UART_HANDLED_RX_ERR_INT;
974 }
975 break;
976 case PCH_UART_IID_RDR: /* Received Data Ready */
Tomoya MORINAGAda3564e2011-02-23 10:03:12 +0900977 if (priv->use_dma) {
978 pch_uart_hal_disable_interrupt(priv,
979 PCH_UART_HAL_RX_INT);
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900980 ret = dma_handle_rx(priv);
Tomoya MORINAGAda3564e2011-02-23 10:03:12 +0900981 if (!ret)
982 pch_uart_hal_enable_interrupt(priv,
983 PCH_UART_HAL_RX_INT);
984 } else {
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900985 ret = handle_rx(priv);
Tomoya MORINAGAda3564e2011-02-23 10:03:12 +0900986 }
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +0900987 break;
988 case PCH_UART_IID_RDR_TO: /* Received Data Ready
989 (FIFO Timeout) */
990 ret = handle_rx_to(priv);
991 break;
992 case PCH_UART_IID_THRE: /* Transmitter Holding Register
993 Empty */
994 if (priv->use_dma)
995 ret = dma_handle_tx(priv);
996 else
997 ret = handle_tx(priv);
998 break;
999 case PCH_UART_IID_MS: /* Modem Status */
1000 ret = PCH_UART_HANDLED_MS_INT;
1001 break;
1002 default: /* Never junp to this label */
Tomoya MORINAGA23877fd2011-02-23 10:03:15 +09001003 dev_err(priv->port.dev, "%s:iid=%d (%lu)\n", __func__,
1004 iid, jiffies);
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09001005 ret = -1;
1006 break;
1007 }
1008 handled |= (unsigned int)ret;
1009 }
1010 if (handled == 0 && iid <= 1) {
1011 if (priv->int_dis_flag)
1012 priv->int_dis_flag = 0;
1013 }
1014
1015 spin_unlock_irqrestore(&priv->port.lock, flags);
1016 return IRQ_RETVAL(handled);
1017}
1018
1019/* This function tests whether the transmitter fifo and shifter for the port
1020 described by 'port' is empty. */
1021static unsigned int pch_uart_tx_empty(struct uart_port *port)
1022{
1023 struct eg20t_port *priv;
1024 int ret;
1025 priv = container_of(port, struct eg20t_port, port);
1026 if (priv->tx_empty)
1027 ret = TIOCSER_TEMT;
1028 else
1029 ret = 0;
1030
1031 return ret;
1032}
1033
1034/* Returns the current state of modem control inputs. */
1035static unsigned int pch_uart_get_mctrl(struct uart_port *port)
1036{
1037 struct eg20t_port *priv;
1038 u8 modem;
1039 unsigned int ret = 0;
1040
1041 priv = container_of(port, struct eg20t_port, port);
1042 modem = pch_uart_hal_get_modem(priv);
1043
1044 if (modem & UART_MSR_DCD)
1045 ret |= TIOCM_CAR;
1046
1047 if (modem & UART_MSR_RI)
1048 ret |= TIOCM_RNG;
1049
1050 if (modem & UART_MSR_DSR)
1051 ret |= TIOCM_DSR;
1052
1053 if (modem & UART_MSR_CTS)
1054 ret |= TIOCM_CTS;
1055
1056 return ret;
1057}
1058
1059static void pch_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1060{
1061 u32 mcr = 0;
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09001062 struct eg20t_port *priv = container_of(port, struct eg20t_port, port);
1063
1064 if (mctrl & TIOCM_DTR)
1065 mcr |= UART_MCR_DTR;
1066 if (mctrl & TIOCM_RTS)
1067 mcr |= UART_MCR_RTS;
1068 if (mctrl & TIOCM_LOOP)
1069 mcr |= UART_MCR_LOOP;
1070
Tomoya MORINAGA9af71552011-02-23 10:03:17 +09001071 if (priv->mcr & UART_MCR_AFE)
1072 mcr |= UART_MCR_AFE;
1073
1074 if (mctrl)
1075 iowrite8(mcr, priv->membase + UART_MCR);
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09001076}
1077
1078static void pch_uart_stop_tx(struct uart_port *port)
1079{
1080 struct eg20t_port *priv;
1081 priv = container_of(port, struct eg20t_port, port);
1082 priv->start_tx = 0;
1083 priv->tx_dma_use = 0;
1084}
1085
1086static void pch_uart_start_tx(struct uart_port *port)
1087{
1088 struct eg20t_port *priv;
1089
1090 priv = container_of(port, struct eg20t_port, port);
1091
Tomoya MORINAGA23877fd2011-02-23 10:03:15 +09001092 if (priv->use_dma) {
1093 if (priv->tx_dma_use) {
1094 dev_dbg(priv->port.dev, "%s : Tx DMA is NOT empty.\n",
1095 __func__);
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09001096 return;
Tomoya MORINAGA23877fd2011-02-23 10:03:15 +09001097 }
1098 }
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09001099
1100 priv->start_tx = 1;
1101 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT);
1102}
1103
1104static void pch_uart_stop_rx(struct uart_port *port)
1105{
1106 struct eg20t_port *priv;
1107 priv = container_of(port, struct eg20t_port, port);
1108 priv->start_rx = 0;
1109 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT);
1110 priv->int_dis_flag = 1;
1111}
1112
1113/* Enable the modem status interrupts. */
1114static void pch_uart_enable_ms(struct uart_port *port)
1115{
1116 struct eg20t_port *priv;
1117 priv = container_of(port, struct eg20t_port, port);
1118 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_MS_INT);
1119}
1120
1121/* Control the transmission of a break signal. */
1122static void pch_uart_break_ctl(struct uart_port *port, int ctl)
1123{
1124 struct eg20t_port *priv;
1125 unsigned long flags;
1126
1127 priv = container_of(port, struct eg20t_port, port);
1128 spin_lock_irqsave(&port->lock, flags);
1129 pch_uart_hal_set_break(priv, ctl);
1130 spin_unlock_irqrestore(&port->lock, flags);
1131}
1132
1133/* Grab any interrupt resources and initialise any low level driver state. */
1134static int pch_uart_startup(struct uart_port *port)
1135{
1136 struct eg20t_port *priv;
1137 int ret;
1138 int fifo_size;
1139 int trigger_level;
1140
1141 priv = container_of(port, struct eg20t_port, port);
1142 priv->tx_empty = 1;
Tomoya MORINAGAaac6c0b2011-02-23 10:03:16 +09001143
1144 if (port->uartclk)
1145 priv->base_baud = port->uartclk;
1146 else
1147 port->uartclk = priv->base_baud;
1148
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09001149 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1150 ret = pch_uart_hal_set_line(priv, default_baud,
1151 PCH_UART_HAL_PARITY_NONE, PCH_UART_HAL_8BIT,
1152 PCH_UART_HAL_STB1);
1153 if (ret)
1154 return ret;
1155
1156 switch (priv->fifo_size) {
1157 case 256:
1158 fifo_size = PCH_UART_HAL_FIFO256;
1159 break;
1160 case 64:
1161 fifo_size = PCH_UART_HAL_FIFO64;
1162 break;
1163 case 16:
1164 fifo_size = PCH_UART_HAL_FIFO16;
1165 case 1:
1166 default:
1167 fifo_size = PCH_UART_HAL_FIFO_DIS;
1168 break;
1169 }
1170
1171 switch (priv->trigger) {
1172 case PCH_UART_HAL_TRIGGER1:
1173 trigger_level = 1;
1174 break;
1175 case PCH_UART_HAL_TRIGGER_L:
1176 trigger_level = priv->fifo_size / 4;
1177 break;
1178 case PCH_UART_HAL_TRIGGER_M:
1179 trigger_level = priv->fifo_size / 2;
1180 break;
1181 case PCH_UART_HAL_TRIGGER_H:
1182 default:
1183 trigger_level = priv->fifo_size - (priv->fifo_size / 8);
1184 break;
1185 }
1186
1187 priv->trigger_level = trigger_level;
1188 ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0,
1189 fifo_size, priv->trigger);
1190 if (ret < 0)
1191 return ret;
1192
1193 ret = request_irq(priv->port.irq, pch_uart_interrupt, IRQF_SHARED,
1194 KBUILD_MODNAME, priv);
1195 if (ret < 0)
1196 return ret;
1197
1198 if (priv->use_dma)
1199 pch_request_dma(port);
1200
1201 priv->start_rx = 1;
1202 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT);
1203 uart_update_timeout(port, CS8, default_baud);
1204
1205 return 0;
1206}
1207
1208static void pch_uart_shutdown(struct uart_port *port)
1209{
1210 struct eg20t_port *priv;
1211 int ret;
1212
1213 priv = container_of(port, struct eg20t_port, port);
1214 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1215 pch_uart_hal_fifo_reset(priv, PCH_UART_HAL_CLR_ALL_FIFO);
1216 ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0,
1217 PCH_UART_HAL_FIFO_DIS, PCH_UART_HAL_TRIGGER1);
1218 if (ret)
Tomoya MORINAGA23877fd2011-02-23 10:03:15 +09001219 dev_err(priv->port.dev,
1220 "pch_uart_hal_set_fifo Failed(ret=%d)\n", ret);
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09001221
1222 if (priv->use_dma_flag)
1223 pch_free_dma(port);
1224
1225 free_irq(priv->port.irq, priv);
1226}
1227
1228/* Change the port parameters, including word length, parity, stop
1229 *bits. Update read_status_mask and ignore_status_mask to indicate
1230 *the types of events we are interested in receiving. */
1231static void pch_uart_set_termios(struct uart_port *port,
1232 struct ktermios *termios, struct ktermios *old)
1233{
1234 int baud;
1235 int rtn;
1236 unsigned int parity, bits, stb;
1237 struct eg20t_port *priv;
1238 unsigned long flags;
1239
1240 priv = container_of(port, struct eg20t_port, port);
1241 switch (termios->c_cflag & CSIZE) {
1242 case CS5:
1243 bits = PCH_UART_HAL_5BIT;
1244 break;
1245 case CS6:
1246 bits = PCH_UART_HAL_6BIT;
1247 break;
1248 case CS7:
1249 bits = PCH_UART_HAL_7BIT;
1250 break;
1251 default: /* CS8 */
1252 bits = PCH_UART_HAL_8BIT;
1253 break;
1254 }
1255 if (termios->c_cflag & CSTOPB)
1256 stb = PCH_UART_HAL_STB2;
1257 else
1258 stb = PCH_UART_HAL_STB1;
1259
1260 if (termios->c_cflag & PARENB) {
1261 if (!(termios->c_cflag & PARODD))
1262 parity = PCH_UART_HAL_PARITY_ODD;
1263 else
1264 parity = PCH_UART_HAL_PARITY_EVEN;
1265
1266 } else {
1267 parity = PCH_UART_HAL_PARITY_NONE;
1268 }
Tomoya MORINAGA9af71552011-02-23 10:03:17 +09001269
1270 /* Only UART0 has auto hardware flow function */
1271 if ((termios->c_cflag & CRTSCTS) && (priv->fifo_size == 256))
1272 priv->mcr |= UART_MCR_AFE;
1273 else
1274 priv->mcr &= ~UART_MCR_AFE;
1275
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09001276 termios->c_cflag &= ~CMSPAR; /* Mark/Space parity is not supported */
1277
1278 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
1279
1280 spin_lock_irqsave(&port->lock, flags);
1281
1282 uart_update_timeout(port, termios->c_cflag, baud);
1283 rtn = pch_uart_hal_set_line(priv, baud, parity, bits, stb);
1284 if (rtn)
1285 goto out;
1286
Tomoya MORINAGAa1d7cfe2011-10-27 15:45:18 +09001287 pch_uart_set_mctrl(&priv->port, priv->port.mctrl);
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09001288 /* Don't rewrite B0 */
1289 if (tty_termios_baud_rate(termios))
1290 tty_termios_encode_baud_rate(termios, baud, baud);
1291
1292out:
1293 spin_unlock_irqrestore(&port->lock, flags);
1294}
1295
1296static const char *pch_uart_type(struct uart_port *port)
1297{
1298 return KBUILD_MODNAME;
1299}
1300
1301static void pch_uart_release_port(struct uart_port *port)
1302{
1303 struct eg20t_port *priv;
1304
1305 priv = container_of(port, struct eg20t_port, port);
1306 pci_iounmap(priv->pdev, priv->membase);
1307 pci_release_regions(priv->pdev);
1308}
1309
1310static int pch_uart_request_port(struct uart_port *port)
1311{
1312 struct eg20t_port *priv;
1313 int ret;
1314 void __iomem *membase;
1315
1316 priv = container_of(port, struct eg20t_port, port);
1317 ret = pci_request_regions(priv->pdev, KBUILD_MODNAME);
1318 if (ret < 0)
1319 return -EBUSY;
1320
1321 membase = pci_iomap(priv->pdev, 1, 0);
1322 if (!membase) {
1323 pci_release_regions(priv->pdev);
1324 return -EBUSY;
1325 }
1326 priv->membase = port->membase = membase;
1327
1328 return 0;
1329}
1330
1331static void pch_uart_config_port(struct uart_port *port, int type)
1332{
1333 struct eg20t_port *priv;
1334
1335 priv = container_of(port, struct eg20t_port, port);
1336 if (type & UART_CONFIG_TYPE) {
1337 port->type = priv->port_type;
1338 pch_uart_request_port(port);
1339 }
1340}
1341
1342static int pch_uart_verify_port(struct uart_port *port,
1343 struct serial_struct *serinfo)
1344{
1345 struct eg20t_port *priv;
1346
1347 priv = container_of(port, struct eg20t_port, port);
1348 if (serinfo->flags & UPF_LOW_LATENCY) {
Tomoya MORINAGA23877fd2011-02-23 10:03:15 +09001349 dev_info(priv->port.dev,
1350 "PCH UART : Use PIO Mode (without DMA)\n");
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09001351 priv->use_dma = 0;
1352 serinfo->flags &= ~UPF_LOW_LATENCY;
1353 } else {
1354#ifndef CONFIG_PCH_DMA
Tomoya MORINAGA23877fd2011-02-23 10:03:15 +09001355 dev_err(priv->port.dev, "%s : PCH DMA is not Loaded.\n",
1356 __func__);
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09001357 return -EOPNOTSUPP;
1358#endif
1359 priv->use_dma = 1;
1360 priv->use_dma_flag = 1;
Tomoya MORINAGA23877fd2011-02-23 10:03:15 +09001361 dev_info(priv->port.dev, "PCH UART : Use DMA Mode\n");
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09001362 }
1363
1364 return 0;
1365}
1366
1367static struct uart_ops pch_uart_ops = {
1368 .tx_empty = pch_uart_tx_empty,
1369 .set_mctrl = pch_uart_set_mctrl,
1370 .get_mctrl = pch_uart_get_mctrl,
1371 .stop_tx = pch_uart_stop_tx,
1372 .start_tx = pch_uart_start_tx,
1373 .stop_rx = pch_uart_stop_rx,
1374 .enable_ms = pch_uart_enable_ms,
1375 .break_ctl = pch_uart_break_ctl,
1376 .startup = pch_uart_startup,
1377 .shutdown = pch_uart_shutdown,
1378 .set_termios = pch_uart_set_termios,
1379/* .pm = pch_uart_pm, Not supported yet */
1380/* .set_wake = pch_uart_set_wake, Not supported yet */
1381 .type = pch_uart_type,
1382 .release_port = pch_uart_release_port,
1383 .request_port = pch_uart_request_port,
1384 .config_port = pch_uart_config_port,
1385 .verify_port = pch_uart_verify_port
1386};
1387
1388static struct uart_driver pch_uart_driver = {
1389 .owner = THIS_MODULE,
1390 .driver_name = KBUILD_MODNAME,
1391 .dev_name = PCH_UART_DRIVER_DEVICE,
1392 .major = 0,
1393 .minor = 0,
1394 .nr = PCH_UART_NR,
1395};
1396
1397static struct eg20t_port *pch_uart_init_port(struct pci_dev *pdev,
Tomoya MORINAGA4564e1e2011-01-28 18:00:01 +09001398 const struct pci_device_id *id)
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09001399{
1400 struct eg20t_port *priv;
1401 int ret;
1402 unsigned int iobase;
1403 unsigned int mapbase;
Tomoya MORINAGA1c518992010-12-16 16:13:29 +09001404 unsigned char *rxbuf;
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09001405 int fifosize, base_baud;
Tomoya MORINAGAfec38d12011-02-23 10:03:19 +09001406 int port_type;
1407 struct pch_uart_driver_data *board;
Alexander Steinfb139df2011-06-15 15:08:55 -07001408 const char *board_name;
Tomoya MORINAGAfec38d12011-02-23 10:03:19 +09001409
1410 board = &drv_dat[id->driver_data];
1411 port_type = board->port_type;
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09001412
1413 priv = kzalloc(sizeof(struct eg20t_port), GFP_KERNEL);
1414 if (priv == NULL)
1415 goto init_port_alloc_err;
1416
Tomoya MORINAGA1c518992010-12-16 16:13:29 +09001417 rxbuf = (unsigned char *)__get_free_page(GFP_KERNEL);
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09001418 if (!rxbuf)
1419 goto init_port_free_txbuf;
1420
Denis Turischev6ae705b2011-03-10 15:14:00 +02001421 base_baud = 1843200; /* 1.8432MHz */
1422
1423 /* quirk for CM-iTC board */
Alexander Steinfb139df2011-06-15 15:08:55 -07001424 board_name = dmi_get_system_info(DMI_BOARD_NAME);
1425 if (board_name && strstr(board_name, "CM-iTC"))
Denis Turischev6ae705b2011-03-10 15:14:00 +02001426 base_baud = 192000000; /* 192.0MHz */
1427
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09001428 switch (port_type) {
1429 case PORT_UNKNOWN:
Tomoya MORINAGA4564e1e2011-01-28 18:00:01 +09001430 fifosize = 256; /* EG20T/ML7213: UART0 */
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09001431 break;
1432 case PORT_8250:
Tomoya MORINAGA4564e1e2011-01-28 18:00:01 +09001433 fifosize = 64; /* EG20T:UART1~3 ML7213: UART1~2*/
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09001434 break;
1435 default:
1436 dev_err(&pdev->dev, "Invalid Port Type(=%d)\n", port_type);
1437 goto init_port_hal_free;
1438 }
1439
Alexander Steine4635952011-07-04 08:58:31 +02001440 pci_enable_msi(pdev);
1441
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09001442 iobase = pci_resource_start(pdev, 0);
1443 mapbase = pci_resource_start(pdev, 1);
1444 priv->mapbase = mapbase;
1445 priv->iobase = iobase;
1446 priv->pdev = pdev;
1447 priv->tx_empty = 1;
Tomoya MORINAGA1c518992010-12-16 16:13:29 +09001448 priv->rxbuf.buf = rxbuf;
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09001449 priv->rxbuf.size = PAGE_SIZE;
1450
1451 priv->fifo_size = fifosize;
1452 priv->base_baud = base_baud;
1453 priv->port_type = PORT_MAX_8250 + port_type + 1;
1454 priv->port.dev = &pdev->dev;
1455 priv->port.iobase = iobase;
1456 priv->port.membase = NULL;
1457 priv->port.mapbase = mapbase;
1458 priv->port.irq = pdev->irq;
1459 priv->port.iotype = UPIO_PORT;
1460 priv->port.ops = &pch_uart_ops;
1461 priv->port.flags = UPF_BOOT_AUTOCONF;
1462 priv->port.fifosize = fifosize;
Tomoya MORINAGAfec38d12011-02-23 10:03:19 +09001463 priv->port.line = board->line_no;
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09001464 priv->trigger = PCH_UART_HAL_TRIGGER_M;
1465
Tomoya MORINAGA7e461322011-02-23 10:03:13 +09001466 spin_lock_init(&priv->port.lock);
1467
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09001468 pci_set_drvdata(pdev, priv);
1469 pch_uart_hal_request(pdev, fifosize, base_baud);
Tomoya MORINAGA4564e1e2011-01-28 18:00:01 +09001470
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09001471 ret = uart_add_one_port(&pch_uart_driver, &priv->port);
1472 if (ret < 0)
1473 goto init_port_hal_free;
1474
1475 return priv;
1476
1477init_port_hal_free:
Tomoya MORINAGA1c518992010-12-16 16:13:29 +09001478 free_page((unsigned long)rxbuf);
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09001479init_port_free_txbuf:
1480 kfree(priv);
1481init_port_alloc_err:
1482
1483 return NULL;
1484}
1485
1486static void pch_uart_exit_port(struct eg20t_port *priv)
1487{
1488 uart_remove_one_port(&pch_uart_driver, &priv->port);
1489 pci_set_drvdata(priv->pdev, NULL);
Tomoya MORINAGA1c518992010-12-16 16:13:29 +09001490 free_page((unsigned long)priv->rxbuf.buf);
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09001491}
1492
1493static void pch_uart_pci_remove(struct pci_dev *pdev)
1494{
1495 struct eg20t_port *priv;
1496
1497 priv = (struct eg20t_port *)pci_get_drvdata(pdev);
Alexander Steine4635952011-07-04 08:58:31 +02001498
1499 pci_disable_msi(pdev);
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09001500 pch_uart_exit_port(priv);
1501 pci_disable_device(pdev);
1502 kfree(priv);
1503 return;
1504}
1505#ifdef CONFIG_PM
1506static int pch_uart_pci_suspend(struct pci_dev *pdev, pm_message_t state)
1507{
1508 struct eg20t_port *priv = pci_get_drvdata(pdev);
1509
1510 uart_suspend_port(&pch_uart_driver, &priv->port);
1511
1512 pci_save_state(pdev);
1513 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1514 return 0;
1515}
1516
1517static int pch_uart_pci_resume(struct pci_dev *pdev)
1518{
1519 struct eg20t_port *priv = pci_get_drvdata(pdev);
1520 int ret;
1521
1522 pci_set_power_state(pdev, PCI_D0);
1523 pci_restore_state(pdev);
1524
1525 ret = pci_enable_device(pdev);
1526 if (ret) {
1527 dev_err(&pdev->dev,
1528 "%s-pci_enable_device failed(ret=%d) ", __func__, ret);
1529 return ret;
1530 }
1531
1532 uart_resume_port(&pch_uart_driver, &priv->port);
1533
1534 return 0;
1535}
1536#else
1537#define pch_uart_pci_suspend NULL
1538#define pch_uart_pci_resume NULL
1539#endif
1540
1541static DEFINE_PCI_DEVICE_TABLE(pch_uart_pci_id) = {
1542 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8811),
Tomoya MORINAGAfec38d12011-02-23 10:03:19 +09001543 .driver_data = pch_et20t_uart0},
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09001544 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8812),
Tomoya MORINAGAfec38d12011-02-23 10:03:19 +09001545 .driver_data = pch_et20t_uart1},
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09001546 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8813),
Tomoya MORINAGAfec38d12011-02-23 10:03:19 +09001547 .driver_data = pch_et20t_uart2},
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09001548 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8814),
Tomoya MORINAGAfec38d12011-02-23 10:03:19 +09001549 .driver_data = pch_et20t_uart3},
Tomoya MORINAGA4564e1e2011-01-28 18:00:01 +09001550 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8027),
Tomoya MORINAGAfec38d12011-02-23 10:03:19 +09001551 .driver_data = pch_ml7213_uart0},
Tomoya MORINAGA4564e1e2011-01-28 18:00:01 +09001552 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8028),
Tomoya MORINAGAfec38d12011-02-23 10:03:19 +09001553 .driver_data = pch_ml7213_uart1},
Tomoya MORINAGA4564e1e2011-01-28 18:00:01 +09001554 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8029),
Tomoya MORINAGAfec38d12011-02-23 10:03:19 +09001555 .driver_data = pch_ml7213_uart2},
Tomoya MORINAGA177c2cb2011-05-09 17:25:20 +09001556 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800C),
1557 .driver_data = pch_ml7223_uart0},
1558 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800D),
1559 .driver_data = pch_ml7223_uart1},
Tomoya MORINAGA8249f742011-10-28 09:38:49 +09001560 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8811),
1561 .driver_data = pch_ml7831_uart0},
1562 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8812),
1563 .driver_data = pch_ml7831_uart1},
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09001564 {0,},
1565};
1566
1567static int __devinit pch_uart_pci_probe(struct pci_dev *pdev,
1568 const struct pci_device_id *id)
1569{
1570 int ret;
1571 struct eg20t_port *priv;
1572
1573 ret = pci_enable_device(pdev);
1574 if (ret < 0)
1575 goto probe_error;
1576
Tomoya MORINAGA4564e1e2011-01-28 18:00:01 +09001577 priv = pch_uart_init_port(pdev, id);
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09001578 if (!priv) {
1579 ret = -EBUSY;
1580 goto probe_disable_device;
1581 }
1582 pci_set_drvdata(pdev, priv);
1583
1584 return ret;
1585
1586probe_disable_device:
Alexander Steine4635952011-07-04 08:58:31 +02001587 pci_disable_msi(pdev);
Tomoya MORINAGA3c6a4832010-11-17 09:55:54 +09001588 pci_disable_device(pdev);
1589probe_error:
1590 return ret;
1591}
1592
1593static struct pci_driver pch_uart_pci_driver = {
1594 .name = "pch_uart",
1595 .id_table = pch_uart_pci_id,
1596 .probe = pch_uart_pci_probe,
1597 .remove = __devexit_p(pch_uart_pci_remove),
1598 .suspend = pch_uart_pci_suspend,
1599 .resume = pch_uart_pci_resume,
1600};
1601
1602static int __init pch_uart_module_init(void)
1603{
1604 int ret;
1605
1606 /* register as UART driver */
1607 ret = uart_register_driver(&pch_uart_driver);
1608 if (ret < 0)
1609 return ret;
1610
1611 /* register as PCI driver */
1612 ret = pci_register_driver(&pch_uart_pci_driver);
1613 if (ret < 0)
1614 uart_unregister_driver(&pch_uart_driver);
1615
1616 return ret;
1617}
1618module_init(pch_uart_module_init);
1619
1620static void __exit pch_uart_module_exit(void)
1621{
1622 pci_unregister_driver(&pch_uart_pci_driver);
1623 uart_unregister_driver(&pch_uart_driver);
1624}
1625module_exit(pch_uart_module_exit);
1626
1627MODULE_LICENSE("GPL v2");
1628MODULE_DESCRIPTION("Intel EG20T PCH UART PCI Driver");
1629module_param(default_baud, uint, S_IRUGO);