Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 1 | /* |
Paul Walmsley | 7359154 | 2010-02-22 22:09:32 -0700 | [diff] [blame] | 2 | * omap_hwmod_2420_data.c - hardware modules present on the OMAP2420 chips |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 3 | * |
Paul Walmsley | 78183f3 | 2011-07-09 19:14:05 -0600 | [diff] [blame] | 4 | * Copyright (C) 2009-2011 Nokia Corporation |
Paul Walmsley | 0a78c5c | 2012-04-19 04:04:31 -0600 | [diff] [blame] | 5 | * Copyright (C) 2012 Texas Instruments, Inc. |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 6 | * Paul Walmsley |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License version 2 as |
| 10 | * published by the Free Software Foundation. |
| 11 | * |
| 12 | * XXX handle crossbar/shared link difference for L3? |
Paul Walmsley | 7359154 | 2010-02-22 22:09:32 -0700 | [diff] [blame] | 13 | * XXX these should be marked initdata for multi-OMAP kernels |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 14 | */ |
Tony Lindgren | ce491cf | 2009-10-20 09:40:47 -0700 | [diff] [blame] | 15 | #include <plat/omap_hwmod.h> |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 16 | #include <mach/irqs.h> |
Tony Lindgren | ce491cf | 2009-10-20 09:40:47 -0700 | [diff] [blame] | 17 | #include <plat/cpu.h> |
| 18 | #include <plat/dma.h> |
Kevin Hilman | 046465b | 2010-09-27 20:19:30 +0530 | [diff] [blame] | 19 | #include <plat/serial.h> |
Paul Walmsley | 2004290 | 2010-09-30 02:40:12 +0530 | [diff] [blame] | 20 | #include <plat/i2c.h> |
Varadarajan, Charulatha | 59c348c | 2010-12-07 16:26:56 -0800 | [diff] [blame] | 21 | #include <plat/gpio.h> |
Charulatha V | 617871d | 2011-02-17 09:53:09 -0800 | [diff] [blame] | 22 | #include <plat/mcspi.h> |
Thara Gopinath | eddb126 | 2011-02-23 00:14:04 -0700 | [diff] [blame] | 23 | #include <plat/dmtimer.h> |
Senthilvadivu Guruswamy | 996746c | 2011-02-22 09:50:36 +0200 | [diff] [blame] | 24 | #include <plat/l3_2xxx.h> |
| 25 | #include <plat/l4_2xxx.h> |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 26 | |
Paul Walmsley | 43b4099 | 2010-02-22 22:09:34 -0700 | [diff] [blame] | 27 | #include "omap_hwmod_common_data.h" |
| 28 | |
Varadarajan, Charulatha | a714b9c | 2010-09-23 20:02:39 +0530 | [diff] [blame] | 29 | #include "cm-regbits-24xx.h" |
Paul Walmsley | 2004290 | 2010-09-30 02:40:12 +0530 | [diff] [blame] | 30 | #include "prm-regbits-24xx.h" |
Paul Walmsley | ff2516f | 2010-12-21 15:39:15 -0700 | [diff] [blame] | 31 | #include "wd_timer.h" |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 32 | |
Paul Walmsley | 7359154 | 2010-02-22 22:09:32 -0700 | [diff] [blame] | 33 | /* |
| 34 | * OMAP2420 hardware module integration data |
| 35 | * |
Paul Walmsley | 844a3b6 | 2012-04-19 04:04:33 -0600 | [diff] [blame^] | 36 | * All of the data in this section should be autogeneratable from the |
Paul Walmsley | 7359154 | 2010-02-22 22:09:32 -0700 | [diff] [blame] | 37 | * TI hardware database or other technical documentation. Data that |
| 38 | * is driver-specific or driver-kernel integration-specific belongs |
| 39 | * elsewhere. |
| 40 | */ |
| 41 | |
Paul Walmsley | 844a3b6 | 2012-04-19 04:04:33 -0600 | [diff] [blame^] | 42 | /* |
| 43 | * IP blocks |
| 44 | */ |
Senthilvadivu Guruswamy | 996746c | 2011-02-22 09:50:36 +0200 | [diff] [blame] | 45 | |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 46 | /* L3 */ |
Kevin Hilman | 4a7cf90 | 2010-07-26 16:34:32 -0600 | [diff] [blame] | 47 | static struct omap_hwmod omap2420_l3_main_hwmod = { |
Benoit Cousson | fa98347 | 2010-07-26 16:34:29 -0600 | [diff] [blame] | 48 | .name = "l3_main", |
Paul Walmsley | 43b4099 | 2010-02-22 22:09:34 -0700 | [diff] [blame] | 49 | .class = &l3_hwmod_class, |
Kevin Hilman | 2eb1875 | 2010-07-26 16:34:28 -0600 | [diff] [blame] | 50 | .flags = HWMOD_NO_IDLEST, |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 51 | }; |
| 52 | |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 53 | /* L4 CORE */ |
| 54 | static struct omap_hwmod omap2420_l4_core_hwmod = { |
Benoit Cousson | fa98347 | 2010-07-26 16:34:29 -0600 | [diff] [blame] | 55 | .name = "l4_core", |
Paul Walmsley | 43b4099 | 2010-02-22 22:09:34 -0700 | [diff] [blame] | 56 | .class = &l4_hwmod_class, |
Kevin Hilman | 2eb1875 | 2010-07-26 16:34:28 -0600 | [diff] [blame] | 57 | .flags = HWMOD_NO_IDLEST, |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 58 | }; |
| 59 | |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 60 | /* L4 WKUP */ |
| 61 | static struct omap_hwmod omap2420_l4_wkup_hwmod = { |
Benoit Cousson | fa98347 | 2010-07-26 16:34:29 -0600 | [diff] [blame] | 62 | .name = "l4_wkup", |
Paul Walmsley | 43b4099 | 2010-02-22 22:09:34 -0700 | [diff] [blame] | 63 | .class = &l4_hwmod_class, |
Kevin Hilman | 2eb1875 | 2010-07-26 16:34:28 -0600 | [diff] [blame] | 64 | .flags = HWMOD_NO_IDLEST, |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 65 | }; |
| 66 | |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 67 | /* MPU */ |
| 68 | static struct omap_hwmod omap2420_mpu_hwmod = { |
Benoit Cousson | 5c2c029 | 2010-05-20 12:31:10 -0600 | [diff] [blame] | 69 | .name = "mpu", |
Paul Walmsley | 43b4099 | 2010-02-22 22:09:34 -0700 | [diff] [blame] | 70 | .class = &mpu_hwmod_class, |
Paul Walmsley | 50ebdac | 2010-02-22 22:09:31 -0700 | [diff] [blame] | 71 | .main_clk = "mpu_ck", |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 72 | }; |
| 73 | |
Paul Walmsley | 844a3b6 | 2012-04-19 04:04:33 -0600 | [diff] [blame^] | 74 | /* IVA2 (IVA2) */ |
Paul Walmsley | 08072ac | 2010-07-26 16:34:33 -0600 | [diff] [blame] | 75 | static struct omap_hwmod omap2420_iva_hwmod = { |
| 76 | .name = "iva", |
| 77 | .class = &iva_hwmod_class, |
Paul Walmsley | 08072ac | 2010-07-26 16:34:33 -0600 | [diff] [blame] | 78 | }; |
| 79 | |
Tarun Kanti DebBarma | c345c8b | 2011-09-20 17:00:18 +0530 | [diff] [blame] | 80 | /* always-on timers dev attribute */ |
| 81 | static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = { |
Paul Walmsley | 844a3b6 | 2012-04-19 04:04:33 -0600 | [diff] [blame^] | 82 | .timer_capability = OMAP_TIMER_ALWON, |
Tarun Kanti DebBarma | c345c8b | 2011-09-20 17:00:18 +0530 | [diff] [blame] | 83 | }; |
| 84 | |
| 85 | /* pwm timers dev attribute */ |
| 86 | static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = { |
Paul Walmsley | 844a3b6 | 2012-04-19 04:04:33 -0600 | [diff] [blame^] | 87 | .timer_capability = OMAP_TIMER_HAS_PWM, |
Tarun Kanti DebBarma | c345c8b | 2011-09-20 17:00:18 +0530 | [diff] [blame] | 88 | }; |
| 89 | |
Thara Gopinath | eddb126 | 2011-02-23 00:14:04 -0700 | [diff] [blame] | 90 | /* timer1 */ |
Thara Gopinath | eddb126 | 2011-02-23 00:14:04 -0700 | [diff] [blame] | 91 | static struct omap_hwmod omap2420_timer1_hwmod = { |
| 92 | .name = "timer1", |
Paul Walmsley | 0d619a8 | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 93 | .mpu_irqs = omap2_timer1_mpu_irqs, |
Thara Gopinath | eddb126 | 2011-02-23 00:14:04 -0700 | [diff] [blame] | 94 | .main_clk = "gpt1_fck", |
| 95 | .prcm = { |
| 96 | .omap2 = { |
| 97 | .prcm_reg_id = 1, |
| 98 | .module_bit = OMAP24XX_EN_GPT1_SHIFT, |
| 99 | .module_offs = WKUP_MOD, |
| 100 | .idlest_reg_id = 1, |
| 101 | .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT, |
| 102 | }, |
| 103 | }, |
Tarun Kanti DebBarma | c345c8b | 2011-09-20 17:00:18 +0530 | [diff] [blame] | 104 | .dev_attr = &capability_alwon_dev_attr, |
Paul Walmsley | 273b946 | 2011-07-09 19:14:08 -0600 | [diff] [blame] | 105 | .class = &omap2xxx_timer_hwmod_class, |
Thara Gopinath | eddb126 | 2011-02-23 00:14:04 -0700 | [diff] [blame] | 106 | }; |
| 107 | |
| 108 | /* timer2 */ |
Thara Gopinath | eddb126 | 2011-02-23 00:14:04 -0700 | [diff] [blame] | 109 | static struct omap_hwmod omap2420_timer2_hwmod = { |
| 110 | .name = "timer2", |
Paul Walmsley | 0d619a8 | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 111 | .mpu_irqs = omap2_timer2_mpu_irqs, |
Thara Gopinath | eddb126 | 2011-02-23 00:14:04 -0700 | [diff] [blame] | 112 | .main_clk = "gpt2_fck", |
| 113 | .prcm = { |
| 114 | .omap2 = { |
| 115 | .prcm_reg_id = 1, |
| 116 | .module_bit = OMAP24XX_EN_GPT2_SHIFT, |
| 117 | .module_offs = CORE_MOD, |
| 118 | .idlest_reg_id = 1, |
| 119 | .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT, |
| 120 | }, |
| 121 | }, |
Tarun Kanti DebBarma | c345c8b | 2011-09-20 17:00:18 +0530 | [diff] [blame] | 122 | .dev_attr = &capability_alwon_dev_attr, |
Paul Walmsley | 273b946 | 2011-07-09 19:14:08 -0600 | [diff] [blame] | 123 | .class = &omap2xxx_timer_hwmod_class, |
Thara Gopinath | eddb126 | 2011-02-23 00:14:04 -0700 | [diff] [blame] | 124 | }; |
| 125 | |
| 126 | /* timer3 */ |
Thara Gopinath | eddb126 | 2011-02-23 00:14:04 -0700 | [diff] [blame] | 127 | static struct omap_hwmod omap2420_timer3_hwmod = { |
| 128 | .name = "timer3", |
Paul Walmsley | 0d619a8 | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 129 | .mpu_irqs = omap2_timer3_mpu_irqs, |
Thara Gopinath | eddb126 | 2011-02-23 00:14:04 -0700 | [diff] [blame] | 130 | .main_clk = "gpt3_fck", |
| 131 | .prcm = { |
| 132 | .omap2 = { |
| 133 | .prcm_reg_id = 1, |
| 134 | .module_bit = OMAP24XX_EN_GPT3_SHIFT, |
| 135 | .module_offs = CORE_MOD, |
| 136 | .idlest_reg_id = 1, |
| 137 | .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT, |
| 138 | }, |
| 139 | }, |
Tarun Kanti DebBarma | c345c8b | 2011-09-20 17:00:18 +0530 | [diff] [blame] | 140 | .dev_attr = &capability_alwon_dev_attr, |
Paul Walmsley | 273b946 | 2011-07-09 19:14:08 -0600 | [diff] [blame] | 141 | .class = &omap2xxx_timer_hwmod_class, |
Thara Gopinath | eddb126 | 2011-02-23 00:14:04 -0700 | [diff] [blame] | 142 | }; |
| 143 | |
| 144 | /* timer4 */ |
Thara Gopinath | eddb126 | 2011-02-23 00:14:04 -0700 | [diff] [blame] | 145 | static struct omap_hwmod omap2420_timer4_hwmod = { |
| 146 | .name = "timer4", |
Paul Walmsley | 0d619a8 | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 147 | .mpu_irqs = omap2_timer4_mpu_irqs, |
Thara Gopinath | eddb126 | 2011-02-23 00:14:04 -0700 | [diff] [blame] | 148 | .main_clk = "gpt4_fck", |
| 149 | .prcm = { |
| 150 | .omap2 = { |
| 151 | .prcm_reg_id = 1, |
| 152 | .module_bit = OMAP24XX_EN_GPT4_SHIFT, |
| 153 | .module_offs = CORE_MOD, |
| 154 | .idlest_reg_id = 1, |
| 155 | .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT, |
| 156 | }, |
| 157 | }, |
Tarun Kanti DebBarma | c345c8b | 2011-09-20 17:00:18 +0530 | [diff] [blame] | 158 | .dev_attr = &capability_alwon_dev_attr, |
Paul Walmsley | 273b946 | 2011-07-09 19:14:08 -0600 | [diff] [blame] | 159 | .class = &omap2xxx_timer_hwmod_class, |
Thara Gopinath | eddb126 | 2011-02-23 00:14:04 -0700 | [diff] [blame] | 160 | }; |
| 161 | |
| 162 | /* timer5 */ |
Thara Gopinath | eddb126 | 2011-02-23 00:14:04 -0700 | [diff] [blame] | 163 | static struct omap_hwmod omap2420_timer5_hwmod = { |
| 164 | .name = "timer5", |
Paul Walmsley | 0d619a8 | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 165 | .mpu_irqs = omap2_timer5_mpu_irqs, |
Thara Gopinath | eddb126 | 2011-02-23 00:14:04 -0700 | [diff] [blame] | 166 | .main_clk = "gpt5_fck", |
| 167 | .prcm = { |
| 168 | .omap2 = { |
| 169 | .prcm_reg_id = 1, |
| 170 | .module_bit = OMAP24XX_EN_GPT5_SHIFT, |
| 171 | .module_offs = CORE_MOD, |
| 172 | .idlest_reg_id = 1, |
| 173 | .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT, |
| 174 | }, |
| 175 | }, |
Tarun Kanti DebBarma | c345c8b | 2011-09-20 17:00:18 +0530 | [diff] [blame] | 176 | .dev_attr = &capability_alwon_dev_attr, |
Paul Walmsley | 273b946 | 2011-07-09 19:14:08 -0600 | [diff] [blame] | 177 | .class = &omap2xxx_timer_hwmod_class, |
Thara Gopinath | eddb126 | 2011-02-23 00:14:04 -0700 | [diff] [blame] | 178 | }; |
| 179 | |
Thara Gopinath | eddb126 | 2011-02-23 00:14:04 -0700 | [diff] [blame] | 180 | /* timer6 */ |
Thara Gopinath | eddb126 | 2011-02-23 00:14:04 -0700 | [diff] [blame] | 181 | static struct omap_hwmod omap2420_timer6_hwmod = { |
| 182 | .name = "timer6", |
Paul Walmsley | 0d619a8 | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 183 | .mpu_irqs = omap2_timer6_mpu_irqs, |
Thara Gopinath | eddb126 | 2011-02-23 00:14:04 -0700 | [diff] [blame] | 184 | .main_clk = "gpt6_fck", |
| 185 | .prcm = { |
| 186 | .omap2 = { |
| 187 | .prcm_reg_id = 1, |
| 188 | .module_bit = OMAP24XX_EN_GPT6_SHIFT, |
| 189 | .module_offs = CORE_MOD, |
| 190 | .idlest_reg_id = 1, |
| 191 | .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT, |
| 192 | }, |
| 193 | }, |
Tarun Kanti DebBarma | c345c8b | 2011-09-20 17:00:18 +0530 | [diff] [blame] | 194 | .dev_attr = &capability_alwon_dev_attr, |
Paul Walmsley | 273b946 | 2011-07-09 19:14:08 -0600 | [diff] [blame] | 195 | .class = &omap2xxx_timer_hwmod_class, |
Thara Gopinath | eddb126 | 2011-02-23 00:14:04 -0700 | [diff] [blame] | 196 | }; |
| 197 | |
| 198 | /* timer7 */ |
Thara Gopinath | eddb126 | 2011-02-23 00:14:04 -0700 | [diff] [blame] | 199 | static struct omap_hwmod omap2420_timer7_hwmod = { |
| 200 | .name = "timer7", |
Paul Walmsley | 0d619a8 | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 201 | .mpu_irqs = omap2_timer7_mpu_irqs, |
Thara Gopinath | eddb126 | 2011-02-23 00:14:04 -0700 | [diff] [blame] | 202 | .main_clk = "gpt7_fck", |
| 203 | .prcm = { |
| 204 | .omap2 = { |
| 205 | .prcm_reg_id = 1, |
| 206 | .module_bit = OMAP24XX_EN_GPT7_SHIFT, |
| 207 | .module_offs = CORE_MOD, |
| 208 | .idlest_reg_id = 1, |
| 209 | .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT, |
| 210 | }, |
| 211 | }, |
Tarun Kanti DebBarma | c345c8b | 2011-09-20 17:00:18 +0530 | [diff] [blame] | 212 | .dev_attr = &capability_alwon_dev_attr, |
Paul Walmsley | 273b946 | 2011-07-09 19:14:08 -0600 | [diff] [blame] | 213 | .class = &omap2xxx_timer_hwmod_class, |
Thara Gopinath | eddb126 | 2011-02-23 00:14:04 -0700 | [diff] [blame] | 214 | }; |
| 215 | |
| 216 | /* timer8 */ |
Thara Gopinath | eddb126 | 2011-02-23 00:14:04 -0700 | [diff] [blame] | 217 | static struct omap_hwmod omap2420_timer8_hwmod = { |
| 218 | .name = "timer8", |
Paul Walmsley | 0d619a8 | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 219 | .mpu_irqs = omap2_timer8_mpu_irqs, |
Thara Gopinath | eddb126 | 2011-02-23 00:14:04 -0700 | [diff] [blame] | 220 | .main_clk = "gpt8_fck", |
| 221 | .prcm = { |
| 222 | .omap2 = { |
| 223 | .prcm_reg_id = 1, |
| 224 | .module_bit = OMAP24XX_EN_GPT8_SHIFT, |
| 225 | .module_offs = CORE_MOD, |
| 226 | .idlest_reg_id = 1, |
| 227 | .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT, |
| 228 | }, |
| 229 | }, |
Tarun Kanti DebBarma | c345c8b | 2011-09-20 17:00:18 +0530 | [diff] [blame] | 230 | .dev_attr = &capability_alwon_dev_attr, |
Paul Walmsley | 273b946 | 2011-07-09 19:14:08 -0600 | [diff] [blame] | 231 | .class = &omap2xxx_timer_hwmod_class, |
Thara Gopinath | eddb126 | 2011-02-23 00:14:04 -0700 | [diff] [blame] | 232 | }; |
| 233 | |
| 234 | /* timer9 */ |
Thara Gopinath | eddb126 | 2011-02-23 00:14:04 -0700 | [diff] [blame] | 235 | static struct omap_hwmod omap2420_timer9_hwmod = { |
| 236 | .name = "timer9", |
Paul Walmsley | 0d619a8 | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 237 | .mpu_irqs = omap2_timer9_mpu_irqs, |
Thara Gopinath | eddb126 | 2011-02-23 00:14:04 -0700 | [diff] [blame] | 238 | .main_clk = "gpt9_fck", |
| 239 | .prcm = { |
| 240 | .omap2 = { |
| 241 | .prcm_reg_id = 1, |
| 242 | .module_bit = OMAP24XX_EN_GPT9_SHIFT, |
| 243 | .module_offs = CORE_MOD, |
| 244 | .idlest_reg_id = 1, |
| 245 | .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT, |
| 246 | }, |
| 247 | }, |
Tarun Kanti DebBarma | c345c8b | 2011-09-20 17:00:18 +0530 | [diff] [blame] | 248 | .dev_attr = &capability_pwm_dev_attr, |
Paul Walmsley | 273b946 | 2011-07-09 19:14:08 -0600 | [diff] [blame] | 249 | .class = &omap2xxx_timer_hwmod_class, |
Thara Gopinath | eddb126 | 2011-02-23 00:14:04 -0700 | [diff] [blame] | 250 | }; |
| 251 | |
| 252 | /* timer10 */ |
Thara Gopinath | eddb126 | 2011-02-23 00:14:04 -0700 | [diff] [blame] | 253 | static struct omap_hwmod omap2420_timer10_hwmod = { |
| 254 | .name = "timer10", |
Paul Walmsley | 0d619a8 | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 255 | .mpu_irqs = omap2_timer10_mpu_irqs, |
Thara Gopinath | eddb126 | 2011-02-23 00:14:04 -0700 | [diff] [blame] | 256 | .main_clk = "gpt10_fck", |
| 257 | .prcm = { |
| 258 | .omap2 = { |
| 259 | .prcm_reg_id = 1, |
| 260 | .module_bit = OMAP24XX_EN_GPT10_SHIFT, |
| 261 | .module_offs = CORE_MOD, |
| 262 | .idlest_reg_id = 1, |
| 263 | .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT, |
| 264 | }, |
| 265 | }, |
Tarun Kanti DebBarma | c345c8b | 2011-09-20 17:00:18 +0530 | [diff] [blame] | 266 | .dev_attr = &capability_pwm_dev_attr, |
Paul Walmsley | 273b946 | 2011-07-09 19:14:08 -0600 | [diff] [blame] | 267 | .class = &omap2xxx_timer_hwmod_class, |
Thara Gopinath | eddb126 | 2011-02-23 00:14:04 -0700 | [diff] [blame] | 268 | }; |
| 269 | |
| 270 | /* timer11 */ |
Thara Gopinath | eddb126 | 2011-02-23 00:14:04 -0700 | [diff] [blame] | 271 | static struct omap_hwmod omap2420_timer11_hwmod = { |
| 272 | .name = "timer11", |
Paul Walmsley | 0d619a8 | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 273 | .mpu_irqs = omap2_timer11_mpu_irqs, |
Thara Gopinath | eddb126 | 2011-02-23 00:14:04 -0700 | [diff] [blame] | 274 | .main_clk = "gpt11_fck", |
| 275 | .prcm = { |
| 276 | .omap2 = { |
| 277 | .prcm_reg_id = 1, |
| 278 | .module_bit = OMAP24XX_EN_GPT11_SHIFT, |
| 279 | .module_offs = CORE_MOD, |
| 280 | .idlest_reg_id = 1, |
| 281 | .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT, |
| 282 | }, |
| 283 | }, |
Tarun Kanti DebBarma | c345c8b | 2011-09-20 17:00:18 +0530 | [diff] [blame] | 284 | .dev_attr = &capability_pwm_dev_attr, |
Paul Walmsley | 273b946 | 2011-07-09 19:14:08 -0600 | [diff] [blame] | 285 | .class = &omap2xxx_timer_hwmod_class, |
Thara Gopinath | eddb126 | 2011-02-23 00:14:04 -0700 | [diff] [blame] | 286 | }; |
| 287 | |
| 288 | /* timer12 */ |
Thara Gopinath | eddb126 | 2011-02-23 00:14:04 -0700 | [diff] [blame] | 289 | static struct omap_hwmod omap2420_timer12_hwmod = { |
| 290 | .name = "timer12", |
Paul Walmsley | 0d619a8 | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 291 | .mpu_irqs = omap2xxx_timer12_mpu_irqs, |
Thara Gopinath | eddb126 | 2011-02-23 00:14:04 -0700 | [diff] [blame] | 292 | .main_clk = "gpt12_fck", |
| 293 | .prcm = { |
| 294 | .omap2 = { |
| 295 | .prcm_reg_id = 1, |
| 296 | .module_bit = OMAP24XX_EN_GPT12_SHIFT, |
| 297 | .module_offs = CORE_MOD, |
| 298 | .idlest_reg_id = 1, |
| 299 | .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT, |
| 300 | }, |
| 301 | }, |
Tarun Kanti DebBarma | c345c8b | 2011-09-20 17:00:18 +0530 | [diff] [blame] | 302 | .dev_attr = &capability_pwm_dev_attr, |
Paul Walmsley | 273b946 | 2011-07-09 19:14:08 -0600 | [diff] [blame] | 303 | .class = &omap2xxx_timer_hwmod_class, |
Thara Gopinath | eddb126 | 2011-02-23 00:14:04 -0700 | [diff] [blame] | 304 | }; |
| 305 | |
Varadarajan, Charulatha | a714b9c | 2010-09-23 20:02:39 +0530 | [diff] [blame] | 306 | static struct omap_hwmod omap2420_wd_timer2_hwmod = { |
| 307 | .name = "wd_timer2", |
Paul Walmsley | 273b946 | 2011-07-09 19:14:08 -0600 | [diff] [blame] | 308 | .class = &omap2xxx_wd_timer_hwmod_class, |
Varadarajan, Charulatha | a714b9c | 2010-09-23 20:02:39 +0530 | [diff] [blame] | 309 | .main_clk = "mpu_wdt_fck", |
| 310 | .prcm = { |
| 311 | .omap2 = { |
| 312 | .prcm_reg_id = 1, |
| 313 | .module_bit = OMAP24XX_EN_MPU_WDT_SHIFT, |
| 314 | .module_offs = WKUP_MOD, |
| 315 | .idlest_reg_id = 1, |
| 316 | .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT, |
| 317 | }, |
| 318 | }, |
Varadarajan, Charulatha | a714b9c | 2010-09-23 20:02:39 +0530 | [diff] [blame] | 319 | }; |
| 320 | |
Kevin Hilman | 046465b | 2010-09-27 20:19:30 +0530 | [diff] [blame] | 321 | /* UART1 */ |
Kevin Hilman | 046465b | 2010-09-27 20:19:30 +0530 | [diff] [blame] | 322 | static struct omap_hwmod omap2420_uart1_hwmod = { |
| 323 | .name = "uart1", |
Paul Walmsley | 0d619a8 | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 324 | .mpu_irqs = omap2_uart1_mpu_irqs, |
Paul Walmsley | d826ebf | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 325 | .sdma_reqs = omap2_uart1_sdma_reqs, |
Kevin Hilman | 046465b | 2010-09-27 20:19:30 +0530 | [diff] [blame] | 326 | .main_clk = "uart1_fck", |
| 327 | .prcm = { |
| 328 | .omap2 = { |
| 329 | .module_offs = CORE_MOD, |
| 330 | .prcm_reg_id = 1, |
| 331 | .module_bit = OMAP24XX_EN_UART1_SHIFT, |
| 332 | .idlest_reg_id = 1, |
| 333 | .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT, |
| 334 | }, |
| 335 | }, |
Paul Walmsley | 273b946 | 2011-07-09 19:14:08 -0600 | [diff] [blame] | 336 | .class = &omap2_uart_class, |
Kevin Hilman | 046465b | 2010-09-27 20:19:30 +0530 | [diff] [blame] | 337 | }; |
| 338 | |
| 339 | /* UART2 */ |
Kevin Hilman | 046465b | 2010-09-27 20:19:30 +0530 | [diff] [blame] | 340 | static struct omap_hwmod omap2420_uart2_hwmod = { |
| 341 | .name = "uart2", |
Paul Walmsley | 0d619a8 | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 342 | .mpu_irqs = omap2_uart2_mpu_irqs, |
Paul Walmsley | d826ebf | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 343 | .sdma_reqs = omap2_uart2_sdma_reqs, |
Kevin Hilman | 046465b | 2010-09-27 20:19:30 +0530 | [diff] [blame] | 344 | .main_clk = "uart2_fck", |
| 345 | .prcm = { |
| 346 | .omap2 = { |
| 347 | .module_offs = CORE_MOD, |
| 348 | .prcm_reg_id = 1, |
| 349 | .module_bit = OMAP24XX_EN_UART2_SHIFT, |
| 350 | .idlest_reg_id = 1, |
| 351 | .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT, |
| 352 | }, |
| 353 | }, |
Paul Walmsley | 273b946 | 2011-07-09 19:14:08 -0600 | [diff] [blame] | 354 | .class = &omap2_uart_class, |
Kevin Hilman | 046465b | 2010-09-27 20:19:30 +0530 | [diff] [blame] | 355 | }; |
| 356 | |
| 357 | /* UART3 */ |
Kevin Hilman | 046465b | 2010-09-27 20:19:30 +0530 | [diff] [blame] | 358 | static struct omap_hwmod omap2420_uart3_hwmod = { |
| 359 | .name = "uart3", |
Paul Walmsley | 0d619a8 | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 360 | .mpu_irqs = omap2_uart3_mpu_irqs, |
Paul Walmsley | d826ebf | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 361 | .sdma_reqs = omap2_uart3_sdma_reqs, |
Kevin Hilman | 046465b | 2010-09-27 20:19:30 +0530 | [diff] [blame] | 362 | .main_clk = "uart3_fck", |
| 363 | .prcm = { |
| 364 | .omap2 = { |
| 365 | .module_offs = CORE_MOD, |
| 366 | .prcm_reg_id = 2, |
| 367 | .module_bit = OMAP24XX_EN_UART3_SHIFT, |
| 368 | .idlest_reg_id = 2, |
| 369 | .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT, |
| 370 | }, |
| 371 | }, |
Paul Walmsley | 273b946 | 2011-07-09 19:14:08 -0600 | [diff] [blame] | 372 | .class = &omap2_uart_class, |
Kevin Hilman | 046465b | 2010-09-27 20:19:30 +0530 | [diff] [blame] | 373 | }; |
| 374 | |
Senthilvadivu Guruswamy | 996746c | 2011-02-22 09:50:36 +0200 | [diff] [blame] | 375 | /* dss */ |
Senthilvadivu Guruswamy | 996746c | 2011-02-22 09:50:36 +0200 | [diff] [blame] | 376 | |
Senthilvadivu Guruswamy | 996746c | 2011-02-22 09:50:36 +0200 | [diff] [blame] | 377 | static struct omap_hwmod_opt_clk dss_opt_clks[] = { |
Tomi Valkeinen | 1258ea5 | 2011-11-08 03:16:09 -0700 | [diff] [blame] | 378 | /* |
| 379 | * The DSS HW needs all DSS clocks enabled during reset. The dss_core |
| 380 | * driver does not use these clocks. |
| 381 | */ |
Senthilvadivu Guruswamy | 996746c | 2011-02-22 09:50:36 +0200 | [diff] [blame] | 382 | { .role = "tv_clk", .clk = "dss_54m_fck" }, |
| 383 | { .role = "sys_clk", .clk = "dss2_fck" }, |
| 384 | }; |
| 385 | |
| 386 | static struct omap_hwmod omap2420_dss_core_hwmod = { |
| 387 | .name = "dss_core", |
Paul Walmsley | 273b946 | 2011-07-09 19:14:08 -0600 | [diff] [blame] | 388 | .class = &omap2_dss_hwmod_class, |
Senthilvadivu Guruswamy | 996746c | 2011-02-22 09:50:36 +0200 | [diff] [blame] | 389 | .main_clk = "dss1_fck", /* instead of dss_fck */ |
Paul Walmsley | d826ebf | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 390 | .sdma_reqs = omap2xxx_dss_sdma_chs, |
Senthilvadivu Guruswamy | 996746c | 2011-02-22 09:50:36 +0200 | [diff] [blame] | 391 | .prcm = { |
| 392 | .omap2 = { |
| 393 | .prcm_reg_id = 1, |
| 394 | .module_bit = OMAP24XX_EN_DSS1_SHIFT, |
| 395 | .module_offs = CORE_MOD, |
| 396 | .idlest_reg_id = 1, |
| 397 | .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT, |
| 398 | }, |
| 399 | }, |
| 400 | .opt_clks = dss_opt_clks, |
| 401 | .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), |
Tomi Valkeinen | 1258ea5 | 2011-11-08 03:16:09 -0700 | [diff] [blame] | 402 | .flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
Senthilvadivu Guruswamy | 996746c | 2011-02-22 09:50:36 +0200 | [diff] [blame] | 403 | }; |
| 404 | |
Senthilvadivu Guruswamy | 996746c | 2011-02-22 09:50:36 +0200 | [diff] [blame] | 405 | static struct omap_hwmod omap2420_dss_dispc_hwmod = { |
| 406 | .name = "dss_dispc", |
Paul Walmsley | 273b946 | 2011-07-09 19:14:08 -0600 | [diff] [blame] | 407 | .class = &omap2_dispc_hwmod_class, |
Paul Walmsley | 0d619a8 | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 408 | .mpu_irqs = omap2_dispc_irqs, |
Senthilvadivu Guruswamy | 996746c | 2011-02-22 09:50:36 +0200 | [diff] [blame] | 409 | .main_clk = "dss1_fck", |
| 410 | .prcm = { |
| 411 | .omap2 = { |
| 412 | .prcm_reg_id = 1, |
| 413 | .module_bit = OMAP24XX_EN_DSS1_SHIFT, |
| 414 | .module_offs = CORE_MOD, |
| 415 | .idlest_reg_id = 1, |
| 416 | .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT, |
| 417 | }, |
| 418 | }, |
Senthilvadivu Guruswamy | 996746c | 2011-02-22 09:50:36 +0200 | [diff] [blame] | 419 | .flags = HWMOD_NO_IDLEST, |
Archit Taneja | b923d40 | 2011-10-06 18:04:08 -0600 | [diff] [blame] | 420 | .dev_attr = &omap2_3_dss_dispc_dev_attr |
Senthilvadivu Guruswamy | 996746c | 2011-02-22 09:50:36 +0200 | [diff] [blame] | 421 | }; |
| 422 | |
Tomi Valkeinen | b8ac10d | 2011-11-08 03:16:09 -0700 | [diff] [blame] | 423 | static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = { |
| 424 | { .role = "ick", .clk = "dss_ick" }, |
| 425 | }; |
| 426 | |
Senthilvadivu Guruswamy | 996746c | 2011-02-22 09:50:36 +0200 | [diff] [blame] | 427 | static struct omap_hwmod omap2420_dss_rfbi_hwmod = { |
| 428 | .name = "dss_rfbi", |
Paul Walmsley | 273b946 | 2011-07-09 19:14:08 -0600 | [diff] [blame] | 429 | .class = &omap2_rfbi_hwmod_class, |
Senthilvadivu Guruswamy | 996746c | 2011-02-22 09:50:36 +0200 | [diff] [blame] | 430 | .main_clk = "dss1_fck", |
| 431 | .prcm = { |
| 432 | .omap2 = { |
| 433 | .prcm_reg_id = 1, |
| 434 | .module_bit = OMAP24XX_EN_DSS1_SHIFT, |
| 435 | .module_offs = CORE_MOD, |
| 436 | }, |
| 437 | }, |
Tomi Valkeinen | b8ac10d | 2011-11-08 03:16:09 -0700 | [diff] [blame] | 438 | .opt_clks = dss_rfbi_opt_clks, |
| 439 | .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks), |
Senthilvadivu Guruswamy | 996746c | 2011-02-22 09:50:36 +0200 | [diff] [blame] | 440 | .flags = HWMOD_NO_IDLEST, |
| 441 | }; |
| 442 | |
Senthilvadivu Guruswamy | 996746c | 2011-02-22 09:50:36 +0200 | [diff] [blame] | 443 | static struct omap_hwmod omap2420_dss_venc_hwmod = { |
| 444 | .name = "dss_venc", |
Paul Walmsley | 273b946 | 2011-07-09 19:14:08 -0600 | [diff] [blame] | 445 | .class = &omap2_venc_hwmod_class, |
Tomi Valkeinen | b8ac10d | 2011-11-08 03:16:09 -0700 | [diff] [blame] | 446 | .main_clk = "dss_54m_fck", |
Senthilvadivu Guruswamy | 996746c | 2011-02-22 09:50:36 +0200 | [diff] [blame] | 447 | .prcm = { |
| 448 | .omap2 = { |
| 449 | .prcm_reg_id = 1, |
| 450 | .module_bit = OMAP24XX_EN_DSS1_SHIFT, |
| 451 | .module_offs = CORE_MOD, |
| 452 | }, |
| 453 | }, |
Senthilvadivu Guruswamy | 996746c | 2011-02-22 09:50:36 +0200 | [diff] [blame] | 454 | .flags = HWMOD_NO_IDLEST, |
| 455 | }; |
| 456 | |
Paul Walmsley | 2004290 | 2010-09-30 02:40:12 +0530 | [diff] [blame] | 457 | /* I2C common */ |
| 458 | static struct omap_hwmod_class_sysconfig i2c_sysc = { |
| 459 | .rev_offs = 0x00, |
| 460 | .sysc_offs = 0x20, |
| 461 | .syss_offs = 0x10, |
Avinash.H.M | d73d65f | 2011-03-03 14:22:46 -0700 | [diff] [blame] | 462 | .sysc_flags = (SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), |
Paul Walmsley | 2004290 | 2010-09-30 02:40:12 +0530 | [diff] [blame] | 463 | .sysc_fields = &omap_hwmod_sysc_type1, |
| 464 | }; |
| 465 | |
| 466 | static struct omap_hwmod_class i2c_class = { |
| 467 | .name = "i2c", |
| 468 | .sysc = &i2c_sysc, |
Andy Green | db791a7 | 2011-07-10 05:27:15 -0600 | [diff] [blame] | 469 | .rev = OMAP_I2C_IP_VERSION_1, |
Avinash.H.M | 6d3c55f | 2011-07-10 05:27:16 -0600 | [diff] [blame] | 470 | .reset = &omap_i2c_reset, |
Paul Walmsley | 2004290 | 2010-09-30 02:40:12 +0530 | [diff] [blame] | 471 | }; |
| 472 | |
Andy Green | 4d4441a | 2011-07-10 05:27:16 -0600 | [diff] [blame] | 473 | static struct omap_i2c_dev_attr i2c_dev_attr = { |
| 474 | .flags = OMAP_I2C_FLAG_NO_FIFO | |
| 475 | OMAP_I2C_FLAG_SIMPLE_CLOCK | |
| 476 | OMAP_I2C_FLAG_16BIT_DATA_REG | |
| 477 | OMAP_I2C_FLAG_BUS_SHIFT_2, |
| 478 | }; |
Paul Walmsley | 2004290 | 2010-09-30 02:40:12 +0530 | [diff] [blame] | 479 | |
| 480 | /* I2C1 */ |
Paul Walmsley | 2004290 | 2010-09-30 02:40:12 +0530 | [diff] [blame] | 481 | static struct omap_hwmod omap2420_i2c1_hwmod = { |
| 482 | .name = "i2c1", |
Paul Walmsley | 0d619a8 | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 483 | .mpu_irqs = omap2_i2c1_mpu_irqs, |
Paul Walmsley | d826ebf | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 484 | .sdma_reqs = omap2_i2c1_sdma_reqs, |
Paul Walmsley | 2004290 | 2010-09-30 02:40:12 +0530 | [diff] [blame] | 485 | .main_clk = "i2c1_fck", |
| 486 | .prcm = { |
| 487 | .omap2 = { |
| 488 | .module_offs = CORE_MOD, |
| 489 | .prcm_reg_id = 1, |
| 490 | .module_bit = OMAP2420_EN_I2C1_SHIFT, |
| 491 | .idlest_reg_id = 1, |
| 492 | .idlest_idle_bit = OMAP2420_ST_I2C1_SHIFT, |
| 493 | }, |
| 494 | }, |
Paul Walmsley | 2004290 | 2010-09-30 02:40:12 +0530 | [diff] [blame] | 495 | .class = &i2c_class, |
| 496 | .dev_attr = &i2c_dev_attr, |
Paul Walmsley | 2004290 | 2010-09-30 02:40:12 +0530 | [diff] [blame] | 497 | .flags = HWMOD_16BIT_REG, |
| 498 | }; |
| 499 | |
| 500 | /* I2C2 */ |
Paul Walmsley | 2004290 | 2010-09-30 02:40:12 +0530 | [diff] [blame] | 501 | static struct omap_hwmod omap2420_i2c2_hwmod = { |
| 502 | .name = "i2c2", |
Paul Walmsley | 0d619a8 | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 503 | .mpu_irqs = omap2_i2c2_mpu_irqs, |
Paul Walmsley | d826ebf | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 504 | .sdma_reqs = omap2_i2c2_sdma_reqs, |
Paul Walmsley | 2004290 | 2010-09-30 02:40:12 +0530 | [diff] [blame] | 505 | .main_clk = "i2c2_fck", |
| 506 | .prcm = { |
| 507 | .omap2 = { |
| 508 | .module_offs = CORE_MOD, |
| 509 | .prcm_reg_id = 1, |
| 510 | .module_bit = OMAP2420_EN_I2C2_SHIFT, |
| 511 | .idlest_reg_id = 1, |
| 512 | .idlest_idle_bit = OMAP2420_ST_I2C2_SHIFT, |
| 513 | }, |
| 514 | }, |
Paul Walmsley | 2004290 | 2010-09-30 02:40:12 +0530 | [diff] [blame] | 515 | .class = &i2c_class, |
| 516 | .dev_attr = &i2c_dev_attr, |
Paul Walmsley | 2004290 | 2010-09-30 02:40:12 +0530 | [diff] [blame] | 517 | .flags = HWMOD_16BIT_REG, |
| 518 | }; |
| 519 | |
Varadarajan, Charulatha | 59c348c | 2010-12-07 16:26:56 -0800 | [diff] [blame] | 520 | /* gpio dev_attr */ |
| 521 | static struct omap_gpio_dev_attr gpio_dev_attr = { |
| 522 | .bank_width = 32, |
| 523 | .dbck_flag = false, |
| 524 | }; |
| 525 | |
Varadarajan, Charulatha | 59c348c | 2010-12-07 16:26:56 -0800 | [diff] [blame] | 526 | /* gpio1 */ |
Varadarajan, Charulatha | 59c348c | 2010-12-07 16:26:56 -0800 | [diff] [blame] | 527 | static struct omap_hwmod omap2420_gpio1_hwmod = { |
| 528 | .name = "gpio1", |
Avinash.H.M | f95440c | 2011-04-05 21:10:15 +0530 | [diff] [blame] | 529 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
Paul Walmsley | 0d619a8 | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 530 | .mpu_irqs = omap2_gpio1_irqs, |
Varadarajan, Charulatha | 59c348c | 2010-12-07 16:26:56 -0800 | [diff] [blame] | 531 | .main_clk = "gpios_fck", |
| 532 | .prcm = { |
| 533 | .omap2 = { |
| 534 | .prcm_reg_id = 1, |
| 535 | .module_bit = OMAP24XX_EN_GPIOS_SHIFT, |
| 536 | .module_offs = WKUP_MOD, |
| 537 | .idlest_reg_id = 1, |
| 538 | .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, |
| 539 | }, |
| 540 | }, |
Paul Walmsley | 273b946 | 2011-07-09 19:14:08 -0600 | [diff] [blame] | 541 | .class = &omap2xxx_gpio_hwmod_class, |
Varadarajan, Charulatha | 59c348c | 2010-12-07 16:26:56 -0800 | [diff] [blame] | 542 | .dev_attr = &gpio_dev_attr, |
Varadarajan, Charulatha | 59c348c | 2010-12-07 16:26:56 -0800 | [diff] [blame] | 543 | }; |
| 544 | |
| 545 | /* gpio2 */ |
Varadarajan, Charulatha | 59c348c | 2010-12-07 16:26:56 -0800 | [diff] [blame] | 546 | static struct omap_hwmod omap2420_gpio2_hwmod = { |
| 547 | .name = "gpio2", |
Avinash.H.M | f95440c | 2011-04-05 21:10:15 +0530 | [diff] [blame] | 548 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
Paul Walmsley | 0d619a8 | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 549 | .mpu_irqs = omap2_gpio2_irqs, |
Varadarajan, Charulatha | 59c348c | 2010-12-07 16:26:56 -0800 | [diff] [blame] | 550 | .main_clk = "gpios_fck", |
| 551 | .prcm = { |
| 552 | .omap2 = { |
| 553 | .prcm_reg_id = 1, |
| 554 | .module_bit = OMAP24XX_EN_GPIOS_SHIFT, |
| 555 | .module_offs = WKUP_MOD, |
| 556 | .idlest_reg_id = 1, |
| 557 | .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, |
| 558 | }, |
| 559 | }, |
Paul Walmsley | 273b946 | 2011-07-09 19:14:08 -0600 | [diff] [blame] | 560 | .class = &omap2xxx_gpio_hwmod_class, |
Varadarajan, Charulatha | 59c348c | 2010-12-07 16:26:56 -0800 | [diff] [blame] | 561 | .dev_attr = &gpio_dev_attr, |
Varadarajan, Charulatha | 59c348c | 2010-12-07 16:26:56 -0800 | [diff] [blame] | 562 | }; |
| 563 | |
| 564 | /* gpio3 */ |
Varadarajan, Charulatha | 59c348c | 2010-12-07 16:26:56 -0800 | [diff] [blame] | 565 | static struct omap_hwmod omap2420_gpio3_hwmod = { |
| 566 | .name = "gpio3", |
Avinash.H.M | f95440c | 2011-04-05 21:10:15 +0530 | [diff] [blame] | 567 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
Paul Walmsley | 0d619a8 | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 568 | .mpu_irqs = omap2_gpio3_irqs, |
Varadarajan, Charulatha | 59c348c | 2010-12-07 16:26:56 -0800 | [diff] [blame] | 569 | .main_clk = "gpios_fck", |
| 570 | .prcm = { |
| 571 | .omap2 = { |
| 572 | .prcm_reg_id = 1, |
| 573 | .module_bit = OMAP24XX_EN_GPIOS_SHIFT, |
| 574 | .module_offs = WKUP_MOD, |
| 575 | .idlest_reg_id = 1, |
| 576 | .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, |
| 577 | }, |
| 578 | }, |
Paul Walmsley | 273b946 | 2011-07-09 19:14:08 -0600 | [diff] [blame] | 579 | .class = &omap2xxx_gpio_hwmod_class, |
Varadarajan, Charulatha | 59c348c | 2010-12-07 16:26:56 -0800 | [diff] [blame] | 580 | .dev_attr = &gpio_dev_attr, |
Varadarajan, Charulatha | 59c348c | 2010-12-07 16:26:56 -0800 | [diff] [blame] | 581 | }; |
| 582 | |
| 583 | /* gpio4 */ |
Varadarajan, Charulatha | 59c348c | 2010-12-07 16:26:56 -0800 | [diff] [blame] | 584 | static struct omap_hwmod omap2420_gpio4_hwmod = { |
| 585 | .name = "gpio4", |
Avinash.H.M | f95440c | 2011-04-05 21:10:15 +0530 | [diff] [blame] | 586 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
Paul Walmsley | 0d619a8 | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 587 | .mpu_irqs = omap2_gpio4_irqs, |
Varadarajan, Charulatha | 59c348c | 2010-12-07 16:26:56 -0800 | [diff] [blame] | 588 | .main_clk = "gpios_fck", |
| 589 | .prcm = { |
| 590 | .omap2 = { |
| 591 | .prcm_reg_id = 1, |
| 592 | .module_bit = OMAP24XX_EN_GPIOS_SHIFT, |
| 593 | .module_offs = WKUP_MOD, |
| 594 | .idlest_reg_id = 1, |
| 595 | .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, |
| 596 | }, |
| 597 | }, |
Paul Walmsley | 273b946 | 2011-07-09 19:14:08 -0600 | [diff] [blame] | 598 | .class = &omap2xxx_gpio_hwmod_class, |
Varadarajan, Charulatha | 59c348c | 2010-12-07 16:26:56 -0800 | [diff] [blame] | 599 | .dev_attr = &gpio_dev_attr, |
Varadarajan, Charulatha | 59c348c | 2010-12-07 16:26:56 -0800 | [diff] [blame] | 600 | }; |
| 601 | |
G, Manjunath Kondaiah | 745685df9 | 2010-12-20 18:27:18 -0800 | [diff] [blame] | 602 | /* dma attributes */ |
| 603 | static struct omap_dma_dev_attr dma_dev_attr = { |
| 604 | .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | |
| 605 | IS_CSSA_32 | IS_CDSA_32, |
| 606 | .lch_count = 32, |
| 607 | }; |
| 608 | |
G, Manjunath Kondaiah | 745685df9 | 2010-12-20 18:27:18 -0800 | [diff] [blame] | 609 | static struct omap_hwmod omap2420_dma_system_hwmod = { |
| 610 | .name = "dma", |
Paul Walmsley | 273b946 | 2011-07-09 19:14:08 -0600 | [diff] [blame] | 611 | .class = &omap2xxx_dma_hwmod_class, |
Paul Walmsley | 0d619a8 | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 612 | .mpu_irqs = omap2_dma_system_irqs, |
G, Manjunath Kondaiah | 745685df9 | 2010-12-20 18:27:18 -0800 | [diff] [blame] | 613 | .main_clk = "core_l3_ck", |
G, Manjunath Kondaiah | 745685df9 | 2010-12-20 18:27:18 -0800 | [diff] [blame] | 614 | .dev_attr = &dma_dev_attr, |
G, Manjunath Kondaiah | 745685df9 | 2010-12-20 18:27:18 -0800 | [diff] [blame] | 615 | .flags = HWMOD_NO_IDLEST, |
| 616 | }; |
| 617 | |
Omar Ramirez Luna | fca1ab5 | 2011-02-24 12:51:32 -0800 | [diff] [blame] | 618 | /* mailbox */ |
Omar Ramirez Luna | fca1ab5 | 2011-02-24 12:51:32 -0800 | [diff] [blame] | 619 | static struct omap_hwmod_irq_info omap2420_mailbox_irqs[] = { |
| 620 | { .name = "dsp", .irq = 26 }, |
| 621 | { .name = "iva", .irq = 34 }, |
Paul Walmsley | 212738a | 2011-07-09 19:14:06 -0600 | [diff] [blame] | 622 | { .irq = -1 } |
Omar Ramirez Luna | fca1ab5 | 2011-02-24 12:51:32 -0800 | [diff] [blame] | 623 | }; |
| 624 | |
Omar Ramirez Luna | fca1ab5 | 2011-02-24 12:51:32 -0800 | [diff] [blame] | 625 | static struct omap_hwmod omap2420_mailbox_hwmod = { |
| 626 | .name = "mailbox", |
Paul Walmsley | 273b946 | 2011-07-09 19:14:08 -0600 | [diff] [blame] | 627 | .class = &omap2xxx_mailbox_hwmod_class, |
Omar Ramirez Luna | fca1ab5 | 2011-02-24 12:51:32 -0800 | [diff] [blame] | 628 | .mpu_irqs = omap2420_mailbox_irqs, |
Omar Ramirez Luna | fca1ab5 | 2011-02-24 12:51:32 -0800 | [diff] [blame] | 629 | .main_clk = "mailboxes_ick", |
| 630 | .prcm = { |
| 631 | .omap2 = { |
| 632 | .prcm_reg_id = 1, |
| 633 | .module_bit = OMAP24XX_EN_MAILBOXES_SHIFT, |
| 634 | .module_offs = CORE_MOD, |
| 635 | .idlest_reg_id = 1, |
| 636 | .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT, |
| 637 | }, |
| 638 | }, |
Omar Ramirez Luna | fca1ab5 | 2011-02-24 12:51:32 -0800 | [diff] [blame] | 639 | }; |
| 640 | |
Charulatha V | 617871d | 2011-02-17 09:53:09 -0800 | [diff] [blame] | 641 | /* mcspi1 */ |
Charulatha V | 617871d | 2011-02-17 09:53:09 -0800 | [diff] [blame] | 642 | static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = { |
| 643 | .num_chipselect = 4, |
| 644 | }; |
| 645 | |
| 646 | static struct omap_hwmod omap2420_mcspi1_hwmod = { |
Paul Walmsley | bec9381 | 2012-04-19 04:03:50 -0600 | [diff] [blame] | 647 | .name = "mcspi1", |
Paul Walmsley | 0d619a8 | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 648 | .mpu_irqs = omap2_mcspi1_mpu_irqs, |
Paul Walmsley | d826ebf | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 649 | .sdma_reqs = omap2_mcspi1_sdma_reqs, |
Charulatha V | 617871d | 2011-02-17 09:53:09 -0800 | [diff] [blame] | 650 | .main_clk = "mcspi1_fck", |
| 651 | .prcm = { |
| 652 | .omap2 = { |
| 653 | .module_offs = CORE_MOD, |
| 654 | .prcm_reg_id = 1, |
| 655 | .module_bit = OMAP24XX_EN_MCSPI1_SHIFT, |
| 656 | .idlest_reg_id = 1, |
| 657 | .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT, |
| 658 | }, |
| 659 | }, |
Paul Walmsley | 273b946 | 2011-07-09 19:14:08 -0600 | [diff] [blame] | 660 | .class = &omap2xxx_mcspi_class, |
| 661 | .dev_attr = &omap_mcspi1_dev_attr, |
Charulatha V | 617871d | 2011-02-17 09:53:09 -0800 | [diff] [blame] | 662 | }; |
| 663 | |
| 664 | /* mcspi2 */ |
Charulatha V | 617871d | 2011-02-17 09:53:09 -0800 | [diff] [blame] | 665 | static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = { |
| 666 | .num_chipselect = 2, |
| 667 | }; |
| 668 | |
| 669 | static struct omap_hwmod omap2420_mcspi2_hwmod = { |
Paul Walmsley | bec9381 | 2012-04-19 04:03:50 -0600 | [diff] [blame] | 670 | .name = "mcspi2", |
Paul Walmsley | 0d619a8 | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 671 | .mpu_irqs = omap2_mcspi2_mpu_irqs, |
Paul Walmsley | d826ebf | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 672 | .sdma_reqs = omap2_mcspi2_sdma_reqs, |
Charulatha V | 617871d | 2011-02-17 09:53:09 -0800 | [diff] [blame] | 673 | .main_clk = "mcspi2_fck", |
| 674 | .prcm = { |
| 675 | .omap2 = { |
| 676 | .module_offs = CORE_MOD, |
| 677 | .prcm_reg_id = 1, |
| 678 | .module_bit = OMAP24XX_EN_MCSPI2_SHIFT, |
| 679 | .idlest_reg_id = 1, |
| 680 | .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT, |
| 681 | }, |
| 682 | }, |
Paul Walmsley | 273b946 | 2011-07-09 19:14:08 -0600 | [diff] [blame] | 683 | .class = &omap2xxx_mcspi_class, |
| 684 | .dev_attr = &omap_mcspi2_dev_attr, |
Charulatha V | 617871d | 2011-02-17 09:53:09 -0800 | [diff] [blame] | 685 | }; |
| 686 | |
Charulatha V | 3cb72fa | 2011-02-24 12:51:46 -0800 | [diff] [blame] | 687 | /* |
| 688 | * 'mcbsp' class |
| 689 | * multi channel buffered serial port controller |
| 690 | */ |
| 691 | |
| 692 | static struct omap_hwmod_class omap2420_mcbsp_hwmod_class = { |
| 693 | .name = "mcbsp", |
| 694 | }; |
| 695 | |
| 696 | /* mcbsp1 */ |
| 697 | static struct omap_hwmod_irq_info omap2420_mcbsp1_irqs[] = { |
| 698 | { .name = "tx", .irq = 59 }, |
| 699 | { .name = "rx", .irq = 60 }, |
Paul Walmsley | 212738a | 2011-07-09 19:14:06 -0600 | [diff] [blame] | 700 | { .irq = -1 } |
Charulatha V | 3cb72fa | 2011-02-24 12:51:46 -0800 | [diff] [blame] | 701 | }; |
| 702 | |
Charulatha V | 3cb72fa | 2011-02-24 12:51:46 -0800 | [diff] [blame] | 703 | static struct omap_hwmod omap2420_mcbsp1_hwmod = { |
| 704 | .name = "mcbsp1", |
| 705 | .class = &omap2420_mcbsp_hwmod_class, |
| 706 | .mpu_irqs = omap2420_mcbsp1_irqs, |
Paul Walmsley | d826ebf | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 707 | .sdma_reqs = omap2_mcbsp1_sdma_reqs, |
Charulatha V | 3cb72fa | 2011-02-24 12:51:46 -0800 | [diff] [blame] | 708 | .main_clk = "mcbsp1_fck", |
| 709 | .prcm = { |
| 710 | .omap2 = { |
| 711 | .prcm_reg_id = 1, |
| 712 | .module_bit = OMAP24XX_EN_MCBSP1_SHIFT, |
| 713 | .module_offs = CORE_MOD, |
| 714 | .idlest_reg_id = 1, |
| 715 | .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT, |
| 716 | }, |
| 717 | }, |
Charulatha V | 3cb72fa | 2011-02-24 12:51:46 -0800 | [diff] [blame] | 718 | }; |
| 719 | |
| 720 | /* mcbsp2 */ |
| 721 | static struct omap_hwmod_irq_info omap2420_mcbsp2_irqs[] = { |
| 722 | { .name = "tx", .irq = 62 }, |
| 723 | { .name = "rx", .irq = 63 }, |
Paul Walmsley | 212738a | 2011-07-09 19:14:06 -0600 | [diff] [blame] | 724 | { .irq = -1 } |
Charulatha V | 3cb72fa | 2011-02-24 12:51:46 -0800 | [diff] [blame] | 725 | }; |
| 726 | |
Charulatha V | 3cb72fa | 2011-02-24 12:51:46 -0800 | [diff] [blame] | 727 | static struct omap_hwmod omap2420_mcbsp2_hwmod = { |
| 728 | .name = "mcbsp2", |
| 729 | .class = &omap2420_mcbsp_hwmod_class, |
| 730 | .mpu_irqs = omap2420_mcbsp2_irqs, |
Paul Walmsley | d826ebf | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 731 | .sdma_reqs = omap2_mcbsp2_sdma_reqs, |
Charulatha V | 3cb72fa | 2011-02-24 12:51:46 -0800 | [diff] [blame] | 732 | .main_clk = "mcbsp2_fck", |
| 733 | .prcm = { |
| 734 | .omap2 = { |
| 735 | .prcm_reg_id = 1, |
| 736 | .module_bit = OMAP24XX_EN_MCBSP2_SHIFT, |
| 737 | .module_offs = CORE_MOD, |
| 738 | .idlest_reg_id = 1, |
| 739 | .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT, |
| 740 | }, |
| 741 | }, |
Charulatha V | 3cb72fa | 2011-02-24 12:51:46 -0800 | [diff] [blame] | 742 | }; |
| 743 | |
Paul Walmsley | 844a3b6 | 2012-04-19 04:04:33 -0600 | [diff] [blame^] | 744 | /* |
| 745 | * interfaces |
| 746 | */ |
| 747 | |
| 748 | /* L3 -> L4_CORE interface */ |
| 749 | static struct omap_hwmod_ocp_if omap2420_l3_main__l4_core = { |
| 750 | .master = &omap2420_l3_main_hwmod, |
| 751 | .slave = &omap2420_l4_core_hwmod, |
| 752 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 753 | }; |
| 754 | |
| 755 | /* MPU -> L3 interface */ |
| 756 | static struct omap_hwmod_ocp_if omap2420_mpu__l3_main = { |
| 757 | .master = &omap2420_mpu_hwmod, |
| 758 | .slave = &omap2420_l3_main_hwmod, |
| 759 | .user = OCP_USER_MPU, |
| 760 | }; |
| 761 | |
| 762 | /* DSS -> l3 */ |
| 763 | static struct omap_hwmod_ocp_if omap2420_dss__l3 = { |
| 764 | .master = &omap2420_dss_core_hwmod, |
| 765 | .slave = &omap2420_l3_main_hwmod, |
| 766 | .fw = { |
| 767 | .omap2 = { |
| 768 | .l3_perm_bit = OMAP2_L3_CORE_FW_CONNID_DSS, |
| 769 | .flags = OMAP_FIREWALL_L3, |
| 770 | } |
| 771 | }, |
| 772 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 773 | }; |
| 774 | |
| 775 | /* l4 core -> mcspi1 interface */ |
| 776 | static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi1 = { |
| 777 | .master = &omap2420_l4_core_hwmod, |
| 778 | .slave = &omap2420_mcspi1_hwmod, |
| 779 | .clk = "mcspi1_ick", |
| 780 | .addr = omap2_mcspi1_addr_space, |
| 781 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 782 | }; |
| 783 | |
| 784 | /* l4 core -> mcspi2 interface */ |
| 785 | static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi2 = { |
| 786 | .master = &omap2420_l4_core_hwmod, |
| 787 | .slave = &omap2420_mcspi2_hwmod, |
| 788 | .clk = "mcspi2_ick", |
| 789 | .addr = omap2_mcspi2_addr_space, |
| 790 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 791 | }; |
| 792 | |
| 793 | /* L4_CORE -> L4_WKUP interface */ |
| 794 | static struct omap_hwmod_ocp_if omap2420_l4_core__l4_wkup = { |
| 795 | .master = &omap2420_l4_core_hwmod, |
| 796 | .slave = &omap2420_l4_wkup_hwmod, |
| 797 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 798 | }; |
| 799 | |
| 800 | /* L4 CORE -> UART1 interface */ |
| 801 | static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = { |
| 802 | .master = &omap2420_l4_core_hwmod, |
| 803 | .slave = &omap2420_uart1_hwmod, |
| 804 | .clk = "uart1_ick", |
| 805 | .addr = omap2xxx_uart1_addr_space, |
| 806 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 807 | }; |
| 808 | |
| 809 | /* L4 CORE -> UART2 interface */ |
| 810 | static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = { |
| 811 | .master = &omap2420_l4_core_hwmod, |
| 812 | .slave = &omap2420_uart2_hwmod, |
| 813 | .clk = "uart2_ick", |
| 814 | .addr = omap2xxx_uart2_addr_space, |
| 815 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 816 | }; |
| 817 | |
| 818 | /* L4 PER -> UART3 interface */ |
| 819 | static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = { |
| 820 | .master = &omap2420_l4_core_hwmod, |
| 821 | .slave = &omap2420_uart3_hwmod, |
| 822 | .clk = "uart3_ick", |
| 823 | .addr = omap2xxx_uart3_addr_space, |
| 824 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 825 | }; |
| 826 | |
| 827 | /* L4 CORE -> I2C1 interface */ |
| 828 | static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = { |
| 829 | .master = &omap2420_l4_core_hwmod, |
| 830 | .slave = &omap2420_i2c1_hwmod, |
| 831 | .clk = "i2c1_ick", |
| 832 | .addr = omap2_i2c1_addr_space, |
| 833 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 834 | }; |
| 835 | |
| 836 | /* L4 CORE -> I2C2 interface */ |
| 837 | static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = { |
| 838 | .master = &omap2420_l4_core_hwmod, |
| 839 | .slave = &omap2420_i2c2_hwmod, |
| 840 | .clk = "i2c2_ick", |
| 841 | .addr = omap2_i2c2_addr_space, |
| 842 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 843 | }; |
| 844 | |
| 845 | /* IVA <- L3 interface */ |
| 846 | static struct omap_hwmod_ocp_if omap2420_l3__iva = { |
| 847 | .master = &omap2420_l3_main_hwmod, |
| 848 | .slave = &omap2420_iva_hwmod, |
| 849 | .clk = "iva1_ifck", |
| 850 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 851 | }; |
| 852 | |
| 853 | static struct omap_hwmod_addr_space omap2420_timer1_addrs[] = { |
| 854 | { |
| 855 | .pa_start = 0x48028000, |
| 856 | .pa_end = 0x48028000 + SZ_1K - 1, |
| 857 | .flags = ADDR_TYPE_RT |
| 858 | }, |
| 859 | { } |
| 860 | }; |
| 861 | |
| 862 | /* l4_wkup -> timer1 */ |
| 863 | static struct omap_hwmod_ocp_if omap2420_l4_wkup__timer1 = { |
| 864 | .master = &omap2420_l4_wkup_hwmod, |
| 865 | .slave = &omap2420_timer1_hwmod, |
| 866 | .clk = "gpt1_ick", |
| 867 | .addr = omap2420_timer1_addrs, |
| 868 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 869 | }; |
| 870 | |
| 871 | /* l4_core -> timer2 */ |
| 872 | static struct omap_hwmod_ocp_if omap2420_l4_core__timer2 = { |
| 873 | .master = &omap2420_l4_core_hwmod, |
| 874 | .slave = &omap2420_timer2_hwmod, |
| 875 | .clk = "gpt2_ick", |
| 876 | .addr = omap2xxx_timer2_addrs, |
| 877 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 878 | }; |
| 879 | |
| 880 | /* l4_core -> timer3 */ |
| 881 | static struct omap_hwmod_ocp_if omap2420_l4_core__timer3 = { |
| 882 | .master = &omap2420_l4_core_hwmod, |
| 883 | .slave = &omap2420_timer3_hwmod, |
| 884 | .clk = "gpt3_ick", |
| 885 | .addr = omap2xxx_timer3_addrs, |
| 886 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 887 | }; |
| 888 | |
| 889 | /* l4_core -> timer4 */ |
| 890 | static struct omap_hwmod_ocp_if omap2420_l4_core__timer4 = { |
| 891 | .master = &omap2420_l4_core_hwmod, |
| 892 | .slave = &omap2420_timer4_hwmod, |
| 893 | .clk = "gpt4_ick", |
| 894 | .addr = omap2xxx_timer4_addrs, |
| 895 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 896 | }; |
| 897 | |
| 898 | /* l4_core -> timer5 */ |
| 899 | static struct omap_hwmod_ocp_if omap2420_l4_core__timer5 = { |
| 900 | .master = &omap2420_l4_core_hwmod, |
| 901 | .slave = &omap2420_timer5_hwmod, |
| 902 | .clk = "gpt5_ick", |
| 903 | .addr = omap2xxx_timer5_addrs, |
| 904 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 905 | }; |
| 906 | |
| 907 | /* l4_core -> timer6 */ |
| 908 | static struct omap_hwmod_ocp_if omap2420_l4_core__timer6 = { |
| 909 | .master = &omap2420_l4_core_hwmod, |
| 910 | .slave = &omap2420_timer6_hwmod, |
| 911 | .clk = "gpt6_ick", |
| 912 | .addr = omap2xxx_timer6_addrs, |
| 913 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 914 | }; |
| 915 | |
| 916 | /* l4_core -> timer7 */ |
| 917 | static struct omap_hwmod_ocp_if omap2420_l4_core__timer7 = { |
| 918 | .master = &omap2420_l4_core_hwmod, |
| 919 | .slave = &omap2420_timer7_hwmod, |
| 920 | .clk = "gpt7_ick", |
| 921 | .addr = omap2xxx_timer7_addrs, |
| 922 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 923 | }; |
| 924 | |
| 925 | /* l4_core -> timer8 */ |
| 926 | static struct omap_hwmod_ocp_if omap2420_l4_core__timer8 = { |
| 927 | .master = &omap2420_l4_core_hwmod, |
| 928 | .slave = &omap2420_timer8_hwmod, |
| 929 | .clk = "gpt8_ick", |
| 930 | .addr = omap2xxx_timer8_addrs, |
| 931 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 932 | }; |
| 933 | |
| 934 | /* l4_core -> timer9 */ |
| 935 | static struct omap_hwmod_ocp_if omap2420_l4_core__timer9 = { |
| 936 | .master = &omap2420_l4_core_hwmod, |
| 937 | .slave = &omap2420_timer9_hwmod, |
| 938 | .clk = "gpt9_ick", |
| 939 | .addr = omap2xxx_timer9_addrs, |
| 940 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 941 | }; |
| 942 | |
| 943 | /* l4_core -> timer10 */ |
| 944 | static struct omap_hwmod_ocp_if omap2420_l4_core__timer10 = { |
| 945 | .master = &omap2420_l4_core_hwmod, |
| 946 | .slave = &omap2420_timer10_hwmod, |
| 947 | .clk = "gpt10_ick", |
| 948 | .addr = omap2_timer10_addrs, |
| 949 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 950 | }; |
| 951 | |
| 952 | /* l4_core -> timer11 */ |
| 953 | static struct omap_hwmod_ocp_if omap2420_l4_core__timer11 = { |
| 954 | .master = &omap2420_l4_core_hwmod, |
| 955 | .slave = &omap2420_timer11_hwmod, |
| 956 | .clk = "gpt11_ick", |
| 957 | .addr = omap2_timer11_addrs, |
| 958 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 959 | }; |
| 960 | |
| 961 | /* l4_core -> timer12 */ |
| 962 | static struct omap_hwmod_ocp_if omap2420_l4_core__timer12 = { |
| 963 | .master = &omap2420_l4_core_hwmod, |
| 964 | .slave = &omap2420_timer12_hwmod, |
| 965 | .clk = "gpt12_ick", |
| 966 | .addr = omap2xxx_timer12_addrs, |
| 967 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 968 | }; |
| 969 | |
| 970 | /* l4_wkup -> wd_timer2 */ |
| 971 | static struct omap_hwmod_addr_space omap2420_wd_timer2_addrs[] = { |
| 972 | { |
| 973 | .pa_start = 0x48022000, |
| 974 | .pa_end = 0x4802207f, |
| 975 | .flags = ADDR_TYPE_RT |
| 976 | }, |
| 977 | { } |
| 978 | }; |
| 979 | |
| 980 | static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = { |
| 981 | .master = &omap2420_l4_wkup_hwmod, |
| 982 | .slave = &omap2420_wd_timer2_hwmod, |
| 983 | .clk = "mpu_wdt_ick", |
| 984 | .addr = omap2420_wd_timer2_addrs, |
| 985 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 986 | }; |
| 987 | |
| 988 | /* l4_core -> dss */ |
| 989 | static struct omap_hwmod_ocp_if omap2420_l4_core__dss = { |
| 990 | .master = &omap2420_l4_core_hwmod, |
| 991 | .slave = &omap2420_dss_core_hwmod, |
| 992 | .clk = "dss_ick", |
| 993 | .addr = omap2_dss_addrs, |
| 994 | .fw = { |
| 995 | .omap2 = { |
| 996 | .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION, |
| 997 | .flags = OMAP_FIREWALL_L4, |
| 998 | } |
| 999 | }, |
| 1000 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 1001 | }; |
| 1002 | |
| 1003 | /* l4_core -> dss_dispc */ |
| 1004 | static struct omap_hwmod_ocp_if omap2420_l4_core__dss_dispc = { |
| 1005 | .master = &omap2420_l4_core_hwmod, |
| 1006 | .slave = &omap2420_dss_dispc_hwmod, |
| 1007 | .clk = "dss_ick", |
| 1008 | .addr = omap2_dss_dispc_addrs, |
| 1009 | .fw = { |
| 1010 | .omap2 = { |
| 1011 | .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_DISPC_REGION, |
| 1012 | .flags = OMAP_FIREWALL_L4, |
| 1013 | } |
| 1014 | }, |
| 1015 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 1016 | }; |
| 1017 | |
| 1018 | /* l4_core -> dss_rfbi */ |
| 1019 | static struct omap_hwmod_ocp_if omap2420_l4_core__dss_rfbi = { |
| 1020 | .master = &omap2420_l4_core_hwmod, |
| 1021 | .slave = &omap2420_dss_rfbi_hwmod, |
| 1022 | .clk = "dss_ick", |
| 1023 | .addr = omap2_dss_rfbi_addrs, |
| 1024 | .fw = { |
| 1025 | .omap2 = { |
| 1026 | .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION, |
| 1027 | .flags = OMAP_FIREWALL_L4, |
| 1028 | } |
| 1029 | }, |
| 1030 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 1031 | }; |
| 1032 | |
| 1033 | /* l4_core -> dss_venc */ |
| 1034 | static struct omap_hwmod_ocp_if omap2420_l4_core__dss_venc = { |
| 1035 | .master = &omap2420_l4_core_hwmod, |
| 1036 | .slave = &omap2420_dss_venc_hwmod, |
| 1037 | .clk = "dss_ick", |
| 1038 | .addr = omap2_dss_venc_addrs, |
| 1039 | .fw = { |
| 1040 | .omap2 = { |
| 1041 | .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_VENC_REGION, |
| 1042 | .flags = OMAP_FIREWALL_L4, |
| 1043 | } |
| 1044 | }, |
| 1045 | .flags = OCPIF_SWSUP_IDLE, |
| 1046 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 1047 | }; |
| 1048 | |
| 1049 | /* l4_wkup -> gpio1 */ |
| 1050 | static struct omap_hwmod_addr_space omap2420_gpio1_addr_space[] = { |
| 1051 | { |
| 1052 | .pa_start = 0x48018000, |
| 1053 | .pa_end = 0x480181ff, |
| 1054 | .flags = ADDR_TYPE_RT |
| 1055 | }, |
| 1056 | { } |
| 1057 | }; |
| 1058 | |
| 1059 | static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio1 = { |
| 1060 | .master = &omap2420_l4_wkup_hwmod, |
| 1061 | .slave = &omap2420_gpio1_hwmod, |
| 1062 | .clk = "gpios_ick", |
| 1063 | .addr = omap2420_gpio1_addr_space, |
| 1064 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 1065 | }; |
| 1066 | |
| 1067 | /* l4_wkup -> gpio2 */ |
| 1068 | static struct omap_hwmod_addr_space omap2420_gpio2_addr_space[] = { |
| 1069 | { |
| 1070 | .pa_start = 0x4801a000, |
| 1071 | .pa_end = 0x4801a1ff, |
| 1072 | .flags = ADDR_TYPE_RT |
| 1073 | }, |
| 1074 | { } |
| 1075 | }; |
| 1076 | |
| 1077 | static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio2 = { |
| 1078 | .master = &omap2420_l4_wkup_hwmod, |
| 1079 | .slave = &omap2420_gpio2_hwmod, |
| 1080 | .clk = "gpios_ick", |
| 1081 | .addr = omap2420_gpio2_addr_space, |
| 1082 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 1083 | }; |
| 1084 | |
| 1085 | /* l4_wkup -> gpio3 */ |
| 1086 | static struct omap_hwmod_addr_space omap2420_gpio3_addr_space[] = { |
| 1087 | { |
| 1088 | .pa_start = 0x4801c000, |
| 1089 | .pa_end = 0x4801c1ff, |
| 1090 | .flags = ADDR_TYPE_RT |
| 1091 | }, |
| 1092 | { } |
| 1093 | }; |
| 1094 | |
| 1095 | static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio3 = { |
| 1096 | .master = &omap2420_l4_wkup_hwmod, |
| 1097 | .slave = &omap2420_gpio3_hwmod, |
| 1098 | .clk = "gpios_ick", |
| 1099 | .addr = omap2420_gpio3_addr_space, |
| 1100 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 1101 | }; |
| 1102 | |
| 1103 | /* l4_wkup -> gpio4 */ |
| 1104 | static struct omap_hwmod_addr_space omap2420_gpio4_addr_space[] = { |
| 1105 | { |
| 1106 | .pa_start = 0x4801e000, |
| 1107 | .pa_end = 0x4801e1ff, |
| 1108 | .flags = ADDR_TYPE_RT |
| 1109 | }, |
| 1110 | { } |
| 1111 | }; |
| 1112 | |
| 1113 | static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio4 = { |
| 1114 | .master = &omap2420_l4_wkup_hwmod, |
| 1115 | .slave = &omap2420_gpio4_hwmod, |
| 1116 | .clk = "gpios_ick", |
| 1117 | .addr = omap2420_gpio4_addr_space, |
| 1118 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 1119 | }; |
| 1120 | |
| 1121 | /* dma_system -> L3 */ |
| 1122 | static struct omap_hwmod_ocp_if omap2420_dma_system__l3 = { |
| 1123 | .master = &omap2420_dma_system_hwmod, |
| 1124 | .slave = &omap2420_l3_main_hwmod, |
| 1125 | .clk = "core_l3_ck", |
| 1126 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 1127 | }; |
| 1128 | |
| 1129 | /* l4_core -> dma_system */ |
| 1130 | static struct omap_hwmod_ocp_if omap2420_l4_core__dma_system = { |
| 1131 | .master = &omap2420_l4_core_hwmod, |
| 1132 | .slave = &omap2420_dma_system_hwmod, |
| 1133 | .clk = "sdma_ick", |
| 1134 | .addr = omap2_dma_system_addrs, |
| 1135 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 1136 | }; |
| 1137 | |
| 1138 | /* l4_core -> mailbox */ |
| 1139 | static struct omap_hwmod_ocp_if omap2420_l4_core__mailbox = { |
| 1140 | .master = &omap2420_l4_core_hwmod, |
| 1141 | .slave = &omap2420_mailbox_hwmod, |
| 1142 | .addr = omap2_mailbox_addrs, |
| 1143 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 1144 | }; |
| 1145 | |
| 1146 | /* l4_core -> mcbsp1 */ |
| 1147 | static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp1 = { |
| 1148 | .master = &omap2420_l4_core_hwmod, |
| 1149 | .slave = &omap2420_mcbsp1_hwmod, |
| 1150 | .clk = "mcbsp1_ick", |
| 1151 | .addr = omap2_mcbsp1_addrs, |
| 1152 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 1153 | }; |
| 1154 | |
| 1155 | /* l4_core -> mcbsp2 */ |
| 1156 | static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp2 = { |
| 1157 | .master = &omap2420_l4_core_hwmod, |
| 1158 | .slave = &omap2420_mcbsp2_hwmod, |
| 1159 | .clk = "mcbsp2_ick", |
| 1160 | .addr = omap2xxx_mcbsp2_addrs, |
| 1161 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 1162 | }; |
| 1163 | |
Paul Walmsley | 0a78c5c | 2012-04-19 04:04:31 -0600 | [diff] [blame] | 1164 | static struct omap_hwmod_ocp_if *omap2420_hwmod_ocp_ifs[] __initdata = { |
| 1165 | &omap2420_l3_main__l4_core, |
| 1166 | &omap2420_mpu__l3_main, |
| 1167 | &omap2420_dss__l3, |
| 1168 | &omap2420_l4_core__mcspi1, |
| 1169 | &omap2420_l4_core__mcspi2, |
| 1170 | &omap2420_l4_core__l4_wkup, |
| 1171 | &omap2_l4_core__uart1, |
| 1172 | &omap2_l4_core__uart2, |
| 1173 | &omap2_l4_core__uart3, |
| 1174 | &omap2420_l4_core__i2c1, |
| 1175 | &omap2420_l4_core__i2c2, |
| 1176 | &omap2420_l3__iva, |
| 1177 | &omap2420_l4_wkup__timer1, |
| 1178 | &omap2420_l4_core__timer2, |
| 1179 | &omap2420_l4_core__timer3, |
| 1180 | &omap2420_l4_core__timer4, |
| 1181 | &omap2420_l4_core__timer5, |
| 1182 | &omap2420_l4_core__timer6, |
| 1183 | &omap2420_l4_core__timer7, |
| 1184 | &omap2420_l4_core__timer8, |
| 1185 | &omap2420_l4_core__timer9, |
| 1186 | &omap2420_l4_core__timer10, |
| 1187 | &omap2420_l4_core__timer11, |
| 1188 | &omap2420_l4_core__timer12, |
| 1189 | &omap2420_l4_wkup__wd_timer2, |
| 1190 | &omap2420_l4_core__dss, |
| 1191 | &omap2420_l4_core__dss_dispc, |
| 1192 | &omap2420_l4_core__dss_rfbi, |
| 1193 | &omap2420_l4_core__dss_venc, |
| 1194 | &omap2420_l4_wkup__gpio1, |
| 1195 | &omap2420_l4_wkup__gpio2, |
| 1196 | &omap2420_l4_wkup__gpio3, |
| 1197 | &omap2420_l4_wkup__gpio4, |
| 1198 | &omap2420_dma_system__l3, |
| 1199 | &omap2420_l4_core__dma_system, |
| 1200 | &omap2420_l4_core__mailbox, |
| 1201 | &omap2420_l4_core__mcbsp1, |
| 1202 | &omap2420_l4_core__mcbsp2, |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 1203 | NULL, |
| 1204 | }; |
| 1205 | |
Paul Walmsley | 7359154 | 2010-02-22 22:09:32 -0700 | [diff] [blame] | 1206 | int __init omap2420_hwmod_init(void) |
| 1207 | { |
Paul Walmsley | 0a78c5c | 2012-04-19 04:04:31 -0600 | [diff] [blame] | 1208 | return omap_hwmod_register_links(omap2420_hwmod_ocp_ifs); |
Paul Walmsley | 7359154 | 2010-02-22 22:09:32 -0700 | [diff] [blame] | 1209 | } |