Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 1 | /* |
Deepak Katragadda | 125fe37 | 2017-03-01 10:28:24 -0800 | [diff] [blame] | 2 | * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 and |
| 6 | * only version 2 as published by the Free Software Foundation. |
| 7 | * |
| 8 | * This program is distributed in the hope that it will be useful, |
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 11 | * GNU General Public License for more details. |
| 12 | */ |
| 13 | |
Deepak Katragadda | 9abd794 | 2017-06-13 14:20:09 -0700 | [diff] [blame] | 14 | #define pr_fmt(fmt) "clk: %s: " fmt, __func__ |
| 15 | |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 16 | #include <linux/kernel.h> |
| 17 | #include <linux/bitops.h> |
| 18 | #include <linux/err.h> |
| 19 | #include <linux/platform_device.h> |
| 20 | #include <linux/module.h> |
| 21 | #include <linux/of.h> |
| 22 | #include <linux/of_device.h> |
| 23 | #include <linux/clk.h> |
| 24 | #include <linux/clk-provider.h> |
| 25 | #include <linux/regmap.h> |
| 26 | #include <linux/reset-controller.h> |
| 27 | |
Kyle Yan | 6a20fae | 2017-02-14 13:34:41 -0800 | [diff] [blame] | 28 | #include <dt-bindings/clock/qcom,gcc-sdm845.h> |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 29 | |
| 30 | #include "common.h" |
| 31 | #include "clk-regmap.h" |
| 32 | #include "clk-pll.h" |
| 33 | #include "clk-rcg.h" |
| 34 | #include "clk-branch.h" |
| 35 | #include "reset.h" |
| 36 | #include "clk-alpha-pll.h" |
Kyle Yan | 6a20fae | 2017-02-14 13:34:41 -0800 | [diff] [blame] | 37 | #include "vdd-level-sdm845.h" |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 38 | |
| 39 | #define GCC_APCS_CLOCK_SLEEP_ENA_VOTE_OFFSET 0x52008 |
| 40 | #define CPUSS_AHB_CLK_SLEEP_ENA BIT(21) |
Deepak Katragadda | b666c98 | 2017-04-10 14:16:17 -0700 | [diff] [blame] | 41 | #define SYS_NOC_CPUSS_AHB_CLK_SLEEP_ENA BIT(0) |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 42 | #define GCC_MMSS_MISC 0x09FFC |
| 43 | #define GCC_GPU_MISC 0x71028 |
| 44 | |
| 45 | #define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) } |
| 46 | |
| 47 | static DEFINE_VDD_REGULATORS(vdd_cx, VDD_CX_NUM, 1, vdd_corner); |
| 48 | static DEFINE_VDD_REGULATORS(vdd_cx_ao, VDD_CX_NUM, 1, vdd_corner); |
| 49 | |
| 50 | enum { |
| 51 | P_BI_TCXO, |
| 52 | P_AUD_REF_CLK, |
| 53 | P_CORE_BI_PLL_TEST_SE, |
| 54 | P_GPLL0_OUT_EVEN, |
| 55 | P_GPLL0_OUT_MAIN, |
Deepak Katragadda | 87732a1 | 2017-07-18 12:07:17 -0700 | [diff] [blame] | 56 | P_GPLL1_OUT_MAIN, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 57 | P_GPLL4_OUT_MAIN, |
Deepak Katragadda | 87732a1 | 2017-07-18 12:07:17 -0700 | [diff] [blame] | 58 | P_GPLL6_OUT_MAIN, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 59 | P_SLEEP_CLK, |
| 60 | }; |
| 61 | |
| 62 | static const struct parent_map gcc_parent_map_0[] = { |
| 63 | { P_BI_TCXO, 0 }, |
| 64 | { P_GPLL0_OUT_MAIN, 1 }, |
| 65 | { P_GPLL0_OUT_EVEN, 6 }, |
| 66 | { P_CORE_BI_PLL_TEST_SE, 7 }, |
| 67 | }; |
| 68 | |
| 69 | static const char * const gcc_parent_names_0[] = { |
| 70 | "bi_tcxo", |
| 71 | "gpll0", |
| 72 | "gpll0_out_even", |
| 73 | "core_bi_pll_test_se", |
| 74 | }; |
| 75 | |
| 76 | static const struct parent_map gcc_parent_map_1[] = { |
| 77 | { P_BI_TCXO, 0 }, |
| 78 | { P_GPLL0_OUT_MAIN, 1 }, |
| 79 | { P_SLEEP_CLK, 5 }, |
| 80 | { P_GPLL0_OUT_EVEN, 6 }, |
| 81 | { P_CORE_BI_PLL_TEST_SE, 7 }, |
| 82 | }; |
| 83 | |
| 84 | static const char * const gcc_parent_names_1[] = { |
| 85 | "bi_tcxo", |
| 86 | "gpll0", |
| 87 | "core_pi_sleep_clk", |
| 88 | "gpll0_out_even", |
| 89 | "core_bi_pll_test_se", |
| 90 | }; |
| 91 | |
| 92 | static const struct parent_map gcc_parent_map_2[] = { |
| 93 | { P_BI_TCXO, 0 }, |
| 94 | { P_SLEEP_CLK, 5 }, |
| 95 | { P_CORE_BI_PLL_TEST_SE, 7 }, |
| 96 | }; |
| 97 | |
| 98 | static const char * const gcc_parent_names_2[] = { |
| 99 | "bi_tcxo", |
| 100 | "core_pi_sleep_clk", |
| 101 | "core_bi_pll_test_se", |
| 102 | }; |
| 103 | |
| 104 | static const struct parent_map gcc_parent_map_3[] = { |
| 105 | { P_BI_TCXO, 0 }, |
| 106 | { P_GPLL0_OUT_MAIN, 1 }, |
| 107 | { P_CORE_BI_PLL_TEST_SE, 7 }, |
| 108 | }; |
| 109 | |
| 110 | static const char * const gcc_parent_names_3[] = { |
| 111 | "bi_tcxo", |
| 112 | "gpll0", |
| 113 | "core_bi_pll_test_se", |
| 114 | }; |
| 115 | |
| 116 | static const struct parent_map gcc_parent_map_4[] = { |
| 117 | { P_BI_TCXO, 0 }, |
| 118 | { P_CORE_BI_PLL_TEST_SE, 7 }, |
| 119 | }; |
| 120 | |
| 121 | static const char * const gcc_parent_names_4[] = { |
| 122 | "bi_tcxo", |
| 123 | "core_bi_pll_test_se", |
| 124 | }; |
| 125 | |
| 126 | static const struct parent_map gcc_parent_map_5[] = { |
| 127 | { P_BI_TCXO, 0 }, |
| 128 | { P_GPLL0_OUT_MAIN, 1 }, |
Deepak Katragadda | 125fe37 | 2017-03-01 10:28:24 -0800 | [diff] [blame] | 129 | { P_GPLL4_OUT_MAIN, 5 }, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 130 | { P_GPLL0_OUT_EVEN, 6 }, |
| 131 | { P_CORE_BI_PLL_TEST_SE, 7 }, |
| 132 | }; |
| 133 | |
| 134 | static const char * const gcc_parent_names_5[] = { |
| 135 | "bi_tcxo", |
| 136 | "gpll0", |
Deepak Katragadda | 125fe37 | 2017-03-01 10:28:24 -0800 | [diff] [blame] | 137 | "gpll4", |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 138 | "gpll0_out_even", |
| 139 | "core_bi_pll_test_se", |
| 140 | }; |
| 141 | |
| 142 | static const struct parent_map gcc_parent_map_6[] = { |
| 143 | { P_BI_TCXO, 0 }, |
| 144 | { P_GPLL0_OUT_MAIN, 1 }, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 145 | { P_AUD_REF_CLK, 2 }, |
| 146 | { P_GPLL0_OUT_EVEN, 6 }, |
| 147 | { P_CORE_BI_PLL_TEST_SE, 7 }, |
| 148 | }; |
| 149 | |
Deepak Katragadda | 125fe37 | 2017-03-01 10:28:24 -0800 | [diff] [blame] | 150 | static const char * const gcc_parent_names_6[] = { |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 151 | "bi_tcxo", |
| 152 | "gpll0", |
| 153 | "aud_ref_clk", |
| 154 | "gpll0_out_even", |
| 155 | "core_bi_pll_test_se", |
| 156 | }; |
| 157 | |
Deepak Katragadda | 3760e05 | 2017-04-20 13:41:32 -0700 | [diff] [blame] | 158 | static const char * const gcc_parent_names_7[] = { |
| 159 | "bi_tcxo_ao", |
| 160 | "gpll0", |
| 161 | "gpll0_out_even", |
| 162 | "core_bi_pll_test_se", |
| 163 | }; |
| 164 | |
Deepak Katragadda | 050c202 | 2017-05-05 09:50:43 -0700 | [diff] [blame] | 165 | static const char * const gcc_parent_names_8[] = { |
| 166 | "bi_tcxo_ao", |
| 167 | "gpll0", |
| 168 | "core_bi_pll_test_se", |
| 169 | }; |
| 170 | |
Deepak Katragadda | 87732a1 | 2017-07-18 12:07:17 -0700 | [diff] [blame] | 171 | static const struct parent_map gcc_parent_map_9[] = { |
| 172 | { P_BI_TCXO, 0 }, |
| 173 | { P_GPLL0_OUT_MAIN, 1 }, |
| 174 | { P_GPLL1_OUT_MAIN, 4 }, |
| 175 | { P_CORE_BI_PLL_TEST_SE, 7 }, |
| 176 | }; |
| 177 | |
| 178 | static const char * const gcc_parent_names_9[] = { |
| 179 | "bi_tcxo", |
| 180 | "gpll0", |
| 181 | "gpll1", |
| 182 | "core_bi_pll_test_se", |
| 183 | }; |
| 184 | |
Deepak Katragadda | f56802e | 2017-07-14 13:39:03 -0700 | [diff] [blame] | 185 | static const struct parent_map gcc_parent_map_10[] = { |
| 186 | { P_BI_TCXO, 0 }, |
| 187 | { P_GPLL0_OUT_MAIN, 1 }, |
| 188 | { P_GPLL4_OUT_MAIN, 5 }, |
| 189 | { P_GPLL0_OUT_EVEN, 6 }, |
| 190 | { P_CORE_BI_PLL_TEST_SE, 7 }, |
| 191 | }; |
| 192 | |
| 193 | static const char * const gcc_parent_names_10[] = { |
| 194 | "bi_tcxo", |
| 195 | "gpll0", |
| 196 | "gpll4", |
| 197 | "gpll0_out_even", |
| 198 | "core_bi_pll_test_se", |
| 199 | }; |
| 200 | |
Deepak Katragadda | 443bd8d | 2017-08-28 22:30:19 +0530 | [diff] [blame] | 201 | static const struct parent_map gcc_parent_map_7[] = { |
| 202 | { P_BI_TCXO, 0 }, |
| 203 | { P_GPLL0_OUT_MAIN, 1 }, |
| 204 | { P_GPLL6_OUT_MAIN, 2 }, |
| 205 | { P_GPLL0_OUT_EVEN, 6 }, |
| 206 | { P_CORE_BI_PLL_TEST_SE, 7 }, |
| 207 | }; |
| 208 | |
| 209 | static const char * const gcc_parent_names_11[] = { |
| 210 | "bi_tcxo", |
| 211 | "gpll0", |
| 212 | "gpll6", |
| 213 | "gpll0_out_even", |
| 214 | "core_bi_pll_test_se", |
| 215 | }; |
| 216 | |
Deepak Katragadda | d075ba3 | 2017-04-06 13:45:47 -0700 | [diff] [blame] | 217 | static struct clk_dummy measure_only_snoc_clk = { |
| 218 | .rrate = 1000, |
| 219 | .hw.init = &(struct clk_init_data){ |
| 220 | .name = "measure_only_snoc_clk", |
| 221 | .ops = &clk_dummy_ops, |
| 222 | }, |
| 223 | }; |
| 224 | |
| 225 | static struct clk_dummy measure_only_cnoc_clk = { |
| 226 | .rrate = 1000, |
| 227 | .hw.init = &(struct clk_init_data){ |
| 228 | .name = "measure_only_cnoc_clk", |
| 229 | .ops = &clk_dummy_ops, |
| 230 | }, |
| 231 | }; |
| 232 | |
| 233 | static struct clk_dummy measure_only_bimc_clk = { |
| 234 | .rrate = 1000, |
| 235 | .hw.init = &(struct clk_init_data){ |
| 236 | .name = "measure_only_bimc_clk", |
| 237 | .ops = &clk_dummy_ops, |
| 238 | }, |
| 239 | }; |
| 240 | |
| 241 | static struct clk_dummy measure_only_ipa_2x_clk = { |
| 242 | .rrate = 1000, |
| 243 | .hw.init = &(struct clk_init_data){ |
| 244 | .name = "measure_only_ipa_2x_clk", |
| 245 | .ops = &clk_dummy_ops, |
| 246 | }, |
| 247 | }; |
| 248 | |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 249 | static struct pll_vco fabia_vco[] = { |
Deepak Katragadda | 47e084f | 2017-06-06 15:08:26 -0700 | [diff] [blame] | 250 | { 249600000, 2000000000, 0 }, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 251 | { 125000000, 1000000000, 1 }, |
| 252 | }; |
| 253 | |
| 254 | static struct clk_alpha_pll gpll0 = { |
| 255 | .offset = 0x0, |
| 256 | .vco_table = fabia_vco, |
| 257 | .num_vco = ARRAY_SIZE(fabia_vco), |
| 258 | .type = FABIA_PLL, |
| 259 | .clkr = { |
| 260 | .enable_reg = 0x52000, |
| 261 | .enable_mask = BIT(0), |
| 262 | .hw.init = &(struct clk_init_data){ |
| 263 | .name = "gpll0", |
| 264 | .parent_names = (const char *[]){ "bi_tcxo" }, |
| 265 | .num_parents = 1, |
| 266 | .ops = &clk_fabia_fixed_pll_ops, |
Deepak Katragadda | d04d2ca | 2017-03-30 11:03:20 -0700 | [diff] [blame] | 267 | VDD_CX_FMAX_MAP4( |
| 268 | MIN, 615000000, |
| 269 | LOW, 1066000000, |
| 270 | LOW_L1, 1600000000, |
| 271 | NOMINAL, 2000000000), |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 272 | }, |
| 273 | }, |
| 274 | }; |
| 275 | |
Deepak Katragadda | f56802e | 2017-07-14 13:39:03 -0700 | [diff] [blame] | 276 | static struct clk_alpha_pll gpll4 = { |
| 277 | .offset = 0x76000, |
| 278 | .vco_table = fabia_vco, |
| 279 | .num_vco = ARRAY_SIZE(fabia_vco), |
| 280 | .type = FABIA_PLL, |
| 281 | .clkr = { |
| 282 | .enable_reg = 0x52000, |
| 283 | .enable_mask = BIT(4), |
| 284 | .hw.init = &(struct clk_init_data){ |
| 285 | .name = "gpll4", |
| 286 | .parent_names = (const char *[]){ "bi_tcxo" }, |
| 287 | .num_parents = 1, |
| 288 | .ops = &clk_fabia_fixed_pll_ops, |
| 289 | VDD_CX_FMAX_MAP4( |
| 290 | MIN, 615000000, |
| 291 | LOW, 1066000000, |
| 292 | LOW_L1, 1600000000, |
| 293 | NOMINAL, 2000000000), |
| 294 | }, |
| 295 | }, |
| 296 | }; |
| 297 | |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 298 | static const struct clk_div_table post_div_table_fabia_even[] = { |
| 299 | { 0x0, 1 }, |
| 300 | { 0x1, 2 }, |
| 301 | { 0x3, 4 }, |
| 302 | { 0x7, 8 }, |
Stephen Boyd | 9e3b0a3 | 2017-03-07 05:30:31 -0800 | [diff] [blame] | 303 | { } |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 304 | }; |
| 305 | |
| 306 | static struct clk_alpha_pll_postdiv gpll0_out_even = { |
| 307 | .offset = 0x0, |
| 308 | .post_div_shift = 8, |
| 309 | .post_div_table = post_div_table_fabia_even, |
| 310 | .num_post_div = ARRAY_SIZE(post_div_table_fabia_even), |
| 311 | .width = 4, |
| 312 | .clkr.hw.init = &(struct clk_init_data){ |
| 313 | .name = "gpll0_out_even", |
| 314 | .parent_names = (const char *[]){ "gpll0" }, |
| 315 | .num_parents = 1, |
| 316 | .ops = &clk_generic_pll_postdiv_ops, |
| 317 | }, |
| 318 | }; |
| 319 | |
Deepak Katragadda | 443bd8d | 2017-08-28 22:30:19 +0530 | [diff] [blame] | 320 | static struct clk_alpha_pll gpll6 = { |
| 321 | .offset = 0x13000, |
| 322 | .vco_table = fabia_vco, |
| 323 | .num_vco = ARRAY_SIZE(fabia_vco), |
| 324 | .type = FABIA_PLL, |
| 325 | .clkr = { |
| 326 | .enable_reg = 0x52000, |
| 327 | .enable_mask = BIT(6), |
| 328 | .hw.init = &(struct clk_init_data){ |
| 329 | .name = "gpll6", |
| 330 | .parent_names = (const char *[]){ "bi_tcxo" }, |
| 331 | .num_parents = 1, |
| 332 | .ops = &clk_fabia_fixed_pll_ops, |
| 333 | VDD_CX_FMAX_MAP4( |
| 334 | MIN, 615000000, |
| 335 | LOW, 1066000000, |
| 336 | LOW_L1, 1600000000, |
| 337 | NOMINAL, 2000000000), |
| 338 | }, |
| 339 | }, |
| 340 | }; |
| 341 | |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 342 | static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = { |
| 343 | F(19200000, P_BI_TCXO, 1, 0, 0), |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 344 | { } |
| 345 | }; |
| 346 | |
| 347 | static struct clk_rcg2 gcc_cpuss_ahb_clk_src = { |
| 348 | .cmd_rcgr = 0x48014, |
| 349 | .mnd_width = 0, |
| 350 | .hid_width = 5, |
| 351 | .parent_map = gcc_parent_map_0, |
| 352 | .freq_tbl = ftbl_gcc_cpuss_ahb_clk_src, |
| 353 | .clkr.hw.init = &(struct clk_init_data){ |
| 354 | .name = "gcc_cpuss_ahb_clk_src", |
Deepak Katragadda | 3760e05 | 2017-04-20 13:41:32 -0700 | [diff] [blame] | 355 | .parent_names = gcc_parent_names_7, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 356 | .num_parents = 4, |
| 357 | .flags = CLK_SET_RATE_PARENT, |
| 358 | .ops = &clk_rcg2_ops, |
| 359 | VDD_CX_FMAX_MAP3_AO( |
| 360 | MIN, 19200000, |
| 361 | LOW, 50000000, |
| 362 | NOMINAL, 100000000), |
| 363 | }, |
| 364 | }; |
| 365 | |
| 366 | static const struct freq_tbl ftbl_gcc_cpuss_rbcpr_clk_src[] = { |
| 367 | F(19200000, P_BI_TCXO, 1, 0, 0), |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 368 | { } |
| 369 | }; |
| 370 | |
Deepak Katragadda | 443bd8d | 2017-08-28 22:30:19 +0530 | [diff] [blame] | 371 | static const struct freq_tbl ftbl_gcc_cpuss_rbcpr_clk_src_sdm670[] = { |
| 372 | F(19200000, P_BI_TCXO, 1, 0, 0), |
| 373 | F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0), |
| 374 | { } |
| 375 | }; |
| 376 | |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 377 | static struct clk_rcg2 gcc_cpuss_rbcpr_clk_src = { |
| 378 | .cmd_rcgr = 0x4815c, |
| 379 | .mnd_width = 0, |
| 380 | .hid_width = 5, |
| 381 | .parent_map = gcc_parent_map_3, |
| 382 | .freq_tbl = ftbl_gcc_cpuss_rbcpr_clk_src, |
| 383 | .clkr.hw.init = &(struct clk_init_data){ |
| 384 | .name = "gcc_cpuss_rbcpr_clk_src", |
Deepak Katragadda | 050c202 | 2017-05-05 09:50:43 -0700 | [diff] [blame] | 385 | .parent_names = gcc_parent_names_8, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 386 | .num_parents = 3, |
| 387 | .flags = CLK_SET_RATE_PARENT, |
| 388 | .ops = &clk_rcg2_ops, |
Deepak Katragadda | 050c202 | 2017-05-05 09:50:43 -0700 | [diff] [blame] | 389 | VDD_CX_FMAX_MAP1_AO( |
Deepak Katragadda | 125fe37 | 2017-03-01 10:28:24 -0800 | [diff] [blame] | 390 | MIN, 19200000), |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 391 | }, |
| 392 | }; |
| 393 | |
| 394 | static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = { |
Deepak Katragadda | bae7106 | 2017-05-22 14:37:11 -0700 | [diff] [blame] | 395 | F(19200000, P_BI_TCXO, 1, 0, 0), |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 396 | F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), |
| 397 | F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), |
| 398 | F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), |
| 399 | F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), |
| 400 | { } |
| 401 | }; |
| 402 | |
| 403 | static struct clk_rcg2 gcc_gp1_clk_src = { |
| 404 | .cmd_rcgr = 0x64004, |
| 405 | .mnd_width = 8, |
| 406 | .hid_width = 5, |
| 407 | .parent_map = gcc_parent_map_1, |
| 408 | .freq_tbl = ftbl_gcc_gp1_clk_src, |
| 409 | .clkr.hw.init = &(struct clk_init_data){ |
| 410 | .name = "gcc_gp1_clk_src", |
| 411 | .parent_names = gcc_parent_names_1, |
| 412 | .num_parents = 5, |
| 413 | .flags = CLK_SET_RATE_PARENT, |
| 414 | .ops = &clk_rcg2_ops, |
| 415 | VDD_CX_FMAX_MAP4( |
| 416 | MIN, 19200000, |
| 417 | LOWER, 50000000, |
| 418 | LOW, 100000000, |
| 419 | NOMINAL, 200000000), |
| 420 | }, |
| 421 | }; |
| 422 | |
| 423 | static struct clk_rcg2 gcc_gp2_clk_src = { |
| 424 | .cmd_rcgr = 0x65004, |
| 425 | .mnd_width = 8, |
| 426 | .hid_width = 5, |
| 427 | .parent_map = gcc_parent_map_1, |
| 428 | .freq_tbl = ftbl_gcc_gp1_clk_src, |
| 429 | .clkr.hw.init = &(struct clk_init_data){ |
| 430 | .name = "gcc_gp2_clk_src", |
| 431 | .parent_names = gcc_parent_names_1, |
| 432 | .num_parents = 5, |
| 433 | .flags = CLK_SET_RATE_PARENT, |
| 434 | .ops = &clk_rcg2_ops, |
| 435 | VDD_CX_FMAX_MAP4( |
| 436 | MIN, 19200000, |
| 437 | LOWER, 50000000, |
| 438 | LOW, 100000000, |
| 439 | NOMINAL, 200000000), |
| 440 | }, |
| 441 | }; |
| 442 | |
| 443 | static struct clk_rcg2 gcc_gp3_clk_src = { |
| 444 | .cmd_rcgr = 0x66004, |
| 445 | .mnd_width = 8, |
| 446 | .hid_width = 5, |
| 447 | .parent_map = gcc_parent_map_1, |
| 448 | .freq_tbl = ftbl_gcc_gp1_clk_src, |
| 449 | .clkr.hw.init = &(struct clk_init_data){ |
| 450 | .name = "gcc_gp3_clk_src", |
| 451 | .parent_names = gcc_parent_names_1, |
| 452 | .num_parents = 5, |
| 453 | .flags = CLK_SET_RATE_PARENT, |
| 454 | .ops = &clk_rcg2_ops, |
| 455 | VDD_CX_FMAX_MAP4( |
| 456 | MIN, 19200000, |
| 457 | LOWER, 50000000, |
| 458 | LOW, 100000000, |
| 459 | NOMINAL, 200000000), |
| 460 | }, |
| 461 | }; |
| 462 | |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 463 | static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = { |
| 464 | F(9600000, P_BI_TCXO, 2, 0, 0), |
| 465 | F(19200000, P_BI_TCXO, 1, 0, 0), |
| 466 | { } |
| 467 | }; |
| 468 | |
| 469 | static struct clk_rcg2 gcc_pcie_0_aux_clk_src = { |
| 470 | .cmd_rcgr = 0x6b028, |
| 471 | .mnd_width = 16, |
| 472 | .hid_width = 5, |
| 473 | .parent_map = gcc_parent_map_2, |
| 474 | .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, |
| 475 | .clkr.hw.init = &(struct clk_init_data){ |
| 476 | .name = "gcc_pcie_0_aux_clk_src", |
| 477 | .parent_names = gcc_parent_names_2, |
| 478 | .num_parents = 3, |
| 479 | .flags = CLK_SET_RATE_PARENT, |
| 480 | .ops = &clk_rcg2_ops, |
| 481 | VDD_CX_FMAX_MAP2( |
| 482 | MIN, 9600000, |
| 483 | LOW, 19200000), |
| 484 | }, |
| 485 | }; |
| 486 | |
| 487 | static struct clk_rcg2 gcc_pcie_1_aux_clk_src = { |
| 488 | .cmd_rcgr = 0x8d028, |
| 489 | .mnd_width = 16, |
| 490 | .hid_width = 5, |
| 491 | .parent_map = gcc_parent_map_2, |
| 492 | .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, |
| 493 | .clkr.hw.init = &(struct clk_init_data){ |
| 494 | .name = "gcc_pcie_1_aux_clk_src", |
| 495 | .parent_names = gcc_parent_names_2, |
| 496 | .num_parents = 3, |
| 497 | .flags = CLK_SET_RATE_PARENT, |
| 498 | .ops = &clk_rcg2_ops, |
| 499 | VDD_CX_FMAX_MAP2( |
| 500 | MIN, 9600000, |
| 501 | LOW, 19200000), |
| 502 | }, |
| 503 | }; |
| 504 | |
| 505 | static const struct freq_tbl ftbl_gcc_pcie_phy_refgen_clk_src[] = { |
| 506 | F(19200000, P_BI_TCXO, 1, 0, 0), |
| 507 | F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), |
| 508 | { } |
| 509 | }; |
| 510 | |
| 511 | static struct clk_rcg2 gcc_pcie_phy_refgen_clk_src = { |
| 512 | .cmd_rcgr = 0x6f014, |
| 513 | .mnd_width = 0, |
| 514 | .hid_width = 5, |
| 515 | .parent_map = gcc_parent_map_0, |
| 516 | .freq_tbl = ftbl_gcc_pcie_phy_refgen_clk_src, |
| 517 | .clkr.hw.init = &(struct clk_init_data){ |
| 518 | .name = "gcc_pcie_phy_refgen_clk_src", |
| 519 | .parent_names = gcc_parent_names_0, |
| 520 | .num_parents = 4, |
| 521 | .flags = CLK_SET_RATE_PARENT, |
| 522 | .ops = &clk_rcg2_ops, |
| 523 | VDD_CX_FMAX_MAP2( |
| 524 | MIN, 19200000, |
| 525 | LOW, 100000000), |
| 526 | }, |
| 527 | }; |
| 528 | |
| 529 | static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = { |
Deepak Katragadda | bae7106 | 2017-05-22 14:37:11 -0700 | [diff] [blame] | 530 | F(9600000, P_BI_TCXO, 2, 0, 0), |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 531 | F(19200000, P_BI_TCXO, 1, 0, 0), |
| 532 | F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0), |
| 533 | { } |
| 534 | }; |
| 535 | |
| 536 | static struct clk_rcg2 gcc_pdm2_clk_src = { |
| 537 | .cmd_rcgr = 0x33010, |
| 538 | .mnd_width = 0, |
| 539 | .hid_width = 5, |
| 540 | .parent_map = gcc_parent_map_0, |
| 541 | .freq_tbl = ftbl_gcc_pdm2_clk_src, |
| 542 | .clkr.hw.init = &(struct clk_init_data){ |
| 543 | .name = "gcc_pdm2_clk_src", |
| 544 | .parent_names = gcc_parent_names_0, |
| 545 | .num_parents = 4, |
| 546 | .flags = CLK_SET_RATE_PARENT, |
| 547 | .ops = &clk_rcg2_ops, |
| 548 | VDD_CX_FMAX_MAP3( |
| 549 | MIN, 9600000, |
| 550 | LOWER, 19200000, |
| 551 | LOW, 60000000), |
| 552 | }, |
| 553 | }; |
| 554 | |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 555 | static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = { |
Deepak Katragadda | 125fe37 | 2017-03-01 10:28:24 -0800 | [diff] [blame] | 556 | F(7372800, P_GPLL0_OUT_EVEN, 1, 384, 15625), |
| 557 | F(14745600, P_GPLL0_OUT_EVEN, 1, 768, 15625), |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 558 | F(19200000, P_BI_TCXO, 1, 0, 0), |
Deepak Katragadda | 125fe37 | 2017-03-01 10:28:24 -0800 | [diff] [blame] | 559 | F(29491200, P_GPLL0_OUT_EVEN, 1, 1536, 15625), |
| 560 | F(32000000, P_GPLL0_OUT_EVEN, 1, 8, 75), |
Deepak Katragadda | f56802e | 2017-07-14 13:39:03 -0700 | [diff] [blame] | 561 | F(38400000, P_GPLL0_OUT_EVEN, 1, 16, 125), |
Deepak Katragadda | 125fe37 | 2017-03-01 10:28:24 -0800 | [diff] [blame] | 562 | F(48000000, P_GPLL0_OUT_EVEN, 1, 4, 25), |
| 563 | F(64000000, P_GPLL0_OUT_EVEN, 1, 16, 75), |
| 564 | F(80000000, P_GPLL0_OUT_EVEN, 1, 4, 15), |
| 565 | F(96000000, P_GPLL0_OUT_EVEN, 1, 8, 25), |
| 566 | F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0), |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 567 | { } |
| 568 | }; |
| 569 | |
Deepak Katragadda | 6c846e3 | 2017-06-07 14:09:49 -0700 | [diff] [blame] | 570 | static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src_sdm845_v2[] = { |
| 571 | F(7372800, P_GPLL0_OUT_EVEN, 1, 384, 15625), |
| 572 | F(14745600, P_GPLL0_OUT_EVEN, 1, 768, 15625), |
| 573 | F(19200000, P_BI_TCXO, 1, 0, 0), |
| 574 | F(29491200, P_GPLL0_OUT_EVEN, 1, 1536, 15625), |
| 575 | F(32000000, P_GPLL0_OUT_EVEN, 1, 8, 75), |
| 576 | F(48000000, P_GPLL0_OUT_EVEN, 1, 4, 25), |
| 577 | F(64000000, P_GPLL0_OUT_EVEN, 1, 16, 75), |
| 578 | F(80000000, P_GPLL0_OUT_EVEN, 1, 4, 15), |
| 579 | F(96000000, P_GPLL0_OUT_EVEN, 1, 8, 25), |
| 580 | F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0), |
| 581 | F(102400000, P_GPLL0_OUT_EVEN, 1, 128, 375), |
| 582 | F(112000000, P_GPLL0_OUT_EVEN, 1, 28, 75), |
| 583 | F(117964800, P_GPLL0_OUT_EVEN, 1, 6144, 15625), |
| 584 | F(120000000, P_GPLL0_OUT_EVEN, 2.5, 0, 0), |
| 585 | F(128000000, P_GPLL0_OUT_MAIN, 1, 16, 75), |
| 586 | { } |
| 587 | }; |
| 588 | |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 589 | static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = { |
| 590 | .cmd_rcgr = 0x17034, |
| 591 | .mnd_width = 16, |
| 592 | .hid_width = 5, |
| 593 | .parent_map = gcc_parent_map_0, |
| 594 | .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, |
| 595 | .enable_safe_config = true, |
| 596 | .clkr.hw.init = &(struct clk_init_data){ |
| 597 | .name = "gcc_qupv3_wrap0_s0_clk_src", |
| 598 | .parent_names = gcc_parent_names_0, |
| 599 | .num_parents = 4, |
| 600 | .flags = CLK_SET_RATE_PARENT, |
| 601 | .ops = &clk_rcg2_ops, |
Deepak Katragadda | 125fe37 | 2017-03-01 10:28:24 -0800 | [diff] [blame] | 602 | VDD_CX_FMAX_MAP3( |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 603 | MIN, 19200000, |
| 604 | LOWER, 75000000, |
Deepak Katragadda | 125fe37 | 2017-03-01 10:28:24 -0800 | [diff] [blame] | 605 | LOW, 100000000), |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 606 | }, |
| 607 | }; |
| 608 | |
| 609 | static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = { |
| 610 | .cmd_rcgr = 0x17164, |
| 611 | .mnd_width = 16, |
| 612 | .hid_width = 5, |
| 613 | .parent_map = gcc_parent_map_0, |
| 614 | .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, |
| 615 | .enable_safe_config = true, |
| 616 | .clkr.hw.init = &(struct clk_init_data){ |
| 617 | .name = "gcc_qupv3_wrap0_s1_clk_src", |
| 618 | .parent_names = gcc_parent_names_0, |
| 619 | .num_parents = 4, |
| 620 | .flags = CLK_SET_RATE_PARENT, |
| 621 | .ops = &clk_rcg2_ops, |
Deepak Katragadda | 125fe37 | 2017-03-01 10:28:24 -0800 | [diff] [blame] | 622 | VDD_CX_FMAX_MAP3( |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 623 | MIN, 19200000, |
| 624 | LOWER, 75000000, |
Deepak Katragadda | 125fe37 | 2017-03-01 10:28:24 -0800 | [diff] [blame] | 625 | LOW, 100000000), |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 626 | }, |
| 627 | }; |
| 628 | |
| 629 | static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = { |
| 630 | .cmd_rcgr = 0x17294, |
| 631 | .mnd_width = 16, |
| 632 | .hid_width = 5, |
| 633 | .parent_map = gcc_parent_map_0, |
| 634 | .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, |
| 635 | .enable_safe_config = true, |
| 636 | .clkr.hw.init = &(struct clk_init_data){ |
| 637 | .name = "gcc_qupv3_wrap0_s2_clk_src", |
| 638 | .parent_names = gcc_parent_names_0, |
| 639 | .num_parents = 4, |
| 640 | .flags = CLK_SET_RATE_PARENT, |
| 641 | .ops = &clk_rcg2_ops, |
Deepak Katragadda | 125fe37 | 2017-03-01 10:28:24 -0800 | [diff] [blame] | 642 | VDD_CX_FMAX_MAP3( |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 643 | MIN, 19200000, |
| 644 | LOWER, 75000000, |
Deepak Katragadda | 125fe37 | 2017-03-01 10:28:24 -0800 | [diff] [blame] | 645 | LOW, 100000000), |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 646 | }, |
| 647 | }; |
| 648 | |
| 649 | static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = { |
| 650 | .cmd_rcgr = 0x173c4, |
| 651 | .mnd_width = 16, |
| 652 | .hid_width = 5, |
| 653 | .parent_map = gcc_parent_map_0, |
| 654 | .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, |
| 655 | .enable_safe_config = true, |
| 656 | .clkr.hw.init = &(struct clk_init_data){ |
| 657 | .name = "gcc_qupv3_wrap0_s3_clk_src", |
| 658 | .parent_names = gcc_parent_names_0, |
| 659 | .num_parents = 4, |
| 660 | .flags = CLK_SET_RATE_PARENT, |
| 661 | .ops = &clk_rcg2_ops, |
Deepak Katragadda | 125fe37 | 2017-03-01 10:28:24 -0800 | [diff] [blame] | 662 | VDD_CX_FMAX_MAP3( |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 663 | MIN, 19200000, |
| 664 | LOWER, 75000000, |
Deepak Katragadda | 125fe37 | 2017-03-01 10:28:24 -0800 | [diff] [blame] | 665 | LOW, 100000000), |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 666 | }, |
| 667 | }; |
| 668 | |
| 669 | static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = { |
| 670 | .cmd_rcgr = 0x174f4, |
| 671 | .mnd_width = 16, |
| 672 | .hid_width = 5, |
| 673 | .parent_map = gcc_parent_map_0, |
| 674 | .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, |
| 675 | .enable_safe_config = true, |
| 676 | .clkr.hw.init = &(struct clk_init_data){ |
| 677 | .name = "gcc_qupv3_wrap0_s4_clk_src", |
| 678 | .parent_names = gcc_parent_names_0, |
| 679 | .num_parents = 4, |
| 680 | .flags = CLK_SET_RATE_PARENT, |
| 681 | .ops = &clk_rcg2_ops, |
Deepak Katragadda | 125fe37 | 2017-03-01 10:28:24 -0800 | [diff] [blame] | 682 | VDD_CX_FMAX_MAP3( |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 683 | MIN, 19200000, |
| 684 | LOWER, 75000000, |
Deepak Katragadda | 125fe37 | 2017-03-01 10:28:24 -0800 | [diff] [blame] | 685 | LOW, 100000000), |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 686 | }, |
| 687 | }; |
| 688 | |
| 689 | static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = { |
| 690 | .cmd_rcgr = 0x17624, |
| 691 | .mnd_width = 16, |
| 692 | .hid_width = 5, |
| 693 | .parent_map = gcc_parent_map_0, |
| 694 | .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, |
| 695 | .enable_safe_config = true, |
| 696 | .clkr.hw.init = &(struct clk_init_data){ |
| 697 | .name = "gcc_qupv3_wrap0_s5_clk_src", |
| 698 | .parent_names = gcc_parent_names_0, |
| 699 | .num_parents = 4, |
| 700 | .flags = CLK_SET_RATE_PARENT, |
| 701 | .ops = &clk_rcg2_ops, |
Deepak Katragadda | 125fe37 | 2017-03-01 10:28:24 -0800 | [diff] [blame] | 702 | VDD_CX_FMAX_MAP3( |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 703 | MIN, 19200000, |
| 704 | LOWER, 75000000, |
Deepak Katragadda | 125fe37 | 2017-03-01 10:28:24 -0800 | [diff] [blame] | 705 | LOW, 100000000), |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 706 | }, |
| 707 | }; |
| 708 | |
| 709 | static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = { |
| 710 | .cmd_rcgr = 0x17754, |
| 711 | .mnd_width = 16, |
| 712 | .hid_width = 5, |
| 713 | .parent_map = gcc_parent_map_0, |
| 714 | .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, |
| 715 | .enable_safe_config = true, |
| 716 | .clkr.hw.init = &(struct clk_init_data){ |
| 717 | .name = "gcc_qupv3_wrap0_s6_clk_src", |
| 718 | .parent_names = gcc_parent_names_0, |
| 719 | .num_parents = 4, |
| 720 | .flags = CLK_SET_RATE_PARENT, |
| 721 | .ops = &clk_rcg2_ops, |
Deepak Katragadda | 125fe37 | 2017-03-01 10:28:24 -0800 | [diff] [blame] | 722 | VDD_CX_FMAX_MAP3( |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 723 | MIN, 19200000, |
| 724 | LOWER, 75000000, |
Deepak Katragadda | 125fe37 | 2017-03-01 10:28:24 -0800 | [diff] [blame] | 725 | LOW, 100000000), |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 726 | }, |
| 727 | }; |
| 728 | |
| 729 | static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = { |
| 730 | .cmd_rcgr = 0x17884, |
| 731 | .mnd_width = 16, |
| 732 | .hid_width = 5, |
| 733 | .parent_map = gcc_parent_map_0, |
| 734 | .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, |
| 735 | .enable_safe_config = true, |
| 736 | .clkr.hw.init = &(struct clk_init_data){ |
| 737 | .name = "gcc_qupv3_wrap0_s7_clk_src", |
| 738 | .parent_names = gcc_parent_names_0, |
| 739 | .num_parents = 4, |
| 740 | .flags = CLK_SET_RATE_PARENT, |
| 741 | .ops = &clk_rcg2_ops, |
Deepak Katragadda | 125fe37 | 2017-03-01 10:28:24 -0800 | [diff] [blame] | 742 | VDD_CX_FMAX_MAP3( |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 743 | MIN, 19200000, |
| 744 | LOWER, 75000000, |
Deepak Katragadda | 125fe37 | 2017-03-01 10:28:24 -0800 | [diff] [blame] | 745 | LOW, 100000000), |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 746 | }, |
| 747 | }; |
| 748 | |
| 749 | static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = { |
| 750 | .cmd_rcgr = 0x18018, |
| 751 | .mnd_width = 16, |
| 752 | .hid_width = 5, |
| 753 | .parent_map = gcc_parent_map_0, |
| 754 | .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, |
| 755 | .enable_safe_config = true, |
| 756 | .clkr.hw.init = &(struct clk_init_data){ |
| 757 | .name = "gcc_qupv3_wrap1_s0_clk_src", |
| 758 | .parent_names = gcc_parent_names_0, |
| 759 | .num_parents = 4, |
| 760 | .flags = CLK_SET_RATE_PARENT, |
| 761 | .ops = &clk_rcg2_ops, |
Deepak Katragadda | 125fe37 | 2017-03-01 10:28:24 -0800 | [diff] [blame] | 762 | VDD_CX_FMAX_MAP3( |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 763 | MIN, 19200000, |
| 764 | LOWER, 75000000, |
Deepak Katragadda | 125fe37 | 2017-03-01 10:28:24 -0800 | [diff] [blame] | 765 | LOW, 100000000), |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 766 | }, |
| 767 | }; |
| 768 | |
| 769 | static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = { |
| 770 | .cmd_rcgr = 0x18148, |
| 771 | .mnd_width = 16, |
| 772 | .hid_width = 5, |
| 773 | .parent_map = gcc_parent_map_0, |
| 774 | .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, |
| 775 | .enable_safe_config = true, |
| 776 | .clkr.hw.init = &(struct clk_init_data){ |
| 777 | .name = "gcc_qupv3_wrap1_s1_clk_src", |
| 778 | .parent_names = gcc_parent_names_0, |
| 779 | .num_parents = 4, |
| 780 | .flags = CLK_SET_RATE_PARENT, |
| 781 | .ops = &clk_rcg2_ops, |
Deepak Katragadda | 125fe37 | 2017-03-01 10:28:24 -0800 | [diff] [blame] | 782 | VDD_CX_FMAX_MAP3( |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 783 | MIN, 19200000, |
| 784 | LOWER, 75000000, |
Deepak Katragadda | 125fe37 | 2017-03-01 10:28:24 -0800 | [diff] [blame] | 785 | LOW, 100000000), |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 786 | }, |
| 787 | }; |
| 788 | |
| 789 | static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = { |
| 790 | .cmd_rcgr = 0x18278, |
| 791 | .mnd_width = 16, |
| 792 | .hid_width = 5, |
| 793 | .parent_map = gcc_parent_map_0, |
| 794 | .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, |
| 795 | .enable_safe_config = true, |
| 796 | .clkr.hw.init = &(struct clk_init_data){ |
| 797 | .name = "gcc_qupv3_wrap1_s2_clk_src", |
| 798 | .parent_names = gcc_parent_names_0, |
| 799 | .num_parents = 4, |
| 800 | .flags = CLK_SET_RATE_PARENT, |
| 801 | .ops = &clk_rcg2_ops, |
Deepak Katragadda | 125fe37 | 2017-03-01 10:28:24 -0800 | [diff] [blame] | 802 | VDD_CX_FMAX_MAP3( |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 803 | MIN, 19200000, |
| 804 | LOWER, 75000000, |
Deepak Katragadda | 125fe37 | 2017-03-01 10:28:24 -0800 | [diff] [blame] | 805 | LOW, 100000000), |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 806 | }, |
| 807 | }; |
| 808 | |
| 809 | static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = { |
| 810 | .cmd_rcgr = 0x183a8, |
| 811 | .mnd_width = 16, |
| 812 | .hid_width = 5, |
| 813 | .parent_map = gcc_parent_map_0, |
| 814 | .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, |
| 815 | .enable_safe_config = true, |
| 816 | .clkr.hw.init = &(struct clk_init_data){ |
| 817 | .name = "gcc_qupv3_wrap1_s3_clk_src", |
| 818 | .parent_names = gcc_parent_names_0, |
| 819 | .num_parents = 4, |
| 820 | .flags = CLK_SET_RATE_PARENT, |
| 821 | .ops = &clk_rcg2_ops, |
Deepak Katragadda | 125fe37 | 2017-03-01 10:28:24 -0800 | [diff] [blame] | 822 | VDD_CX_FMAX_MAP3( |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 823 | MIN, 19200000, |
| 824 | LOWER, 75000000, |
Deepak Katragadda | 125fe37 | 2017-03-01 10:28:24 -0800 | [diff] [blame] | 825 | LOW, 100000000), |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 826 | }, |
| 827 | }; |
| 828 | |
| 829 | static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = { |
| 830 | .cmd_rcgr = 0x184d8, |
| 831 | .mnd_width = 16, |
| 832 | .hid_width = 5, |
| 833 | .parent_map = gcc_parent_map_0, |
| 834 | .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, |
| 835 | .enable_safe_config = true, |
| 836 | .clkr.hw.init = &(struct clk_init_data){ |
| 837 | .name = "gcc_qupv3_wrap1_s4_clk_src", |
| 838 | .parent_names = gcc_parent_names_0, |
| 839 | .num_parents = 4, |
| 840 | .flags = CLK_SET_RATE_PARENT, |
| 841 | .ops = &clk_rcg2_ops, |
Deepak Katragadda | 125fe37 | 2017-03-01 10:28:24 -0800 | [diff] [blame] | 842 | VDD_CX_FMAX_MAP3( |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 843 | MIN, 19200000, |
| 844 | LOWER, 75000000, |
Deepak Katragadda | 125fe37 | 2017-03-01 10:28:24 -0800 | [diff] [blame] | 845 | LOW, 100000000), |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 846 | }, |
| 847 | }; |
| 848 | |
| 849 | static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = { |
| 850 | .cmd_rcgr = 0x18608, |
| 851 | .mnd_width = 16, |
| 852 | .hid_width = 5, |
| 853 | .parent_map = gcc_parent_map_0, |
| 854 | .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, |
| 855 | .enable_safe_config = true, |
| 856 | .clkr.hw.init = &(struct clk_init_data){ |
| 857 | .name = "gcc_qupv3_wrap1_s5_clk_src", |
| 858 | .parent_names = gcc_parent_names_0, |
| 859 | .num_parents = 4, |
| 860 | .flags = CLK_SET_RATE_PARENT, |
| 861 | .ops = &clk_rcg2_ops, |
Deepak Katragadda | 125fe37 | 2017-03-01 10:28:24 -0800 | [diff] [blame] | 862 | VDD_CX_FMAX_MAP3( |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 863 | MIN, 19200000, |
| 864 | LOWER, 75000000, |
Deepak Katragadda | 125fe37 | 2017-03-01 10:28:24 -0800 | [diff] [blame] | 865 | LOW, 100000000), |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 866 | }, |
| 867 | }; |
| 868 | |
| 869 | static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = { |
| 870 | .cmd_rcgr = 0x18738, |
| 871 | .mnd_width = 16, |
| 872 | .hid_width = 5, |
| 873 | .parent_map = gcc_parent_map_0, |
| 874 | .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, |
| 875 | .enable_safe_config = true, |
| 876 | .clkr.hw.init = &(struct clk_init_data){ |
| 877 | .name = "gcc_qupv3_wrap1_s6_clk_src", |
| 878 | .parent_names = gcc_parent_names_0, |
| 879 | .num_parents = 4, |
| 880 | .flags = CLK_SET_RATE_PARENT, |
| 881 | .ops = &clk_rcg2_ops, |
Deepak Katragadda | 125fe37 | 2017-03-01 10:28:24 -0800 | [diff] [blame] | 882 | VDD_CX_FMAX_MAP3( |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 883 | MIN, 19200000, |
| 884 | LOWER, 75000000, |
Deepak Katragadda | 125fe37 | 2017-03-01 10:28:24 -0800 | [diff] [blame] | 885 | LOW, 100000000), |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 886 | }, |
| 887 | }; |
| 888 | |
| 889 | static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = { |
| 890 | .cmd_rcgr = 0x18868, |
| 891 | .mnd_width = 16, |
| 892 | .hid_width = 5, |
| 893 | .parent_map = gcc_parent_map_0, |
| 894 | .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, |
| 895 | .enable_safe_config = true, |
| 896 | .clkr.hw.init = &(struct clk_init_data){ |
| 897 | .name = "gcc_qupv3_wrap1_s7_clk_src", |
| 898 | .parent_names = gcc_parent_names_0, |
| 899 | .num_parents = 4, |
| 900 | .flags = CLK_SET_RATE_PARENT, |
| 901 | .ops = &clk_rcg2_ops, |
Deepak Katragadda | 125fe37 | 2017-03-01 10:28:24 -0800 | [diff] [blame] | 902 | VDD_CX_FMAX_MAP3( |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 903 | MIN, 19200000, |
| 904 | LOWER, 75000000, |
Deepak Katragadda | 125fe37 | 2017-03-01 10:28:24 -0800 | [diff] [blame] | 905 | LOW, 100000000), |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 906 | }, |
| 907 | }; |
| 908 | |
Deepak Katragadda | 443bd8d | 2017-08-28 22:30:19 +0530 | [diff] [blame] | 909 | static const struct freq_tbl ftbl_gcc_sdcc1_ice_core_clk_src[] = { |
| 910 | F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0), |
| 911 | F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), |
| 912 | F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), |
| 913 | F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), |
| 914 | { } |
| 915 | }; |
| 916 | |
| 917 | static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = { |
| 918 | .cmd_rcgr = 0x26010, |
| 919 | .mnd_width = 8, |
| 920 | .hid_width = 5, |
| 921 | .parent_map = gcc_parent_map_0, |
| 922 | .freq_tbl = ftbl_gcc_sdcc1_ice_core_clk_src, |
| 923 | .enable_safe_config = true, |
| 924 | .clkr.hw.init = &(struct clk_init_data){ |
| 925 | .name = "gcc_sdcc1_ice_core_clk_src", |
| 926 | .parent_names = gcc_parent_names_0, |
| 927 | .num_parents = 4, |
| 928 | .flags = CLK_SET_RATE_PARENT, |
| 929 | .ops = &clk_rcg2_ops, |
| 930 | VDD_CX_FMAX_MAP3( |
| 931 | MIN, 75000000, |
| 932 | LOW, 150000000, |
| 933 | NOMINAL, 300000000), |
| 934 | }, |
| 935 | }; |
| 936 | |
| 937 | static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = { |
| 938 | F(144000, P_BI_TCXO, 16, 3, 25), |
| 939 | F(400000, P_BI_TCXO, 12, 1, 4), |
| 940 | F(20000000, P_GPLL0_OUT_EVEN, 5, 1, 3), |
| 941 | F(25000000, P_GPLL0_OUT_EVEN, 6, 1, 2), |
| 942 | F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), |
| 943 | F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), |
| 944 | F(192000000, P_GPLL6_OUT_MAIN, 2, 0, 0), |
| 945 | F(384000000, P_GPLL6_OUT_MAIN, 1, 0, 0), |
| 946 | { } |
| 947 | }; |
| 948 | |
| 949 | static struct clk_rcg2 gcc_sdcc1_apps_clk_src = { |
| 950 | .cmd_rcgr = 0x26028, |
| 951 | .mnd_width = 8, |
| 952 | .hid_width = 5, |
| 953 | .parent_map = gcc_parent_map_7, |
| 954 | .freq_tbl = ftbl_gcc_sdcc1_apps_clk_src, |
| 955 | .enable_safe_config = true, |
| 956 | .clkr.hw.init = &(struct clk_init_data){ |
| 957 | .name = "gcc_sdcc1_apps_clk_src", |
| 958 | .parent_names = gcc_parent_names_11, |
| 959 | .num_parents = 5, |
| 960 | .flags = CLK_SET_RATE_PARENT, |
| 961 | .ops = &clk_rcg2_ops, |
| 962 | VDD_CX_FMAX_MAP4( |
| 963 | MIN, 19200000, |
| 964 | LOWER, 50000000, |
| 965 | LOW, 100000000, |
| 966 | NOMINAL, 384000000), |
| 967 | }, |
| 968 | }; |
| 969 | |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 970 | static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = { |
Deepak Katragadda | 5d08d67 | 2017-04-18 09:38:30 -0700 | [diff] [blame] | 971 | F(400000, P_BI_TCXO, 12, 1, 4), |
Deepak Katragadda | bae7106 | 2017-05-22 14:37:11 -0700 | [diff] [blame] | 972 | F(9600000, P_BI_TCXO, 2, 0, 0), |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 973 | F(19200000, P_BI_TCXO, 1, 0, 0), |
Deepak Katragadda | 47e084f | 2017-06-06 15:08:26 -0700 | [diff] [blame] | 974 | F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), |
| 975 | F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 976 | F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), |
Deepak Katragadda | f56802e | 2017-07-14 13:39:03 -0700 | [diff] [blame] | 977 | F(201500000, P_GPLL4_OUT_MAIN, 4, 0, 0), |
| 978 | { } |
| 979 | }; |
| 980 | |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 981 | static struct clk_rcg2 gcc_sdcc2_apps_clk_src = { |
| 982 | .cmd_rcgr = 0x1400c, |
| 983 | .mnd_width = 8, |
| 984 | .hid_width = 5, |
Deepak Katragadda | f56802e | 2017-07-14 13:39:03 -0700 | [diff] [blame] | 985 | .parent_map = gcc_parent_map_10, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 986 | .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src, |
| 987 | .enable_safe_config = true, |
| 988 | .clkr.hw.init = &(struct clk_init_data){ |
| 989 | .name = "gcc_sdcc2_apps_clk_src", |
Deepak Katragadda | f56802e | 2017-07-14 13:39:03 -0700 | [diff] [blame] | 990 | .parent_names = gcc_parent_names_10, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 991 | .num_parents = 5, |
| 992 | .flags = CLK_SET_RATE_PARENT, |
| 993 | .ops = &clk_rcg2_ops, |
| 994 | VDD_CX_FMAX_MAP4( |
| 995 | MIN, 9600000, |
| 996 | LOWER, 19200000, |
| 997 | LOW, 100000000, |
Deepak Katragadda | f56802e | 2017-07-14 13:39:03 -0700 | [diff] [blame] | 998 | LOW_L1, 201500000), |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 999 | }, |
| 1000 | }; |
| 1001 | |
| 1002 | static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = { |
Deepak Katragadda | 5d08d67 | 2017-04-18 09:38:30 -0700 | [diff] [blame] | 1003 | F(400000, P_BI_TCXO, 12, 1, 4), |
Deepak Katragadda | bae7106 | 2017-05-22 14:37:11 -0700 | [diff] [blame] | 1004 | F(9600000, P_BI_TCXO, 2, 0, 0), |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 1005 | F(19200000, P_BI_TCXO, 1, 0, 0), |
Deepak Katragadda | 5d08d67 | 2017-04-18 09:38:30 -0700 | [diff] [blame] | 1006 | F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2), |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 1007 | F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0), |
| 1008 | F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), |
| 1009 | { } |
| 1010 | }; |
| 1011 | |
Deepak Katragadda | 443bd8d | 2017-08-28 22:30:19 +0530 | [diff] [blame] | 1012 | static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src_sdm670[] = { |
| 1013 | F(400000, P_BI_TCXO, 12, 1, 4), |
| 1014 | F(9600000, P_BI_TCXO, 2, 0, 0), |
| 1015 | F(19200000, P_BI_TCXO, 1, 0, 0), |
| 1016 | F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), |
| 1017 | F(33333333, P_GPLL0_OUT_EVEN, 9, 0, 0), |
| 1018 | F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0), |
| 1019 | F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), |
| 1020 | { } |
| 1021 | }; |
| 1022 | |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 1023 | static struct clk_rcg2 gcc_sdcc4_apps_clk_src = { |
| 1024 | .cmd_rcgr = 0x1600c, |
| 1025 | .mnd_width = 8, |
| 1026 | .hid_width = 5, |
Deepak Katragadda | 443bd8d | 2017-08-28 22:30:19 +0530 | [diff] [blame] | 1027 | .parent_map = gcc_parent_map_0, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 1028 | .freq_tbl = ftbl_gcc_sdcc4_apps_clk_src, |
Deepak Katragadda | 125fe37 | 2017-03-01 10:28:24 -0800 | [diff] [blame] | 1029 | .enable_safe_config = true, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 1030 | .clkr.hw.init = &(struct clk_init_data){ |
| 1031 | .name = "gcc_sdcc4_apps_clk_src", |
Deepak Katragadda | 443bd8d | 2017-08-28 22:30:19 +0530 | [diff] [blame] | 1032 | .parent_names = gcc_parent_names_0, |
| 1033 | .num_parents = 4, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 1034 | .flags = CLK_SET_RATE_PARENT, |
| 1035 | .ops = &clk_rcg2_ops, |
| 1036 | VDD_CX_FMAX_MAP4( |
| 1037 | MIN, 9600000, |
| 1038 | LOWER, 19200000, |
| 1039 | LOW, 50000000, |
| 1040 | NOMINAL, 100000000), |
| 1041 | }, |
| 1042 | }; |
| 1043 | |
| 1044 | static const struct freq_tbl ftbl_gcc_tsif_ref_clk_src[] = { |
| 1045 | F(105495, P_BI_TCXO, 2, 1, 91), |
| 1046 | { } |
| 1047 | }; |
| 1048 | |
| 1049 | static struct clk_rcg2 gcc_tsif_ref_clk_src = { |
| 1050 | .cmd_rcgr = 0x36010, |
| 1051 | .mnd_width = 8, |
| 1052 | .hid_width = 5, |
Deepak Katragadda | 125fe37 | 2017-03-01 10:28:24 -0800 | [diff] [blame] | 1053 | .parent_map = gcc_parent_map_6, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 1054 | .freq_tbl = ftbl_gcc_tsif_ref_clk_src, |
| 1055 | .clkr.hw.init = &(struct clk_init_data){ |
| 1056 | .name = "gcc_tsif_ref_clk_src", |
Deepak Katragadda | 125fe37 | 2017-03-01 10:28:24 -0800 | [diff] [blame] | 1057 | .parent_names = gcc_parent_names_6, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 1058 | .num_parents = 5, |
| 1059 | .flags = CLK_SET_RATE_PARENT, |
| 1060 | .ops = &clk_rcg2_ops, |
| 1061 | VDD_CX_FMAX_MAP1( |
| 1062 | MIN, 105495), |
| 1063 | }, |
| 1064 | }; |
| 1065 | |
Deepak Katragadda | bae7106 | 2017-05-22 14:37:11 -0700 | [diff] [blame] | 1066 | static const struct freq_tbl ftbl_gcc_ufs_card_axi_clk_src[] = { |
| 1067 | F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), |
| 1068 | F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), |
| 1069 | F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), |
| 1070 | F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), |
| 1071 | { } |
| 1072 | }; |
| 1073 | |
Deepak Katragadda | 6c846e3 | 2017-06-07 14:09:49 -0700 | [diff] [blame] | 1074 | static const struct freq_tbl ftbl_gcc_ufs_card_axi_clk_src_sdm845_v2[] = { |
| 1075 | F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), |
| 1076 | F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), |
| 1077 | F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), |
| 1078 | F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), |
| 1079 | F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), |
| 1080 | { } |
| 1081 | }; |
| 1082 | |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 1083 | static struct clk_rcg2 gcc_ufs_card_axi_clk_src = { |
| 1084 | .cmd_rcgr = 0x7501c, |
| 1085 | .mnd_width = 8, |
| 1086 | .hid_width = 5, |
| 1087 | .parent_map = gcc_parent_map_0, |
Deepak Katragadda | bae7106 | 2017-05-22 14:37:11 -0700 | [diff] [blame] | 1088 | .freq_tbl = ftbl_gcc_ufs_card_axi_clk_src, |
Deepak Katragadda | 536caff | 2017-04-04 17:47:56 -0700 | [diff] [blame] | 1089 | .flags = FORCE_ENABLE_RCG, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 1090 | .clkr.hw.init = &(struct clk_init_data){ |
| 1091 | .name = "gcc_ufs_card_axi_clk_src", |
| 1092 | .parent_names = gcc_parent_names_0, |
| 1093 | .num_parents = 4, |
| 1094 | .flags = CLK_SET_RATE_PARENT, |
| 1095 | .ops = &clk_rcg2_ops, |
Deepak Katragadda | 125fe37 | 2017-03-01 10:28:24 -0800 | [diff] [blame] | 1096 | VDD_CX_FMAX_MAP3( |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 1097 | MIN, 50000000, |
| 1098 | LOW, 100000000, |
Deepak Katragadda | 125fe37 | 2017-03-01 10:28:24 -0800 | [diff] [blame] | 1099 | NOMINAL, 200000000), |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 1100 | }, |
| 1101 | }; |
| 1102 | |
| 1103 | static const struct freq_tbl ftbl_gcc_ufs_card_ice_core_clk_src[] = { |
| 1104 | F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0), |
| 1105 | F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0), |
| 1106 | F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), |
| 1107 | F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), |
| 1108 | { } |
| 1109 | }; |
| 1110 | |
| 1111 | static struct clk_rcg2 gcc_ufs_card_ice_core_clk_src = { |
| 1112 | .cmd_rcgr = 0x7505c, |
| 1113 | .mnd_width = 0, |
| 1114 | .hid_width = 5, |
| 1115 | .parent_map = gcc_parent_map_0, |
| 1116 | .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src, |
Deepak Katragadda | 536caff | 2017-04-04 17:47:56 -0700 | [diff] [blame] | 1117 | .flags = FORCE_ENABLE_RCG, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 1118 | .clkr.hw.init = &(struct clk_init_data){ |
| 1119 | .name = "gcc_ufs_card_ice_core_clk_src", |
| 1120 | .parent_names = gcc_parent_names_0, |
| 1121 | .num_parents = 4, |
| 1122 | .flags = CLK_SET_RATE_PARENT, |
| 1123 | .ops = &clk_rcg2_ops, |
| 1124 | VDD_CX_FMAX_MAP3( |
| 1125 | MIN, 75000000, |
| 1126 | LOW, 150000000, |
| 1127 | NOMINAL, 300000000), |
| 1128 | }, |
| 1129 | }; |
| 1130 | |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 1131 | static struct clk_rcg2 gcc_ufs_card_phy_aux_clk_src = { |
| 1132 | .cmd_rcgr = 0x75090, |
| 1133 | .mnd_width = 0, |
| 1134 | .hid_width = 5, |
| 1135 | .parent_map = gcc_parent_map_4, |
Deepak Katragadda | 125fe37 | 2017-03-01 10:28:24 -0800 | [diff] [blame] | 1136 | .freq_tbl = ftbl_gcc_cpuss_rbcpr_clk_src, |
Deepak Katragadda | 536caff | 2017-04-04 17:47:56 -0700 | [diff] [blame] | 1137 | .flags = FORCE_ENABLE_RCG, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 1138 | .clkr.hw.init = &(struct clk_init_data){ |
| 1139 | .name = "gcc_ufs_card_phy_aux_clk_src", |
| 1140 | .parent_names = gcc_parent_names_4, |
| 1141 | .num_parents = 2, |
| 1142 | .flags = CLK_SET_RATE_PARENT, |
| 1143 | .ops = &clk_rcg2_ops, |
| 1144 | VDD_CX_FMAX_MAP1( |
| 1145 | MIN, 19200000), |
| 1146 | }, |
| 1147 | }; |
| 1148 | |
| 1149 | static const struct freq_tbl ftbl_gcc_ufs_card_unipro_core_clk_src[] = { |
| 1150 | F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0), |
| 1151 | F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0), |
| 1152 | F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), |
| 1153 | { } |
| 1154 | }; |
| 1155 | |
| 1156 | static struct clk_rcg2 gcc_ufs_card_unipro_core_clk_src = { |
| 1157 | .cmd_rcgr = 0x75074, |
| 1158 | .mnd_width = 0, |
| 1159 | .hid_width = 5, |
| 1160 | .parent_map = gcc_parent_map_0, |
| 1161 | .freq_tbl = ftbl_gcc_ufs_card_unipro_core_clk_src, |
Deepak Katragadda | 536caff | 2017-04-04 17:47:56 -0700 | [diff] [blame] | 1162 | .flags = FORCE_ENABLE_RCG, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 1163 | .clkr.hw.init = &(struct clk_init_data){ |
| 1164 | .name = "gcc_ufs_card_unipro_core_clk_src", |
| 1165 | .parent_names = gcc_parent_names_0, |
| 1166 | .num_parents = 4, |
| 1167 | .flags = CLK_SET_RATE_PARENT, |
| 1168 | .ops = &clk_rcg2_ops, |
| 1169 | VDD_CX_FMAX_MAP3( |
| 1170 | MIN, 37500000, |
| 1171 | LOW, 75000000, |
| 1172 | NOMINAL, 150000000), |
| 1173 | }, |
| 1174 | }; |
| 1175 | |
Deepak Katragadda | 125fe37 | 2017-03-01 10:28:24 -0800 | [diff] [blame] | 1176 | static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = { |
| 1177 | F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), |
| 1178 | F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), |
| 1179 | F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), |
| 1180 | F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), |
| 1181 | F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), |
| 1182 | { } |
| 1183 | }; |
| 1184 | |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 1185 | static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = { |
| 1186 | .cmd_rcgr = 0x7701c, |
| 1187 | .mnd_width = 8, |
| 1188 | .hid_width = 5, |
| 1189 | .parent_map = gcc_parent_map_0, |
Deepak Katragadda | 125fe37 | 2017-03-01 10:28:24 -0800 | [diff] [blame] | 1190 | .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src, |
Deepak Katragadda | 536caff | 2017-04-04 17:47:56 -0700 | [diff] [blame] | 1191 | .flags = FORCE_ENABLE_RCG, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 1192 | .clkr.hw.init = &(struct clk_init_data){ |
| 1193 | .name = "gcc_ufs_phy_axi_clk_src", |
| 1194 | .parent_names = gcc_parent_names_0, |
| 1195 | .num_parents = 4, |
| 1196 | .flags = CLK_SET_RATE_PARENT, |
| 1197 | .ops = &clk_rcg2_ops, |
| 1198 | VDD_CX_FMAX_MAP4( |
| 1199 | MIN, 50000000, |
| 1200 | LOW, 100000000, |
| 1201 | NOMINAL, 200000000, |
| 1202 | HIGH, 240000000), |
| 1203 | }, |
| 1204 | }; |
| 1205 | |
| 1206 | static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = { |
| 1207 | .cmd_rcgr = 0x7705c, |
| 1208 | .mnd_width = 0, |
| 1209 | .hid_width = 5, |
| 1210 | .parent_map = gcc_parent_map_0, |
| 1211 | .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src, |
Deepak Katragadda | 536caff | 2017-04-04 17:47:56 -0700 | [diff] [blame] | 1212 | .flags = FORCE_ENABLE_RCG, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 1213 | .clkr.hw.init = &(struct clk_init_data){ |
| 1214 | .name = "gcc_ufs_phy_ice_core_clk_src", |
| 1215 | .parent_names = gcc_parent_names_0, |
| 1216 | .num_parents = 4, |
| 1217 | .flags = CLK_SET_RATE_PARENT, |
| 1218 | .ops = &clk_rcg2_ops, |
| 1219 | VDD_CX_FMAX_MAP3( |
| 1220 | MIN, 75000000, |
| 1221 | LOW, 150000000, |
| 1222 | NOMINAL, 300000000), |
| 1223 | }, |
| 1224 | }; |
| 1225 | |
| 1226 | static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = { |
| 1227 | .cmd_rcgr = 0x77090, |
| 1228 | .mnd_width = 0, |
| 1229 | .hid_width = 5, |
| 1230 | .parent_map = gcc_parent_map_4, |
| 1231 | .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, |
Deepak Katragadda | 536caff | 2017-04-04 17:47:56 -0700 | [diff] [blame] | 1232 | .flags = FORCE_ENABLE_RCG, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 1233 | .clkr.hw.init = &(struct clk_init_data){ |
| 1234 | .name = "gcc_ufs_phy_phy_aux_clk_src", |
| 1235 | .parent_names = gcc_parent_names_4, |
| 1236 | .num_parents = 2, |
| 1237 | .flags = CLK_SET_RATE_PARENT, |
| 1238 | .ops = &clk_rcg2_ops, |
| 1239 | VDD_CX_FMAX_MAP1( |
| 1240 | MIN, 19200000), |
| 1241 | }, |
| 1242 | }; |
| 1243 | |
| 1244 | static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = { |
| 1245 | .cmd_rcgr = 0x77074, |
| 1246 | .mnd_width = 0, |
| 1247 | .hid_width = 5, |
| 1248 | .parent_map = gcc_parent_map_0, |
| 1249 | .freq_tbl = ftbl_gcc_ufs_card_unipro_core_clk_src, |
Deepak Katragadda | 536caff | 2017-04-04 17:47:56 -0700 | [diff] [blame] | 1250 | .flags = FORCE_ENABLE_RCG, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 1251 | .clkr.hw.init = &(struct clk_init_data){ |
| 1252 | .name = "gcc_ufs_phy_unipro_core_clk_src", |
| 1253 | .parent_names = gcc_parent_names_0, |
| 1254 | .num_parents = 4, |
| 1255 | .flags = CLK_SET_RATE_PARENT, |
| 1256 | .ops = &clk_rcg2_ops, |
| 1257 | VDD_CX_FMAX_MAP3( |
| 1258 | MIN, 37500000, |
| 1259 | LOW, 75000000, |
| 1260 | NOMINAL, 150000000), |
| 1261 | }, |
| 1262 | }; |
| 1263 | |
| 1264 | static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = { |
| 1265 | F(33333333, P_GPLL0_OUT_EVEN, 9, 0, 0), |
| 1266 | F(66666667, P_GPLL0_OUT_EVEN, 4.5, 0, 0), |
| 1267 | F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0), |
| 1268 | F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), |
| 1269 | F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), |
| 1270 | { } |
| 1271 | }; |
| 1272 | |
| 1273 | static struct clk_rcg2 gcc_usb30_prim_master_clk_src = { |
| 1274 | .cmd_rcgr = 0xf018, |
| 1275 | .mnd_width = 8, |
| 1276 | .hid_width = 5, |
| 1277 | .parent_map = gcc_parent_map_0, |
| 1278 | .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src, |
| 1279 | .enable_safe_config = true, |
| 1280 | .clkr.hw.init = &(struct clk_init_data){ |
| 1281 | .name = "gcc_usb30_prim_master_clk_src", |
| 1282 | .parent_names = gcc_parent_names_0, |
| 1283 | .num_parents = 4, |
| 1284 | .flags = CLK_SET_RATE_PARENT, |
| 1285 | .ops = &clk_rcg2_ops, |
| 1286 | VDD_CX_FMAX_MAP5( |
| 1287 | MIN, 33333333, |
| 1288 | LOWER, 66666667, |
| 1289 | LOW, 133333333, |
| 1290 | NOMINAL, 200000000, |
| 1291 | HIGH, 240000000), |
| 1292 | }, |
| 1293 | }; |
| 1294 | |
| 1295 | static const struct freq_tbl ftbl_gcc_usb30_prim_mock_utmi_clk_src[] = { |
Deepak Katragadda | bae7106 | 2017-05-22 14:37:11 -0700 | [diff] [blame] | 1296 | F(19200000, P_BI_TCXO, 1, 0, 0), |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 1297 | F(20000000, P_GPLL0_OUT_EVEN, 15, 0, 0), |
| 1298 | F(40000000, P_GPLL0_OUT_EVEN, 7.5, 0, 0), |
| 1299 | F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0), |
| 1300 | { } |
| 1301 | }; |
| 1302 | |
| 1303 | static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = { |
| 1304 | .cmd_rcgr = 0xf030, |
| 1305 | .mnd_width = 0, |
| 1306 | .hid_width = 5, |
| 1307 | .parent_map = gcc_parent_map_0, |
| 1308 | .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src, |
| 1309 | .enable_safe_config = true, |
| 1310 | .clkr.hw.init = &(struct clk_init_data){ |
| 1311 | .name = "gcc_usb30_prim_mock_utmi_clk_src", |
| 1312 | .parent_names = gcc_parent_names_0, |
| 1313 | .num_parents = 4, |
| 1314 | .flags = CLK_SET_RATE_PARENT, |
| 1315 | .ops = &clk_rcg2_ops, |
| 1316 | VDD_CX_FMAX_MAP3( |
| 1317 | MIN, 19200000, |
| 1318 | LOWER, 40000000, |
| 1319 | LOW, 60000000), |
| 1320 | }, |
| 1321 | }; |
| 1322 | |
| 1323 | static struct clk_rcg2 gcc_usb30_sec_master_clk_src = { |
| 1324 | .cmd_rcgr = 0x10018, |
| 1325 | .mnd_width = 8, |
| 1326 | .hid_width = 5, |
| 1327 | .parent_map = gcc_parent_map_0, |
| 1328 | .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src, |
| 1329 | .clkr.hw.init = &(struct clk_init_data){ |
| 1330 | .name = "gcc_usb30_sec_master_clk_src", |
| 1331 | .parent_names = gcc_parent_names_0, |
| 1332 | .num_parents = 4, |
| 1333 | .flags = CLK_SET_RATE_PARENT, |
| 1334 | .ops = &clk_rcg2_ops, |
| 1335 | VDD_CX_FMAX_MAP5( |
| 1336 | MIN, 33333333, |
| 1337 | LOWER, 66666667, |
| 1338 | LOW, 133333333, |
| 1339 | NOMINAL, 200000000, |
| 1340 | HIGH, 240000000), |
| 1341 | }, |
| 1342 | }; |
| 1343 | |
| 1344 | static struct clk_rcg2 gcc_usb30_sec_mock_utmi_clk_src = { |
| 1345 | .cmd_rcgr = 0x10030, |
| 1346 | .mnd_width = 0, |
| 1347 | .hid_width = 5, |
| 1348 | .parent_map = gcc_parent_map_0, |
| 1349 | .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src, |
| 1350 | .clkr.hw.init = &(struct clk_init_data){ |
| 1351 | .name = "gcc_usb30_sec_mock_utmi_clk_src", |
| 1352 | .parent_names = gcc_parent_names_0, |
| 1353 | .num_parents = 4, |
| 1354 | .flags = CLK_SET_RATE_PARENT, |
| 1355 | .ops = &clk_rcg2_ops, |
| 1356 | VDD_CX_FMAX_MAP3( |
| 1357 | MIN, 19200000, |
| 1358 | LOWER, 40000000, |
| 1359 | LOW, 60000000), |
| 1360 | }, |
| 1361 | }; |
| 1362 | |
| 1363 | static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = { |
| 1364 | .cmd_rcgr = 0xf05c, |
| 1365 | .mnd_width = 0, |
| 1366 | .hid_width = 5, |
| 1367 | .parent_map = gcc_parent_map_2, |
Deepak Katragadda | 125fe37 | 2017-03-01 10:28:24 -0800 | [diff] [blame] | 1368 | .freq_tbl = ftbl_gcc_cpuss_rbcpr_clk_src, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 1369 | .clkr.hw.init = &(struct clk_init_data){ |
| 1370 | .name = "gcc_usb3_prim_phy_aux_clk_src", |
| 1371 | .parent_names = gcc_parent_names_2, |
| 1372 | .num_parents = 3, |
| 1373 | .flags = CLK_SET_RATE_PARENT, |
| 1374 | .ops = &clk_rcg2_ops, |
| 1375 | VDD_CX_FMAX_MAP1( |
| 1376 | MIN, 19200000), |
| 1377 | }, |
| 1378 | }; |
| 1379 | |
| 1380 | static struct clk_rcg2 gcc_usb3_sec_phy_aux_clk_src = { |
| 1381 | .cmd_rcgr = 0x1005c, |
| 1382 | .mnd_width = 0, |
| 1383 | .hid_width = 5, |
| 1384 | .parent_map = gcc_parent_map_2, |
Deepak Katragadda | 125fe37 | 2017-03-01 10:28:24 -0800 | [diff] [blame] | 1385 | .freq_tbl = ftbl_gcc_cpuss_rbcpr_clk_src, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 1386 | .enable_safe_config = true, |
| 1387 | .clkr.hw.init = &(struct clk_init_data){ |
| 1388 | .name = "gcc_usb3_sec_phy_aux_clk_src", |
| 1389 | .parent_names = gcc_parent_names_2, |
| 1390 | .num_parents = 3, |
| 1391 | .flags = CLK_SET_RATE_PARENT, |
| 1392 | .ops = &clk_rcg2_ops, |
| 1393 | VDD_CX_FMAX_MAP1( |
| 1394 | MIN, 19200000), |
| 1395 | }, |
| 1396 | }; |
| 1397 | |
Deepak Katragadda | 87732a1 | 2017-07-18 12:07:17 -0700 | [diff] [blame] | 1398 | static struct clk_rcg2 gcc_vs_ctrl_clk_src = { |
| 1399 | .cmd_rcgr = 0x7a030, |
| 1400 | .mnd_width = 0, |
| 1401 | .hid_width = 5, |
| 1402 | .parent_map = gcc_parent_map_3, |
| 1403 | .freq_tbl = ftbl_gcc_cpuss_rbcpr_clk_src, |
| 1404 | .clkr.hw.init = &(struct clk_init_data){ |
| 1405 | .name = "gcc_vs_ctrl_clk_src", |
| 1406 | .parent_names = gcc_parent_names_3, |
| 1407 | .num_parents = 3, |
| 1408 | .flags = CLK_SET_RATE_PARENT, |
| 1409 | .ops = &clk_rcg2_ops, |
| 1410 | VDD_CX_FMAX_MAP1( |
| 1411 | MIN, 19200000), |
| 1412 | }, |
| 1413 | }; |
| 1414 | |
| 1415 | static const struct freq_tbl ftbl_gcc_vsensor_clk_src[] = { |
| 1416 | F(19200000, P_BI_TCXO, 1, 0, 0), |
| 1417 | F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), |
| 1418 | F(600000000, P_GPLL0_OUT_MAIN, 1, 0, 0), |
| 1419 | { } |
| 1420 | }; |
| 1421 | |
| 1422 | static struct clk_rcg2 gcc_vsensor_clk_src = { |
| 1423 | .cmd_rcgr = 0x7a018, |
| 1424 | .mnd_width = 0, |
| 1425 | .hid_width = 5, |
| 1426 | .parent_map = gcc_parent_map_9, |
| 1427 | .freq_tbl = ftbl_gcc_vsensor_clk_src, |
| 1428 | .clkr.hw.init = &(struct clk_init_data){ |
| 1429 | .name = "gcc_vsensor_clk_src", |
| 1430 | .parent_names = gcc_parent_names_9, |
| 1431 | .num_parents = 4, |
| 1432 | .flags = CLK_SET_RATE_PARENT, |
| 1433 | .ops = &clk_rcg2_ops, |
| 1434 | VDD_CX_FMAX_MAP3( |
| 1435 | MIN, 19200000, |
| 1436 | LOW, 300000000, |
| 1437 | LOW_L1, 600000000), |
| 1438 | }, |
| 1439 | }; |
| 1440 | |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 1441 | static struct clk_branch gcc_aggre_noc_pcie_tbu_clk = { |
| 1442 | .halt_reg = 0x90014, |
| 1443 | .halt_check = BRANCH_HALT, |
| 1444 | .clkr = { |
| 1445 | .enable_reg = 0x90014, |
| 1446 | .enable_mask = BIT(0), |
| 1447 | .hw.init = &(struct clk_init_data){ |
| 1448 | .name = "gcc_aggre_noc_pcie_tbu_clk", |
| 1449 | .ops = &clk_branch2_ops, |
| 1450 | }, |
| 1451 | }, |
| 1452 | }; |
| 1453 | |
| 1454 | static struct clk_branch gcc_aggre_ufs_card_axi_clk = { |
| 1455 | .halt_reg = 0x82028, |
| 1456 | .halt_check = BRANCH_HALT, |
Deepak Katragadda | b1886f4 | 2017-06-19 11:52:32 -0700 | [diff] [blame] | 1457 | .hwcg_reg = 0x82028, |
| 1458 | .hwcg_bit = 1, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 1459 | .clkr = { |
| 1460 | .enable_reg = 0x82028, |
| 1461 | .enable_mask = BIT(0), |
| 1462 | .hw.init = &(struct clk_init_data){ |
| 1463 | .name = "gcc_aggre_ufs_card_axi_clk", |
| 1464 | .parent_names = (const char *[]){ |
| 1465 | "gcc_ufs_card_axi_clk_src", |
| 1466 | }, |
| 1467 | .num_parents = 1, |
| 1468 | .flags = CLK_SET_RATE_PARENT, |
| 1469 | .ops = &clk_branch2_ops, |
| 1470 | }, |
| 1471 | }, |
| 1472 | }; |
| 1473 | |
Deepak Katragadda | 536caff | 2017-04-04 17:47:56 -0700 | [diff] [blame] | 1474 | static struct clk_branch gcc_aggre_ufs_card_axi_hw_ctl_clk = { |
| 1475 | .halt_reg = 0x82028, |
| 1476 | .clkr = { |
| 1477 | .enable_reg = 0x82028, |
| 1478 | .enable_mask = BIT(1), |
| 1479 | .hw.init = &(struct clk_init_data){ |
| 1480 | .name = "gcc_aggre_ufs_card_axi_hw_ctl_clk", |
| 1481 | .parent_names = (const char *[]){ |
| 1482 | "gcc_aggre_ufs_card_axi_clk", |
| 1483 | }, |
| 1484 | .num_parents = 1, |
| 1485 | .flags = CLK_SET_RATE_PARENT, |
| 1486 | .ops = &clk_branch2_hw_ctl_ops, |
| 1487 | }, |
| 1488 | }, |
| 1489 | }; |
| 1490 | |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 1491 | static struct clk_branch gcc_aggre_ufs_phy_axi_clk = { |
| 1492 | .halt_reg = 0x82024, |
| 1493 | .halt_check = BRANCH_HALT, |
Deepak Katragadda | b1886f4 | 2017-06-19 11:52:32 -0700 | [diff] [blame] | 1494 | .hwcg_reg = 0x82024, |
| 1495 | .hwcg_bit = 1, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 1496 | .clkr = { |
| 1497 | .enable_reg = 0x82024, |
| 1498 | .enable_mask = BIT(0), |
| 1499 | .hw.init = &(struct clk_init_data){ |
| 1500 | .name = "gcc_aggre_ufs_phy_axi_clk", |
| 1501 | .parent_names = (const char *[]){ |
| 1502 | "gcc_ufs_phy_axi_clk_src", |
| 1503 | }, |
| 1504 | .num_parents = 1, |
| 1505 | .flags = CLK_SET_RATE_PARENT, |
| 1506 | .ops = &clk_branch2_ops, |
| 1507 | }, |
| 1508 | }, |
| 1509 | }; |
| 1510 | |
Deepak Katragadda | 536caff | 2017-04-04 17:47:56 -0700 | [diff] [blame] | 1511 | static struct clk_branch gcc_aggre_ufs_phy_axi_hw_ctl_clk = { |
| 1512 | .halt_reg = 0x82024, |
| 1513 | .clkr = { |
| 1514 | .enable_reg = 0x82024, |
| 1515 | .enable_mask = BIT(1), |
| 1516 | .hw.init = &(struct clk_init_data){ |
| 1517 | .name = "gcc_aggre_ufs_phy_axi_hw_ctl_clk", |
| 1518 | .parent_names = (const char *[]){ |
| 1519 | "gcc_aggre_ufs_phy_axi_clk", |
| 1520 | }, |
| 1521 | .num_parents = 1, |
| 1522 | .flags = CLK_SET_RATE_PARENT, |
| 1523 | .ops = &clk_branch2_hw_ctl_ops, |
| 1524 | }, |
| 1525 | }, |
| 1526 | }; |
| 1527 | |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 1528 | static struct clk_branch gcc_aggre_usb3_prim_axi_clk = { |
| 1529 | .halt_reg = 0x8201c, |
| 1530 | .halt_check = BRANCH_HALT, |
| 1531 | .clkr = { |
| 1532 | .enable_reg = 0x8201c, |
| 1533 | .enable_mask = BIT(0), |
| 1534 | .hw.init = &(struct clk_init_data){ |
| 1535 | .name = "gcc_aggre_usb3_prim_axi_clk", |
| 1536 | .parent_names = (const char *[]){ |
| 1537 | "gcc_usb30_prim_master_clk_src", |
| 1538 | }, |
| 1539 | .num_parents = 1, |
| 1540 | .flags = CLK_SET_RATE_PARENT, |
| 1541 | .ops = &clk_branch2_ops, |
| 1542 | }, |
| 1543 | }, |
| 1544 | }; |
| 1545 | |
| 1546 | static struct clk_branch gcc_aggre_usb3_sec_axi_clk = { |
| 1547 | .halt_reg = 0x82020, |
| 1548 | .halt_check = BRANCH_HALT, |
| 1549 | .clkr = { |
| 1550 | .enable_reg = 0x82020, |
| 1551 | .enable_mask = BIT(0), |
| 1552 | .hw.init = &(struct clk_init_data){ |
| 1553 | .name = "gcc_aggre_usb3_sec_axi_clk", |
| 1554 | .parent_names = (const char *[]){ |
| 1555 | "gcc_usb30_sec_master_clk_src", |
| 1556 | }, |
| 1557 | .num_parents = 1, |
| 1558 | .flags = CLK_SET_RATE_PARENT, |
| 1559 | .ops = &clk_branch2_ops, |
| 1560 | }, |
| 1561 | }, |
| 1562 | }; |
| 1563 | |
Deepak Katragadda | 87732a1 | 2017-07-18 12:07:17 -0700 | [diff] [blame] | 1564 | static struct clk_branch gcc_apc_vs_clk = { |
| 1565 | .halt_reg = 0x7a050, |
| 1566 | .halt_check = BRANCH_HALT, |
| 1567 | .clkr = { |
| 1568 | .enable_reg = 0x7a050, |
| 1569 | .enable_mask = BIT(0), |
| 1570 | .hw.init = &(struct clk_init_data){ |
| 1571 | .name = "gcc_apc_vs_clk", |
| 1572 | .parent_names = (const char *[]){ |
| 1573 | "gcc_vsensor_clk_src", |
| 1574 | }, |
| 1575 | .num_parents = 1, |
| 1576 | .flags = CLK_SET_RATE_PARENT, |
| 1577 | .ops = &clk_branch2_ops, |
| 1578 | }, |
| 1579 | }, |
| 1580 | }; |
| 1581 | |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 1582 | static struct clk_branch gcc_boot_rom_ahb_clk = { |
| 1583 | .halt_reg = 0x38004, |
| 1584 | .halt_check = BRANCH_HALT_VOTED, |
Deepak Katragadda | b1886f4 | 2017-06-19 11:52:32 -0700 | [diff] [blame] | 1585 | .hwcg_reg = 0x38004, |
| 1586 | .hwcg_bit = 1, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 1587 | .clkr = { |
| 1588 | .enable_reg = 0x52004, |
| 1589 | .enable_mask = BIT(10), |
| 1590 | .hw.init = &(struct clk_init_data){ |
| 1591 | .name = "gcc_boot_rom_ahb_clk", |
| 1592 | .ops = &clk_branch2_ops, |
| 1593 | }, |
| 1594 | }, |
| 1595 | }; |
| 1596 | |
| 1597 | static struct clk_branch gcc_camera_ahb_clk = { |
| 1598 | .halt_reg = 0xb008, |
| 1599 | .halt_check = BRANCH_HALT, |
Deepak Katragadda | b1886f4 | 2017-06-19 11:52:32 -0700 | [diff] [blame] | 1600 | .hwcg_reg = 0xb008, |
| 1601 | .hwcg_bit = 1, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 1602 | .clkr = { |
| 1603 | .enable_reg = 0xb008, |
| 1604 | .enable_mask = BIT(0), |
| 1605 | .hw.init = &(struct clk_init_data){ |
| 1606 | .name = "gcc_camera_ahb_clk", |
Deepak Katragadda | d8a8279 | 2017-07-26 13:26:26 -0700 | [diff] [blame] | 1607 | .flags = CLK_IS_CRITICAL, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 1608 | .ops = &clk_branch2_ops, |
| 1609 | }, |
| 1610 | }, |
| 1611 | }; |
| 1612 | |
| 1613 | static struct clk_branch gcc_camera_axi_clk = { |
| 1614 | .halt_reg = 0xb020, |
| 1615 | .halt_check = BRANCH_VOTED, |
| 1616 | .clkr = { |
| 1617 | .enable_reg = 0xb020, |
| 1618 | .enable_mask = BIT(0), |
| 1619 | .hw.init = &(struct clk_init_data){ |
| 1620 | .name = "gcc_camera_axi_clk", |
| 1621 | .ops = &clk_branch2_ops, |
| 1622 | }, |
| 1623 | }, |
| 1624 | }; |
| 1625 | |
| 1626 | static struct clk_branch gcc_camera_xo_clk = { |
| 1627 | .halt_reg = 0xb02c, |
| 1628 | .halt_check = BRANCH_HALT, |
| 1629 | .clkr = { |
| 1630 | .enable_reg = 0xb02c, |
| 1631 | .enable_mask = BIT(0), |
| 1632 | .hw.init = &(struct clk_init_data){ |
| 1633 | .name = "gcc_camera_xo_clk", |
Deepak Katragadda | d8a8279 | 2017-07-26 13:26:26 -0700 | [diff] [blame] | 1634 | .flags = CLK_IS_CRITICAL, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 1635 | .ops = &clk_branch2_ops, |
| 1636 | }, |
| 1637 | }, |
| 1638 | }; |
| 1639 | |
| 1640 | static struct clk_branch gcc_ce1_ahb_clk = { |
| 1641 | .halt_reg = 0x4100c, |
| 1642 | .halt_check = BRANCH_HALT_VOTED, |
Deepak Katragadda | b1886f4 | 2017-06-19 11:52:32 -0700 | [diff] [blame] | 1643 | .hwcg_reg = 0x4100c, |
| 1644 | .hwcg_bit = 1, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 1645 | .clkr = { |
| 1646 | .enable_reg = 0x52004, |
| 1647 | .enable_mask = BIT(3), |
| 1648 | .hw.init = &(struct clk_init_data){ |
| 1649 | .name = "gcc_ce1_ahb_clk", |
| 1650 | .ops = &clk_branch2_ops, |
| 1651 | }, |
| 1652 | }, |
| 1653 | }; |
| 1654 | |
| 1655 | static struct clk_branch gcc_ce1_axi_clk = { |
| 1656 | .halt_reg = 0x41008, |
| 1657 | .halt_check = BRANCH_HALT_VOTED, |
| 1658 | .clkr = { |
| 1659 | .enable_reg = 0x52004, |
| 1660 | .enable_mask = BIT(4), |
| 1661 | .hw.init = &(struct clk_init_data){ |
| 1662 | .name = "gcc_ce1_axi_clk", |
| 1663 | .ops = &clk_branch2_ops, |
| 1664 | }, |
| 1665 | }, |
| 1666 | }; |
| 1667 | |
| 1668 | static struct clk_branch gcc_ce1_clk = { |
| 1669 | .halt_reg = 0x41004, |
| 1670 | .halt_check = BRANCH_HALT_VOTED, |
| 1671 | .clkr = { |
| 1672 | .enable_reg = 0x52004, |
| 1673 | .enable_mask = BIT(5), |
| 1674 | .hw.init = &(struct clk_init_data){ |
| 1675 | .name = "gcc_ce1_clk", |
| 1676 | .ops = &clk_branch2_ops, |
| 1677 | }, |
| 1678 | }, |
| 1679 | }; |
| 1680 | |
| 1681 | static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = { |
| 1682 | .halt_reg = 0x502c, |
| 1683 | .halt_check = BRANCH_HALT, |
| 1684 | .clkr = { |
| 1685 | .enable_reg = 0x502c, |
| 1686 | .enable_mask = BIT(0), |
| 1687 | .hw.init = &(struct clk_init_data){ |
| 1688 | .name = "gcc_cfg_noc_usb3_prim_axi_clk", |
| 1689 | .parent_names = (const char *[]){ |
| 1690 | "gcc_usb30_prim_master_clk_src", |
| 1691 | }, |
| 1692 | .num_parents = 1, |
| 1693 | .flags = CLK_SET_RATE_PARENT, |
| 1694 | .ops = &clk_branch2_ops, |
| 1695 | }, |
| 1696 | }, |
| 1697 | }; |
| 1698 | |
| 1699 | static struct clk_branch gcc_cfg_noc_usb3_sec_axi_clk = { |
| 1700 | .halt_reg = 0x5030, |
| 1701 | .halt_check = BRANCH_HALT, |
| 1702 | .clkr = { |
| 1703 | .enable_reg = 0x5030, |
| 1704 | .enable_mask = BIT(0), |
| 1705 | .hw.init = &(struct clk_init_data){ |
| 1706 | .name = "gcc_cfg_noc_usb3_sec_axi_clk", |
| 1707 | .parent_names = (const char *[]){ |
| 1708 | "gcc_usb30_sec_master_clk_src", |
| 1709 | }, |
| 1710 | .num_parents = 1, |
| 1711 | .flags = CLK_SET_RATE_PARENT, |
| 1712 | .ops = &clk_branch2_ops, |
| 1713 | }, |
| 1714 | }, |
| 1715 | }; |
| 1716 | |
| 1717 | static struct clk_branch gcc_cpuss_ahb_clk = { |
| 1718 | .halt_reg = 0x48000, |
| 1719 | .halt_check = BRANCH_HALT_VOTED, |
| 1720 | .clkr = { |
| 1721 | .enable_reg = 0x52004, |
| 1722 | .enable_mask = BIT(21), |
| 1723 | .hw.init = &(struct clk_init_data){ |
| 1724 | .name = "gcc_cpuss_ahb_clk", |
| 1725 | .parent_names = (const char *[]){ |
| 1726 | "gcc_cpuss_ahb_clk_src", |
| 1727 | }, |
| 1728 | .num_parents = 1, |
Deepak Katragadda | d8a8279 | 2017-07-26 13:26:26 -0700 | [diff] [blame] | 1729 | .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 1730 | .ops = &clk_branch2_ops, |
| 1731 | }, |
| 1732 | }, |
| 1733 | }; |
| 1734 | |
| 1735 | static struct clk_branch gcc_cpuss_dvm_bus_clk = { |
| 1736 | .halt_reg = 0x48190, |
| 1737 | .halt_check = BRANCH_HALT, |
| 1738 | .clkr = { |
| 1739 | .enable_reg = 0x48190, |
| 1740 | .enable_mask = BIT(0), |
| 1741 | .hw.init = &(struct clk_init_data){ |
| 1742 | .name = "gcc_cpuss_dvm_bus_clk", |
Deepak Katragadda | d8a8279 | 2017-07-26 13:26:26 -0700 | [diff] [blame] | 1743 | .flags = CLK_IS_CRITICAL, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 1744 | .ops = &clk_branch2_ops, |
| 1745 | }, |
| 1746 | }, |
| 1747 | }; |
| 1748 | |
| 1749 | static struct clk_branch gcc_cpuss_gnoc_clk = { |
| 1750 | .halt_reg = 0x48004, |
| 1751 | .halt_check = BRANCH_HALT_VOTED, |
Deepak Katragadda | b1886f4 | 2017-06-19 11:52:32 -0700 | [diff] [blame] | 1752 | .hwcg_reg = 0x48004, |
| 1753 | .hwcg_bit = 1, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 1754 | .clkr = { |
| 1755 | .enable_reg = 0x52004, |
| 1756 | .enable_mask = BIT(22), |
| 1757 | .hw.init = &(struct clk_init_data){ |
| 1758 | .name = "gcc_cpuss_gnoc_clk", |
Deepak Katragadda | d8a8279 | 2017-07-26 13:26:26 -0700 | [diff] [blame] | 1759 | .flags = CLK_IS_CRITICAL, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 1760 | .ops = &clk_branch2_ops, |
| 1761 | }, |
| 1762 | }, |
| 1763 | }; |
| 1764 | |
| 1765 | static struct clk_branch gcc_cpuss_rbcpr_clk = { |
| 1766 | .halt_reg = 0x48008, |
| 1767 | .halt_check = BRANCH_HALT, |
| 1768 | .clkr = { |
| 1769 | .enable_reg = 0x48008, |
| 1770 | .enable_mask = BIT(0), |
| 1771 | .hw.init = &(struct clk_init_data){ |
| 1772 | .name = "gcc_cpuss_rbcpr_clk", |
| 1773 | .parent_names = (const char *[]){ |
| 1774 | "gcc_cpuss_rbcpr_clk_src", |
| 1775 | }, |
| 1776 | .num_parents = 1, |
| 1777 | .flags = CLK_SET_RATE_PARENT, |
| 1778 | .ops = &clk_branch2_ops, |
| 1779 | }, |
| 1780 | }, |
| 1781 | }; |
| 1782 | |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 1783 | static struct clk_branch gcc_ddrss_gpu_axi_clk = { |
| 1784 | .halt_reg = 0x44038, |
Deepak Katragadda | d4ec4b7 | 2017-04-18 15:02:12 -0700 | [diff] [blame] | 1785 | .halt_check = BRANCH_VOTED, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 1786 | .clkr = { |
| 1787 | .enable_reg = 0x44038, |
| 1788 | .enable_mask = BIT(0), |
| 1789 | .hw.init = &(struct clk_init_data){ |
| 1790 | .name = "gcc_ddrss_gpu_axi_clk", |
| 1791 | .ops = &clk_branch2_ops, |
| 1792 | }, |
| 1793 | }, |
| 1794 | }; |
| 1795 | |
| 1796 | static struct clk_branch gcc_disp_ahb_clk = { |
| 1797 | .halt_reg = 0xb00c, |
| 1798 | .halt_check = BRANCH_HALT, |
Deepak Katragadda | b1886f4 | 2017-06-19 11:52:32 -0700 | [diff] [blame] | 1799 | .hwcg_reg = 0xb00c, |
| 1800 | .hwcg_bit = 1, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 1801 | .clkr = { |
| 1802 | .enable_reg = 0xb00c, |
| 1803 | .enable_mask = BIT(0), |
| 1804 | .hw.init = &(struct clk_init_data){ |
| 1805 | .name = "gcc_disp_ahb_clk", |
Deepak Katragadda | d8a8279 | 2017-07-26 13:26:26 -0700 | [diff] [blame] | 1806 | .flags = CLK_IS_CRITICAL, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 1807 | .ops = &clk_branch2_ops, |
| 1808 | }, |
| 1809 | }, |
| 1810 | }; |
| 1811 | |
| 1812 | static struct clk_branch gcc_disp_axi_clk = { |
| 1813 | .halt_reg = 0xb024, |
| 1814 | .halt_check = BRANCH_VOTED, |
| 1815 | .clkr = { |
| 1816 | .enable_reg = 0xb024, |
| 1817 | .enable_mask = BIT(0), |
| 1818 | .hw.init = &(struct clk_init_data){ |
| 1819 | .name = "gcc_disp_axi_clk", |
| 1820 | .ops = &clk_branch2_ops, |
| 1821 | }, |
| 1822 | }, |
| 1823 | }; |
| 1824 | |
| 1825 | static struct clk_gate2 gcc_disp_gpll0_clk_src = { |
| 1826 | .udelay = 500, |
| 1827 | .clkr = { |
| 1828 | .enable_reg = 0x52004, |
| 1829 | .enable_mask = BIT(18), |
| 1830 | .hw.init = &(struct clk_init_data){ |
| 1831 | .name = "gcc_disp_gpll0_clk_src", |
| 1832 | .parent_names = (const char *[]){ |
| 1833 | "gpll0", |
| 1834 | }, |
| 1835 | .num_parents = 1, |
| 1836 | .flags = CLK_SET_RATE_PARENT, |
| 1837 | .ops = &clk_gate2_ops, |
| 1838 | }, |
| 1839 | }, |
| 1840 | }; |
| 1841 | |
| 1842 | static struct clk_gate2 gcc_disp_gpll0_div_clk_src = { |
| 1843 | .udelay = 500, |
| 1844 | .clkr = { |
| 1845 | .enable_reg = 0x52004, |
| 1846 | .enable_mask = BIT(19), |
| 1847 | .hw.init = &(struct clk_init_data){ |
| 1848 | .name = "gcc_disp_gpll0_div_clk_src", |
| 1849 | .parent_names = (const char *[]){ |
| 1850 | "gpll0_out_even", |
| 1851 | }, |
| 1852 | .num_parents = 1, |
| 1853 | .flags = CLK_SET_RATE_PARENT, |
| 1854 | .ops = &clk_gate2_ops, |
| 1855 | }, |
| 1856 | }, |
| 1857 | }; |
| 1858 | |
| 1859 | static struct clk_branch gcc_disp_xo_clk = { |
| 1860 | .halt_reg = 0xb030, |
| 1861 | .halt_check = BRANCH_HALT, |
| 1862 | .clkr = { |
| 1863 | .enable_reg = 0xb030, |
| 1864 | .enable_mask = BIT(0), |
| 1865 | .hw.init = &(struct clk_init_data){ |
| 1866 | .name = "gcc_disp_xo_clk", |
Deepak Katragadda | d8a8279 | 2017-07-26 13:26:26 -0700 | [diff] [blame] | 1867 | .flags = CLK_IS_CRITICAL, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 1868 | .ops = &clk_branch2_ops, |
| 1869 | }, |
| 1870 | }, |
| 1871 | }; |
| 1872 | |
| 1873 | static struct clk_branch gcc_gp1_clk = { |
| 1874 | .halt_reg = 0x64000, |
| 1875 | .halt_check = BRANCH_HALT, |
| 1876 | .clkr = { |
| 1877 | .enable_reg = 0x64000, |
| 1878 | .enable_mask = BIT(0), |
| 1879 | .hw.init = &(struct clk_init_data){ |
| 1880 | .name = "gcc_gp1_clk", |
| 1881 | .parent_names = (const char *[]){ |
| 1882 | "gcc_gp1_clk_src", |
| 1883 | }, |
| 1884 | .num_parents = 1, |
| 1885 | .flags = CLK_SET_RATE_PARENT, |
| 1886 | .ops = &clk_branch2_ops, |
| 1887 | }, |
| 1888 | }, |
| 1889 | }; |
| 1890 | |
| 1891 | static struct clk_branch gcc_gp2_clk = { |
| 1892 | .halt_reg = 0x65000, |
| 1893 | .halt_check = BRANCH_HALT, |
| 1894 | .clkr = { |
| 1895 | .enable_reg = 0x65000, |
| 1896 | .enable_mask = BIT(0), |
| 1897 | .hw.init = &(struct clk_init_data){ |
| 1898 | .name = "gcc_gp2_clk", |
| 1899 | .parent_names = (const char *[]){ |
| 1900 | "gcc_gp2_clk_src", |
| 1901 | }, |
| 1902 | .num_parents = 1, |
| 1903 | .flags = CLK_SET_RATE_PARENT, |
| 1904 | .ops = &clk_branch2_ops, |
| 1905 | }, |
| 1906 | }, |
| 1907 | }; |
| 1908 | |
| 1909 | static struct clk_branch gcc_gp3_clk = { |
| 1910 | .halt_reg = 0x66000, |
| 1911 | .halt_check = BRANCH_HALT, |
| 1912 | .clkr = { |
| 1913 | .enable_reg = 0x66000, |
| 1914 | .enable_mask = BIT(0), |
| 1915 | .hw.init = &(struct clk_init_data){ |
| 1916 | .name = "gcc_gp3_clk", |
| 1917 | .parent_names = (const char *[]){ |
| 1918 | "gcc_gp3_clk_src", |
| 1919 | }, |
| 1920 | .num_parents = 1, |
| 1921 | .flags = CLK_SET_RATE_PARENT, |
| 1922 | .ops = &clk_branch2_ops, |
| 1923 | }, |
| 1924 | }, |
| 1925 | }; |
| 1926 | |
| 1927 | static struct clk_branch gcc_gpu_cfg_ahb_clk = { |
| 1928 | .halt_reg = 0x71004, |
| 1929 | .halt_check = BRANCH_HALT, |
Deepak Katragadda | b1886f4 | 2017-06-19 11:52:32 -0700 | [diff] [blame] | 1930 | .hwcg_reg = 0x71004, |
| 1931 | .hwcg_bit = 1, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 1932 | .clkr = { |
| 1933 | .enable_reg = 0x71004, |
| 1934 | .enable_mask = BIT(0), |
| 1935 | .hw.init = &(struct clk_init_data){ |
| 1936 | .name = "gcc_gpu_cfg_ahb_clk", |
Deepak Katragadda | d8a8279 | 2017-07-26 13:26:26 -0700 | [diff] [blame] | 1937 | .flags = CLK_IS_CRITICAL, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 1938 | .ops = &clk_branch2_ops, |
| 1939 | }, |
| 1940 | }, |
| 1941 | }; |
| 1942 | |
| 1943 | static struct clk_gate2 gcc_gpu_gpll0_clk_src = { |
| 1944 | .udelay = 500, |
| 1945 | .clkr = { |
| 1946 | .enable_reg = 0x52004, |
| 1947 | .enable_mask = BIT(15), |
| 1948 | .hw.init = &(struct clk_init_data){ |
| 1949 | .name = "gcc_gpu_gpll0_clk_src", |
| 1950 | .parent_names = (const char *[]){ |
| 1951 | "gpll0", |
| 1952 | }, |
| 1953 | .num_parents = 1, |
| 1954 | .flags = CLK_SET_RATE_PARENT, |
| 1955 | .ops = &clk_gate2_ops, |
| 1956 | }, |
| 1957 | }, |
| 1958 | }; |
| 1959 | |
| 1960 | static struct clk_gate2 gcc_gpu_gpll0_div_clk_src = { |
| 1961 | .udelay = 500, |
| 1962 | .clkr = { |
| 1963 | .enable_reg = 0x52004, |
| 1964 | .enable_mask = BIT(16), |
| 1965 | .hw.init = &(struct clk_init_data){ |
| 1966 | .name = "gcc_gpu_gpll0_div_clk_src", |
| 1967 | .parent_names = (const char *[]){ |
| 1968 | "gpll0_out_even", |
| 1969 | }, |
| 1970 | .num_parents = 1, |
| 1971 | .flags = CLK_SET_RATE_PARENT, |
| 1972 | .ops = &clk_gate2_ops, |
| 1973 | }, |
| 1974 | }, |
| 1975 | }; |
| 1976 | |
Deepak Katragadda | 69ba1ca | 2017-05-12 13:37:52 -0700 | [diff] [blame] | 1977 | static struct clk_branch gcc_gpu_iref_clk = { |
| 1978 | .halt_reg = 0x8c010, |
| 1979 | .halt_check = BRANCH_HALT, |
| 1980 | .clkr = { |
| 1981 | .enable_reg = 0x8c010, |
| 1982 | .enable_mask = BIT(0), |
| 1983 | .hw.init = &(struct clk_init_data){ |
| 1984 | .name = "gcc_gpu_iref_clk", |
| 1985 | .ops = &clk_branch2_ops, |
| 1986 | }, |
| 1987 | }, |
| 1988 | }; |
| 1989 | |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 1990 | static struct clk_branch gcc_gpu_memnoc_gfx_clk = { |
| 1991 | .halt_reg = 0x7100c, |
Deepak Katragadda | d4ec4b7 | 2017-04-18 15:02:12 -0700 | [diff] [blame] | 1992 | .halt_check = BRANCH_VOTED, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 1993 | .clkr = { |
| 1994 | .enable_reg = 0x7100c, |
| 1995 | .enable_mask = BIT(0), |
| 1996 | .hw.init = &(struct clk_init_data){ |
| 1997 | .name = "gcc_gpu_memnoc_gfx_clk", |
| 1998 | .ops = &clk_branch2_ops, |
| 1999 | }, |
| 2000 | }, |
| 2001 | }; |
| 2002 | |
| 2003 | static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = { |
| 2004 | .halt_reg = 0x71018, |
| 2005 | .halt_check = BRANCH_HALT, |
| 2006 | .clkr = { |
| 2007 | .enable_reg = 0x71018, |
| 2008 | .enable_mask = BIT(0), |
| 2009 | .hw.init = &(struct clk_init_data){ |
| 2010 | .name = "gcc_gpu_snoc_dvm_gfx_clk", |
| 2011 | .ops = &clk_branch2_ops, |
| 2012 | }, |
| 2013 | }, |
| 2014 | }; |
| 2015 | |
Deepak Katragadda | 87732a1 | 2017-07-18 12:07:17 -0700 | [diff] [blame] | 2016 | static struct clk_branch gcc_gpu_vs_clk = { |
| 2017 | .halt_reg = 0x7a04c, |
| 2018 | .halt_check = BRANCH_HALT, |
| 2019 | .clkr = { |
| 2020 | .enable_reg = 0x7a04c, |
| 2021 | .enable_mask = BIT(0), |
| 2022 | .hw.init = &(struct clk_init_data){ |
| 2023 | .name = "gcc_gpu_vs_clk", |
| 2024 | .parent_names = (const char *[]){ |
| 2025 | "gcc_vsensor_clk_src", |
| 2026 | }, |
| 2027 | .num_parents = 1, |
| 2028 | .flags = CLK_SET_RATE_PARENT, |
| 2029 | .ops = &clk_branch2_ops, |
| 2030 | }, |
| 2031 | }, |
| 2032 | }; |
| 2033 | |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 2034 | static struct clk_branch gcc_mss_axis2_clk = { |
| 2035 | .halt_reg = 0x8a008, |
| 2036 | .halt_check = BRANCH_HALT, |
| 2037 | .clkr = { |
| 2038 | .enable_reg = 0x8a008, |
| 2039 | .enable_mask = BIT(0), |
| 2040 | .hw.init = &(struct clk_init_data){ |
| 2041 | .name = "gcc_mss_axis2_clk", |
| 2042 | .ops = &clk_branch2_ops, |
| 2043 | }, |
| 2044 | }, |
| 2045 | }; |
| 2046 | |
| 2047 | static struct clk_branch gcc_mss_cfg_ahb_clk = { |
| 2048 | .halt_reg = 0x8a000, |
| 2049 | .halt_check = BRANCH_HALT, |
Deepak Katragadda | b1886f4 | 2017-06-19 11:52:32 -0700 | [diff] [blame] | 2050 | .hwcg_reg = 0x8a000, |
| 2051 | .hwcg_bit = 1, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 2052 | .clkr = { |
| 2053 | .enable_reg = 0x8a000, |
| 2054 | .enable_mask = BIT(0), |
| 2055 | .hw.init = &(struct clk_init_data){ |
| 2056 | .name = "gcc_mss_cfg_ahb_clk", |
| 2057 | .ops = &clk_branch2_ops, |
| 2058 | }, |
| 2059 | }, |
| 2060 | }; |
| 2061 | |
| 2062 | static struct clk_gate2 gcc_mss_gpll0_div_clk_src = { |
| 2063 | .udelay = 500, |
| 2064 | .clkr = { |
| 2065 | .enable_reg = 0x52004, |
| 2066 | .enable_mask = BIT(17), |
| 2067 | .hw.init = &(struct clk_init_data){ |
| 2068 | .name = "gcc_mss_gpll0_div_clk_src", |
| 2069 | .ops = &clk_gate2_ops, |
| 2070 | }, |
| 2071 | }, |
| 2072 | }; |
| 2073 | |
| 2074 | static struct clk_branch gcc_mss_mfab_axis_clk = { |
| 2075 | .halt_reg = 0x8a004, |
| 2076 | .halt_check = BRANCH_VOTED, |
Deepak Katragadda | b1886f4 | 2017-06-19 11:52:32 -0700 | [diff] [blame] | 2077 | .hwcg_reg = 0x8a004, |
| 2078 | .hwcg_bit = 1, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 2079 | .clkr = { |
| 2080 | .enable_reg = 0x8a004, |
| 2081 | .enable_mask = BIT(0), |
| 2082 | .hw.init = &(struct clk_init_data){ |
| 2083 | .name = "gcc_mss_mfab_axis_clk", |
| 2084 | .ops = &clk_branch2_ops, |
| 2085 | }, |
| 2086 | }, |
| 2087 | }; |
| 2088 | |
| 2089 | static struct clk_branch gcc_mss_q6_memnoc_axi_clk = { |
| 2090 | .halt_reg = 0x8a154, |
| 2091 | .halt_check = BRANCH_VOTED, |
| 2092 | .clkr = { |
| 2093 | .enable_reg = 0x8a154, |
| 2094 | .enable_mask = BIT(0), |
| 2095 | .hw.init = &(struct clk_init_data){ |
| 2096 | .name = "gcc_mss_q6_memnoc_axi_clk", |
| 2097 | .ops = &clk_branch2_ops, |
| 2098 | }, |
| 2099 | }, |
| 2100 | }; |
| 2101 | |
| 2102 | static struct clk_branch gcc_mss_snoc_axi_clk = { |
| 2103 | .halt_reg = 0x8a150, |
| 2104 | .halt_check = BRANCH_HALT, |
| 2105 | .clkr = { |
| 2106 | .enable_reg = 0x8a150, |
| 2107 | .enable_mask = BIT(0), |
| 2108 | .hw.init = &(struct clk_init_data){ |
| 2109 | .name = "gcc_mss_snoc_axi_clk", |
| 2110 | .ops = &clk_branch2_ops, |
| 2111 | }, |
| 2112 | }, |
| 2113 | }; |
| 2114 | |
Deepak Katragadda | 87732a1 | 2017-07-18 12:07:17 -0700 | [diff] [blame] | 2115 | static struct clk_branch gcc_mss_vs_clk = { |
| 2116 | .halt_reg = 0x7a048, |
| 2117 | .halt_check = BRANCH_HALT, |
| 2118 | .clkr = { |
| 2119 | .enable_reg = 0x7a048, |
| 2120 | .enable_mask = BIT(0), |
| 2121 | .hw.init = &(struct clk_init_data){ |
| 2122 | .name = "gcc_mss_vs_clk", |
| 2123 | .parent_names = (const char *[]){ |
| 2124 | "gcc_vsensor_clk_src", |
| 2125 | }, |
| 2126 | .num_parents = 1, |
| 2127 | .flags = CLK_SET_RATE_PARENT, |
| 2128 | .ops = &clk_branch2_ops, |
| 2129 | }, |
| 2130 | }, |
| 2131 | }; |
| 2132 | |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 2133 | static struct clk_branch gcc_pcie_0_aux_clk = { |
| 2134 | .halt_reg = 0x6b01c, |
| 2135 | .halt_check = BRANCH_HALT_VOTED, |
| 2136 | .clkr = { |
| 2137 | .enable_reg = 0x5200c, |
| 2138 | .enable_mask = BIT(3), |
| 2139 | .hw.init = &(struct clk_init_data){ |
| 2140 | .name = "gcc_pcie_0_aux_clk", |
| 2141 | .parent_names = (const char *[]){ |
| 2142 | "gcc_pcie_0_aux_clk_src", |
| 2143 | }, |
| 2144 | .num_parents = 1, |
| 2145 | .flags = CLK_SET_RATE_PARENT, |
| 2146 | .ops = &clk_branch2_ops, |
| 2147 | }, |
| 2148 | }, |
| 2149 | }; |
| 2150 | |
| 2151 | static struct clk_branch gcc_pcie_0_cfg_ahb_clk = { |
| 2152 | .halt_reg = 0x6b018, |
| 2153 | .halt_check = BRANCH_HALT_VOTED, |
Deepak Katragadda | b1886f4 | 2017-06-19 11:52:32 -0700 | [diff] [blame] | 2154 | .hwcg_reg = 0x6b018, |
| 2155 | .hwcg_bit = 1, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 2156 | .clkr = { |
| 2157 | .enable_reg = 0x5200c, |
| 2158 | .enable_mask = BIT(2), |
| 2159 | .hw.init = &(struct clk_init_data){ |
| 2160 | .name = "gcc_pcie_0_cfg_ahb_clk", |
| 2161 | .ops = &clk_branch2_ops, |
| 2162 | }, |
| 2163 | }, |
| 2164 | }; |
| 2165 | |
| 2166 | static struct clk_branch gcc_pcie_0_clkref_clk = { |
| 2167 | .halt_reg = 0x8c00c, |
| 2168 | .halt_check = BRANCH_HALT, |
| 2169 | .clkr = { |
| 2170 | .enable_reg = 0x8c00c, |
| 2171 | .enable_mask = BIT(0), |
| 2172 | .hw.init = &(struct clk_init_data){ |
| 2173 | .name = "gcc_pcie_0_clkref_clk", |
| 2174 | .ops = &clk_branch2_ops, |
| 2175 | }, |
| 2176 | }, |
| 2177 | }; |
| 2178 | |
| 2179 | static struct clk_branch gcc_pcie_0_mstr_axi_clk = { |
| 2180 | .halt_reg = 0x6b014, |
| 2181 | .halt_check = BRANCH_HALT_VOTED, |
| 2182 | .clkr = { |
| 2183 | .enable_reg = 0x5200c, |
| 2184 | .enable_mask = BIT(1), |
| 2185 | .hw.init = &(struct clk_init_data){ |
| 2186 | .name = "gcc_pcie_0_mstr_axi_clk", |
| 2187 | .ops = &clk_branch2_ops, |
| 2188 | }, |
| 2189 | }, |
| 2190 | }; |
| 2191 | |
Deepak Katragadda | 4f92344 | 2017-05-03 11:35:43 -0700 | [diff] [blame] | 2192 | static struct clk_branch gcc_pcie_0_pipe_clk = { |
| 2193 | .halt_reg = 0x6b020, |
| 2194 | .halt_check = BRANCH_VOTED, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 2195 | .clkr = { |
| 2196 | .enable_reg = 0x5200c, |
| 2197 | .enable_mask = BIT(4), |
| 2198 | .hw.init = &(struct clk_init_data){ |
| 2199 | .name = "gcc_pcie_0_pipe_clk", |
Deepak Katragadda | 4f92344 | 2017-05-03 11:35:43 -0700 | [diff] [blame] | 2200 | .ops = &clk_branch2_ops, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 2201 | }, |
| 2202 | }, |
| 2203 | }; |
| 2204 | |
| 2205 | static struct clk_branch gcc_pcie_0_slv_axi_clk = { |
| 2206 | .halt_reg = 0x6b010, |
| 2207 | .halt_check = BRANCH_HALT_VOTED, |
Deepak Katragadda | b1886f4 | 2017-06-19 11:52:32 -0700 | [diff] [blame] | 2208 | .hwcg_reg = 0x6b010, |
| 2209 | .hwcg_bit = 1, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 2210 | .clkr = { |
| 2211 | .enable_reg = 0x5200c, |
| 2212 | .enable_mask = BIT(0), |
| 2213 | .hw.init = &(struct clk_init_data){ |
| 2214 | .name = "gcc_pcie_0_slv_axi_clk", |
| 2215 | .ops = &clk_branch2_ops, |
| 2216 | }, |
| 2217 | }, |
| 2218 | }; |
| 2219 | |
| 2220 | static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = { |
| 2221 | .halt_reg = 0x6b00c, |
| 2222 | .halt_check = BRANCH_HALT_VOTED, |
| 2223 | .clkr = { |
| 2224 | .enable_reg = 0x5200c, |
| 2225 | .enable_mask = BIT(5), |
| 2226 | .hw.init = &(struct clk_init_data){ |
| 2227 | .name = "gcc_pcie_0_slv_q2a_axi_clk", |
| 2228 | .ops = &clk_branch2_ops, |
| 2229 | }, |
| 2230 | }, |
| 2231 | }; |
| 2232 | |
| 2233 | static struct clk_branch gcc_pcie_1_aux_clk = { |
| 2234 | .halt_reg = 0x8d01c, |
| 2235 | .halt_check = BRANCH_HALT_VOTED, |
| 2236 | .clkr = { |
| 2237 | .enable_reg = 0x52004, |
| 2238 | .enable_mask = BIT(29), |
| 2239 | .hw.init = &(struct clk_init_data){ |
| 2240 | .name = "gcc_pcie_1_aux_clk", |
| 2241 | .parent_names = (const char *[]){ |
| 2242 | "gcc_pcie_1_aux_clk_src", |
| 2243 | }, |
| 2244 | .num_parents = 1, |
| 2245 | .flags = CLK_SET_RATE_PARENT, |
| 2246 | .ops = &clk_branch2_ops, |
| 2247 | }, |
| 2248 | }, |
| 2249 | }; |
| 2250 | |
| 2251 | static struct clk_branch gcc_pcie_1_cfg_ahb_clk = { |
| 2252 | .halt_reg = 0x8d018, |
| 2253 | .halt_check = BRANCH_HALT_VOTED, |
Deepak Katragadda | b1886f4 | 2017-06-19 11:52:32 -0700 | [diff] [blame] | 2254 | .hwcg_reg = 0x8d018, |
| 2255 | .hwcg_bit = 1, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 2256 | .clkr = { |
| 2257 | .enable_reg = 0x52004, |
| 2258 | .enable_mask = BIT(28), |
| 2259 | .hw.init = &(struct clk_init_data){ |
| 2260 | .name = "gcc_pcie_1_cfg_ahb_clk", |
| 2261 | .ops = &clk_branch2_ops, |
| 2262 | }, |
| 2263 | }, |
| 2264 | }; |
| 2265 | |
| 2266 | static struct clk_branch gcc_pcie_1_clkref_clk = { |
| 2267 | .halt_reg = 0x8c02c, |
| 2268 | .halt_check = BRANCH_HALT, |
| 2269 | .clkr = { |
| 2270 | .enable_reg = 0x8c02c, |
| 2271 | .enable_mask = BIT(0), |
| 2272 | .hw.init = &(struct clk_init_data){ |
| 2273 | .name = "gcc_pcie_1_clkref_clk", |
| 2274 | .ops = &clk_branch2_ops, |
| 2275 | }, |
| 2276 | }, |
| 2277 | }; |
| 2278 | |
| 2279 | static struct clk_branch gcc_pcie_1_mstr_axi_clk = { |
| 2280 | .halt_reg = 0x8d014, |
| 2281 | .halt_check = BRANCH_HALT_VOTED, |
| 2282 | .clkr = { |
| 2283 | .enable_reg = 0x52004, |
| 2284 | .enable_mask = BIT(27), |
| 2285 | .hw.init = &(struct clk_init_data){ |
| 2286 | .name = "gcc_pcie_1_mstr_axi_clk", |
| 2287 | .ops = &clk_branch2_ops, |
| 2288 | }, |
| 2289 | }, |
| 2290 | }; |
| 2291 | |
Deepak Katragadda | 4f92344 | 2017-05-03 11:35:43 -0700 | [diff] [blame] | 2292 | static struct clk_branch gcc_pcie_1_pipe_clk = { |
| 2293 | .halt_reg = 0x8d020, |
| 2294 | .halt_check = BRANCH_VOTED, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 2295 | .clkr = { |
| 2296 | .enable_reg = 0x52004, |
| 2297 | .enable_mask = BIT(30), |
| 2298 | .hw.init = &(struct clk_init_data){ |
| 2299 | .name = "gcc_pcie_1_pipe_clk", |
Deepak Katragadda | 4f92344 | 2017-05-03 11:35:43 -0700 | [diff] [blame] | 2300 | .ops = &clk_branch2_ops, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 2301 | }, |
| 2302 | }, |
| 2303 | }; |
| 2304 | |
| 2305 | static struct clk_branch gcc_pcie_1_slv_axi_clk = { |
| 2306 | .halt_reg = 0x8d010, |
| 2307 | .halt_check = BRANCH_HALT_VOTED, |
Deepak Katragadda | b1886f4 | 2017-06-19 11:52:32 -0700 | [diff] [blame] | 2308 | .hwcg_reg = 0x8d010, |
| 2309 | .hwcg_bit = 1, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 2310 | .clkr = { |
| 2311 | .enable_reg = 0x52004, |
| 2312 | .enable_mask = BIT(26), |
| 2313 | .hw.init = &(struct clk_init_data){ |
| 2314 | .name = "gcc_pcie_1_slv_axi_clk", |
| 2315 | .ops = &clk_branch2_ops, |
| 2316 | }, |
| 2317 | }, |
| 2318 | }; |
| 2319 | |
| 2320 | static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk = { |
| 2321 | .halt_reg = 0x8d00c, |
| 2322 | .halt_check = BRANCH_HALT_VOTED, |
| 2323 | .clkr = { |
| 2324 | .enable_reg = 0x52004, |
| 2325 | .enable_mask = BIT(25), |
| 2326 | .hw.init = &(struct clk_init_data){ |
| 2327 | .name = "gcc_pcie_1_slv_q2a_axi_clk", |
| 2328 | .ops = &clk_branch2_ops, |
| 2329 | }, |
| 2330 | }, |
| 2331 | }; |
| 2332 | |
| 2333 | static struct clk_branch gcc_pcie_phy_aux_clk = { |
| 2334 | .halt_reg = 0x6f004, |
| 2335 | .halt_check = BRANCH_HALT, |
| 2336 | .clkr = { |
| 2337 | .enable_reg = 0x6f004, |
| 2338 | .enable_mask = BIT(0), |
| 2339 | .hw.init = &(struct clk_init_data){ |
| 2340 | .name = "gcc_pcie_phy_aux_clk", |
| 2341 | .parent_names = (const char *[]){ |
| 2342 | "gcc_pcie_0_aux_clk_src", |
| 2343 | }, |
| 2344 | .num_parents = 1, |
| 2345 | .flags = CLK_SET_RATE_PARENT, |
| 2346 | .ops = &clk_branch2_ops, |
| 2347 | }, |
| 2348 | }, |
| 2349 | }; |
| 2350 | |
| 2351 | static struct clk_branch gcc_pcie_phy_refgen_clk = { |
| 2352 | .halt_reg = 0x6f02c, |
| 2353 | .halt_check = BRANCH_HALT, |
| 2354 | .clkr = { |
| 2355 | .enable_reg = 0x6f02c, |
| 2356 | .enable_mask = BIT(0), |
| 2357 | .hw.init = &(struct clk_init_data){ |
| 2358 | .name = "gcc_pcie_phy_refgen_clk", |
| 2359 | .parent_names = (const char *[]){ |
| 2360 | "gcc_pcie_phy_refgen_clk_src", |
| 2361 | }, |
| 2362 | .num_parents = 1, |
| 2363 | .flags = CLK_SET_RATE_PARENT, |
| 2364 | .ops = &clk_branch2_ops, |
| 2365 | }, |
| 2366 | }, |
| 2367 | }; |
| 2368 | |
| 2369 | static struct clk_branch gcc_pdm2_clk = { |
| 2370 | .halt_reg = 0x3300c, |
| 2371 | .halt_check = BRANCH_HALT, |
| 2372 | .clkr = { |
| 2373 | .enable_reg = 0x3300c, |
| 2374 | .enable_mask = BIT(0), |
| 2375 | .hw.init = &(struct clk_init_data){ |
| 2376 | .name = "gcc_pdm2_clk", |
| 2377 | .parent_names = (const char *[]){ |
| 2378 | "gcc_pdm2_clk_src", |
| 2379 | }, |
| 2380 | .num_parents = 1, |
| 2381 | .flags = CLK_SET_RATE_PARENT, |
| 2382 | .ops = &clk_branch2_ops, |
| 2383 | }, |
| 2384 | }, |
| 2385 | }; |
| 2386 | |
| 2387 | static struct clk_branch gcc_pdm_ahb_clk = { |
| 2388 | .halt_reg = 0x33004, |
| 2389 | .halt_check = BRANCH_HALT, |
Deepak Katragadda | b1886f4 | 2017-06-19 11:52:32 -0700 | [diff] [blame] | 2390 | .hwcg_reg = 0x33004, |
| 2391 | .hwcg_bit = 1, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 2392 | .clkr = { |
| 2393 | .enable_reg = 0x33004, |
| 2394 | .enable_mask = BIT(0), |
| 2395 | .hw.init = &(struct clk_init_data){ |
| 2396 | .name = "gcc_pdm_ahb_clk", |
| 2397 | .ops = &clk_branch2_ops, |
| 2398 | }, |
| 2399 | }, |
| 2400 | }; |
| 2401 | |
| 2402 | static struct clk_branch gcc_pdm_xo4_clk = { |
| 2403 | .halt_reg = 0x33008, |
| 2404 | .halt_check = BRANCH_HALT, |
| 2405 | .clkr = { |
| 2406 | .enable_reg = 0x33008, |
| 2407 | .enable_mask = BIT(0), |
| 2408 | .hw.init = &(struct clk_init_data){ |
| 2409 | .name = "gcc_pdm_xo4_clk", |
| 2410 | .ops = &clk_branch2_ops, |
| 2411 | }, |
| 2412 | }, |
| 2413 | }; |
| 2414 | |
| 2415 | static struct clk_branch gcc_prng_ahb_clk = { |
| 2416 | .halt_reg = 0x34004, |
| 2417 | .halt_check = BRANCH_HALT_VOTED, |
Deepak Katragadda | b1886f4 | 2017-06-19 11:52:32 -0700 | [diff] [blame] | 2418 | .hwcg_reg = 0x34004, |
| 2419 | .hwcg_bit = 1, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 2420 | .clkr = { |
| 2421 | .enable_reg = 0x52004, |
| 2422 | .enable_mask = BIT(13), |
| 2423 | .hw.init = &(struct clk_init_data){ |
| 2424 | .name = "gcc_prng_ahb_clk", |
| 2425 | .ops = &clk_branch2_ops, |
| 2426 | }, |
| 2427 | }, |
| 2428 | }; |
| 2429 | |
| 2430 | static struct clk_branch gcc_qmip_camera_ahb_clk = { |
| 2431 | .halt_reg = 0xb014, |
| 2432 | .halt_check = BRANCH_HALT, |
Deepak Katragadda | b1886f4 | 2017-06-19 11:52:32 -0700 | [diff] [blame] | 2433 | .hwcg_reg = 0xb014, |
| 2434 | .hwcg_bit = 1, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 2435 | .clkr = { |
| 2436 | .enable_reg = 0xb014, |
| 2437 | .enable_mask = BIT(0), |
| 2438 | .hw.init = &(struct clk_init_data){ |
| 2439 | .name = "gcc_qmip_camera_ahb_clk", |
| 2440 | .ops = &clk_branch2_ops, |
| 2441 | }, |
| 2442 | }, |
| 2443 | }; |
| 2444 | |
| 2445 | static struct clk_branch gcc_qmip_disp_ahb_clk = { |
| 2446 | .halt_reg = 0xb018, |
| 2447 | .halt_check = BRANCH_HALT, |
Deepak Katragadda | b1886f4 | 2017-06-19 11:52:32 -0700 | [diff] [blame] | 2448 | .hwcg_reg = 0xb018, |
| 2449 | .hwcg_bit = 1, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 2450 | .clkr = { |
| 2451 | .enable_reg = 0xb018, |
| 2452 | .enable_mask = BIT(0), |
| 2453 | .hw.init = &(struct clk_init_data){ |
| 2454 | .name = "gcc_qmip_disp_ahb_clk", |
| 2455 | .ops = &clk_branch2_ops, |
| 2456 | }, |
| 2457 | }, |
| 2458 | }; |
| 2459 | |
| 2460 | static struct clk_branch gcc_qmip_video_ahb_clk = { |
| 2461 | .halt_reg = 0xb010, |
| 2462 | .halt_check = BRANCH_HALT, |
Deepak Katragadda | b1886f4 | 2017-06-19 11:52:32 -0700 | [diff] [blame] | 2463 | .hwcg_reg = 0xb010, |
| 2464 | .hwcg_bit = 1, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 2465 | .clkr = { |
| 2466 | .enable_reg = 0xb010, |
| 2467 | .enable_mask = BIT(0), |
| 2468 | .hw.init = &(struct clk_init_data){ |
| 2469 | .name = "gcc_qmip_video_ahb_clk", |
| 2470 | .ops = &clk_branch2_ops, |
| 2471 | }, |
| 2472 | }, |
| 2473 | }; |
| 2474 | |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 2475 | static struct clk_branch gcc_qupv3_wrap0_s0_clk = { |
| 2476 | .halt_reg = 0x17030, |
| 2477 | .halt_check = BRANCH_HALT_VOTED, |
| 2478 | .clkr = { |
| 2479 | .enable_reg = 0x5200c, |
| 2480 | .enable_mask = BIT(10), |
| 2481 | .hw.init = &(struct clk_init_data){ |
| 2482 | .name = "gcc_qupv3_wrap0_s0_clk", |
| 2483 | .parent_names = (const char *[]){ |
| 2484 | "gcc_qupv3_wrap0_s0_clk_src", |
| 2485 | }, |
| 2486 | .num_parents = 1, |
| 2487 | .flags = CLK_SET_RATE_PARENT, |
| 2488 | .ops = &clk_branch2_ops, |
| 2489 | }, |
| 2490 | }, |
| 2491 | }; |
| 2492 | |
| 2493 | static struct clk_branch gcc_qupv3_wrap0_s1_clk = { |
| 2494 | .halt_reg = 0x17160, |
| 2495 | .halt_check = BRANCH_HALT_VOTED, |
| 2496 | .clkr = { |
| 2497 | .enable_reg = 0x5200c, |
| 2498 | .enable_mask = BIT(11), |
| 2499 | .hw.init = &(struct clk_init_data){ |
| 2500 | .name = "gcc_qupv3_wrap0_s1_clk", |
| 2501 | .parent_names = (const char *[]){ |
| 2502 | "gcc_qupv3_wrap0_s1_clk_src", |
| 2503 | }, |
| 2504 | .num_parents = 1, |
| 2505 | .flags = CLK_SET_RATE_PARENT, |
| 2506 | .ops = &clk_branch2_ops, |
| 2507 | }, |
| 2508 | }, |
| 2509 | }; |
| 2510 | |
| 2511 | static struct clk_branch gcc_qupv3_wrap0_s2_clk = { |
| 2512 | .halt_reg = 0x17290, |
| 2513 | .halt_check = BRANCH_HALT_VOTED, |
| 2514 | .clkr = { |
| 2515 | .enable_reg = 0x5200c, |
| 2516 | .enable_mask = BIT(12), |
| 2517 | .hw.init = &(struct clk_init_data){ |
| 2518 | .name = "gcc_qupv3_wrap0_s2_clk", |
| 2519 | .parent_names = (const char *[]){ |
| 2520 | "gcc_qupv3_wrap0_s2_clk_src", |
| 2521 | }, |
| 2522 | .num_parents = 1, |
| 2523 | .flags = CLK_SET_RATE_PARENT, |
| 2524 | .ops = &clk_branch2_ops, |
| 2525 | }, |
| 2526 | }, |
| 2527 | }; |
| 2528 | |
| 2529 | static struct clk_branch gcc_qupv3_wrap0_s3_clk = { |
| 2530 | .halt_reg = 0x173c0, |
| 2531 | .halt_check = BRANCH_HALT_VOTED, |
| 2532 | .clkr = { |
| 2533 | .enable_reg = 0x5200c, |
| 2534 | .enable_mask = BIT(13), |
| 2535 | .hw.init = &(struct clk_init_data){ |
| 2536 | .name = "gcc_qupv3_wrap0_s3_clk", |
| 2537 | .parent_names = (const char *[]){ |
| 2538 | "gcc_qupv3_wrap0_s3_clk_src", |
| 2539 | }, |
| 2540 | .num_parents = 1, |
| 2541 | .flags = CLK_SET_RATE_PARENT, |
| 2542 | .ops = &clk_branch2_ops, |
| 2543 | }, |
| 2544 | }, |
| 2545 | }; |
| 2546 | |
| 2547 | static struct clk_branch gcc_qupv3_wrap0_s4_clk = { |
| 2548 | .halt_reg = 0x174f0, |
| 2549 | .halt_check = BRANCH_HALT_VOTED, |
| 2550 | .clkr = { |
| 2551 | .enable_reg = 0x5200c, |
| 2552 | .enable_mask = BIT(14), |
| 2553 | .hw.init = &(struct clk_init_data){ |
| 2554 | .name = "gcc_qupv3_wrap0_s4_clk", |
| 2555 | .parent_names = (const char *[]){ |
| 2556 | "gcc_qupv3_wrap0_s4_clk_src", |
| 2557 | }, |
| 2558 | .num_parents = 1, |
| 2559 | .flags = CLK_SET_RATE_PARENT, |
| 2560 | .ops = &clk_branch2_ops, |
| 2561 | }, |
| 2562 | }, |
| 2563 | }; |
| 2564 | |
| 2565 | static struct clk_branch gcc_qupv3_wrap0_s5_clk = { |
| 2566 | .halt_reg = 0x17620, |
| 2567 | .halt_check = BRANCH_HALT_VOTED, |
| 2568 | .clkr = { |
| 2569 | .enable_reg = 0x5200c, |
| 2570 | .enable_mask = BIT(15), |
| 2571 | .hw.init = &(struct clk_init_data){ |
| 2572 | .name = "gcc_qupv3_wrap0_s5_clk", |
| 2573 | .parent_names = (const char *[]){ |
| 2574 | "gcc_qupv3_wrap0_s5_clk_src", |
| 2575 | }, |
| 2576 | .num_parents = 1, |
| 2577 | .flags = CLK_SET_RATE_PARENT, |
| 2578 | .ops = &clk_branch2_ops, |
| 2579 | }, |
| 2580 | }, |
| 2581 | }; |
| 2582 | |
| 2583 | static struct clk_branch gcc_qupv3_wrap0_s6_clk = { |
| 2584 | .halt_reg = 0x17750, |
| 2585 | .halt_check = BRANCH_HALT_VOTED, |
| 2586 | .clkr = { |
| 2587 | .enable_reg = 0x5200c, |
| 2588 | .enable_mask = BIT(16), |
| 2589 | .hw.init = &(struct clk_init_data){ |
| 2590 | .name = "gcc_qupv3_wrap0_s6_clk", |
| 2591 | .parent_names = (const char *[]){ |
| 2592 | "gcc_qupv3_wrap0_s6_clk_src", |
| 2593 | }, |
| 2594 | .num_parents = 1, |
| 2595 | .flags = CLK_SET_RATE_PARENT, |
| 2596 | .ops = &clk_branch2_ops, |
| 2597 | }, |
| 2598 | }, |
| 2599 | }; |
| 2600 | |
| 2601 | static struct clk_branch gcc_qupv3_wrap0_s7_clk = { |
| 2602 | .halt_reg = 0x17880, |
| 2603 | .halt_check = BRANCH_HALT_VOTED, |
| 2604 | .clkr = { |
| 2605 | .enable_reg = 0x5200c, |
| 2606 | .enable_mask = BIT(17), |
| 2607 | .hw.init = &(struct clk_init_data){ |
| 2608 | .name = "gcc_qupv3_wrap0_s7_clk", |
| 2609 | .parent_names = (const char *[]){ |
| 2610 | "gcc_qupv3_wrap0_s7_clk_src", |
| 2611 | }, |
| 2612 | .num_parents = 1, |
| 2613 | .flags = CLK_SET_RATE_PARENT, |
| 2614 | .ops = &clk_branch2_ops, |
| 2615 | }, |
| 2616 | }, |
| 2617 | }; |
| 2618 | |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 2619 | static struct clk_branch gcc_qupv3_wrap1_s0_clk = { |
| 2620 | .halt_reg = 0x18014, |
| 2621 | .halt_check = BRANCH_HALT_VOTED, |
| 2622 | .clkr = { |
| 2623 | .enable_reg = 0x5200c, |
| 2624 | .enable_mask = BIT(22), |
| 2625 | .hw.init = &(struct clk_init_data){ |
| 2626 | .name = "gcc_qupv3_wrap1_s0_clk", |
| 2627 | .parent_names = (const char *[]){ |
| 2628 | "gcc_qupv3_wrap1_s0_clk_src", |
| 2629 | }, |
| 2630 | .num_parents = 1, |
| 2631 | .flags = CLK_SET_RATE_PARENT, |
| 2632 | .ops = &clk_branch2_ops, |
| 2633 | }, |
| 2634 | }, |
| 2635 | }; |
| 2636 | |
| 2637 | static struct clk_branch gcc_qupv3_wrap1_s1_clk = { |
| 2638 | .halt_reg = 0x18144, |
| 2639 | .halt_check = BRANCH_HALT_VOTED, |
| 2640 | .clkr = { |
| 2641 | .enable_reg = 0x5200c, |
| 2642 | .enable_mask = BIT(23), |
| 2643 | .hw.init = &(struct clk_init_data){ |
| 2644 | .name = "gcc_qupv3_wrap1_s1_clk", |
| 2645 | .parent_names = (const char *[]){ |
| 2646 | "gcc_qupv3_wrap1_s1_clk_src", |
| 2647 | }, |
| 2648 | .num_parents = 1, |
| 2649 | .flags = CLK_SET_RATE_PARENT, |
| 2650 | .ops = &clk_branch2_ops, |
| 2651 | }, |
| 2652 | }, |
| 2653 | }; |
| 2654 | |
| 2655 | static struct clk_branch gcc_qupv3_wrap1_s2_clk = { |
| 2656 | .halt_reg = 0x18274, |
| 2657 | .halt_check = BRANCH_HALT_VOTED, |
| 2658 | .clkr = { |
| 2659 | .enable_reg = 0x5200c, |
| 2660 | .enable_mask = BIT(24), |
| 2661 | .hw.init = &(struct clk_init_data){ |
| 2662 | .name = "gcc_qupv3_wrap1_s2_clk", |
| 2663 | .parent_names = (const char *[]){ |
| 2664 | "gcc_qupv3_wrap1_s2_clk_src", |
| 2665 | }, |
| 2666 | .num_parents = 1, |
| 2667 | .flags = CLK_SET_RATE_PARENT, |
| 2668 | .ops = &clk_branch2_ops, |
| 2669 | }, |
| 2670 | }, |
| 2671 | }; |
| 2672 | |
| 2673 | static struct clk_branch gcc_qupv3_wrap1_s3_clk = { |
| 2674 | .halt_reg = 0x183a4, |
| 2675 | .halt_check = BRANCH_HALT_VOTED, |
| 2676 | .clkr = { |
| 2677 | .enable_reg = 0x5200c, |
| 2678 | .enable_mask = BIT(25), |
| 2679 | .hw.init = &(struct clk_init_data){ |
| 2680 | .name = "gcc_qupv3_wrap1_s3_clk", |
| 2681 | .parent_names = (const char *[]){ |
| 2682 | "gcc_qupv3_wrap1_s3_clk_src", |
| 2683 | }, |
| 2684 | .num_parents = 1, |
| 2685 | .flags = CLK_SET_RATE_PARENT, |
| 2686 | .ops = &clk_branch2_ops, |
| 2687 | }, |
| 2688 | }, |
| 2689 | }; |
| 2690 | |
| 2691 | static struct clk_branch gcc_qupv3_wrap1_s4_clk = { |
| 2692 | .halt_reg = 0x184d4, |
| 2693 | .halt_check = BRANCH_HALT_VOTED, |
| 2694 | .clkr = { |
| 2695 | .enable_reg = 0x5200c, |
| 2696 | .enable_mask = BIT(26), |
| 2697 | .hw.init = &(struct clk_init_data){ |
| 2698 | .name = "gcc_qupv3_wrap1_s4_clk", |
| 2699 | .parent_names = (const char *[]){ |
| 2700 | "gcc_qupv3_wrap1_s4_clk_src", |
| 2701 | }, |
| 2702 | .num_parents = 1, |
| 2703 | .flags = CLK_SET_RATE_PARENT, |
| 2704 | .ops = &clk_branch2_ops, |
| 2705 | }, |
| 2706 | }, |
| 2707 | }; |
| 2708 | |
| 2709 | static struct clk_branch gcc_qupv3_wrap1_s5_clk = { |
| 2710 | .halt_reg = 0x18604, |
| 2711 | .halt_check = BRANCH_HALT_VOTED, |
| 2712 | .clkr = { |
| 2713 | .enable_reg = 0x5200c, |
| 2714 | .enable_mask = BIT(27), |
| 2715 | .hw.init = &(struct clk_init_data){ |
| 2716 | .name = "gcc_qupv3_wrap1_s5_clk", |
| 2717 | .parent_names = (const char *[]){ |
| 2718 | "gcc_qupv3_wrap1_s5_clk_src", |
| 2719 | }, |
| 2720 | .num_parents = 1, |
| 2721 | .flags = CLK_SET_RATE_PARENT, |
| 2722 | .ops = &clk_branch2_ops, |
| 2723 | }, |
| 2724 | }, |
| 2725 | }; |
| 2726 | |
| 2727 | static struct clk_branch gcc_qupv3_wrap1_s6_clk = { |
| 2728 | .halt_reg = 0x18734, |
| 2729 | .halt_check = BRANCH_HALT_VOTED, |
| 2730 | .clkr = { |
| 2731 | .enable_reg = 0x5200c, |
| 2732 | .enable_mask = BIT(28), |
| 2733 | .hw.init = &(struct clk_init_data){ |
| 2734 | .name = "gcc_qupv3_wrap1_s6_clk", |
| 2735 | .parent_names = (const char *[]){ |
| 2736 | "gcc_qupv3_wrap1_s6_clk_src", |
| 2737 | }, |
| 2738 | .num_parents = 1, |
| 2739 | .flags = CLK_SET_RATE_PARENT, |
| 2740 | .ops = &clk_branch2_ops, |
| 2741 | }, |
| 2742 | }, |
| 2743 | }; |
| 2744 | |
| 2745 | static struct clk_branch gcc_qupv3_wrap1_s7_clk = { |
| 2746 | .halt_reg = 0x18864, |
| 2747 | .halt_check = BRANCH_HALT_VOTED, |
| 2748 | .clkr = { |
| 2749 | .enable_reg = 0x5200c, |
| 2750 | .enable_mask = BIT(29), |
| 2751 | .hw.init = &(struct clk_init_data){ |
| 2752 | .name = "gcc_qupv3_wrap1_s7_clk", |
| 2753 | .parent_names = (const char *[]){ |
| 2754 | "gcc_qupv3_wrap1_s7_clk_src", |
| 2755 | }, |
| 2756 | .num_parents = 1, |
| 2757 | .flags = CLK_SET_RATE_PARENT, |
| 2758 | .ops = &clk_branch2_ops, |
| 2759 | }, |
| 2760 | }, |
| 2761 | }; |
| 2762 | |
| 2763 | static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = { |
| 2764 | .halt_reg = 0x17004, |
| 2765 | .halt_check = BRANCH_HALT_VOTED, |
| 2766 | .clkr = { |
| 2767 | .enable_reg = 0x5200c, |
| 2768 | .enable_mask = BIT(6), |
| 2769 | .hw.init = &(struct clk_init_data){ |
| 2770 | .name = "gcc_qupv3_wrap_0_m_ahb_clk", |
| 2771 | .ops = &clk_branch2_ops, |
| 2772 | }, |
| 2773 | }, |
| 2774 | }; |
| 2775 | |
| 2776 | static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = { |
| 2777 | .halt_reg = 0x17008, |
| 2778 | .halt_check = BRANCH_HALT_VOTED, |
Deepak Katragadda | b1886f4 | 2017-06-19 11:52:32 -0700 | [diff] [blame] | 2779 | .hwcg_reg = 0x17008, |
| 2780 | .hwcg_bit = 1, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 2781 | .clkr = { |
| 2782 | .enable_reg = 0x5200c, |
| 2783 | .enable_mask = BIT(7), |
| 2784 | .hw.init = &(struct clk_init_data){ |
| 2785 | .name = "gcc_qupv3_wrap_0_s_ahb_clk", |
| 2786 | .ops = &clk_branch2_ops, |
| 2787 | }, |
| 2788 | }, |
| 2789 | }; |
| 2790 | |
| 2791 | static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = { |
| 2792 | .halt_reg = 0x1800c, |
| 2793 | .halt_check = BRANCH_HALT_VOTED, |
| 2794 | .clkr = { |
| 2795 | .enable_reg = 0x5200c, |
| 2796 | .enable_mask = BIT(20), |
| 2797 | .hw.init = &(struct clk_init_data){ |
| 2798 | .name = "gcc_qupv3_wrap_1_m_ahb_clk", |
| 2799 | .ops = &clk_branch2_ops, |
| 2800 | }, |
| 2801 | }, |
| 2802 | }; |
| 2803 | |
| 2804 | static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = { |
| 2805 | .halt_reg = 0x18010, |
| 2806 | .halt_check = BRANCH_HALT_VOTED, |
Deepak Katragadda | b1886f4 | 2017-06-19 11:52:32 -0700 | [diff] [blame] | 2807 | .hwcg_reg = 0x18010, |
| 2808 | .hwcg_bit = 1, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 2809 | .clkr = { |
| 2810 | .enable_reg = 0x5200c, |
| 2811 | .enable_mask = BIT(21), |
| 2812 | .hw.init = &(struct clk_init_data){ |
| 2813 | .name = "gcc_qupv3_wrap_1_s_ahb_clk", |
| 2814 | .ops = &clk_branch2_ops, |
| 2815 | }, |
| 2816 | }, |
| 2817 | }; |
| 2818 | |
Deepak Katragadda | 443bd8d | 2017-08-28 22:30:19 +0530 | [diff] [blame] | 2819 | static struct clk_branch gcc_sdcc1_ice_core_clk = { |
| 2820 | .halt_reg = 0x2600c, |
| 2821 | .halt_check = BRANCH_HALT, |
| 2822 | .clkr = { |
| 2823 | .enable_reg = 0x2600c, |
| 2824 | .enable_mask = BIT(0), |
| 2825 | .hw.init = &(struct clk_init_data){ |
| 2826 | .name = "gcc_sdcc1_ice_core_clk", |
| 2827 | .parent_names = (const char *[]){ |
| 2828 | "gcc_sdcc1_ice_core_clk_src", |
| 2829 | }, |
| 2830 | .num_parents = 1, |
| 2831 | .flags = CLK_SET_RATE_PARENT, |
| 2832 | .ops = &clk_branch2_ops, |
| 2833 | }, |
| 2834 | }, |
| 2835 | }; |
| 2836 | |
| 2837 | static struct clk_branch gcc_sdcc1_ahb_clk = { |
| 2838 | .halt_reg = 0x26008, |
| 2839 | .halt_check = BRANCH_HALT, |
| 2840 | .clkr = { |
| 2841 | .enable_reg = 0x26008, |
| 2842 | .enable_mask = BIT(0), |
| 2843 | .hw.init = &(struct clk_init_data){ |
| 2844 | .name = "gcc_sdcc1_ahb_clk", |
| 2845 | .ops = &clk_branch2_ops, |
| 2846 | }, |
| 2847 | }, |
| 2848 | }; |
| 2849 | |
| 2850 | static struct clk_branch gcc_sdcc1_apps_clk = { |
| 2851 | .halt_reg = 0x26004, |
| 2852 | .halt_check = BRANCH_HALT, |
| 2853 | .clkr = { |
| 2854 | .enable_reg = 0x26004, |
| 2855 | .enable_mask = BIT(0), |
| 2856 | .hw.init = &(struct clk_init_data){ |
| 2857 | .name = "gcc_sdcc1_apps_clk", |
| 2858 | .parent_names = (const char *[]){ |
| 2859 | "gcc_sdcc1_apps_clk_src", |
| 2860 | }, |
| 2861 | .num_parents = 1, |
| 2862 | .flags = CLK_SET_RATE_PARENT, |
| 2863 | .ops = &clk_branch2_ops, |
| 2864 | }, |
| 2865 | }, |
| 2866 | }; |
| 2867 | |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 2868 | static struct clk_branch gcc_sdcc2_ahb_clk = { |
| 2869 | .halt_reg = 0x14008, |
| 2870 | .halt_check = BRANCH_HALT, |
| 2871 | .clkr = { |
| 2872 | .enable_reg = 0x14008, |
| 2873 | .enable_mask = BIT(0), |
| 2874 | .hw.init = &(struct clk_init_data){ |
| 2875 | .name = "gcc_sdcc2_ahb_clk", |
| 2876 | .ops = &clk_branch2_ops, |
| 2877 | }, |
| 2878 | }, |
| 2879 | }; |
| 2880 | |
| 2881 | static struct clk_branch gcc_sdcc2_apps_clk = { |
| 2882 | .halt_reg = 0x14004, |
| 2883 | .halt_check = BRANCH_HALT, |
| 2884 | .clkr = { |
| 2885 | .enable_reg = 0x14004, |
| 2886 | .enable_mask = BIT(0), |
| 2887 | .hw.init = &(struct clk_init_data){ |
| 2888 | .name = "gcc_sdcc2_apps_clk", |
| 2889 | .parent_names = (const char *[]){ |
| 2890 | "gcc_sdcc2_apps_clk_src", |
| 2891 | }, |
| 2892 | .num_parents = 1, |
| 2893 | .flags = CLK_SET_RATE_PARENT, |
| 2894 | .ops = &clk_branch2_ops, |
| 2895 | }, |
| 2896 | }, |
| 2897 | }; |
| 2898 | |
| 2899 | static struct clk_branch gcc_sdcc4_ahb_clk = { |
| 2900 | .halt_reg = 0x16008, |
| 2901 | .halt_check = BRANCH_HALT, |
| 2902 | .clkr = { |
| 2903 | .enable_reg = 0x16008, |
| 2904 | .enable_mask = BIT(0), |
| 2905 | .hw.init = &(struct clk_init_data){ |
| 2906 | .name = "gcc_sdcc4_ahb_clk", |
| 2907 | .ops = &clk_branch2_ops, |
| 2908 | }, |
| 2909 | }, |
| 2910 | }; |
| 2911 | |
| 2912 | static struct clk_branch gcc_sdcc4_apps_clk = { |
| 2913 | .halt_reg = 0x16004, |
| 2914 | .halt_check = BRANCH_HALT, |
| 2915 | .clkr = { |
| 2916 | .enable_reg = 0x16004, |
| 2917 | .enable_mask = BIT(0), |
| 2918 | .hw.init = &(struct clk_init_data){ |
| 2919 | .name = "gcc_sdcc4_apps_clk", |
| 2920 | .parent_names = (const char *[]){ |
| 2921 | "gcc_sdcc4_apps_clk_src", |
| 2922 | }, |
| 2923 | .num_parents = 1, |
| 2924 | .flags = CLK_SET_RATE_PARENT, |
| 2925 | .ops = &clk_branch2_ops, |
| 2926 | }, |
| 2927 | }, |
| 2928 | }; |
| 2929 | |
| 2930 | static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = { |
| 2931 | .halt_reg = 0x414c, |
| 2932 | .halt_check = BRANCH_HALT_VOTED, |
| 2933 | .clkr = { |
| 2934 | .enable_reg = 0x52004, |
| 2935 | .enable_mask = BIT(0), |
| 2936 | .hw.init = &(struct clk_init_data){ |
| 2937 | .name = "gcc_sys_noc_cpuss_ahb_clk", |
| 2938 | .parent_names = (const char *[]){ |
| 2939 | "gcc_cpuss_ahb_clk_src", |
| 2940 | }, |
| 2941 | .num_parents = 1, |
Deepak Katragadda | d8a8279 | 2017-07-26 13:26:26 -0700 | [diff] [blame] | 2942 | .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 2943 | .ops = &clk_branch2_ops, |
| 2944 | }, |
| 2945 | }, |
| 2946 | }; |
| 2947 | |
| 2948 | static struct clk_branch gcc_tsif_ahb_clk = { |
| 2949 | .halt_reg = 0x36004, |
| 2950 | .halt_check = BRANCH_HALT, |
| 2951 | .clkr = { |
| 2952 | .enable_reg = 0x36004, |
| 2953 | .enable_mask = BIT(0), |
| 2954 | .hw.init = &(struct clk_init_data){ |
| 2955 | .name = "gcc_tsif_ahb_clk", |
| 2956 | .ops = &clk_branch2_ops, |
| 2957 | }, |
| 2958 | }, |
| 2959 | }; |
| 2960 | |
| 2961 | static struct clk_branch gcc_tsif_inactivity_timers_clk = { |
| 2962 | .halt_reg = 0x3600c, |
| 2963 | .halt_check = BRANCH_HALT, |
| 2964 | .clkr = { |
| 2965 | .enable_reg = 0x3600c, |
| 2966 | .enable_mask = BIT(0), |
| 2967 | .hw.init = &(struct clk_init_data){ |
| 2968 | .name = "gcc_tsif_inactivity_timers_clk", |
| 2969 | .ops = &clk_branch2_ops, |
| 2970 | }, |
| 2971 | }, |
| 2972 | }; |
| 2973 | |
| 2974 | static struct clk_branch gcc_tsif_ref_clk = { |
| 2975 | .halt_reg = 0x36008, |
| 2976 | .halt_check = BRANCH_HALT, |
| 2977 | .clkr = { |
| 2978 | .enable_reg = 0x36008, |
| 2979 | .enable_mask = BIT(0), |
| 2980 | .hw.init = &(struct clk_init_data){ |
| 2981 | .name = "gcc_tsif_ref_clk", |
| 2982 | .parent_names = (const char *[]){ |
| 2983 | "gcc_tsif_ref_clk_src", |
| 2984 | }, |
| 2985 | .num_parents = 1, |
| 2986 | .flags = CLK_SET_RATE_PARENT, |
| 2987 | .ops = &clk_branch2_ops, |
| 2988 | }, |
| 2989 | }, |
| 2990 | }; |
| 2991 | |
| 2992 | static struct clk_branch gcc_ufs_card_ahb_clk = { |
| 2993 | .halt_reg = 0x75010, |
| 2994 | .halt_check = BRANCH_HALT, |
Deepak Katragadda | b1886f4 | 2017-06-19 11:52:32 -0700 | [diff] [blame] | 2995 | .hwcg_reg = 0x75010, |
| 2996 | .hwcg_bit = 1, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 2997 | .clkr = { |
| 2998 | .enable_reg = 0x75010, |
| 2999 | .enable_mask = BIT(0), |
| 3000 | .hw.init = &(struct clk_init_data){ |
| 3001 | .name = "gcc_ufs_card_ahb_clk", |
| 3002 | .ops = &clk_branch2_ops, |
| 3003 | }, |
| 3004 | }, |
| 3005 | }; |
| 3006 | |
| 3007 | static struct clk_branch gcc_ufs_card_axi_clk = { |
| 3008 | .halt_reg = 0x7500c, |
| 3009 | .halt_check = BRANCH_HALT, |
Deepak Katragadda | b1886f4 | 2017-06-19 11:52:32 -0700 | [diff] [blame] | 3010 | .hwcg_reg = 0x7500c, |
| 3011 | .hwcg_bit = 1, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 3012 | .clkr = { |
| 3013 | .enable_reg = 0x7500c, |
| 3014 | .enable_mask = BIT(0), |
| 3015 | .hw.init = &(struct clk_init_data){ |
| 3016 | .name = "gcc_ufs_card_axi_clk", |
| 3017 | .parent_names = (const char *[]){ |
| 3018 | "gcc_ufs_card_axi_clk_src", |
| 3019 | }, |
| 3020 | .num_parents = 1, |
| 3021 | .flags = CLK_SET_RATE_PARENT, |
| 3022 | .ops = &clk_branch2_ops, |
| 3023 | }, |
| 3024 | }, |
| 3025 | }; |
| 3026 | |
Deepak Katragadda | 536caff | 2017-04-04 17:47:56 -0700 | [diff] [blame] | 3027 | static struct clk_branch gcc_ufs_card_axi_hw_ctl_clk = { |
| 3028 | .halt_reg = 0x7500c, |
| 3029 | .clkr = { |
| 3030 | .enable_reg = 0x7500c, |
| 3031 | .enable_mask = BIT(1), |
| 3032 | .hw.init = &(struct clk_init_data){ |
| 3033 | .name = "gcc_ufs_card_axi_hw_ctl_clk", |
| 3034 | .parent_names = (const char *[]){ |
| 3035 | "gcc_ufs_card_axi_clk", |
| 3036 | }, |
| 3037 | .num_parents = 1, |
| 3038 | .flags = CLK_SET_RATE_PARENT, |
| 3039 | .ops = &clk_branch2_hw_ctl_ops, |
| 3040 | }, |
| 3041 | }, |
| 3042 | }; |
| 3043 | |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 3044 | static struct clk_branch gcc_ufs_card_clkref_clk = { |
| 3045 | .halt_reg = 0x8c004, |
| 3046 | .halt_check = BRANCH_HALT, |
| 3047 | .clkr = { |
| 3048 | .enable_reg = 0x8c004, |
| 3049 | .enable_mask = BIT(0), |
| 3050 | .hw.init = &(struct clk_init_data){ |
| 3051 | .name = "gcc_ufs_card_clkref_clk", |
| 3052 | .ops = &clk_branch2_ops, |
| 3053 | }, |
| 3054 | }, |
| 3055 | }; |
| 3056 | |
| 3057 | static struct clk_branch gcc_ufs_card_ice_core_clk = { |
| 3058 | .halt_reg = 0x75058, |
| 3059 | .halt_check = BRANCH_HALT, |
Deepak Katragadda | b1886f4 | 2017-06-19 11:52:32 -0700 | [diff] [blame] | 3060 | .hwcg_reg = 0x75058, |
| 3061 | .hwcg_bit = 1, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 3062 | .clkr = { |
| 3063 | .enable_reg = 0x75058, |
| 3064 | .enable_mask = BIT(0), |
| 3065 | .hw.init = &(struct clk_init_data){ |
| 3066 | .name = "gcc_ufs_card_ice_core_clk", |
| 3067 | .parent_names = (const char *[]){ |
| 3068 | "gcc_ufs_card_ice_core_clk_src", |
| 3069 | }, |
| 3070 | .num_parents = 1, |
| 3071 | .flags = CLK_SET_RATE_PARENT, |
| 3072 | .ops = &clk_branch2_ops, |
| 3073 | }, |
| 3074 | }, |
| 3075 | }; |
| 3076 | |
Deepak Katragadda | 536caff | 2017-04-04 17:47:56 -0700 | [diff] [blame] | 3077 | static struct clk_branch gcc_ufs_card_ice_core_hw_ctl_clk = { |
| 3078 | .halt_reg = 0x75058, |
| 3079 | .clkr = { |
| 3080 | .enable_reg = 0x75058, |
| 3081 | .enable_mask = BIT(1), |
| 3082 | .hw.init = &(struct clk_init_data){ |
| 3083 | .name = "gcc_ufs_card_ice_core_hw_ctl_clk", |
| 3084 | .parent_names = (const char *[]){ |
| 3085 | "gcc_ufs_card_ice_core_clk", |
| 3086 | }, |
| 3087 | .num_parents = 1, |
| 3088 | .flags = CLK_SET_RATE_PARENT, |
| 3089 | .ops = &clk_branch2_hw_ctl_ops, |
| 3090 | }, |
| 3091 | }, |
| 3092 | }; |
| 3093 | |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 3094 | static struct clk_branch gcc_ufs_card_phy_aux_clk = { |
| 3095 | .halt_reg = 0x7508c, |
| 3096 | .halt_check = BRANCH_HALT, |
Deepak Katragadda | b1886f4 | 2017-06-19 11:52:32 -0700 | [diff] [blame] | 3097 | .hwcg_reg = 0x7508c, |
| 3098 | .hwcg_bit = 1, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 3099 | .clkr = { |
| 3100 | .enable_reg = 0x7508c, |
| 3101 | .enable_mask = BIT(0), |
| 3102 | .hw.init = &(struct clk_init_data){ |
| 3103 | .name = "gcc_ufs_card_phy_aux_clk", |
| 3104 | .parent_names = (const char *[]){ |
| 3105 | "gcc_ufs_card_phy_aux_clk_src", |
| 3106 | }, |
| 3107 | .num_parents = 1, |
| 3108 | .flags = CLK_SET_RATE_PARENT, |
| 3109 | .ops = &clk_branch2_ops, |
| 3110 | }, |
| 3111 | }, |
| 3112 | }; |
| 3113 | |
Deepak Katragadda | 536caff | 2017-04-04 17:47:56 -0700 | [diff] [blame] | 3114 | static struct clk_branch gcc_ufs_card_phy_aux_hw_ctl_clk = { |
| 3115 | .halt_reg = 0x7508c, |
| 3116 | .clkr = { |
| 3117 | .enable_reg = 0x7508c, |
| 3118 | .enable_mask = BIT(1), |
| 3119 | .hw.init = &(struct clk_init_data){ |
| 3120 | .name = "gcc_ufs_card_phy_aux_hw_ctl_clk", |
| 3121 | .parent_names = (const char *[]){ |
| 3122 | "gcc_ufs_card_phy_aux_clk", |
| 3123 | }, |
| 3124 | .num_parents = 1, |
| 3125 | .flags = CLK_SET_RATE_PARENT, |
| 3126 | .ops = &clk_branch2_hw_ctl_ops, |
| 3127 | }, |
| 3128 | }, |
| 3129 | }; |
| 3130 | |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 3131 | static struct clk_gate2 gcc_ufs_card_rx_symbol_0_clk = { |
| 3132 | .udelay = 500, |
| 3133 | .clkr = { |
| 3134 | .enable_reg = 0x75018, |
| 3135 | .enable_mask = BIT(0), |
| 3136 | .hw.init = &(struct clk_init_data){ |
| 3137 | .name = "gcc_ufs_card_rx_symbol_0_clk", |
| 3138 | .ops = &clk_gate2_ops, |
| 3139 | }, |
| 3140 | }, |
| 3141 | }; |
| 3142 | |
| 3143 | static struct clk_gate2 gcc_ufs_card_rx_symbol_1_clk = { |
| 3144 | .udelay = 500, |
| 3145 | .clkr = { |
| 3146 | .enable_reg = 0x750a8, |
| 3147 | .enable_mask = BIT(0), |
| 3148 | .hw.init = &(struct clk_init_data){ |
| 3149 | .name = "gcc_ufs_card_rx_symbol_1_clk", |
| 3150 | .ops = &clk_gate2_ops, |
| 3151 | }, |
| 3152 | }, |
| 3153 | }; |
| 3154 | |
| 3155 | static struct clk_gate2 gcc_ufs_card_tx_symbol_0_clk = { |
| 3156 | .udelay = 500, |
| 3157 | .clkr = { |
| 3158 | .enable_reg = 0x75014, |
| 3159 | .enable_mask = BIT(0), |
| 3160 | .hw.init = &(struct clk_init_data){ |
| 3161 | .name = "gcc_ufs_card_tx_symbol_0_clk", |
| 3162 | .ops = &clk_gate2_ops, |
| 3163 | }, |
| 3164 | }, |
| 3165 | }; |
| 3166 | |
| 3167 | static struct clk_branch gcc_ufs_card_unipro_core_clk = { |
| 3168 | .halt_reg = 0x75054, |
| 3169 | .halt_check = BRANCH_HALT, |
Deepak Katragadda | b1886f4 | 2017-06-19 11:52:32 -0700 | [diff] [blame] | 3170 | .hwcg_reg = 0x75054, |
| 3171 | .hwcg_bit = 1, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 3172 | .clkr = { |
| 3173 | .enable_reg = 0x75054, |
| 3174 | .enable_mask = BIT(0), |
| 3175 | .hw.init = &(struct clk_init_data){ |
| 3176 | .name = "gcc_ufs_card_unipro_core_clk", |
| 3177 | .parent_names = (const char *[]){ |
| 3178 | "gcc_ufs_card_unipro_core_clk_src", |
| 3179 | }, |
| 3180 | .num_parents = 1, |
| 3181 | .flags = CLK_SET_RATE_PARENT, |
| 3182 | .ops = &clk_branch2_ops, |
| 3183 | }, |
| 3184 | }, |
| 3185 | }; |
| 3186 | |
Deepak Katragadda | 536caff | 2017-04-04 17:47:56 -0700 | [diff] [blame] | 3187 | static struct clk_branch gcc_ufs_card_unipro_core_hw_ctl_clk = { |
| 3188 | .halt_reg = 0x75054, |
| 3189 | .clkr = { |
| 3190 | .enable_reg = 0x75054, |
| 3191 | .enable_mask = BIT(1), |
| 3192 | .hw.init = &(struct clk_init_data){ |
| 3193 | .name = "gcc_ufs_card_unipro_core_hw_ctl_clk", |
| 3194 | .parent_names = (const char *[]){ |
| 3195 | "gcc_ufs_card_unipro_core_clk", |
| 3196 | }, |
| 3197 | .num_parents = 1, |
| 3198 | .flags = CLK_SET_RATE_PARENT, |
| 3199 | .ops = &clk_branch2_hw_ctl_ops, |
| 3200 | }, |
| 3201 | }, |
| 3202 | }; |
| 3203 | |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 3204 | static struct clk_branch gcc_ufs_mem_clkref_clk = { |
| 3205 | .halt_reg = 0x8c000, |
| 3206 | .halt_check = BRANCH_HALT, |
| 3207 | .clkr = { |
| 3208 | .enable_reg = 0x8c000, |
| 3209 | .enable_mask = BIT(0), |
| 3210 | .hw.init = &(struct clk_init_data){ |
| 3211 | .name = "gcc_ufs_mem_clkref_clk", |
| 3212 | .ops = &clk_branch2_ops, |
| 3213 | }, |
| 3214 | }, |
| 3215 | }; |
| 3216 | |
| 3217 | static struct clk_branch gcc_ufs_phy_ahb_clk = { |
| 3218 | .halt_reg = 0x77010, |
| 3219 | .halt_check = BRANCH_HALT, |
Deepak Katragadda | b1886f4 | 2017-06-19 11:52:32 -0700 | [diff] [blame] | 3220 | .hwcg_reg = 0x77010, |
| 3221 | .hwcg_bit = 1, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 3222 | .clkr = { |
| 3223 | .enable_reg = 0x77010, |
| 3224 | .enable_mask = BIT(0), |
| 3225 | .hw.init = &(struct clk_init_data){ |
| 3226 | .name = "gcc_ufs_phy_ahb_clk", |
| 3227 | .ops = &clk_branch2_ops, |
| 3228 | }, |
| 3229 | }, |
| 3230 | }; |
| 3231 | |
| 3232 | static struct clk_branch gcc_ufs_phy_axi_clk = { |
| 3233 | .halt_reg = 0x7700c, |
| 3234 | .halt_check = BRANCH_HALT, |
Deepak Katragadda | b1886f4 | 2017-06-19 11:52:32 -0700 | [diff] [blame] | 3235 | .hwcg_reg = 0x7700c, |
| 3236 | .hwcg_bit = 1, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 3237 | .clkr = { |
| 3238 | .enable_reg = 0x7700c, |
| 3239 | .enable_mask = BIT(0), |
| 3240 | .hw.init = &(struct clk_init_data){ |
| 3241 | .name = "gcc_ufs_phy_axi_clk", |
| 3242 | .parent_names = (const char *[]){ |
| 3243 | "gcc_ufs_phy_axi_clk_src", |
| 3244 | }, |
| 3245 | .num_parents = 1, |
| 3246 | .flags = CLK_SET_RATE_PARENT, |
| 3247 | .ops = &clk_branch2_ops, |
| 3248 | }, |
| 3249 | }, |
| 3250 | }; |
| 3251 | |
Deepak Katragadda | 536caff | 2017-04-04 17:47:56 -0700 | [diff] [blame] | 3252 | static struct clk_branch gcc_ufs_phy_axi_hw_ctl_clk = { |
| 3253 | .halt_reg = 0x7700c, |
| 3254 | .clkr = { |
| 3255 | .enable_reg = 0x7700c, |
| 3256 | .enable_mask = BIT(1), |
| 3257 | .hw.init = &(struct clk_init_data){ |
| 3258 | .name = "gcc_ufs_phy_axi_hw_ctl_clk", |
| 3259 | .parent_names = (const char *[]){ |
| 3260 | "gcc_ufs_phy_axi_clk", |
| 3261 | }, |
| 3262 | .num_parents = 1, |
| 3263 | .flags = CLK_SET_RATE_PARENT, |
| 3264 | .ops = &clk_branch2_hw_ctl_ops, |
| 3265 | }, |
| 3266 | }, |
| 3267 | }; |
| 3268 | |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 3269 | static struct clk_branch gcc_ufs_phy_ice_core_clk = { |
| 3270 | .halt_reg = 0x77058, |
| 3271 | .halt_check = BRANCH_HALT, |
Deepak Katragadda | b1886f4 | 2017-06-19 11:52:32 -0700 | [diff] [blame] | 3272 | .hwcg_reg = 0x77058, |
| 3273 | .hwcg_bit = 1, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 3274 | .clkr = { |
| 3275 | .enable_reg = 0x77058, |
| 3276 | .enable_mask = BIT(0), |
| 3277 | .hw.init = &(struct clk_init_data){ |
| 3278 | .name = "gcc_ufs_phy_ice_core_clk", |
| 3279 | .parent_names = (const char *[]){ |
| 3280 | "gcc_ufs_phy_ice_core_clk_src", |
| 3281 | }, |
| 3282 | .num_parents = 1, |
| 3283 | .flags = CLK_SET_RATE_PARENT, |
| 3284 | .ops = &clk_branch2_ops, |
| 3285 | }, |
| 3286 | }, |
| 3287 | }; |
| 3288 | |
Deepak Katragadda | 536caff | 2017-04-04 17:47:56 -0700 | [diff] [blame] | 3289 | static struct clk_branch gcc_ufs_phy_ice_core_hw_ctl_clk = { |
| 3290 | .halt_reg = 0x77058, |
| 3291 | .clkr = { |
| 3292 | .enable_reg = 0x77058, |
| 3293 | .enable_mask = BIT(1), |
| 3294 | .hw.init = &(struct clk_init_data){ |
| 3295 | .name = "gcc_ufs_phy_ice_core_hw_ctl_clk", |
| 3296 | .parent_names = (const char *[]){ |
| 3297 | "gcc_ufs_phy_ice_core_clk", |
| 3298 | }, |
| 3299 | .num_parents = 1, |
| 3300 | .flags = CLK_SET_RATE_PARENT, |
| 3301 | .ops = &clk_branch2_hw_ctl_ops, |
| 3302 | }, |
| 3303 | }, |
| 3304 | }; |
| 3305 | |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 3306 | static struct clk_branch gcc_ufs_phy_phy_aux_clk = { |
| 3307 | .halt_reg = 0x7708c, |
| 3308 | .halt_check = BRANCH_HALT, |
Deepak Katragadda | b1886f4 | 2017-06-19 11:52:32 -0700 | [diff] [blame] | 3309 | .hwcg_reg = 0x7708c, |
| 3310 | .hwcg_bit = 1, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 3311 | .clkr = { |
| 3312 | .enable_reg = 0x7708c, |
| 3313 | .enable_mask = BIT(0), |
| 3314 | .hw.init = &(struct clk_init_data){ |
| 3315 | .name = "gcc_ufs_phy_phy_aux_clk", |
| 3316 | .parent_names = (const char *[]){ |
| 3317 | "gcc_ufs_phy_phy_aux_clk_src", |
| 3318 | }, |
| 3319 | .num_parents = 1, |
| 3320 | .flags = CLK_SET_RATE_PARENT, |
| 3321 | .ops = &clk_branch2_ops, |
| 3322 | }, |
| 3323 | }, |
| 3324 | }; |
| 3325 | |
Deepak Katragadda | 536caff | 2017-04-04 17:47:56 -0700 | [diff] [blame] | 3326 | static struct clk_branch gcc_ufs_phy_phy_aux_hw_ctl_clk = { |
| 3327 | .halt_reg = 0x7708c, |
| 3328 | .clkr = { |
| 3329 | .enable_reg = 0x7708c, |
| 3330 | .enable_mask = BIT(1), |
| 3331 | .hw.init = &(struct clk_init_data){ |
| 3332 | .name = "gcc_ufs_phy_phy_aux_hw_ctl_clk", |
| 3333 | .parent_names = (const char *[]){ |
| 3334 | "gcc_ufs_phy_phy_aux_clk", |
| 3335 | }, |
| 3336 | .num_parents = 1, |
| 3337 | .flags = CLK_SET_RATE_PARENT, |
| 3338 | .ops = &clk_branch2_hw_ctl_ops, |
| 3339 | }, |
| 3340 | }, |
| 3341 | }; |
| 3342 | |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 3343 | static struct clk_gate2 gcc_ufs_phy_rx_symbol_0_clk = { |
| 3344 | .udelay = 500, |
| 3345 | .clkr = { |
| 3346 | .enable_reg = 0x77018, |
| 3347 | .enable_mask = BIT(0), |
| 3348 | .hw.init = &(struct clk_init_data){ |
| 3349 | .name = "gcc_ufs_phy_rx_symbol_0_clk", |
| 3350 | .ops = &clk_gate2_ops, |
| 3351 | }, |
| 3352 | }, |
| 3353 | }; |
| 3354 | |
| 3355 | static struct clk_gate2 gcc_ufs_phy_rx_symbol_1_clk = { |
| 3356 | .udelay = 500, |
| 3357 | .clkr = { |
| 3358 | .enable_reg = 0x770a8, |
| 3359 | .enable_mask = BIT(0), |
| 3360 | .hw.init = &(struct clk_init_data){ |
| 3361 | .name = "gcc_ufs_phy_rx_symbol_1_clk", |
| 3362 | .ops = &clk_gate2_ops, |
| 3363 | }, |
| 3364 | }, |
| 3365 | }; |
| 3366 | |
| 3367 | static struct clk_gate2 gcc_ufs_phy_tx_symbol_0_clk = { |
| 3368 | .udelay = 500, |
| 3369 | .clkr = { |
| 3370 | .enable_reg = 0x77014, |
| 3371 | .enable_mask = BIT(0), |
| 3372 | .hw.init = &(struct clk_init_data){ |
| 3373 | .name = "gcc_ufs_phy_tx_symbol_0_clk", |
| 3374 | .ops = &clk_gate2_ops, |
| 3375 | }, |
| 3376 | }, |
| 3377 | }; |
| 3378 | |
| 3379 | static struct clk_branch gcc_ufs_phy_unipro_core_clk = { |
| 3380 | .halt_reg = 0x77054, |
| 3381 | .halt_check = BRANCH_HALT, |
Deepak Katragadda | b1886f4 | 2017-06-19 11:52:32 -0700 | [diff] [blame] | 3382 | .hwcg_reg = 0x77054, |
| 3383 | .hwcg_bit = 1, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 3384 | .clkr = { |
| 3385 | .enable_reg = 0x77054, |
| 3386 | .enable_mask = BIT(0), |
| 3387 | .hw.init = &(struct clk_init_data){ |
| 3388 | .name = "gcc_ufs_phy_unipro_core_clk", |
| 3389 | .parent_names = (const char *[]){ |
| 3390 | "gcc_ufs_phy_unipro_core_clk_src", |
| 3391 | }, |
| 3392 | .num_parents = 1, |
| 3393 | .flags = CLK_SET_RATE_PARENT, |
| 3394 | .ops = &clk_branch2_ops, |
| 3395 | }, |
| 3396 | }, |
| 3397 | }; |
| 3398 | |
Deepak Katragadda | 536caff | 2017-04-04 17:47:56 -0700 | [diff] [blame] | 3399 | static struct clk_branch gcc_ufs_phy_unipro_core_hw_ctl_clk = { |
| 3400 | .halt_reg = 0x77054, |
| 3401 | .clkr = { |
| 3402 | .enable_reg = 0x77054, |
| 3403 | .enable_mask = BIT(1), |
| 3404 | .hw.init = &(struct clk_init_data){ |
| 3405 | .name = "gcc_ufs_phy_unipro_core_hw_ctl_clk", |
| 3406 | .parent_names = (const char *[]){ |
| 3407 | "gcc_ufs_phy_unipro_core_clk", |
| 3408 | }, |
| 3409 | .num_parents = 1, |
| 3410 | .flags = CLK_SET_RATE_PARENT, |
| 3411 | .ops = &clk_branch2_hw_ctl_ops, |
| 3412 | }, |
| 3413 | }, |
| 3414 | }; |
| 3415 | |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 3416 | static struct clk_branch gcc_usb30_prim_master_clk = { |
| 3417 | .halt_reg = 0xf00c, |
| 3418 | .halt_check = BRANCH_HALT, |
| 3419 | .clkr = { |
| 3420 | .enable_reg = 0xf00c, |
| 3421 | .enable_mask = BIT(0), |
| 3422 | .hw.init = &(struct clk_init_data){ |
| 3423 | .name = "gcc_usb30_prim_master_clk", |
| 3424 | .parent_names = (const char *[]){ |
| 3425 | "gcc_usb30_prim_master_clk_src", |
| 3426 | }, |
| 3427 | .num_parents = 1, |
| 3428 | .flags = CLK_SET_RATE_PARENT, |
| 3429 | .ops = &clk_branch2_ops, |
| 3430 | }, |
| 3431 | }, |
| 3432 | }; |
| 3433 | |
| 3434 | static struct clk_branch gcc_usb30_prim_mock_utmi_clk = { |
| 3435 | .halt_reg = 0xf014, |
| 3436 | .halt_check = BRANCH_HALT, |
| 3437 | .clkr = { |
| 3438 | .enable_reg = 0xf014, |
| 3439 | .enable_mask = BIT(0), |
| 3440 | .hw.init = &(struct clk_init_data){ |
| 3441 | .name = "gcc_usb30_prim_mock_utmi_clk", |
| 3442 | .parent_names = (const char *[]){ |
| 3443 | "gcc_usb30_prim_mock_utmi_clk_src", |
| 3444 | }, |
| 3445 | .num_parents = 1, |
| 3446 | .flags = CLK_SET_RATE_PARENT, |
| 3447 | .ops = &clk_branch2_ops, |
| 3448 | }, |
| 3449 | }, |
| 3450 | }; |
| 3451 | |
| 3452 | static struct clk_branch gcc_usb30_prim_sleep_clk = { |
| 3453 | .halt_reg = 0xf010, |
| 3454 | .halt_check = BRANCH_HALT, |
| 3455 | .clkr = { |
| 3456 | .enable_reg = 0xf010, |
| 3457 | .enable_mask = BIT(0), |
| 3458 | .hw.init = &(struct clk_init_data){ |
| 3459 | .name = "gcc_usb30_prim_sleep_clk", |
| 3460 | .ops = &clk_branch2_ops, |
| 3461 | }, |
| 3462 | }, |
| 3463 | }; |
| 3464 | |
| 3465 | static struct clk_branch gcc_usb30_sec_master_clk = { |
| 3466 | .halt_reg = 0x1000c, |
| 3467 | .halt_check = BRANCH_HALT, |
| 3468 | .clkr = { |
| 3469 | .enable_reg = 0x1000c, |
| 3470 | .enable_mask = BIT(0), |
| 3471 | .hw.init = &(struct clk_init_data){ |
| 3472 | .name = "gcc_usb30_sec_master_clk", |
| 3473 | .parent_names = (const char *[]){ |
| 3474 | "gcc_usb30_sec_master_clk_src", |
| 3475 | }, |
| 3476 | .num_parents = 1, |
| 3477 | .flags = CLK_SET_RATE_PARENT, |
| 3478 | .ops = &clk_branch2_ops, |
| 3479 | }, |
| 3480 | }, |
| 3481 | }; |
| 3482 | |
| 3483 | static struct clk_branch gcc_usb30_sec_mock_utmi_clk = { |
| 3484 | .halt_reg = 0x10014, |
| 3485 | .halt_check = BRANCH_HALT, |
| 3486 | .clkr = { |
| 3487 | .enable_reg = 0x10014, |
| 3488 | .enable_mask = BIT(0), |
| 3489 | .hw.init = &(struct clk_init_data){ |
| 3490 | .name = "gcc_usb30_sec_mock_utmi_clk", |
| 3491 | .parent_names = (const char *[]){ |
| 3492 | "gcc_usb30_sec_mock_utmi_clk_src", |
| 3493 | }, |
| 3494 | .num_parents = 1, |
| 3495 | .flags = CLK_SET_RATE_PARENT, |
| 3496 | .ops = &clk_branch2_ops, |
| 3497 | }, |
| 3498 | }, |
| 3499 | }; |
| 3500 | |
| 3501 | static struct clk_branch gcc_usb30_sec_sleep_clk = { |
| 3502 | .halt_reg = 0x10010, |
| 3503 | .halt_check = BRANCH_HALT, |
| 3504 | .clkr = { |
| 3505 | .enable_reg = 0x10010, |
| 3506 | .enable_mask = BIT(0), |
| 3507 | .hw.init = &(struct clk_init_data){ |
| 3508 | .name = "gcc_usb30_sec_sleep_clk", |
| 3509 | .ops = &clk_branch2_ops, |
| 3510 | }, |
| 3511 | }, |
| 3512 | }; |
| 3513 | |
| 3514 | static struct clk_branch gcc_usb3_prim_clkref_clk = { |
| 3515 | .halt_reg = 0x8c008, |
| 3516 | .halt_check = BRANCH_HALT, |
| 3517 | .clkr = { |
| 3518 | .enable_reg = 0x8c008, |
| 3519 | .enable_mask = BIT(0), |
| 3520 | .hw.init = &(struct clk_init_data){ |
| 3521 | .name = "gcc_usb3_prim_clkref_clk", |
| 3522 | .ops = &clk_branch2_ops, |
| 3523 | }, |
| 3524 | }, |
| 3525 | }; |
| 3526 | |
| 3527 | static struct clk_branch gcc_usb3_prim_phy_aux_clk = { |
| 3528 | .halt_reg = 0xf04c, |
| 3529 | .halt_check = BRANCH_HALT, |
| 3530 | .clkr = { |
| 3531 | .enable_reg = 0xf04c, |
| 3532 | .enable_mask = BIT(0), |
| 3533 | .hw.init = &(struct clk_init_data){ |
| 3534 | .name = "gcc_usb3_prim_phy_aux_clk", |
| 3535 | .parent_names = (const char *[]){ |
| 3536 | "gcc_usb3_prim_phy_aux_clk_src", |
| 3537 | }, |
| 3538 | .num_parents = 1, |
| 3539 | .flags = CLK_SET_RATE_PARENT, |
| 3540 | .ops = &clk_branch2_ops, |
| 3541 | }, |
| 3542 | }, |
| 3543 | }; |
| 3544 | |
| 3545 | static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = { |
| 3546 | .halt_reg = 0xf050, |
| 3547 | .halt_check = BRANCH_HALT, |
| 3548 | .clkr = { |
| 3549 | .enable_reg = 0xf050, |
| 3550 | .enable_mask = BIT(0), |
| 3551 | .hw.init = &(struct clk_init_data){ |
| 3552 | .name = "gcc_usb3_prim_phy_com_aux_clk", |
| 3553 | .parent_names = (const char *[]){ |
| 3554 | "gcc_usb3_prim_phy_aux_clk_src", |
| 3555 | }, |
| 3556 | .num_parents = 1, |
| 3557 | .flags = CLK_SET_RATE_PARENT, |
| 3558 | .ops = &clk_branch2_ops, |
| 3559 | }, |
| 3560 | }, |
| 3561 | }; |
| 3562 | |
| 3563 | static struct clk_gate2 gcc_usb3_prim_phy_pipe_clk = { |
| 3564 | .udelay = 500, |
| 3565 | .clkr = { |
| 3566 | .enable_reg = 0xf054, |
| 3567 | .enable_mask = BIT(0), |
| 3568 | .hw.init = &(struct clk_init_data){ |
| 3569 | .name = "gcc_usb3_prim_phy_pipe_clk", |
| 3570 | .ops = &clk_gate2_ops, |
| 3571 | }, |
| 3572 | }, |
| 3573 | }; |
| 3574 | |
| 3575 | static struct clk_branch gcc_usb3_sec_clkref_clk = { |
| 3576 | .halt_reg = 0x8c028, |
| 3577 | .halt_check = BRANCH_HALT, |
| 3578 | .clkr = { |
| 3579 | .enable_reg = 0x8c028, |
| 3580 | .enable_mask = BIT(0), |
| 3581 | .hw.init = &(struct clk_init_data){ |
| 3582 | .name = "gcc_usb3_sec_clkref_clk", |
| 3583 | .ops = &clk_branch2_ops, |
| 3584 | }, |
| 3585 | }, |
| 3586 | }; |
| 3587 | |
| 3588 | static struct clk_branch gcc_usb3_sec_phy_aux_clk = { |
| 3589 | .halt_reg = 0x1004c, |
| 3590 | .halt_check = BRANCH_HALT, |
| 3591 | .clkr = { |
| 3592 | .enable_reg = 0x1004c, |
| 3593 | .enable_mask = BIT(0), |
| 3594 | .hw.init = &(struct clk_init_data){ |
| 3595 | .name = "gcc_usb3_sec_phy_aux_clk", |
| 3596 | .parent_names = (const char *[]){ |
| 3597 | "gcc_usb3_sec_phy_aux_clk_src", |
| 3598 | }, |
| 3599 | .num_parents = 1, |
| 3600 | .flags = CLK_SET_RATE_PARENT, |
| 3601 | .ops = &clk_branch2_ops, |
| 3602 | }, |
| 3603 | }, |
| 3604 | }; |
| 3605 | |
| 3606 | static struct clk_branch gcc_usb3_sec_phy_com_aux_clk = { |
| 3607 | .halt_reg = 0x10050, |
| 3608 | .halt_check = BRANCH_HALT, |
| 3609 | .clkr = { |
| 3610 | .enable_reg = 0x10050, |
| 3611 | .enable_mask = BIT(0), |
| 3612 | .hw.init = &(struct clk_init_data){ |
| 3613 | .name = "gcc_usb3_sec_phy_com_aux_clk", |
| 3614 | .parent_names = (const char *[]){ |
| 3615 | "gcc_usb3_sec_phy_aux_clk_src", |
| 3616 | }, |
| 3617 | .num_parents = 1, |
| 3618 | .flags = CLK_SET_RATE_PARENT, |
| 3619 | .ops = &clk_branch2_ops, |
| 3620 | }, |
| 3621 | }, |
| 3622 | }; |
| 3623 | |
| 3624 | static struct clk_gate2 gcc_usb3_sec_phy_pipe_clk = { |
| 3625 | .udelay = 500, |
| 3626 | .clkr = { |
| 3627 | .enable_reg = 0x10054, |
| 3628 | .enable_mask = BIT(0), |
| 3629 | .hw.init = &(struct clk_init_data){ |
| 3630 | .name = "gcc_usb3_sec_phy_pipe_clk", |
| 3631 | .ops = &clk_gate2_ops, |
| 3632 | }, |
| 3633 | }, |
| 3634 | }; |
| 3635 | |
| 3636 | static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = { |
| 3637 | .halt_reg = 0x6a004, |
| 3638 | .halt_check = BRANCH_HALT, |
Deepak Katragadda | b1886f4 | 2017-06-19 11:52:32 -0700 | [diff] [blame] | 3639 | .hwcg_reg = 0x6a004, |
| 3640 | .hwcg_bit = 1, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 3641 | .clkr = { |
| 3642 | .enable_reg = 0x6a004, |
| 3643 | .enable_mask = BIT(0), |
| 3644 | .hw.init = &(struct clk_init_data){ |
| 3645 | .name = "gcc_usb_phy_cfg_ahb2phy_clk", |
| 3646 | .ops = &clk_branch2_ops, |
| 3647 | }, |
| 3648 | }, |
| 3649 | }; |
| 3650 | |
Deepak Katragadda | 87732a1 | 2017-07-18 12:07:17 -0700 | [diff] [blame] | 3651 | static struct clk_branch gcc_vdda_vs_clk = { |
| 3652 | .halt_reg = 0x7a00c, |
| 3653 | .halt_check = BRANCH_HALT, |
| 3654 | .clkr = { |
| 3655 | .enable_reg = 0x7a00c, |
| 3656 | .enable_mask = BIT(0), |
| 3657 | .hw.init = &(struct clk_init_data){ |
| 3658 | .name = "gcc_vdda_vs_clk", |
| 3659 | .parent_names = (const char *[]){ |
| 3660 | "gcc_vsensor_clk_src", |
| 3661 | }, |
| 3662 | .num_parents = 1, |
| 3663 | .flags = CLK_SET_RATE_PARENT, |
| 3664 | .ops = &clk_branch2_ops, |
| 3665 | }, |
| 3666 | }, |
| 3667 | }; |
| 3668 | |
| 3669 | static struct clk_branch gcc_vddcx_vs_clk = { |
| 3670 | .halt_reg = 0x7a004, |
| 3671 | .halt_check = BRANCH_HALT, |
| 3672 | .clkr = { |
| 3673 | .enable_reg = 0x7a004, |
| 3674 | .enable_mask = BIT(0), |
| 3675 | .hw.init = &(struct clk_init_data){ |
| 3676 | .name = "gcc_vddcx_vs_clk", |
| 3677 | .parent_names = (const char *[]){ |
| 3678 | "gcc_vsensor_clk_src", |
| 3679 | }, |
| 3680 | .num_parents = 1, |
| 3681 | .flags = CLK_SET_RATE_PARENT, |
| 3682 | .ops = &clk_branch2_ops, |
| 3683 | }, |
| 3684 | }, |
| 3685 | }; |
| 3686 | |
| 3687 | static struct clk_branch gcc_vddmx_vs_clk = { |
| 3688 | .halt_reg = 0x7a008, |
| 3689 | .halt_check = BRANCH_HALT, |
| 3690 | .clkr = { |
| 3691 | .enable_reg = 0x7a008, |
| 3692 | .enable_mask = BIT(0), |
| 3693 | .hw.init = &(struct clk_init_data){ |
| 3694 | .name = "gcc_vddmx_vs_clk", |
| 3695 | .parent_names = (const char *[]){ |
| 3696 | "gcc_vsensor_clk_src", |
| 3697 | }, |
| 3698 | .num_parents = 1, |
| 3699 | .flags = CLK_SET_RATE_PARENT, |
| 3700 | .ops = &clk_branch2_ops, |
| 3701 | }, |
| 3702 | }, |
| 3703 | }; |
| 3704 | |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 3705 | static struct clk_branch gcc_video_ahb_clk = { |
| 3706 | .halt_reg = 0xb004, |
| 3707 | .halt_check = BRANCH_HALT, |
Deepak Katragadda | b1886f4 | 2017-06-19 11:52:32 -0700 | [diff] [blame] | 3708 | .hwcg_reg = 0xb004, |
| 3709 | .hwcg_bit = 1, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 3710 | .clkr = { |
| 3711 | .enable_reg = 0xb004, |
| 3712 | .enable_mask = BIT(0), |
| 3713 | .hw.init = &(struct clk_init_data){ |
| 3714 | .name = "gcc_video_ahb_clk", |
Deepak Katragadda | d8a8279 | 2017-07-26 13:26:26 -0700 | [diff] [blame] | 3715 | .flags = CLK_IS_CRITICAL, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 3716 | .ops = &clk_branch2_ops, |
| 3717 | }, |
| 3718 | }, |
| 3719 | }; |
| 3720 | |
| 3721 | static struct clk_branch gcc_video_axi_clk = { |
| 3722 | .halt_reg = 0xb01c, |
| 3723 | .halt_check = BRANCH_VOTED, |
| 3724 | .clkr = { |
| 3725 | .enable_reg = 0xb01c, |
| 3726 | .enable_mask = BIT(0), |
| 3727 | .hw.init = &(struct clk_init_data){ |
| 3728 | .name = "gcc_video_axi_clk", |
| 3729 | .ops = &clk_branch2_ops, |
| 3730 | }, |
| 3731 | }, |
| 3732 | }; |
| 3733 | |
| 3734 | static struct clk_branch gcc_video_xo_clk = { |
| 3735 | .halt_reg = 0xb028, |
| 3736 | .halt_check = BRANCH_HALT, |
| 3737 | .clkr = { |
| 3738 | .enable_reg = 0xb028, |
| 3739 | .enable_mask = BIT(0), |
| 3740 | .hw.init = &(struct clk_init_data){ |
| 3741 | .name = "gcc_video_xo_clk", |
Deepak Katragadda | d8a8279 | 2017-07-26 13:26:26 -0700 | [diff] [blame] | 3742 | .flags = CLK_IS_CRITICAL, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 3743 | .ops = &clk_branch2_ops, |
| 3744 | }, |
| 3745 | }, |
| 3746 | }; |
| 3747 | |
Deepak Katragadda | 87732a1 | 2017-07-18 12:07:17 -0700 | [diff] [blame] | 3748 | static struct clk_branch gcc_vs_ctrl_ahb_clk = { |
| 3749 | .halt_reg = 0x7a014, |
| 3750 | .halt_check = BRANCH_HALT, |
| 3751 | .hwcg_reg = 0x7a014, |
| 3752 | .hwcg_bit = 1, |
| 3753 | .clkr = { |
| 3754 | .enable_reg = 0x7a014, |
| 3755 | .enable_mask = BIT(0), |
| 3756 | .hw.init = &(struct clk_init_data){ |
| 3757 | .name = "gcc_vs_ctrl_ahb_clk", |
| 3758 | .ops = &clk_branch2_ops, |
| 3759 | }, |
| 3760 | }, |
| 3761 | }; |
| 3762 | |
| 3763 | static struct clk_branch gcc_vs_ctrl_clk = { |
| 3764 | .halt_reg = 0x7a010, |
| 3765 | .halt_check = BRANCH_HALT, |
| 3766 | .clkr = { |
| 3767 | .enable_reg = 0x7a010, |
| 3768 | .enable_mask = BIT(0), |
| 3769 | .hw.init = &(struct clk_init_data){ |
| 3770 | .name = "gcc_vs_ctrl_clk", |
| 3771 | .parent_names = (const char *[]){ |
| 3772 | "gcc_vs_ctrl_clk_src", |
| 3773 | }, |
| 3774 | .num_parents = 1, |
| 3775 | .flags = CLK_SET_RATE_PARENT, |
| 3776 | .ops = &clk_branch2_ops, |
| 3777 | }, |
| 3778 | }, |
| 3779 | }; |
| 3780 | |
Deepak Katragadda | d075ba3 | 2017-04-06 13:45:47 -0700 | [diff] [blame] | 3781 | struct clk_hw *gcc_sdm845_hws[] = { |
| 3782 | [MEASURE_ONLY_SNOC_CLK] = &measure_only_snoc_clk.hw, |
| 3783 | [MEASURE_ONLY_CNOC_CLK] = &measure_only_cnoc_clk.hw, |
| 3784 | [MEASURE_ONLY_BIMC_CLK] = &measure_only_bimc_clk.hw, |
| 3785 | [MEASURE_ONLY_IPA_2X_CLK] = &measure_only_ipa_2x_clk.hw, |
| 3786 | }; |
| 3787 | |
Kyle Yan | 6a20fae | 2017-02-14 13:34:41 -0800 | [diff] [blame] | 3788 | static struct clk_regmap *gcc_sdm845_clocks[] = { |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 3789 | [GCC_AGGRE_NOC_PCIE_TBU_CLK] = &gcc_aggre_noc_pcie_tbu_clk.clkr, |
| 3790 | [GCC_AGGRE_UFS_CARD_AXI_CLK] = &gcc_aggre_ufs_card_axi_clk.clkr, |
Deepak Katragadda | 536caff | 2017-04-04 17:47:56 -0700 | [diff] [blame] | 3791 | [GCC_AGGRE_UFS_CARD_AXI_HW_CTL_CLK] = |
| 3792 | &gcc_aggre_ufs_card_axi_hw_ctl_clk.clkr, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 3793 | [GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr, |
Deepak Katragadda | 536caff | 2017-04-04 17:47:56 -0700 | [diff] [blame] | 3794 | [GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK] = |
| 3795 | &gcc_aggre_ufs_phy_axi_hw_ctl_clk.clkr, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 3796 | [GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr, |
| 3797 | [GCC_AGGRE_USB3_SEC_AXI_CLK] = &gcc_aggre_usb3_sec_axi_clk.clkr, |
Deepak Katragadda | 87732a1 | 2017-07-18 12:07:17 -0700 | [diff] [blame] | 3798 | [GCC_APC_VS_CLK] = &gcc_apc_vs_clk.clkr, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 3799 | [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, |
| 3800 | [GCC_CAMERA_AHB_CLK] = &gcc_camera_ahb_clk.clkr, |
| 3801 | [GCC_CAMERA_AXI_CLK] = &gcc_camera_axi_clk.clkr, |
| 3802 | [GCC_CAMERA_XO_CLK] = &gcc_camera_xo_clk.clkr, |
| 3803 | [GCC_CE1_AHB_CLK] = &gcc_ce1_ahb_clk.clkr, |
| 3804 | [GCC_CE1_AXI_CLK] = &gcc_ce1_axi_clk.clkr, |
| 3805 | [GCC_CE1_CLK] = &gcc_ce1_clk.clkr, |
| 3806 | [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr, |
| 3807 | [GCC_CFG_NOC_USB3_SEC_AXI_CLK] = &gcc_cfg_noc_usb3_sec_axi_clk.clkr, |
| 3808 | [GCC_CPUSS_AHB_CLK] = &gcc_cpuss_ahb_clk.clkr, |
| 3809 | [GCC_CPUSS_AHB_CLK_SRC] = &gcc_cpuss_ahb_clk_src.clkr, |
| 3810 | [GCC_CPUSS_DVM_BUS_CLK] = &gcc_cpuss_dvm_bus_clk.clkr, |
| 3811 | [GCC_CPUSS_GNOC_CLK] = &gcc_cpuss_gnoc_clk.clkr, |
| 3812 | [GCC_CPUSS_RBCPR_CLK] = &gcc_cpuss_rbcpr_clk.clkr, |
| 3813 | [GCC_CPUSS_RBCPR_CLK_SRC] = &gcc_cpuss_rbcpr_clk_src.clkr, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 3814 | [GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr, |
| 3815 | [GCC_DISP_AHB_CLK] = &gcc_disp_ahb_clk.clkr, |
| 3816 | [GCC_DISP_AXI_CLK] = &gcc_disp_axi_clk.clkr, |
| 3817 | [GCC_DISP_GPLL0_CLK_SRC] = &gcc_disp_gpll0_clk_src.clkr, |
| 3818 | [GCC_DISP_GPLL0_DIV_CLK_SRC] = &gcc_disp_gpll0_div_clk_src.clkr, |
| 3819 | [GCC_DISP_XO_CLK] = &gcc_disp_xo_clk.clkr, |
| 3820 | [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, |
| 3821 | [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr, |
| 3822 | [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, |
| 3823 | [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr, |
| 3824 | [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, |
| 3825 | [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr, |
| 3826 | [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr, |
| 3827 | [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr, |
| 3828 | [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr, |
Deepak Katragadda | 69ba1ca | 2017-05-12 13:37:52 -0700 | [diff] [blame] | 3829 | [GCC_GPU_IREF_CLK] = &gcc_gpu_iref_clk.clkr, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 3830 | [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr, |
| 3831 | [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr, |
Deepak Katragadda | 87732a1 | 2017-07-18 12:07:17 -0700 | [diff] [blame] | 3832 | [GCC_GPU_VS_CLK] = &gcc_gpu_vs_clk.clkr, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 3833 | [GCC_MSS_AXIS2_CLK] = &gcc_mss_axis2_clk.clkr, |
| 3834 | [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr, |
| 3835 | [GCC_MSS_GPLL0_DIV_CLK_SRC] = &gcc_mss_gpll0_div_clk_src.clkr, |
| 3836 | [GCC_MSS_MFAB_AXIS_CLK] = &gcc_mss_mfab_axis_clk.clkr, |
| 3837 | [GCC_MSS_Q6_MEMNOC_AXI_CLK] = &gcc_mss_q6_memnoc_axi_clk.clkr, |
| 3838 | [GCC_MSS_SNOC_AXI_CLK] = &gcc_mss_snoc_axi_clk.clkr, |
Deepak Katragadda | 87732a1 | 2017-07-18 12:07:17 -0700 | [diff] [blame] | 3839 | [GCC_MSS_VS_CLK] = &gcc_mss_vs_clk.clkr, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 3840 | [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr, |
| 3841 | [GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr, |
| 3842 | [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr, |
| 3843 | [GCC_PCIE_0_CLKREF_CLK] = &gcc_pcie_0_clkref_clk.clkr, |
| 3844 | [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr, |
| 3845 | [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr, |
| 3846 | [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr, |
| 3847 | [GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr, |
| 3848 | [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr, |
| 3849 | [GCC_PCIE_1_AUX_CLK_SRC] = &gcc_pcie_1_aux_clk_src.clkr, |
| 3850 | [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr, |
| 3851 | [GCC_PCIE_1_CLKREF_CLK] = &gcc_pcie_1_clkref_clk.clkr, |
| 3852 | [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr, |
| 3853 | [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr, |
| 3854 | [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr, |
| 3855 | [GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &gcc_pcie_1_slv_q2a_axi_clk.clkr, |
| 3856 | [GCC_PCIE_PHY_AUX_CLK] = &gcc_pcie_phy_aux_clk.clkr, |
| 3857 | [GCC_PCIE_PHY_REFGEN_CLK] = &gcc_pcie_phy_refgen_clk.clkr, |
| 3858 | [GCC_PCIE_PHY_REFGEN_CLK_SRC] = &gcc_pcie_phy_refgen_clk_src.clkr, |
| 3859 | [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, |
| 3860 | [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr, |
| 3861 | [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, |
| 3862 | [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr, |
| 3863 | [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr, |
| 3864 | [GCC_QMIP_CAMERA_AHB_CLK] = &gcc_qmip_camera_ahb_clk.clkr, |
| 3865 | [GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr, |
| 3866 | [GCC_QMIP_VIDEO_AHB_CLK] = &gcc_qmip_video_ahb_clk.clkr, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 3867 | [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr, |
| 3868 | [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr, |
| 3869 | [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr, |
| 3870 | [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr, |
| 3871 | [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr, |
| 3872 | [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr, |
| 3873 | [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr, |
| 3874 | [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr, |
| 3875 | [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr, |
| 3876 | [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr, |
| 3877 | [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr, |
| 3878 | [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr, |
| 3879 | [GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr, |
| 3880 | [GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr, |
| 3881 | [GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.clkr, |
| 3882 | [GCC_QUPV3_WRAP0_S7_CLK_SRC] = &gcc_qupv3_wrap0_s7_clk_src.clkr, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 3883 | [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr, |
| 3884 | [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr, |
| 3885 | [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr, |
| 3886 | [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr, |
| 3887 | [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr, |
| 3888 | [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr, |
| 3889 | [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr, |
| 3890 | [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr, |
| 3891 | [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr, |
| 3892 | [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr, |
| 3893 | [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr, |
| 3894 | [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr, |
| 3895 | [GCC_QUPV3_WRAP1_S6_CLK] = &gcc_qupv3_wrap1_s6_clk.clkr, |
| 3896 | [GCC_QUPV3_WRAP1_S6_CLK_SRC] = &gcc_qupv3_wrap1_s6_clk_src.clkr, |
| 3897 | [GCC_QUPV3_WRAP1_S7_CLK] = &gcc_qupv3_wrap1_s7_clk.clkr, |
| 3898 | [GCC_QUPV3_WRAP1_S7_CLK_SRC] = &gcc_qupv3_wrap1_s7_clk_src.clkr, |
| 3899 | [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr, |
| 3900 | [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr, |
| 3901 | [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr, |
| 3902 | [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 3903 | [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, |
| 3904 | [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, |
| 3905 | [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr, |
| 3906 | [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr, |
| 3907 | [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr, |
| 3908 | [GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdcc4_apps_clk_src.clkr, |
| 3909 | [GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr, |
| 3910 | [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr, |
| 3911 | [GCC_TSIF_INACTIVITY_TIMERS_CLK] = |
| 3912 | &gcc_tsif_inactivity_timers_clk.clkr, |
| 3913 | [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr, |
| 3914 | [GCC_TSIF_REF_CLK_SRC] = &gcc_tsif_ref_clk_src.clkr, |
| 3915 | [GCC_UFS_CARD_AHB_CLK] = &gcc_ufs_card_ahb_clk.clkr, |
| 3916 | [GCC_UFS_CARD_AXI_CLK] = &gcc_ufs_card_axi_clk.clkr, |
Deepak Katragadda | 536caff | 2017-04-04 17:47:56 -0700 | [diff] [blame] | 3917 | [GCC_UFS_CARD_AXI_HW_CTL_CLK] = &gcc_ufs_card_axi_hw_ctl_clk.clkr, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 3918 | [GCC_UFS_CARD_AXI_CLK_SRC] = &gcc_ufs_card_axi_clk_src.clkr, |
| 3919 | [GCC_UFS_CARD_CLKREF_CLK] = &gcc_ufs_card_clkref_clk.clkr, |
| 3920 | [GCC_UFS_CARD_ICE_CORE_CLK] = &gcc_ufs_card_ice_core_clk.clkr, |
Deepak Katragadda | 536caff | 2017-04-04 17:47:56 -0700 | [diff] [blame] | 3921 | [GCC_UFS_CARD_ICE_CORE_HW_CTL_CLK] = |
| 3922 | &gcc_ufs_card_ice_core_hw_ctl_clk.clkr, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 3923 | [GCC_UFS_CARD_ICE_CORE_CLK_SRC] = &gcc_ufs_card_ice_core_clk_src.clkr, |
| 3924 | [GCC_UFS_CARD_PHY_AUX_CLK] = &gcc_ufs_card_phy_aux_clk.clkr, |
Deepak Katragadda | 536caff | 2017-04-04 17:47:56 -0700 | [diff] [blame] | 3925 | [GCC_UFS_CARD_PHY_AUX_HW_CTL_CLK] = |
| 3926 | &gcc_ufs_card_phy_aux_hw_ctl_clk.clkr, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 3927 | [GCC_UFS_CARD_PHY_AUX_CLK_SRC] = &gcc_ufs_card_phy_aux_clk_src.clkr, |
| 3928 | [GCC_UFS_CARD_RX_SYMBOL_0_CLK] = &gcc_ufs_card_rx_symbol_0_clk.clkr, |
| 3929 | [GCC_UFS_CARD_RX_SYMBOL_1_CLK] = &gcc_ufs_card_rx_symbol_1_clk.clkr, |
| 3930 | [GCC_UFS_CARD_TX_SYMBOL_0_CLK] = &gcc_ufs_card_tx_symbol_0_clk.clkr, |
| 3931 | [GCC_UFS_CARD_UNIPRO_CORE_CLK] = &gcc_ufs_card_unipro_core_clk.clkr, |
Deepak Katragadda | 536caff | 2017-04-04 17:47:56 -0700 | [diff] [blame] | 3932 | [GCC_UFS_CARD_UNIPRO_CORE_HW_CTL_CLK] = |
| 3933 | &gcc_ufs_card_unipro_core_hw_ctl_clk.clkr, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 3934 | [GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC] = |
| 3935 | &gcc_ufs_card_unipro_core_clk_src.clkr, |
| 3936 | [GCC_UFS_MEM_CLKREF_CLK] = &gcc_ufs_mem_clkref_clk.clkr, |
| 3937 | [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr, |
| 3938 | [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr, |
Deepak Katragadda | 536caff | 2017-04-04 17:47:56 -0700 | [diff] [blame] | 3939 | [GCC_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_ufs_phy_axi_hw_ctl_clk.clkr, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 3940 | [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr, |
| 3941 | [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr, |
Deepak Katragadda | 536caff | 2017-04-04 17:47:56 -0700 | [diff] [blame] | 3942 | [GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK] = |
| 3943 | &gcc_ufs_phy_ice_core_hw_ctl_clk.clkr, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 3944 | [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr, |
| 3945 | [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr, |
Deepak Katragadda | 536caff | 2017-04-04 17:47:56 -0700 | [diff] [blame] | 3946 | [GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK] = &gcc_ufs_phy_phy_aux_hw_ctl_clk.clkr, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 3947 | [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr, |
| 3948 | [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr, |
| 3949 | [GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr, |
| 3950 | [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr, |
| 3951 | [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr, |
Deepak Katragadda | 536caff | 2017-04-04 17:47:56 -0700 | [diff] [blame] | 3952 | [GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK] = |
| 3953 | &gcc_ufs_phy_unipro_core_hw_ctl_clk.clkr, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 3954 | [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = |
| 3955 | &gcc_ufs_phy_unipro_core_clk_src.clkr, |
| 3956 | [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr, |
| 3957 | [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr, |
| 3958 | [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr, |
| 3959 | [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = |
| 3960 | &gcc_usb30_prim_mock_utmi_clk_src.clkr, |
| 3961 | [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr, |
| 3962 | [GCC_USB30_SEC_MASTER_CLK] = &gcc_usb30_sec_master_clk.clkr, |
| 3963 | [GCC_USB30_SEC_MASTER_CLK_SRC] = &gcc_usb30_sec_master_clk_src.clkr, |
| 3964 | [GCC_USB30_SEC_MOCK_UTMI_CLK] = &gcc_usb30_sec_mock_utmi_clk.clkr, |
| 3965 | [GCC_USB30_SEC_MOCK_UTMI_CLK_SRC] = |
| 3966 | &gcc_usb30_sec_mock_utmi_clk_src.clkr, |
| 3967 | [GCC_USB30_SEC_SLEEP_CLK] = &gcc_usb30_sec_sleep_clk.clkr, |
| 3968 | [GCC_USB3_PRIM_CLKREF_CLK] = &gcc_usb3_prim_clkref_clk.clkr, |
| 3969 | [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr, |
| 3970 | [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr, |
| 3971 | [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr, |
| 3972 | [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr, |
| 3973 | [GCC_USB3_SEC_CLKREF_CLK] = &gcc_usb3_sec_clkref_clk.clkr, |
| 3974 | [GCC_USB3_SEC_PHY_AUX_CLK] = &gcc_usb3_sec_phy_aux_clk.clkr, |
| 3975 | [GCC_USB3_SEC_PHY_AUX_CLK_SRC] = &gcc_usb3_sec_phy_aux_clk_src.clkr, |
| 3976 | [GCC_USB3_SEC_PHY_COM_AUX_CLK] = &gcc_usb3_sec_phy_com_aux_clk.clkr, |
| 3977 | [GCC_USB3_SEC_PHY_PIPE_CLK] = &gcc_usb3_sec_phy_pipe_clk.clkr, |
| 3978 | [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr, |
Deepak Katragadda | 87732a1 | 2017-07-18 12:07:17 -0700 | [diff] [blame] | 3979 | [GCC_VDDA_VS_CLK] = &gcc_vdda_vs_clk.clkr, |
| 3980 | [GCC_VDDCX_VS_CLK] = &gcc_vddcx_vs_clk.clkr, |
| 3981 | [GCC_VDDMX_VS_CLK] = &gcc_vddmx_vs_clk.clkr, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 3982 | [GCC_VIDEO_AHB_CLK] = &gcc_video_ahb_clk.clkr, |
| 3983 | [GCC_VIDEO_AXI_CLK] = &gcc_video_axi_clk.clkr, |
| 3984 | [GCC_VIDEO_XO_CLK] = &gcc_video_xo_clk.clkr, |
Deepak Katragadda | 87732a1 | 2017-07-18 12:07:17 -0700 | [diff] [blame] | 3985 | [GCC_VS_CTRL_AHB_CLK] = &gcc_vs_ctrl_ahb_clk.clkr, |
| 3986 | [GCC_VS_CTRL_CLK] = &gcc_vs_ctrl_clk.clkr, |
| 3987 | [GCC_VS_CTRL_CLK_SRC] = &gcc_vs_ctrl_clk_src.clkr, |
| 3988 | [GCC_VSENSOR_CLK_SRC] = &gcc_vsensor_clk_src.clkr, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 3989 | [GPLL0] = &gpll0.clkr, |
| 3990 | [GPLL0_OUT_EVEN] = &gpll0_out_even.clkr, |
Deepak Katragadda | f56802e | 2017-07-14 13:39:03 -0700 | [diff] [blame] | 3991 | [GPLL4] = &gpll4.clkr, |
Deepak Katragadda | 443bd8d | 2017-08-28 22:30:19 +0530 | [diff] [blame] | 3992 | [GCC_SDCC1_AHB_CLK] = NULL, |
| 3993 | [GCC_SDCC1_APPS_CLK] = NULL, |
| 3994 | [GCC_SDCC1_ICE_CORE_CLK] = NULL, |
| 3995 | [GCC_SDCC1_APPS_CLK_SRC] = NULL, |
| 3996 | [GCC_SDCC1_ICE_CORE_CLK_SRC] = NULL, |
| 3997 | [GPLL6] = NULL, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 3998 | }; |
| 3999 | |
Kyle Yan | 6a20fae | 2017-02-14 13:34:41 -0800 | [diff] [blame] | 4000 | static const struct qcom_reset_map gcc_sdm845_resets[] = { |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 4001 | [GCC_MMSS_BCR] = { 0xb000 }, |
| 4002 | [GCC_PCIE_0_BCR] = { 0x6b000 }, |
| 4003 | [GCC_PCIE_1_BCR] = { 0x8d000 }, |
| 4004 | [GCC_PCIE_PHY_BCR] = { 0x6f000 }, |
| 4005 | [GCC_PDM_BCR] = { 0x33000 }, |
| 4006 | [GCC_PRNG_BCR] = { 0x34000 }, |
| 4007 | [GCC_QUPV3_WRAPPER_0_BCR] = { 0x17000 }, |
| 4008 | [GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 }, |
Deepak Katragadda | 15e9aca | 2017-03-14 14:10:59 -0700 | [diff] [blame] | 4009 | [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 }, |
| 4010 | [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 }, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 4011 | [GCC_SDCC2_BCR] = { 0x14000 }, |
| 4012 | [GCC_SDCC4_BCR] = { 0x16000 }, |
| 4013 | [GCC_TSIF_BCR] = { 0x36000 }, |
| 4014 | [GCC_UFS_CARD_BCR] = { 0x75000 }, |
| 4015 | [GCC_UFS_PHY_BCR] = { 0x77000 }, |
| 4016 | [GCC_USB30_PRIM_BCR] = { 0xf000 }, |
| 4017 | [GCC_USB30_SEC_BCR] = { 0x10000 }, |
Deepak Katragadda | 15e9aca | 2017-03-14 14:10:59 -0700 | [diff] [blame] | 4018 | [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 }, |
| 4019 | [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 }, |
| 4020 | [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 }, |
| 4021 | [GCC_USB3_PHY_SEC_BCR] = { 0x5000c }, |
| 4022 | [GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 }, |
| 4023 | [GCC_USB3_DP_PHY_SEC_BCR] = { 0x50014 }, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 4024 | [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 }, |
Deepak Katragadda | 1a64727 | 2017-04-21 14:16:44 -0700 | [diff] [blame] | 4025 | [GCC_PCIE_0_PHY_BCR] = { 0x6c01c }, |
| 4026 | [GCC_PCIE_1_PHY_BCR] = { 0x8e01c }, |
Deepak Katragadda | 443bd8d | 2017-08-28 22:30:19 +0530 | [diff] [blame] | 4027 | [GCC_SDCC1_BCR] = { 0x26000 }, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 4028 | }; |
| 4029 | |
Taniya Das | 5bac2ec | 2017-04-13 15:22:34 +0530 | [diff] [blame] | 4030 | /* List of RCG clocks and corresponding flags requested for DFS Mode */ |
| 4031 | static struct clk_dfs gcc_dfs_clocks[] = { |
| 4032 | { &gcc_qupv3_wrap0_s0_clk_src, DFS_ENABLE_RCG }, |
| 4033 | { &gcc_qupv3_wrap0_s1_clk_src, DFS_ENABLE_RCG }, |
| 4034 | { &gcc_qupv3_wrap0_s2_clk_src, DFS_ENABLE_RCG }, |
| 4035 | { &gcc_qupv3_wrap0_s3_clk_src, DFS_ENABLE_RCG }, |
| 4036 | { &gcc_qupv3_wrap0_s4_clk_src, DFS_ENABLE_RCG }, |
| 4037 | { &gcc_qupv3_wrap0_s5_clk_src, DFS_ENABLE_RCG }, |
| 4038 | { &gcc_qupv3_wrap0_s6_clk_src, DFS_ENABLE_RCG }, |
| 4039 | { &gcc_qupv3_wrap0_s7_clk_src, DFS_ENABLE_RCG }, |
| 4040 | { &gcc_qupv3_wrap1_s0_clk_src, DFS_ENABLE_RCG }, |
| 4041 | { &gcc_qupv3_wrap1_s1_clk_src, DFS_ENABLE_RCG }, |
| 4042 | { &gcc_qupv3_wrap1_s2_clk_src, DFS_ENABLE_RCG }, |
| 4043 | { &gcc_qupv3_wrap1_s3_clk_src, DFS_ENABLE_RCG }, |
| 4044 | { &gcc_qupv3_wrap1_s4_clk_src, DFS_ENABLE_RCG }, |
| 4045 | { &gcc_qupv3_wrap1_s5_clk_src, DFS_ENABLE_RCG }, |
| 4046 | { &gcc_qupv3_wrap1_s6_clk_src, DFS_ENABLE_RCG }, |
| 4047 | { &gcc_qupv3_wrap1_s7_clk_src, DFS_ENABLE_RCG }, |
| 4048 | }; |
| 4049 | |
| 4050 | static const struct qcom_cc_dfs_desc gcc_sdm845_dfs_desc = { |
| 4051 | .clks = gcc_dfs_clocks, |
| 4052 | .num_clks = ARRAY_SIZE(gcc_dfs_clocks), |
| 4053 | }; |
| 4054 | |
Kyle Yan | 6a20fae | 2017-02-14 13:34:41 -0800 | [diff] [blame] | 4055 | static const struct regmap_config gcc_sdm845_regmap_config = { |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 4056 | .reg_bits = 32, |
| 4057 | .reg_stride = 4, |
| 4058 | .val_bits = 32, |
| 4059 | .max_register = 0x182090, |
| 4060 | .fast_io = true, |
| 4061 | }; |
| 4062 | |
Kyle Yan | 6a20fae | 2017-02-14 13:34:41 -0800 | [diff] [blame] | 4063 | static const struct qcom_cc_desc gcc_sdm845_desc = { |
| 4064 | .config = &gcc_sdm845_regmap_config, |
| 4065 | .clks = gcc_sdm845_clocks, |
| 4066 | .num_clks = ARRAY_SIZE(gcc_sdm845_clocks), |
| 4067 | .resets = gcc_sdm845_resets, |
| 4068 | .num_resets = ARRAY_SIZE(gcc_sdm845_resets), |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 4069 | }; |
| 4070 | |
Kyle Yan | 6a20fae | 2017-02-14 13:34:41 -0800 | [diff] [blame] | 4071 | static const struct of_device_id gcc_sdm845_match_table[] = { |
| 4072 | { .compatible = "qcom,gcc-sdm845" }, |
Deepak Katragadda | 6c846e3 | 2017-06-07 14:09:49 -0700 | [diff] [blame] | 4073 | { .compatible = "qcom,gcc-sdm845-v2" }, |
Deepak Katragadda | 443bd8d | 2017-08-28 22:30:19 +0530 | [diff] [blame] | 4074 | { .compatible = "qcom,gcc-sdm670" }, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 4075 | { } |
| 4076 | }; |
Kyle Yan | 6a20fae | 2017-02-14 13:34:41 -0800 | [diff] [blame] | 4077 | MODULE_DEVICE_TABLE(of, gcc_sdm845_match_table); |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 4078 | |
Deepak Katragadda | 6c846e3 | 2017-06-07 14:09:49 -0700 | [diff] [blame] | 4079 | static void gcc_sdm845_fixup_sdm845v2(void) |
| 4080 | { |
| 4081 | gcc_qupv3_wrap0_s0_clk_src.freq_tbl = |
| 4082 | ftbl_gcc_qupv3_wrap0_s0_clk_src_sdm845_v2; |
| 4083 | gcc_qupv3_wrap0_s0_clk_src.clkr.hw.init->rate_max[VDD_CX_MIN] = |
| 4084 | 50000000; |
| 4085 | gcc_qupv3_wrap0_s0_clk_src.clkr.hw.init->rate_max[VDD_CX_NOMINAL] = |
| 4086 | 128000000; |
| 4087 | gcc_qupv3_wrap0_s1_clk_src.freq_tbl = |
| 4088 | ftbl_gcc_qupv3_wrap0_s0_clk_src_sdm845_v2; |
| 4089 | gcc_qupv3_wrap0_s1_clk_src.clkr.hw.init->rate_max[VDD_CX_MIN] = |
| 4090 | 50000000; |
| 4091 | gcc_qupv3_wrap0_s1_clk_src.clkr.hw.init->rate_max[VDD_CX_NOMINAL] = |
| 4092 | 128000000; |
| 4093 | gcc_qupv3_wrap0_s2_clk_src.freq_tbl = |
| 4094 | ftbl_gcc_qupv3_wrap0_s0_clk_src_sdm845_v2; |
| 4095 | gcc_qupv3_wrap0_s2_clk_src.clkr.hw.init->rate_max[VDD_CX_MIN] = |
| 4096 | 50000000; |
| 4097 | gcc_qupv3_wrap0_s2_clk_src.clkr.hw.init->rate_max[VDD_CX_NOMINAL] = |
| 4098 | 128000000; |
| 4099 | gcc_qupv3_wrap0_s3_clk_src.freq_tbl = |
| 4100 | ftbl_gcc_qupv3_wrap0_s0_clk_src_sdm845_v2; |
| 4101 | gcc_qupv3_wrap0_s3_clk_src.clkr.hw.init->rate_max[VDD_CX_MIN] = |
| 4102 | 50000000; |
| 4103 | gcc_qupv3_wrap0_s3_clk_src.clkr.hw.init->rate_max[VDD_CX_NOMINAL] = |
| 4104 | 128000000; |
| 4105 | gcc_qupv3_wrap0_s4_clk_src.freq_tbl = |
| 4106 | ftbl_gcc_qupv3_wrap0_s0_clk_src_sdm845_v2; |
| 4107 | gcc_qupv3_wrap0_s4_clk_src.clkr.hw.init->rate_max[VDD_CX_MIN] = |
| 4108 | 50000000; |
| 4109 | gcc_qupv3_wrap0_s4_clk_src.clkr.hw.init->rate_max[VDD_CX_NOMINAL] = |
| 4110 | 128000000; |
| 4111 | gcc_qupv3_wrap0_s5_clk_src.freq_tbl = |
| 4112 | ftbl_gcc_qupv3_wrap0_s0_clk_src_sdm845_v2; |
| 4113 | gcc_qupv3_wrap0_s5_clk_src.clkr.hw.init->rate_max[VDD_CX_MIN] = |
| 4114 | 50000000; |
| 4115 | gcc_qupv3_wrap0_s5_clk_src.clkr.hw.init->rate_max[VDD_CX_NOMINAL] = |
| 4116 | 128000000; |
| 4117 | gcc_qupv3_wrap0_s6_clk_src.freq_tbl = |
| 4118 | ftbl_gcc_qupv3_wrap0_s0_clk_src_sdm845_v2; |
| 4119 | gcc_qupv3_wrap0_s6_clk_src.clkr.hw.init->rate_max[VDD_CX_MIN] = |
| 4120 | 50000000; |
| 4121 | gcc_qupv3_wrap0_s6_clk_src.clkr.hw.init->rate_max[VDD_CX_NOMINAL] = |
| 4122 | 128000000; |
| 4123 | gcc_qupv3_wrap0_s7_clk_src.freq_tbl = |
| 4124 | ftbl_gcc_qupv3_wrap0_s0_clk_src_sdm845_v2; |
| 4125 | gcc_qupv3_wrap0_s7_clk_src.clkr.hw.init->rate_max[VDD_CX_MIN] = |
| 4126 | 50000000; |
| 4127 | gcc_qupv3_wrap0_s7_clk_src.clkr.hw.init->rate_max[VDD_CX_NOMINAL] = |
| 4128 | 128000000; |
| 4129 | gcc_qupv3_wrap1_s0_clk_src.freq_tbl = |
| 4130 | ftbl_gcc_qupv3_wrap0_s0_clk_src_sdm845_v2; |
| 4131 | gcc_qupv3_wrap1_s0_clk_src.clkr.hw.init->rate_max[VDD_CX_MIN] = |
| 4132 | 50000000; |
| 4133 | gcc_qupv3_wrap1_s0_clk_src.clkr.hw.init->rate_max[VDD_CX_NOMINAL] = |
| 4134 | 128000000; |
| 4135 | gcc_qupv3_wrap1_s1_clk_src.freq_tbl = |
| 4136 | ftbl_gcc_qupv3_wrap0_s0_clk_src_sdm845_v2; |
| 4137 | gcc_qupv3_wrap1_s1_clk_src.clkr.hw.init->rate_max[VDD_CX_MIN] = |
| 4138 | 50000000; |
| 4139 | gcc_qupv3_wrap1_s1_clk_src.clkr.hw.init->rate_max[VDD_CX_NOMINAL] = |
| 4140 | 128000000; |
| 4141 | gcc_qupv3_wrap1_s2_clk_src.freq_tbl = |
| 4142 | ftbl_gcc_qupv3_wrap0_s0_clk_src_sdm845_v2; |
| 4143 | gcc_qupv3_wrap1_s2_clk_src.clkr.hw.init->rate_max[VDD_CX_MIN] = |
| 4144 | 50000000; |
| 4145 | gcc_qupv3_wrap1_s2_clk_src.clkr.hw.init->rate_max[VDD_CX_NOMINAL] = |
| 4146 | 128000000; |
| 4147 | gcc_qupv3_wrap1_s3_clk_src.freq_tbl = |
| 4148 | ftbl_gcc_qupv3_wrap0_s0_clk_src_sdm845_v2; |
| 4149 | gcc_qupv3_wrap1_s3_clk_src.clkr.hw.init->rate_max[VDD_CX_MIN] = |
| 4150 | 50000000; |
| 4151 | gcc_qupv3_wrap1_s3_clk_src.clkr.hw.init->rate_max[VDD_CX_NOMINAL] = |
| 4152 | 128000000; |
| 4153 | gcc_qupv3_wrap1_s4_clk_src.freq_tbl = |
| 4154 | ftbl_gcc_qupv3_wrap0_s0_clk_src_sdm845_v2; |
| 4155 | gcc_qupv3_wrap1_s4_clk_src.clkr.hw.init->rate_max[VDD_CX_MIN] = |
| 4156 | 50000000; |
| 4157 | gcc_qupv3_wrap1_s4_clk_src.clkr.hw.init->rate_max[VDD_CX_NOMINAL] = |
| 4158 | 128000000; |
| 4159 | gcc_qupv3_wrap1_s5_clk_src.freq_tbl = |
| 4160 | ftbl_gcc_qupv3_wrap0_s0_clk_src_sdm845_v2; |
| 4161 | gcc_qupv3_wrap1_s5_clk_src.clkr.hw.init->rate_max[VDD_CX_MIN] = |
| 4162 | 50000000; |
| 4163 | gcc_qupv3_wrap1_s5_clk_src.clkr.hw.init->rate_max[VDD_CX_NOMINAL] = |
| 4164 | 128000000; |
| 4165 | gcc_qupv3_wrap1_s6_clk_src.freq_tbl = |
| 4166 | ftbl_gcc_qupv3_wrap0_s0_clk_src_sdm845_v2; |
| 4167 | gcc_qupv3_wrap1_s6_clk_src.clkr.hw.init->rate_max[VDD_CX_MIN] = |
| 4168 | 50000000; |
| 4169 | gcc_qupv3_wrap1_s6_clk_src.clkr.hw.init->rate_max[VDD_CX_NOMINAL] = |
| 4170 | 128000000; |
| 4171 | gcc_qupv3_wrap1_s7_clk_src.freq_tbl = |
| 4172 | ftbl_gcc_qupv3_wrap0_s0_clk_src_sdm845_v2; |
| 4173 | gcc_qupv3_wrap1_s7_clk_src.clkr.hw.init->rate_max[VDD_CX_MIN] = |
| 4174 | 50000000; |
| 4175 | gcc_qupv3_wrap1_s7_clk_src.clkr.hw.init->rate_max[VDD_CX_NOMINAL] = |
| 4176 | 128000000; |
| 4177 | gcc_ufs_card_axi_clk_src.freq_tbl = |
| 4178 | ftbl_gcc_ufs_card_axi_clk_src_sdm845_v2; |
| 4179 | gcc_ufs_card_axi_clk_src.clkr.hw.init->rate_max[VDD_CX_HIGH] = |
| 4180 | 240000000; |
| 4181 | gcc_ufs_phy_axi_clk_src.freq_tbl = |
| 4182 | ftbl_gcc_ufs_card_axi_clk_src_sdm845_v2; |
| 4183 | } |
| 4184 | |
Deepak Katragadda | 443bd8d | 2017-08-28 22:30:19 +0530 | [diff] [blame] | 4185 | static void gcc_sdm845_fixup_sdm670(void) |
| 4186 | { |
| 4187 | gcc_sdm845_fixup_sdm845v2(); |
| 4188 | |
| 4189 | gcc_sdm845_clocks[GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr; |
| 4190 | gcc_sdm845_clocks[GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr; |
| 4191 | gcc_sdm845_clocks[GCC_SDCC1_ICE_CORE_CLK] = |
| 4192 | &gcc_sdcc1_ice_core_clk.clkr; |
| 4193 | gcc_sdm845_clocks[GCC_SDCC1_APPS_CLK_SRC] = |
| 4194 | &gcc_sdcc1_apps_clk_src.clkr; |
| 4195 | gcc_sdm845_clocks[GCC_SDCC1_ICE_CORE_CLK_SRC] = |
| 4196 | &gcc_sdcc1_ice_core_clk_src.clkr; |
| 4197 | gcc_sdm845_clocks[GPLL6] = &gpll6.clkr; |
| 4198 | gcc_sdm845_clocks[GCC_AGGRE_UFS_CARD_AXI_CLK] = NULL; |
| 4199 | gcc_sdm845_clocks[GCC_AGGRE_UFS_CARD_AXI_HW_CTL_CLK] = NULL; |
| 4200 | gcc_sdm845_clocks[GCC_AGGRE_USB3_SEC_AXI_CLK] = NULL; |
| 4201 | gcc_sdm845_clocks[GCC_AGGRE_NOC_PCIE_TBU_CLK] = NULL; |
| 4202 | gcc_sdm845_clocks[GCC_CFG_NOC_USB3_SEC_AXI_CLK] = NULL; |
| 4203 | gcc_sdm845_clocks[GCC_PCIE_0_AUX_CLK] = NULL; |
| 4204 | gcc_sdm845_clocks[GCC_PCIE_0_AUX_CLK_SRC] = NULL; |
| 4205 | gcc_sdm845_clocks[GCC_PCIE_0_CFG_AHB_CLK] = NULL; |
| 4206 | gcc_sdm845_clocks[GCC_PCIE_0_CLKREF_CLK] = NULL; |
| 4207 | gcc_sdm845_clocks[GCC_PCIE_0_MSTR_AXI_CLK] = NULL; |
| 4208 | gcc_sdm845_clocks[GCC_PCIE_0_PIPE_CLK] = NULL; |
| 4209 | gcc_sdm845_clocks[GCC_PCIE_0_SLV_AXI_CLK] = NULL; |
| 4210 | gcc_sdm845_clocks[GCC_PCIE_0_SLV_Q2A_AXI_CLK] = NULL; |
| 4211 | gcc_sdm845_clocks[GCC_PCIE_1_AUX_CLK] = NULL; |
| 4212 | gcc_sdm845_clocks[GCC_PCIE_1_AUX_CLK_SRC] = NULL; |
| 4213 | gcc_sdm845_clocks[GCC_PCIE_1_CFG_AHB_CLK] = NULL; |
| 4214 | gcc_sdm845_clocks[GCC_PCIE_1_CLKREF_CLK] = NULL; |
| 4215 | gcc_sdm845_clocks[GCC_PCIE_1_MSTR_AXI_CLK] = NULL; |
| 4216 | gcc_sdm845_clocks[GCC_PCIE_1_PIPE_CLK] = NULL; |
| 4217 | gcc_sdm845_clocks[GCC_PCIE_1_SLV_AXI_CLK] = NULL; |
| 4218 | gcc_sdm845_clocks[GCC_PCIE_1_SLV_Q2A_AXI_CLK] = NULL; |
| 4219 | gcc_sdm845_clocks[GCC_PCIE_PHY_AUX_CLK] = NULL; |
| 4220 | gcc_sdm845_clocks[GCC_PCIE_PHY_REFGEN_CLK] = NULL; |
| 4221 | gcc_sdm845_clocks[GCC_PCIE_PHY_REFGEN_CLK_SRC] = NULL; |
| 4222 | gcc_sdm845_clocks[GCC_UFS_CARD_AHB_CLK] = NULL; |
| 4223 | gcc_sdm845_clocks[GCC_UFS_CARD_AXI_CLK] = NULL; |
| 4224 | gcc_sdm845_clocks[GCC_UFS_CARD_AXI_HW_CTL_CLK] = NULL; |
| 4225 | gcc_sdm845_clocks[GCC_UFS_CARD_AXI_CLK_SRC] = NULL; |
| 4226 | gcc_sdm845_clocks[GCC_UFS_CARD_CLKREF_CLK] = NULL; |
| 4227 | gcc_sdm845_clocks[GCC_UFS_CARD_ICE_CORE_CLK] = NULL; |
| 4228 | gcc_sdm845_clocks[GCC_UFS_CARD_ICE_CORE_HW_CTL_CLK] = NULL; |
| 4229 | gcc_sdm845_clocks[GCC_UFS_CARD_ICE_CORE_CLK_SRC] = NULL; |
| 4230 | gcc_sdm845_clocks[GCC_UFS_CARD_PHY_AUX_CLK] = NULL; |
| 4231 | gcc_sdm845_clocks[GCC_UFS_CARD_PHY_AUX_HW_CTL_CLK] = NULL; |
| 4232 | gcc_sdm845_clocks[GCC_UFS_CARD_PHY_AUX_CLK_SRC] = NULL; |
| 4233 | gcc_sdm845_clocks[GCC_UFS_CARD_RX_SYMBOL_0_CLK] = NULL; |
| 4234 | gcc_sdm845_clocks[GCC_UFS_CARD_RX_SYMBOL_1_CLK] = NULL; |
| 4235 | gcc_sdm845_clocks[GCC_UFS_CARD_TX_SYMBOL_0_CLK] = NULL; |
| 4236 | gcc_sdm845_clocks[GCC_UFS_CARD_UNIPRO_CORE_CLK] = NULL; |
| 4237 | gcc_sdm845_clocks[GCC_UFS_CARD_UNIPRO_CORE_HW_CTL_CLK] = NULL; |
| 4238 | gcc_sdm845_clocks[GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC] = NULL; |
| 4239 | gcc_sdm845_clocks[GCC_UFS_PHY_RX_SYMBOL_1_CLK] = NULL; |
| 4240 | gcc_sdm845_clocks[GCC_USB30_SEC_MASTER_CLK] = NULL; |
| 4241 | gcc_sdm845_clocks[GCC_USB30_SEC_MASTER_CLK_SRC] = NULL; |
| 4242 | gcc_sdm845_clocks[GCC_USB30_SEC_MOCK_UTMI_CLK] = NULL; |
| 4243 | gcc_sdm845_clocks[GCC_USB30_SEC_MOCK_UTMI_CLK_SRC] = NULL; |
| 4244 | gcc_sdm845_clocks[GCC_USB30_SEC_SLEEP_CLK] = NULL; |
| 4245 | gcc_sdm845_clocks[GCC_USB3_SEC_CLKREF_CLK] = NULL; |
| 4246 | gcc_sdm845_clocks[GCC_USB3_SEC_PHY_AUX_CLK] = NULL; |
| 4247 | gcc_sdm845_clocks[GCC_USB3_SEC_PHY_AUX_CLK_SRC] = NULL; |
| 4248 | gcc_sdm845_clocks[GCC_USB3_SEC_PHY_COM_AUX_CLK] = NULL; |
| 4249 | gcc_sdm845_clocks[GCC_USB3_SEC_PHY_PIPE_CLK] = NULL; |
| 4250 | |
| 4251 | gcc_cpuss_rbcpr_clk_src.freq_tbl = ftbl_gcc_cpuss_rbcpr_clk_src_sdm670; |
| 4252 | gcc_cpuss_rbcpr_clk_src.clkr.hw.init->rate_max[VDD_CX_NOMINAL] = |
| 4253 | 50000000; |
| 4254 | gcc_sdcc2_apps_clk_src.clkr.hw.init->rate_max[VDD_CX_LOWER] = |
| 4255 | 50000000; |
| 4256 | gcc_sdcc2_apps_clk_src.clkr.hw.init->rate_max[VDD_CX_LOW_L1] = |
| 4257 | 100000000; |
| 4258 | gcc_sdcc2_apps_clk_src.clkr.hw.init->rate_max[VDD_CX_NOMINAL] = |
| 4259 | 201500000; |
| 4260 | gcc_sdcc4_apps_clk_src.freq_tbl = ftbl_gcc_sdcc4_apps_clk_src_sdm670; |
| 4261 | gcc_sdcc4_apps_clk_src.clkr.hw.init->rate_max[VDD_CX_LOWER] = |
| 4262 | 33333333; |
| 4263 | } |
| 4264 | |
Deepak Katragadda | 6c846e3 | 2017-06-07 14:09:49 -0700 | [diff] [blame] | 4265 | static int gcc_sdm845_fixup(struct platform_device *pdev) |
| 4266 | { |
| 4267 | const char *compat = NULL; |
| 4268 | int compatlen = 0; |
| 4269 | |
| 4270 | compat = of_get_property(pdev->dev.of_node, "compatible", &compatlen); |
| 4271 | if (!compat || (compatlen <= 0)) |
| 4272 | return -EINVAL; |
| 4273 | |
| 4274 | if (!strcmp(compat, "qcom,gcc-sdm845-v2")) |
| 4275 | gcc_sdm845_fixup_sdm845v2(); |
Deepak Katragadda | 443bd8d | 2017-08-28 22:30:19 +0530 | [diff] [blame] | 4276 | else if (!strcmp(compat, "qcom,gcc-sdm670")) |
| 4277 | gcc_sdm845_fixup_sdm670(); |
Deepak Katragadda | 6c846e3 | 2017-06-07 14:09:49 -0700 | [diff] [blame] | 4278 | |
| 4279 | return 0; |
| 4280 | } |
| 4281 | |
Kyle Yan | 6a20fae | 2017-02-14 13:34:41 -0800 | [diff] [blame] | 4282 | static int gcc_sdm845_probe(struct platform_device *pdev) |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 4283 | { |
Deepak Katragadda | d075ba3 | 2017-04-06 13:45:47 -0700 | [diff] [blame] | 4284 | struct clk *clk; |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 4285 | struct regmap *regmap; |
Deepak Katragadda | d075ba3 | 2017-04-06 13:45:47 -0700 | [diff] [blame] | 4286 | int i, ret = 0; |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 4287 | |
Kyle Yan | 6a20fae | 2017-02-14 13:34:41 -0800 | [diff] [blame] | 4288 | regmap = qcom_cc_map(pdev, &gcc_sdm845_desc); |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 4289 | if (IS_ERR(regmap)) |
| 4290 | return PTR_ERR(regmap); |
| 4291 | |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 4292 | /* |
Deepak Katragadda | b666c98 | 2017-04-10 14:16:17 -0700 | [diff] [blame] | 4293 | * Set the *_SLEEP_ENA bits to allow certain cpuss* clocks to be |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 4294 | * turned off by hardware during certain apps low power modes. |
| 4295 | */ |
| 4296 | regmap_update_bits(regmap, GCC_APCS_CLOCK_SLEEP_ENA_VOTE_OFFSET, |
Deepak Katragadda | b666c98 | 2017-04-10 14:16:17 -0700 | [diff] [blame] | 4297 | CPUSS_AHB_CLK_SLEEP_ENA | SYS_NOC_CPUSS_AHB_CLK_SLEEP_ENA, |
| 4298 | CPUSS_AHB_CLK_SLEEP_ENA | SYS_NOC_CPUSS_AHB_CLK_SLEEP_ENA); |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 4299 | |
| 4300 | vdd_cx.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_cx"); |
| 4301 | if (IS_ERR(vdd_cx.regulator[0])) { |
| 4302 | if (!(PTR_ERR(vdd_cx.regulator[0]) == -EPROBE_DEFER)) |
| 4303 | dev_err(&pdev->dev, |
| 4304 | "Unable to get vdd_cx regulator\n"); |
| 4305 | return PTR_ERR(vdd_cx.regulator[0]); |
| 4306 | } |
| 4307 | |
| 4308 | vdd_cx_ao.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_cx_ao"); |
| 4309 | if (IS_ERR(vdd_cx_ao.regulator[0])) { |
| 4310 | if (!(PTR_ERR(vdd_cx_ao.regulator[0]) == -EPROBE_DEFER)) |
| 4311 | dev_err(&pdev->dev, |
| 4312 | "Unable to get vdd_cx_ao regulator\n"); |
| 4313 | return PTR_ERR(vdd_cx_ao.regulator[0]); |
| 4314 | } |
| 4315 | |
Deepak Katragadda | 6c846e3 | 2017-06-07 14:09:49 -0700 | [diff] [blame] | 4316 | ret = gcc_sdm845_fixup(pdev); |
| 4317 | if (ret) |
| 4318 | return ret; |
| 4319 | |
Deepak Katragadda | d075ba3 | 2017-04-06 13:45:47 -0700 | [diff] [blame] | 4320 | /* Register the dummy measurement clocks */ |
| 4321 | for (i = 0; i < ARRAY_SIZE(gcc_sdm845_hws); i++) { |
| 4322 | clk = devm_clk_register(&pdev->dev, gcc_sdm845_hws[i]); |
| 4323 | if (IS_ERR(clk)) |
| 4324 | return PTR_ERR(clk); |
| 4325 | } |
| 4326 | |
Kyle Yan | 6a20fae | 2017-02-14 13:34:41 -0800 | [diff] [blame] | 4327 | ret = qcom_cc_really_probe(pdev, &gcc_sdm845_desc, regmap); |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 4328 | if (ret) { |
| 4329 | dev_err(&pdev->dev, "Failed to register GCC clocks\n"); |
| 4330 | return ret; |
| 4331 | } |
| 4332 | |
| 4333 | /* Disable the GPLL0 active input to MMSS and GPU via MISC registers */ |
| 4334 | regmap_update_bits(regmap, GCC_MMSS_MISC, 0x3, 0x3); |
| 4335 | regmap_update_bits(regmap, GCC_GPU_MISC, 0x3, 0x3); |
| 4336 | |
Deepak Katragadda | 5783d77 | 2017-08-04 13:33:36 -0700 | [diff] [blame] | 4337 | /* Keep this clock on all the time on SDM845 v1 */ |
| 4338 | if (of_device_is_compatible(pdev->dev.of_node, "qcom,gcc-sdm845")) |
| 4339 | clk_prepare_enable(gcc_aggre_noc_pcie_tbu_clk.clkr.hw.clk); |
| 4340 | |
Taniya Das | 5bac2ec | 2017-04-13 15:22:34 +0530 | [diff] [blame] | 4341 | /* DFS clock registration */ |
| 4342 | ret = qcom_cc_register_rcg_dfs(pdev, &gcc_sdm845_dfs_desc); |
| 4343 | if (ret) |
| 4344 | dev_err(&pdev->dev, "Failed to register with DFS!\n"); |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 4345 | |
| 4346 | dev_info(&pdev->dev, "Registered GCC clocks\n"); |
| 4347 | return ret; |
| 4348 | } |
| 4349 | |
Kyle Yan | 6a20fae | 2017-02-14 13:34:41 -0800 | [diff] [blame] | 4350 | static struct platform_driver gcc_sdm845_driver = { |
| 4351 | .probe = gcc_sdm845_probe, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 4352 | .driver = { |
Kyle Yan | 6a20fae | 2017-02-14 13:34:41 -0800 | [diff] [blame] | 4353 | .name = "gcc-sdm845", |
| 4354 | .of_match_table = gcc_sdm845_match_table, |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 4355 | }, |
| 4356 | }; |
| 4357 | |
Kyle Yan | 6a20fae | 2017-02-14 13:34:41 -0800 | [diff] [blame] | 4358 | static int __init gcc_sdm845_init(void) |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 4359 | { |
Kyle Yan | 6a20fae | 2017-02-14 13:34:41 -0800 | [diff] [blame] | 4360 | return platform_driver_register(&gcc_sdm845_driver); |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 4361 | } |
Deepak Katragadda | ef44e10 | 2017-06-21 10:30:46 -0700 | [diff] [blame] | 4362 | subsys_initcall(gcc_sdm845_init); |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 4363 | |
Kyle Yan | 6a20fae | 2017-02-14 13:34:41 -0800 | [diff] [blame] | 4364 | static void __exit gcc_sdm845_exit(void) |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 4365 | { |
Kyle Yan | 6a20fae | 2017-02-14 13:34:41 -0800 | [diff] [blame] | 4366 | platform_driver_unregister(&gcc_sdm845_driver); |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 4367 | } |
Kyle Yan | 6a20fae | 2017-02-14 13:34:41 -0800 | [diff] [blame] | 4368 | module_exit(gcc_sdm845_exit); |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 4369 | |
Kyle Yan | 6a20fae | 2017-02-14 13:34:41 -0800 | [diff] [blame] | 4370 | MODULE_DESCRIPTION("QTI GCC SDM845 Driver"); |
Deepak Katragadda | 575a45f | 2016-10-11 15:06:56 -0700 | [diff] [blame] | 4371 | MODULE_LICENSE("GPL v2"); |
Kyle Yan | 6a20fae | 2017-02-14 13:34:41 -0800 | [diff] [blame] | 4372 | MODULE_ALIAS("platform:gcc-sdm845"); |