Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1 | /* |
Sujith | cee075a | 2009-03-13 09:07:23 +0530 | [diff] [blame] | 2 | * Copyright (c) 2008-2009 Atheros Communications Inc. |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 3 | * |
| 4 | * Permission to use, copy, modify, and/or distribute this software for any |
| 5 | * purpose with or without fee is hereby granted, provided that the above |
| 6 | * copyright notice and this permission notice appear in all copies. |
| 7 | * |
| 8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
| 9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
| 10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
| 11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
| 12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
| 13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
| 14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
| 15 | */ |
| 16 | |
| 17 | #include <linux/io.h> |
| 18 | #include <asm/unaligned.h> |
| 19 | |
Luis R. Rodriguez | af03abe | 2009-09-09 02:33:11 -0700 | [diff] [blame] | 20 | #include "hw.h" |
Luis R. Rodriguez | d70357d | 2010-04-15 17:38:06 -0400 | [diff] [blame] | 21 | #include "hw-ops.h" |
Luis R. Rodriguez | cfe8cba | 2009-09-13 23:39:31 -0700 | [diff] [blame] | 22 | #include "rc.h" |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 23 | #include "initvals.h" |
| 24 | |
Luis R. Rodriguez | 4febf7b | 2008-12-23 15:58:48 -0800 | [diff] [blame] | 25 | #define ATH9K_CLOCK_RATE_CCK 22 |
| 26 | #define ATH9K_CLOCK_RATE_5GHZ_OFDM 40 |
| 27 | #define ATH9K_CLOCK_RATE_2GHZ_OFDM 44 |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 28 | |
Luis R. Rodriguez | d70357d | 2010-04-15 17:38:06 -0400 | [diff] [blame] | 29 | static void ar9002_hw_attach_ops(struct ath_hw *ah); |
Luis R. Rodriguez | 8525f28 | 2010-04-15 17:38:19 -0400 | [diff] [blame] | 30 | static void ar9003_hw_attach_ops(struct ath_hw *ah); |
Luis R. Rodriguez | d70357d | 2010-04-15 17:38:06 -0400 | [diff] [blame] | 31 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 32 | static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 33 | |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 34 | MODULE_AUTHOR("Atheros Communications"); |
| 35 | MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards."); |
| 36 | MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards"); |
| 37 | MODULE_LICENSE("Dual BSD/GPL"); |
| 38 | |
| 39 | static int __init ath9k_init(void) |
| 40 | { |
| 41 | return 0; |
| 42 | } |
| 43 | module_init(ath9k_init); |
| 44 | |
| 45 | static void __exit ath9k_exit(void) |
| 46 | { |
| 47 | return; |
| 48 | } |
| 49 | module_exit(ath9k_exit); |
| 50 | |
Luis R. Rodriguez | d70357d | 2010-04-15 17:38:06 -0400 | [diff] [blame] | 51 | /* Private hardware callbacks */ |
| 52 | |
| 53 | static void ath9k_hw_init_cal_settings(struct ath_hw *ah) |
| 54 | { |
| 55 | ath9k_hw_private_ops(ah)->init_cal_settings(ah); |
| 56 | } |
| 57 | |
| 58 | static void ath9k_hw_init_mode_regs(struct ath_hw *ah) |
| 59 | { |
| 60 | ath9k_hw_private_ops(ah)->init_mode_regs(ah); |
| 61 | } |
| 62 | |
| 63 | static bool ath9k_hw_macversion_supported(struct ath_hw *ah) |
| 64 | { |
| 65 | struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah); |
| 66 | |
| 67 | return priv_ops->macversion_supported(ah->hw_version.macVersion); |
| 68 | } |
| 69 | |
Luis R. Rodriguez | 6477396 | 2010-04-15 17:38:17 -0400 | [diff] [blame] | 70 | static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah, |
| 71 | struct ath9k_channel *chan) |
| 72 | { |
| 73 | return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan); |
| 74 | } |
| 75 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 76 | /********************/ |
| 77 | /* Helper Functions */ |
| 78 | /********************/ |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 79 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 80 | static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 81 | { |
Luis R. Rodriguez | b002a4a | 2009-09-13 00:03:27 -0700 | [diff] [blame] | 82 | struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf; |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 83 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 84 | if (!ah->curchan) /* should really check for CCK instead */ |
Luis R. Rodriguez | 4febf7b | 2008-12-23 15:58:48 -0800 | [diff] [blame] | 85 | return usecs *ATH9K_CLOCK_RATE_CCK; |
| 86 | if (conf->channel->band == IEEE80211_BAND_2GHZ) |
| 87 | return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM; |
| 88 | return usecs *ATH9K_CLOCK_RATE_5GHZ_OFDM; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 89 | } |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 90 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 91 | static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 92 | { |
Luis R. Rodriguez | b002a4a | 2009-09-13 00:03:27 -0700 | [diff] [blame] | 93 | struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf; |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 94 | |
Luis R. Rodriguez | 4febf7b | 2008-12-23 15:58:48 -0800 | [diff] [blame] | 95 | if (conf_is_ht40(conf)) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 96 | return ath9k_hw_mac_clks(ah, usecs) * 2; |
| 97 | else |
| 98 | return ath9k_hw_mac_clks(ah, usecs); |
| 99 | } |
| 100 | |
Sujith | 0caa7b1 | 2009-02-16 13:23:20 +0530 | [diff] [blame] | 101 | bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 102 | { |
| 103 | int i; |
| 104 | |
Sujith | 0caa7b1 | 2009-02-16 13:23:20 +0530 | [diff] [blame] | 105 | BUG_ON(timeout < AH_TIME_QUANTUM); |
| 106 | |
| 107 | for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) { |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 108 | if ((REG_READ(ah, reg) & mask) == val) |
| 109 | return true; |
| 110 | |
| 111 | udelay(AH_TIME_QUANTUM); |
| 112 | } |
Sujith | 04bd463 | 2008-11-28 22:18:05 +0530 | [diff] [blame] | 113 | |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 114 | ath_print(ath9k_hw_common(ah), ATH_DBG_ANY, |
| 115 | "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n", |
| 116 | timeout, reg, REG_READ(ah, reg), mask, val); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 117 | |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 118 | return false; |
| 119 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 120 | EXPORT_SYMBOL(ath9k_hw_wait); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 121 | |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 122 | u32 ath9k_hw_reverse_bits(u32 val, u32 n) |
| 123 | { |
| 124 | u32 retval; |
| 125 | int i; |
| 126 | |
| 127 | for (i = 0, retval = 0; i < n; i++) { |
| 128 | retval = (retval << 1) | (val & 1); |
| 129 | val >>= 1; |
| 130 | } |
| 131 | return retval; |
| 132 | } |
| 133 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 134 | bool ath9k_get_channel_edges(struct ath_hw *ah, |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 135 | u16 flags, u16 *low, |
| 136 | u16 *high) |
| 137 | { |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 138 | struct ath9k_hw_capabilities *pCap = &ah->caps; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 139 | |
| 140 | if (flags & CHANNEL_5GHZ) { |
| 141 | *low = pCap->low_5ghz_chan; |
| 142 | *high = pCap->high_5ghz_chan; |
| 143 | return true; |
| 144 | } |
| 145 | if ((flags & CHANNEL_2GHZ)) { |
| 146 | *low = pCap->low_2ghz_chan; |
| 147 | *high = pCap->high_2ghz_chan; |
| 148 | return true; |
| 149 | } |
| 150 | return false; |
| 151 | } |
| 152 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 153 | u16 ath9k_hw_computetxtime(struct ath_hw *ah, |
Felix Fietkau | 545750d | 2009-11-23 22:21:01 +0100 | [diff] [blame] | 154 | u8 phy, int kbps, |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 155 | u32 frameLen, u16 rateix, |
| 156 | bool shortPreamble) |
| 157 | { |
| 158 | u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 159 | |
| 160 | if (kbps == 0) |
| 161 | return 0; |
| 162 | |
Felix Fietkau | 545750d | 2009-11-23 22:21:01 +0100 | [diff] [blame] | 163 | switch (phy) { |
Sujith | 46d14a5 | 2008-11-18 09:08:13 +0530 | [diff] [blame] | 164 | case WLAN_RC_PHY_CCK: |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 165 | phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS; |
Felix Fietkau | 545750d | 2009-11-23 22:21:01 +0100 | [diff] [blame] | 166 | if (shortPreamble) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 167 | phyTime >>= 1; |
| 168 | numBits = frameLen << 3; |
| 169 | txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps); |
| 170 | break; |
Sujith | 46d14a5 | 2008-11-18 09:08:13 +0530 | [diff] [blame] | 171 | case WLAN_RC_PHY_OFDM: |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 172 | if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) { |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 173 | bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000; |
| 174 | numBits = OFDM_PLCP_BITS + (frameLen << 3); |
| 175 | numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); |
| 176 | txTime = OFDM_SIFS_TIME_QUARTER |
| 177 | + OFDM_PREAMBLE_TIME_QUARTER |
| 178 | + (numSymbols * OFDM_SYMBOL_TIME_QUARTER); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 179 | } else if (ah->curchan && |
| 180 | IS_CHAN_HALF_RATE(ah->curchan)) { |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 181 | bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000; |
| 182 | numBits = OFDM_PLCP_BITS + (frameLen << 3); |
| 183 | numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); |
| 184 | txTime = OFDM_SIFS_TIME_HALF + |
| 185 | OFDM_PREAMBLE_TIME_HALF |
| 186 | + (numSymbols * OFDM_SYMBOL_TIME_HALF); |
| 187 | } else { |
| 188 | bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000; |
| 189 | numBits = OFDM_PLCP_BITS + (frameLen << 3); |
| 190 | numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); |
| 191 | txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME |
| 192 | + (numSymbols * OFDM_SYMBOL_TIME); |
| 193 | } |
| 194 | break; |
| 195 | default: |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 196 | ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL, |
Felix Fietkau | 545750d | 2009-11-23 22:21:01 +0100 | [diff] [blame] | 197 | "Unknown phy %u (rate ix %u)\n", phy, rateix); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 198 | txTime = 0; |
| 199 | break; |
| 200 | } |
| 201 | |
| 202 | return txTime; |
| 203 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 204 | EXPORT_SYMBOL(ath9k_hw_computetxtime); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 205 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 206 | void ath9k_hw_get_channel_centers(struct ath_hw *ah, |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 207 | struct ath9k_channel *chan, |
| 208 | struct chan_centers *centers) |
| 209 | { |
| 210 | int8_t extoff; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 211 | |
| 212 | if (!IS_CHAN_HT40(chan)) { |
| 213 | centers->ctl_center = centers->ext_center = |
| 214 | centers->synth_center = chan->channel; |
| 215 | return; |
| 216 | } |
| 217 | |
| 218 | if ((chan->chanmode == CHANNEL_A_HT40PLUS) || |
| 219 | (chan->chanmode == CHANNEL_G_HT40PLUS)) { |
| 220 | centers->synth_center = |
| 221 | chan->channel + HT40_CHANNEL_CENTER_SHIFT; |
| 222 | extoff = 1; |
| 223 | } else { |
| 224 | centers->synth_center = |
| 225 | chan->channel - HT40_CHANNEL_CENTER_SHIFT; |
| 226 | extoff = -1; |
| 227 | } |
| 228 | |
| 229 | centers->ctl_center = |
| 230 | centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT); |
Luis R. Rodriguez | 6420014 | 2009-09-13 22:05:04 -0700 | [diff] [blame] | 231 | /* 25 MHz spacing is supported by hw but not on upper layers */ |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 232 | centers->ext_center = |
Luis R. Rodriguez | 6420014 | 2009-09-13 22:05:04 -0700 | [diff] [blame] | 233 | centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 234 | } |
| 235 | |
| 236 | /******************/ |
| 237 | /* Chip Revisions */ |
| 238 | /******************/ |
| 239 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 240 | static void ath9k_hw_read_revisions(struct ath_hw *ah) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 241 | { |
| 242 | u32 val; |
| 243 | |
| 244 | val = REG_READ(ah, AR_SREV) & AR_SREV_ID; |
| 245 | |
| 246 | if (val == 0xFF) { |
| 247 | val = REG_READ(ah, AR_SREV); |
Sujith | d535a42 | 2009-02-09 13:27:06 +0530 | [diff] [blame] | 248 | ah->hw_version.macVersion = |
| 249 | (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S; |
| 250 | ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 251 | ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 252 | } else { |
| 253 | if (!AR_SREV_9100(ah)) |
Sujith | d535a42 | 2009-02-09 13:27:06 +0530 | [diff] [blame] | 254 | ah->hw_version.macVersion = MS(val, AR_SREV_VERSION); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 255 | |
Sujith | d535a42 | 2009-02-09 13:27:06 +0530 | [diff] [blame] | 256 | ah->hw_version.macRev = val & AR_SREV_REVISION; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 257 | |
Sujith | d535a42 | 2009-02-09 13:27:06 +0530 | [diff] [blame] | 258 | if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE) |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 259 | ah->is_pciexpress = true; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 260 | } |
| 261 | } |
| 262 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 263 | static int ath9k_hw_get_radiorev(struct ath_hw *ah) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 264 | { |
| 265 | u32 val; |
| 266 | int i; |
| 267 | |
| 268 | REG_WRITE(ah, AR_PHY(0x36), 0x00007058); |
| 269 | |
| 270 | for (i = 0; i < 8; i++) |
| 271 | REG_WRITE(ah, AR_PHY(0x20), 0x00010000); |
| 272 | val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff; |
| 273 | val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4); |
| 274 | |
| 275 | return ath9k_hw_reverse_bits(val, 8); |
| 276 | } |
| 277 | |
| 278 | /************************************/ |
| 279 | /* HW Attach, Detach, Init Routines */ |
| 280 | /************************************/ |
| 281 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 282 | static void ath9k_hw_disablepcie(struct ath_hw *ah) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 283 | { |
Sujith | feed029 | 2009-01-29 11:37:35 +0530 | [diff] [blame] | 284 | if (AR_SREV_9100(ah)) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 285 | return; |
| 286 | |
| 287 | REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); |
| 288 | REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); |
| 289 | REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029); |
| 290 | REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824); |
| 291 | REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579); |
| 292 | REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000); |
| 293 | REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); |
| 294 | REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); |
| 295 | REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007); |
| 296 | |
| 297 | REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); |
| 298 | } |
| 299 | |
Senthil Balasubramanian | 1f3f061 | 2010-04-15 17:38:29 -0400 | [diff] [blame] | 300 | /* This should work for all families including legacy */ |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 301 | static bool ath9k_hw_chip_test(struct ath_hw *ah) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 302 | { |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 303 | struct ath_common *common = ath9k_hw_common(ah); |
Senthil Balasubramanian | 1f3f061 | 2010-04-15 17:38:29 -0400 | [diff] [blame] | 304 | u32 regAddr[2] = { AR_STA_ID0 }; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 305 | u32 regHold[2]; |
| 306 | u32 patternData[4] = { 0x55555555, |
| 307 | 0xaaaaaaaa, |
| 308 | 0x66666666, |
| 309 | 0x99999999 }; |
Senthil Balasubramanian | 1f3f061 | 2010-04-15 17:38:29 -0400 | [diff] [blame] | 310 | int i, j, loop_max; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 311 | |
Senthil Balasubramanian | 1f3f061 | 2010-04-15 17:38:29 -0400 | [diff] [blame] | 312 | if (!AR_SREV_9300_20_OR_LATER(ah)) { |
| 313 | loop_max = 2; |
| 314 | regAddr[1] = AR_PHY_BASE + (8 << 2); |
| 315 | } else |
| 316 | loop_max = 1; |
| 317 | |
| 318 | for (i = 0; i < loop_max; i++) { |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 319 | u32 addr = regAddr[i]; |
| 320 | u32 wrData, rdData; |
| 321 | |
| 322 | regHold[i] = REG_READ(ah, addr); |
| 323 | for (j = 0; j < 0x100; j++) { |
| 324 | wrData = (j << 16) | j; |
| 325 | REG_WRITE(ah, addr, wrData); |
| 326 | rdData = REG_READ(ah, addr); |
| 327 | if (rdData != wrData) { |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 328 | ath_print(common, ATH_DBG_FATAL, |
| 329 | "address test failed " |
| 330 | "addr: 0x%08x - wr:0x%08x != " |
| 331 | "rd:0x%08x\n", |
| 332 | addr, wrData, rdData); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 333 | return false; |
| 334 | } |
| 335 | } |
| 336 | for (j = 0; j < 4; j++) { |
| 337 | wrData = patternData[j]; |
| 338 | REG_WRITE(ah, addr, wrData); |
| 339 | rdData = REG_READ(ah, addr); |
| 340 | if (wrData != rdData) { |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 341 | ath_print(common, ATH_DBG_FATAL, |
| 342 | "address test failed " |
| 343 | "addr: 0x%08x - wr:0x%08x != " |
| 344 | "rd:0x%08x\n", |
| 345 | addr, wrData, rdData); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 346 | return false; |
| 347 | } |
| 348 | } |
| 349 | REG_WRITE(ah, regAddr[i], regHold[i]); |
| 350 | } |
| 351 | udelay(100); |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 352 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 353 | return true; |
| 354 | } |
| 355 | |
Luis R. Rodriguez | b8b0f37 | 2009-08-03 12:24:43 -0700 | [diff] [blame] | 356 | static void ath9k_hw_init_config(struct ath_hw *ah) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 357 | { |
| 358 | int i; |
| 359 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 360 | ah->config.dma_beacon_response_time = 2; |
| 361 | ah->config.sw_beacon_response_time = 10; |
| 362 | ah->config.additional_swba_backoff = 0; |
| 363 | ah->config.ack_6mb = 0x0; |
| 364 | ah->config.cwm_ignore_extcca = 0; |
| 365 | ah->config.pcie_powersave_enable = 0; |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 366 | ah->config.pcie_clock_req = 0; |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 367 | ah->config.pcie_waen = 0; |
| 368 | ah->config.analog_shiftreg = 1; |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 369 | ah->config.ofdm_trig_low = 200; |
| 370 | ah->config.ofdm_trig_high = 500; |
| 371 | ah->config.cck_trig_high = 200; |
| 372 | ah->config.cck_trig_low = 100; |
Luis R. Rodriguez | 31a0bd3 | 2010-04-15 17:38:22 -0400 | [diff] [blame] | 373 | |
| 374 | /* |
| 375 | * For now ANI is disabled for AR9003, it is still |
| 376 | * being tested. |
| 377 | */ |
| 378 | if (!AR_SREV_9300_20_OR_LATER(ah)) |
| 379 | ah->config.enable_ani = 1; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 380 | |
| 381 | for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) { |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 382 | ah->config.spurchans[i][0] = AR_NO_SPUR; |
| 383 | ah->config.spurchans[i][1] = AR_NO_SPUR; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 384 | } |
| 385 | |
Luis R. Rodriguez | 5ffaf8a | 2010-02-02 11:58:33 -0500 | [diff] [blame] | 386 | if (ah->hw_version.devid != AR2427_DEVID_PCIE) |
| 387 | ah->config.ht_enable = 1; |
| 388 | else |
| 389 | ah->config.ht_enable = 0; |
| 390 | |
Sujith | 0ce024c | 2009-12-14 14:57:00 +0530 | [diff] [blame] | 391 | ah->config.rx_intr_mitigation = true; |
Luis R. Rodriguez | 6158425 | 2009-03-12 18:18:49 -0400 | [diff] [blame] | 392 | |
| 393 | /* |
| 394 | * We need this for PCI devices only (Cardbus, PCI, miniPCI) |
| 395 | * _and_ if on non-uniprocessor systems (Multiprocessor/HT). |
| 396 | * This means we use it for all AR5416 devices, and the few |
| 397 | * minor PCI AR9280 devices out there. |
| 398 | * |
| 399 | * Serialization is required because these devices do not handle |
| 400 | * well the case of two concurrent reads/writes due to the latency |
| 401 | * involved. During one read/write another read/write can be issued |
| 402 | * on another CPU while the previous read/write may still be working |
| 403 | * on our hardware, if we hit this case the hardware poops in a loop. |
| 404 | * We prevent this by serializing reads and writes. |
| 405 | * |
| 406 | * This issue is not present on PCI-Express devices or pre-AR5416 |
| 407 | * devices (legacy, 802.11abg). |
| 408 | */ |
| 409 | if (num_possible_cpus() > 1) |
David S. Miller | 2d6a5e9 | 2009-03-17 15:01:30 -0700 | [diff] [blame] | 410 | ah->config.serialize_regmode = SER_REG_MODE_AUTO; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 411 | } |
| 412 | |
Luis R. Rodriguez | 50aca25 | 2009-08-03 12:24:42 -0700 | [diff] [blame] | 413 | static void ath9k_hw_init_defaults(struct ath_hw *ah) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 414 | { |
Luis R. Rodriguez | 608b88c | 2009-08-17 18:07:23 -0700 | [diff] [blame] | 415 | struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); |
| 416 | |
| 417 | regulatory->country_code = CTRY_DEFAULT; |
| 418 | regulatory->power_limit = MAX_RATE_POWER; |
| 419 | regulatory->tp_scale = ATH9K_TP_SCALE_MAX; |
| 420 | |
Sujith | d535a42 | 2009-02-09 13:27:06 +0530 | [diff] [blame] | 421 | ah->hw_version.magic = AR5416_MAGIC; |
Sujith | d535a42 | 2009-02-09 13:27:06 +0530 | [diff] [blame] | 422 | ah->hw_version.subvendorid = 0; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 423 | |
| 424 | ah->ah_flags = 0; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 425 | if (!AR_SREV_9100(ah)) |
| 426 | ah->ah_flags = AH_USE_EEPROM; |
| 427 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 428 | ah->atim_window = 0; |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 429 | ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE; |
| 430 | ah->beacon_interval = 100; |
| 431 | ah->enable_32kHz_clock = DONT_USE_32KHZ; |
| 432 | ah->slottime = (u32) -1; |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 433 | ah->globaltxtimeout = (u32) -1; |
Gabor Juhos | cbdec97 | 2009-07-24 17:27:22 +0200 | [diff] [blame] | 434 | ah->power_mode = ATH9K_PM_UNDEFINED; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 435 | } |
| 436 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 437 | static int ath9k_hw_rf_claim(struct ath_hw *ah) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 438 | { |
| 439 | u32 val; |
| 440 | |
| 441 | REG_WRITE(ah, AR_PHY(0), 0x00000007); |
| 442 | |
| 443 | val = ath9k_hw_get_radiorev(ah); |
| 444 | switch (val & AR_RADIO_SREV_MAJOR) { |
| 445 | case 0: |
| 446 | val = AR_RAD5133_SREV_MAJOR; |
| 447 | break; |
| 448 | case AR_RAD5133_SREV_MAJOR: |
| 449 | case AR_RAD5122_SREV_MAJOR: |
| 450 | case AR_RAD2133_SREV_MAJOR: |
| 451 | case AR_RAD2122_SREV_MAJOR: |
| 452 | break; |
| 453 | default: |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 454 | ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL, |
| 455 | "Radio Chip Rev 0x%02X not supported\n", |
| 456 | val & AR_RADIO_SREV_MAJOR); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 457 | return -EOPNOTSUPP; |
| 458 | } |
| 459 | |
Sujith | d535a42 | 2009-02-09 13:27:06 +0530 | [diff] [blame] | 460 | ah->hw_version.analog5GhzRev = val; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 461 | |
| 462 | return 0; |
| 463 | } |
| 464 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 465 | static int ath9k_hw_init_macaddr(struct ath_hw *ah) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 466 | { |
Luis R. Rodriguez | 1510718 | 2009-09-10 09:22:37 -0700 | [diff] [blame] | 467 | struct ath_common *common = ath9k_hw_common(ah); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 468 | u32 sum; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 469 | int i; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 470 | u16 eeval; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 471 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 472 | sum = 0; |
| 473 | for (i = 0; i < 3; i++) { |
Sujith | f74df6f | 2009-02-09 13:27:24 +0530 | [diff] [blame] | 474 | eeval = ah->eep_ops->get_eeprom(ah, AR_EEPROM_MAC(i)); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 475 | sum += eeval; |
Luis R. Rodriguez | 1510718 | 2009-09-10 09:22:37 -0700 | [diff] [blame] | 476 | common->macaddr[2 * i] = eeval >> 8; |
| 477 | common->macaddr[2 * i + 1] = eeval & 0xff; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 478 | } |
Sujith | d8baa93 | 2009-03-30 15:28:25 +0530 | [diff] [blame] | 479 | if (sum == 0 || sum == 0xffff * 3) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 480 | return -EADDRNOTAVAIL; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 481 | |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 482 | return 0; |
| 483 | } |
| 484 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 485 | static void ath9k_hw_init_rxgain_ini(struct ath_hw *ah) |
Senthil Balasubramanian | 9f80420 | 2008-11-13 17:58:41 +0530 | [diff] [blame] | 486 | { |
| 487 | u32 rxgain_type; |
Senthil Balasubramanian | 9f80420 | 2008-11-13 17:58:41 +0530 | [diff] [blame] | 488 | |
Sujith | f74df6f | 2009-02-09 13:27:24 +0530 | [diff] [blame] | 489 | if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) { |
| 490 | rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE); |
Senthil Balasubramanian | 9f80420 | 2008-11-13 17:58:41 +0530 | [diff] [blame] | 491 | |
| 492 | if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF) |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 493 | INIT_INI_ARRAY(&ah->iniModesRxGain, |
Senthil Balasubramanian | 9f80420 | 2008-11-13 17:58:41 +0530 | [diff] [blame] | 494 | ar9280Modes_backoff_13db_rxgain_9280_2, |
| 495 | ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6); |
| 496 | else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF) |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 497 | INIT_INI_ARRAY(&ah->iniModesRxGain, |
Senthil Balasubramanian | 9f80420 | 2008-11-13 17:58:41 +0530 | [diff] [blame] | 498 | ar9280Modes_backoff_23db_rxgain_9280_2, |
| 499 | ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6); |
| 500 | else |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 501 | INIT_INI_ARRAY(&ah->iniModesRxGain, |
Senthil Balasubramanian | 9f80420 | 2008-11-13 17:58:41 +0530 | [diff] [blame] | 502 | ar9280Modes_original_rxgain_9280_2, |
| 503 | ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6); |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 504 | } else { |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 505 | INIT_INI_ARRAY(&ah->iniModesRxGain, |
Senthil Balasubramanian | 9f80420 | 2008-11-13 17:58:41 +0530 | [diff] [blame] | 506 | ar9280Modes_original_rxgain_9280_2, |
| 507 | ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6); |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 508 | } |
Senthil Balasubramanian | 9f80420 | 2008-11-13 17:58:41 +0530 | [diff] [blame] | 509 | } |
| 510 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 511 | static void ath9k_hw_init_txgain_ini(struct ath_hw *ah) |
Senthil Balasubramanian | 9f80420 | 2008-11-13 17:58:41 +0530 | [diff] [blame] | 512 | { |
| 513 | u32 txgain_type; |
Senthil Balasubramanian | 9f80420 | 2008-11-13 17:58:41 +0530 | [diff] [blame] | 514 | |
Sujith | f74df6f | 2009-02-09 13:27:24 +0530 | [diff] [blame] | 515 | if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) { |
| 516 | txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE); |
Senthil Balasubramanian | 9f80420 | 2008-11-13 17:58:41 +0530 | [diff] [blame] | 517 | |
| 518 | if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 519 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
Senthil Balasubramanian | 9f80420 | 2008-11-13 17:58:41 +0530 | [diff] [blame] | 520 | ar9280Modes_high_power_tx_gain_9280_2, |
| 521 | ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6); |
| 522 | else |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 523 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
Senthil Balasubramanian | 9f80420 | 2008-11-13 17:58:41 +0530 | [diff] [blame] | 524 | ar9280Modes_original_tx_gain_9280_2, |
| 525 | ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6); |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 526 | } else { |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 527 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
Senthil Balasubramanian | 9f80420 | 2008-11-13 17:58:41 +0530 | [diff] [blame] | 528 | ar9280Modes_original_tx_gain_9280_2, |
| 529 | ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6); |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 530 | } |
Senthil Balasubramanian | 9f80420 | 2008-11-13 17:58:41 +0530 | [diff] [blame] | 531 | } |
| 532 | |
Luis R. Rodriguez | f637cfd | 2009-08-03 12:24:46 -0700 | [diff] [blame] | 533 | static int ath9k_hw_post_init(struct ath_hw *ah) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 534 | { |
| 535 | int ecode; |
| 536 | |
Sujith | 527d485 | 2010-03-17 14:25:16 +0530 | [diff] [blame] | 537 | if (!AR_SREV_9271(ah)) { |
| 538 | if (!ath9k_hw_chip_test(ah)) |
| 539 | return -ENODEV; |
| 540 | } |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 541 | |
| 542 | ecode = ath9k_hw_rf_claim(ah); |
| 543 | if (ecode != 0) |
| 544 | return ecode; |
| 545 | |
Luis R. Rodriguez | f637cfd | 2009-08-03 12:24:46 -0700 | [diff] [blame] | 546 | ecode = ath9k_hw_eeprom_init(ah); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 547 | if (ecode != 0) |
| 548 | return ecode; |
Sujith | 7d01b22 | 2009-03-13 08:55:55 +0530 | [diff] [blame] | 549 | |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 550 | ath_print(ath9k_hw_common(ah), ATH_DBG_CONFIG, |
| 551 | "Eeprom VER: %d, REV: %d\n", |
| 552 | ah->eep_ops->get_eeprom_ver(ah), |
| 553 | ah->eep_ops->get_eeprom_rev(ah)); |
Sujith | 7d01b22 | 2009-03-13 08:55:55 +0530 | [diff] [blame] | 554 | |
Luis R. Rodriguez | 8fe6536 | 2010-04-15 17:38:14 -0400 | [diff] [blame] | 555 | ecode = ath9k_hw_rf_alloc_ext_banks(ah); |
| 556 | if (ecode) { |
| 557 | ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL, |
| 558 | "Failed allocating banks for " |
| 559 | "external radio\n"); |
| 560 | return ecode; |
Luis R. Rodriguez | 574d6b1 | 2009-10-19 02:33:37 -0400 | [diff] [blame] | 561 | } |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 562 | |
| 563 | if (!AR_SREV_9100(ah)) { |
| 564 | ath9k_hw_ani_setup(ah); |
Luis R. Rodriguez | f637cfd | 2009-08-03 12:24:46 -0700 | [diff] [blame] | 565 | ath9k_hw_ani_init(ah); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 566 | } |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 567 | |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 568 | return 0; |
| 569 | } |
| 570 | |
Luis R. Rodriguez | d70357d | 2010-04-15 17:38:06 -0400 | [diff] [blame] | 571 | static bool ar9002_hw_macversion_supported(u32 macversion) |
Luis R. Rodriguez | f9d4a66 | 2009-08-03 12:24:41 -0700 | [diff] [blame] | 572 | { |
| 573 | switch (macversion) { |
| 574 | case AR_SREV_VERSION_5416_PCI: |
| 575 | case AR_SREV_VERSION_5416_PCIE: |
| 576 | case AR_SREV_VERSION_9160: |
| 577 | case AR_SREV_VERSION_9100: |
| 578 | case AR_SREV_VERSION_9280: |
| 579 | case AR_SREV_VERSION_9285: |
| 580 | case AR_SREV_VERSION_9287: |
Luis R. Rodriguez | d7e7d22 | 2009-08-03 23:14:12 -0400 | [diff] [blame] | 581 | case AR_SREV_VERSION_9271: |
Luis R. Rodriguez | 7976b42 | 2009-09-23 23:07:02 -0400 | [diff] [blame] | 582 | return true; |
Luis R. Rodriguez | f9d4a66 | 2009-08-03 12:24:41 -0700 | [diff] [blame] | 583 | default: |
| 584 | break; |
| 585 | } |
| 586 | return false; |
| 587 | } |
| 588 | |
Luis R. Rodriguez | 61accab | 2010-04-15 17:38:21 -0400 | [diff] [blame] | 589 | static bool ar9003_hw_macversion_supported(u32 macversion) |
| 590 | { |
| 591 | switch (macversion) { |
| 592 | case AR_SREV_VERSION_9300: |
| 593 | return true; |
| 594 | default: |
| 595 | break; |
| 596 | } |
| 597 | return false; |
| 598 | } |
| 599 | |
Luis R. Rodriguez | d70357d | 2010-04-15 17:38:06 -0400 | [diff] [blame] | 600 | static void ar9002_hw_init_cal_settings(struct ath_hw *ah) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 601 | { |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 602 | if (AR_SREV_9160_10_OR_LATER(ah)) { |
| 603 | if (AR_SREV_9280_10_OR_LATER(ah)) { |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 604 | ah->iq_caldata.calData = &iq_cal_single_sample; |
| 605 | ah->adcgain_caldata.calData = |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 606 | &adc_gain_cal_single_sample; |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 607 | ah->adcdc_caldata.calData = |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 608 | &adc_dc_cal_single_sample; |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 609 | ah->adcdc_calinitdata.calData = |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 610 | &adc_init_dc_cal; |
| 611 | } else { |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 612 | ah->iq_caldata.calData = &iq_cal_multi_sample; |
| 613 | ah->adcgain_caldata.calData = |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 614 | &adc_gain_cal_multi_sample; |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 615 | ah->adcdc_caldata.calData = |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 616 | &adc_dc_cal_multi_sample; |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 617 | ah->adcdc_calinitdata.calData = |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 618 | &adc_init_dc_cal; |
| 619 | } |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 620 | ah->supp_cals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 621 | } |
Luis R. Rodriguez | aa4058a | 2009-08-03 12:24:45 -0700 | [diff] [blame] | 622 | } |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 623 | |
Luis R. Rodriguez | d70357d | 2010-04-15 17:38:06 -0400 | [diff] [blame] | 624 | static void ar9002_hw_init_mode_regs(struct ath_hw *ah) |
Luis R. Rodriguez | aa4058a | 2009-08-03 12:24:45 -0700 | [diff] [blame] | 625 | { |
Luis R. Rodriguez | d7e7d22 | 2009-08-03 23:14:12 -0400 | [diff] [blame] | 626 | if (AR_SREV_9271(ah)) { |
Luis R. Rodriguez | 8564328 | 2009-10-19 02:33:33 -0400 | [diff] [blame] | 627 | INIT_INI_ARRAY(&ah->iniModes, ar9271Modes_9271, |
| 628 | ARRAY_SIZE(ar9271Modes_9271), 6); |
| 629 | INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271, |
| 630 | ARRAY_SIZE(ar9271Common_9271), 2); |
Sujith | 70807e9 | 2010-03-17 14:25:14 +0530 | [diff] [blame] | 631 | INIT_INI_ARRAY(&ah->iniCommon_normal_cck_fir_coeff_9271, |
| 632 | ar9271Common_normal_cck_fir_coeff_9271, |
| 633 | ARRAY_SIZE(ar9271Common_normal_cck_fir_coeff_9271), 2); |
| 634 | INIT_INI_ARRAY(&ah->iniCommon_japan_2484_cck_fir_coeff_9271, |
| 635 | ar9271Common_japan_2484_cck_fir_coeff_9271, |
| 636 | ARRAY_SIZE(ar9271Common_japan_2484_cck_fir_coeff_9271), 2); |
Luis R. Rodriguez | 8564328 | 2009-10-19 02:33:33 -0400 | [diff] [blame] | 637 | INIT_INI_ARRAY(&ah->iniModes_9271_1_0_only, |
| 638 | ar9271Modes_9271_1_0_only, |
| 639 | ARRAY_SIZE(ar9271Modes_9271_1_0_only), 6); |
Sujith | 70807e9 | 2010-03-17 14:25:14 +0530 | [diff] [blame] | 640 | INIT_INI_ARRAY(&ah->iniModes_9271_ANI_reg, ar9271Modes_9271_ANI_reg, |
| 641 | ARRAY_SIZE(ar9271Modes_9271_ANI_reg), 6); |
| 642 | INIT_INI_ARRAY(&ah->iniModes_high_power_tx_gain_9271, |
| 643 | ar9271Modes_high_power_tx_gain_9271, |
| 644 | ARRAY_SIZE(ar9271Modes_high_power_tx_gain_9271), 6); |
| 645 | INIT_INI_ARRAY(&ah->iniModes_normal_power_tx_gain_9271, |
| 646 | ar9271Modes_normal_power_tx_gain_9271, |
| 647 | ARRAY_SIZE(ar9271Modes_normal_power_tx_gain_9271), 6); |
Luis R. Rodriguez | d7e7d22 | 2009-08-03 23:14:12 -0400 | [diff] [blame] | 648 | return; |
| 649 | } |
| 650 | |
Vivek Natarajan | ac88b6e | 2009-07-23 10:59:57 +0530 | [diff] [blame] | 651 | if (AR_SREV_9287_11_OR_LATER(ah)) { |
| 652 | INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1, |
| 653 | ARRAY_SIZE(ar9287Modes_9287_1_1), 6); |
| 654 | INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_1, |
| 655 | ARRAY_SIZE(ar9287Common_9287_1_1), 2); |
| 656 | if (ah->config.pcie_clock_req) |
| 657 | INIT_INI_ARRAY(&ah->iniPcieSerdes, |
| 658 | ar9287PciePhy_clkreq_off_L1_9287_1_1, |
| 659 | ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_1), 2); |
| 660 | else |
| 661 | INIT_INI_ARRAY(&ah->iniPcieSerdes, |
| 662 | ar9287PciePhy_clkreq_always_on_L1_9287_1_1, |
| 663 | ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_1), |
| 664 | 2); |
| 665 | } else if (AR_SREV_9287_10_OR_LATER(ah)) { |
| 666 | INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_0, |
| 667 | ARRAY_SIZE(ar9287Modes_9287_1_0), 6); |
| 668 | INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_0, |
| 669 | ARRAY_SIZE(ar9287Common_9287_1_0), 2); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 670 | |
Vivek Natarajan | ac88b6e | 2009-07-23 10:59:57 +0530 | [diff] [blame] | 671 | if (ah->config.pcie_clock_req) |
| 672 | INIT_INI_ARRAY(&ah->iniPcieSerdes, |
| 673 | ar9287PciePhy_clkreq_off_L1_9287_1_0, |
| 674 | ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_0), 2); |
| 675 | else |
| 676 | INIT_INI_ARRAY(&ah->iniPcieSerdes, |
| 677 | ar9287PciePhy_clkreq_always_on_L1_9287_1_0, |
| 678 | ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_0), |
| 679 | 2); |
| 680 | } else if (AR_SREV_9285_12_OR_LATER(ah)) { |
| 681 | |
Senthil Balasubramanian | 4e84516 | 2009-03-06 11:24:10 +0530 | [diff] [blame] | 682 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 683 | INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2, |
Senthil Balasubramanian | e759407 | 2008-12-08 19:43:48 +0530 | [diff] [blame] | 684 | ARRAY_SIZE(ar9285Modes_9285_1_2), 6); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 685 | INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2, |
Senthil Balasubramanian | e759407 | 2008-12-08 19:43:48 +0530 | [diff] [blame] | 686 | ARRAY_SIZE(ar9285Common_9285_1_2), 2); |
| 687 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 688 | if (ah->config.pcie_clock_req) { |
| 689 | INIT_INI_ARRAY(&ah->iniPcieSerdes, |
Senthil Balasubramanian | e759407 | 2008-12-08 19:43:48 +0530 | [diff] [blame] | 690 | ar9285PciePhy_clkreq_off_L1_9285_1_2, |
| 691 | ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2); |
| 692 | } else { |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 693 | INIT_INI_ARRAY(&ah->iniPcieSerdes, |
Senthil Balasubramanian | e759407 | 2008-12-08 19:43:48 +0530 | [diff] [blame] | 694 | ar9285PciePhy_clkreq_always_on_L1_9285_1_2, |
| 695 | ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2), |
| 696 | 2); |
| 697 | } |
| 698 | } else if (AR_SREV_9285_10_OR_LATER(ah)) { |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 699 | INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285, |
Senthil Balasubramanian | e759407 | 2008-12-08 19:43:48 +0530 | [diff] [blame] | 700 | ARRAY_SIZE(ar9285Modes_9285), 6); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 701 | INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285, |
Senthil Balasubramanian | e759407 | 2008-12-08 19:43:48 +0530 | [diff] [blame] | 702 | ARRAY_SIZE(ar9285Common_9285), 2); |
| 703 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 704 | if (ah->config.pcie_clock_req) { |
| 705 | INIT_INI_ARRAY(&ah->iniPcieSerdes, |
Senthil Balasubramanian | e759407 | 2008-12-08 19:43:48 +0530 | [diff] [blame] | 706 | ar9285PciePhy_clkreq_off_L1_9285, |
| 707 | ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2); |
| 708 | } else { |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 709 | INIT_INI_ARRAY(&ah->iniPcieSerdes, |
Senthil Balasubramanian | e759407 | 2008-12-08 19:43:48 +0530 | [diff] [blame] | 710 | ar9285PciePhy_clkreq_always_on_L1_9285, |
| 711 | ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2); |
| 712 | } |
| 713 | } else if (AR_SREV_9280_20_OR_LATER(ah)) { |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 714 | INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2, |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 715 | ARRAY_SIZE(ar9280Modes_9280_2), 6); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 716 | INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2, |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 717 | ARRAY_SIZE(ar9280Common_9280_2), 2); |
| 718 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 719 | if (ah->config.pcie_clock_req) { |
| 720 | INIT_INI_ARRAY(&ah->iniPcieSerdes, |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 721 | ar9280PciePhy_clkreq_off_L1_9280, |
| 722 | ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 723 | } else { |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 724 | INIT_INI_ARRAY(&ah->iniPcieSerdes, |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 725 | ar9280PciePhy_clkreq_always_on_L1_9280, |
| 726 | ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 727 | } |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 728 | INIT_INI_ARRAY(&ah->iniModesAdditional, |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 729 | ar9280Modes_fast_clock_9280_2, |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 730 | ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 731 | } else if (AR_SREV_9280_10_OR_LATER(ah)) { |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 732 | INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280, |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 733 | ARRAY_SIZE(ar9280Modes_9280), 6); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 734 | INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280, |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 735 | ARRAY_SIZE(ar9280Common_9280), 2); |
| 736 | } else if (AR_SREV_9160_10_OR_LATER(ah)) { |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 737 | INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160, |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 738 | ARRAY_SIZE(ar5416Modes_9160), 6); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 739 | INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160, |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 740 | ARRAY_SIZE(ar5416Common_9160), 2); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 741 | INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9160, |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 742 | ARRAY_SIZE(ar5416Bank0_9160), 2); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 743 | INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9160, |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 744 | ARRAY_SIZE(ar5416BB_RfGain_9160), 3); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 745 | INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9160, |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 746 | ARRAY_SIZE(ar5416Bank1_9160), 2); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 747 | INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9160, |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 748 | ARRAY_SIZE(ar5416Bank2_9160), 2); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 749 | INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9160, |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 750 | ARRAY_SIZE(ar5416Bank3_9160), 3); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 751 | INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9160, |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 752 | ARRAY_SIZE(ar5416Bank6_9160), 3); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 753 | INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9160, |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 754 | ARRAY_SIZE(ar5416Bank6TPC_9160), 3); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 755 | INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9160, |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 756 | ARRAY_SIZE(ar5416Bank7_9160), 2); |
| 757 | if (AR_SREV_9160_11(ah)) { |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 758 | INIT_INI_ARRAY(&ah->iniAddac, |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 759 | ar5416Addac_91601_1, |
| 760 | ARRAY_SIZE(ar5416Addac_91601_1), 2); |
| 761 | } else { |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 762 | INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160, |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 763 | ARRAY_SIZE(ar5416Addac_9160), 2); |
| 764 | } |
| 765 | } else if (AR_SREV_9100_OR_LATER(ah)) { |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 766 | INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100, |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 767 | ARRAY_SIZE(ar5416Modes_9100), 6); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 768 | INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100, |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 769 | ARRAY_SIZE(ar5416Common_9100), 2); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 770 | INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9100, |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 771 | ARRAY_SIZE(ar5416Bank0_9100), 2); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 772 | INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9100, |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 773 | ARRAY_SIZE(ar5416BB_RfGain_9100), 3); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 774 | INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9100, |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 775 | ARRAY_SIZE(ar5416Bank1_9100), 2); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 776 | INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9100, |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 777 | ARRAY_SIZE(ar5416Bank2_9100), 2); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 778 | INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9100, |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 779 | ARRAY_SIZE(ar5416Bank3_9100), 3); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 780 | INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100, |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 781 | ARRAY_SIZE(ar5416Bank6_9100), 3); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 782 | INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100, |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 783 | ARRAY_SIZE(ar5416Bank6TPC_9100), 3); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 784 | INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9100, |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 785 | ARRAY_SIZE(ar5416Bank7_9100), 2); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 786 | INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100, |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 787 | ARRAY_SIZE(ar5416Addac_9100), 2); |
| 788 | } else { |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 789 | INIT_INI_ARRAY(&ah->iniModes, ar5416Modes, |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 790 | ARRAY_SIZE(ar5416Modes), 6); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 791 | INIT_INI_ARRAY(&ah->iniCommon, ar5416Common, |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 792 | ARRAY_SIZE(ar5416Common), 2); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 793 | INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0, |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 794 | ARRAY_SIZE(ar5416Bank0), 2); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 795 | INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain, |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 796 | ARRAY_SIZE(ar5416BB_RfGain), 3); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 797 | INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1, |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 798 | ARRAY_SIZE(ar5416Bank1), 2); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 799 | INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2, |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 800 | ARRAY_SIZE(ar5416Bank2), 2); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 801 | INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3, |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 802 | ARRAY_SIZE(ar5416Bank3), 3); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 803 | INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6, |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 804 | ARRAY_SIZE(ar5416Bank6), 3); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 805 | INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC, |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 806 | ARRAY_SIZE(ar5416Bank6TPC), 3); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 807 | INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7, |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 808 | ARRAY_SIZE(ar5416Bank7), 2); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 809 | INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac, |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 810 | ARRAY_SIZE(ar5416Addac), 2); |
| 811 | } |
Luis R. Rodriguez | aa4058a | 2009-08-03 12:24:45 -0700 | [diff] [blame] | 812 | } |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 813 | |
Luis R. Rodriguez | aa4058a | 2009-08-03 12:24:45 -0700 | [diff] [blame] | 814 | static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah) |
| 815 | { |
Vivek Natarajan | b37fa87 | 2009-09-23 16:27:27 +0530 | [diff] [blame] | 816 | if (AR_SREV_9287_11_OR_LATER(ah)) |
Vivek Natarajan | ac88b6e | 2009-07-23 10:59:57 +0530 | [diff] [blame] | 817 | INIT_INI_ARRAY(&ah->iniModesRxGain, |
| 818 | ar9287Modes_rx_gain_9287_1_1, |
| 819 | ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_1), 6); |
| 820 | else if (AR_SREV_9287_10(ah)) |
| 821 | INIT_INI_ARRAY(&ah->iniModesRxGain, |
| 822 | ar9287Modes_rx_gain_9287_1_0, |
| 823 | ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_0), 6); |
| 824 | else if (AR_SREV_9280_20(ah)) |
| 825 | ath9k_hw_init_rxgain_ini(ah); |
| 826 | |
Vivek Natarajan | b37fa87 | 2009-09-23 16:27:27 +0530 | [diff] [blame] | 827 | if (AR_SREV_9287_11_OR_LATER(ah)) { |
Vivek Natarajan | ac88b6e | 2009-07-23 10:59:57 +0530 | [diff] [blame] | 828 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
| 829 | ar9287Modes_tx_gain_9287_1_1, |
| 830 | ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_1), 6); |
| 831 | } else if (AR_SREV_9287_10(ah)) { |
| 832 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
| 833 | ar9287Modes_tx_gain_9287_1_0, |
| 834 | ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_0), 6); |
| 835 | } else if (AR_SREV_9280_20(ah)) { |
| 836 | ath9k_hw_init_txgain_ini(ah); |
| 837 | } else if (AR_SREV_9285_12_OR_LATER(ah)) { |
Senthil Balasubramanian | 4e84516 | 2009-03-06 11:24:10 +0530 | [diff] [blame] | 838 | u32 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE); |
| 839 | |
| 840 | /* txgain table */ |
| 841 | if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) { |
Vivek Natarajan | 53bc7aa | 2010-04-05 14:48:04 +0530 | [diff] [blame] | 842 | if (AR_SREV_9285E_20(ah)) { |
| 843 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
| 844 | ar9285Modes_XE2_0_high_power, |
| 845 | ARRAY_SIZE( |
| 846 | ar9285Modes_XE2_0_high_power), 6); |
| 847 | } else { |
| 848 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
| 849 | ar9285Modes_high_power_tx_gain_9285_1_2, |
| 850 | ARRAY_SIZE( |
| 851 | ar9285Modes_high_power_tx_gain_9285_1_2), 6); |
| 852 | } |
Senthil Balasubramanian | 4e84516 | 2009-03-06 11:24:10 +0530 | [diff] [blame] | 853 | } else { |
Vivek Natarajan | 53bc7aa | 2010-04-05 14:48:04 +0530 | [diff] [blame] | 854 | if (AR_SREV_9285E_20(ah)) { |
| 855 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
| 856 | ar9285Modes_XE2_0_normal_power, |
| 857 | ARRAY_SIZE( |
| 858 | ar9285Modes_XE2_0_normal_power), 6); |
| 859 | } else { |
| 860 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
| 861 | ar9285Modes_original_tx_gain_9285_1_2, |
| 862 | ARRAY_SIZE( |
| 863 | ar9285Modes_original_tx_gain_9285_1_2), 6); |
| 864 | } |
Senthil Balasubramanian | 4e84516 | 2009-03-06 11:24:10 +0530 | [diff] [blame] | 865 | } |
Senthil Balasubramanian | 4e84516 | 2009-03-06 11:24:10 +0530 | [diff] [blame] | 866 | } |
Luis R. Rodriguez | aa4058a | 2009-08-03 12:24:45 -0700 | [diff] [blame] | 867 | } |
Senthil Balasubramanian | 4e84516 | 2009-03-06 11:24:10 +0530 | [diff] [blame] | 868 | |
Felix Fietkau | aa8bc9e | 2010-01-23 20:04:18 +0100 | [diff] [blame] | 869 | static void ath9k_hw_init_eeprom_fix(struct ath_hw *ah) |
Luis R. Rodriguez | aa4058a | 2009-08-03 12:24:45 -0700 | [diff] [blame] | 870 | { |
Pavel Roskin | 2eb46d9 | 2010-04-07 01:33:33 -0400 | [diff] [blame] | 871 | struct base_eep_header *pBase = &(ah->eeprom.def.baseEepHeader); |
| 872 | struct ath_common *common = ath9k_hw_common(ah); |
Sujith | 06d0f06 | 2009-02-12 10:06:45 +0530 | [diff] [blame] | 873 | |
Pavel Roskin | 2eb46d9 | 2010-04-07 01:33:33 -0400 | [diff] [blame] | 874 | ah->need_an_top2_fixup = (ah->hw_version.devid == AR9280_DEVID_PCI) && |
| 875 | (ah->eep_map != EEP_MAP_4KBITS) && |
| 876 | ((pBase->version & 0xff) > 0x0a) && |
| 877 | (pBase->pwdclkind == 0); |
Sujith | 06d0f06 | 2009-02-12 10:06:45 +0530 | [diff] [blame] | 878 | |
Pavel Roskin | 2eb46d9 | 2010-04-07 01:33:33 -0400 | [diff] [blame] | 879 | if (ah->need_an_top2_fixup) |
| 880 | ath_print(common, ATH_DBG_EEPROM, |
| 881 | "needs fixup for AR_AN_TOP2 register\n"); |
Luis R. Rodriguez | aa4058a | 2009-08-03 12:24:45 -0700 | [diff] [blame] | 882 | } |
| 883 | |
Luis R. Rodriguez | 8525f28 | 2010-04-15 17:38:19 -0400 | [diff] [blame] | 884 | static void ath9k_hw_attach_ops(struct ath_hw *ah) |
| 885 | { |
| 886 | if (AR_SREV_9300_20_OR_LATER(ah)) |
| 887 | ar9003_hw_attach_ops(ah); |
| 888 | else |
| 889 | ar9002_hw_attach_ops(ah); |
| 890 | } |
| 891 | |
Luis R. Rodriguez | d70357d | 2010-04-15 17:38:06 -0400 | [diff] [blame] | 892 | /* Called for all hardware families */ |
| 893 | static int __ath9k_hw_init(struct ath_hw *ah) |
Luis R. Rodriguez | aa4058a | 2009-08-03 12:24:45 -0700 | [diff] [blame] | 894 | { |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 895 | struct ath_common *common = ath9k_hw_common(ah); |
Luis R. Rodriguez | 95fafca | 2009-08-03 12:24:54 -0700 | [diff] [blame] | 896 | int r = 0; |
Luis R. Rodriguez | aa4058a | 2009-08-03 12:24:45 -0700 | [diff] [blame] | 897 | |
Luis R. Rodriguez | bab1f62 | 2010-04-15 17:38:20 -0400 | [diff] [blame] | 898 | if (ah->hw_version.devid == AR5416_AR9100_DEVID) |
| 899 | ah->hw_version.macVersion = AR_SREV_VERSION_9100; |
Luis R. Rodriguez | aa4058a | 2009-08-03 12:24:45 -0700 | [diff] [blame] | 900 | |
| 901 | if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) { |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 902 | ath_print(common, ATH_DBG_FATAL, |
| 903 | "Couldn't reset chip\n"); |
Luis R. Rodriguez | 95fafca | 2009-08-03 12:24:54 -0700 | [diff] [blame] | 904 | return -EIO; |
Luis R. Rodriguez | aa4058a | 2009-08-03 12:24:45 -0700 | [diff] [blame] | 905 | } |
| 906 | |
Luis R. Rodriguez | bab1f62 | 2010-04-15 17:38:20 -0400 | [diff] [blame] | 907 | ath9k_hw_init_defaults(ah); |
| 908 | ath9k_hw_init_config(ah); |
| 909 | |
Luis R. Rodriguez | 8525f28 | 2010-04-15 17:38:19 -0400 | [diff] [blame] | 910 | ath9k_hw_attach_ops(ah); |
Luis R. Rodriguez | d70357d | 2010-04-15 17:38:06 -0400 | [diff] [blame] | 911 | |
Luis R. Rodriguez | 9ecdef4 | 2009-09-09 21:10:09 -0700 | [diff] [blame] | 912 | if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) { |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 913 | ath_print(common, ATH_DBG_FATAL, "Couldn't wakeup chip\n"); |
Luis R. Rodriguez | 95fafca | 2009-08-03 12:24:54 -0700 | [diff] [blame] | 914 | return -EIO; |
Luis R. Rodriguez | aa4058a | 2009-08-03 12:24:45 -0700 | [diff] [blame] | 915 | } |
| 916 | |
| 917 | if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) { |
| 918 | if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI || |
| 919 | (AR_SREV_9280(ah) && !ah->is_pciexpress)) { |
| 920 | ah->config.serialize_regmode = |
| 921 | SER_REG_MODE_ON; |
| 922 | } else { |
| 923 | ah->config.serialize_regmode = |
| 924 | SER_REG_MODE_OFF; |
| 925 | } |
| 926 | } |
| 927 | |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 928 | ath_print(common, ATH_DBG_RESET, "serialize_regmode is %d\n", |
Luis R. Rodriguez | aa4058a | 2009-08-03 12:24:45 -0700 | [diff] [blame] | 929 | ah->config.serialize_regmode); |
| 930 | |
Luis R. Rodriguez | f4709fd | 2009-11-24 21:37:57 -0500 | [diff] [blame] | 931 | if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) |
| 932 | ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1; |
| 933 | else |
| 934 | ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD; |
| 935 | |
Luis R. Rodriguez | d70357d | 2010-04-15 17:38:06 -0400 | [diff] [blame] | 936 | if (!ath9k_hw_macversion_supported(ah)) { |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 937 | ath_print(common, ATH_DBG_FATAL, |
| 938 | "Mac Chip Rev 0x%02x.%x is not supported by " |
| 939 | "this driver\n", ah->hw_version.macVersion, |
| 940 | ah->hw_version.macRev); |
Luis R. Rodriguez | 95fafca | 2009-08-03 12:24:54 -0700 | [diff] [blame] | 941 | return -EOPNOTSUPP; |
Luis R. Rodriguez | aa4058a | 2009-08-03 12:24:45 -0700 | [diff] [blame] | 942 | } |
| 943 | |
| 944 | if (AR_SREV_9100(ah)) { |
| 945 | ah->iq_caldata.calData = &iq_cal_multi_sample; |
| 946 | ah->supp_cals = IQ_MISMATCH_CAL; |
| 947 | ah->is_pciexpress = false; |
| 948 | } |
Luis R. Rodriguez | d7e7d22 | 2009-08-03 23:14:12 -0400 | [diff] [blame] | 949 | |
| 950 | if (AR_SREV_9271(ah)) |
| 951 | ah->is_pciexpress = false; |
| 952 | |
Luis R. Rodriguez | aa4058a | 2009-08-03 12:24:45 -0700 | [diff] [blame] | 953 | ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID); |
Luis R. Rodriguez | aa4058a | 2009-08-03 12:24:45 -0700 | [diff] [blame] | 954 | ath9k_hw_init_cal_settings(ah); |
| 955 | |
| 956 | ah->ani_function = ATH9K_ANI_ALL; |
Luis R. Rodriguez | 31a0bd3 | 2010-04-15 17:38:22 -0400 | [diff] [blame] | 957 | if (AR_SREV_9280_10_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah)) |
Luis R. Rodriguez | aa4058a | 2009-08-03 12:24:45 -0700 | [diff] [blame] | 958 | ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL; |
| 959 | |
| 960 | ath9k_hw_init_mode_regs(ah); |
| 961 | |
| 962 | if (ah->is_pciexpress) |
Vivek Natarajan | 93b1b37 | 2009-09-17 09:24:58 +0530 | [diff] [blame] | 963 | ath9k_hw_configpcipowersave(ah, 0, 0); |
Luis R. Rodriguez | aa4058a | 2009-08-03 12:24:45 -0700 | [diff] [blame] | 964 | else |
| 965 | ath9k_hw_disablepcie(ah); |
| 966 | |
Sujith | 193cd45 | 2009-09-18 15:04:07 +0530 | [diff] [blame] | 967 | /* Support for Japan ch.14 (2484) spread */ |
| 968 | if (AR_SREV_9287_11_OR_LATER(ah)) { |
| 969 | INIT_INI_ARRAY(&ah->iniCckfirNormal, |
| 970 | ar9287Common_normal_cck_fir_coeff_92871_1, |
| 971 | ARRAY_SIZE(ar9287Common_normal_cck_fir_coeff_92871_1), 2); |
| 972 | INIT_INI_ARRAY(&ah->iniCckfirJapan2484, |
| 973 | ar9287Common_japan_2484_cck_fir_coeff_92871_1, |
| 974 | ARRAY_SIZE(ar9287Common_japan_2484_cck_fir_coeff_92871_1), 2); |
| 975 | } |
| 976 | |
Luis R. Rodriguez | f637cfd | 2009-08-03 12:24:46 -0700 | [diff] [blame] | 977 | r = ath9k_hw_post_init(ah); |
Luis R. Rodriguez | aa4058a | 2009-08-03 12:24:45 -0700 | [diff] [blame] | 978 | if (r) |
Luis R. Rodriguez | 95fafca | 2009-08-03 12:24:54 -0700 | [diff] [blame] | 979 | return r; |
Luis R. Rodriguez | aa4058a | 2009-08-03 12:24:45 -0700 | [diff] [blame] | 980 | |
| 981 | ath9k_hw_init_mode_gain_regs(ah); |
Gabor Juhos | a9a29ce | 2009-11-27 12:01:35 +0100 | [diff] [blame] | 982 | r = ath9k_hw_fill_cap_info(ah); |
| 983 | if (r) |
| 984 | return r; |
| 985 | |
Felix Fietkau | aa8bc9e | 2010-01-23 20:04:18 +0100 | [diff] [blame] | 986 | ath9k_hw_init_eeprom_fix(ah); |
Sujith | f6688cd | 2008-12-07 21:43:10 +0530 | [diff] [blame] | 987 | |
Luis R. Rodriguez | 4f3acf8 | 2009-08-03 12:24:36 -0700 | [diff] [blame] | 988 | r = ath9k_hw_init_macaddr(ah); |
| 989 | if (r) { |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 990 | ath_print(common, ATH_DBG_FATAL, |
| 991 | "Failed to initialize MAC address\n"); |
Luis R. Rodriguez | 95fafca | 2009-08-03 12:24:54 -0700 | [diff] [blame] | 992 | return r; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 993 | } |
| 994 | |
Luis R. Rodriguez | d7e7d22 | 2009-08-03 23:14:12 -0400 | [diff] [blame] | 995 | if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 996 | ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 997 | else |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 998 | ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 999 | |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1000 | ath9k_init_nfcal_hist_buffer(ah); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1001 | |
Luis R. Rodriguez | 211f585 | 2009-10-06 21:19:07 -0400 | [diff] [blame] | 1002 | common->state = ATH_HW_INITIALIZED; |
| 1003 | |
Luis R. Rodriguez | 4f3acf8 | 2009-08-03 12:24:36 -0700 | [diff] [blame] | 1004 | return 0; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1005 | } |
| 1006 | |
Luis R. Rodriguez | d70357d | 2010-04-15 17:38:06 -0400 | [diff] [blame] | 1007 | int ath9k_hw_init(struct ath_hw *ah) |
| 1008 | { |
| 1009 | int ret; |
| 1010 | struct ath_common *common = ath9k_hw_common(ah); |
| 1011 | |
| 1012 | /* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */ |
| 1013 | switch (ah->hw_version.devid) { |
| 1014 | case AR5416_DEVID_PCI: |
| 1015 | case AR5416_DEVID_PCIE: |
| 1016 | case AR5416_AR9100_DEVID: |
| 1017 | case AR9160_DEVID_PCI: |
| 1018 | case AR9280_DEVID_PCI: |
| 1019 | case AR9280_DEVID_PCIE: |
| 1020 | case AR9285_DEVID_PCIE: |
Senthil Balasubramanian | db3cc53 | 2010-04-15 17:38:18 -0400 | [diff] [blame] | 1021 | case AR9287_DEVID_PCI: |
| 1022 | case AR9287_DEVID_PCIE: |
Luis R. Rodriguez | d70357d | 2010-04-15 17:38:06 -0400 | [diff] [blame] | 1023 | case AR2427_DEVID_PCIE: |
Senthil Balasubramanian | db3cc53 | 2010-04-15 17:38:18 -0400 | [diff] [blame] | 1024 | case AR9300_DEVID_PCIE: |
Luis R. Rodriguez | d70357d | 2010-04-15 17:38:06 -0400 | [diff] [blame] | 1025 | break; |
| 1026 | default: |
| 1027 | if (common->bus_ops->ath_bus_type == ATH_USB) |
| 1028 | break; |
| 1029 | ath_print(common, ATH_DBG_FATAL, |
| 1030 | "Hardware device ID 0x%04x not supported\n", |
| 1031 | ah->hw_version.devid); |
| 1032 | return -EOPNOTSUPP; |
| 1033 | } |
| 1034 | |
| 1035 | ret = __ath9k_hw_init(ah); |
| 1036 | if (ret) { |
| 1037 | ath_print(common, ATH_DBG_FATAL, |
| 1038 | "Unable to initialize hardware; " |
| 1039 | "initialization status: %d\n", ret); |
| 1040 | return ret; |
| 1041 | } |
| 1042 | |
| 1043 | return 0; |
| 1044 | } |
| 1045 | EXPORT_SYMBOL(ath9k_hw_init); |
| 1046 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 1047 | static void ath9k_hw_init_qos(struct ath_hw *ah) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1048 | { |
| 1049 | REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa); |
| 1050 | REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210); |
| 1051 | |
| 1052 | REG_WRITE(ah, AR_QOS_NO_ACK, |
| 1053 | SM(2, AR_QOS_NO_ACK_TWO_BIT) | |
| 1054 | SM(5, AR_QOS_NO_ACK_BIT_OFF) | |
| 1055 | SM(0, AR_QOS_NO_ACK_BYTE_OFF)); |
| 1056 | |
| 1057 | REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL); |
| 1058 | REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF); |
| 1059 | REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF); |
| 1060 | REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF); |
| 1061 | REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF); |
| 1062 | } |
| 1063 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 1064 | static void ath9k_hw_init_pll(struct ath_hw *ah, |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1065 | struct ath9k_channel *chan) |
| 1066 | { |
Luis R. Rodriguez | 6477396 | 2010-04-15 17:38:17 -0400 | [diff] [blame] | 1067 | u32 pll = ath9k_hw_compute_pll_control(ah, chan); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1068 | |
Gabor Juhos | d03a66c | 2009-01-14 20:17:09 +0100 | [diff] [blame] | 1069 | REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1070 | |
Luis R. Rodriguez | c75724d | 2009-10-19 02:33:34 -0400 | [diff] [blame] | 1071 | /* Switch the core clock for ar9271 to 117Mhz */ |
| 1072 | if (AR_SREV_9271(ah)) { |
Sujith | 25e2ab1 | 2010-03-17 14:25:22 +0530 | [diff] [blame] | 1073 | udelay(500); |
| 1074 | REG_WRITE(ah, 0x50040, 0x304); |
Luis R. Rodriguez | c75724d | 2009-10-19 02:33:34 -0400 | [diff] [blame] | 1075 | } |
| 1076 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1077 | udelay(RTC_PLL_SETTLE_DELAY); |
| 1078 | |
| 1079 | REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK); |
| 1080 | } |
| 1081 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 1082 | static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah, |
Colin McCabe | d97809d | 2008-12-01 13:38:55 -0800 | [diff] [blame] | 1083 | enum nl80211_iftype opmode) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1084 | { |
Pavel Roskin | 152d530 | 2010-03-31 18:05:37 -0400 | [diff] [blame] | 1085 | u32 imr_reg = AR_IMR_TXERR | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1086 | AR_IMR_TXURN | |
| 1087 | AR_IMR_RXERR | |
| 1088 | AR_IMR_RXORN | |
| 1089 | AR_IMR_BCNMISC; |
| 1090 | |
Sujith | 0ce024c | 2009-12-14 14:57:00 +0530 | [diff] [blame] | 1091 | if (ah->config.rx_intr_mitigation) |
Pavel Roskin | 152d530 | 2010-03-31 18:05:37 -0400 | [diff] [blame] | 1092 | imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1093 | else |
Pavel Roskin | 152d530 | 2010-03-31 18:05:37 -0400 | [diff] [blame] | 1094 | imr_reg |= AR_IMR_RXOK; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1095 | |
Pavel Roskin | 152d530 | 2010-03-31 18:05:37 -0400 | [diff] [blame] | 1096 | imr_reg |= AR_IMR_TXOK; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1097 | |
Colin McCabe | d97809d | 2008-12-01 13:38:55 -0800 | [diff] [blame] | 1098 | if (opmode == NL80211_IFTYPE_AP) |
Pavel Roskin | 152d530 | 2010-03-31 18:05:37 -0400 | [diff] [blame] | 1099 | imr_reg |= AR_IMR_MIB; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1100 | |
Pavel Roskin | 152d530 | 2010-03-31 18:05:37 -0400 | [diff] [blame] | 1101 | REG_WRITE(ah, AR_IMR, imr_reg); |
Pavel Roskin | 74bad5c | 2010-02-23 18:15:27 -0500 | [diff] [blame] | 1102 | ah->imrs2_reg |= AR_IMR_S2_GTT; |
| 1103 | REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1104 | |
| 1105 | if (!AR_SREV_9100(ah)) { |
| 1106 | REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF); |
| 1107 | REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT); |
| 1108 | REG_WRITE(ah, AR_INTR_SYNC_MASK, 0); |
| 1109 | } |
| 1110 | } |
| 1111 | |
Felix Fietkau | 0005baf | 2010-01-15 02:33:40 +0100 | [diff] [blame] | 1112 | static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1113 | { |
Felix Fietkau | 0005baf | 2010-01-15 02:33:40 +0100 | [diff] [blame] | 1114 | u32 val = ath9k_hw_mac_to_clks(ah, us); |
| 1115 | val = min(val, (u32) 0xFFFF); |
| 1116 | REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1117 | } |
| 1118 | |
Felix Fietkau | 0005baf | 2010-01-15 02:33:40 +0100 | [diff] [blame] | 1119 | static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1120 | { |
Felix Fietkau | 0005baf | 2010-01-15 02:33:40 +0100 | [diff] [blame] | 1121 | u32 val = ath9k_hw_mac_to_clks(ah, us); |
| 1122 | val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK)); |
| 1123 | REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val); |
| 1124 | } |
| 1125 | |
| 1126 | static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us) |
| 1127 | { |
| 1128 | u32 val = ath9k_hw_mac_to_clks(ah, us); |
| 1129 | val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS)); |
| 1130 | REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1131 | } |
| 1132 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 1133 | static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1134 | { |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1135 | if (tu > 0xFFFF) { |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 1136 | ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT, |
| 1137 | "bad global tx timeout %u\n", tu); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1138 | ah->globaltxtimeout = (u32) -1; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1139 | return false; |
| 1140 | } else { |
| 1141 | REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1142 | ah->globaltxtimeout = tu; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1143 | return true; |
| 1144 | } |
| 1145 | } |
| 1146 | |
Felix Fietkau | 0005baf | 2010-01-15 02:33:40 +0100 | [diff] [blame] | 1147 | void ath9k_hw_init_global_settings(struct ath_hw *ah) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1148 | { |
Felix Fietkau | 0005baf | 2010-01-15 02:33:40 +0100 | [diff] [blame] | 1149 | struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf; |
| 1150 | int acktimeout; |
Felix Fietkau | e239d85 | 2010-01-15 02:34:58 +0100 | [diff] [blame] | 1151 | int slottime; |
Felix Fietkau | 0005baf | 2010-01-15 02:33:40 +0100 | [diff] [blame] | 1152 | int sifstime; |
| 1153 | |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 1154 | ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n", |
| 1155 | ah->misc_mode); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1156 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1157 | if (ah->misc_mode != 0) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1158 | REG_WRITE(ah, AR_PCU_MISC, |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1159 | REG_READ(ah, AR_PCU_MISC) | ah->misc_mode); |
Felix Fietkau | 0005baf | 2010-01-15 02:33:40 +0100 | [diff] [blame] | 1160 | |
| 1161 | if (conf->channel && conf->channel->band == IEEE80211_BAND_5GHZ) |
| 1162 | sifstime = 16; |
| 1163 | else |
| 1164 | sifstime = 10; |
| 1165 | |
Felix Fietkau | e239d85 | 2010-01-15 02:34:58 +0100 | [diff] [blame] | 1166 | /* As defined by IEEE 802.11-2007 17.3.8.6 */ |
| 1167 | slottime = ah->slottime + 3 * ah->coverage_class; |
| 1168 | acktimeout = slottime + sifstime; |
Felix Fietkau | 42c4568 | 2010-02-11 18:07:19 +0100 | [diff] [blame] | 1169 | |
| 1170 | /* |
| 1171 | * Workaround for early ACK timeouts, add an offset to match the |
| 1172 | * initval's 64us ack timeout value. |
| 1173 | * This was initially only meant to work around an issue with delayed |
| 1174 | * BA frames in some implementations, but it has been found to fix ACK |
| 1175 | * timeout issues in other cases as well. |
| 1176 | */ |
| 1177 | if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ) |
| 1178 | acktimeout += 64 - sifstime - ah->slottime; |
| 1179 | |
Felix Fietkau | e239d85 | 2010-01-15 02:34:58 +0100 | [diff] [blame] | 1180 | ath9k_hw_setslottime(ah, slottime); |
Felix Fietkau | 0005baf | 2010-01-15 02:33:40 +0100 | [diff] [blame] | 1181 | ath9k_hw_set_ack_timeout(ah, acktimeout); |
| 1182 | ath9k_hw_set_cts_timeout(ah, acktimeout); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1183 | if (ah->globaltxtimeout != (u32) -1) |
| 1184 | ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1185 | } |
Felix Fietkau | 0005baf | 2010-01-15 02:33:40 +0100 | [diff] [blame] | 1186 | EXPORT_SYMBOL(ath9k_hw_init_global_settings); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1187 | |
Sujith | 285f2dd | 2010-01-08 10:36:07 +0530 | [diff] [blame] | 1188 | void ath9k_hw_deinit(struct ath_hw *ah) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1189 | { |
Luis R. Rodriguez | 211f585 | 2009-10-06 21:19:07 -0400 | [diff] [blame] | 1190 | struct ath_common *common = ath9k_hw_common(ah); |
| 1191 | |
Sujith | 736b3a2 | 2010-03-17 14:25:24 +0530 | [diff] [blame] | 1192 | if (common->state < ATH_HW_INITIALIZED) |
Luis R. Rodriguez | 211f585 | 2009-10-06 21:19:07 -0400 | [diff] [blame] | 1193 | goto free_hw; |
| 1194 | |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1195 | if (!AR_SREV_9100(ah)) |
Luis R. Rodriguez | e70c0cf | 2009-08-03 12:24:51 -0700 | [diff] [blame] | 1196 | ath9k_hw_ani_disable(ah); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1197 | |
Luis R. Rodriguez | 9ecdef4 | 2009-09-09 21:10:09 -0700 | [diff] [blame] | 1198 | ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP); |
Luis R. Rodriguez | 211f585 | 2009-10-06 21:19:07 -0400 | [diff] [blame] | 1199 | |
| 1200 | free_hw: |
Luis R. Rodriguez | 8fe6536 | 2010-04-15 17:38:14 -0400 | [diff] [blame] | 1201 | ath9k_hw_rf_free_ext_banks(ah); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1202 | } |
Sujith | 285f2dd | 2010-01-08 10:36:07 +0530 | [diff] [blame] | 1203 | EXPORT_SYMBOL(ath9k_hw_deinit); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1204 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1205 | /*******/ |
| 1206 | /* INI */ |
| 1207 | /*******/ |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1208 | |
Luis R. Rodriguez | 8fe6536 | 2010-04-15 17:38:14 -0400 | [diff] [blame] | 1209 | u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan) |
Bob Copeland | 3a702e4 | 2009-03-30 22:30:29 -0400 | [diff] [blame] | 1210 | { |
| 1211 | u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band); |
| 1212 | |
| 1213 | if (IS_CHAN_B(chan)) |
| 1214 | ctl |= CTL_11B; |
| 1215 | else if (IS_CHAN_G(chan)) |
| 1216 | ctl |= CTL_11G; |
| 1217 | else |
| 1218 | ctl |= CTL_11A; |
| 1219 | |
| 1220 | return ctl; |
| 1221 | } |
| 1222 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1223 | /****************************************/ |
| 1224 | /* Reset and Channel Switching Routines */ |
| 1225 | /****************************************/ |
| 1226 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 1227 | static inline void ath9k_hw_set_dma(struct ath_hw *ah) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1228 | { |
| 1229 | u32 regval; |
| 1230 | |
Luis R. Rodriguez | d7e7d22 | 2009-08-03 23:14:12 -0400 | [diff] [blame] | 1231 | /* |
| 1232 | * set AHB_MODE not to do cacheline prefetches |
| 1233 | */ |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1234 | regval = REG_READ(ah, AR_AHB_MODE); |
| 1235 | REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN); |
| 1236 | |
Luis R. Rodriguez | d7e7d22 | 2009-08-03 23:14:12 -0400 | [diff] [blame] | 1237 | /* |
| 1238 | * let mac dma reads be in 128 byte chunks |
| 1239 | */ |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1240 | regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK; |
| 1241 | REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B); |
| 1242 | |
Luis R. Rodriguez | d7e7d22 | 2009-08-03 23:14:12 -0400 | [diff] [blame] | 1243 | /* |
| 1244 | * Restore TX Trigger Level to its pre-reset value. |
| 1245 | * The initial value depends on whether aggregation is enabled, and is |
| 1246 | * adjusted whenever underruns are detected. |
| 1247 | */ |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1248 | REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1249 | |
Luis R. Rodriguez | d7e7d22 | 2009-08-03 23:14:12 -0400 | [diff] [blame] | 1250 | /* |
| 1251 | * let mac dma writes be in 128 byte chunks |
| 1252 | */ |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1253 | regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK; |
| 1254 | REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B); |
| 1255 | |
Luis R. Rodriguez | d7e7d22 | 2009-08-03 23:14:12 -0400 | [diff] [blame] | 1256 | /* |
| 1257 | * Setup receive FIFO threshold to hold off TX activities |
| 1258 | */ |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1259 | REG_WRITE(ah, AR_RXFIFO_CFG, 0x200); |
| 1260 | |
Luis R. Rodriguez | d7e7d22 | 2009-08-03 23:14:12 -0400 | [diff] [blame] | 1261 | /* |
| 1262 | * reduce the number of usable entries in PCU TXBUF to avoid |
| 1263 | * wrap around issues. |
| 1264 | */ |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1265 | if (AR_SREV_9285(ah)) { |
Luis R. Rodriguez | d7e7d22 | 2009-08-03 23:14:12 -0400 | [diff] [blame] | 1266 | /* For AR9285 the number of Fifos are reduced to half. |
| 1267 | * So set the usable tx buf size also to half to |
| 1268 | * avoid data/delimiter underruns |
| 1269 | */ |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1270 | REG_WRITE(ah, AR_PCU_TXBUF_CTRL, |
| 1271 | AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE); |
Luis R. Rodriguez | d7e7d22 | 2009-08-03 23:14:12 -0400 | [diff] [blame] | 1272 | } else if (!AR_SREV_9271(ah)) { |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1273 | REG_WRITE(ah, AR_PCU_TXBUF_CTRL, |
| 1274 | AR_PCU_TXBUF_CTRL_USABLE_SIZE); |
| 1275 | } |
| 1276 | } |
| 1277 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 1278 | static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1279 | { |
| 1280 | u32 val; |
| 1281 | |
| 1282 | val = REG_READ(ah, AR_STA_ID1); |
| 1283 | val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC); |
| 1284 | switch (opmode) { |
Colin McCabe | d97809d | 2008-12-01 13:38:55 -0800 | [diff] [blame] | 1285 | case NL80211_IFTYPE_AP: |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1286 | REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP |
| 1287 | | AR_STA_ID1_KSRCH_MODE); |
| 1288 | REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); |
| 1289 | break; |
Colin McCabe | d97809d | 2008-12-01 13:38:55 -0800 | [diff] [blame] | 1290 | case NL80211_IFTYPE_ADHOC: |
Pat Erley | 9cb5412 | 2009-03-20 22:59:59 -0400 | [diff] [blame] | 1291 | case NL80211_IFTYPE_MESH_POINT: |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1292 | REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC |
| 1293 | | AR_STA_ID1_KSRCH_MODE); |
| 1294 | REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); |
| 1295 | break; |
Colin McCabe | d97809d | 2008-12-01 13:38:55 -0800 | [diff] [blame] | 1296 | case NL80211_IFTYPE_STATION: |
| 1297 | case NL80211_IFTYPE_MONITOR: |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1298 | REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE); |
| 1299 | break; |
| 1300 | } |
| 1301 | } |
| 1302 | |
Luis R. Rodriguez | 8fe6536 | 2010-04-15 17:38:14 -0400 | [diff] [blame] | 1303 | void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled, |
| 1304 | u32 *coef_mantissa, u32 *coef_exponent) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1305 | { |
| 1306 | u32 coef_exp, coef_man; |
| 1307 | |
| 1308 | for (coef_exp = 31; coef_exp > 0; coef_exp--) |
| 1309 | if ((coef_scaled >> coef_exp) & 0x1) |
| 1310 | break; |
| 1311 | |
| 1312 | coef_exp = 14 - (coef_exp - COEF_SCALE_S); |
| 1313 | |
| 1314 | coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1)); |
| 1315 | |
| 1316 | *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp); |
| 1317 | *coef_exponent = coef_exp - 16; |
| 1318 | } |
| 1319 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 1320 | static bool ath9k_hw_set_reset(struct ath_hw *ah, int type) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1321 | { |
| 1322 | u32 rst_flags; |
| 1323 | u32 tmpReg; |
| 1324 | |
Sujith | 7076849 | 2009-02-16 13:23:12 +0530 | [diff] [blame] | 1325 | if (AR_SREV_9100(ah)) { |
| 1326 | u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK); |
| 1327 | val &= ~AR_RTC_DERIVED_CLK_PERIOD; |
| 1328 | val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD); |
| 1329 | REG_WRITE(ah, AR_RTC_DERIVED_CLK, val); |
| 1330 | (void)REG_READ(ah, AR_RTC_DERIVED_CLK); |
| 1331 | } |
| 1332 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1333 | REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | |
| 1334 | AR_RTC_FORCE_WAKE_ON_INT); |
| 1335 | |
| 1336 | if (AR_SREV_9100(ah)) { |
| 1337 | rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD | |
| 1338 | AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET; |
| 1339 | } else { |
| 1340 | tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE); |
| 1341 | if (tmpReg & |
| 1342 | (AR_INTR_SYNC_LOCAL_TIMEOUT | |
| 1343 | AR_INTR_SYNC_RADM_CPL_TIMEOUT)) { |
Luis R. Rodriguez | 42d5bc3 | 2010-04-15 17:38:12 -0400 | [diff] [blame] | 1344 | u32 val; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1345 | REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0); |
Luis R. Rodriguez | 42d5bc3 | 2010-04-15 17:38:12 -0400 | [diff] [blame] | 1346 | |
| 1347 | val = AR_RC_HOSTIF; |
| 1348 | if (!AR_SREV_9300_20_OR_LATER(ah)) |
| 1349 | val |= AR_RC_AHB; |
| 1350 | REG_WRITE(ah, AR_RC, val); |
| 1351 | |
| 1352 | } else if (!AR_SREV_9300_20_OR_LATER(ah)) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1353 | REG_WRITE(ah, AR_RC, AR_RC_AHB); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1354 | |
| 1355 | rst_flags = AR_RTC_RC_MAC_WARM; |
| 1356 | if (type == ATH9K_RESET_COLD) |
| 1357 | rst_flags |= AR_RTC_RC_MAC_COLD; |
| 1358 | } |
| 1359 | |
Gabor Juhos | d03a66c | 2009-01-14 20:17:09 +0100 | [diff] [blame] | 1360 | REG_WRITE(ah, AR_RTC_RC, rst_flags); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1361 | udelay(50); |
| 1362 | |
Gabor Juhos | d03a66c | 2009-01-14 20:17:09 +0100 | [diff] [blame] | 1363 | REG_WRITE(ah, AR_RTC_RC, 0); |
Sujith | 0caa7b1 | 2009-02-16 13:23:20 +0530 | [diff] [blame] | 1364 | if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) { |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 1365 | ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, |
| 1366 | "RTC stuck in MAC reset\n"); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1367 | return false; |
| 1368 | } |
| 1369 | |
| 1370 | if (!AR_SREV_9100(ah)) |
| 1371 | REG_WRITE(ah, AR_RC, 0); |
| 1372 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1373 | if (AR_SREV_9100(ah)) |
| 1374 | udelay(50); |
| 1375 | |
| 1376 | return true; |
| 1377 | } |
| 1378 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 1379 | static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1380 | { |
| 1381 | REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | |
| 1382 | AR_RTC_FORCE_WAKE_ON_INT); |
| 1383 | |
Luis R. Rodriguez | 42d5bc3 | 2010-04-15 17:38:12 -0400 | [diff] [blame] | 1384 | if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) |
Vasanthakumar Thiagarajan | 1c29ce6 | 2009-08-31 17:48:36 +0530 | [diff] [blame] | 1385 | REG_WRITE(ah, AR_RC, AR_RC_AHB); |
| 1386 | |
Gabor Juhos | d03a66c | 2009-01-14 20:17:09 +0100 | [diff] [blame] | 1387 | REG_WRITE(ah, AR_RTC_RESET, 0); |
Vasanthakumar Thiagarajan | 1c29ce6 | 2009-08-31 17:48:36 +0530 | [diff] [blame] | 1388 | |
Senthil Balasubramanian | 84e2169 | 2010-04-15 17:38:30 -0400 | [diff] [blame^] | 1389 | if (!AR_SREV_9300_20_OR_LATER(ah)) |
| 1390 | udelay(2); |
| 1391 | |
| 1392 | if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) |
Vasanthakumar Thiagarajan | 1c29ce6 | 2009-08-31 17:48:36 +0530 | [diff] [blame] | 1393 | REG_WRITE(ah, AR_RC, 0); |
| 1394 | |
Gabor Juhos | d03a66c | 2009-01-14 20:17:09 +0100 | [diff] [blame] | 1395 | REG_WRITE(ah, AR_RTC_RESET, 1); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1396 | |
| 1397 | if (!ath9k_hw_wait(ah, |
| 1398 | AR_RTC_STATUS, |
| 1399 | AR_RTC_STATUS_M, |
Sujith | 0caa7b1 | 2009-02-16 13:23:20 +0530 | [diff] [blame] | 1400 | AR_RTC_STATUS_ON, |
| 1401 | AH_WAIT_TIMEOUT)) { |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 1402 | ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, |
| 1403 | "RTC not waking up\n"); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1404 | return false; |
| 1405 | } |
| 1406 | |
| 1407 | ath9k_hw_read_revisions(ah); |
| 1408 | |
| 1409 | return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM); |
| 1410 | } |
| 1411 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 1412 | static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1413 | { |
| 1414 | REG_WRITE(ah, AR_RTC_FORCE_WAKE, |
| 1415 | AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT); |
| 1416 | |
| 1417 | switch (type) { |
| 1418 | case ATH9K_RESET_POWER_ON: |
| 1419 | return ath9k_hw_set_reset_power_on(ah); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1420 | case ATH9K_RESET_WARM: |
| 1421 | case ATH9K_RESET_COLD: |
| 1422 | return ath9k_hw_set_reset(ah, type); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1423 | default: |
| 1424 | return false; |
| 1425 | } |
| 1426 | } |
| 1427 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 1428 | static bool ath9k_hw_chip_reset(struct ath_hw *ah, |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1429 | struct ath9k_channel *chan) |
| 1430 | { |
Vivek Natarajan | 42abfbe | 2009-09-17 09:27:59 +0530 | [diff] [blame] | 1431 | if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) { |
Senthil Balasubramanian | 8bd1d07 | 2009-02-12 13:57:03 +0530 | [diff] [blame] | 1432 | if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) |
| 1433 | return false; |
| 1434 | } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM)) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1435 | return false; |
| 1436 | |
Luis R. Rodriguez | 9ecdef4 | 2009-09-09 21:10:09 -0700 | [diff] [blame] | 1437 | if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1438 | return false; |
| 1439 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1440 | ah->chip_fullsleep = false; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1441 | ath9k_hw_init_pll(ah, chan); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1442 | ath9k_hw_set_rfmode(ah, chan); |
| 1443 | |
| 1444 | return true; |
| 1445 | } |
| 1446 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 1447 | static bool ath9k_hw_channel_change(struct ath_hw *ah, |
Luis R. Rodriguez | 25c56ee | 2009-09-13 23:04:44 -0700 | [diff] [blame] | 1448 | struct ath9k_channel *chan) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1449 | { |
Luis R. Rodriguez | 608b88c | 2009-08-17 18:07:23 -0700 | [diff] [blame] | 1450 | struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 1451 | struct ath_common *common = ath9k_hw_common(ah); |
Luis R. Rodriguez | 5f8e077 | 2009-01-22 15:16:48 -0800 | [diff] [blame] | 1452 | struct ieee80211_channel *channel = chan->chan; |
Luis R. Rodriguez | 8fe6536 | 2010-04-15 17:38:14 -0400 | [diff] [blame] | 1453 | u32 qnum; |
Luis R. Rodriguez | 0a3b7ba | 2009-10-19 02:33:40 -0400 | [diff] [blame] | 1454 | int r; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1455 | |
| 1456 | for (qnum = 0; qnum < AR_NUM_QCU; qnum++) { |
| 1457 | if (ath9k_hw_numtxpending(ah, qnum)) { |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 1458 | ath_print(common, ATH_DBG_QUEUE, |
| 1459 | "Transmit frames pending on " |
| 1460 | "queue %d\n", qnum); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1461 | return false; |
| 1462 | } |
| 1463 | } |
| 1464 | |
Luis R. Rodriguez | 8fe6536 | 2010-04-15 17:38:14 -0400 | [diff] [blame] | 1465 | if (!ath9k_hw_rfbus_req(ah)) { |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 1466 | ath_print(common, ATH_DBG_FATAL, |
| 1467 | "Could not kill baseband RX\n"); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1468 | return false; |
| 1469 | } |
| 1470 | |
Luis R. Rodriguez | 8fe6536 | 2010-04-15 17:38:14 -0400 | [diff] [blame] | 1471 | ath9k_hw_set_channel_regs(ah, chan); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1472 | |
Luis R. Rodriguez | 8fe6536 | 2010-04-15 17:38:14 -0400 | [diff] [blame] | 1473 | r = ath9k_hw_rf_set_freq(ah, chan); |
Luis R. Rodriguez | 0a3b7ba | 2009-10-19 02:33:40 -0400 | [diff] [blame] | 1474 | if (r) { |
| 1475 | ath_print(common, ATH_DBG_FATAL, |
| 1476 | "Failed to set channel\n"); |
| 1477 | return false; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1478 | } |
| 1479 | |
Vasanthakumar Thiagarajan | 8fbff4b | 2009-05-08 17:54:51 -0700 | [diff] [blame] | 1480 | ah->eep_ops->set_txpower(ah, chan, |
Luis R. Rodriguez | 608b88c | 2009-08-17 18:07:23 -0700 | [diff] [blame] | 1481 | ath9k_regd_get_ctl(regulatory, chan), |
Sujith | f74df6f | 2009-02-09 13:27:24 +0530 | [diff] [blame] | 1482 | channel->max_antenna_gain * 2, |
| 1483 | channel->max_power * 2, |
| 1484 | min((u32) MAX_RATE_POWER, |
Luis R. Rodriguez | 608b88c | 2009-08-17 18:07:23 -0700 | [diff] [blame] | 1485 | (u32) regulatory->power_limit)); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1486 | |
Luis R. Rodriguez | 8fe6536 | 2010-04-15 17:38:14 -0400 | [diff] [blame] | 1487 | ath9k_hw_rfbus_done(ah); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1488 | |
| 1489 | if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan)) |
| 1490 | ath9k_hw_set_delta_slope(ah, chan); |
| 1491 | |
Luis R. Rodriguez | 8fe6536 | 2010-04-15 17:38:14 -0400 | [diff] [blame] | 1492 | ath9k_hw_spur_mitigate_freq(ah, chan); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1493 | |
| 1494 | if (!chan->oneTimeCalsDone) |
| 1495 | chan->oneTimeCalsDone = true; |
| 1496 | |
| 1497 | return true; |
| 1498 | } |
| 1499 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 1500 | int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, |
Luis R. Rodriguez | ae8d285 | 2008-12-23 15:58:40 -0800 | [diff] [blame] | 1501 | bool bChannelChange) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1502 | { |
Luis R. Rodriguez | 1510718 | 2009-09-10 09:22:37 -0700 | [diff] [blame] | 1503 | struct ath_common *common = ath9k_hw_common(ah); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1504 | u32 saveLedState; |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1505 | struct ath9k_channel *curchan = ah->curchan; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1506 | u32 saveDefAntenna; |
| 1507 | u32 macStaId1; |
Sujith | 46fe782 | 2009-09-17 09:25:25 +0530 | [diff] [blame] | 1508 | u64 tsf = 0; |
Luis R. Rodriguez | 8fe6536 | 2010-04-15 17:38:14 -0400 | [diff] [blame] | 1509 | int i, r; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1510 | |
Luis R. Rodriguez | 43c2761 | 2009-09-13 21:07:07 -0700 | [diff] [blame] | 1511 | ah->txchainmask = common->tx_chainmask; |
| 1512 | ah->rxchainmask = common->rx_chainmask; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1513 | |
Luis R. Rodriguez | 9ecdef4 | 2009-09-09 21:10:09 -0700 | [diff] [blame] | 1514 | if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) |
Luis R. Rodriguez | ae8d285 | 2008-12-23 15:58:40 -0800 | [diff] [blame] | 1515 | return -EIO; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1516 | |
Vasanthakumar Thiagarajan | 9ebef799 | 2009-09-17 09:26:44 +0530 | [diff] [blame] | 1517 | if (curchan && !ah->chip_fullsleep) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1518 | ath9k_hw_getnf(ah, curchan); |
| 1519 | |
| 1520 | if (bChannelChange && |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1521 | (ah->chip_fullsleep != true) && |
| 1522 | (ah->curchan != NULL) && |
| 1523 | (chan->channel != ah->curchan->channel) && |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1524 | ((chan->channelFlags & CHANNEL_ALL) == |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1525 | (ah->curchan->channelFlags & CHANNEL_ALL)) && |
Vasanthakumar Thiagarajan | 0a475cc | 2009-09-17 09:27:10 +0530 | [diff] [blame] | 1526 | !(AR_SREV_9280(ah) || IS_CHAN_A_5MHZ_SPACED(chan) || |
| 1527 | IS_CHAN_A_5MHZ_SPACED(ah->curchan))) { |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1528 | |
Luis R. Rodriguez | 25c56ee | 2009-09-13 23:04:44 -0700 | [diff] [blame] | 1529 | if (ath9k_hw_channel_change(ah, chan)) { |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1530 | ath9k_hw_loadnf(ah, ah->curchan); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1531 | ath9k_hw_start_nfcal(ah); |
Luis R. Rodriguez | ae8d285 | 2008-12-23 15:58:40 -0800 | [diff] [blame] | 1532 | return 0; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1533 | } |
| 1534 | } |
| 1535 | |
| 1536 | saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA); |
| 1537 | if (saveDefAntenna == 0) |
| 1538 | saveDefAntenna = 1; |
| 1539 | |
| 1540 | macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B; |
| 1541 | |
Sujith | 46fe782 | 2009-09-17 09:25:25 +0530 | [diff] [blame] | 1542 | /* For chips on which RTC reset is done, save TSF before it gets cleared */ |
| 1543 | if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) |
| 1544 | tsf = ath9k_hw_gettsf64(ah); |
| 1545 | |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1546 | saveLedState = REG_READ(ah, AR_CFG_LED) & |
| 1547 | (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL | |
| 1548 | AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW); |
| 1549 | |
| 1550 | ath9k_hw_mark_phy_inactive(ah); |
| 1551 | |
Sujith | 05020d2 | 2010-03-17 14:25:23 +0530 | [diff] [blame] | 1552 | /* Only required on the first reset */ |
Luis R. Rodriguez | d7e7d22 | 2009-08-03 23:14:12 -0400 | [diff] [blame] | 1553 | if (AR_SREV_9271(ah) && ah->htc_reset_init) { |
| 1554 | REG_WRITE(ah, |
| 1555 | AR9271_RESET_POWER_DOWN_CONTROL, |
| 1556 | AR9271_RADIO_RF_RST); |
| 1557 | udelay(50); |
| 1558 | } |
| 1559 | |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1560 | if (!ath9k_hw_chip_reset(ah, chan)) { |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 1561 | ath_print(common, ATH_DBG_FATAL, "Chip reset failed\n"); |
Luis R. Rodriguez | ae8d285 | 2008-12-23 15:58:40 -0800 | [diff] [blame] | 1562 | return -EINVAL; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1563 | } |
| 1564 | |
Sujith | 05020d2 | 2010-03-17 14:25:23 +0530 | [diff] [blame] | 1565 | /* Only required on the first reset */ |
Luis R. Rodriguez | d7e7d22 | 2009-08-03 23:14:12 -0400 | [diff] [blame] | 1566 | if (AR_SREV_9271(ah) && ah->htc_reset_init) { |
| 1567 | ah->htc_reset_init = false; |
| 1568 | REG_WRITE(ah, |
| 1569 | AR9271_RESET_POWER_DOWN_CONTROL, |
| 1570 | AR9271_GATE_MAC_CTL); |
| 1571 | udelay(50); |
| 1572 | } |
| 1573 | |
Sujith | 46fe782 | 2009-09-17 09:25:25 +0530 | [diff] [blame] | 1574 | /* Restore TSF */ |
| 1575 | if (tsf && AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) |
| 1576 | ath9k_hw_settsf64(ah, tsf); |
| 1577 | |
Vasanthakumar Thiagarajan | 369391d | 2009-01-21 19:24:13 +0530 | [diff] [blame] | 1578 | if (AR_SREV_9280_10_OR_LATER(ah)) |
| 1579 | REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1580 | |
Luis R. Rodriguez | 25c56ee | 2009-09-13 23:04:44 -0700 | [diff] [blame] | 1581 | r = ath9k_hw_process_ini(ah, chan); |
Luis R. Rodriguez | ae8d285 | 2008-12-23 15:58:40 -0800 | [diff] [blame] | 1582 | if (r) |
| 1583 | return r; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1584 | |
Jouni Malinen | 0ced0e1 | 2009-01-08 13:32:13 +0200 | [diff] [blame] | 1585 | /* Setup MFP options for CCMP */ |
| 1586 | if (AR_SREV_9280_20_OR_LATER(ah)) { |
| 1587 | /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt |
| 1588 | * frames when constructing CCMP AAD. */ |
| 1589 | REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT, |
| 1590 | 0xc7ff); |
| 1591 | ah->sw_mgmt_crypto = false; |
| 1592 | } else if (AR_SREV_9160_10_OR_LATER(ah)) { |
| 1593 | /* Disable hardware crypto for management frames */ |
| 1594 | REG_CLR_BIT(ah, AR_PCU_MISC_MODE2, |
| 1595 | AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE); |
| 1596 | REG_SET_BIT(ah, AR_PCU_MISC_MODE2, |
| 1597 | AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT); |
| 1598 | ah->sw_mgmt_crypto = true; |
| 1599 | } else |
| 1600 | ah->sw_mgmt_crypto = true; |
| 1601 | |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1602 | if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan)) |
| 1603 | ath9k_hw_set_delta_slope(ah, chan); |
| 1604 | |
Luis R. Rodriguez | 8fe6536 | 2010-04-15 17:38:14 -0400 | [diff] [blame] | 1605 | ath9k_hw_spur_mitigate_freq(ah, chan); |
Sujith | d650915 | 2009-03-13 08:56:05 +0530 | [diff] [blame] | 1606 | ah->eep_ops->set_board_values(ah, chan); |
Luis R. Rodriguez | a776582 | 2009-10-19 02:33:45 -0400 | [diff] [blame] | 1607 | |
Luis R. Rodriguez | 1510718 | 2009-09-10 09:22:37 -0700 | [diff] [blame] | 1608 | REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr)); |
| 1609 | REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1610 | | macStaId1 |
| 1611 | | AR_STA_ID1_RTS_USE_DEF |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1612 | | (ah->config. |
Sujith | 60b67f5 | 2008-08-07 10:52:38 +0530 | [diff] [blame] | 1613 | ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0) |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1614 | | ah->sta_id1_defaults); |
| 1615 | ath9k_hw_set_operating_mode(ah, ah->opmode); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1616 | |
Luis R. Rodriguez | 13b8155 | 2009-09-10 17:52:45 -0700 | [diff] [blame] | 1617 | ath_hw_setbssidmask(common); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1618 | |
| 1619 | REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna); |
| 1620 | |
Luis R. Rodriguez | 3453ad8 | 2009-09-10 08:57:00 -0700 | [diff] [blame] | 1621 | ath9k_hw_write_associd(ah); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1622 | |
| 1623 | REG_WRITE(ah, AR_ISR, ~0); |
| 1624 | |
| 1625 | REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR); |
| 1626 | |
Luis R. Rodriguez | 8fe6536 | 2010-04-15 17:38:14 -0400 | [diff] [blame] | 1627 | r = ath9k_hw_rf_set_freq(ah, chan); |
Luis R. Rodriguez | 0a3b7ba | 2009-10-19 02:33:40 -0400 | [diff] [blame] | 1628 | if (r) |
| 1629 | return r; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1630 | |
| 1631 | for (i = 0; i < AR_NUM_DCU; i++) |
| 1632 | REG_WRITE(ah, AR_DQCUMASK(i), 1 << i); |
| 1633 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1634 | ah->intr_txqs = 0; |
| 1635 | for (i = 0; i < ah->caps.total_queues; i++) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1636 | ath9k_hw_resettxqueue(ah, i); |
| 1637 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1638 | ath9k_hw_init_interrupt_masks(ah, ah->opmode); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1639 | ath9k_hw_init_qos(ah); |
| 1640 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1641 | if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT) |
Vasanthakumar Thiagarajan | 500c064 | 2008-09-10 18:50:17 +0530 | [diff] [blame] | 1642 | ath9k_enable_rfkill(ah); |
Johannes Berg | 3b319aa | 2009-06-13 14:50:26 +0530 | [diff] [blame] | 1643 | |
Felix Fietkau | 0005baf | 2010-01-15 02:33:40 +0100 | [diff] [blame] | 1644 | ath9k_hw_init_global_settings(ah); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1645 | |
Vivek Natarajan | 326bebb | 2009-08-14 11:33:36 +0530 | [diff] [blame] | 1646 | if (AR_SREV_9287_12_OR_LATER(ah)) { |
Vivek Natarajan | ac88b6e | 2009-07-23 10:59:57 +0530 | [diff] [blame] | 1647 | REG_WRITE(ah, AR_D_GBL_IFS_SIFS, |
| 1648 | AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR); |
| 1649 | REG_WRITE(ah, AR_D_GBL_IFS_SLOT, |
| 1650 | AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR); |
| 1651 | REG_WRITE(ah, AR_D_GBL_IFS_EIFS, |
| 1652 | AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR); |
| 1653 | |
| 1654 | REG_WRITE(ah, AR_TIME_OUT, AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR); |
| 1655 | REG_WRITE(ah, AR_USEC, AR_USEC_ASYNC_FIFO_DUR); |
| 1656 | |
| 1657 | REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER, |
| 1658 | AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768); |
| 1659 | REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN, |
| 1660 | AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL); |
| 1661 | } |
Vivek Natarajan | 326bebb | 2009-08-14 11:33:36 +0530 | [diff] [blame] | 1662 | if (AR_SREV_9287_12_OR_LATER(ah)) { |
Vivek Natarajan | ac88b6e | 2009-07-23 10:59:57 +0530 | [diff] [blame] | 1663 | REG_SET_BIT(ah, AR_PCU_MISC_MODE2, |
| 1664 | AR_PCU_MISC_MODE2_ENABLE_AGGWEP); |
| 1665 | } |
| 1666 | |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1667 | REG_WRITE(ah, AR_STA_ID1, |
| 1668 | REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM); |
| 1669 | |
| 1670 | ath9k_hw_set_dma(ah); |
| 1671 | |
| 1672 | REG_WRITE(ah, AR_OBS, 8); |
| 1673 | |
Sujith | 0ce024c | 2009-12-14 14:57:00 +0530 | [diff] [blame] | 1674 | if (ah->config.rx_intr_mitigation) { |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1675 | REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500); |
| 1676 | REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000); |
| 1677 | } |
| 1678 | |
| 1679 | ath9k_hw_init_bb(ah, chan); |
| 1680 | |
Luis R. Rodriguez | ae8d285 | 2008-12-23 15:58:40 -0800 | [diff] [blame] | 1681 | if (!ath9k_hw_init_cal(ah, chan)) |
Joe Perches | 6badaaf | 2009-06-28 09:26:32 -0700 | [diff] [blame] | 1682 | return -EIO; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1683 | |
Luis R. Rodriguez | 8fe6536 | 2010-04-15 17:38:14 -0400 | [diff] [blame] | 1684 | ath9k_hw_restore_chainmask(ah); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1685 | REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ); |
| 1686 | |
Luis R. Rodriguez | d7e7d22 | 2009-08-03 23:14:12 -0400 | [diff] [blame] | 1687 | /* |
| 1688 | * For big endian systems turn on swapping for descriptors |
| 1689 | */ |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1690 | if (AR_SREV_9100(ah)) { |
| 1691 | u32 mask; |
| 1692 | mask = REG_READ(ah, AR_CFG); |
| 1693 | if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) { |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 1694 | ath_print(common, ATH_DBG_RESET, |
Sujith | 04bd463 | 2008-11-28 22:18:05 +0530 | [diff] [blame] | 1695 | "CFG Byte Swap Set 0x%x\n", mask); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1696 | } else { |
| 1697 | mask = |
| 1698 | INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB; |
| 1699 | REG_WRITE(ah, AR_CFG, mask); |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 1700 | ath_print(common, ATH_DBG_RESET, |
Sujith | 04bd463 | 2008-11-28 22:18:05 +0530 | [diff] [blame] | 1701 | "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG)); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1702 | } |
| 1703 | } else { |
Luis R. Rodriguez | d7e7d22 | 2009-08-03 23:14:12 -0400 | [diff] [blame] | 1704 | /* Configure AR9271 target WLAN */ |
| 1705 | if (AR_SREV_9271(ah)) |
| 1706 | REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1707 | #ifdef __BIG_ENDIAN |
Luis R. Rodriguez | d7e7d22 | 2009-08-03 23:14:12 -0400 | [diff] [blame] | 1708 | else |
| 1709 | REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1710 | #endif |
| 1711 | } |
| 1712 | |
Luis R. Rodriguez | 766ec4a | 2009-09-09 14:52:02 -0700 | [diff] [blame] | 1713 | if (ah->btcoex_hw.enabled) |
Vasanthakumar Thiagarajan | 42cc41e | 2009-08-26 21:08:45 +0530 | [diff] [blame] | 1714 | ath9k_hw_btcoex_enable(ah); |
| 1715 | |
Luis R. Rodriguez | ae8d285 | 2008-12-23 15:58:40 -0800 | [diff] [blame] | 1716 | return 0; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1717 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 1718 | EXPORT_SYMBOL(ath9k_hw_reset); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1719 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1720 | /************************/ |
| 1721 | /* Key Cache Management */ |
| 1722 | /************************/ |
| 1723 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 1724 | bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1725 | { |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1726 | u32 keyType; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1727 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1728 | if (entry >= ah->caps.keycache_size) { |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 1729 | ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL, |
| 1730 | "keychache entry %u out of range\n", entry); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1731 | return false; |
| 1732 | } |
| 1733 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1734 | keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry)); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1735 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1736 | REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0); |
| 1737 | REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0); |
| 1738 | REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0); |
| 1739 | REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0); |
| 1740 | REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0); |
| 1741 | REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR); |
| 1742 | REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0); |
| 1743 | REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0); |
| 1744 | |
| 1745 | if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) { |
| 1746 | u16 micentry = entry + 64; |
| 1747 | |
| 1748 | REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0); |
| 1749 | REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0); |
| 1750 | REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0); |
| 1751 | REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0); |
| 1752 | |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1753 | } |
| 1754 | |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1755 | return true; |
| 1756 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 1757 | EXPORT_SYMBOL(ath9k_hw_keyreset); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1758 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 1759 | bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1760 | { |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1761 | u32 macHi, macLo; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1762 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1763 | if (entry >= ah->caps.keycache_size) { |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 1764 | ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL, |
| 1765 | "keychache entry %u out of range\n", entry); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1766 | return false; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1767 | } |
| 1768 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1769 | if (mac != NULL) { |
| 1770 | macHi = (mac[5] << 8) | mac[4]; |
| 1771 | macLo = (mac[3] << 24) | |
| 1772 | (mac[2] << 16) | |
| 1773 | (mac[1] << 8) | |
| 1774 | mac[0]; |
| 1775 | macLo >>= 1; |
| 1776 | macLo |= (macHi & 1) << 31; |
| 1777 | macHi >>= 1; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1778 | } else { |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1779 | macLo = macHi = 0; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1780 | } |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1781 | REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo); |
| 1782 | REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1783 | |
| 1784 | return true; |
| 1785 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 1786 | EXPORT_SYMBOL(ath9k_hw_keysetmac); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1787 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 1788 | bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry, |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1789 | const struct ath9k_keyval *k, |
Jouni Malinen | e0caf9e | 2009-03-02 18:15:53 +0200 | [diff] [blame] | 1790 | const u8 *mac) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1791 | { |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1792 | const struct ath9k_hw_capabilities *pCap = &ah->caps; |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 1793 | struct ath_common *common = ath9k_hw_common(ah); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1794 | u32 key0, key1, key2, key3, key4; |
| 1795 | u32 keyType; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1796 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1797 | if (entry >= pCap->keycache_size) { |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 1798 | ath_print(common, ATH_DBG_FATAL, |
| 1799 | "keycache entry %u out of range\n", entry); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1800 | return false; |
| 1801 | } |
| 1802 | |
| 1803 | switch (k->kv_type) { |
| 1804 | case ATH9K_CIPHER_AES_OCB: |
| 1805 | keyType = AR_KEYTABLE_TYPE_AES; |
| 1806 | break; |
| 1807 | case ATH9K_CIPHER_AES_CCM: |
| 1808 | if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) { |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 1809 | ath_print(common, ATH_DBG_ANY, |
| 1810 | "AES-CCM not supported by mac rev 0x%x\n", |
| 1811 | ah->hw_version.macRev); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1812 | return false; |
| 1813 | } |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1814 | keyType = AR_KEYTABLE_TYPE_CCM; |
| 1815 | break; |
| 1816 | case ATH9K_CIPHER_TKIP: |
| 1817 | keyType = AR_KEYTABLE_TYPE_TKIP; |
| 1818 | if (ATH9K_IS_MIC_ENABLED(ah) |
| 1819 | && entry + 64 >= pCap->keycache_size) { |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 1820 | ath_print(common, ATH_DBG_ANY, |
| 1821 | "entry %u inappropriate for TKIP\n", entry); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1822 | return false; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1823 | } |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1824 | break; |
| 1825 | case ATH9K_CIPHER_WEP: |
Zhu Yi | e31a16d | 2009-05-21 21:47:03 +0800 | [diff] [blame] | 1826 | if (k->kv_len < WLAN_KEY_LEN_WEP40) { |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 1827 | ath_print(common, ATH_DBG_ANY, |
| 1828 | "WEP key length %u too small\n", k->kv_len); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1829 | return false; |
| 1830 | } |
Zhu Yi | e31a16d | 2009-05-21 21:47:03 +0800 | [diff] [blame] | 1831 | if (k->kv_len <= WLAN_KEY_LEN_WEP40) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1832 | keyType = AR_KEYTABLE_TYPE_40; |
Zhu Yi | e31a16d | 2009-05-21 21:47:03 +0800 | [diff] [blame] | 1833 | else if (k->kv_len <= WLAN_KEY_LEN_WEP104) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1834 | keyType = AR_KEYTABLE_TYPE_104; |
| 1835 | else |
| 1836 | keyType = AR_KEYTABLE_TYPE_128; |
| 1837 | break; |
| 1838 | case ATH9K_CIPHER_CLR: |
| 1839 | keyType = AR_KEYTABLE_TYPE_CLR; |
| 1840 | break; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1841 | default: |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 1842 | ath_print(common, ATH_DBG_FATAL, |
| 1843 | "cipher %u not supported\n", k->kv_type); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1844 | return false; |
| 1845 | } |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1846 | |
Jouni Malinen | e0caf9e | 2009-03-02 18:15:53 +0200 | [diff] [blame] | 1847 | key0 = get_unaligned_le32(k->kv_val + 0); |
| 1848 | key1 = get_unaligned_le16(k->kv_val + 4); |
| 1849 | key2 = get_unaligned_le32(k->kv_val + 6); |
| 1850 | key3 = get_unaligned_le16(k->kv_val + 10); |
| 1851 | key4 = get_unaligned_le32(k->kv_val + 12); |
Zhu Yi | e31a16d | 2009-05-21 21:47:03 +0800 | [diff] [blame] | 1852 | if (k->kv_len <= WLAN_KEY_LEN_WEP104) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1853 | key4 &= 0xff; |
| 1854 | |
Jouni Malinen | 672903b | 2009-03-02 15:06:31 +0200 | [diff] [blame] | 1855 | /* |
| 1856 | * Note: Key cache registers access special memory area that requires |
| 1857 | * two 32-bit writes to actually update the values in the internal |
| 1858 | * memory. Consequently, the exact order and pairs used here must be |
| 1859 | * maintained. |
| 1860 | */ |
| 1861 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1862 | if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) { |
| 1863 | u16 micentry = entry + 64; |
| 1864 | |
Jouni Malinen | 672903b | 2009-03-02 15:06:31 +0200 | [diff] [blame] | 1865 | /* |
| 1866 | * Write inverted key[47:0] first to avoid Michael MIC errors |
| 1867 | * on frames that could be sent or received at the same time. |
| 1868 | * The correct key will be written in the end once everything |
| 1869 | * else is ready. |
| 1870 | */ |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1871 | REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0); |
| 1872 | REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1); |
Jouni Malinen | 672903b | 2009-03-02 15:06:31 +0200 | [diff] [blame] | 1873 | |
| 1874 | /* Write key[95:48] */ |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1875 | REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2); |
| 1876 | REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3); |
Jouni Malinen | 672903b | 2009-03-02 15:06:31 +0200 | [diff] [blame] | 1877 | |
| 1878 | /* Write key[127:96] and key type */ |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1879 | REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4); |
| 1880 | REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType); |
Jouni Malinen | 672903b | 2009-03-02 15:06:31 +0200 | [diff] [blame] | 1881 | |
| 1882 | /* Write MAC address for the entry */ |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1883 | (void) ath9k_hw_keysetmac(ah, entry, mac); |
| 1884 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1885 | if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) { |
Jouni Malinen | 672903b | 2009-03-02 15:06:31 +0200 | [diff] [blame] | 1886 | /* |
| 1887 | * TKIP uses two key cache entries: |
| 1888 | * Michael MIC TX/RX keys in the same key cache entry |
| 1889 | * (idx = main index + 64): |
| 1890 | * key0 [31:0] = RX key [31:0] |
| 1891 | * key1 [15:0] = TX key [31:16] |
| 1892 | * key1 [31:16] = reserved |
| 1893 | * key2 [31:0] = RX key [63:32] |
| 1894 | * key3 [15:0] = TX key [15:0] |
| 1895 | * key3 [31:16] = reserved |
| 1896 | * key4 [31:0] = TX key [63:32] |
| 1897 | */ |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1898 | u32 mic0, mic1, mic2, mic3, mic4; |
| 1899 | |
| 1900 | mic0 = get_unaligned_le32(k->kv_mic + 0); |
| 1901 | mic2 = get_unaligned_le32(k->kv_mic + 4); |
| 1902 | mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff; |
| 1903 | mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff; |
| 1904 | mic4 = get_unaligned_le32(k->kv_txmic + 4); |
Jouni Malinen | 672903b | 2009-03-02 15:06:31 +0200 | [diff] [blame] | 1905 | |
| 1906 | /* Write RX[31:0] and TX[31:16] */ |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1907 | REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0); |
| 1908 | REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1); |
Jouni Malinen | 672903b | 2009-03-02 15:06:31 +0200 | [diff] [blame] | 1909 | |
| 1910 | /* Write RX[63:32] and TX[15:0] */ |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1911 | REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2); |
| 1912 | REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3); |
Jouni Malinen | 672903b | 2009-03-02 15:06:31 +0200 | [diff] [blame] | 1913 | |
| 1914 | /* Write TX[63:32] and keyType(reserved) */ |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1915 | REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4); |
| 1916 | REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry), |
| 1917 | AR_KEYTABLE_TYPE_CLR); |
| 1918 | |
| 1919 | } else { |
Jouni Malinen | 672903b | 2009-03-02 15:06:31 +0200 | [diff] [blame] | 1920 | /* |
| 1921 | * TKIP uses four key cache entries (two for group |
| 1922 | * keys): |
| 1923 | * Michael MIC TX/RX keys are in different key cache |
| 1924 | * entries (idx = main index + 64 for TX and |
| 1925 | * main index + 32 + 96 for RX): |
| 1926 | * key0 [31:0] = TX/RX MIC key [31:0] |
| 1927 | * key1 [31:0] = reserved |
| 1928 | * key2 [31:0] = TX/RX MIC key [63:32] |
| 1929 | * key3 [31:0] = reserved |
| 1930 | * key4 [31:0] = reserved |
| 1931 | * |
| 1932 | * Upper layer code will call this function separately |
| 1933 | * for TX and RX keys when these registers offsets are |
| 1934 | * used. |
| 1935 | */ |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1936 | u32 mic0, mic2; |
| 1937 | |
| 1938 | mic0 = get_unaligned_le32(k->kv_mic + 0); |
| 1939 | mic2 = get_unaligned_le32(k->kv_mic + 4); |
Jouni Malinen | 672903b | 2009-03-02 15:06:31 +0200 | [diff] [blame] | 1940 | |
| 1941 | /* Write MIC key[31:0] */ |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1942 | REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0); |
| 1943 | REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0); |
Jouni Malinen | 672903b | 2009-03-02 15:06:31 +0200 | [diff] [blame] | 1944 | |
| 1945 | /* Write MIC key[63:32] */ |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1946 | REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2); |
| 1947 | REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0); |
Jouni Malinen | 672903b | 2009-03-02 15:06:31 +0200 | [diff] [blame] | 1948 | |
| 1949 | /* Write TX[63:32] and keyType(reserved) */ |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1950 | REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0); |
| 1951 | REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry), |
| 1952 | AR_KEYTABLE_TYPE_CLR); |
| 1953 | } |
Jouni Malinen | 672903b | 2009-03-02 15:06:31 +0200 | [diff] [blame] | 1954 | |
| 1955 | /* MAC address registers are reserved for the MIC entry */ |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1956 | REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0); |
| 1957 | REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0); |
Jouni Malinen | 672903b | 2009-03-02 15:06:31 +0200 | [diff] [blame] | 1958 | |
| 1959 | /* |
| 1960 | * Write the correct (un-inverted) key[47:0] last to enable |
| 1961 | * TKIP now that all other registers are set with correct |
| 1962 | * values. |
| 1963 | */ |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1964 | REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0); |
| 1965 | REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1); |
| 1966 | } else { |
Jouni Malinen | 672903b | 2009-03-02 15:06:31 +0200 | [diff] [blame] | 1967 | /* Write key[47:0] */ |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1968 | REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0); |
| 1969 | REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1); |
Jouni Malinen | 672903b | 2009-03-02 15:06:31 +0200 | [diff] [blame] | 1970 | |
| 1971 | /* Write key[95:48] */ |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1972 | REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2); |
| 1973 | REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3); |
Jouni Malinen | 672903b | 2009-03-02 15:06:31 +0200 | [diff] [blame] | 1974 | |
| 1975 | /* Write key[127:96] and key type */ |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1976 | REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4); |
| 1977 | REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType); |
| 1978 | |
Jouni Malinen | 672903b | 2009-03-02 15:06:31 +0200 | [diff] [blame] | 1979 | /* Write MAC address for the entry */ |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1980 | (void) ath9k_hw_keysetmac(ah, entry, mac); |
| 1981 | } |
| 1982 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1983 | return true; |
| 1984 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 1985 | EXPORT_SYMBOL(ath9k_hw_set_keycache_entry); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1986 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 1987 | bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1988 | { |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1989 | if (entry < ah->caps.keycache_size) { |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1990 | u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry)); |
| 1991 | if (val & AR_KEYTABLE_VALID) |
| 1992 | return true; |
| 1993 | } |
| 1994 | return false; |
| 1995 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 1996 | EXPORT_SYMBOL(ath9k_hw_keyisvalid); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1997 | |
| 1998 | /******************************/ |
| 1999 | /* Power Management (Chipset) */ |
| 2000 | /******************************/ |
| 2001 | |
Luis R. Rodriguez | 42d5bc3 | 2010-04-15 17:38:12 -0400 | [diff] [blame] | 2002 | /* |
| 2003 | * Notify Power Mgt is disabled in self-generated frames. |
| 2004 | * If requested, force chip to sleep. |
| 2005 | */ |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 2006 | static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2007 | { |
| 2008 | REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); |
| 2009 | if (setChip) { |
Luis R. Rodriguez | 42d5bc3 | 2010-04-15 17:38:12 -0400 | [diff] [blame] | 2010 | /* |
| 2011 | * Clear the RTC force wake bit to allow the |
| 2012 | * mac to go to sleep. |
| 2013 | */ |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2014 | REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, |
| 2015 | AR_RTC_FORCE_WAKE_EN); |
Luis R. Rodriguez | 42d5bc3 | 2010-04-15 17:38:12 -0400 | [diff] [blame] | 2016 | if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2017 | REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF); |
| 2018 | |
Luis R. Rodriguez | 42d5bc3 | 2010-04-15 17:38:12 -0400 | [diff] [blame] | 2019 | /* Shutdown chip. Active low */ |
Sujith | 14b3af3 | 2010-03-17 14:25:18 +0530 | [diff] [blame] | 2020 | if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah)) |
Sujith | 4921be8 | 2009-09-18 15:04:27 +0530 | [diff] [blame] | 2021 | REG_CLR_BIT(ah, (AR_RTC_RESET), |
| 2022 | AR_RTC_RESET_EN); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2023 | } |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2024 | } |
| 2025 | |
Luis R. Rodriguez | bbd79af | 2010-04-15 17:38:16 -0400 | [diff] [blame] | 2026 | /* |
| 2027 | * Notify Power Management is enabled in self-generating |
| 2028 | * frames. If request, set power mode of chip to |
| 2029 | * auto/normal. Duration in units of 128us (1/8 TU). |
| 2030 | */ |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 2031 | static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2032 | { |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2033 | REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); |
| 2034 | if (setChip) { |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 2035 | struct ath9k_hw_capabilities *pCap = &ah->caps; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2036 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2037 | if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { |
Luis R. Rodriguez | bbd79af | 2010-04-15 17:38:16 -0400 | [diff] [blame] | 2038 | /* Set WakeOnInterrupt bit; clear ForceWake bit */ |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2039 | REG_WRITE(ah, AR_RTC_FORCE_WAKE, |
| 2040 | AR_RTC_FORCE_WAKE_ON_INT); |
| 2041 | } else { |
Luis R. Rodriguez | bbd79af | 2010-04-15 17:38:16 -0400 | [diff] [blame] | 2042 | /* |
| 2043 | * Clear the RTC force wake bit to allow the |
| 2044 | * mac to go to sleep. |
| 2045 | */ |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2046 | REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, |
| 2047 | AR_RTC_FORCE_WAKE_EN); |
| 2048 | } |
| 2049 | } |
| 2050 | } |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2051 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 2052 | static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2053 | { |
| 2054 | u32 val; |
| 2055 | int i; |
| 2056 | |
| 2057 | if (setChip) { |
| 2058 | if ((REG_READ(ah, AR_RTC_STATUS) & |
| 2059 | AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) { |
| 2060 | if (ath9k_hw_set_reset_reg(ah, |
| 2061 | ATH9K_RESET_POWER_ON) != true) { |
| 2062 | return false; |
| 2063 | } |
Luis R. Rodriguez | e041228 | 2010-04-15 17:38:15 -0400 | [diff] [blame] | 2064 | if (!AR_SREV_9300_20_OR_LATER(ah)) |
| 2065 | ath9k_hw_init_pll(ah, NULL); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2066 | } |
| 2067 | if (AR_SREV_9100(ah)) |
| 2068 | REG_SET_BIT(ah, AR_RTC_RESET, |
| 2069 | AR_RTC_RESET_EN); |
| 2070 | |
| 2071 | REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, |
| 2072 | AR_RTC_FORCE_WAKE_EN); |
| 2073 | udelay(50); |
| 2074 | |
| 2075 | for (i = POWER_UP_TIME / 50; i > 0; i--) { |
| 2076 | val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M; |
| 2077 | if (val == AR_RTC_STATUS_ON) |
| 2078 | break; |
| 2079 | udelay(50); |
| 2080 | REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, |
| 2081 | AR_RTC_FORCE_WAKE_EN); |
| 2082 | } |
| 2083 | if (i == 0) { |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 2084 | ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL, |
| 2085 | "Failed to wakeup in %uus\n", |
| 2086 | POWER_UP_TIME / 20); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2087 | return false; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2088 | } |
| 2089 | } |
| 2090 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2091 | REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); |
| 2092 | |
| 2093 | return true; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2094 | } |
| 2095 | |
Luis R. Rodriguez | 9ecdef4 | 2009-09-09 21:10:09 -0700 | [diff] [blame] | 2096 | bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2097 | { |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 2098 | struct ath_common *common = ath9k_hw_common(ah); |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 2099 | int status = true, setChip = true; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2100 | static const char *modes[] = { |
| 2101 | "AWAKE", |
| 2102 | "FULL-SLEEP", |
| 2103 | "NETWORK SLEEP", |
| 2104 | "UNDEFINED" |
| 2105 | }; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2106 | |
Gabor Juhos | cbdec97 | 2009-07-24 17:27:22 +0200 | [diff] [blame] | 2107 | if (ah->power_mode == mode) |
| 2108 | return status; |
| 2109 | |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 2110 | ath_print(common, ATH_DBG_RESET, "%s -> %s\n", |
| 2111 | modes[ah->power_mode], modes[mode]); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2112 | |
| 2113 | switch (mode) { |
| 2114 | case ATH9K_PM_AWAKE: |
| 2115 | status = ath9k_hw_set_power_awake(ah, setChip); |
| 2116 | break; |
| 2117 | case ATH9K_PM_FULL_SLEEP: |
| 2118 | ath9k_set_power_sleep(ah, setChip); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 2119 | ah->chip_fullsleep = true; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2120 | break; |
| 2121 | case ATH9K_PM_NETWORK_SLEEP: |
| 2122 | ath9k_set_power_network_sleep(ah, setChip); |
| 2123 | break; |
| 2124 | default: |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 2125 | ath_print(common, ATH_DBG_FATAL, |
| 2126 | "Unknown power mode %u\n", mode); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2127 | return false; |
| 2128 | } |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 2129 | ah->power_mode = mode; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2130 | |
| 2131 | return status; |
| 2132 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 2133 | EXPORT_SYMBOL(ath9k_hw_setpower); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2134 | |
Luis R. Rodriguez | 24c1a28 | 2009-02-10 15:35:22 -0800 | [diff] [blame] | 2135 | /* |
| 2136 | * Helper for ASPM support. |
| 2137 | * |
| 2138 | * Disable PLL when in L0s as well as receiver clock when in L1. |
| 2139 | * This power saving option must be enabled through the SerDes. |
| 2140 | * |
| 2141 | * Programming the SerDes must go through the same 288 bit serial shift |
| 2142 | * register as the other analog registers. Hence the 9 writes. |
| 2143 | */ |
Luis R. Rodriguez | d70357d | 2010-04-15 17:38:06 -0400 | [diff] [blame] | 2144 | static void ar9002_hw_configpcipowersave(struct ath_hw *ah, |
| 2145 | int restore, |
| 2146 | int power_off) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2147 | { |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2148 | u8 i; |
Vivek Natarajan | 93b1b37 | 2009-09-17 09:24:58 +0530 | [diff] [blame] | 2149 | u32 val; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2150 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 2151 | if (ah->is_pciexpress != true) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2152 | return; |
| 2153 | |
Luis R. Rodriguez | 24c1a28 | 2009-02-10 15:35:22 -0800 | [diff] [blame] | 2154 | /* Do not touch SerDes registers */ |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 2155 | if (ah->config.pcie_powersave_enable == 2) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2156 | return; |
| 2157 | |
Luis R. Rodriguez | 24c1a28 | 2009-02-10 15:35:22 -0800 | [diff] [blame] | 2158 | /* Nothing to do on restore for 11N */ |
Vivek Natarajan | 93b1b37 | 2009-09-17 09:24:58 +0530 | [diff] [blame] | 2159 | if (!restore) { |
| 2160 | if (AR_SREV_9280_20_OR_LATER(ah)) { |
| 2161 | /* |
| 2162 | * AR9280 2.0 or later chips use SerDes values from the |
| 2163 | * initvals.h initialized depending on chipset during |
Luis R. Rodriguez | d70357d | 2010-04-15 17:38:06 -0400 | [diff] [blame] | 2164 | * __ath9k_hw_init() |
Vivek Natarajan | 93b1b37 | 2009-09-17 09:24:58 +0530 | [diff] [blame] | 2165 | */ |
| 2166 | for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) { |
| 2167 | REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0), |
| 2168 | INI_RA(&ah->iniPcieSerdes, i, 1)); |
| 2169 | } |
| 2170 | } else if (AR_SREV_9280(ah) && |
| 2171 | (ah->hw_version.macRev == AR_SREV_REVISION_9280_10)) { |
| 2172 | REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00); |
| 2173 | REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2174 | |
Vivek Natarajan | 93b1b37 | 2009-09-17 09:24:58 +0530 | [diff] [blame] | 2175 | /* RX shut off when elecidle is asserted */ |
| 2176 | REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019); |
| 2177 | REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820); |
| 2178 | REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560); |
| 2179 | |
| 2180 | /* Shut off CLKREQ active in L1 */ |
| 2181 | if (ah->config.pcie_clock_req) |
| 2182 | REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc); |
| 2183 | else |
| 2184 | REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd); |
| 2185 | |
| 2186 | REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); |
| 2187 | REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); |
| 2188 | REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007); |
| 2189 | |
| 2190 | /* Load the new settings */ |
| 2191 | REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); |
| 2192 | |
| 2193 | } else { |
| 2194 | REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); |
| 2195 | REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); |
| 2196 | |
| 2197 | /* RX shut off when elecidle is asserted */ |
| 2198 | REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039); |
| 2199 | REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824); |
| 2200 | REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579); |
| 2201 | |
| 2202 | /* |
| 2203 | * Ignore ah->ah_config.pcie_clock_req setting for |
| 2204 | * pre-AR9280 11n |
| 2205 | */ |
| 2206 | REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff); |
| 2207 | |
| 2208 | REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); |
| 2209 | REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); |
| 2210 | REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007); |
| 2211 | |
| 2212 | /* Load the new settings */ |
| 2213 | REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2214 | } |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2215 | |
Vivek Natarajan | 93b1b37 | 2009-09-17 09:24:58 +0530 | [diff] [blame] | 2216 | udelay(1000); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2217 | |
Vivek Natarajan | 93b1b37 | 2009-09-17 09:24:58 +0530 | [diff] [blame] | 2218 | /* set bit 19 to allow forcing of pcie core into L1 state */ |
| 2219 | REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2220 | |
Vivek Natarajan | 93b1b37 | 2009-09-17 09:24:58 +0530 | [diff] [blame] | 2221 | /* Several PCIe massages to ensure proper behaviour */ |
| 2222 | if (ah->config.pcie_waen) { |
| 2223 | val = ah->config.pcie_waen; |
| 2224 | if (!power_off) |
| 2225 | val &= (~AR_WA_D3_L1_DISABLE); |
| 2226 | } else { |
| 2227 | if (AR_SREV_9285(ah) || AR_SREV_9271(ah) || |
| 2228 | AR_SREV_9287(ah)) { |
| 2229 | val = AR9285_WA_DEFAULT; |
| 2230 | if (!power_off) |
| 2231 | val &= (~AR_WA_D3_L1_DISABLE); |
| 2232 | } else if (AR_SREV_9280(ah)) { |
| 2233 | /* |
| 2234 | * On AR9280 chips bit 22 of 0x4004 needs to be |
| 2235 | * set otherwise card may disappear. |
| 2236 | */ |
| 2237 | val = AR9280_WA_DEFAULT; |
| 2238 | if (!power_off) |
| 2239 | val &= (~AR_WA_D3_L1_DISABLE); |
| 2240 | } else |
| 2241 | val = AR_WA_DEFAULT; |
| 2242 | } |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2243 | |
Vivek Natarajan | 93b1b37 | 2009-09-17 09:24:58 +0530 | [diff] [blame] | 2244 | REG_WRITE(ah, AR_WA, val); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2245 | } |
| 2246 | |
Vivek Natarajan | 93b1b37 | 2009-09-17 09:24:58 +0530 | [diff] [blame] | 2247 | if (power_off) { |
Luis R. Rodriguez | 24c1a28 | 2009-02-10 15:35:22 -0800 | [diff] [blame] | 2248 | /* |
Vivek Natarajan | 93b1b37 | 2009-09-17 09:24:58 +0530 | [diff] [blame] | 2249 | * Set PCIe workaround bits |
| 2250 | * bit 14 in WA register (disable L1) should only |
| 2251 | * be set when device enters D3 and be cleared |
| 2252 | * when device comes back to D0. |
Luis R. Rodriguez | 24c1a28 | 2009-02-10 15:35:22 -0800 | [diff] [blame] | 2253 | */ |
Vivek Natarajan | 93b1b37 | 2009-09-17 09:24:58 +0530 | [diff] [blame] | 2254 | if (ah->config.pcie_waen) { |
| 2255 | if (ah->config.pcie_waen & AR_WA_D3_L1_DISABLE) |
| 2256 | REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE); |
| 2257 | } else { |
| 2258 | if (((AR_SREV_9285(ah) || AR_SREV_9271(ah) || |
| 2259 | AR_SREV_9287(ah)) && |
| 2260 | (AR9285_WA_DEFAULT & AR_WA_D3_L1_DISABLE)) || |
| 2261 | (AR_SREV_9280(ah) && |
| 2262 | (AR9280_WA_DEFAULT & AR_WA_D3_L1_DISABLE))) { |
| 2263 | REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE); |
| 2264 | } |
| 2265 | } |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2266 | } |
| 2267 | } |
| 2268 | |
| 2269 | /**********************/ |
| 2270 | /* Interrupt Handling */ |
| 2271 | /**********************/ |
| 2272 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 2273 | bool ath9k_hw_intrpend(struct ath_hw *ah) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2274 | { |
| 2275 | u32 host_isr; |
| 2276 | |
| 2277 | if (AR_SREV_9100(ah)) |
| 2278 | return true; |
| 2279 | |
| 2280 | host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE); |
| 2281 | if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS)) |
| 2282 | return true; |
| 2283 | |
| 2284 | host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE); |
| 2285 | if ((host_isr & AR_INTR_SYNC_DEFAULT) |
| 2286 | && (host_isr != AR_INTR_SPURIOUS)) |
| 2287 | return true; |
| 2288 | |
| 2289 | return false; |
| 2290 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 2291 | EXPORT_SYMBOL(ath9k_hw_intrpend); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2292 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 2293 | bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2294 | { |
| 2295 | u32 isr = 0; |
| 2296 | u32 mask2 = 0; |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 2297 | struct ath9k_hw_capabilities *pCap = &ah->caps; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2298 | u32 sync_cause = 0; |
| 2299 | bool fatal_int = false; |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 2300 | struct ath_common *common = ath9k_hw_common(ah); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2301 | |
| 2302 | if (!AR_SREV_9100(ah)) { |
| 2303 | if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) { |
| 2304 | if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M) |
| 2305 | == AR_RTC_STATUS_ON) { |
| 2306 | isr = REG_READ(ah, AR_ISR); |
| 2307 | } |
| 2308 | } |
| 2309 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2310 | sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) & |
| 2311 | AR_INTR_SYNC_DEFAULT; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2312 | |
| 2313 | *masked = 0; |
| 2314 | |
| 2315 | if (!isr && !sync_cause) |
| 2316 | return false; |
| 2317 | } else { |
| 2318 | *masked = 0; |
| 2319 | isr = REG_READ(ah, AR_ISR); |
| 2320 | } |
| 2321 | |
| 2322 | if (isr) { |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2323 | if (isr & AR_ISR_BCNMISC) { |
| 2324 | u32 isr2; |
| 2325 | isr2 = REG_READ(ah, AR_ISR_S2); |
| 2326 | if (isr2 & AR_ISR_S2_TIM) |
| 2327 | mask2 |= ATH9K_INT_TIM; |
| 2328 | if (isr2 & AR_ISR_S2_DTIM) |
| 2329 | mask2 |= ATH9K_INT_DTIM; |
| 2330 | if (isr2 & AR_ISR_S2_DTIMSYNC) |
| 2331 | mask2 |= ATH9K_INT_DTIMSYNC; |
| 2332 | if (isr2 & (AR_ISR_S2_CABEND)) |
| 2333 | mask2 |= ATH9K_INT_CABEND; |
| 2334 | if (isr2 & AR_ISR_S2_GTT) |
| 2335 | mask2 |= ATH9K_INT_GTT; |
| 2336 | if (isr2 & AR_ISR_S2_CST) |
| 2337 | mask2 |= ATH9K_INT_CST; |
Sujith | 4af9cf4 | 2009-02-12 10:06:47 +0530 | [diff] [blame] | 2338 | if (isr2 & AR_ISR_S2_TSFOOR) |
| 2339 | mask2 |= ATH9K_INT_TSFOOR; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2340 | } |
| 2341 | |
| 2342 | isr = REG_READ(ah, AR_ISR_RAC); |
| 2343 | if (isr == 0xffffffff) { |
| 2344 | *masked = 0; |
| 2345 | return false; |
| 2346 | } |
| 2347 | |
| 2348 | *masked = isr & ATH9K_INT_COMMON; |
| 2349 | |
Sujith | 0ce024c | 2009-12-14 14:57:00 +0530 | [diff] [blame] | 2350 | if (ah->config.rx_intr_mitigation) { |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2351 | if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM)) |
| 2352 | *masked |= ATH9K_INT_RX; |
| 2353 | } |
| 2354 | |
| 2355 | if (isr & (AR_ISR_RXOK | AR_ISR_RXERR)) |
| 2356 | *masked |= ATH9K_INT_RX; |
| 2357 | if (isr & |
| 2358 | (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR | |
| 2359 | AR_ISR_TXEOL)) { |
| 2360 | u32 s0_s, s1_s; |
| 2361 | |
| 2362 | *masked |= ATH9K_INT_TX; |
| 2363 | |
| 2364 | s0_s = REG_READ(ah, AR_ISR_S0_S); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 2365 | ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK); |
| 2366 | ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2367 | |
| 2368 | s1_s = REG_READ(ah, AR_ISR_S1_S); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 2369 | ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR); |
| 2370 | ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2371 | } |
| 2372 | |
| 2373 | if (isr & AR_ISR_RXORN) { |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 2374 | ath_print(common, ATH_DBG_INTERRUPT, |
| 2375 | "receive FIFO overrun interrupt\n"); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2376 | } |
| 2377 | |
| 2378 | if (!AR_SREV_9100(ah)) { |
Sujith | 60b67f5 | 2008-08-07 10:52:38 +0530 | [diff] [blame] | 2379 | if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2380 | u32 isr5 = REG_READ(ah, AR_ISR_S5_S); |
| 2381 | if (isr5 & AR_ISR_S5_TIM_TIMER) |
| 2382 | *masked |= ATH9K_INT_TIM_TIMER; |
| 2383 | } |
| 2384 | } |
| 2385 | |
| 2386 | *masked |= mask2; |
| 2387 | } |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2388 | |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2389 | if (AR_SREV_9100(ah)) |
| 2390 | return true; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2391 | |
Vasanthakumar Thiagarajan | ff155a4 | 2009-08-26 21:08:49 +0530 | [diff] [blame] | 2392 | if (isr & AR_ISR_GENTMR) { |
| 2393 | u32 s5_s; |
| 2394 | |
| 2395 | s5_s = REG_READ(ah, AR_ISR_S5_S); |
| 2396 | if (isr & AR_ISR_GENTMR) { |
| 2397 | ah->intr_gen_timer_trigger = |
| 2398 | MS(s5_s, AR_ISR_S5_GENTIMER_TRIG); |
| 2399 | |
| 2400 | ah->intr_gen_timer_thresh = |
| 2401 | MS(s5_s, AR_ISR_S5_GENTIMER_THRESH); |
| 2402 | |
| 2403 | if (ah->intr_gen_timer_trigger) |
| 2404 | *masked |= ATH9K_INT_GENTIMER; |
| 2405 | |
| 2406 | } |
| 2407 | } |
| 2408 | |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2409 | if (sync_cause) { |
| 2410 | fatal_int = |
| 2411 | (sync_cause & |
| 2412 | (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR)) |
| 2413 | ? true : false; |
| 2414 | |
| 2415 | if (fatal_int) { |
| 2416 | if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) { |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 2417 | ath_print(common, ATH_DBG_ANY, |
| 2418 | "received PCI FATAL interrupt\n"); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2419 | } |
| 2420 | if (sync_cause & AR_INTR_SYNC_HOST1_PERR) { |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 2421 | ath_print(common, ATH_DBG_ANY, |
| 2422 | "received PCI PERR interrupt\n"); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2423 | } |
Steven Luo | a89bff9 | 2009-04-12 02:57:54 -0700 | [diff] [blame] | 2424 | *masked |= ATH9K_INT_FATAL; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2425 | } |
| 2426 | if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) { |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 2427 | ath_print(common, ATH_DBG_INTERRUPT, |
| 2428 | "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n"); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2429 | REG_WRITE(ah, AR_RC, AR_RC_HOSTIF); |
| 2430 | REG_WRITE(ah, AR_RC, 0); |
| 2431 | *masked |= ATH9K_INT_FATAL; |
| 2432 | } |
| 2433 | if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) { |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 2434 | ath_print(common, ATH_DBG_INTERRUPT, |
| 2435 | "AR_INTR_SYNC_LOCAL_TIMEOUT\n"); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2436 | } |
| 2437 | |
| 2438 | REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause); |
| 2439 | (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR); |
| 2440 | } |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2441 | |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2442 | return true; |
| 2443 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 2444 | EXPORT_SYMBOL(ath9k_hw_getisr); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2445 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 2446 | enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2447 | { |
Pavel Roskin | 152d530 | 2010-03-31 18:05:37 -0400 | [diff] [blame] | 2448 | enum ath9k_int omask = ah->imask; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2449 | u32 mask, mask2; |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 2450 | struct ath9k_hw_capabilities *pCap = &ah->caps; |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 2451 | struct ath_common *common = ath9k_hw_common(ah); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2452 | |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 2453 | ath_print(common, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2454 | |
| 2455 | if (omask & ATH9K_INT_GLOBAL) { |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 2456 | ath_print(common, ATH_DBG_INTERRUPT, "disable IER\n"); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2457 | REG_WRITE(ah, AR_IER, AR_IER_DISABLE); |
| 2458 | (void) REG_READ(ah, AR_IER); |
| 2459 | if (!AR_SREV_9100(ah)) { |
| 2460 | REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0); |
| 2461 | (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE); |
| 2462 | |
| 2463 | REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0); |
| 2464 | (void) REG_READ(ah, AR_INTR_SYNC_ENABLE); |
| 2465 | } |
| 2466 | } |
| 2467 | |
| 2468 | mask = ints & ATH9K_INT_COMMON; |
| 2469 | mask2 = 0; |
| 2470 | |
| 2471 | if (ints & ATH9K_INT_TX) { |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 2472 | if (ah->txok_interrupt_mask) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2473 | mask |= AR_IMR_TXOK; |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 2474 | if (ah->txdesc_interrupt_mask) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2475 | mask |= AR_IMR_TXDESC; |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 2476 | if (ah->txerr_interrupt_mask) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2477 | mask |= AR_IMR_TXERR; |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 2478 | if (ah->txeol_interrupt_mask) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2479 | mask |= AR_IMR_TXEOL; |
| 2480 | } |
| 2481 | if (ints & ATH9K_INT_RX) { |
| 2482 | mask |= AR_IMR_RXERR; |
Sujith | 0ce024c | 2009-12-14 14:57:00 +0530 | [diff] [blame] | 2483 | if (ah->config.rx_intr_mitigation) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2484 | mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM; |
| 2485 | else |
| 2486 | mask |= AR_IMR_RXOK | AR_IMR_RXDESC; |
Sujith | 60b67f5 | 2008-08-07 10:52:38 +0530 | [diff] [blame] | 2487 | if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2488 | mask |= AR_IMR_GENTMR; |
| 2489 | } |
| 2490 | |
| 2491 | if (ints & (ATH9K_INT_BMISC)) { |
| 2492 | mask |= AR_IMR_BCNMISC; |
| 2493 | if (ints & ATH9K_INT_TIM) |
| 2494 | mask2 |= AR_IMR_S2_TIM; |
| 2495 | if (ints & ATH9K_INT_DTIM) |
| 2496 | mask2 |= AR_IMR_S2_DTIM; |
| 2497 | if (ints & ATH9K_INT_DTIMSYNC) |
| 2498 | mask2 |= AR_IMR_S2_DTIMSYNC; |
| 2499 | if (ints & ATH9K_INT_CABEND) |
Sujith | 4af9cf4 | 2009-02-12 10:06:47 +0530 | [diff] [blame] | 2500 | mask2 |= AR_IMR_S2_CABEND; |
| 2501 | if (ints & ATH9K_INT_TSFOOR) |
| 2502 | mask2 |= AR_IMR_S2_TSFOOR; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2503 | } |
| 2504 | |
| 2505 | if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) { |
| 2506 | mask |= AR_IMR_BCNMISC; |
| 2507 | if (ints & ATH9K_INT_GTT) |
| 2508 | mask2 |= AR_IMR_S2_GTT; |
| 2509 | if (ints & ATH9K_INT_CST) |
| 2510 | mask2 |= AR_IMR_S2_CST; |
| 2511 | } |
| 2512 | |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 2513 | ath_print(common, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2514 | REG_WRITE(ah, AR_IMR, mask); |
Pavel Roskin | 74bad5c | 2010-02-23 18:15:27 -0500 | [diff] [blame] | 2515 | ah->imrs2_reg &= ~(AR_IMR_S2_TIM | AR_IMR_S2_DTIM | AR_IMR_S2_DTIMSYNC | |
| 2516 | AR_IMR_S2_CABEND | AR_IMR_S2_CABTO | |
| 2517 | AR_IMR_S2_TSFOOR | AR_IMR_S2_GTT | AR_IMR_S2_CST); |
| 2518 | ah->imrs2_reg |= mask2; |
| 2519 | REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2520 | |
Sujith | 60b67f5 | 2008-08-07 10:52:38 +0530 | [diff] [blame] | 2521 | if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2522 | if (ints & ATH9K_INT_TIM_TIMER) |
| 2523 | REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER); |
| 2524 | else |
| 2525 | REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER); |
| 2526 | } |
| 2527 | |
| 2528 | if (ints & ATH9K_INT_GLOBAL) { |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 2529 | ath_print(common, ATH_DBG_INTERRUPT, "enable IER\n"); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2530 | REG_WRITE(ah, AR_IER, AR_IER_ENABLE); |
| 2531 | if (!AR_SREV_9100(ah)) { |
| 2532 | REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, |
| 2533 | AR_INTR_MAC_IRQ); |
| 2534 | REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ); |
| 2535 | |
| 2536 | |
| 2537 | REG_WRITE(ah, AR_INTR_SYNC_ENABLE, |
| 2538 | AR_INTR_SYNC_DEFAULT); |
| 2539 | REG_WRITE(ah, AR_INTR_SYNC_MASK, |
| 2540 | AR_INTR_SYNC_DEFAULT); |
| 2541 | } |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 2542 | ath_print(common, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n", |
| 2543 | REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER)); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2544 | } |
| 2545 | |
| 2546 | return omask; |
| 2547 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 2548 | EXPORT_SYMBOL(ath9k_hw_set_interrupts); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2549 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2550 | /*******************/ |
| 2551 | /* Beacon Handling */ |
| 2552 | /*******************/ |
| 2553 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 2554 | void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2555 | { |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2556 | int flags = 0; |
| 2557 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 2558 | ah->beacon_interval = beacon_period; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2559 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 2560 | switch (ah->opmode) { |
Colin McCabe | d97809d | 2008-12-01 13:38:55 -0800 | [diff] [blame] | 2561 | case NL80211_IFTYPE_STATION: |
| 2562 | case NL80211_IFTYPE_MONITOR: |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2563 | REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon)); |
| 2564 | REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff); |
| 2565 | REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff); |
| 2566 | flags |= AR_TBTT_TIMER_EN; |
| 2567 | break; |
Colin McCabe | d97809d | 2008-12-01 13:38:55 -0800 | [diff] [blame] | 2568 | case NL80211_IFTYPE_ADHOC: |
Pat Erley | 9cb5412 | 2009-03-20 22:59:59 -0400 | [diff] [blame] | 2569 | case NL80211_IFTYPE_MESH_POINT: |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2570 | REG_SET_BIT(ah, AR_TXCFG, |
| 2571 | AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY); |
| 2572 | REG_WRITE(ah, AR_NEXT_NDP_TIMER, |
| 2573 | TU_TO_USEC(next_beacon + |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 2574 | (ah->atim_window ? ah-> |
| 2575 | atim_window : 1))); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2576 | flags |= AR_NDP_TIMER_EN; |
Colin McCabe | d97809d | 2008-12-01 13:38:55 -0800 | [diff] [blame] | 2577 | case NL80211_IFTYPE_AP: |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2578 | REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon)); |
| 2579 | REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, |
| 2580 | TU_TO_USEC(next_beacon - |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 2581 | ah->config. |
Sujith | 60b67f5 | 2008-08-07 10:52:38 +0530 | [diff] [blame] | 2582 | dma_beacon_response_time)); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2583 | REG_WRITE(ah, AR_NEXT_SWBA, |
| 2584 | TU_TO_USEC(next_beacon - |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 2585 | ah->config. |
Sujith | 60b67f5 | 2008-08-07 10:52:38 +0530 | [diff] [blame] | 2586 | sw_beacon_response_time)); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2587 | flags |= |
| 2588 | AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN; |
| 2589 | break; |
Colin McCabe | d97809d | 2008-12-01 13:38:55 -0800 | [diff] [blame] | 2590 | default: |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 2591 | ath_print(ath9k_hw_common(ah), ATH_DBG_BEACON, |
| 2592 | "%s: unsupported opmode: %d\n", |
| 2593 | __func__, ah->opmode); |
Colin McCabe | d97809d | 2008-12-01 13:38:55 -0800 | [diff] [blame] | 2594 | return; |
| 2595 | break; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2596 | } |
| 2597 | |
| 2598 | REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period)); |
| 2599 | REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period)); |
| 2600 | REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period)); |
| 2601 | REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period)); |
| 2602 | |
| 2603 | beacon_period &= ~ATH9K_BEACON_ENA; |
| 2604 | if (beacon_period & ATH9K_BEACON_RESET_TSF) { |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2605 | ath9k_hw_reset_tsf(ah); |
| 2606 | } |
| 2607 | |
| 2608 | REG_SET_BIT(ah, AR_TIMER_MODE, flags); |
| 2609 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 2610 | EXPORT_SYMBOL(ath9k_hw_beaconinit); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2611 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 2612 | void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah, |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2613 | const struct ath9k_beacon_state *bs) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2614 | { |
| 2615 | u32 nextTbtt, beaconintval, dtimperiod, beacontimeout; |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 2616 | struct ath9k_hw_capabilities *pCap = &ah->caps; |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 2617 | struct ath_common *common = ath9k_hw_common(ah); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2618 | |
| 2619 | REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt)); |
| 2620 | |
| 2621 | REG_WRITE(ah, AR_BEACON_PERIOD, |
| 2622 | TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD)); |
| 2623 | REG_WRITE(ah, AR_DMA_BEACON_PERIOD, |
| 2624 | TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD)); |
| 2625 | |
| 2626 | REG_RMW_FIELD(ah, AR_RSSI_THR, |
| 2627 | AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold); |
| 2628 | |
| 2629 | beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD; |
| 2630 | |
| 2631 | if (bs->bs_sleepduration > beaconintval) |
| 2632 | beaconintval = bs->bs_sleepduration; |
| 2633 | |
| 2634 | dtimperiod = bs->bs_dtimperiod; |
| 2635 | if (bs->bs_sleepduration > dtimperiod) |
| 2636 | dtimperiod = bs->bs_sleepduration; |
| 2637 | |
| 2638 | if (beaconintval == dtimperiod) |
| 2639 | nextTbtt = bs->bs_nextdtim; |
| 2640 | else |
| 2641 | nextTbtt = bs->bs_nexttbtt; |
| 2642 | |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 2643 | ath_print(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim); |
| 2644 | ath_print(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt); |
| 2645 | ath_print(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval); |
| 2646 | ath_print(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2647 | |
| 2648 | REG_WRITE(ah, AR_NEXT_DTIM, |
| 2649 | TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP)); |
| 2650 | REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP)); |
| 2651 | |
| 2652 | REG_WRITE(ah, AR_SLEEP1, |
| 2653 | SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT) |
| 2654 | | AR_SLEEP1_ASSUME_DTIM); |
| 2655 | |
Sujith | 60b67f5 | 2008-08-07 10:52:38 +0530 | [diff] [blame] | 2656 | if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2657 | beacontimeout = (BEACON_TIMEOUT_VAL << 3); |
| 2658 | else |
| 2659 | beacontimeout = MIN_BEACON_TIMEOUT_VAL; |
| 2660 | |
| 2661 | REG_WRITE(ah, AR_SLEEP2, |
| 2662 | SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT)); |
| 2663 | |
| 2664 | REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval)); |
| 2665 | REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod)); |
| 2666 | |
| 2667 | REG_SET_BIT(ah, AR_TIMER_MODE, |
| 2668 | AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN | |
| 2669 | AR_DTIM_TIMER_EN); |
| 2670 | |
Sujith | 4af9cf4 | 2009-02-12 10:06:47 +0530 | [diff] [blame] | 2671 | /* TSF Out of Range Threshold */ |
| 2672 | REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2673 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 2674 | EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2675 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2676 | /*******************/ |
| 2677 | /* HW Capabilities */ |
| 2678 | /*******************/ |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2679 | |
Gabor Juhos | a9a29ce | 2009-11-27 12:01:35 +0100 | [diff] [blame] | 2680 | int ath9k_hw_fill_cap_info(struct ath_hw *ah) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2681 | { |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 2682 | struct ath9k_hw_capabilities *pCap = &ah->caps; |
Luis R. Rodriguez | 608b88c | 2009-08-17 18:07:23 -0700 | [diff] [blame] | 2683 | struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 2684 | struct ath_common *common = ath9k_hw_common(ah); |
Luis R. Rodriguez | 766ec4a | 2009-09-09 14:52:02 -0700 | [diff] [blame] | 2685 | struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw; |
Luis R. Rodriguez | 608b88c | 2009-08-17 18:07:23 -0700 | [diff] [blame] | 2686 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2687 | u16 capField = 0, eeval; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2688 | |
Sujith | f74df6f | 2009-02-09 13:27:24 +0530 | [diff] [blame] | 2689 | eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0); |
Luis R. Rodriguez | 608b88c | 2009-08-17 18:07:23 -0700 | [diff] [blame] | 2690 | regulatory->current_rd = eeval; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2691 | |
Sujith | f74df6f | 2009-02-09 13:27:24 +0530 | [diff] [blame] | 2692 | eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1); |
Sujith | fec0de1 | 2009-02-12 10:06:43 +0530 | [diff] [blame] | 2693 | if (AR_SREV_9285_10_OR_LATER(ah)) |
| 2694 | eeval |= AR9285_RDEXT_DEFAULT; |
Luis R. Rodriguez | 608b88c | 2009-08-17 18:07:23 -0700 | [diff] [blame] | 2695 | regulatory->current_rd_ext = eeval; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2696 | |
Sujith | f74df6f | 2009-02-09 13:27:24 +0530 | [diff] [blame] | 2697 | capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2698 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 2699 | if (ah->opmode != NL80211_IFTYPE_AP && |
Sujith | d535a42 | 2009-02-09 13:27:06 +0530 | [diff] [blame] | 2700 | ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) { |
Luis R. Rodriguez | 608b88c | 2009-08-17 18:07:23 -0700 | [diff] [blame] | 2701 | if (regulatory->current_rd == 0x64 || |
| 2702 | regulatory->current_rd == 0x65) |
| 2703 | regulatory->current_rd += 5; |
| 2704 | else if (regulatory->current_rd == 0x41) |
| 2705 | regulatory->current_rd = 0x43; |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 2706 | ath_print(common, ATH_DBG_REGULATORY, |
| 2707 | "regdomain mapped to 0x%x\n", regulatory->current_rd); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2708 | } |
Sujith | dc2222a | 2008-08-14 13:26:55 +0530 | [diff] [blame] | 2709 | |
Sujith | f74df6f | 2009-02-09 13:27:24 +0530 | [diff] [blame] | 2710 | eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE); |
Gabor Juhos | a9a29ce | 2009-11-27 12:01:35 +0100 | [diff] [blame] | 2711 | if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) { |
| 2712 | ath_print(common, ATH_DBG_FATAL, |
| 2713 | "no band has been marked as supported in EEPROM.\n"); |
| 2714 | return -EINVAL; |
| 2715 | } |
| 2716 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2717 | bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2718 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2719 | if (eeval & AR5416_OPFLAGS_11A) { |
| 2720 | set_bit(ATH9K_MODE_11A, pCap->wireless_modes); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 2721 | if (ah->config.ht_enable) { |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2722 | if (!(eeval & AR5416_OPFLAGS_N_5G_HT20)) |
| 2723 | set_bit(ATH9K_MODE_11NA_HT20, |
| 2724 | pCap->wireless_modes); |
| 2725 | if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) { |
| 2726 | set_bit(ATH9K_MODE_11NA_HT40PLUS, |
| 2727 | pCap->wireless_modes); |
| 2728 | set_bit(ATH9K_MODE_11NA_HT40MINUS, |
| 2729 | pCap->wireless_modes); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2730 | } |
| 2731 | } |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2732 | } |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2733 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2734 | if (eeval & AR5416_OPFLAGS_11G) { |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2735 | set_bit(ATH9K_MODE_11G, pCap->wireless_modes); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 2736 | if (ah->config.ht_enable) { |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2737 | if (!(eeval & AR5416_OPFLAGS_N_2G_HT20)) |
| 2738 | set_bit(ATH9K_MODE_11NG_HT20, |
| 2739 | pCap->wireless_modes); |
| 2740 | if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) { |
| 2741 | set_bit(ATH9K_MODE_11NG_HT40PLUS, |
| 2742 | pCap->wireless_modes); |
| 2743 | set_bit(ATH9K_MODE_11NG_HT40MINUS, |
| 2744 | pCap->wireless_modes); |
| 2745 | } |
| 2746 | } |
Luis R. Rodriguez | 6f25542 | 2008-10-03 15:45:27 -0700 | [diff] [blame] | 2747 | } |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2748 | |
Sujith | f74df6f | 2009-02-09 13:27:24 +0530 | [diff] [blame] | 2749 | pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK); |
Luis R. Rodriguez | d7e7d22 | 2009-08-03 23:14:12 -0400 | [diff] [blame] | 2750 | /* |
| 2751 | * For AR9271 we will temporarilly uses the rx chainmax as read from |
| 2752 | * the EEPROM. |
| 2753 | */ |
Sujith | 8147f5d | 2009-02-20 15:13:23 +0530 | [diff] [blame] | 2754 | if ((ah->hw_version.devid == AR5416_DEVID_PCI) && |
Luis R. Rodriguez | d7e7d22 | 2009-08-03 23:14:12 -0400 | [diff] [blame] | 2755 | !(eeval & AR5416_OPFLAGS_11A) && |
| 2756 | !(AR_SREV_9271(ah))) |
| 2757 | /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */ |
Sujith | 8147f5d | 2009-02-20 15:13:23 +0530 | [diff] [blame] | 2758 | pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7; |
| 2759 | else |
Luis R. Rodriguez | d7e7d22 | 2009-08-03 23:14:12 -0400 | [diff] [blame] | 2760 | /* Use rx_chainmask from EEPROM. */ |
Sujith | 8147f5d | 2009-02-20 15:13:23 +0530 | [diff] [blame] | 2761 | pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2762 | |
Sujith | d535a42 | 2009-02-09 13:27:06 +0530 | [diff] [blame] | 2763 | if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0))) |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 2764 | ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2765 | |
| 2766 | pCap->low_2ghz_chan = 2312; |
| 2767 | pCap->high_2ghz_chan = 2732; |
| 2768 | |
| 2769 | pCap->low_5ghz_chan = 4920; |
| 2770 | pCap->high_5ghz_chan = 6100; |
| 2771 | |
| 2772 | pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP; |
| 2773 | pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP; |
| 2774 | pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM; |
| 2775 | |
| 2776 | pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP; |
| 2777 | pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP; |
| 2778 | pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM; |
| 2779 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 2780 | if (ah->config.ht_enable) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2781 | pCap->hw_caps |= ATH9K_HW_CAP_HT; |
| 2782 | else |
| 2783 | pCap->hw_caps &= ~ATH9K_HW_CAP_HT; |
| 2784 | |
| 2785 | pCap->hw_caps |= ATH9K_HW_CAP_GTT; |
| 2786 | pCap->hw_caps |= ATH9K_HW_CAP_VEOL; |
| 2787 | pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK; |
| 2788 | pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH; |
| 2789 | |
| 2790 | if (capField & AR_EEPROM_EEPCAP_MAXQCU) |
| 2791 | pCap->total_queues = |
| 2792 | MS(capField, AR_EEPROM_EEPCAP_MAXQCU); |
| 2793 | else |
| 2794 | pCap->total_queues = ATH9K_NUM_TX_QUEUES; |
| 2795 | |
| 2796 | if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES) |
| 2797 | pCap->keycache_size = |
| 2798 | 1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES); |
| 2799 | else |
| 2800 | pCap->keycache_size = AR_KEYTABLE_SIZE; |
| 2801 | |
| 2802 | pCap->hw_caps |= ATH9K_HW_CAP_FASTCC; |
Luis R. Rodriguez | f4709fd | 2009-11-24 21:37:57 -0500 | [diff] [blame] | 2803 | |
| 2804 | if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) |
| 2805 | pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD >> 1; |
| 2806 | else |
| 2807 | pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2808 | |
Sujith | 5b5fa35 | 2010-03-17 14:25:15 +0530 | [diff] [blame] | 2809 | if (AR_SREV_9271(ah)) |
| 2810 | pCap->num_gpio_pins = AR9271_NUM_GPIO; |
| 2811 | else if (AR_SREV_9285_10_OR_LATER(ah)) |
Senthil Balasubramanian | cb33c41 | 2008-12-24 18:03:58 +0530 | [diff] [blame] | 2812 | pCap->num_gpio_pins = AR9285_NUM_GPIO; |
| 2813 | else if (AR_SREV_9280_10_OR_LATER(ah)) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2814 | pCap->num_gpio_pins = AR928X_NUM_GPIO; |
| 2815 | else |
| 2816 | pCap->num_gpio_pins = AR_NUM_GPIO; |
| 2817 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2818 | if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) { |
| 2819 | pCap->hw_caps |= ATH9K_HW_CAP_CST; |
| 2820 | pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX; |
| 2821 | } else { |
| 2822 | pCap->rts_aggr_limit = (8 * 1024); |
| 2823 | } |
| 2824 | |
| 2825 | pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM; |
| 2826 | |
Senthil Balasubramanian | e97275c | 2008-11-13 18:00:02 +0530 | [diff] [blame] | 2827 | #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE) |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 2828 | ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT); |
| 2829 | if (ah->rfsilent & EEP_RFSILENT_ENABLED) { |
| 2830 | ah->rfkill_gpio = |
| 2831 | MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL); |
| 2832 | ah->rfkill_polarity = |
| 2833 | MS(ah->rfsilent, EEP_RFSILENT_POLARITY); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2834 | |
| 2835 | pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT; |
| 2836 | } |
| 2837 | #endif |
Vivek Natarajan | bde748a | 2010-04-05 14:48:05 +0530 | [diff] [blame] | 2838 | if (AR_SREV_9271(ah)) |
| 2839 | pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP; |
| 2840 | else |
| 2841 | pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2842 | |
Senthil Balasubramanian | e759407 | 2008-12-08 19:43:48 +0530 | [diff] [blame] | 2843 | if (AR_SREV_9280(ah) || AR_SREV_9285(ah)) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2844 | pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS; |
| 2845 | else |
| 2846 | pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS; |
| 2847 | |
Luis R. Rodriguez | 608b88c | 2009-08-17 18:07:23 -0700 | [diff] [blame] | 2848 | if (regulatory->current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) { |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2849 | pCap->reg_cap = |
| 2850 | AR_EEPROM_EEREGCAP_EN_KK_NEW_11A | |
| 2851 | AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN | |
| 2852 | AR_EEPROM_EEREGCAP_EN_KK_U2 | |
| 2853 | AR_EEPROM_EEREGCAP_EN_KK_MIDBAND; |
| 2854 | } else { |
| 2855 | pCap->reg_cap = |
| 2856 | AR_EEPROM_EEREGCAP_EN_KK_NEW_11A | |
| 2857 | AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN; |
| 2858 | } |
| 2859 | |
Senthil Balasubramanian | ebb90cf | 2009-09-18 15:07:33 +0530 | [diff] [blame] | 2860 | /* Advertise midband for AR5416 with FCC midband set in eeprom */ |
| 2861 | if (regulatory->current_rd_ext & (1 << REG_EXT_FCC_MIDBAND) && |
| 2862 | AR_SREV_5416(ah)) |
| 2863 | pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2864 | |
| 2865 | pCap->num_antcfg_5ghz = |
Sujith | f74df6f | 2009-02-09 13:27:24 +0530 | [diff] [blame] | 2866 | ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2867 | pCap->num_antcfg_2ghz = |
Sujith | f74df6f | 2009-02-09 13:27:24 +0530 | [diff] [blame] | 2868 | ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2869 | |
Vasanthakumar Thiagarajan | fe12946 | 2009-09-09 15:25:50 +0530 | [diff] [blame] | 2870 | if (AR_SREV_9280_10_OR_LATER(ah) && |
Luis R. Rodriguez | a36cfbc | 2009-09-09 16:05:32 -0700 | [diff] [blame] | 2871 | ath9k_hw_btcoex_supported(ah)) { |
Luis R. Rodriguez | 766ec4a | 2009-09-09 14:52:02 -0700 | [diff] [blame] | 2872 | btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO; |
| 2873 | btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO; |
Vasanthakumar Thiagarajan | 22f25d0 | 2009-08-26 21:08:47 +0530 | [diff] [blame] | 2874 | |
Vasanthakumar Thiagarajan | 8c8f9ba | 2009-09-09 15:25:52 +0530 | [diff] [blame] | 2875 | if (AR_SREV_9285(ah)) { |
Luis R. Rodriguez | 766ec4a | 2009-09-09 14:52:02 -0700 | [diff] [blame] | 2876 | btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE; |
| 2877 | btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO; |
Vasanthakumar Thiagarajan | 8c8f9ba | 2009-09-09 15:25:52 +0530 | [diff] [blame] | 2878 | } else { |
Luis R. Rodriguez | 766ec4a | 2009-09-09 14:52:02 -0700 | [diff] [blame] | 2879 | btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE; |
Vasanthakumar Thiagarajan | 8c8f9ba | 2009-09-09 15:25:52 +0530 | [diff] [blame] | 2880 | } |
Vasanthakumar Thiagarajan | 22f25d0 | 2009-08-26 21:08:47 +0530 | [diff] [blame] | 2881 | } else { |
Luis R. Rodriguez | 766ec4a | 2009-09-09 14:52:02 -0700 | [diff] [blame] | 2882 | btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE; |
Vasanthakumar Thiagarajan | c97c92d | 2009-01-02 15:35:46 +0530 | [diff] [blame] | 2883 | } |
Gabor Juhos | a9a29ce | 2009-11-27 12:01:35 +0100 | [diff] [blame] | 2884 | |
Vasanthakumar Thiagarajan | ceb2644 | 2010-04-15 17:38:25 -0400 | [diff] [blame] | 2885 | if (AR_SREV_9300_20_OR_LATER(ah)) { |
Vasanthakumar Thiagarajan | 1adf02f | 2010-04-15 17:38:24 -0400 | [diff] [blame] | 2886 | pCap->hw_caps |= ATH9K_HW_CAP_EDMA; |
Vasanthakumar Thiagarajan | ceb2644 | 2010-04-15 17:38:25 -0400 | [diff] [blame] | 2887 | pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH; |
| 2888 | pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH; |
| 2889 | pCap->rx_status_len = sizeof(struct ar9003_rxs); |
| 2890 | } |
Vasanthakumar Thiagarajan | 1adf02f | 2010-04-15 17:38:24 -0400 | [diff] [blame] | 2891 | |
Gabor Juhos | a9a29ce | 2009-11-27 12:01:35 +0100 | [diff] [blame] | 2892 | return 0; |
Luis R. Rodriguez | 6f25542 | 2008-10-03 15:45:27 -0700 | [diff] [blame] | 2893 | } |
| 2894 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 2895 | bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type, |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2896 | u32 capability, u32 *result) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2897 | { |
Luis R. Rodriguez | 608b88c | 2009-08-17 18:07:23 -0700 | [diff] [blame] | 2898 | struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2899 | switch (type) { |
| 2900 | case ATH9K_CAP_CIPHER: |
| 2901 | switch (capability) { |
| 2902 | case ATH9K_CIPHER_AES_CCM: |
| 2903 | case ATH9K_CIPHER_AES_OCB: |
| 2904 | case ATH9K_CIPHER_TKIP: |
| 2905 | case ATH9K_CIPHER_WEP: |
| 2906 | case ATH9K_CIPHER_MIC: |
| 2907 | case ATH9K_CIPHER_CLR: |
| 2908 | return true; |
| 2909 | default: |
| 2910 | return false; |
| 2911 | } |
| 2912 | case ATH9K_CAP_TKIP_MIC: |
| 2913 | switch (capability) { |
| 2914 | case 0: |
| 2915 | return true; |
| 2916 | case 1: |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 2917 | return (ah->sta_id1_defaults & |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2918 | AR_STA_ID1_CRPT_MIC_ENABLE) ? true : |
| 2919 | false; |
| 2920 | } |
| 2921 | case ATH9K_CAP_TKIP_SPLIT: |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 2922 | return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ? |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2923 | false : true; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2924 | case ATH9K_CAP_MCAST_KEYSRCH: |
| 2925 | switch (capability) { |
| 2926 | case 0: |
| 2927 | return true; |
| 2928 | case 1: |
| 2929 | if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) { |
| 2930 | return false; |
| 2931 | } else { |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 2932 | return (ah->sta_id1_defaults & |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2933 | AR_STA_ID1_MCAST_KSRCH) ? true : |
| 2934 | false; |
| 2935 | } |
| 2936 | } |
| 2937 | return false; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2938 | case ATH9K_CAP_TXPOW: |
| 2939 | switch (capability) { |
| 2940 | case 0: |
| 2941 | return 0; |
| 2942 | case 1: |
Luis R. Rodriguez | 608b88c | 2009-08-17 18:07:23 -0700 | [diff] [blame] | 2943 | *result = regulatory->power_limit; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2944 | return 0; |
| 2945 | case 2: |
Luis R. Rodriguez | 608b88c | 2009-08-17 18:07:23 -0700 | [diff] [blame] | 2946 | *result = regulatory->max_power_level; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2947 | return 0; |
| 2948 | case 3: |
Luis R. Rodriguez | 608b88c | 2009-08-17 18:07:23 -0700 | [diff] [blame] | 2949 | *result = regulatory->tp_scale; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2950 | return 0; |
| 2951 | } |
| 2952 | return false; |
Senthil Balasubramanian | 8bd1d07 | 2009-02-12 13:57:03 +0530 | [diff] [blame] | 2953 | case ATH9K_CAP_DS: |
| 2954 | return (AR_SREV_9280_20_OR_LATER(ah) && |
| 2955 | (ah->eep_ops->get_eeprom(ah, EEP_RC_CHAIN_MASK) == 1)) |
| 2956 | ? false : true; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2957 | default: |
| 2958 | return false; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2959 | } |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2960 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 2961 | EXPORT_SYMBOL(ath9k_hw_getcapability); |
Luis R. Rodriguez | 6f25542 | 2008-10-03 15:45:27 -0700 | [diff] [blame] | 2962 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 2963 | bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type, |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2964 | u32 capability, u32 setting, int *status) |
| 2965 | { |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2966 | switch (type) { |
| 2967 | case ATH9K_CAP_TKIP_MIC: |
| 2968 | if (setting) |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 2969 | ah->sta_id1_defaults |= |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2970 | AR_STA_ID1_CRPT_MIC_ENABLE; |
| 2971 | else |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 2972 | ah->sta_id1_defaults &= |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2973 | ~AR_STA_ID1_CRPT_MIC_ENABLE; |
| 2974 | return true; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2975 | case ATH9K_CAP_MCAST_KEYSRCH: |
| 2976 | if (setting) |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 2977 | ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2978 | else |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 2979 | ah->sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2980 | return true; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2981 | default: |
| 2982 | return false; |
| 2983 | } |
| 2984 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 2985 | EXPORT_SYMBOL(ath9k_hw_setcapability); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2986 | |
| 2987 | /****************************/ |
| 2988 | /* GPIO / RFKILL / Antennae */ |
| 2989 | /****************************/ |
| 2990 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 2991 | static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah, |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2992 | u32 gpio, u32 type) |
| 2993 | { |
| 2994 | int addr; |
| 2995 | u32 gpio_shift, tmp; |
| 2996 | |
| 2997 | if (gpio > 11) |
| 2998 | addr = AR_GPIO_OUTPUT_MUX3; |
| 2999 | else if (gpio > 5) |
| 3000 | addr = AR_GPIO_OUTPUT_MUX2; |
| 3001 | else |
| 3002 | addr = AR_GPIO_OUTPUT_MUX1; |
| 3003 | |
| 3004 | gpio_shift = (gpio % 6) * 5; |
| 3005 | |
| 3006 | if (AR_SREV_9280_20_OR_LATER(ah) |
| 3007 | || (addr != AR_GPIO_OUTPUT_MUX1)) { |
| 3008 | REG_RMW(ah, addr, (type << gpio_shift), |
| 3009 | (0x1f << gpio_shift)); |
| 3010 | } else { |
| 3011 | tmp = REG_READ(ah, addr); |
| 3012 | tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0); |
| 3013 | tmp &= ~(0x1f << gpio_shift); |
| 3014 | tmp |= (type << gpio_shift); |
| 3015 | REG_WRITE(ah, addr, tmp); |
| 3016 | } |
| 3017 | } |
| 3018 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 3019 | void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3020 | { |
| 3021 | u32 gpio_shift; |
| 3022 | |
Luis R. Rodriguez | 9680e8a | 2009-09-13 23:28:00 -0700 | [diff] [blame] | 3023 | BUG_ON(gpio >= ah->caps.num_gpio_pins); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3024 | |
| 3025 | gpio_shift = gpio << 1; |
| 3026 | |
| 3027 | REG_RMW(ah, |
| 3028 | AR_GPIO_OE_OUT, |
| 3029 | (AR_GPIO_OE_OUT_DRV_NO << gpio_shift), |
| 3030 | (AR_GPIO_OE_OUT_DRV << gpio_shift)); |
| 3031 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 3032 | EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3033 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 3034 | u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3035 | { |
Senthil Balasubramanian | cb33c41 | 2008-12-24 18:03:58 +0530 | [diff] [blame] | 3036 | #define MS_REG_READ(x, y) \ |
| 3037 | (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y))) |
| 3038 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 3039 | if (gpio >= ah->caps.num_gpio_pins) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3040 | return 0xffffffff; |
| 3041 | |
Felix Fietkau | 783dfca | 2010-04-15 17:38:11 -0400 | [diff] [blame] | 3042 | if (AR_SREV_9300_20_OR_LATER(ah)) |
| 3043 | return MS_REG_READ(AR9300, gpio) != 0; |
| 3044 | else if (AR_SREV_9271(ah)) |
Sujith | 5b5fa35 | 2010-03-17 14:25:15 +0530 | [diff] [blame] | 3045 | return MS_REG_READ(AR9271, gpio) != 0; |
| 3046 | else if (AR_SREV_9287_10_OR_LATER(ah)) |
Vivek Natarajan | ac88b6e | 2009-07-23 10:59:57 +0530 | [diff] [blame] | 3047 | return MS_REG_READ(AR9287, gpio) != 0; |
| 3048 | else if (AR_SREV_9285_10_OR_LATER(ah)) |
Senthil Balasubramanian | cb33c41 | 2008-12-24 18:03:58 +0530 | [diff] [blame] | 3049 | return MS_REG_READ(AR9285, gpio) != 0; |
| 3050 | else if (AR_SREV_9280_10_OR_LATER(ah)) |
| 3051 | return MS_REG_READ(AR928X, gpio) != 0; |
| 3052 | else |
| 3053 | return MS_REG_READ(AR, gpio) != 0; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3054 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 3055 | EXPORT_SYMBOL(ath9k_hw_gpio_get); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3056 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 3057 | void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio, |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3058 | u32 ah_signal_type) |
| 3059 | { |
| 3060 | u32 gpio_shift; |
| 3061 | |
| 3062 | ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type); |
| 3063 | |
| 3064 | gpio_shift = 2 * gpio; |
| 3065 | |
| 3066 | REG_RMW(ah, |
| 3067 | AR_GPIO_OE_OUT, |
| 3068 | (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift), |
| 3069 | (AR_GPIO_OE_OUT_DRV << gpio_shift)); |
| 3070 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 3071 | EXPORT_SYMBOL(ath9k_hw_cfg_output); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3072 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 3073 | void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3074 | { |
Sujith | 5b5fa35 | 2010-03-17 14:25:15 +0530 | [diff] [blame] | 3075 | if (AR_SREV_9271(ah)) |
| 3076 | val = ~val; |
| 3077 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3078 | REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio), |
| 3079 | AR_GPIO_BIT(gpio)); |
| 3080 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 3081 | EXPORT_SYMBOL(ath9k_hw_set_gpio); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3082 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 3083 | u32 ath9k_hw_getdefantenna(struct ath_hw *ah) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3084 | { |
| 3085 | return REG_READ(ah, AR_DEF_ANTENNA) & 0x7; |
| 3086 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 3087 | EXPORT_SYMBOL(ath9k_hw_getdefantenna); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3088 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 3089 | void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3090 | { |
| 3091 | REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7)); |
| 3092 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 3093 | EXPORT_SYMBOL(ath9k_hw_setantenna); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3094 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3095 | /*********************/ |
| 3096 | /* General Operation */ |
| 3097 | /*********************/ |
| 3098 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 3099 | u32 ath9k_hw_getrxfilter(struct ath_hw *ah) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3100 | { |
| 3101 | u32 bits = REG_READ(ah, AR_RX_FILTER); |
| 3102 | u32 phybits = REG_READ(ah, AR_PHY_ERR); |
| 3103 | |
| 3104 | if (phybits & AR_PHY_ERR_RADAR) |
| 3105 | bits |= ATH9K_RX_FILTER_PHYRADAR; |
| 3106 | if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING)) |
| 3107 | bits |= ATH9K_RX_FILTER_PHYERR; |
| 3108 | |
| 3109 | return bits; |
| 3110 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 3111 | EXPORT_SYMBOL(ath9k_hw_getrxfilter); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3112 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 3113 | void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3114 | { |
| 3115 | u32 phybits; |
| 3116 | |
Sujith | 7ea310b | 2009-09-03 12:08:43 +0530 | [diff] [blame] | 3117 | REG_WRITE(ah, AR_RX_FILTER, bits); |
| 3118 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3119 | phybits = 0; |
| 3120 | if (bits & ATH9K_RX_FILTER_PHYRADAR) |
| 3121 | phybits |= AR_PHY_ERR_RADAR; |
| 3122 | if (bits & ATH9K_RX_FILTER_PHYERR) |
| 3123 | phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING; |
| 3124 | REG_WRITE(ah, AR_PHY_ERR, phybits); |
| 3125 | |
| 3126 | if (phybits) |
| 3127 | REG_WRITE(ah, AR_RXCFG, |
| 3128 | REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA); |
| 3129 | else |
| 3130 | REG_WRITE(ah, AR_RXCFG, |
| 3131 | REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA); |
| 3132 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 3133 | EXPORT_SYMBOL(ath9k_hw_setrxfilter); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3134 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 3135 | bool ath9k_hw_phy_disable(struct ath_hw *ah) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3136 | { |
Senthil Balasubramanian | 63a75b9 | 2009-09-18 15:07:03 +0530 | [diff] [blame] | 3137 | if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM)) |
| 3138 | return false; |
| 3139 | |
| 3140 | ath9k_hw_init_pll(ah, NULL); |
| 3141 | return true; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3142 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 3143 | EXPORT_SYMBOL(ath9k_hw_phy_disable); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3144 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 3145 | bool ath9k_hw_disable(struct ath_hw *ah) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3146 | { |
Luis R. Rodriguez | 9ecdef4 | 2009-09-09 21:10:09 -0700 | [diff] [blame] | 3147 | if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3148 | return false; |
| 3149 | |
Senthil Balasubramanian | 63a75b9 | 2009-09-18 15:07:03 +0530 | [diff] [blame] | 3150 | if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD)) |
| 3151 | return false; |
| 3152 | |
| 3153 | ath9k_hw_init_pll(ah, NULL); |
| 3154 | return true; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3155 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 3156 | EXPORT_SYMBOL(ath9k_hw_disable); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3157 | |
Vasanthakumar Thiagarajan | 8fbff4b | 2009-05-08 17:54:51 -0700 | [diff] [blame] | 3158 | void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3159 | { |
Luis R. Rodriguez | 608b88c | 2009-08-17 18:07:23 -0700 | [diff] [blame] | 3160 | struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 3161 | struct ath9k_channel *chan = ah->curchan; |
Luis R. Rodriguez | 5f8e077 | 2009-01-22 15:16:48 -0800 | [diff] [blame] | 3162 | struct ieee80211_channel *channel = chan->chan; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3163 | |
Luis R. Rodriguez | 608b88c | 2009-08-17 18:07:23 -0700 | [diff] [blame] | 3164 | regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3165 | |
Vasanthakumar Thiagarajan | 8fbff4b | 2009-05-08 17:54:51 -0700 | [diff] [blame] | 3166 | ah->eep_ops->set_txpower(ah, chan, |
Luis R. Rodriguez | 608b88c | 2009-08-17 18:07:23 -0700 | [diff] [blame] | 3167 | ath9k_regd_get_ctl(regulatory, chan), |
Vasanthakumar Thiagarajan | 8fbff4b | 2009-05-08 17:54:51 -0700 | [diff] [blame] | 3168 | channel->max_antenna_gain * 2, |
| 3169 | channel->max_power * 2, |
| 3170 | min((u32) MAX_RATE_POWER, |
Luis R. Rodriguez | 608b88c | 2009-08-17 18:07:23 -0700 | [diff] [blame] | 3171 | (u32) regulatory->power_limit)); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3172 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 3173 | EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3174 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 3175 | void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3176 | { |
Luis R. Rodriguez | 1510718 | 2009-09-10 09:22:37 -0700 | [diff] [blame] | 3177 | memcpy(ath9k_hw_common(ah)->macaddr, mac, ETH_ALEN); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3178 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 3179 | EXPORT_SYMBOL(ath9k_hw_setmac); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3180 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 3181 | void ath9k_hw_setopmode(struct ath_hw *ah) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3182 | { |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 3183 | ath9k_hw_set_operating_mode(ah, ah->opmode); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3184 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 3185 | EXPORT_SYMBOL(ath9k_hw_setopmode); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3186 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 3187 | void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3188 | { |
| 3189 | REG_WRITE(ah, AR_MCAST_FIL0, filter0); |
| 3190 | REG_WRITE(ah, AR_MCAST_FIL1, filter1); |
| 3191 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 3192 | EXPORT_SYMBOL(ath9k_hw_setmcastfilter); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3193 | |
Luis R. Rodriguez | f2b2143 | 2009-09-10 08:50:20 -0700 | [diff] [blame] | 3194 | void ath9k_hw_write_associd(struct ath_hw *ah) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3195 | { |
Luis R. Rodriguez | 1510718 | 2009-09-10 09:22:37 -0700 | [diff] [blame] | 3196 | struct ath_common *common = ath9k_hw_common(ah); |
| 3197 | |
| 3198 | REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid)); |
| 3199 | REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) | |
| 3200 | ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S)); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3201 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 3202 | EXPORT_SYMBOL(ath9k_hw_write_associd); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3203 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 3204 | u64 ath9k_hw_gettsf64(struct ath_hw *ah) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3205 | { |
| 3206 | u64 tsf; |
| 3207 | |
| 3208 | tsf = REG_READ(ah, AR_TSF_U32); |
| 3209 | tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32); |
| 3210 | |
| 3211 | return tsf; |
| 3212 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 3213 | EXPORT_SYMBOL(ath9k_hw_gettsf64); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3214 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 3215 | void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64) |
Alina Friedrichsen | 27abe06 | 2009-01-23 05:44:21 +0100 | [diff] [blame] | 3216 | { |
Alina Friedrichsen | 27abe06 | 2009-01-23 05:44:21 +0100 | [diff] [blame] | 3217 | REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff); |
Alina Friedrichsen | b9a1619 | 2009-03-02 23:28:38 +0100 | [diff] [blame] | 3218 | REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff); |
Alina Friedrichsen | 27abe06 | 2009-01-23 05:44:21 +0100 | [diff] [blame] | 3219 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 3220 | EXPORT_SYMBOL(ath9k_hw_settsf64); |
Alina Friedrichsen | 27abe06 | 2009-01-23 05:44:21 +0100 | [diff] [blame] | 3221 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 3222 | void ath9k_hw_reset_tsf(struct ath_hw *ah) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3223 | { |
Gabor Juhos | f9b604f | 2009-06-21 00:02:15 +0200 | [diff] [blame] | 3224 | if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0, |
| 3225 | AH_TSF_WRITE_TIMEOUT)) |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 3226 | ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, |
| 3227 | "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n"); |
Gabor Juhos | f9b604f | 2009-06-21 00:02:15 +0200 | [diff] [blame] | 3228 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3229 | REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 3230 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 3231 | EXPORT_SYMBOL(ath9k_hw_reset_tsf); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 3232 | |
Sujith | 54e4cec | 2009-08-07 09:45:09 +0530 | [diff] [blame] | 3233 | void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 3234 | { |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 3235 | if (setting) |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 3236 | ah->misc_mode |= AR_PCU_TX_ADD_TSF; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 3237 | else |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 3238 | ah->misc_mode &= ~AR_PCU_TX_ADD_TSF; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 3239 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 3240 | EXPORT_SYMBOL(ath9k_hw_set_tsfadjust); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 3241 | |
Luis R. Rodriguez | 30cbd42 | 2009-11-03 16:10:46 -0800 | [diff] [blame] | 3242 | /* |
| 3243 | * Extend 15-bit time stamp from rx descriptor to |
| 3244 | * a full 64-bit TSF using the current h/w TSF. |
| 3245 | */ |
| 3246 | u64 ath9k_hw_extend_tsf(struct ath_hw *ah, u32 rstamp) |
| 3247 | { |
| 3248 | u64 tsf; |
| 3249 | |
| 3250 | tsf = ath9k_hw_gettsf64(ah); |
| 3251 | if ((tsf & 0x7fff) < rstamp) |
| 3252 | tsf -= 0x8000; |
| 3253 | return (tsf & ~0x7fff) | rstamp; |
| 3254 | } |
| 3255 | EXPORT_SYMBOL(ath9k_hw_extend_tsf); |
| 3256 | |
Luis R. Rodriguez | 25c56ee | 2009-09-13 23:04:44 -0700 | [diff] [blame] | 3257 | void ath9k_hw_set11nmac2040(struct ath_hw *ah) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 3258 | { |
Luis R. Rodriguez | 25c56ee | 2009-09-13 23:04:44 -0700 | [diff] [blame] | 3259 | struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3260 | u32 macmode; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 3261 | |
Luis R. Rodriguez | 25c56ee | 2009-09-13 23:04:44 -0700 | [diff] [blame] | 3262 | if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3263 | macmode = AR_2040_JOINED_RX_CLEAR; |
| 3264 | else |
| 3265 | macmode = 0; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 3266 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 3267 | REG_WRITE(ah, AR_2040_MODE, macmode); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 3268 | } |
Vasanthakumar Thiagarajan | ff155a4 | 2009-08-26 21:08:49 +0530 | [diff] [blame] | 3269 | |
| 3270 | /* HW Generic timers configuration */ |
| 3271 | |
| 3272 | static const struct ath_gen_timer_configuration gen_tmr_configuration[] = |
| 3273 | { |
| 3274 | {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, |
| 3275 | {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, |
| 3276 | {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, |
| 3277 | {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, |
| 3278 | {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, |
| 3279 | {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, |
| 3280 | {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, |
| 3281 | {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, |
| 3282 | {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001}, |
| 3283 | {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4, |
| 3284 | AR_NDP2_TIMER_MODE, 0x0002}, |
| 3285 | {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4, |
| 3286 | AR_NDP2_TIMER_MODE, 0x0004}, |
| 3287 | {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4, |
| 3288 | AR_NDP2_TIMER_MODE, 0x0008}, |
| 3289 | {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4, |
| 3290 | AR_NDP2_TIMER_MODE, 0x0010}, |
| 3291 | {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4, |
| 3292 | AR_NDP2_TIMER_MODE, 0x0020}, |
| 3293 | {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4, |
| 3294 | AR_NDP2_TIMER_MODE, 0x0040}, |
| 3295 | {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4, |
| 3296 | AR_NDP2_TIMER_MODE, 0x0080} |
| 3297 | }; |
| 3298 | |
| 3299 | /* HW generic timer primitives */ |
| 3300 | |
| 3301 | /* compute and clear index of rightmost 1 */ |
| 3302 | static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask) |
| 3303 | { |
| 3304 | u32 b; |
| 3305 | |
| 3306 | b = *mask; |
| 3307 | b &= (0-b); |
| 3308 | *mask &= ~b; |
| 3309 | b *= debruijn32; |
| 3310 | b >>= 27; |
| 3311 | |
| 3312 | return timer_table->gen_timer_index[b]; |
| 3313 | } |
| 3314 | |
Vasanthakumar Thiagarajan | 1773912 | 2009-08-26 21:08:50 +0530 | [diff] [blame] | 3315 | u32 ath9k_hw_gettsf32(struct ath_hw *ah) |
Vasanthakumar Thiagarajan | ff155a4 | 2009-08-26 21:08:49 +0530 | [diff] [blame] | 3316 | { |
| 3317 | return REG_READ(ah, AR_TSF_L32); |
| 3318 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 3319 | EXPORT_SYMBOL(ath9k_hw_gettsf32); |
Vasanthakumar Thiagarajan | ff155a4 | 2009-08-26 21:08:49 +0530 | [diff] [blame] | 3320 | |
| 3321 | struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah, |
| 3322 | void (*trigger)(void *), |
| 3323 | void (*overflow)(void *), |
| 3324 | void *arg, |
| 3325 | u8 timer_index) |
| 3326 | { |
| 3327 | struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; |
| 3328 | struct ath_gen_timer *timer; |
| 3329 | |
| 3330 | timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL); |
| 3331 | |
| 3332 | if (timer == NULL) { |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 3333 | ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL, |
| 3334 | "Failed to allocate memory" |
| 3335 | "for hw timer[%d]\n", timer_index); |
Vasanthakumar Thiagarajan | ff155a4 | 2009-08-26 21:08:49 +0530 | [diff] [blame] | 3336 | return NULL; |
| 3337 | } |
| 3338 | |
| 3339 | /* allocate a hardware generic timer slot */ |
| 3340 | timer_table->timers[timer_index] = timer; |
| 3341 | timer->index = timer_index; |
| 3342 | timer->trigger = trigger; |
| 3343 | timer->overflow = overflow; |
| 3344 | timer->arg = arg; |
| 3345 | |
| 3346 | return timer; |
| 3347 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 3348 | EXPORT_SYMBOL(ath_gen_timer_alloc); |
Vasanthakumar Thiagarajan | ff155a4 | 2009-08-26 21:08:49 +0530 | [diff] [blame] | 3349 | |
Luis R. Rodriguez | cd9bf68 | 2009-09-13 02:08:34 -0700 | [diff] [blame] | 3350 | void ath9k_hw_gen_timer_start(struct ath_hw *ah, |
| 3351 | struct ath_gen_timer *timer, |
| 3352 | u32 timer_next, |
| 3353 | u32 timer_period) |
Vasanthakumar Thiagarajan | ff155a4 | 2009-08-26 21:08:49 +0530 | [diff] [blame] | 3354 | { |
| 3355 | struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; |
| 3356 | u32 tsf; |
| 3357 | |
| 3358 | BUG_ON(!timer_period); |
| 3359 | |
| 3360 | set_bit(timer->index, &timer_table->timer_mask.timer_bits); |
| 3361 | |
| 3362 | tsf = ath9k_hw_gettsf32(ah); |
| 3363 | |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 3364 | ath_print(ath9k_hw_common(ah), ATH_DBG_HWTIMER, |
| 3365 | "curent tsf %x period %x" |
| 3366 | "timer_next %x\n", tsf, timer_period, timer_next); |
Vasanthakumar Thiagarajan | ff155a4 | 2009-08-26 21:08:49 +0530 | [diff] [blame] | 3367 | |
| 3368 | /* |
| 3369 | * Pull timer_next forward if the current TSF already passed it |
| 3370 | * because of software latency |
| 3371 | */ |
| 3372 | if (timer_next < tsf) |
| 3373 | timer_next = tsf + timer_period; |
| 3374 | |
| 3375 | /* |
| 3376 | * Program generic timer registers |
| 3377 | */ |
| 3378 | REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr, |
| 3379 | timer_next); |
| 3380 | REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr, |
| 3381 | timer_period); |
| 3382 | REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr, |
| 3383 | gen_tmr_configuration[timer->index].mode_mask); |
| 3384 | |
| 3385 | /* Enable both trigger and thresh interrupt masks */ |
| 3386 | REG_SET_BIT(ah, AR_IMR_S5, |
| 3387 | (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) | |
| 3388 | SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG))); |
Vasanthakumar Thiagarajan | ff155a4 | 2009-08-26 21:08:49 +0530 | [diff] [blame] | 3389 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 3390 | EXPORT_SYMBOL(ath9k_hw_gen_timer_start); |
Vasanthakumar Thiagarajan | ff155a4 | 2009-08-26 21:08:49 +0530 | [diff] [blame] | 3391 | |
Luis R. Rodriguez | cd9bf68 | 2009-09-13 02:08:34 -0700 | [diff] [blame] | 3392 | void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer) |
Vasanthakumar Thiagarajan | ff155a4 | 2009-08-26 21:08:49 +0530 | [diff] [blame] | 3393 | { |
| 3394 | struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; |
| 3395 | |
| 3396 | if ((timer->index < AR_FIRST_NDP_TIMER) || |
| 3397 | (timer->index >= ATH_MAX_GEN_TIMER)) { |
| 3398 | return; |
| 3399 | } |
| 3400 | |
| 3401 | /* Clear generic timer enable bits. */ |
| 3402 | REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr, |
| 3403 | gen_tmr_configuration[timer->index].mode_mask); |
| 3404 | |
| 3405 | /* Disable both trigger and thresh interrupt masks */ |
| 3406 | REG_CLR_BIT(ah, AR_IMR_S5, |
| 3407 | (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) | |
| 3408 | SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG))); |
| 3409 | |
| 3410 | clear_bit(timer->index, &timer_table->timer_mask.timer_bits); |
Vasanthakumar Thiagarajan | ff155a4 | 2009-08-26 21:08:49 +0530 | [diff] [blame] | 3411 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 3412 | EXPORT_SYMBOL(ath9k_hw_gen_timer_stop); |
Vasanthakumar Thiagarajan | ff155a4 | 2009-08-26 21:08:49 +0530 | [diff] [blame] | 3413 | |
| 3414 | void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer) |
| 3415 | { |
| 3416 | struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; |
| 3417 | |
| 3418 | /* free the hardware generic timer slot */ |
| 3419 | timer_table->timers[timer->index] = NULL; |
| 3420 | kfree(timer); |
| 3421 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 3422 | EXPORT_SYMBOL(ath_gen_timer_free); |
Vasanthakumar Thiagarajan | ff155a4 | 2009-08-26 21:08:49 +0530 | [diff] [blame] | 3423 | |
| 3424 | /* |
| 3425 | * Generic Timer Interrupts handling |
| 3426 | */ |
| 3427 | void ath_gen_timer_isr(struct ath_hw *ah) |
| 3428 | { |
| 3429 | struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; |
| 3430 | struct ath_gen_timer *timer; |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 3431 | struct ath_common *common = ath9k_hw_common(ah); |
Vasanthakumar Thiagarajan | ff155a4 | 2009-08-26 21:08:49 +0530 | [diff] [blame] | 3432 | u32 trigger_mask, thresh_mask, index; |
| 3433 | |
| 3434 | /* get hardware generic timer interrupt status */ |
| 3435 | trigger_mask = ah->intr_gen_timer_trigger; |
| 3436 | thresh_mask = ah->intr_gen_timer_thresh; |
| 3437 | trigger_mask &= timer_table->timer_mask.val; |
| 3438 | thresh_mask &= timer_table->timer_mask.val; |
| 3439 | |
| 3440 | trigger_mask &= ~thresh_mask; |
| 3441 | |
| 3442 | while (thresh_mask) { |
| 3443 | index = rightmost_index(timer_table, &thresh_mask); |
| 3444 | timer = timer_table->timers[index]; |
| 3445 | BUG_ON(!timer); |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 3446 | ath_print(common, ATH_DBG_HWTIMER, |
| 3447 | "TSF overflow for Gen timer %d\n", index); |
Vasanthakumar Thiagarajan | ff155a4 | 2009-08-26 21:08:49 +0530 | [diff] [blame] | 3448 | timer->overflow(timer->arg); |
| 3449 | } |
| 3450 | |
| 3451 | while (trigger_mask) { |
| 3452 | index = rightmost_index(timer_table, &trigger_mask); |
| 3453 | timer = timer_table->timers[index]; |
| 3454 | BUG_ON(!timer); |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 3455 | ath_print(common, ATH_DBG_HWTIMER, |
| 3456 | "Gen timer[%d] trigger\n", index); |
Vasanthakumar Thiagarajan | ff155a4 | 2009-08-26 21:08:49 +0530 | [diff] [blame] | 3457 | timer->trigger(timer->arg); |
| 3458 | } |
| 3459 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 3460 | EXPORT_SYMBOL(ath_gen_timer_isr); |
Luis R. Rodriguez | 2da4f01 | 2009-10-27 12:59:33 -0400 | [diff] [blame] | 3461 | |
Sujith | 05020d2 | 2010-03-17 14:25:23 +0530 | [diff] [blame] | 3462 | /********/ |
| 3463 | /* HTC */ |
| 3464 | /********/ |
| 3465 | |
| 3466 | void ath9k_hw_htc_resetinit(struct ath_hw *ah) |
| 3467 | { |
| 3468 | ah->htc_reset_init = true; |
| 3469 | } |
| 3470 | EXPORT_SYMBOL(ath9k_hw_htc_resetinit); |
| 3471 | |
Luis R. Rodriguez | 2da4f01 | 2009-10-27 12:59:33 -0400 | [diff] [blame] | 3472 | static struct { |
| 3473 | u32 version; |
| 3474 | const char * name; |
| 3475 | } ath_mac_bb_names[] = { |
| 3476 | /* Devices with external radios */ |
| 3477 | { AR_SREV_VERSION_5416_PCI, "5416" }, |
| 3478 | { AR_SREV_VERSION_5416_PCIE, "5418" }, |
| 3479 | { AR_SREV_VERSION_9100, "9100" }, |
| 3480 | { AR_SREV_VERSION_9160, "9160" }, |
| 3481 | /* Single-chip solutions */ |
| 3482 | { AR_SREV_VERSION_9280, "9280" }, |
| 3483 | { AR_SREV_VERSION_9285, "9285" }, |
Luis R. Rodriguez | 1115847 | 2009-10-27 12:59:35 -0400 | [diff] [blame] | 3484 | { AR_SREV_VERSION_9287, "9287" }, |
| 3485 | { AR_SREV_VERSION_9271, "9271" }, |
Luis R. Rodriguez | 2da4f01 | 2009-10-27 12:59:33 -0400 | [diff] [blame] | 3486 | }; |
| 3487 | |
| 3488 | /* For devices with external radios */ |
| 3489 | static struct { |
| 3490 | u16 version; |
| 3491 | const char * name; |
| 3492 | } ath_rf_names[] = { |
| 3493 | { 0, "5133" }, |
| 3494 | { AR_RAD5133_SREV_MAJOR, "5133" }, |
| 3495 | { AR_RAD5122_SREV_MAJOR, "5122" }, |
| 3496 | { AR_RAD2133_SREV_MAJOR, "2133" }, |
| 3497 | { AR_RAD2122_SREV_MAJOR, "2122" } |
| 3498 | }; |
| 3499 | |
| 3500 | /* |
| 3501 | * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown. |
| 3502 | */ |
Luis R. Rodriguez | f934c4d | 2009-10-27 12:59:34 -0400 | [diff] [blame] | 3503 | static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version) |
Luis R. Rodriguez | 2da4f01 | 2009-10-27 12:59:33 -0400 | [diff] [blame] | 3504 | { |
| 3505 | int i; |
| 3506 | |
| 3507 | for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) { |
| 3508 | if (ath_mac_bb_names[i].version == mac_bb_version) { |
| 3509 | return ath_mac_bb_names[i].name; |
| 3510 | } |
| 3511 | } |
| 3512 | |
| 3513 | return "????"; |
| 3514 | } |
Luis R. Rodriguez | 2da4f01 | 2009-10-27 12:59:33 -0400 | [diff] [blame] | 3515 | |
| 3516 | /* |
| 3517 | * Return the RF name. "????" is returned if the RF is unknown. |
| 3518 | * Used for devices with external radios. |
| 3519 | */ |
Luis R. Rodriguez | f934c4d | 2009-10-27 12:59:34 -0400 | [diff] [blame] | 3520 | static const char *ath9k_hw_rf_name(u16 rf_version) |
Luis R. Rodriguez | 2da4f01 | 2009-10-27 12:59:33 -0400 | [diff] [blame] | 3521 | { |
| 3522 | int i; |
| 3523 | |
| 3524 | for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) { |
| 3525 | if (ath_rf_names[i].version == rf_version) { |
| 3526 | return ath_rf_names[i].name; |
| 3527 | } |
| 3528 | } |
| 3529 | |
| 3530 | return "????"; |
| 3531 | } |
Luis R. Rodriguez | f934c4d | 2009-10-27 12:59:34 -0400 | [diff] [blame] | 3532 | |
| 3533 | void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len) |
| 3534 | { |
| 3535 | int used; |
| 3536 | |
| 3537 | /* chipsets >= AR9280 are single-chip */ |
| 3538 | if (AR_SREV_9280_10_OR_LATER(ah)) { |
| 3539 | used = snprintf(hw_name, len, |
| 3540 | "Atheros AR%s Rev:%x", |
| 3541 | ath9k_hw_mac_bb_name(ah->hw_version.macVersion), |
| 3542 | ah->hw_version.macRev); |
| 3543 | } |
| 3544 | else { |
| 3545 | used = snprintf(hw_name, len, |
| 3546 | "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x", |
| 3547 | ath9k_hw_mac_bb_name(ah->hw_version.macVersion), |
| 3548 | ah->hw_version.macRev, |
| 3549 | ath9k_hw_rf_name((ah->hw_version.analog5GhzRev & |
| 3550 | AR_RADIO_SREV_MAJOR)), |
| 3551 | ah->hw_version.phyRev); |
| 3552 | } |
| 3553 | |
| 3554 | hw_name[used] = '\0'; |
| 3555 | } |
| 3556 | EXPORT_SYMBOL(ath9k_hw_name); |
Luis R. Rodriguez | d70357d | 2010-04-15 17:38:06 -0400 | [diff] [blame] | 3557 | |
| 3558 | /* Sets up the AR5008/AR9001/AR9002 hardware familiy callbacks */ |
| 3559 | static void ar9002_hw_attach_ops(struct ath_hw *ah) |
| 3560 | { |
| 3561 | struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah); |
| 3562 | struct ath_hw_ops *ops = ath9k_hw_ops(ah); |
| 3563 | |
| 3564 | priv_ops->init_cal_settings = ar9002_hw_init_cal_settings; |
| 3565 | priv_ops->init_mode_regs = ar9002_hw_init_mode_regs; |
| 3566 | priv_ops->macversion_supported = ar9002_hw_macversion_supported; |
| 3567 | |
| 3568 | ops->config_pci_powersave = ar9002_hw_configpcipowersave; |
Luis R. Rodriguez | 8fe6536 | 2010-04-15 17:38:14 -0400 | [diff] [blame] | 3569 | |
Luis R. Rodriguez | 8525f28 | 2010-04-15 17:38:19 -0400 | [diff] [blame] | 3570 | ar5008_hw_attach_phy_ops(ah); |
Luis R. Rodriguez | 8fe6536 | 2010-04-15 17:38:14 -0400 | [diff] [blame] | 3571 | if (AR_SREV_9280_10_OR_LATER(ah)) |
| 3572 | ar9002_hw_attach_phy_ops(ah); |
Vasanthakumar Thiagarajan | ae3bb6d | 2010-04-15 17:38:27 -0400 | [diff] [blame] | 3573 | |
| 3574 | ar9002_hw_attach_mac_ops(ah); |
Luis R. Rodriguez | 8525f28 | 2010-04-15 17:38:19 -0400 | [diff] [blame] | 3575 | } |
| 3576 | |
| 3577 | /* Sets up the AR9003 hardware familiy callbacks */ |
| 3578 | static void ar9003_hw_attach_ops(struct ath_hw *ah) |
| 3579 | { |
Luis R. Rodriguez | 61accab | 2010-04-15 17:38:21 -0400 | [diff] [blame] | 3580 | struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah); |
| 3581 | |
| 3582 | priv_ops->macversion_supported = ar9003_hw_macversion_supported; |
| 3583 | |
Luis R. Rodriguez | 8525f28 | 2010-04-15 17:38:19 -0400 | [diff] [blame] | 3584 | ar9003_hw_attach_phy_ops(ah); |
Vasanthakumar Thiagarajan | ae3bb6d | 2010-04-15 17:38:27 -0400 | [diff] [blame] | 3585 | |
| 3586 | ar9003_hw_attach_mac_ops(ah); |
Luis R. Rodriguez | d70357d | 2010-04-15 17:38:06 -0400 | [diff] [blame] | 3587 | } |