Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2012 Freescale Semiconductor, Inc. |
| 3 | * |
Viresh Kumar | 748c876 | 2014-08-28 11:22:24 +0530 | [diff] [blame] | 4 | * Copyright (C) 2014 Linaro. |
| 5 | * Viresh Kumar <viresh.kumar@linaro.org> |
| 6 | * |
Viresh Kumar | bbcf071 | 2014-09-09 19:58:03 +0530 | [diff] [blame] | 7 | * The OPP code in function set_target() is reused from |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 8 | * drivers/cpufreq/omap-cpufreq.c |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License version 2 as |
| 12 | * published by the Free Software Foundation. |
| 13 | */ |
| 14 | |
| 15 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
| 16 | |
| 17 | #include <linux/clk.h> |
Sudeep KarkadaNagesha | e1825b2 | 2013-09-10 18:59:46 +0100 | [diff] [blame] | 18 | #include <linux/cpu.h> |
Eduardo Valentin | 77cff59 | 2013-07-15 09:09:14 -0400 | [diff] [blame] | 19 | #include <linux/cpu_cooling.h> |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 20 | #include <linux/cpufreq.h> |
Thomas Petazzoni | 34e5a52 | 2014-10-19 11:30:28 +0200 | [diff] [blame] | 21 | #include <linux/cpufreq-dt.h> |
Eduardo Valentin | 77cff59 | 2013-07-15 09:09:14 -0400 | [diff] [blame] | 22 | #include <linux/cpumask.h> |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 23 | #include <linux/err.h> |
| 24 | #include <linux/module.h> |
| 25 | #include <linux/of.h> |
Nishanth Menon | e4db1c7 | 2013-09-19 16:03:52 -0500 | [diff] [blame] | 26 | #include <linux/pm_opp.h> |
Shawn Guo | 5553f9e | 2013-01-30 14:27:49 +0000 | [diff] [blame] | 27 | #include <linux/platform_device.h> |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 28 | #include <linux/regulator/consumer.h> |
| 29 | #include <linux/slab.h> |
Eduardo Valentin | 77cff59 | 2013-07-15 09:09:14 -0400 | [diff] [blame] | 30 | #include <linux/thermal.h> |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 31 | |
Viresh Kumar | d2f31f1 | 2014-08-28 11:22:28 +0530 | [diff] [blame] | 32 | struct private_data { |
| 33 | struct device *cpu_dev; |
| 34 | struct regulator *cpu_reg; |
| 35 | struct thermal_cooling_device *cdev; |
| 36 | unsigned int voltage_tolerance; /* in percentage */ |
| 37 | }; |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 38 | |
Viresh Kumar | bbcf071 | 2014-09-09 19:58:03 +0530 | [diff] [blame] | 39 | static int set_target(struct cpufreq_policy *policy, unsigned int index) |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 40 | { |
Nishanth Menon | 47d43ba | 2013-09-19 16:03:51 -0500 | [diff] [blame] | 41 | struct dev_pm_opp *opp; |
Viresh Kumar | d2f31f1 | 2014-08-28 11:22:28 +0530 | [diff] [blame] | 42 | struct cpufreq_frequency_table *freq_table = policy->freq_table; |
| 43 | struct clk *cpu_clk = policy->clk; |
| 44 | struct private_data *priv = policy->driver_data; |
| 45 | struct device *cpu_dev = priv->cpu_dev; |
| 46 | struct regulator *cpu_reg = priv->cpu_reg; |
jhbird.choi@samsung.com | 5df6055 | 2013-03-18 08:09:42 +0000 | [diff] [blame] | 47 | unsigned long volt = 0, volt_old = 0, tol = 0; |
Viresh Kumar | d4019f0 | 2013-08-14 19:38:24 +0530 | [diff] [blame] | 48 | unsigned int old_freq, new_freq; |
Guennadi Liakhovetski | 0ca6843 | 2013-02-25 18:22:37 +0100 | [diff] [blame] | 49 | long freq_Hz, freq_exact; |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 50 | int ret; |
| 51 | |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 52 | freq_Hz = clk_round_rate(cpu_clk, freq_table[index].frequency * 1000); |
Paul Walmsley | 2209b0c | 2013-11-25 18:01:18 -0800 | [diff] [blame] | 53 | if (freq_Hz <= 0) |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 54 | freq_Hz = freq_table[index].frequency * 1000; |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 55 | |
Viresh Kumar | d4019f0 | 2013-08-14 19:38:24 +0530 | [diff] [blame] | 56 | freq_exact = freq_Hz; |
| 57 | new_freq = freq_Hz / 1000; |
| 58 | old_freq = clk_get_rate(cpu_clk) / 1000; |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 59 | |
Mark Brown | 4a511de | 2013-08-13 14:58:24 +0200 | [diff] [blame] | 60 | if (!IS_ERR(cpu_reg)) { |
Stefan Wahren | 0a1e879 | 2014-10-17 22:09:48 +0000 | [diff] [blame] | 61 | unsigned long opp_freq; |
| 62 | |
Nishanth Menon | 78e8eb8 | 2013-01-18 19:52:33 +0000 | [diff] [blame] | 63 | rcu_read_lock(); |
Nishanth Menon | 5d4879c | 2013-09-19 16:03:50 -0500 | [diff] [blame] | 64 | opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_Hz); |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 65 | if (IS_ERR(opp)) { |
Nishanth Menon | 78e8eb8 | 2013-01-18 19:52:33 +0000 | [diff] [blame] | 66 | rcu_read_unlock(); |
Viresh Kumar | fbd48ca | 2014-08-28 11:22:27 +0530 | [diff] [blame] | 67 | dev_err(cpu_dev, "failed to find OPP for %ld\n", |
| 68 | freq_Hz); |
Viresh Kumar | d4019f0 | 2013-08-14 19:38:24 +0530 | [diff] [blame] | 69 | return PTR_ERR(opp); |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 70 | } |
Nishanth Menon | 5d4879c | 2013-09-19 16:03:50 -0500 | [diff] [blame] | 71 | volt = dev_pm_opp_get_voltage(opp); |
Stefan Wahren | 0a1e879 | 2014-10-17 22:09:48 +0000 | [diff] [blame] | 72 | opp_freq = dev_pm_opp_get_freq(opp); |
Nishanth Menon | 78e8eb8 | 2013-01-18 19:52:33 +0000 | [diff] [blame] | 73 | rcu_read_unlock(); |
Viresh Kumar | d2f31f1 | 2014-08-28 11:22:28 +0530 | [diff] [blame] | 74 | tol = volt * priv->voltage_tolerance / 100; |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 75 | volt_old = regulator_get_voltage(cpu_reg); |
Stefan Wahren | 0a1e879 | 2014-10-17 22:09:48 +0000 | [diff] [blame] | 76 | dev_dbg(cpu_dev, "Found OPP: %ld kHz, %ld uV\n", |
| 77 | opp_freq / 1000, volt); |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 78 | } |
| 79 | |
Viresh Kumar | fbd48ca | 2014-08-28 11:22:27 +0530 | [diff] [blame] | 80 | dev_dbg(cpu_dev, "%u MHz, %ld mV --> %u MHz, %ld mV\n", |
Stefan Wahren | 8197bb1 | 2014-10-17 22:09:49 +0000 | [diff] [blame] | 81 | old_freq / 1000, (volt_old > 0) ? volt_old / 1000 : -1, |
Viresh Kumar | fbd48ca | 2014-08-28 11:22:27 +0530 | [diff] [blame] | 82 | new_freq / 1000, volt ? volt / 1000 : -1); |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 83 | |
| 84 | /* scaling up? scale voltage before frequency */ |
Viresh Kumar | d4019f0 | 2013-08-14 19:38:24 +0530 | [diff] [blame] | 85 | if (!IS_ERR(cpu_reg) && new_freq > old_freq) { |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 86 | ret = regulator_set_voltage_tol(cpu_reg, volt, tol); |
| 87 | if (ret) { |
Viresh Kumar | fbd48ca | 2014-08-28 11:22:27 +0530 | [diff] [blame] | 88 | dev_err(cpu_dev, "failed to scale voltage up: %d\n", |
| 89 | ret); |
Viresh Kumar | d4019f0 | 2013-08-14 19:38:24 +0530 | [diff] [blame] | 90 | return ret; |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 91 | } |
| 92 | } |
| 93 | |
Guennadi Liakhovetski | 0ca6843 | 2013-02-25 18:22:37 +0100 | [diff] [blame] | 94 | ret = clk_set_rate(cpu_clk, freq_exact); |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 95 | if (ret) { |
Viresh Kumar | fbd48ca | 2014-08-28 11:22:27 +0530 | [diff] [blame] | 96 | dev_err(cpu_dev, "failed to set clock rate: %d\n", ret); |
Stefan Wahren | 8197bb1 | 2014-10-17 22:09:49 +0000 | [diff] [blame] | 97 | if (!IS_ERR(cpu_reg) && volt_old > 0) |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 98 | regulator_set_voltage_tol(cpu_reg, volt_old, tol); |
Viresh Kumar | d4019f0 | 2013-08-14 19:38:24 +0530 | [diff] [blame] | 99 | return ret; |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 100 | } |
| 101 | |
| 102 | /* scaling down? scale voltage after frequency */ |
Viresh Kumar | d4019f0 | 2013-08-14 19:38:24 +0530 | [diff] [blame] | 103 | if (!IS_ERR(cpu_reg) && new_freq < old_freq) { |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 104 | ret = regulator_set_voltage_tol(cpu_reg, volt, tol); |
| 105 | if (ret) { |
Viresh Kumar | fbd48ca | 2014-08-28 11:22:27 +0530 | [diff] [blame] | 106 | dev_err(cpu_dev, "failed to scale voltage down: %d\n", |
| 107 | ret); |
Viresh Kumar | d4019f0 | 2013-08-14 19:38:24 +0530 | [diff] [blame] | 108 | clk_set_rate(cpu_clk, old_freq * 1000); |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 109 | } |
| 110 | } |
| 111 | |
Viresh Kumar | fd143b4 | 2013-04-01 12:57:44 +0000 | [diff] [blame] | 112 | return ret; |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 113 | } |
| 114 | |
Viresh Kumar | 95b6105 | 2014-08-28 11:22:30 +0530 | [diff] [blame] | 115 | static int allocate_resources(int cpu, struct device **cdev, |
Viresh Kumar | d2f31f1 | 2014-08-28 11:22:28 +0530 | [diff] [blame] | 116 | struct regulator **creg, struct clk **cclk) |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 117 | { |
Viresh Kumar | d2f31f1 | 2014-08-28 11:22:28 +0530 | [diff] [blame] | 118 | struct device *cpu_dev; |
| 119 | struct regulator *cpu_reg; |
| 120 | struct clk *cpu_clk; |
| 121 | int ret = 0; |
Viresh Kumar | 2d2c5e0 | 2014-08-28 11:22:29 +0530 | [diff] [blame] | 122 | char *reg_cpu0 = "cpu0", *reg_cpu = "cpu", *reg; |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 123 | |
Viresh Kumar | 95b6105 | 2014-08-28 11:22:30 +0530 | [diff] [blame] | 124 | cpu_dev = get_cpu_device(cpu); |
Sudeep KarkadaNagesha | e1825b2 | 2013-09-10 18:59:46 +0100 | [diff] [blame] | 125 | if (!cpu_dev) { |
Viresh Kumar | 95b6105 | 2014-08-28 11:22:30 +0530 | [diff] [blame] | 126 | pr_err("failed to get cpu%d device\n", cpu); |
Sudeep KarkadaNagesha | e1825b2 | 2013-09-10 18:59:46 +0100 | [diff] [blame] | 127 | return -ENODEV; |
| 128 | } |
Paolo Pisati | f5c3ef2 | 2013-03-28 09:24:29 +0000 | [diff] [blame] | 129 | |
Viresh Kumar | 2d2c5e0 | 2014-08-28 11:22:29 +0530 | [diff] [blame] | 130 | /* Try "cpu0" for older DTs */ |
Viresh Kumar | 95b6105 | 2014-08-28 11:22:30 +0530 | [diff] [blame] | 131 | if (!cpu) |
| 132 | reg = reg_cpu0; |
| 133 | else |
| 134 | reg = reg_cpu; |
Viresh Kumar | 2d2c5e0 | 2014-08-28 11:22:29 +0530 | [diff] [blame] | 135 | |
| 136 | try_again: |
| 137 | cpu_reg = regulator_get_optional(cpu_dev, reg); |
Nishanth Menon | fc31d6f | 2013-05-01 13:38:12 +0000 | [diff] [blame] | 138 | if (IS_ERR(cpu_reg)) { |
| 139 | /* |
Viresh Kumar | 95b6105 | 2014-08-28 11:22:30 +0530 | [diff] [blame] | 140 | * If cpu's regulator supply node is present, but regulator is |
Nishanth Menon | fc31d6f | 2013-05-01 13:38:12 +0000 | [diff] [blame] | 141 | * not yet registered, we should try defering probe. |
| 142 | */ |
| 143 | if (PTR_ERR(cpu_reg) == -EPROBE_DEFER) { |
Viresh Kumar | 95b6105 | 2014-08-28 11:22:30 +0530 | [diff] [blame] | 144 | dev_dbg(cpu_dev, "cpu%d regulator not ready, retry\n", |
| 145 | cpu); |
Viresh Kumar | d2f31f1 | 2014-08-28 11:22:28 +0530 | [diff] [blame] | 146 | return -EPROBE_DEFER; |
Nishanth Menon | fc31d6f | 2013-05-01 13:38:12 +0000 | [diff] [blame] | 147 | } |
Viresh Kumar | 2d2c5e0 | 2014-08-28 11:22:29 +0530 | [diff] [blame] | 148 | |
| 149 | /* Try with "cpu-supply" */ |
| 150 | if (reg == reg_cpu0) { |
| 151 | reg = reg_cpu; |
| 152 | goto try_again; |
| 153 | } |
| 154 | |
Thomas Petazzoni | a00de1a | 2014-10-19 11:30:29 +0200 | [diff] [blame] | 155 | dev_dbg(cpu_dev, "no regulator for cpu%d: %ld\n", |
| 156 | cpu, PTR_ERR(cpu_reg)); |
Nishanth Menon | fc31d6f | 2013-05-01 13:38:12 +0000 | [diff] [blame] | 157 | } |
| 158 | |
Lucas Stach | e3beb0a | 2014-05-16 12:20:42 +0200 | [diff] [blame] | 159 | cpu_clk = clk_get(cpu_dev, NULL); |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 160 | if (IS_ERR(cpu_clk)) { |
Viresh Kumar | d2f31f1 | 2014-08-28 11:22:28 +0530 | [diff] [blame] | 161 | /* put regulator */ |
| 162 | if (!IS_ERR(cpu_reg)) |
| 163 | regulator_put(cpu_reg); |
| 164 | |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 165 | ret = PTR_ERR(cpu_clk); |
Viresh Kumar | 48a8624 | 2014-08-28 11:22:26 +0530 | [diff] [blame] | 166 | |
| 167 | /* |
| 168 | * If cpu's clk node is present, but clock is not yet |
| 169 | * registered, we should try defering probe. |
| 170 | */ |
| 171 | if (ret == -EPROBE_DEFER) |
Viresh Kumar | 95b6105 | 2014-08-28 11:22:30 +0530 | [diff] [blame] | 172 | dev_dbg(cpu_dev, "cpu%d clock not ready, retry\n", cpu); |
Viresh Kumar | 48a8624 | 2014-08-28 11:22:26 +0530 | [diff] [blame] | 173 | else |
Abhilash Kesavan | 7179621 | 2014-10-31 18:09:33 +0530 | [diff] [blame] | 174 | dev_err(cpu_dev, "failed to get cpu%d clock: %d\n", cpu, |
| 175 | ret); |
Viresh Kumar | d2f31f1 | 2014-08-28 11:22:28 +0530 | [diff] [blame] | 176 | } else { |
| 177 | *cdev = cpu_dev; |
| 178 | *creg = cpu_reg; |
| 179 | *cclk = cpu_clk; |
| 180 | } |
Viresh Kumar | 48a8624 | 2014-08-28 11:22:26 +0530 | [diff] [blame] | 181 | |
Viresh Kumar | d2f31f1 | 2014-08-28 11:22:28 +0530 | [diff] [blame] | 182 | return ret; |
| 183 | } |
| 184 | |
Viresh Kumar | bbcf071 | 2014-09-09 19:58:03 +0530 | [diff] [blame] | 185 | static int cpufreq_init(struct cpufreq_policy *policy) |
Viresh Kumar | d2f31f1 | 2014-08-28 11:22:28 +0530 | [diff] [blame] | 186 | { |
Thomas Petazzoni | 34e5a52 | 2014-10-19 11:30:28 +0200 | [diff] [blame] | 187 | struct cpufreq_dt_platform_data *pd; |
Viresh Kumar | d2f31f1 | 2014-08-28 11:22:28 +0530 | [diff] [blame] | 188 | struct cpufreq_frequency_table *freq_table; |
Viresh Kumar | d2f31f1 | 2014-08-28 11:22:28 +0530 | [diff] [blame] | 189 | struct device_node *np; |
| 190 | struct private_data *priv; |
| 191 | struct device *cpu_dev; |
| 192 | struct regulator *cpu_reg; |
| 193 | struct clk *cpu_clk; |
Lucas Stach | 045ee45 | 2014-10-24 15:05:55 +0200 | [diff] [blame] | 194 | unsigned long min_uV = ~0, max_uV = 0; |
Viresh Kumar | d2f31f1 | 2014-08-28 11:22:28 +0530 | [diff] [blame] | 195 | unsigned int transition_latency; |
| 196 | int ret; |
| 197 | |
Viresh Kumar | 95b6105 | 2014-08-28 11:22:30 +0530 | [diff] [blame] | 198 | ret = allocate_resources(policy->cpu, &cpu_dev, &cpu_reg, &cpu_clk); |
Viresh Kumar | d2f31f1 | 2014-08-28 11:22:28 +0530 | [diff] [blame] | 199 | if (ret) { |
Geert Uytterhoeven | edd52b1 | 2014-10-23 11:52:54 +0200 | [diff] [blame] | 200 | pr_err("%s: Failed to allocate resources: %d\n", __func__, ret); |
Viresh Kumar | d2f31f1 | 2014-08-28 11:22:28 +0530 | [diff] [blame] | 201 | return ret; |
| 202 | } |
| 203 | |
| 204 | np = of_node_get(cpu_dev->of_node); |
| 205 | if (!np) { |
| 206 | dev_err(cpu_dev, "failed to find cpu%d node\n", policy->cpu); |
| 207 | ret = -ENOENT; |
| 208 | goto out_put_reg_clk; |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 209 | } |
| 210 | |
Viresh Kumar | 1bf8cc3 | 2014-07-11 20:24:19 +0530 | [diff] [blame] | 211 | /* OPPs might be populated at runtime, don't check for error here */ |
| 212 | of_init_opp_table(cpu_dev); |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 213 | |
Dmitry Torokhov | 62a041a | 2014-12-16 15:09:39 -0800 | [diff] [blame] | 214 | /* |
| 215 | * But we need OPP table to function so if it is not there let's |
| 216 | * give platform code chance to provide it for us. |
| 217 | */ |
| 218 | ret = dev_pm_opp_get_opp_count(cpu_dev); |
| 219 | if (ret <= 0) { |
| 220 | pr_debug("OPP table is not ready, deferring probe\n"); |
| 221 | ret = -EPROBE_DEFER; |
| 222 | goto out_free_opp; |
| 223 | } |
| 224 | |
Viresh Kumar | d2f31f1 | 2014-08-28 11:22:28 +0530 | [diff] [blame] | 225 | priv = kzalloc(sizeof(*priv), GFP_KERNEL); |
| 226 | if (!priv) { |
| 227 | ret = -ENOMEM; |
Viresh Kumar | 2f0f609 | 2014-11-25 16:04:21 +0530 | [diff] [blame] | 228 | goto out_free_opp; |
Viresh Kumar | d2f31f1 | 2014-08-28 11:22:28 +0530 | [diff] [blame] | 229 | } |
| 230 | |
| 231 | of_property_read_u32(np, "voltage-tolerance", &priv->voltage_tolerance); |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 232 | |
| 233 | if (of_property_read_u32(np, "clock-latency", &transition_latency)) |
| 234 | transition_latency = CPUFREQ_ETERNAL; |
| 235 | |
Philipp Zabel | 43c638e | 2013-09-26 11:19:37 +0200 | [diff] [blame] | 236 | if (!IS_ERR(cpu_reg)) { |
Lucas Stach | 045ee45 | 2014-10-24 15:05:55 +0200 | [diff] [blame] | 237 | unsigned long opp_freq = 0; |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 238 | |
| 239 | /* |
Lucas Stach | 045ee45 | 2014-10-24 15:05:55 +0200 | [diff] [blame] | 240 | * Disable any OPPs where the connected regulator isn't able to |
| 241 | * provide the specified voltage and record minimum and maximum |
| 242 | * voltage levels. |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 243 | */ |
Lucas Stach | 045ee45 | 2014-10-24 15:05:55 +0200 | [diff] [blame] | 244 | while (1) { |
| 245 | struct dev_pm_opp *opp; |
| 246 | unsigned long opp_uV, tol_uV; |
| 247 | |
| 248 | rcu_read_lock(); |
| 249 | opp = dev_pm_opp_find_freq_ceil(cpu_dev, &opp_freq); |
| 250 | if (IS_ERR(opp)) { |
| 251 | rcu_read_unlock(); |
| 252 | break; |
| 253 | } |
| 254 | opp_uV = dev_pm_opp_get_voltage(opp); |
| 255 | rcu_read_unlock(); |
| 256 | |
| 257 | tol_uV = opp_uV * priv->voltage_tolerance / 100; |
| 258 | if (regulator_is_supported_voltage(cpu_reg, opp_uV, |
| 259 | opp_uV + tol_uV)) { |
| 260 | if (opp_uV < min_uV) |
| 261 | min_uV = opp_uV; |
| 262 | if (opp_uV > max_uV) |
| 263 | max_uV = opp_uV; |
| 264 | } else { |
| 265 | dev_pm_opp_disable(cpu_dev, opp_freq); |
| 266 | } |
| 267 | |
| 268 | opp_freq++; |
| 269 | } |
| 270 | |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 271 | ret = regulator_set_voltage_time(cpu_reg, min_uV, max_uV); |
| 272 | if (ret > 0) |
| 273 | transition_latency += ret * 1000; |
| 274 | } |
| 275 | |
Lucas Stach | 045ee45 | 2014-10-24 15:05:55 +0200 | [diff] [blame] | 276 | ret = dev_pm_opp_init_cpufreq_table(cpu_dev, &freq_table); |
| 277 | if (ret) { |
| 278 | pr_err("failed to init cpufreq table: %d\n", ret); |
| 279 | goto out_free_priv; |
| 280 | } |
| 281 | |
Viresh Kumar | d2f31f1 | 2014-08-28 11:22:28 +0530 | [diff] [blame] | 282 | priv->cpu_dev = cpu_dev; |
| 283 | priv->cpu_reg = cpu_reg; |
| 284 | policy->driver_data = priv; |
| 285 | |
| 286 | policy->clk = cpu_clk; |
Thomas Petazzoni | 34e5a52 | 2014-10-19 11:30:28 +0200 | [diff] [blame] | 287 | ret = cpufreq_table_validate_and_show(policy, freq_table); |
| 288 | if (ret) { |
| 289 | dev_err(cpu_dev, "%s: invalid frequency table: %d\n", __func__, |
| 290 | ret); |
Viresh Kumar | 9a00442 | 2014-11-27 06:07:52 +0530 | [diff] [blame] | 291 | goto out_free_cpufreq_table; |
Thomas Petazzoni | 34e5a52 | 2014-10-19 11:30:28 +0200 | [diff] [blame] | 292 | } |
| 293 | |
| 294 | policy->cpuinfo.transition_latency = transition_latency; |
| 295 | |
| 296 | pd = cpufreq_get_driver_data(); |
Geert Uytterhoeven | c81407f | 2014-10-27 14:44:40 +0100 | [diff] [blame] | 297 | if (!pd || !pd->independent_clocks) |
Thomas Petazzoni | 34e5a52 | 2014-10-19 11:30:28 +0200 | [diff] [blame] | 298 | cpumask_setall(policy->cpus); |
Viresh Kumar | d2f31f1 | 2014-08-28 11:22:28 +0530 | [diff] [blame] | 299 | |
Lucas Stach | f9739d2 | 2014-09-26 15:33:46 +0200 | [diff] [blame] | 300 | of_node_put(np); |
| 301 | |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 302 | return 0; |
| 303 | |
Viresh Kumar | 9a00442 | 2014-11-27 06:07:52 +0530 | [diff] [blame] | 304 | out_free_cpufreq_table: |
Nishanth Menon | 5d4879c | 2013-09-19 16:03:50 -0500 | [diff] [blame] | 305 | dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table); |
Lucas Stach | 045ee45 | 2014-10-24 15:05:55 +0200 | [diff] [blame] | 306 | out_free_priv: |
| 307 | kfree(priv); |
Viresh Kumar | 2f0f609 | 2014-11-25 16:04:21 +0530 | [diff] [blame] | 308 | out_free_opp: |
| 309 | of_free_opp_table(cpu_dev); |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 310 | of_node_put(np); |
Viresh Kumar | d2f31f1 | 2014-08-28 11:22:28 +0530 | [diff] [blame] | 311 | out_put_reg_clk: |
| 312 | clk_put(cpu_clk); |
| 313 | if (!IS_ERR(cpu_reg)) |
| 314 | regulator_put(cpu_reg); |
| 315 | |
| 316 | return ret; |
| 317 | } |
| 318 | |
Viresh Kumar | bbcf071 | 2014-09-09 19:58:03 +0530 | [diff] [blame] | 319 | static int cpufreq_exit(struct cpufreq_policy *policy) |
Viresh Kumar | d2f31f1 | 2014-08-28 11:22:28 +0530 | [diff] [blame] | 320 | { |
| 321 | struct private_data *priv = policy->driver_data; |
| 322 | |
Markus Elfring | 17ad13b | 2015-02-03 19:21:21 +0100 | [diff] [blame] | 323 | cpufreq_cooling_unregister(priv->cdev); |
Viresh Kumar | d2f31f1 | 2014-08-28 11:22:28 +0530 | [diff] [blame] | 324 | dev_pm_opp_free_cpufreq_table(priv->cpu_dev, &policy->freq_table); |
Viresh Kumar | 2f0f609 | 2014-11-25 16:04:21 +0530 | [diff] [blame] | 325 | of_free_opp_table(priv->cpu_dev); |
Viresh Kumar | d2f31f1 | 2014-08-28 11:22:28 +0530 | [diff] [blame] | 326 | clk_put(policy->clk); |
| 327 | if (!IS_ERR(priv->cpu_reg)) |
| 328 | regulator_put(priv->cpu_reg); |
| 329 | kfree(priv); |
| 330 | |
| 331 | return 0; |
| 332 | } |
| 333 | |
Viresh Kumar | 9a00442 | 2014-11-27 06:07:52 +0530 | [diff] [blame] | 334 | static void cpufreq_ready(struct cpufreq_policy *policy) |
| 335 | { |
| 336 | struct private_data *priv = policy->driver_data; |
| 337 | struct device_node *np = of_node_get(priv->cpu_dev->of_node); |
| 338 | |
| 339 | if (WARN_ON(!np)) |
| 340 | return; |
| 341 | |
| 342 | /* |
| 343 | * For now, just loading the cooling device; |
| 344 | * thermal DT code takes care of matching them. |
| 345 | */ |
| 346 | if (of_find_property(np, "#cooling-cells", NULL)) { |
| 347 | priv->cdev = of_cpufreq_cooling_register(np, |
| 348 | policy->related_cpus); |
| 349 | if (IS_ERR(priv->cdev)) { |
| 350 | dev_err(priv->cpu_dev, |
| 351 | "running cpufreq without cooling device: %ld\n", |
| 352 | PTR_ERR(priv->cdev)); |
| 353 | |
| 354 | priv->cdev = NULL; |
| 355 | } |
| 356 | } |
| 357 | |
| 358 | of_node_put(np); |
| 359 | } |
| 360 | |
Viresh Kumar | bbcf071 | 2014-09-09 19:58:03 +0530 | [diff] [blame] | 361 | static struct cpufreq_driver dt_cpufreq_driver = { |
Viresh Kumar | d2f31f1 | 2014-08-28 11:22:28 +0530 | [diff] [blame] | 362 | .flags = CPUFREQ_STICKY | CPUFREQ_NEED_INITIAL_FREQ_CHECK, |
| 363 | .verify = cpufreq_generic_frequency_table_verify, |
Viresh Kumar | bbcf071 | 2014-09-09 19:58:03 +0530 | [diff] [blame] | 364 | .target_index = set_target, |
Viresh Kumar | d2f31f1 | 2014-08-28 11:22:28 +0530 | [diff] [blame] | 365 | .get = cpufreq_generic_get, |
Viresh Kumar | bbcf071 | 2014-09-09 19:58:03 +0530 | [diff] [blame] | 366 | .init = cpufreq_init, |
| 367 | .exit = cpufreq_exit, |
Viresh Kumar | 9a00442 | 2014-11-27 06:07:52 +0530 | [diff] [blame] | 368 | .ready = cpufreq_ready, |
Viresh Kumar | bbcf071 | 2014-09-09 19:58:03 +0530 | [diff] [blame] | 369 | .name = "cpufreq-dt", |
Viresh Kumar | d2f31f1 | 2014-08-28 11:22:28 +0530 | [diff] [blame] | 370 | .attr = cpufreq_generic_attr, |
| 371 | }; |
| 372 | |
Viresh Kumar | bbcf071 | 2014-09-09 19:58:03 +0530 | [diff] [blame] | 373 | static int dt_cpufreq_probe(struct platform_device *pdev) |
Viresh Kumar | d2f31f1 | 2014-08-28 11:22:28 +0530 | [diff] [blame] | 374 | { |
| 375 | struct device *cpu_dev; |
| 376 | struct regulator *cpu_reg; |
| 377 | struct clk *cpu_clk; |
| 378 | int ret; |
| 379 | |
| 380 | /* |
| 381 | * All per-cluster (CPUs sharing clock/voltages) initialization is done |
| 382 | * from ->init(). In probe(), we just need to make sure that clk and |
| 383 | * regulators are available. Else defer probe and retry. |
| 384 | * |
| 385 | * FIXME: Is checking this only for CPU0 sufficient ? |
| 386 | */ |
Viresh Kumar | 95b6105 | 2014-08-28 11:22:30 +0530 | [diff] [blame] | 387 | ret = allocate_resources(0, &cpu_dev, &cpu_reg, &cpu_clk); |
Viresh Kumar | d2f31f1 | 2014-08-28 11:22:28 +0530 | [diff] [blame] | 388 | if (ret) |
| 389 | return ret; |
| 390 | |
| 391 | clk_put(cpu_clk); |
| 392 | if (!IS_ERR(cpu_reg)) |
| 393 | regulator_put(cpu_reg); |
| 394 | |
Thomas Petazzoni | 34e5a52 | 2014-10-19 11:30:28 +0200 | [diff] [blame] | 395 | dt_cpufreq_driver.driver_data = dev_get_platdata(&pdev->dev); |
| 396 | |
Viresh Kumar | bbcf071 | 2014-09-09 19:58:03 +0530 | [diff] [blame] | 397 | ret = cpufreq_register_driver(&dt_cpufreq_driver); |
Viresh Kumar | d2f31f1 | 2014-08-28 11:22:28 +0530 | [diff] [blame] | 398 | if (ret) |
| 399 | dev_err(cpu_dev, "failed register driver: %d\n", ret); |
| 400 | |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 401 | return ret; |
| 402 | } |
Shawn Guo | 5553f9e | 2013-01-30 14:27:49 +0000 | [diff] [blame] | 403 | |
Viresh Kumar | bbcf071 | 2014-09-09 19:58:03 +0530 | [diff] [blame] | 404 | static int dt_cpufreq_remove(struct platform_device *pdev) |
Shawn Guo | 5553f9e | 2013-01-30 14:27:49 +0000 | [diff] [blame] | 405 | { |
Viresh Kumar | bbcf071 | 2014-09-09 19:58:03 +0530 | [diff] [blame] | 406 | cpufreq_unregister_driver(&dt_cpufreq_driver); |
Shawn Guo | 5553f9e | 2013-01-30 14:27:49 +0000 | [diff] [blame] | 407 | return 0; |
| 408 | } |
| 409 | |
Viresh Kumar | bbcf071 | 2014-09-09 19:58:03 +0530 | [diff] [blame] | 410 | static struct platform_driver dt_cpufreq_platdrv = { |
Shawn Guo | 5553f9e | 2013-01-30 14:27:49 +0000 | [diff] [blame] | 411 | .driver = { |
Viresh Kumar | bbcf071 | 2014-09-09 19:58:03 +0530 | [diff] [blame] | 412 | .name = "cpufreq-dt", |
Shawn Guo | 5553f9e | 2013-01-30 14:27:49 +0000 | [diff] [blame] | 413 | }, |
Viresh Kumar | bbcf071 | 2014-09-09 19:58:03 +0530 | [diff] [blame] | 414 | .probe = dt_cpufreq_probe, |
| 415 | .remove = dt_cpufreq_remove, |
Shawn Guo | 5553f9e | 2013-01-30 14:27:49 +0000 | [diff] [blame] | 416 | }; |
Viresh Kumar | bbcf071 | 2014-09-09 19:58:03 +0530 | [diff] [blame] | 417 | module_platform_driver(dt_cpufreq_platdrv); |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 418 | |
Viresh Kumar | 748c876 | 2014-08-28 11:22:24 +0530 | [diff] [blame] | 419 | MODULE_AUTHOR("Viresh Kumar <viresh.kumar@linaro.org>"); |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 420 | MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>"); |
Viresh Kumar | bbcf071 | 2014-09-09 19:58:03 +0530 | [diff] [blame] | 421 | MODULE_DESCRIPTION("Generic cpufreq driver"); |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 422 | MODULE_LICENSE("GPL"); |