Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 1 | /* |
| 2 | * This file is subject to the terms and conditions of the GNU General Public |
| 3 | * License. See the file "COPYING" in the main directory of this archive |
| 4 | * for more details. |
| 5 | * |
| 6 | * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr> |
| 7 | * Copyright (C) 2008 Nicolas Schichan <nschichan@freebox.fr> |
| 8 | */ |
| 9 | |
| 10 | #include <linux/kernel.h> |
| 11 | #include <linux/init.h> |
| 12 | #include <linux/interrupt.h> |
| 13 | #include <linux/module.h> |
David Howells | ca4d3e67 | 2010-10-07 14:08:54 +0100 | [diff] [blame] | 14 | #include <linux/irq.h> |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 15 | #include <asm/irq_cpu.h> |
| 16 | #include <asm/mipsregs.h> |
| 17 | #include <bcm63xx_cpu.h> |
| 18 | #include <bcm63xx_regs.h> |
| 19 | #include <bcm63xx_io.h> |
| 20 | #include <bcm63xx_irq.h> |
| 21 | |
Maxime Bizon | f61cced | 2011-11-04 19:09:31 +0100 | [diff] [blame] | 22 | static u32 irq_stat_addr, irq_mask_addr; |
| 23 | static void (*dispatch_internal)(void); |
Maxime Bizon | 37c42a7 | 2011-11-04 19:09:32 +0100 | [diff] [blame] | 24 | static int is_ext_irq_cascaded; |
Maxime Bizon | 6224892 | 2011-11-04 19:09:34 +0100 | [diff] [blame] | 25 | static unsigned int ext_irq_count; |
Maxime Bizon | 37c42a7 | 2011-11-04 19:09:32 +0100 | [diff] [blame] | 26 | static unsigned int ext_irq_start, ext_irq_end; |
Maxime Bizon | 6224892 | 2011-11-04 19:09:34 +0100 | [diff] [blame] | 27 | static unsigned int ext_irq_cfg_reg1, ext_irq_cfg_reg2; |
Maxime Bizon | 71a4392 | 2011-11-04 19:09:33 +0100 | [diff] [blame] | 28 | static void (*internal_irq_mask)(unsigned int irq); |
| 29 | static void (*internal_irq_unmask)(unsigned int irq); |
Maxime Bizon | f61cced | 2011-11-04 19:09:31 +0100 | [diff] [blame] | 30 | |
Maxime Bizon | f61cced | 2011-11-04 19:09:31 +0100 | [diff] [blame] | 31 | |
Maxime Bizon | 6224892 | 2011-11-04 19:09:34 +0100 | [diff] [blame] | 32 | static inline u32 get_ext_irq_perf_reg(int irq) |
| 33 | { |
| 34 | if (irq < 4) |
| 35 | return ext_irq_cfg_reg1; |
| 36 | return ext_irq_cfg_reg2; |
| 37 | } |
| 38 | |
Maxime Bizon | f61cced | 2011-11-04 19:09:31 +0100 | [diff] [blame] | 39 | static inline void handle_internal(int intbit) |
| 40 | { |
Maxime Bizon | 37c42a7 | 2011-11-04 19:09:32 +0100 | [diff] [blame] | 41 | if (is_ext_irq_cascaded && |
| 42 | intbit >= ext_irq_start && intbit <= ext_irq_end) |
| 43 | do_IRQ(intbit - ext_irq_start + IRQ_EXTERNAL_BASE); |
| 44 | else |
| 45 | do_IRQ(intbit + IRQ_INTERNAL_BASE); |
Maxime Bizon | f61cced | 2011-11-04 19:09:31 +0100 | [diff] [blame] | 46 | } |
| 47 | |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 48 | /* |
| 49 | * dispatch internal devices IRQ (uart, enet, watchdog, ...). do not |
| 50 | * prioritize any interrupt relatively to another. the static counter |
| 51 | * will resume the loop where it ended the last time we left this |
| 52 | * function. |
| 53 | */ |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 54 | |
Jonas Gorski | 86ee433 | 2014-07-12 12:49:35 +0200 | [diff] [blame^] | 55 | #define BUILD_IPIC_INTERNAL(width) \ |
| 56 | void __dispatch_internal_##width(void) \ |
| 57 | { \ |
| 58 | u32 pending[width / 32]; \ |
| 59 | unsigned int src, tgt; \ |
| 60 | bool irqs_pending = false; \ |
| 61 | static unsigned int i; \ |
| 62 | \ |
| 63 | /* read registers in reverse order */ \ |
| 64 | for (src = 0, tgt = (width / 32); src < (width / 32); src++) { \ |
| 65 | u32 val; \ |
| 66 | \ |
| 67 | val = bcm_readl(irq_stat_addr + src * sizeof(u32)); \ |
| 68 | val &= bcm_readl(irq_mask_addr + src * sizeof(u32)); \ |
| 69 | pending[--tgt] = val; \ |
| 70 | \ |
| 71 | if (val) \ |
| 72 | irqs_pending = true; \ |
| 73 | } \ |
| 74 | \ |
| 75 | if (!irqs_pending) \ |
| 76 | return; \ |
| 77 | \ |
| 78 | while (1) { \ |
| 79 | unsigned int to_call = i; \ |
| 80 | \ |
| 81 | i = (i + 1) & (width - 1); \ |
| 82 | if (pending[to_call / 32] & (1 << (to_call & 0x1f))) { \ |
| 83 | handle_internal(to_call); \ |
| 84 | break; \ |
| 85 | } \ |
| 86 | } \ |
| 87 | } \ |
| 88 | \ |
| 89 | static void __internal_irq_mask_##width(unsigned int irq) \ |
| 90 | { \ |
| 91 | u32 val; \ |
| 92 | unsigned reg = (irq / 32) ^ (width/32 - 1); \ |
| 93 | unsigned bit = irq & 0x1f; \ |
| 94 | \ |
| 95 | val = bcm_readl(irq_mask_addr + reg * sizeof(u32)); \ |
| 96 | val &= ~(1 << bit); \ |
| 97 | bcm_writel(val, irq_mask_addr + reg * sizeof(u32)); \ |
| 98 | } \ |
| 99 | \ |
| 100 | static void __internal_irq_unmask_##width(unsigned int irq) \ |
| 101 | { \ |
| 102 | u32 val; \ |
| 103 | unsigned reg = (irq / 32) ^ (width/32 - 1); \ |
| 104 | unsigned bit = irq & 0x1f; \ |
| 105 | \ |
| 106 | val = bcm_readl(irq_mask_addr + reg * sizeof(u32)); \ |
| 107 | val |= (1 << bit); \ |
| 108 | bcm_writel(val, irq_mask_addr + reg * sizeof(u32)); \ |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 109 | } |
| 110 | |
Jonas Gorski | 86ee433 | 2014-07-12 12:49:35 +0200 | [diff] [blame^] | 111 | BUILD_IPIC_INTERNAL(32); |
| 112 | BUILD_IPIC_INTERNAL(64); |
Maxime Bizon | 71a4392 | 2011-11-04 19:09:33 +0100 | [diff] [blame] | 113 | |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 114 | asmlinkage void plat_irq_dispatch(void) |
| 115 | { |
| 116 | u32 cause; |
| 117 | |
| 118 | do { |
| 119 | cause = read_c0_cause() & read_c0_status() & ST0_IM; |
| 120 | |
| 121 | if (!cause) |
| 122 | break; |
| 123 | |
| 124 | if (cause & CAUSEF_IP7) |
| 125 | do_IRQ(7); |
Kevin Cernekee | 937ad10 | 2013-06-03 14:39:34 +0000 | [diff] [blame] | 126 | if (cause & CAUSEF_IP0) |
| 127 | do_IRQ(0); |
| 128 | if (cause & CAUSEF_IP1) |
| 129 | do_IRQ(1); |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 130 | if (cause & CAUSEF_IP2) |
Maxime Bizon | f61cced | 2011-11-04 19:09:31 +0100 | [diff] [blame] | 131 | dispatch_internal(); |
Maxime Bizon | 37c42a7 | 2011-11-04 19:09:32 +0100 | [diff] [blame] | 132 | if (!is_ext_irq_cascaded) { |
| 133 | if (cause & CAUSEF_IP3) |
| 134 | do_IRQ(IRQ_EXT_0); |
| 135 | if (cause & CAUSEF_IP4) |
| 136 | do_IRQ(IRQ_EXT_1); |
| 137 | if (cause & CAUSEF_IP5) |
| 138 | do_IRQ(IRQ_EXT_2); |
| 139 | if (cause & CAUSEF_IP6) |
| 140 | do_IRQ(IRQ_EXT_3); |
| 141 | } |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 142 | } while (1); |
| 143 | } |
| 144 | |
| 145 | /* |
| 146 | * internal IRQs operations: only mask/unmask on PERF irq mask |
| 147 | * register. |
| 148 | */ |
Maxime Bizon | 37c42a7 | 2011-11-04 19:09:32 +0100 | [diff] [blame] | 149 | static void bcm63xx_internal_irq_mask(struct irq_data *d) |
| 150 | { |
| 151 | internal_irq_mask(d->irq - IRQ_INTERNAL_BASE); |
| 152 | } |
| 153 | |
| 154 | static void bcm63xx_internal_irq_unmask(struct irq_data *d) |
| 155 | { |
| 156 | internal_irq_unmask(d->irq - IRQ_INTERNAL_BASE); |
| 157 | } |
| 158 | |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 159 | /* |
| 160 | * external IRQs operations: mask/unmask and clear on PERF external |
| 161 | * irq control register. |
| 162 | */ |
Thomas Gleixner | 93f2936 | 2011-03-23 21:08:47 +0000 | [diff] [blame] | 163 | static void bcm63xx_external_irq_mask(struct irq_data *d) |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 164 | { |
Maxime Bizon | 37c42a7 | 2011-11-04 19:09:32 +0100 | [diff] [blame] | 165 | unsigned int irq = d->irq - IRQ_EXTERNAL_BASE; |
Maxime Bizon | 6224892 | 2011-11-04 19:09:34 +0100 | [diff] [blame] | 166 | u32 reg, regaddr; |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 167 | |
Maxime Bizon | 6224892 | 2011-11-04 19:09:34 +0100 | [diff] [blame] | 168 | regaddr = get_ext_irq_perf_reg(irq); |
| 169 | reg = bcm_perf_readl(regaddr); |
| 170 | |
| 171 | if (BCMCPU_IS_6348()) |
| 172 | reg &= ~EXTIRQ_CFG_MASK_6348(irq % 4); |
| 173 | else |
| 174 | reg &= ~EXTIRQ_CFG_MASK(irq % 4); |
| 175 | |
| 176 | bcm_perf_writel(reg, regaddr); |
Maxime Bizon | 37c42a7 | 2011-11-04 19:09:32 +0100 | [diff] [blame] | 177 | if (is_ext_irq_cascaded) |
| 178 | internal_irq_mask(irq + ext_irq_start); |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 179 | } |
| 180 | |
Thomas Gleixner | 93f2936 | 2011-03-23 21:08:47 +0000 | [diff] [blame] | 181 | static void bcm63xx_external_irq_unmask(struct irq_data *d) |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 182 | { |
Maxime Bizon | 37c42a7 | 2011-11-04 19:09:32 +0100 | [diff] [blame] | 183 | unsigned int irq = d->irq - IRQ_EXTERNAL_BASE; |
Maxime Bizon | 6224892 | 2011-11-04 19:09:34 +0100 | [diff] [blame] | 184 | u32 reg, regaddr; |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 185 | |
Maxime Bizon | 6224892 | 2011-11-04 19:09:34 +0100 | [diff] [blame] | 186 | regaddr = get_ext_irq_perf_reg(irq); |
| 187 | reg = bcm_perf_readl(regaddr); |
| 188 | |
| 189 | if (BCMCPU_IS_6348()) |
| 190 | reg |= EXTIRQ_CFG_MASK_6348(irq % 4); |
| 191 | else |
| 192 | reg |= EXTIRQ_CFG_MASK(irq % 4); |
| 193 | |
| 194 | bcm_perf_writel(reg, regaddr); |
| 195 | |
Maxime Bizon | 37c42a7 | 2011-11-04 19:09:32 +0100 | [diff] [blame] | 196 | if (is_ext_irq_cascaded) |
| 197 | internal_irq_unmask(irq + ext_irq_start); |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 198 | } |
| 199 | |
Thomas Gleixner | 93f2936 | 2011-03-23 21:08:47 +0000 | [diff] [blame] | 200 | static void bcm63xx_external_irq_clear(struct irq_data *d) |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 201 | { |
Maxime Bizon | 37c42a7 | 2011-11-04 19:09:32 +0100 | [diff] [blame] | 202 | unsigned int irq = d->irq - IRQ_EXTERNAL_BASE; |
Maxime Bizon | 6224892 | 2011-11-04 19:09:34 +0100 | [diff] [blame] | 203 | u32 reg, regaddr; |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 204 | |
Maxime Bizon | 6224892 | 2011-11-04 19:09:34 +0100 | [diff] [blame] | 205 | regaddr = get_ext_irq_perf_reg(irq); |
| 206 | reg = bcm_perf_readl(regaddr); |
| 207 | |
| 208 | if (BCMCPU_IS_6348()) |
| 209 | reg |= EXTIRQ_CFG_CLEAR_6348(irq % 4); |
| 210 | else |
| 211 | reg |= EXTIRQ_CFG_CLEAR(irq % 4); |
| 212 | |
| 213 | bcm_perf_writel(reg, regaddr); |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 214 | } |
| 215 | |
Thomas Gleixner | 93f2936 | 2011-03-23 21:08:47 +0000 | [diff] [blame] | 216 | static int bcm63xx_external_irq_set_type(struct irq_data *d, |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 217 | unsigned int flow_type) |
| 218 | { |
Maxime Bizon | 37c42a7 | 2011-11-04 19:09:32 +0100 | [diff] [blame] | 219 | unsigned int irq = d->irq - IRQ_EXTERNAL_BASE; |
Maxime Bizon | 6224892 | 2011-11-04 19:09:34 +0100 | [diff] [blame] | 220 | u32 reg, regaddr; |
| 221 | int levelsense, sense, bothedge; |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 222 | |
| 223 | flow_type &= IRQ_TYPE_SENSE_MASK; |
| 224 | |
| 225 | if (flow_type == IRQ_TYPE_NONE) |
| 226 | flow_type = IRQ_TYPE_LEVEL_LOW; |
| 227 | |
Maxime Bizon | 6224892 | 2011-11-04 19:09:34 +0100 | [diff] [blame] | 228 | levelsense = sense = bothedge = 0; |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 229 | switch (flow_type) { |
| 230 | case IRQ_TYPE_EDGE_BOTH: |
Maxime Bizon | 6224892 | 2011-11-04 19:09:34 +0100 | [diff] [blame] | 231 | bothedge = 1; |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 232 | break; |
| 233 | |
| 234 | case IRQ_TYPE_EDGE_RISING: |
Maxime Bizon | 6224892 | 2011-11-04 19:09:34 +0100 | [diff] [blame] | 235 | sense = 1; |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 236 | break; |
| 237 | |
| 238 | case IRQ_TYPE_EDGE_FALLING: |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 239 | break; |
| 240 | |
| 241 | case IRQ_TYPE_LEVEL_HIGH: |
Maxime Bizon | 6224892 | 2011-11-04 19:09:34 +0100 | [diff] [blame] | 242 | levelsense = 1; |
| 243 | sense = 1; |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 244 | break; |
| 245 | |
| 246 | case IRQ_TYPE_LEVEL_LOW: |
Maxime Bizon | 6224892 | 2011-11-04 19:09:34 +0100 | [diff] [blame] | 247 | levelsense = 1; |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 248 | break; |
| 249 | |
| 250 | default: |
| 251 | printk(KERN_ERR "bogus flow type combination given !\n"); |
| 252 | return -EINVAL; |
| 253 | } |
Maxime Bizon | 6224892 | 2011-11-04 19:09:34 +0100 | [diff] [blame] | 254 | |
| 255 | regaddr = get_ext_irq_perf_reg(irq); |
| 256 | reg = bcm_perf_readl(regaddr); |
| 257 | irq %= 4; |
| 258 | |
Maxime Bizon | 58e380a | 2012-07-13 07:46:05 +0000 | [diff] [blame] | 259 | switch (bcm63xx_get_cpu_id()) { |
| 260 | case BCM6348_CPU_ID: |
Maxime Bizon | 6224892 | 2011-11-04 19:09:34 +0100 | [diff] [blame] | 261 | if (levelsense) |
| 262 | reg |= EXTIRQ_CFG_LEVELSENSE_6348(irq); |
| 263 | else |
| 264 | reg &= ~EXTIRQ_CFG_LEVELSENSE_6348(irq); |
| 265 | if (sense) |
| 266 | reg |= EXTIRQ_CFG_SENSE_6348(irq); |
| 267 | else |
| 268 | reg &= ~EXTIRQ_CFG_SENSE_6348(irq); |
| 269 | if (bothedge) |
| 270 | reg |= EXTIRQ_CFG_BOTHEDGE_6348(irq); |
| 271 | else |
| 272 | reg &= ~EXTIRQ_CFG_BOTHEDGE_6348(irq); |
Maxime Bizon | 58e380a | 2012-07-13 07:46:05 +0000 | [diff] [blame] | 273 | break; |
Maxime Bizon | 6224892 | 2011-11-04 19:09:34 +0100 | [diff] [blame] | 274 | |
Florian Fainelli | 7b93342 | 2013-06-18 16:55:40 +0000 | [diff] [blame] | 275 | case BCM3368_CPU_ID: |
Maxime Bizon | 58e380a | 2012-07-13 07:46:05 +0000 | [diff] [blame] | 276 | case BCM6328_CPU_ID: |
| 277 | case BCM6338_CPU_ID: |
| 278 | case BCM6345_CPU_ID: |
| 279 | case BCM6358_CPU_ID: |
Jonas Gorski | 2c8aaf7 | 2013-03-21 14:03:17 +0000 | [diff] [blame] | 280 | case BCM6362_CPU_ID: |
Maxime Bizon | 58e380a | 2012-07-13 07:46:05 +0000 | [diff] [blame] | 281 | case BCM6368_CPU_ID: |
Maxime Bizon | 6224892 | 2011-11-04 19:09:34 +0100 | [diff] [blame] | 282 | if (levelsense) |
| 283 | reg |= EXTIRQ_CFG_LEVELSENSE(irq); |
| 284 | else |
| 285 | reg &= ~EXTIRQ_CFG_LEVELSENSE(irq); |
| 286 | if (sense) |
| 287 | reg |= EXTIRQ_CFG_SENSE(irq); |
| 288 | else |
| 289 | reg &= ~EXTIRQ_CFG_SENSE(irq); |
| 290 | if (bothedge) |
| 291 | reg |= EXTIRQ_CFG_BOTHEDGE(irq); |
| 292 | else |
| 293 | reg &= ~EXTIRQ_CFG_BOTHEDGE(irq); |
Maxime Bizon | 58e380a | 2012-07-13 07:46:05 +0000 | [diff] [blame] | 294 | break; |
| 295 | default: |
| 296 | BUG(); |
Maxime Bizon | 6224892 | 2011-11-04 19:09:34 +0100 | [diff] [blame] | 297 | } |
| 298 | |
| 299 | bcm_perf_writel(reg, regaddr); |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 300 | |
Thomas Gleixner | 93f2936 | 2011-03-23 21:08:47 +0000 | [diff] [blame] | 301 | irqd_set_trigger_type(d, flow_type); |
| 302 | if (flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) |
| 303 | __irq_set_handler_locked(d->irq, handle_level_irq); |
| 304 | else |
| 305 | __irq_set_handler_locked(d->irq, handle_edge_irq); |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 306 | |
Thomas Gleixner | 93f2936 | 2011-03-23 21:08:47 +0000 | [diff] [blame] | 307 | return IRQ_SET_MASK_OK_NOCOPY; |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 308 | } |
| 309 | |
| 310 | static struct irq_chip bcm63xx_internal_irq_chip = { |
| 311 | .name = "bcm63xx_ipic", |
Thomas Gleixner | 93f2936 | 2011-03-23 21:08:47 +0000 | [diff] [blame] | 312 | .irq_mask = bcm63xx_internal_irq_mask, |
| 313 | .irq_unmask = bcm63xx_internal_irq_unmask, |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 314 | }; |
| 315 | |
| 316 | static struct irq_chip bcm63xx_external_irq_chip = { |
| 317 | .name = "bcm63xx_epic", |
Thomas Gleixner | 93f2936 | 2011-03-23 21:08:47 +0000 | [diff] [blame] | 318 | .irq_ack = bcm63xx_external_irq_clear, |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 319 | |
Thomas Gleixner | 93f2936 | 2011-03-23 21:08:47 +0000 | [diff] [blame] | 320 | .irq_mask = bcm63xx_external_irq_mask, |
| 321 | .irq_unmask = bcm63xx_external_irq_unmask, |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 322 | |
Thomas Gleixner | 93f2936 | 2011-03-23 21:08:47 +0000 | [diff] [blame] | 323 | .irq_set_type = bcm63xx_external_irq_set_type, |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 324 | }; |
| 325 | |
| 326 | static struct irqaction cpu_ip2_cascade_action = { |
| 327 | .handler = no_action, |
| 328 | .name = "cascade_ip2", |
Wu Zhangjin | 5a4a4ad | 2011-07-23 12:41:24 +0000 | [diff] [blame] | 329 | .flags = IRQF_NO_THREAD, |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 330 | }; |
| 331 | |
Maxime Bizon | 37c42a7 | 2011-11-04 19:09:32 +0100 | [diff] [blame] | 332 | static struct irqaction cpu_ext_cascade_action = { |
| 333 | .handler = no_action, |
| 334 | .name = "cascade_extirq", |
| 335 | .flags = IRQF_NO_THREAD, |
| 336 | }; |
| 337 | |
Jonas Gorski | a6dfde8 | 2014-07-12 12:49:34 +0200 | [diff] [blame] | 338 | static void bcm63xx_init_irq(void) |
| 339 | { |
| 340 | int irq_bits; |
| 341 | |
| 342 | irq_stat_addr = bcm63xx_regset_address(RSET_PERF); |
| 343 | irq_mask_addr = bcm63xx_regset_address(RSET_PERF); |
| 344 | |
| 345 | switch (bcm63xx_get_cpu_id()) { |
| 346 | case BCM3368_CPU_ID: |
| 347 | irq_stat_addr += PERF_IRQSTAT_3368_REG; |
| 348 | irq_mask_addr += PERF_IRQMASK_3368_REG; |
| 349 | irq_bits = 32; |
| 350 | ext_irq_count = 4; |
| 351 | ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_3368; |
| 352 | break; |
| 353 | case BCM6328_CPU_ID: |
| 354 | irq_stat_addr += PERF_IRQSTAT_6328_REG; |
| 355 | irq_mask_addr += PERF_IRQMASK_6328_REG; |
| 356 | irq_bits = 64; |
| 357 | ext_irq_count = 4; |
| 358 | is_ext_irq_cascaded = 1; |
| 359 | ext_irq_start = BCM_6328_EXT_IRQ0 - IRQ_INTERNAL_BASE; |
| 360 | ext_irq_end = BCM_6328_EXT_IRQ3 - IRQ_INTERNAL_BASE; |
| 361 | ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6328; |
| 362 | break; |
| 363 | case BCM6338_CPU_ID: |
| 364 | irq_stat_addr += PERF_IRQSTAT_6338_REG; |
| 365 | irq_mask_addr += PERF_IRQMASK_6338_REG; |
| 366 | irq_bits = 32; |
| 367 | ext_irq_count = 4; |
| 368 | ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6338; |
| 369 | break; |
| 370 | case BCM6345_CPU_ID: |
| 371 | irq_stat_addr += PERF_IRQSTAT_6345_REG; |
| 372 | irq_mask_addr += PERF_IRQMASK_6345_REG; |
| 373 | irq_bits = 32; |
| 374 | ext_irq_count = 4; |
| 375 | ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6345; |
| 376 | break; |
| 377 | case BCM6348_CPU_ID: |
| 378 | irq_stat_addr += PERF_IRQSTAT_6348_REG; |
| 379 | irq_mask_addr += PERF_IRQMASK_6348_REG; |
| 380 | irq_bits = 32; |
| 381 | ext_irq_count = 4; |
| 382 | ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6348; |
| 383 | break; |
| 384 | case BCM6358_CPU_ID: |
| 385 | irq_stat_addr += PERF_IRQSTAT_6358_REG; |
| 386 | irq_mask_addr += PERF_IRQMASK_6358_REG; |
| 387 | irq_bits = 32; |
| 388 | ext_irq_count = 4; |
| 389 | is_ext_irq_cascaded = 1; |
| 390 | ext_irq_start = BCM_6358_EXT_IRQ0 - IRQ_INTERNAL_BASE; |
| 391 | ext_irq_end = BCM_6358_EXT_IRQ3 - IRQ_INTERNAL_BASE; |
| 392 | ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6358; |
| 393 | break; |
| 394 | case BCM6362_CPU_ID: |
| 395 | irq_stat_addr += PERF_IRQSTAT_6362_REG; |
| 396 | irq_mask_addr += PERF_IRQMASK_6362_REG; |
| 397 | irq_bits = 64; |
| 398 | ext_irq_count = 4; |
| 399 | is_ext_irq_cascaded = 1; |
| 400 | ext_irq_start = BCM_6362_EXT_IRQ0 - IRQ_INTERNAL_BASE; |
| 401 | ext_irq_end = BCM_6362_EXT_IRQ3 - IRQ_INTERNAL_BASE; |
| 402 | ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6362; |
| 403 | break; |
| 404 | case BCM6368_CPU_ID: |
| 405 | irq_stat_addr += PERF_IRQSTAT_6368_REG; |
| 406 | irq_mask_addr += PERF_IRQMASK_6368_REG; |
| 407 | irq_bits = 64; |
| 408 | ext_irq_count = 6; |
| 409 | is_ext_irq_cascaded = 1; |
| 410 | ext_irq_start = BCM_6368_EXT_IRQ0 - IRQ_INTERNAL_BASE; |
| 411 | ext_irq_end = BCM_6368_EXT_IRQ5 - IRQ_INTERNAL_BASE; |
| 412 | ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6368; |
| 413 | ext_irq_cfg_reg2 = PERF_EXTIRQ_CFG_REG2_6368; |
| 414 | break; |
| 415 | default: |
| 416 | BUG(); |
| 417 | } |
| 418 | |
| 419 | if (irq_bits == 32) { |
| 420 | dispatch_internal = __dispatch_internal_32; |
| 421 | internal_irq_mask = __internal_irq_mask_32; |
| 422 | internal_irq_unmask = __internal_irq_unmask_32; |
| 423 | } else { |
| 424 | dispatch_internal = __dispatch_internal_64; |
| 425 | internal_irq_mask = __internal_irq_mask_64; |
| 426 | internal_irq_unmask = __internal_irq_unmask_64; |
| 427 | } |
| 428 | } |
| 429 | |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 430 | void __init arch_init_irq(void) |
| 431 | { |
| 432 | int i; |
| 433 | |
Maxime Bizon | f61cced | 2011-11-04 19:09:31 +0100 | [diff] [blame] | 434 | bcm63xx_init_irq(); |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 435 | mips_cpu_irq_init(); |
| 436 | for (i = IRQ_INTERNAL_BASE; i < NR_IRQS; ++i) |
Thomas Gleixner | e4ec798 | 2011-03-27 15:19:28 +0200 | [diff] [blame] | 437 | irq_set_chip_and_handler(i, &bcm63xx_internal_irq_chip, |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 438 | handle_level_irq); |
| 439 | |
Maxime Bizon | 6224892 | 2011-11-04 19:09:34 +0100 | [diff] [blame] | 440 | for (i = IRQ_EXTERNAL_BASE; i < IRQ_EXTERNAL_BASE + ext_irq_count; ++i) |
Thomas Gleixner | e4ec798 | 2011-03-27 15:19:28 +0200 | [diff] [blame] | 441 | irq_set_chip_and_handler(i, &bcm63xx_external_irq_chip, |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 442 | handle_edge_irq); |
| 443 | |
Maxime Bizon | 37c42a7 | 2011-11-04 19:09:32 +0100 | [diff] [blame] | 444 | if (!is_ext_irq_cascaded) { |
Maxime Bizon | 6224892 | 2011-11-04 19:09:34 +0100 | [diff] [blame] | 445 | for (i = 3; i < 3 + ext_irq_count; ++i) |
Maxime Bizon | 37c42a7 | 2011-11-04 19:09:32 +0100 | [diff] [blame] | 446 | setup_irq(MIPS_CPU_IRQ_BASE + i, &cpu_ext_cascade_action); |
| 447 | } |
| 448 | |
| 449 | setup_irq(MIPS_CPU_IRQ_BASE + 2, &cpu_ip2_cascade_action); |
Maxime Bizon | e7300d0 | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 450 | } |