blob: 1a3ca2488164033ea4328b32ce50c517cf4e908b [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001comment "Processor Type"
2
Linus Torvalds1da177e2005-04-16 15:20:36 -07003# Select CPU types depending on the architecture selected. This selects
4# which CPUs we support in the kernel image, and the compiler instruction
5# optimiser behaviour.
6
7# ARM610
8config CPU_ARM610
Russell Kingc7508152008-10-26 10:55:14 +00009 bool "Support ARM610 processor" if ARCH_RPC
Linus Torvalds1da177e2005-04-16 15:20:36 -070010 select CPU_32v3
11 select CPU_CACHE_V3
12 select CPU_CACHE_VIVT
Hyok S. Choifefdaa02006-09-26 17:36:37 +090013 select CPU_CP15_MMU
Hyok S. Choif9c21a62006-06-21 22:26:29 +010014 select CPU_COPY_V3 if MMU
15 select CPU_TLB_V3 if MMU
Kirill A. Shutemov4fb28472009-09-25 13:39:47 +010016 select CPU_PABRT_LEGACY
Linus Torvalds1da177e2005-04-16 15:20:36 -070017 help
18 The ARM610 is the successor to the ARM3 processor
19 and was produced by VLSI Technology Inc.
20
21 Say Y if you want support for the ARM610 processor.
22 Otherwise, say N.
23
Hyok S. Choi07e0da72006-09-26 17:37:36 +090024# ARM7TDMI
25config CPU_ARM7TDMI
26 bool "Support ARM7TDMI processor"
Russell King6b237a32006-09-27 17:44:39 +010027 depends on !MMU
Hyok S. Choi07e0da72006-09-26 17:37:36 +090028 select CPU_32v4T
29 select CPU_ABRT_LV4T
Kirill A. Shutemov4fb28472009-09-25 13:39:47 +010030 select CPU_PABRT_LEGACY
Hyok S. Choi07e0da72006-09-26 17:37:36 +090031 select CPU_CACHE_V4
32 help
33 A 32-bit RISC microprocessor based on the ARM7 processor core
34 which has no memory control unit and cache.
35
36 Say Y if you want support for the ARM7TDMI processor.
37 Otherwise, say N.
38
Linus Torvalds1da177e2005-04-16 15:20:36 -070039# ARM710
40config CPU_ARM710
Russell Kingc7508152008-10-26 10:55:14 +000041 bool "Support ARM710 processor" if ARCH_RPC
Linus Torvalds1da177e2005-04-16 15:20:36 -070042 select CPU_32v3
43 select CPU_CACHE_V3
44 select CPU_CACHE_VIVT
Hyok S. Choifefdaa02006-09-26 17:36:37 +090045 select CPU_CP15_MMU
Hyok S. Choif9c21a62006-06-21 22:26:29 +010046 select CPU_COPY_V3 if MMU
47 select CPU_TLB_V3 if MMU
Kirill A. Shutemov4fb28472009-09-25 13:39:47 +010048 select CPU_PABRT_LEGACY
Linus Torvalds1da177e2005-04-16 15:20:36 -070049 help
50 A 32-bit RISC microprocessor based on the ARM7 processor core
51 designed by Advanced RISC Machines Ltd. The ARM710 is the
52 successor to the ARM610 processor. It was released in
53 July 1994 by VLSI Technology Inc.
54
55 Say Y if you want support for the ARM710 processor.
56 Otherwise, say N.
57
58# ARM720T
59config CPU_ARM720T
Russell Kingc7508152008-10-26 10:55:14 +000060 bool "Support ARM720T processor" if ARCH_INTEGRATOR
Lennert Buytenhek260e98e2006-08-28 12:51:20 +010061 select CPU_32v4T
Linus Torvalds1da177e2005-04-16 15:20:36 -070062 select CPU_ABRT_LV4T
Kirill A. Shutemov4fb28472009-09-25 13:39:47 +010063 select CPU_PABRT_LEGACY
Linus Torvalds1da177e2005-04-16 15:20:36 -070064 select CPU_CACHE_V4
65 select CPU_CACHE_VIVT
Hyok S. Choifefdaa02006-09-26 17:36:37 +090066 select CPU_CP15_MMU
Hyok S. Choif9c21a62006-06-21 22:26:29 +010067 select CPU_COPY_V4WT if MMU
68 select CPU_TLB_V4WT if MMU
Linus Torvalds1da177e2005-04-16 15:20:36 -070069 help
70 A 32-bit RISC processor with 8kByte Cache, Write Buffer and
71 MMU built around an ARM7TDMI core.
72
73 Say Y if you want support for the ARM720T processor.
74 Otherwise, say N.
75
Hyok S. Choib731c312006-09-26 17:37:50 +090076# ARM740T
77config CPU_ARM740T
78 bool "Support ARM740T processor" if ARCH_INTEGRATOR
Russell King6b237a32006-09-27 17:44:39 +010079 depends on !MMU
Hyok S. Choib731c312006-09-26 17:37:50 +090080 select CPU_32v4T
81 select CPU_ABRT_LV4T
Kirill A. Shutemov4fb28472009-09-25 13:39:47 +010082 select CPU_PABRT_LEGACY
Hyok S. Choib731c312006-09-26 17:37:50 +090083 select CPU_CACHE_V3 # although the core is v4t
84 select CPU_CP15_MPU
85 help
86 A 32-bit RISC processor with 8KB cache or 4KB variants,
87 write buffer and MPU(Protection Unit) built around
88 an ARM7TDMI core.
89
90 Say Y if you want support for the ARM740T processor.
91 Otherwise, say N.
92
Hyok S. Choi43f5f012006-09-26 17:38:05 +090093# ARM9TDMI
94config CPU_ARM9TDMI
95 bool "Support ARM9TDMI processor"
Russell King6b237a32006-09-27 17:44:39 +010096 depends on !MMU
Hyok S. Choi43f5f012006-09-26 17:38:05 +090097 select CPU_32v4T
Hyok S. Choi0f45d7f2006-09-28 21:46:16 +090098 select CPU_ABRT_NOMMU
Kirill A. Shutemov4fb28472009-09-25 13:39:47 +010099 select CPU_PABRT_LEGACY
Hyok S. Choi43f5f012006-09-26 17:38:05 +0900100 select CPU_CACHE_V4
101 help
102 A 32-bit RISC microprocessor based on the ARM9 processor core
103 which has no memory control unit and cache.
104
105 Say Y if you want support for the ARM9TDMI processor.
106 Otherwise, say N.
107
Linus Torvalds1da177e2005-04-16 15:20:36 -0700108# ARM920T
109config CPU_ARM920T
Russell Kingc7508152008-10-26 10:55:14 +0000110 bool "Support ARM920T processor" if ARCH_INTEGRATOR
Lennert Buytenhek260e98e2006-08-28 12:51:20 +0100111 select CPU_32v4T
Linus Torvalds1da177e2005-04-16 15:20:36 -0700112 select CPU_ABRT_EV4T
Kirill A. Shutemov4fb28472009-09-25 13:39:47 +0100113 select CPU_PABRT_LEGACY
Linus Torvalds1da177e2005-04-16 15:20:36 -0700114 select CPU_CACHE_V4WT
115 select CPU_CACHE_VIVT
Hyok S. Choifefdaa02006-09-26 17:36:37 +0900116 select CPU_CP15_MMU
Hyok S. Choif9c21a62006-06-21 22:26:29 +0100117 select CPU_COPY_V4WB if MMU
118 select CPU_TLB_V4WBI if MMU
Linus Torvalds1da177e2005-04-16 15:20:36 -0700119 help
120 The ARM920T is licensed to be produced by numerous vendors,
Hartley Sweetenc768e6762009-10-21 02:27:01 +0100121 and is used in the Cirrus EP93xx and the Samsung S3C2410.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700122
123 Say Y if you want support for the ARM920T processor.
124 Otherwise, say N.
125
126# ARM922T
127config CPU_ARM922T
128 bool "Support ARM922T processor" if ARCH_INTEGRATOR
Lennert Buytenhek260e98e2006-08-28 12:51:20 +0100129 select CPU_32v4T
Linus Torvalds1da177e2005-04-16 15:20:36 -0700130 select CPU_ABRT_EV4T
Kirill A. Shutemov4fb28472009-09-25 13:39:47 +0100131 select CPU_PABRT_LEGACY
Linus Torvalds1da177e2005-04-16 15:20:36 -0700132 select CPU_CACHE_V4WT
133 select CPU_CACHE_VIVT
Hyok S. Choifefdaa02006-09-26 17:36:37 +0900134 select CPU_CP15_MMU
Hyok S. Choif9c21a62006-06-21 22:26:29 +0100135 select CPU_COPY_V4WB if MMU
136 select CPU_TLB_V4WBI if MMU
Linus Torvalds1da177e2005-04-16 15:20:36 -0700137 help
138 The ARM922T is a version of the ARM920T, but with smaller
139 instruction and data caches. It is used in Altera's
Andrew Victorc53c9cf2007-05-11 21:01:28 +0100140 Excalibur XA device family and Micrel's KS8695 Centaur.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700141
142 Say Y if you want support for the ARM922T processor.
143 Otherwise, say N.
144
145# ARM925T
146config CPU_ARM925T
Tony Lindgrenb288f752005-07-10 19:58:08 +0100147 bool "Support ARM925T processor" if ARCH_OMAP1
Lennert Buytenhek260e98e2006-08-28 12:51:20 +0100148 select CPU_32v4T
Linus Torvalds1da177e2005-04-16 15:20:36 -0700149 select CPU_ABRT_EV4T
Kirill A. Shutemov4fb28472009-09-25 13:39:47 +0100150 select CPU_PABRT_LEGACY
Linus Torvalds1da177e2005-04-16 15:20:36 -0700151 select CPU_CACHE_V4WT
152 select CPU_CACHE_VIVT
Hyok S. Choifefdaa02006-09-26 17:36:37 +0900153 select CPU_CP15_MMU
Hyok S. Choif9c21a62006-06-21 22:26:29 +0100154 select CPU_COPY_V4WB if MMU
155 select CPU_TLB_V4WBI if MMU
Linus Torvalds1da177e2005-04-16 15:20:36 -0700156 help
157 The ARM925T is a mix between the ARM920T and ARM926T, but with
158 different instruction and data caches. It is used in TI's OMAP
159 device family.
160
161 Say Y if you want support for the ARM925T processor.
162 Otherwise, say N.
163
164# ARM926T
165config CPU_ARM926T
Russell Kingc7508152008-10-26 10:55:14 +0000166 bool "Support ARM926T processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB
Linus Torvalds1da177e2005-04-16 15:20:36 -0700167 select CPU_32v5
168 select CPU_ABRT_EV5TJ
Kirill A. Shutemov4fb28472009-09-25 13:39:47 +0100169 select CPU_PABRT_LEGACY
Linus Torvalds1da177e2005-04-16 15:20:36 -0700170 select CPU_CACHE_VIVT
Hyok S. Choifefdaa02006-09-26 17:36:37 +0900171 select CPU_CP15_MMU
Hyok S. Choif9c21a62006-06-21 22:26:29 +0100172 select CPU_COPY_V4WB if MMU
173 select CPU_TLB_V4WBI if MMU
Linus Torvalds1da177e2005-04-16 15:20:36 -0700174 help
175 This is a variant of the ARM920. It has slightly different
176 instruction sequences for cache and TLB operations. Curiously,
177 there is no documentation on it at the ARM corporate website.
178
179 Say Y if you want support for the ARM926T processor.
180 Otherwise, say N.
181
Paulius Zaleckas28853ac2009-03-25 13:10:01 +0200182# FA526
183config CPU_FA526
184 bool
185 select CPU_32v4
186 select CPU_ABRT_EV4
Kirill A. Shutemov4fb28472009-09-25 13:39:47 +0100187 select CPU_PABRT_LEGACY
Paulius Zaleckas28853ac2009-03-25 13:10:01 +0200188 select CPU_CACHE_VIVT
189 select CPU_CP15_MMU
190 select CPU_CACHE_FA
191 select CPU_COPY_FA if MMU
192 select CPU_TLB_FA if MMU
193 help
194 The FA526 is a version of the ARMv4 compatible processor with
195 Branch Target Buffer, Unified TLB and cache line size 16.
196
197 Say Y if you want support for the FA526 processor.
198 Otherwise, say N.
199
Hyok S. Choid60674e2006-09-26 17:38:18 +0900200# ARM940T
201config CPU_ARM940T
202 bool "Support ARM940T processor" if ARCH_INTEGRATOR
Russell King6b237a32006-09-27 17:44:39 +0100203 depends on !MMU
Hyok S. Choid60674e2006-09-26 17:38:18 +0900204 select CPU_32v4T
Hyok S. Choi0f45d7f2006-09-28 21:46:16 +0900205 select CPU_ABRT_NOMMU
Kirill A. Shutemov4fb28472009-09-25 13:39:47 +0100206 select CPU_PABRT_LEGACY
Hyok S. Choid60674e2006-09-26 17:38:18 +0900207 select CPU_CACHE_VIVT
208 select CPU_CP15_MPU
209 help
210 ARM940T is a member of the ARM9TDMI family of general-
Matt LaPlante3cb2fcc2006-11-30 05:22:59 +0100211 purpose microprocessors with MPU and separate 4KB
Hyok S. Choid60674e2006-09-26 17:38:18 +0900212 instruction and 4KB data cases, each with a 4-word line
213 length.
214
215 Say Y if you want support for the ARM940T processor.
216 Otherwise, say N.
217
Hyok S. Choif37f46e2006-09-26 17:38:32 +0900218# ARM946E-S
219config CPU_ARM946E
220 bool "Support ARM946E-S processor" if ARCH_INTEGRATOR
Russell King6b237a32006-09-27 17:44:39 +0100221 depends on !MMU
Hyok S. Choif37f46e2006-09-26 17:38:32 +0900222 select CPU_32v5
Hyok S. Choi0f45d7f2006-09-28 21:46:16 +0900223 select CPU_ABRT_NOMMU
Kirill A. Shutemov4fb28472009-09-25 13:39:47 +0100224 select CPU_PABRT_LEGACY
Hyok S. Choif37f46e2006-09-26 17:38:32 +0900225 select CPU_CACHE_VIVT
226 select CPU_CP15_MPU
227 help
228 ARM946E-S is a member of the ARM9E-S family of high-
229 performance, 32-bit system-on-chip processor solutions.
230 The TCM and ARMv5TE 32-bit instruction set is supported.
231
232 Say Y if you want support for the ARM946E-S processor.
233 Otherwise, say N.
234
Linus Torvalds1da177e2005-04-16 15:20:36 -0700235# ARM1020 - needs validating
236config CPU_ARM1020
Russell Kingc7508152008-10-26 10:55:14 +0000237 bool "Support ARM1020T (rev 0) processor" if ARCH_INTEGRATOR
Linus Torvalds1da177e2005-04-16 15:20:36 -0700238 select CPU_32v5
239 select CPU_ABRT_EV4T
Kirill A. Shutemov4fb28472009-09-25 13:39:47 +0100240 select CPU_PABRT_LEGACY
Linus Torvalds1da177e2005-04-16 15:20:36 -0700241 select CPU_CACHE_V4WT
242 select CPU_CACHE_VIVT
Hyok S. Choifefdaa02006-09-26 17:36:37 +0900243 select CPU_CP15_MMU
Hyok S. Choif9c21a62006-06-21 22:26:29 +0100244 select CPU_COPY_V4WB if MMU
245 select CPU_TLB_V4WBI if MMU
Linus Torvalds1da177e2005-04-16 15:20:36 -0700246 help
247 The ARM1020 is the 32K cached version of the ARM10 processor,
248 with an addition of a floating-point unit.
249
250 Say Y if you want support for the ARM1020 processor.
251 Otherwise, say N.
252
253# ARM1020E - needs validating
254config CPU_ARM1020E
Russell Kingc7508152008-10-26 10:55:14 +0000255 bool "Support ARM1020E processor" if ARCH_INTEGRATOR
Linus Torvalds1da177e2005-04-16 15:20:36 -0700256 select CPU_32v5
257 select CPU_ABRT_EV4T
Kirill A. Shutemov4fb28472009-09-25 13:39:47 +0100258 select CPU_PABRT_LEGACY
Linus Torvalds1da177e2005-04-16 15:20:36 -0700259 select CPU_CACHE_V4WT
260 select CPU_CACHE_VIVT
Hyok S. Choifefdaa02006-09-26 17:36:37 +0900261 select CPU_CP15_MMU
Hyok S. Choif9c21a62006-06-21 22:26:29 +0100262 select CPU_COPY_V4WB if MMU
263 select CPU_TLB_V4WBI if MMU
Linus Torvalds1da177e2005-04-16 15:20:36 -0700264 depends on n
265
266# ARM1022E
267config CPU_ARM1022
Russell Kingc7508152008-10-26 10:55:14 +0000268 bool "Support ARM1022E processor" if ARCH_INTEGRATOR
Linus Torvalds1da177e2005-04-16 15:20:36 -0700269 select CPU_32v5
270 select CPU_ABRT_EV4T
Kirill A. Shutemov4fb28472009-09-25 13:39:47 +0100271 select CPU_PABRT_LEGACY
Linus Torvalds1da177e2005-04-16 15:20:36 -0700272 select CPU_CACHE_VIVT
Hyok S. Choifefdaa02006-09-26 17:36:37 +0900273 select CPU_CP15_MMU
Hyok S. Choif9c21a62006-06-21 22:26:29 +0100274 select CPU_COPY_V4WB if MMU # can probably do better
275 select CPU_TLB_V4WBI if MMU
Linus Torvalds1da177e2005-04-16 15:20:36 -0700276 help
277 The ARM1022E is an implementation of the ARMv5TE architecture
278 based upon the ARM10 integer core with a 16KiB L1 Harvard cache,
279 embedded trace macrocell, and a floating-point unit.
280
281 Say Y if you want support for the ARM1022E processor.
282 Otherwise, say N.
283
284# ARM1026EJ-S
285config CPU_ARM1026
Russell Kingc7508152008-10-26 10:55:14 +0000286 bool "Support ARM1026EJ-S processor" if ARCH_INTEGRATOR
Linus Torvalds1da177e2005-04-16 15:20:36 -0700287 select CPU_32v5
288 select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10
Kirill A. Shutemov4fb28472009-09-25 13:39:47 +0100289 select CPU_PABRT_LEGACY
Linus Torvalds1da177e2005-04-16 15:20:36 -0700290 select CPU_CACHE_VIVT
Hyok S. Choifefdaa02006-09-26 17:36:37 +0900291 select CPU_CP15_MMU
Hyok S. Choif9c21a62006-06-21 22:26:29 +0100292 select CPU_COPY_V4WB if MMU # can probably do better
293 select CPU_TLB_V4WBI if MMU
Linus Torvalds1da177e2005-04-16 15:20:36 -0700294 help
295 The ARM1026EJ-S is an implementation of the ARMv5TEJ architecture
296 based upon the ARM10 integer core.
297
298 Say Y if you want support for the ARM1026EJ-S processor.
299 Otherwise, say N.
300
301# SA110
302config CPU_SA110
Russell Kingc7508152008-10-26 10:55:14 +0000303 bool "Support StrongARM(R) SA-110 processor" if ARCH_RPC
Linus Torvalds1da177e2005-04-16 15:20:36 -0700304 select CPU_32v3 if ARCH_RPC
305 select CPU_32v4 if !ARCH_RPC
306 select CPU_ABRT_EV4
Kirill A. Shutemov4fb28472009-09-25 13:39:47 +0100307 select CPU_PABRT_LEGACY
Linus Torvalds1da177e2005-04-16 15:20:36 -0700308 select CPU_CACHE_V4WB
309 select CPU_CACHE_VIVT
Hyok S. Choifefdaa02006-09-26 17:36:37 +0900310 select CPU_CP15_MMU
Hyok S. Choif9c21a62006-06-21 22:26:29 +0100311 select CPU_COPY_V4WB if MMU
312 select CPU_TLB_V4WB if MMU
Linus Torvalds1da177e2005-04-16 15:20:36 -0700313 help
314 The Intel StrongARM(R) SA-110 is a 32-bit microprocessor and
315 is available at five speeds ranging from 100 MHz to 233 MHz.
316 More information is available at
317 <http://developer.intel.com/design/strong/sa110.htm>.
318
319 Say Y if you want support for the SA-110 processor.
320 Otherwise, say N.
321
322# SA1100
323config CPU_SA1100
324 bool
Linus Torvalds1da177e2005-04-16 15:20:36 -0700325 select CPU_32v4
326 select CPU_ABRT_EV4
Kirill A. Shutemov4fb28472009-09-25 13:39:47 +0100327 select CPU_PABRT_LEGACY
Linus Torvalds1da177e2005-04-16 15:20:36 -0700328 select CPU_CACHE_V4WB
329 select CPU_CACHE_VIVT
Hyok S. Choifefdaa02006-09-26 17:36:37 +0900330 select CPU_CP15_MMU
Hyok S. Choif9c21a62006-06-21 22:26:29 +0100331 select CPU_TLB_V4WB if MMU
Linus Torvalds1da177e2005-04-16 15:20:36 -0700332
333# XScale
334config CPU_XSCALE
335 bool
Linus Torvalds1da177e2005-04-16 15:20:36 -0700336 select CPU_32v5
337 select CPU_ABRT_EV5T
Kirill A. Shutemov4fb28472009-09-25 13:39:47 +0100338 select CPU_PABRT_LEGACY
Linus Torvalds1da177e2005-04-16 15:20:36 -0700339 select CPU_CACHE_VIVT
Hyok S. Choifefdaa02006-09-26 17:36:37 +0900340 select CPU_CP15_MMU
Hyok S. Choif9c21a62006-06-21 22:26:29 +0100341 select CPU_TLB_V4WBI if MMU
Linus Torvalds1da177e2005-04-16 15:20:36 -0700342
Lennert Buytenhek23bdf862006-03-28 21:00:40 +0100343# XScale Core Version 3
344config CPU_XSC3
345 bool
Lennert Buytenhek23bdf862006-03-28 21:00:40 +0100346 select CPU_32v5
347 select CPU_ABRT_EV5T
Kirill A. Shutemov4fb28472009-09-25 13:39:47 +0100348 select CPU_PABRT_LEGACY
Lennert Buytenhek23bdf862006-03-28 21:00:40 +0100349 select CPU_CACHE_VIVT
Hyok S. Choifefdaa02006-09-26 17:36:37 +0900350 select CPU_CP15_MMU
Hyok S. Choif9c21a62006-06-21 22:26:29 +0100351 select CPU_TLB_V4WBI if MMU
Lennert Buytenhek23bdf862006-03-28 21:00:40 +0100352 select IO_36
353
Eric Miao49cbe782009-01-20 14:15:18 +0800354# Marvell PJ1 (Mohawk)
355config CPU_MOHAWK
356 bool
357 select CPU_32v5
358 select CPU_ABRT_EV5T
Kirill A. Shutemov4fb28472009-09-25 13:39:47 +0100359 select CPU_PABRT_LEGACY
Eric Miao49cbe782009-01-20 14:15:18 +0800360 select CPU_CACHE_VIVT
361 select CPU_CP15_MMU
362 select CPU_TLB_V4WBI if MMU
363 select CPU_COPY_V4WB if MMU
364
Assaf Hoffmane50d6402007-10-23 15:14:41 -0400365# Feroceon
366config CPU_FEROCEON
367 bool
Assaf Hoffmane50d6402007-10-23 15:14:41 -0400368 select CPU_32v5
369 select CPU_ABRT_EV5T
Kirill A. Shutemov4fb28472009-09-25 13:39:47 +0100370 select CPU_PABRT_LEGACY
Assaf Hoffmane50d6402007-10-23 15:14:41 -0400371 select CPU_CACHE_VIVT
372 select CPU_CP15_MMU
Lennert Buytenhek0ed15072008-04-24 01:31:45 -0400373 select CPU_COPY_FEROCEON if MMU
Lennert Buytenhek99c6dc12008-06-22 22:45:04 +0200374 select CPU_TLB_FEROCEON if MMU
Assaf Hoffmane50d6402007-10-23 15:14:41 -0400375
Tzachi Perelsteind910a0a2007-11-06 10:35:40 +0200376config CPU_FEROCEON_OLD_ID
377 bool "Accept early Feroceon cores with an ARM926 ID"
378 depends on CPU_FEROCEON && !CPU_ARM926T
379 default y
380 help
381 This enables the usage of some old Feroceon cores
382 for which the CPU ID is equal to the ARM926 ID.
383 Relevant for Feroceon-1850 and early Feroceon-2850.
384
Haojian Zhuanga4553352010-11-24 11:54:19 +0800385# Marvell PJ4
386config CPU_PJ4
387 bool
388 select CPU_V7
389 select ARM_THUMBEE
390
Linus Torvalds1da177e2005-04-16 15:20:36 -0700391# ARMv6
392config CPU_V6
Russell Kingc7862822011-01-17 18:20:05 +0000393 bool "Support ARM V6 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX
Linus Torvalds1da177e2005-04-16 15:20:36 -0700394 select CPU_32v6
395 select CPU_ABRT_EV6
Kirill A. Shutemov4fb28472009-09-25 13:39:47 +0100396 select CPU_PABRT_V6
Linus Torvalds1da177e2005-04-16 15:20:36 -0700397 select CPU_CACHE_V6
398 select CPU_CACHE_VIPT
Hyok S. Choifefdaa02006-09-26 17:36:37 +0900399 select CPU_CP15_MMU
Catalin Marinas7b4c9652007-07-20 11:42:57 +0100400 select CPU_HAS_ASID if MMU
Hyok S. Choif9c21a62006-06-21 22:26:29 +0100401 select CPU_COPY_V6 if MMU
402 select CPU_TLB_V6 if MMU
Linus Torvalds1da177e2005-04-16 15:20:36 -0700403
Russell King4a5f79e2005-11-03 15:48:21 +0000404# ARMv6k
Russell Kinge399b1a2011-01-17 15:08:32 +0000405config CPU_V6K
Russell Kingc7862822011-01-17 18:20:05 +0000406 bool "Support ARM V6K processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX
Russell Kinge399b1a2011-01-17 15:08:32 +0000407 select CPU_32v6
Russell King60799c62011-01-15 16:25:04 +0000408 select CPU_32v6K
Russell Kinge399b1a2011-01-17 15:08:32 +0000409 select CPU_ABRT_EV6
410 select CPU_PABRT_V6
411 select CPU_CACHE_V6
412 select CPU_CACHE_VIPT
413 select CPU_CP15_MMU
414 select CPU_HAS_ASID if MMU
415 select CPU_COPY_V6 if MMU
416 select CPU_TLB_V6 if MMU
Russell King4a5f79e2005-11-03 15:48:21 +0000417
Catalin Marinas23688e92007-05-08 22:45:26 +0100418# ARMv7
419config CPU_V7
Colin Tuckley1b504bb2009-05-30 13:56:12 +0100420 bool "Support ARM V7 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX
Russell King15490ef2011-02-09 16:33:46 +0000421 select CPU_32v6K
Catalin Marinas23688e92007-05-08 22:45:26 +0100422 select CPU_32v7
423 select CPU_ABRT_EV7
Kirill A. Shutemov4fb28472009-09-25 13:39:47 +0100424 select CPU_PABRT_V7
Catalin Marinas23688e92007-05-08 22:45:26 +0100425 select CPU_CACHE_V7
426 select CPU_CACHE_VIPT
427 select CPU_CP15_MMU
Catalin Marinas2eb8c822007-07-20 11:43:02 +0100428 select CPU_HAS_ASID if MMU
Catalin Marinas23688e92007-05-08 22:45:26 +0100429 select CPU_COPY_V6 if MMU
Catalin Marinas2ccdd1e2007-05-18 11:25:31 +0100430 select CPU_TLB_V7 if MMU
Catalin Marinas23688e92007-05-08 22:45:26 +0100431
Linus Torvalds1da177e2005-04-16 15:20:36 -0700432# Figure out what processor architecture version we should be using.
433# This defines the compiler instruction set which depends on the machine type.
434config CPU_32v3
435 bool
Russell King60b6cf62006-06-19 17:36:43 +0100436 select TLS_REG_EMUL if SMP || !MMU
Russell King48fa14f2006-03-16 14:52:33 +0000437 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
Russell King8762df42011-01-17 15:53:56 +0000438 select CPU_USE_DOMAINS if MMU
Linus Torvalds1da177e2005-04-16 15:20:36 -0700439
440config CPU_32v4
441 bool
Russell King60b6cf62006-06-19 17:36:43 +0100442 select TLS_REG_EMUL if SMP || !MMU
Russell King48fa14f2006-03-16 14:52:33 +0000443 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
Russell King8762df42011-01-17 15:53:56 +0000444 select CPU_USE_DOMAINS if MMU
Linus Torvalds1da177e2005-04-16 15:20:36 -0700445
Lennert Buytenhek260e98e2006-08-28 12:51:20 +0100446config CPU_32v4T
447 bool
448 select TLS_REG_EMUL if SMP || !MMU
449 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
Russell King8762df42011-01-17 15:53:56 +0000450 select CPU_USE_DOMAINS if MMU
Lennert Buytenhek260e98e2006-08-28 12:51:20 +0100451
Linus Torvalds1da177e2005-04-16 15:20:36 -0700452config CPU_32v5
453 bool
Russell King60b6cf62006-06-19 17:36:43 +0100454 select TLS_REG_EMUL if SMP || !MMU
Russell King48fa14f2006-03-16 14:52:33 +0000455 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
Russell King8762df42011-01-17 15:53:56 +0000456 select CPU_USE_DOMAINS if MMU
Linus Torvalds1da177e2005-04-16 15:20:36 -0700457
458config CPU_32v6
459 bool
Catalin Marinas367afaf2007-07-20 11:42:51 +0100460 select TLS_REG_EMUL if !CPU_32v6K && !MMU
Russell King8762df42011-01-17 15:53:56 +0000461 select CPU_USE_DOMAINS if CPU_V6 && MMU
Linus Torvalds1da177e2005-04-16 15:20:36 -0700462
Russell Kinge399b1a2011-01-17 15:08:32 +0000463config CPU_32v6K
Russell King60799c62011-01-15 16:25:04 +0000464 bool
Linus Torvalds1da177e2005-04-16 15:20:36 -0700465
Catalin Marinas23688e92007-05-08 22:45:26 +0100466config CPU_32v7
467 bool
468
Linus Torvalds1da177e2005-04-16 15:20:36 -0700469# The abort model
Hyok S. Choi0f45d7f2006-09-28 21:46:16 +0900470config CPU_ABRT_NOMMU
471 bool
472
Linus Torvalds1da177e2005-04-16 15:20:36 -0700473config CPU_ABRT_EV4
474 bool
475
476config CPU_ABRT_EV4T
477 bool
478
479config CPU_ABRT_LV4T
480 bool
481
482config CPU_ABRT_EV5T
483 bool
484
485config CPU_ABRT_EV5TJ
486 bool
487
488config CPU_ABRT_EV6
489 bool
490
Catalin Marinas23688e92007-05-08 22:45:26 +0100491config CPU_ABRT_EV7
492 bool
493
Kirill A. Shutemov4fb28472009-09-25 13:39:47 +0100494config CPU_PABRT_LEGACY
Paul Brook48d79272008-04-18 22:43:07 +0100495 bool
496
Kirill A. Shutemov4fb28472009-09-25 13:39:47 +0100497config CPU_PABRT_V6
498 bool
499
500config CPU_PABRT_V7
Paul Brook48d79272008-04-18 22:43:07 +0100501 bool
502
Linus Torvalds1da177e2005-04-16 15:20:36 -0700503# The cache model
504config CPU_CACHE_V3
505 bool
506
507config CPU_CACHE_V4
508 bool
509
510config CPU_CACHE_V4WT
511 bool
512
513config CPU_CACHE_V4WB
514 bool
515
516config CPU_CACHE_V6
517 bool
518
Catalin Marinas23688e92007-05-08 22:45:26 +0100519config CPU_CACHE_V7
520 bool
521
Linus Torvalds1da177e2005-04-16 15:20:36 -0700522config CPU_CACHE_VIVT
523 bool
524
525config CPU_CACHE_VIPT
526 bool
527
Paulius Zaleckas28853ac2009-03-25 13:10:01 +0200528config CPU_CACHE_FA
529 bool
530
Hyok S. Choif9c21a62006-06-21 22:26:29 +0100531if MMU
Linus Torvalds1da177e2005-04-16 15:20:36 -0700532# The copy-page model
533config CPU_COPY_V3
534 bool
535
536config CPU_COPY_V4WT
537 bool
538
539config CPU_COPY_V4WB
540 bool
541
Lennert Buytenhek0ed15072008-04-24 01:31:45 -0400542config CPU_COPY_FEROCEON
543 bool
544
Paulius Zaleckas28853ac2009-03-25 13:10:01 +0200545config CPU_COPY_FA
546 bool
547
Linus Torvalds1da177e2005-04-16 15:20:36 -0700548config CPU_COPY_V6
549 bool
550
551# This selects the TLB model
552config CPU_TLB_V3
553 bool
554 help
555 ARM Architecture Version 3 TLB.
556
557config CPU_TLB_V4WT
558 bool
559 help
560 ARM Architecture Version 4 TLB with writethrough cache.
561
562config CPU_TLB_V4WB
563 bool
564 help
565 ARM Architecture Version 4 TLB with writeback cache.
566
567config CPU_TLB_V4WBI
568 bool
569 help
570 ARM Architecture Version 4 TLB with writeback cache and invalidate
571 instruction cache entry.
572
Lennert Buytenhek99c6dc12008-06-22 22:45:04 +0200573config CPU_TLB_FEROCEON
574 bool
575 help
576 Feroceon TLB (v4wbi with non-outer-cachable page table walks).
577
Paulius Zaleckas28853ac2009-03-25 13:10:01 +0200578config CPU_TLB_FA
579 bool
580 help
581 Faraday ARM FA526 architecture, unified TLB with writeback cache
582 and invalidate instruction cache entry. Branch target buffer is
583 also supported.
584
Linus Torvalds1da177e2005-04-16 15:20:36 -0700585config CPU_TLB_V6
586 bool
587
Catalin Marinas2ccdd1e2007-05-18 11:25:31 +0100588config CPU_TLB_V7
589 bool
590
Dave Estese220ba62009-08-11 17:58:49 -0400591config VERIFY_PERMISSION_FAULT
592 bool
Hyok S. Choif9c21a62006-06-21 22:26:29 +0100593endif
594
Russell King516793c2007-05-17 10:19:23 +0100595config CPU_HAS_ASID
596 bool
597 help
598 This indicates whether the CPU has the ASID register; used to
599 tag TLB and possibly cache entries.
600
Hyok S. Choifefdaa02006-09-26 17:36:37 +0900601config CPU_CP15
602 bool
603 help
604 Processor has the CP15 register.
605
606config CPU_CP15_MMU
607 bool
608 select CPU_CP15
609 help
610 Processor has the CP15 register, which has MMU related registers.
611
612config CPU_CP15_MPU
613 bool
614 select CPU_CP15
615 help
616 Processor has the CP15 register, which has MPU related registers.
617
Catalin Marinas247055a2010-09-13 16:03:21 +0100618config CPU_USE_DOMAINS
619 bool
Catalin Marinas247055a2010-09-13 16:03:21 +0100620 help
621 This option enables or disables the use of domain switching
622 via the set_fs() function.
623
Lennert Buytenhek23bdf862006-03-28 21:00:40 +0100624#
625# CPU supports 36-bit I/O
626#
627config IO_36
628 bool
629
Linus Torvalds1da177e2005-04-16 15:20:36 -0700630comment "Processor Features"
631
Catalin Marinas497b7e92011-11-22 17:30:32 +0000632config ARM_LPAE
633 bool "Support for the Large Physical Address Extension"
634 depends on MMU && CPU_V7
635 help
636 Say Y if you have an ARMv7 processor supporting the LPAE page
637 table format and you would like to access memory beyond the
638 4GB limit. The resulting kernel image will not run on
639 processors without the LPA extension.
640
641 If unsure, say N.
642
643config ARCH_PHYS_ADDR_T_64BIT
644 def_bool ARM_LPAE
645
646config ARCH_DMA_ADDR_T_64BIT
647 bool
648
Linus Torvalds1da177e2005-04-16 15:20:36 -0700649config ARM_THUMB
650 bool "Support Thumb user binaries"
Russell Kinge399b1a2011-01-17 15:08:32 +0000651 depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_V6 || CPU_V6K || CPU_V7 || CPU_FEROCEON
Linus Torvalds1da177e2005-04-16 15:20:36 -0700652 default y
653 help
654 Say Y if you want to include kernel support for running user space
655 Thumb binaries.
656
657 The Thumb instruction set is a compressed form of the standard ARM
658 instruction set resulting in smaller binaries at the expense of
659 slightly less efficient code.
660
661 If you don't know what this all is, saying Y is a safe choice.
662
Catalin Marinasd7f864b2008-04-18 22:43:06 +0100663config ARM_THUMBEE
664 bool "Enable ThumbEE CPU extension"
665 depends on CPU_V7
666 help
667 Say Y here if you have a CPU with the ThumbEE extension and code to
668 make use of it. Say N for code that can run on CPUs without ThumbEE.
669
Leif Lindholm64d2dc32010-09-16 18:00:47 +0100670config SWP_EMULATE
671 bool "Emulate SWP/SWPB instructions"
Russell Kingbd1274d2011-03-16 23:35:26 +0000672 depends on !CPU_USE_DOMAINS && CPU_V7
Leif Lindholm64d2dc32010-09-16 18:00:47 +0100673 select HAVE_PROC_CPU if PROC_FS
674 default y if SMP
675 help
676 ARMv6 architecture deprecates use of the SWP/SWPB instructions.
677 ARMv7 multiprocessing extensions introduce the ability to disable
678 these instructions, triggering an undefined instruction exception
679 when executed. Say Y here to enable software emulation of these
680 instructions for userspace (not kernel) using LDREX/STREX.
681 Also creates /proc/cpu/swp_emulation for statistics.
682
683 In some older versions of glibc [<=2.8] SWP is used during futex
684 trylock() operations with the assumption that the code will not
685 be preempted. This invalid assumption may be more likely to fail
686 with SWP emulation enabled, leading to deadlock of the user
687 application.
688
689 NOTE: when accessing uncached shared regions, LDREX/STREX rely
690 on an external transaction monitoring block called a global
691 monitor to maintain update atomicity. If your system does not
692 implement a global monitor, this option can cause programs that
693 perform SWP operations to uncached memory to deadlock.
694
695 If unsure, say Y.
696
Linus Torvalds1da177e2005-04-16 15:20:36 -0700697config CPU_BIG_ENDIAN
698 bool "Build big-endian kernel"
699 depends on ARCH_SUPPORTS_BIG_ENDIAN
700 help
701 Say Y if you plan on running a kernel in big-endian mode.
702 Note that your board must be properly built and your board
703 port must properly enable any big-endian related features
704 of your chipset/board/processor.
705
Catalin Marinas26584852009-05-30 14:00:18 +0100706config CPU_ENDIAN_BE8
707 bool
708 depends on CPU_BIG_ENDIAN
Russell Kinge399b1a2011-01-17 15:08:32 +0000709 default CPU_V6 || CPU_V6K || CPU_V7
Catalin Marinas26584852009-05-30 14:00:18 +0100710 help
711 Support for the BE-8 (big-endian) mode on ARMv6 and ARMv7 processors.
712
713config CPU_ENDIAN_BE32
714 bool
715 depends on CPU_BIG_ENDIAN
716 default !CPU_ENDIAN_BE8
717 help
718 Support for the BE-32 (big-endian) mode on pre-ARMv6 processors.
719
Hyok S. Choi6afd6fa2006-09-28 21:46:34 +0900720config CPU_HIGH_VECTOR
Robert P. J. Day6340aa62007-02-17 19:05:24 +0100721 depends on !MMU && CPU_CP15 && !CPU_ARM740T
Hyok S. Choi6afd6fa2006-09-28 21:46:34 +0900722 bool "Select the High exception vector"
Hyok S. Choi6afd6fa2006-09-28 21:46:34 +0900723 help
724 Say Y here to select high exception vector(0xFFFF0000~).
725 The exception vector can be vary depending on the platform
726 design in nommu mode. If your platform needs to select
727 high exception vector, say Y.
728 Otherwise or if you are unsure, say N, and the low exception
729 vector (0x00000000~) will be used.
730
Linus Torvalds1da177e2005-04-16 15:20:36 -0700731config CPU_ICACHE_DISABLE
Hyok S. Choif12d0d72006-09-26 17:36:37 +0900732 bool "Disable I-Cache (I-bit)"
733 depends on CPU_CP15 && !(CPU_ARM610 || CPU_ARM710 || CPU_ARM720T || CPU_ARM740T || CPU_XSCALE || CPU_XSC3)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700734 help
735 Say Y here to disable the processor instruction cache. Unless
736 you have a reason not to or are unsure, say N.
737
738config CPU_DCACHE_DISABLE
Hyok S. Choif12d0d72006-09-26 17:36:37 +0900739 bool "Disable D-Cache (C-bit)"
740 depends on CPU_CP15
Linus Torvalds1da177e2005-04-16 15:20:36 -0700741 help
742 Say Y here to disable the processor data cache. Unless
743 you have a reason not to or are unsure, say N.
744
Hyok S. Choif37f46e2006-09-26 17:38:32 +0900745config CPU_DCACHE_SIZE
746 hex
747 depends on CPU_ARM740T || CPU_ARM946E
748 default 0x00001000 if CPU_ARM740T
749 default 0x00002000 # default size for ARM946E-S
750 help
751 Some cores are synthesizable to have various sized cache. For
752 ARM946E-S case, it can vary from 0KB to 1MB.
753 To support such cache operations, it is efficient to know the size
754 before compile time.
755 If your SoC is configured to have a different size, define the value
756 here with proper conditions.
757
Linus Torvalds1da177e2005-04-16 15:20:36 -0700758config CPU_DCACHE_WRITETHROUGH
759 bool "Force write through D-cache"
Paulius Zaleckas28853ac2009-03-25 13:10:01 +0200760 depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_FA526) && !CPU_DCACHE_DISABLE
Linus Torvalds1da177e2005-04-16 15:20:36 -0700761 default y if CPU_ARM925T
762 help
763 Say Y here to use the data cache in writethrough mode. Unless you
764 specifically require this or are unsure, say N.
765
766config CPU_CACHE_ROUND_ROBIN
767 bool "Round robin I and D cache replacement algorithm"
Hyok S. Choif37f46e2006-09-26 17:38:32 +0900768 depends on (CPU_ARM926T || CPU_ARM946E || CPU_ARM1020) && (!CPU_ICACHE_DISABLE || !CPU_DCACHE_DISABLE)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700769 help
770 Say Y here to use the predictable round-robin cache replacement
771 policy. Unless you specifically require this or are unsure, say N.
772
773config CPU_BPREDICT_DISABLE
774 bool "Disable branch prediction"
Russell Kinge399b1a2011-01-17 15:08:32 +0000775 depends on CPU_ARM1020 || CPU_V6 || CPU_V6K || CPU_MOHAWK || CPU_XSC3 || CPU_V7 || CPU_FA526
Linus Torvalds1da177e2005-04-16 15:20:36 -0700776 help
777 Say Y here to disable branch prediction. If unsure, say N.
Nicolas Pitre2d2669b2005-04-29 22:08:33 +0100778
Nicolas Pitre4b0e07a2005-05-05 23:24:45 +0100779config TLS_REG_EMUL
780 bool
Nicolas Pitre4b0e07a2005-05-05 23:24:45 +0100781 help
Nicolas Pitre70489c82005-05-12 19:27:12 +0100782 An SMP system using a pre-ARMv6 processor (there are apparently
783 a few prototypes like that in existence) and therefore access to
784 that required register must be emulated.
Nicolas Pitre4b0e07a2005-05-05 23:24:45 +0100785
Nicolas Pitredcef1f62005-06-08 19:00:47 +0100786config NEEDS_SYSCALL_FOR_CMPXCHG
787 bool
Nicolas Pitredcef1f62005-06-08 19:00:47 +0100788 help
789 SMP on a pre-ARMv6 processor? Well OK then.
790 Forget about fast user space cmpxchg support.
791 It is just not possible.
792
Catalin Marinasad642d92010-06-21 15:10:07 +0100793config DMA_CACHE_RWFO
794 bool "Enable read/write for ownership DMA cache maintenance"
Russell King3bc28c82011-01-18 13:30:33 +0000795 depends on CPU_V6K && SMP
Catalin Marinasad642d92010-06-21 15:10:07 +0100796 default y
797 help
798 The Snoop Control Unit on ARM11MPCore does not detect the
799 cache maintenance operations and the dma_{map,unmap}_area()
800 functions may leave stale cache entries on other CPUs. By
801 enabling this option, Read or Write For Ownership in the ARMv6
802 DMA cache maintenance functions is performed. These LDR/STR
803 instructions change the cache line state to shared or modified
804 so that the cache operation has the desired effect.
805
806 Note that the workaround is only valid on processors that do
807 not perform speculative loads into the D-cache. For such
808 processors, if cache maintenance operations are not broadcast
809 in hardware, other workarounds are needed (e.g. cache
810 maintenance broadcasting in software via FIQ).
811
Catalin Marinas953233d2007-02-05 14:48:08 +0100812config OUTER_CACHE
813 bool
Catalin Marinas382266a2007-02-05 14:48:19 +0100814
Catalin Marinas319f5512010-03-24 16:47:53 +0100815config OUTER_CACHE_SYNC
816 bool
817 help
818 The outer cache has a outer_cache_fns.sync function pointer
819 that can be used to drain the write buffer of the outer cache.
820
Lennert Buytenhek99c6dc12008-06-22 22:45:04 +0200821config CACHE_FEROCEON_L2
822 bool "Enable the Feroceon L2 cache controller"
Stanislav Samsonov794d15b2008-06-22 22:45:10 +0200823 depends on ARCH_KIRKWOOD || ARCH_MV78XX0
Lennert Buytenhek99c6dc12008-06-22 22:45:04 +0200824 default y
Catalin Marinas382266a2007-02-05 14:48:19 +0100825 select OUTER_CACHE
Lennert Buytenhek99c6dc12008-06-22 22:45:04 +0200826 help
827 This option enables the Feroceon L2 cache controller.
828
Ronen Shitrit4360bb42008-09-23 15:28:10 +0300829config CACHE_FEROCEON_L2_WRITETHROUGH
830 bool "Force Feroceon L2 cache write through"
831 depends on CACHE_FEROCEON_L2
Ronen Shitrit4360bb42008-09-23 15:28:10 +0300832 help
833 Say Y here to use the Feroceon L2 cache in writethrough mode.
834 Unless you specifically require this, say N for writeback mode.
835
Dave Martince5ea9f2011-11-29 15:56:19 +0000836config MIGHT_HAVE_CACHE_L2X0
837 bool
838 help
839 This option should be selected by machines which have a L2x0
840 or PL310 cache controller, but where its use is optional.
841
842 The only effect of this option is to make CACHE_L2X0 and
843 related options available to the user for configuration.
844
845 Boards or SoCs which always require the cache controller
846 support to be present should select CACHE_L2X0 directly
847 instead of this option, thus preventing the user from
848 inadvertently configuring a broken kernel.
849
Linus Torvalds1da177e2005-04-16 15:20:36 -0700850config CACHE_L2X0
Dave Martince5ea9f2011-11-29 15:56:19 +0000851 bool "Enable the L2x0 outer cache controller" if MIGHT_HAVE_CACHE_L2X0
852 default MIGHT_HAVE_CACHE_L2X0
Linus Torvalds1da177e2005-04-16 15:20:36 -0700853 select OUTER_CACHE
Catalin Marinas23107c52010-03-24 16:48:53 +0100854 select OUTER_CACHE_SYNC
Catalin Marinasba927952008-04-18 22:43:17 +0100855 help
856 This option enables the L2x0 PrimeCell.
Eric Miao905a09d2008-06-06 16:34:03 +0800857
Catalin Marinas9a6655e2010-08-31 13:05:22 +0100858config CACHE_PL310
859 bool
860 depends on CACHE_L2X0
Russell Kinge399b1a2011-01-17 15:08:32 +0000861 default y if CPU_V7 && !(CPU_V6 || CPU_V6K)
Catalin Marinas9a6655e2010-08-31 13:05:22 +0100862 help
863 This option enables optimisations for the PL310 cache
864 controller.
865
Lennert Buytenhek573a6522009-11-24 19:33:52 +0200866config CACHE_TAUROS2
867 bool "Enable the Tauros2 L2 cache controller"
Haojian Zhuang3f408fa2010-11-24 11:54:21 +0800868 depends on (ARCH_DOVE || ARCH_MMP || CPU_PJ4)
Lennert Buytenhek573a6522009-11-24 19:33:52 +0200869 default y
870 select OUTER_CACHE
871 help
872 This option enables the Tauros2 L2 cache controller (as
873 found on PJ1/PJ4).
874
Eric Miao905a09d2008-06-06 16:34:03 +0800875config CACHE_XSC3L2
876 bool "Enable the L2 cache on XScale3"
877 depends on CPU_XSC3
878 default y
879 select OUTER_CACHE
880 help
881 This option enables the L2 cache on XScale3.
Kirill A. Shutemov910a17e2009-09-15 10:23:53 +0100882
Russell King5637a122011-02-14 15:55:45 +0000883config ARM_L1_CACHE_SHIFT_6
884 bool
Will Deacona092f2b2012-01-20 12:01:10 +0100885 default y if CPU_V7
Russell King5637a122011-02-14 15:55:45 +0000886 help
887 Setting ARM L1 cache line size to 64 Bytes.
888
Kirill A. Shutemov910a17e2009-09-15 10:23:53 +0100889config ARM_L1_CACHE_SHIFT
890 int
Kukjin Kimd6d502f2010-02-22 00:02:59 +0100891 default 6 if ARM_L1_CACHE_SHIFT_6
Kirill A. Shutemov910a17e2009-09-15 10:23:53 +0100892 default 5
Russell King47ab0de2010-05-15 11:02:43 +0100893
894config ARM_DMA_MEM_BUFFERABLE
Russell Kinge399b1a2011-01-17 15:08:32 +0000895 bool "Use non-cacheable memory for DMA" if (CPU_V6 || CPU_V6K) && !CPU_V7
Catalin Marinas42c4daf2010-07-01 13:22:48 +0100896 depends on !(MACH_REALVIEW_PB1176 || REALVIEW_EB_ARM11MP || \
897 MACH_REALVIEW_PB11MP)
Russell Kinge399b1a2011-01-17 15:08:32 +0000898 default y if CPU_V6 || CPU_V6K || CPU_V7
Russell King47ab0de2010-05-15 11:02:43 +0100899 help
900 Historically, the kernel has used strongly ordered mappings to
901 provide DMA coherent memory. With the advent of ARMv7, mapping
902 memory with differing types results in unpredictable behaviour,
903 so on these CPUs, this option is forced on.
904
905 Multiple mappings with differing attributes is also unpredictable
906 on ARMv6 CPUs, but since they do not have aggressive speculative
907 prefetch, no harm appears to occur.
908
909 However, drivers may be missing the necessary barriers for ARMv6,
910 and therefore turning this on may result in unpredictable driver
911 behaviour. Therefore, we offer this as an option.
912
913 You are recommended say 'Y' here and debug any affected drivers.
Russell Kingac1d4262010-05-17 17:24:04 +0100914
Catalin Marinase7c56502010-03-24 16:49:54 +0100915config ARCH_HAS_BARRIERS
916 bool
917 help
918 This option allows the use of custom mandatory barriers
919 included via the mach/barriers.h file.