Banajit Goswami | b016de9 | 2017-02-15 21:02:30 -0800 | [diff] [blame] | 1 | /* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. |
Kyle Yan | 679cbee | 2016-07-27 16:55:20 -0700 | [diff] [blame] | 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | */ |
| 12 | |
| 13 | &soc { |
Channagoud Kadabi | eb7f011 | 2017-04-03 20:39:27 -0700 | [diff] [blame] | 14 | tlmm: pinctrl@03400000 { |
Kyle Yan | 6a20fae | 2017-02-14 13:34:41 -0800 | [diff] [blame] | 15 | compatible = "qcom,sdm845-pinctrl"; |
Channagoud Kadabi | eb7f011 | 2017-04-03 20:39:27 -0700 | [diff] [blame] | 16 | reg = <0x03400000 0xc00000>; |
Kyle Yan | 679cbee | 2016-07-27 16:55:20 -0700 | [diff] [blame] | 17 | interrupts = <0 208 0>; |
| 18 | gpio-controller; |
| 19 | #gpio-cells = <2>; |
| 20 | interrupt-controller; |
| 21 | #interrupt-cells = <2>; |
Banajit Goswami | b016de9 | 2017-02-15 21:02:30 -0800 | [diff] [blame] | 22 | |
Subhash Jadavani | afe2a79 | 2017-03-31 21:08:29 -0700 | [diff] [blame] | 23 | ufs_dev_reset_assert: ufs_dev_reset_assert { |
| 24 | config { |
| 25 | pins = "ufs_reset"; |
| 26 | bias-pull-down; /* default: pull down */ |
| 27 | /* |
| 28 | * UFS_RESET driver strengths are having |
| 29 | * different values/steps compared to typical |
| 30 | * GPIO drive strengths. |
| 31 | * |
| 32 | * Following table clarifies: |
| 33 | * |
| 34 | * HDRV value | UFS_RESET | Typical GPIO |
| 35 | * (dec) | (mA) | (mA) |
| 36 | * 0 | 0.8 | 2 |
| 37 | * 1 | 1.55 | 4 |
| 38 | * 2 | 2.35 | 6 |
| 39 | * 3 | 3.1 | 8 |
| 40 | * 4 | 3.9 | 10 |
| 41 | * 5 | 4.65 | 12 |
| 42 | * 6 | 5.4 | 14 |
| 43 | * 7 | 6.15 | 16 |
| 44 | * |
| 45 | * POR value for UFS_RESET HDRV is 3 which means |
| 46 | * 3.1mA and we want to use that. Hence just |
| 47 | * specify 8mA to "drive-strength" binding and |
| 48 | * that should result into writing 3 to HDRV |
| 49 | * field. |
| 50 | */ |
| 51 | drive-strength = <8>; /* default: 3.1 mA */ |
| 52 | output-low; /* active low reset */ |
| 53 | }; |
| 54 | }; |
| 55 | |
| 56 | ufs_dev_reset_deassert: ufs_dev_reset_deassert { |
| 57 | config { |
| 58 | pins = "ufs_reset"; |
| 59 | bias-pull-down; /* default: pull down */ |
| 60 | /* |
| 61 | * default: 3.1 mA |
| 62 | * check comments under ufs_dev_reset_assert |
| 63 | */ |
| 64 | drive-strength = <8>; |
| 65 | output-high; /* active low reset */ |
| 66 | }; |
| 67 | }; |
| 68 | |
Subbaraman Narayanamurthy | cd21c81 | 2017-03-30 18:36:49 -0700 | [diff] [blame] | 69 | flash_led3_front { |
| 70 | flash_led3_front_en: flash_led3_front_en { |
| 71 | mux { |
| 72 | pins = "gpio21"; |
Subbaraman Narayanamurthy | 58377f0 | 2017-03-21 20:38:43 -0700 | [diff] [blame] | 73 | function = "gpio"; |
| 74 | }; |
| 75 | |
| 76 | config { |
| 77 | pins = "gpio21"; |
Subbaraman Narayanamurthy | cd21c81 | 2017-03-30 18:36:49 -0700 | [diff] [blame] | 78 | drive_strength = <2>; |
| 79 | output-high; |
Subbaraman Narayanamurthy | 58377f0 | 2017-03-21 20:38:43 -0700 | [diff] [blame] | 80 | bias-disable; |
Subbaraman Narayanamurthy | cd21c81 | 2017-03-30 18:36:49 -0700 | [diff] [blame] | 81 | }; |
| 82 | }; |
| 83 | |
| 84 | flash_led3_front_dis: flash_led3_front_dis { |
| 85 | mux { |
| 86 | pins = "gpio21"; |
Subbaraman Narayanamurthy | 58377f0 | 2017-03-21 20:38:43 -0700 | [diff] [blame] | 87 | function = "gpio"; |
| 88 | }; |
| 89 | |
| 90 | config { |
| 91 | pins = "gpio21"; |
Subbaraman Narayanamurthy | cd21c81 | 2017-03-30 18:36:49 -0700 | [diff] [blame] | 92 | drive_strength = <2>; |
| 93 | output-low; |
Subbaraman Narayanamurthy | 58377f0 | 2017-03-21 20:38:43 -0700 | [diff] [blame] | 94 | bias-disable; |
Subbaraman Narayanamurthy | cd21c81 | 2017-03-30 18:36:49 -0700 | [diff] [blame] | 95 | }; |
| 96 | }; |
| 97 | }; |
Subhash Jadavani | afe2a79 | 2017-03-31 21:08:29 -0700 | [diff] [blame] | 98 | |
Banajit Goswami | b016de9 | 2017-02-15 21:02:30 -0800 | [diff] [blame] | 99 | wcd9xxx_intr { |
| 100 | wcd_intr_default: wcd_intr_default{ |
| 101 | mux { |
| 102 | pins = "gpio54"; |
| 103 | function = "gpio"; |
| 104 | }; |
| 105 | |
| 106 | config { |
| 107 | pins = "gpio54"; |
| 108 | drive-strength = <2>; /* 2 mA */ |
| 109 | bias-pull-down; /* pull down */ |
| 110 | input-enable; |
| 111 | }; |
| 112 | }; |
| 113 | }; |
| 114 | |
Xiaonian Wang | 898e090 | 2017-04-08 06:46:29 +0800 | [diff] [blame] | 115 | sdc2_clk_on: sdc2_clk_on { |
| 116 | config { |
| 117 | pins = "sdc2_clk"; |
| 118 | bias-disable; /* NO pull */ |
| 119 | drive-strength = <16>; /* 16 MA */ |
| 120 | }; |
| 121 | }; |
| 122 | |
| 123 | sdc2_clk_off: sdc2_clk_off { |
| 124 | config { |
| 125 | pins = "sdc2_clk"; |
| 126 | bias-disable; /* NO pull */ |
| 127 | drive-strength = <2>; /* 2 MA */ |
| 128 | }; |
| 129 | }; |
| 130 | |
| 131 | sdc2_cmd_on: sdc2_cmd_on { |
| 132 | config { |
| 133 | pins = "sdc2_cmd"; |
| 134 | bias-pull-up; /* pull up */ |
| 135 | drive-strength = <10>; /* 10 MA */ |
| 136 | }; |
| 137 | }; |
| 138 | |
| 139 | sdc2_cmd_off: sdc2_cmd_off { |
| 140 | config { |
| 141 | pins = "sdc2_cmd"; |
| 142 | bias-pull-up; /* pull up */ |
| 143 | drive-strength = <2>; /* 2 MA */ |
| 144 | }; |
| 145 | }; |
| 146 | |
| 147 | sdc2_data_on: sdc2_data_on { |
| 148 | config { |
| 149 | pins = "sdc2_data"; |
| 150 | bias-pull-up; /* pull up */ |
| 151 | drive-strength = <10>; /* 10 MA */ |
| 152 | }; |
| 153 | }; |
| 154 | |
| 155 | sdc2_data_off: sdc2_data_off { |
| 156 | config { |
| 157 | pins = "sdc2_data"; |
| 158 | bias-pull-up; /* pull up */ |
| 159 | drive-strength = <2>; /* 2 MA */ |
| 160 | }; |
| 161 | }; |
| 162 | |
Banajit Goswami | b016de9 | 2017-02-15 21:02:30 -0800 | [diff] [blame] | 163 | cdc_reset_ctrl { |
| 164 | cdc_reset_sleep: cdc_reset_sleep { |
| 165 | mux { |
| 166 | pins = "gpio64"; |
| 167 | function = "gpio"; |
| 168 | }; |
| 169 | config { |
| 170 | pins = "gpio64"; |
| 171 | drive-strength = <2>; |
| 172 | bias-disable; |
| 173 | output-low; |
| 174 | }; |
| 175 | }; |
| 176 | |
| 177 | cdc_reset_active:cdc_reset_active { |
| 178 | mux { |
| 179 | pins = "gpio64"; |
| 180 | function = "gpio"; |
| 181 | }; |
| 182 | config { |
| 183 | pins = "gpio64"; |
| 184 | drive-strength = <8>; |
| 185 | bias-pull-down; |
| 186 | output-high; |
| 187 | }; |
| 188 | }; |
| 189 | }; |
| 190 | |
| 191 | spkr_i2s_clk_pin { |
| 192 | spkr_i2s_clk_sleep: spkr_i2s_clk_sleep { |
| 193 | mux { |
| 194 | pins = "gpio69"; |
| 195 | function = "spkr_i2s"; |
| 196 | }; |
| 197 | |
| 198 | config { |
| 199 | pins = "gpio69"; |
| 200 | drive-strength = <2>; /* 2 mA */ |
| 201 | bias-pull-down; /* PULL DOWN */ |
| 202 | }; |
| 203 | }; |
| 204 | |
| 205 | spkr_i2s_clk_active: spkr_i2s_clk_active { |
| 206 | mux { |
| 207 | pins = "gpio69"; |
| 208 | function = "spkr_i2s"; |
| 209 | }; |
| 210 | |
| 211 | config { |
| 212 | pins = "gpio69"; |
| 213 | drive-strength = <8>; /* 8 mA */ |
| 214 | bias-disable; /* NO PULL */ |
| 215 | }; |
| 216 | }; |
| 217 | }; |
| 218 | |
| 219 | wcd_gnd_mic_swap { |
| 220 | wcd_gnd_mic_swap_idle: wcd_gnd_mic_swap_idle { |
| 221 | mux { |
| 222 | pins = "gpio51"; |
| 223 | function = "gpio"; |
| 224 | }; |
| 225 | config { |
| 226 | pins = "gpio51"; |
| 227 | drive-strength = <2>; |
| 228 | bias-pull-down; |
| 229 | output-low; |
| 230 | }; |
| 231 | }; |
| 232 | |
| 233 | wcd_gnd_mic_swap_active: wcd_gnd_mic_swap_active { |
| 234 | mux { |
| 235 | pins = "gpio51"; |
| 236 | function = "gpio"; |
| 237 | }; |
| 238 | config { |
| 239 | pins = "gpio51"; |
| 240 | drive-strength = <2>; |
| 241 | bias-disable; |
| 242 | output-high; |
| 243 | }; |
| 244 | }; |
| 245 | }; |
| 246 | |
| 247 | pri_aux_pcm_clk { |
| 248 | pri_aux_pcm_clk_sleep: pri_aux_pcm_clk_sleep { |
| 249 | mux { |
| 250 | pins = "gpio65"; |
| 251 | function = "gpio"; |
| 252 | }; |
| 253 | |
| 254 | config { |
| 255 | pins = "gpio65"; |
| 256 | drive-strength = <2>; /* 2 mA */ |
| 257 | bias-pull-down; /* PULL DOWN */ |
| 258 | input-enable; |
| 259 | }; |
| 260 | }; |
| 261 | |
| 262 | pri_aux_pcm_clk_active: pri_aux_pcm_clk_active { |
| 263 | mux { |
| 264 | pins = "gpio65"; |
| 265 | function = "pri_mi2s"; |
| 266 | }; |
| 267 | |
| 268 | config { |
| 269 | pins = "gpio65"; |
| 270 | drive-strength = <8>; /* 8 mA */ |
| 271 | bias-disable; /* NO PULL */ |
| 272 | output-high; |
| 273 | }; |
| 274 | }; |
| 275 | }; |
| 276 | |
| 277 | pri_aux_pcm_sync { |
| 278 | pri_aux_pcm_sync_sleep: pri_aux_pcm_sync_sleep { |
| 279 | mux { |
| 280 | pins = "gpio66"; |
| 281 | function = "gpio"; |
| 282 | }; |
| 283 | |
| 284 | config { |
| 285 | pins = "gpio66"; |
| 286 | drive-strength = <2>; /* 2 mA */ |
| 287 | bias-pull-down; /* PULL DOWN */ |
| 288 | input-enable; |
| 289 | }; |
| 290 | }; |
| 291 | |
| 292 | pri_aux_pcm_sync_active: pri_aux_pcm_sync_active { |
| 293 | mux { |
| 294 | pins = "gpio66"; |
| 295 | function = "pri_mi2s_ws"; |
| 296 | }; |
| 297 | |
| 298 | config { |
| 299 | pins = "gpio66"; |
| 300 | drive-strength = <8>; /* 8 mA */ |
| 301 | bias-disable; /* NO PULL */ |
| 302 | output-high; |
| 303 | }; |
| 304 | }; |
| 305 | }; |
| 306 | |
| 307 | pri_aux_pcm_din { |
| 308 | pri_aux_pcm_din_sleep: pri_aux_pcm_din_sleep { |
| 309 | mux { |
| 310 | pins = "gpio67"; |
| 311 | function = "gpio"; |
| 312 | }; |
| 313 | |
| 314 | config { |
| 315 | pins = "gpio67"; |
| 316 | drive-strength = <2>; /* 2 mA */ |
| 317 | bias-pull-down; /* PULL DOWN */ |
| 318 | input-enable; |
| 319 | }; |
| 320 | }; |
| 321 | |
| 322 | pri_aux_pcm_din_active: pri_aux_pcm_din_active { |
| 323 | mux { |
| 324 | pins = "gpio67"; |
| 325 | function = "pri_mi2s"; |
| 326 | }; |
| 327 | |
| 328 | config { |
| 329 | pins = "gpio67"; |
| 330 | drive-strength = <8>; /* 8 mA */ |
| 331 | bias-disable; /* NO PULL */ |
| 332 | }; |
| 333 | }; |
| 334 | }; |
| 335 | |
| 336 | pri_aux_pcm_dout { |
| 337 | pri_aux_pcm_dout_sleep: pri_aux_pcm_dout_sleep { |
| 338 | mux { |
| 339 | pins = "gpio68"; |
| 340 | function = "gpio"; |
| 341 | }; |
| 342 | |
| 343 | config { |
| 344 | pins = "gpio68"; |
| 345 | drive-strength = <2>; /* 2 mA */ |
| 346 | bias-pull-down; /* PULL DOWN */ |
| 347 | input-enable; |
| 348 | }; |
| 349 | }; |
| 350 | |
| 351 | pri_aux_pcm_dout_active: pri_aux_pcm_dout_active { |
| 352 | mux { |
| 353 | pins = "gpio68"; |
| 354 | function = "pri_mi2s"; |
| 355 | }; |
| 356 | |
| 357 | config { |
| 358 | pins = "gpio68"; |
| 359 | drive-strength = <8>; /* 8 mA */ |
| 360 | bias-disable; /* NO PULL */ |
| 361 | }; |
| 362 | }; |
| 363 | }; |
| 364 | |
Shashank Babu Chinta Venkata | 2f40bc7 | 2017-03-21 15:31:38 -0700 | [diff] [blame] | 365 | pmx_sde: pmx_sde { |
| 366 | sde_dsi_active: sde_dsi_active { |
| 367 | mux { |
| 368 | pins = "gpio6", "gpio52"; |
| 369 | function = "gpio"; |
| 370 | }; |
| 371 | |
| 372 | config { |
| 373 | pins = "gpio6", "gpio52"; |
| 374 | drive-strength = <8>; /* 8 mA */ |
| 375 | bias-disable = <0>; /* no pull */ |
| 376 | }; |
| 377 | }; |
| 378 | sde_dsi_suspend: sde_dsi_suspend { |
| 379 | mux { |
| 380 | pins = "gpio6", "gpio52"; |
| 381 | function = "gpio"; |
| 382 | }; |
| 383 | |
| 384 | config { |
| 385 | pins = "gpio6", "gpio52"; |
| 386 | drive-strength = <2>; /* 2 mA */ |
| 387 | bias-pull-down; /* PULL DOWN */ |
| 388 | }; |
| 389 | }; |
| 390 | }; |
| 391 | |
| 392 | pmx_sde_te { |
| 393 | sde_te_active: sde_te_active { |
| 394 | mux { |
| 395 | pins = "gpio10"; |
| 396 | function = "mdp_vsync"; |
| 397 | }; |
| 398 | |
| 399 | config { |
| 400 | pins = "gpio10"; |
| 401 | drive-strength = <2>; /* 2 mA */ |
| 402 | bias-pull-down; /* PULL DOWN */ |
| 403 | }; |
| 404 | }; |
| 405 | |
| 406 | sde_te_suspend: sde_te_suspend { |
| 407 | mux { |
| 408 | pins = "gpio10"; |
| 409 | function = "mdp_vsync"; |
| 410 | }; |
| 411 | |
| 412 | config { |
| 413 | pins = "gpio10"; |
| 414 | drive-strength = <2>; /* 2 mA */ |
| 415 | bias-pull-down; /* PULL DOWN */ |
| 416 | }; |
| 417 | }; |
| 418 | }; |
| 419 | |
Padmanabhan Komanduru | 887085e | 2017-05-02 14:57:12 -0700 | [diff] [blame^] | 420 | sde_dp_aux_active: sde_dp_aux_active { |
| 421 | mux { |
| 422 | pins = "gpio43", "gpio51"; |
| 423 | function = "gpio"; |
| 424 | }; |
| 425 | |
| 426 | config { |
| 427 | pins = "gpio43", "gpio51"; |
| 428 | bias-disable = <0>; /* no pull */ |
| 429 | drive-strength = <8>; |
| 430 | }; |
| 431 | }; |
| 432 | |
| 433 | sde_dp_aux_suspend: sde_dp_aux_suspend { |
| 434 | mux { |
| 435 | pins = "gpio43", "gpio51"; |
| 436 | function = "gpio"; |
| 437 | }; |
| 438 | |
| 439 | config { |
| 440 | pins = "gpio43", "gpio51"; |
| 441 | bias-pull-down; |
| 442 | drive-strength = <2>; |
| 443 | }; |
| 444 | }; |
| 445 | |
| 446 | sde_dp_usbplug_cc_active: sde_dp_usbplug_cc_active { |
| 447 | mux { |
| 448 | pins = "gpio38"; |
| 449 | function = "gpio"; |
| 450 | }; |
| 451 | |
| 452 | config { |
| 453 | pins = "gpio38"; |
| 454 | bias-disable; |
| 455 | drive-strength = <16>; |
| 456 | }; |
| 457 | }; |
| 458 | |
| 459 | sde_dp_usbplug_cc_suspend: sde_dp_usbplug_cc_suspend { |
| 460 | mux { |
| 461 | pins = "gpio38"; |
| 462 | function = "gpio"; |
| 463 | }; |
| 464 | |
| 465 | config { |
| 466 | pins = "gpio38"; |
| 467 | bias-pull-down; |
| 468 | drive-strength = <2>; |
| 469 | }; |
| 470 | }; |
| 471 | |
Banajit Goswami | b016de9 | 2017-02-15 21:02:30 -0800 | [diff] [blame] | 472 | sec_aux_pcm { |
| 473 | sec_aux_pcm_sleep: sec_aux_pcm_sleep { |
| 474 | mux { |
| 475 | pins = "gpio80", "gpio81"; |
| 476 | function = "gpio"; |
| 477 | }; |
| 478 | |
| 479 | config { |
| 480 | pins = "gpio80", "gpio81"; |
| 481 | drive-strength = <2>; /* 2 mA */ |
| 482 | bias-pull-down; /* PULL DOWN */ |
| 483 | input-enable; |
| 484 | }; |
| 485 | }; |
| 486 | |
| 487 | sec_aux_pcm_active: sec_aux_pcm_active { |
| 488 | mux { |
| 489 | pins = "gpio80", "gpio81"; |
| 490 | function = "sec_mi2s"; |
| 491 | }; |
| 492 | |
| 493 | config { |
| 494 | pins = "gpio80", "gpio81"; |
| 495 | drive-strength = <8>; /* 8 mA */ |
| 496 | bias-disable; /* NO PULL */ |
| 497 | }; |
| 498 | }; |
| 499 | }; |
| 500 | |
| 501 | sec_aux_pcm_din { |
| 502 | sec_aux_pcm_din_sleep: sec_aux_pcm_din_sleep { |
| 503 | mux { |
| 504 | pins = "gpio82"; |
| 505 | function = "gpio"; |
| 506 | }; |
| 507 | |
| 508 | config { |
| 509 | pins = "gpio82"; |
| 510 | drive-strength = <2>; /* 2 mA */ |
| 511 | bias-pull-down; /* PULL DOWN */ |
| 512 | input-enable; |
| 513 | }; |
| 514 | }; |
| 515 | |
| 516 | sec_aux_pcm_din_active: sec_aux_pcm_din_active { |
| 517 | mux { |
| 518 | pins = "gpio82"; |
| 519 | function = "sec_mi2s"; |
| 520 | }; |
| 521 | |
| 522 | config { |
| 523 | pins = "gpio82"; |
| 524 | drive-strength = <8>; /* 8 mA */ |
| 525 | bias-disable; /* NO PULL */ |
| 526 | }; |
| 527 | }; |
| 528 | }; |
| 529 | |
| 530 | sec_aux_pcm_dout { |
| 531 | sec_aux_pcm_dout_sleep: sec_aux_pcm_dout_sleep { |
| 532 | mux { |
| 533 | pins = "gpio83"; |
| 534 | function = "gpio"; |
| 535 | }; |
| 536 | |
| 537 | config { |
| 538 | pins = "gpio83"; |
| 539 | drive-strength = <2>; /* 2 mA */ |
| 540 | bias-pull-down; /* PULL DOWN */ |
| 541 | input-enable; |
| 542 | }; |
| 543 | }; |
| 544 | |
| 545 | sec_aux_pcm_dout_active: sec_aux_pcm_dout_active { |
| 546 | mux { |
| 547 | pins = "gpio83"; |
| 548 | function = "sec_mi2s"; |
| 549 | }; |
| 550 | |
| 551 | config { |
| 552 | pins = "gpio83"; |
| 553 | drive-strength = <8>; /* 8 mA */ |
| 554 | bias-disable; /* NO PULL */ |
| 555 | }; |
| 556 | }; |
| 557 | }; |
| 558 | |
| 559 | tert_aux_pcm { |
| 560 | tert_aux_pcm_sleep: tert_aux_pcm_sleep { |
| 561 | mux { |
| 562 | pins = "gpio75", "gpio76"; |
| 563 | function = "gpio"; |
| 564 | }; |
| 565 | |
| 566 | config { |
| 567 | pins = "gpio75", "gpio76"; |
| 568 | drive-strength = <2>; /* 2 mA */ |
| 569 | bias-pull-down; /* PULL DOWN */ |
| 570 | input-enable; |
| 571 | }; |
| 572 | }; |
| 573 | |
| 574 | tert_aux_pcm_active: tert_aux_pcm_active { |
| 575 | mux { |
| 576 | pins = "gpio75", "gpio76"; |
| 577 | function = "ter_mi2s"; |
| 578 | }; |
| 579 | |
| 580 | config { |
| 581 | pins = "gpio75", "gpio76"; |
| 582 | drive-strength = <8>; /* 8 mA */ |
| 583 | bias-disable; /* NO PULL */ |
| 584 | output-high; |
| 585 | }; |
| 586 | }; |
| 587 | }; |
| 588 | |
| 589 | tert_aux_pcm_din { |
| 590 | tert_aux_pcm_din_sleep: tert_aux_pcm_din_sleep { |
| 591 | mux { |
| 592 | pins = "gpio77"; |
| 593 | function = "gpio"; |
| 594 | }; |
| 595 | |
| 596 | config { |
| 597 | pins = "gpio77"; |
| 598 | drive-strength = <2>; /* 2 mA */ |
| 599 | bias-pull-down; /* PULL DOWN */ |
| 600 | input-enable; |
| 601 | }; |
| 602 | }; |
| 603 | |
| 604 | tert_aux_pcm_din_active: tert_aux_pcm_din_active { |
| 605 | mux { |
| 606 | pins = "gpio77"; |
| 607 | function = "ter_mi2s"; |
| 608 | }; |
| 609 | |
| 610 | config { |
| 611 | pins = "gpio77"; |
| 612 | drive-strength = <8>; /* 8 mA */ |
| 613 | bias-disable; /* NO PULL */ |
| 614 | }; |
| 615 | }; |
| 616 | }; |
| 617 | |
| 618 | tert_aux_pcm_dout { |
| 619 | tert_aux_pcm_dout_sleep: tert_aux_pcm_dout_sleep { |
| 620 | mux { |
| 621 | pins = "gpio78"; |
| 622 | function = "gpio"; |
| 623 | }; |
| 624 | |
| 625 | config { |
| 626 | pins = "gpio78"; |
| 627 | drive-strength = <2>; /* 2 mA */ |
| 628 | bias-pull-down; /* PULL DOWN */ |
| 629 | input-enable; |
| 630 | }; |
| 631 | }; |
| 632 | |
| 633 | tert_aux_pcm_dout_active: tert_aux_pcm_dout_active { |
| 634 | mux { |
| 635 | pins = "gpio78"; |
| 636 | function = "ter_mi2s"; |
| 637 | }; |
| 638 | |
| 639 | config { |
| 640 | pins = "gpio78"; |
| 641 | drive-strength = <8>; /* 8 mA */ |
| 642 | bias-disable; /* NO PULL */ |
| 643 | }; |
| 644 | }; |
| 645 | }; |
| 646 | |
| 647 | quat_aux_pcm { |
| 648 | quat_aux_pcm_sleep: quat_aux_pcm_sleep { |
| 649 | mux { |
| 650 | pins = "gpio58", "gpio59"; |
| 651 | function = "gpio"; |
| 652 | }; |
| 653 | |
| 654 | config { |
| 655 | pins = "gpio58", "gpio59"; |
| 656 | drive-strength = <2>; /* 2 mA */ |
| 657 | bias-pull-down; /* PULL DOWN */ |
| 658 | input-enable; |
| 659 | }; |
| 660 | }; |
| 661 | |
| 662 | quat_aux_pcm_active: quat_aux_pcm_active { |
| 663 | mux { |
| 664 | pins = "gpio58", "gpio59"; |
| 665 | function = "qua_mi2s"; |
| 666 | }; |
| 667 | |
| 668 | config { |
| 669 | pins = "gpio58", "gpio59"; |
| 670 | drive-strength = <8>; /* 8 mA */ |
| 671 | bias-disable; /* NO PULL */ |
| 672 | output-high; |
| 673 | }; |
| 674 | }; |
| 675 | }; |
| 676 | |
| 677 | quat_aux_pcm_din { |
| 678 | quat_aux_pcm_din_sleep: quat_aux_pcm_din_sleep { |
| 679 | mux { |
| 680 | pins = "gpio60"; |
| 681 | function = "gpio"; |
| 682 | }; |
| 683 | |
| 684 | config { |
| 685 | pins = "gpio60"; |
| 686 | drive-strength = <2>; /* 2 mA */ |
| 687 | bias-pull-down; /* PULL DOWN */ |
| 688 | input-enable; |
| 689 | }; |
| 690 | }; |
| 691 | |
| 692 | quat_aux_pcm_din_active: quat_aux_pcm_din_active { |
| 693 | mux { |
| 694 | pins = "gpio60"; |
| 695 | function = "qua_mi2s"; |
| 696 | }; |
| 697 | |
| 698 | config { |
| 699 | pins = "gpio60"; |
| 700 | drive-strength = <8>; /* 8 mA */ |
| 701 | bias-disable; /* NO PULL */ |
| 702 | }; |
| 703 | }; |
| 704 | }; |
| 705 | |
| 706 | quat_aux_pcm_dout { |
| 707 | quat_aux_pcm_dout_sleep: quat_aux_pcm_dout_sleep { |
| 708 | mux { |
| 709 | pins = "gpio61"; |
| 710 | function = "gpio"; |
| 711 | }; |
| 712 | |
| 713 | config { |
| 714 | pins = "gpio61"; |
| 715 | drive-strength = <2>; /* 2 mA */ |
| 716 | bias-pull-down; /* PULL DOWN */ |
| 717 | input-enable; |
| 718 | }; |
| 719 | }; |
| 720 | |
| 721 | quat_aux_pcm_dout_active: quat_aux_pcm_dout_active { |
| 722 | mux { |
| 723 | pins = "gpio61"; |
| 724 | function = "qua_mi2s"; |
| 725 | }; |
| 726 | |
| 727 | config { |
| 728 | pins = "gpio61"; |
| 729 | drive-strength = <8>; /* 8 mA */ |
| 730 | bias-disable; /* NO PULL */ |
| 731 | }; |
| 732 | }; |
| 733 | }; |
| 734 | |
| 735 | pri_mi2s_mclk { |
| 736 | pri_mi2s_mclk_sleep: pri_mi2s_mclk_sleep { |
| 737 | mux { |
| 738 | pins = "gpio64"; |
| 739 | function = "gpio"; |
| 740 | }; |
| 741 | |
| 742 | config { |
| 743 | pins = "gpio64"; |
| 744 | drive-strength = <2>; /* 2 mA */ |
| 745 | bias-pull-down; /* PULL DOWN */ |
| 746 | input-enable; |
| 747 | }; |
| 748 | }; |
| 749 | |
| 750 | pri_mi2s_mclk_active: pri_mi2s_mclk_active { |
| 751 | mux { |
| 752 | pins = "gpio64"; |
| 753 | function = "pri_mi2s"; |
| 754 | }; |
| 755 | |
| 756 | config { |
| 757 | pins = "gpio64"; |
| 758 | drive-strength = <8>; /* 8 mA */ |
| 759 | bias-disable; /* NO PULL */ |
| 760 | output-high; |
| 761 | }; |
| 762 | }; |
| 763 | }; |
| 764 | |
| 765 | pri_mi2s_sck { |
| 766 | pri_mi2s_sck_sleep: pri_mi2s_sck_sleep { |
| 767 | mux { |
| 768 | pins = "gpio65"; |
| 769 | function = "gpio"; |
| 770 | }; |
| 771 | |
| 772 | config { |
| 773 | pins = "gpio65"; |
| 774 | drive-strength = <2>; /* 2 mA */ |
| 775 | bias-pull-down; /* PULL DOWN */ |
| 776 | input-enable; |
| 777 | }; |
| 778 | }; |
| 779 | |
| 780 | pri_mi2s_sck_active: pri_mi2s_sck_active { |
| 781 | mux { |
| 782 | pins = "gpio65"; |
| 783 | function = "pri_mi2s"; |
| 784 | }; |
| 785 | |
| 786 | config { |
| 787 | pins = "gpio65"; |
| 788 | drive-strength = <8>; /* 8 mA */ |
| 789 | bias-disable; /* NO PULL */ |
| 790 | output-high; |
| 791 | }; |
| 792 | }; |
| 793 | }; |
| 794 | |
| 795 | pri_mi2s_ws { |
| 796 | pri_mi2s_ws_sleep: pri_mi2s_ws_sleep { |
| 797 | mux { |
| 798 | pins = "gpio66"; |
| 799 | function = "gpio"; |
| 800 | }; |
| 801 | |
| 802 | config { |
| 803 | pins = "gpio66"; |
| 804 | drive-strength = <2>; /* 2 mA */ |
| 805 | bias-pull-down; /* PULL DOWN */ |
| 806 | input-enable; |
| 807 | }; |
| 808 | }; |
| 809 | |
| 810 | pri_mi2s_ws_active: pri_mi2s_ws_active { |
| 811 | mux { |
| 812 | pins = "gpio66"; |
| 813 | function = "pri_mi2s_ws"; |
| 814 | }; |
| 815 | |
| 816 | config { |
| 817 | pins = "gpio66"; |
| 818 | drive-strength = <8>; /* 8 mA */ |
| 819 | bias-disable; /* NO PULL */ |
| 820 | output-high; |
| 821 | }; |
| 822 | }; |
| 823 | }; |
| 824 | |
| 825 | pri_mi2s_sd0 { |
| 826 | pri_mi2s_sd0_sleep: pri_mi2s_sd0_sleep { |
| 827 | mux { |
| 828 | pins = "gpio67"; |
| 829 | function = "gpio"; |
| 830 | }; |
| 831 | |
| 832 | config { |
| 833 | pins = "gpio67"; |
| 834 | drive-strength = <2>; /* 2 mA */ |
| 835 | bias-pull-down; /* PULL DOWN */ |
| 836 | input-enable; |
| 837 | }; |
| 838 | }; |
| 839 | |
| 840 | pri_mi2s_sd0_active: pri_mi2s_sd0_active { |
| 841 | mux { |
| 842 | pins = "gpio67"; |
| 843 | function = "pri_mi2s"; |
| 844 | }; |
| 845 | |
| 846 | config { |
| 847 | pins = "gpio67"; |
| 848 | drive-strength = <8>; /* 8 mA */ |
| 849 | bias-disable; /* NO PULL */ |
| 850 | }; |
| 851 | }; |
| 852 | }; |
| 853 | |
| 854 | pri_mi2s_sd1 { |
| 855 | pri_mi2s_sd1_sleep: pri_mi2s_sd1_sleep { |
| 856 | mux { |
| 857 | pins = "gpio68"; |
| 858 | function = "gpio"; |
| 859 | }; |
| 860 | |
| 861 | config { |
| 862 | pins = "gpio68"; |
| 863 | drive-strength = <2>; /* 2 mA */ |
| 864 | bias-pull-down; /* PULL DOWN */ |
| 865 | input-enable; |
| 866 | }; |
| 867 | }; |
| 868 | |
| 869 | pri_mi2s_sd1_active: pri_mi2s_sd1_active { |
| 870 | mux { |
| 871 | pins = "gpio68"; |
| 872 | function = "pri_mi2s"; |
| 873 | }; |
| 874 | |
| 875 | config { |
| 876 | pins = "gpio68"; |
| 877 | drive-strength = <8>; /* 8 mA */ |
| 878 | bias-disable; /* NO PULL */ |
| 879 | }; |
| 880 | }; |
| 881 | }; |
| 882 | |
| 883 | sec_mi2s_mclk { |
| 884 | sec_mi2s_mclk_sleep: sec_mi2s_mclk_sleep { |
| 885 | mux { |
| 886 | pins = "gpio79"; |
| 887 | function = "gpio"; |
| 888 | }; |
| 889 | |
| 890 | config { |
| 891 | pins = "gpio79"; |
| 892 | drive-strength = <2>; /* 2 mA */ |
| 893 | bias-pull-down; /* PULL DOWN */ |
| 894 | input-enable; |
| 895 | }; |
| 896 | }; |
| 897 | |
| 898 | sec_mi2s_mclk_active: sec_mi2s_mclk_active { |
| 899 | mux { |
| 900 | pins = "gpio79"; |
| 901 | function = "sec_mi2s"; |
| 902 | }; |
| 903 | |
| 904 | config { |
| 905 | pins = "gpio79"; |
| 906 | drive-strength = <8>; /* 8 mA */ |
| 907 | bias-disable; /* NO PULL */ |
| 908 | }; |
| 909 | }; |
| 910 | }; |
| 911 | |
| 912 | sec_mi2s { |
| 913 | sec_mi2s_sleep: sec_mi2s_sleep { |
| 914 | mux { |
| 915 | pins = "gpio80", "gpio81"; |
| 916 | function = "gpio"; |
| 917 | }; |
| 918 | |
| 919 | config { |
| 920 | pins = "gpio80", "gpio81"; |
| 921 | drive-strength = <2>; /* 2 mA */ |
| 922 | bias-disable; /* NO PULL */ |
| 923 | input-enable; |
| 924 | }; |
| 925 | }; |
| 926 | |
| 927 | sec_mi2s_active: sec_mi2s_active { |
| 928 | mux { |
| 929 | pins = "gpio80", "gpio81"; |
| 930 | function = "sec_mi2s"; |
| 931 | }; |
| 932 | |
| 933 | config { |
| 934 | pins = "gpio80", "gpio81"; |
| 935 | drive-strength = <8>; /* 8 mA */ |
| 936 | bias-disable; /* NO PULL */ |
| 937 | }; |
| 938 | }; |
| 939 | }; |
| 940 | |
| 941 | sec_mi2s_sd0 { |
| 942 | sec_mi2s_sd0_sleep: sec_mi2s_sd0_sleep { |
| 943 | mux { |
| 944 | pins = "gpio82"; |
| 945 | function = "gpio"; |
| 946 | }; |
| 947 | |
| 948 | config { |
| 949 | pins = "gpio82"; |
| 950 | drive-strength = <2>; /* 2 mA */ |
| 951 | bias-pull-down; /* PULL DOWN */ |
| 952 | input-enable; |
| 953 | }; |
| 954 | }; |
| 955 | |
| 956 | sec_mi2s_sd0_active: sec_mi2s_sd0_active { |
| 957 | mux { |
| 958 | pins = "gpio82"; |
| 959 | function = "sec_mi2s"; |
| 960 | }; |
| 961 | |
| 962 | config { |
| 963 | pins = "gpio82"; |
| 964 | drive-strength = <8>; /* 8 mA */ |
| 965 | bias-disable; /* NO PULL */ |
| 966 | }; |
| 967 | }; |
| 968 | }; |
| 969 | |
| 970 | sec_mi2s_sd1 { |
| 971 | sec_mi2s_sd1_sleep: sec_mi2s_sd1_sleep { |
| 972 | mux { |
| 973 | pins = "gpio83"; |
| 974 | function = "gpio"; |
| 975 | }; |
| 976 | |
| 977 | config { |
| 978 | pins = "gpio83"; |
| 979 | drive-strength = <2>; /* 2 mA */ |
| 980 | bias-pull-down; /* PULL DOWN */ |
| 981 | input-enable; |
| 982 | }; |
| 983 | }; |
| 984 | |
| 985 | sec_mi2s_sd1_active: sec_mi2s_sd1_active { |
| 986 | mux { |
| 987 | pins = "gpio83"; |
| 988 | function = "sec_mi2s"; |
| 989 | }; |
| 990 | |
| 991 | config { |
| 992 | pins = "gpio83"; |
| 993 | drive-strength = <8>; /* 8 mA */ |
| 994 | bias-disable; /* NO PULL */ |
| 995 | }; |
| 996 | }; |
| 997 | }; |
| 998 | |
| 999 | tert_mi2s_mclk { |
| 1000 | tert_mi2s_mclk_sleep: tert_mi2s_mclk_sleep { |
| 1001 | mux { |
| 1002 | pins = "gpio74"; |
| 1003 | function = "gpio"; |
| 1004 | }; |
| 1005 | |
| 1006 | config { |
| 1007 | pins = "gpio74"; |
| 1008 | drive-strength = <2>; /* 2 mA */ |
| 1009 | bias-pull-down; /* PULL DOWN */ |
| 1010 | input-enable; |
| 1011 | }; |
| 1012 | }; |
| 1013 | |
| 1014 | tert_mi2s_mclk_active: tert_mi2s_mclk_active { |
| 1015 | mux { |
| 1016 | pins = "gpio74"; |
| 1017 | function = "ter_mi2s"; |
| 1018 | }; |
| 1019 | |
| 1020 | config { |
| 1021 | pins = "gpio74"; |
| 1022 | drive-strength = <8>; /* 8 mA */ |
| 1023 | bias-disable; /* NO PULL */ |
| 1024 | }; |
| 1025 | }; |
| 1026 | }; |
| 1027 | |
| 1028 | tert_mi2s { |
| 1029 | tert_mi2s_sleep: tert_mi2s_sleep { |
| 1030 | mux { |
| 1031 | pins = "gpio75", "gpio76"; |
| 1032 | function = "gpio"; |
| 1033 | }; |
| 1034 | |
| 1035 | config { |
| 1036 | pins = "gpio75", "gpio76"; |
| 1037 | drive-strength = <2>; /* 2 mA */ |
| 1038 | bias-pull-down; /* PULL DOWN */ |
| 1039 | input-enable; |
| 1040 | }; |
| 1041 | }; |
| 1042 | |
| 1043 | tert_mi2s_active: tert_mi2s_active { |
| 1044 | mux { |
| 1045 | pins = "gpio75", "gpio76"; |
| 1046 | function = "ter_mi2s"; |
| 1047 | }; |
| 1048 | |
| 1049 | config { |
| 1050 | pins = "gpio75", "gpio76"; |
| 1051 | drive-strength = <8>; /* 8 mA */ |
| 1052 | bias-disable; /* NO PULL */ |
| 1053 | output-high; |
| 1054 | }; |
| 1055 | }; |
| 1056 | }; |
| 1057 | |
| 1058 | tert_mi2s_sd0 { |
| 1059 | tert_mi2s_sd0_sleep: tert_mi2s_sd0_sleep { |
| 1060 | mux { |
| 1061 | pins = "gpio77"; |
| 1062 | function = "gpio"; |
| 1063 | }; |
| 1064 | |
| 1065 | config { |
| 1066 | pins = "gpio77"; |
| 1067 | drive-strength = <2>; /* 2 mA */ |
| 1068 | bias-pull-down; /* PULL DOWN */ |
| 1069 | input-enable; |
| 1070 | }; |
| 1071 | }; |
| 1072 | |
| 1073 | tert_mi2s_sd0_active: tert_mi2s_sd0_active { |
| 1074 | mux { |
| 1075 | pins = "gpio77"; |
| 1076 | function = "ter_mi2s"; |
| 1077 | }; |
| 1078 | |
| 1079 | config { |
| 1080 | pins = "gpio77"; |
| 1081 | drive-strength = <8>; /* 8 mA */ |
| 1082 | bias-disable; /* NO PULL */ |
| 1083 | }; |
| 1084 | }; |
| 1085 | }; |
| 1086 | |
| 1087 | tert_mi2s_sd1 { |
| 1088 | tert_mi2s_sd1_sleep: tert_mi2s_sd1_sleep { |
| 1089 | mux { |
| 1090 | pins = "gpio78"; |
| 1091 | function = "gpio"; |
| 1092 | }; |
| 1093 | |
| 1094 | config { |
| 1095 | pins = "gpio78"; |
| 1096 | drive-strength = <2>; /* 2 mA */ |
| 1097 | bias-pull-down; /* PULL DOWN */ |
| 1098 | input-enable; |
| 1099 | }; |
| 1100 | }; |
| 1101 | |
| 1102 | tert_mi2s_sd1_active: tert_mi2s_sd1_active { |
| 1103 | mux { |
| 1104 | pins = "gpio78"; |
| 1105 | function = "ter_mi2s"; |
| 1106 | }; |
| 1107 | |
| 1108 | config { |
| 1109 | pins = "gpio78"; |
| 1110 | drive-strength = <8>; /* 8 mA */ |
| 1111 | bias-disable; /* NO PULL */ |
| 1112 | }; |
| 1113 | }; |
| 1114 | }; |
| 1115 | |
| 1116 | quat_mi2s_mclk { |
| 1117 | quat_mi2s_mclk_sleep: quat_mi2s_mclk_sleep { |
| 1118 | mux { |
| 1119 | pins = "gpio57"; |
| 1120 | function = "gpio"; |
| 1121 | }; |
| 1122 | |
| 1123 | config { |
| 1124 | pins = "gpio57"; |
| 1125 | drive-strength = <2>; /* 2 mA */ |
| 1126 | bias-pull-down; /* PULL DOWN */ |
| 1127 | input-enable; |
| 1128 | }; |
| 1129 | }; |
| 1130 | |
| 1131 | quat_mi2s_mclk_active: quat_mi2s_mclk_active { |
| 1132 | mux { |
| 1133 | pins = "gpio57"; |
| 1134 | function = "qua_mi2s"; |
| 1135 | }; |
| 1136 | |
| 1137 | config { |
| 1138 | pins = "gpio57"; |
| 1139 | drive-strength = <8>; /* 8 mA */ |
| 1140 | bias-disable; /* NO PULL */ |
| 1141 | }; |
| 1142 | }; |
| 1143 | }; |
| 1144 | |
| 1145 | quat_mi2s { |
| 1146 | quat_mi2s_sleep: quat_mi2s_sleep { |
| 1147 | mux { |
| 1148 | pins = "gpio58", "gpio59"; |
| 1149 | function = "gpio"; |
| 1150 | }; |
| 1151 | |
| 1152 | config { |
| 1153 | pins = "gpio58", "gpio59"; |
| 1154 | drive-strength = <2>; /* 2 mA */ |
| 1155 | bias-pull-down; /* PULL DOWN */ |
| 1156 | input-enable; |
| 1157 | }; |
| 1158 | }; |
| 1159 | |
| 1160 | quat_mi2s_active: quat_mi2s_active { |
| 1161 | mux { |
| 1162 | pins = "gpio58", "gpio59"; |
| 1163 | function = "qua_mi2s"; |
| 1164 | }; |
| 1165 | |
| 1166 | config { |
| 1167 | pins = "gpio58", "gpio59"; |
| 1168 | drive-strength = <8>; /* 8 mA */ |
| 1169 | bias-disable; /* NO PULL */ |
| 1170 | output-high; |
| 1171 | }; |
| 1172 | }; |
| 1173 | }; |
| 1174 | |
| 1175 | quat_mi2s_sd0 { |
| 1176 | quat_mi2s_sd0_sleep: quat_mi2s_sd0_sleep { |
| 1177 | mux { |
| 1178 | pins = "gpio60"; |
| 1179 | function = "gpio"; |
| 1180 | }; |
| 1181 | |
| 1182 | config { |
| 1183 | pins = "gpio60"; |
| 1184 | drive-strength = <2>; /* 2 mA */ |
| 1185 | bias-pull-down; /* PULL DOWN */ |
| 1186 | input-enable; |
| 1187 | }; |
| 1188 | }; |
| 1189 | |
| 1190 | quat_mi2s_sd0_active: quat_mi2s_sd0_active { |
| 1191 | mux { |
| 1192 | pins = "gpio60"; |
| 1193 | function = "qua_mi2s"; |
| 1194 | }; |
| 1195 | |
| 1196 | config { |
| 1197 | pins = "gpio60"; |
| 1198 | drive-strength = <8>; /* 8 mA */ |
| 1199 | bias-disable; /* NO PULL */ |
| 1200 | }; |
| 1201 | }; |
| 1202 | }; |
| 1203 | |
| 1204 | quat_mi2s_sd1 { |
| 1205 | quat_mi2s_sd1_sleep: quat_mi2s_sd1_sleep { |
| 1206 | mux { |
| 1207 | pins = "gpio61"; |
| 1208 | function = "gpio"; |
| 1209 | }; |
| 1210 | |
| 1211 | config { |
| 1212 | pins = "gpio61"; |
| 1213 | drive-strength = <2>; /* 2 mA */ |
| 1214 | bias-pull-down; /* PULL DOWN */ |
| 1215 | input-enable; |
| 1216 | }; |
| 1217 | }; |
| 1218 | |
| 1219 | quat_mi2s_sd1_active: quat_mi2s_sd1_active { |
| 1220 | mux { |
| 1221 | pins = "gpio61"; |
| 1222 | function = "qua_mi2s"; |
| 1223 | }; |
| 1224 | |
| 1225 | config { |
| 1226 | pins = "gpio61"; |
| 1227 | drive-strength = <8>; /* 8 mA */ |
| 1228 | bias-disable; /* NO PULL */ |
| 1229 | }; |
| 1230 | }; |
| 1231 | }; |
| 1232 | |
| 1233 | quat_mi2s_sd2 { |
| 1234 | quat_mi2s_sd2_sleep: quat_mi2s_sd2_sleep { |
| 1235 | mux { |
| 1236 | pins = "gpio62"; |
| 1237 | function = "gpio"; |
| 1238 | }; |
| 1239 | |
| 1240 | config { |
| 1241 | pins = "gpio62"; |
| 1242 | drive-strength = <2>; /* 2 mA */ |
| 1243 | bias-pull-down; /* PULL DOWN */ |
| 1244 | input-enable; |
| 1245 | }; |
| 1246 | }; |
| 1247 | |
| 1248 | quat_mi2s_sd2_active: quat_mi2s_sd2_active { |
| 1249 | mux { |
| 1250 | pins = "gpio62"; |
| 1251 | function = "qua_mi2s"; |
| 1252 | }; |
| 1253 | |
| 1254 | config { |
| 1255 | pins = "gpio62"; |
| 1256 | drive-strength = <8>; /* 8 mA */ |
| 1257 | bias-disable; /* NO PULL */ |
| 1258 | }; |
| 1259 | }; |
| 1260 | }; |
| 1261 | |
| 1262 | quat_mi2s_sd3 { |
| 1263 | quat_mi2s_sd3_sleep: quat_mi2s_sd3_sleep { |
| 1264 | mux { |
| 1265 | pins = "gpio63"; |
| 1266 | function = "gpio"; |
| 1267 | }; |
| 1268 | |
| 1269 | config { |
| 1270 | pins = "gpio63"; |
| 1271 | drive-strength = <2>; /* 2 mA */ |
| 1272 | bias-pull-down; /* PULL DOWN */ |
| 1273 | input-enable; |
| 1274 | }; |
| 1275 | }; |
| 1276 | |
| 1277 | quat_mi2s_sd3_active: quat_mi2s_sd3_active { |
| 1278 | mux { |
| 1279 | pins = "gpio63"; |
| 1280 | function = "qua_mi2s"; |
| 1281 | }; |
| 1282 | |
| 1283 | config { |
| 1284 | pins = "gpio63"; |
| 1285 | drive-strength = <8>; /* 8 mA */ |
| 1286 | bias-disable; /* NO PULL */ |
| 1287 | }; |
| 1288 | }; |
| 1289 | }; |
Girish Mahadevan | 2e2fbe7 | 2017-03-28 13:28:18 -0600 | [diff] [blame] | 1290 | |
| 1291 | /* QUPv3 South SE mappings */ |
| 1292 | /* SE 0 pin mappings */ |
| 1293 | qupv3_se0_i2c_pins: qupv3_se0_i2c_pins { |
| 1294 | qupv3_se0_i2c_active: qupv3_se0_i2c_active { |
| 1295 | mux { |
| 1296 | pins = "gpio0", "gpio1"; |
| 1297 | function = "qup0"; |
| 1298 | }; |
| 1299 | |
| 1300 | config { |
| 1301 | pins = "gpio0", "gpio1"; |
| 1302 | drive-strength = <2>; |
| 1303 | bias-disable; |
| 1304 | }; |
| 1305 | }; |
| 1306 | |
| 1307 | qupv3_se0_i2c_sleep: qupv3_se0_i2c_sleep { |
| 1308 | mux { |
| 1309 | pins = "gpio0", "gpio1"; |
| 1310 | function = "gpio"; |
| 1311 | }; |
| 1312 | |
| 1313 | config { |
| 1314 | pins = "gpio0", "gpio1"; |
| 1315 | drive-strength = <2>; |
| 1316 | bias-pull-up; |
| 1317 | }; |
| 1318 | }; |
| 1319 | }; |
| 1320 | |
| 1321 | qupv3_se0_spi_pins: qupv3_se0_spi_pins { |
| 1322 | qupv3_se0_spi_active: qupv3_se0_spi_active { |
| 1323 | mux { |
| 1324 | pins = "gpio0", "gpio1", "gpio2", |
| 1325 | "gpio3"; |
| 1326 | function = "qup0"; |
| 1327 | }; |
| 1328 | |
| 1329 | config { |
| 1330 | pins = "gpio0", "gpio1", "gpio2", |
| 1331 | "gpio3"; |
| 1332 | drive-strength = <6>; |
| 1333 | bias-disable; |
| 1334 | }; |
| 1335 | }; |
| 1336 | |
| 1337 | qupv3_se0_spi_sleep: qupv3_se0_spi_sleep { |
| 1338 | mux { |
| 1339 | pins = "gpio0", "gpio1", "gpio2", |
| 1340 | "gpio3"; |
| 1341 | function = "gpio"; |
| 1342 | }; |
| 1343 | |
| 1344 | config { |
| 1345 | pins = "gpio0", "gpio1", "gpio2", |
| 1346 | "gpio3"; |
| 1347 | drive-strength = <6>; |
| 1348 | bias-disable; |
| 1349 | }; |
| 1350 | }; |
| 1351 | }; |
| 1352 | |
| 1353 | /* SE 1 pin mappings */ |
| 1354 | qupv3_se1_i2c_pins: qupv3_se1_i2c_pins { |
| 1355 | qupv3_se1_i2c_active: qupv3_se1_i2c_active { |
| 1356 | mux { |
| 1357 | pins = "gpio17", "gpio18"; |
| 1358 | function = "qup1"; |
| 1359 | }; |
| 1360 | |
| 1361 | config { |
| 1362 | pins = "gpio17", "gpio18"; |
| 1363 | drive-strength = <2>; |
| 1364 | bias-disable; |
| 1365 | }; |
| 1366 | }; |
| 1367 | |
| 1368 | qupv3_se1_i2c_sleep: qupv3_se1_i2c_sleep { |
| 1369 | mux { |
| 1370 | pins = "gpio17", "gpio18"; |
| 1371 | function = "gpio"; |
| 1372 | }; |
| 1373 | |
| 1374 | config { |
| 1375 | pins = "gpio17", "gpio18"; |
| 1376 | drive-strength = <2>; |
| 1377 | bias-pull-up; |
| 1378 | }; |
| 1379 | }; |
| 1380 | }; |
| 1381 | |
| 1382 | qupv3_se1_spi_pins: qupv3_se1_spi_pins { |
| 1383 | qupv3_se1_spi_active: qupv3_se1_spi_active { |
| 1384 | mux { |
| 1385 | pins = "gpio17", "gpio18", "gpio19", |
| 1386 | "gpio20"; |
| 1387 | function = "qup1"; |
| 1388 | }; |
| 1389 | |
| 1390 | config { |
| 1391 | pins = "gpio17", "gpio18", "gpio19", |
| 1392 | "gpio20"; |
| 1393 | drive-strength = <6>; |
| 1394 | bias-disable; |
| 1395 | }; |
| 1396 | }; |
| 1397 | |
| 1398 | qupv3_se1_spi_sleep: qupv3_se1_spi_sleep { |
| 1399 | mux { |
| 1400 | pins = "gpio17", "gpio18", "gpio19", |
| 1401 | "gpio20"; |
| 1402 | function = "gpio"; |
| 1403 | }; |
| 1404 | |
| 1405 | config { |
| 1406 | pins = "gpio17", "gpio18", "gpio19", |
| 1407 | "gpio20"; |
| 1408 | drive-strength = <6>; |
| 1409 | bias-disable; |
| 1410 | }; |
| 1411 | }; |
| 1412 | }; |
| 1413 | |
| 1414 | /* SE 2 pin mappings */ |
| 1415 | qupv3_se2_i2c_pins: qupv3_se2_i2c_pins { |
| 1416 | qupv3_se2_i2c_active: qupv3_se2_i2c_active { |
| 1417 | mux { |
| 1418 | pins = "gpio27", "gpio28"; |
| 1419 | function = "qup2"; |
| 1420 | }; |
| 1421 | |
| 1422 | config { |
| 1423 | pins = "gpio27", "gpio28"; |
| 1424 | drive-strength = <2>; |
| 1425 | bias-disable; |
| 1426 | }; |
| 1427 | }; |
| 1428 | |
| 1429 | qupv3_se2_i2c_sleep: qupv3_se2_i2c_sleep { |
| 1430 | mux { |
| 1431 | pins = "gpio27", "gpio28"; |
| 1432 | function = "gpio"; |
| 1433 | }; |
| 1434 | |
| 1435 | config { |
| 1436 | pins = "gpio27", "gpio28"; |
| 1437 | drive-strength = <2>; |
| 1438 | bias-pull-up; |
| 1439 | }; |
| 1440 | }; |
| 1441 | }; |
| 1442 | |
| 1443 | qupv3_se2_spi_pins: qupv3_se2_spi_pins { |
| 1444 | qupv3_se2_spi_active: qupv3_se2_spi_active { |
| 1445 | mux { |
| 1446 | pins = "gpio27", "gpio28", "gpio29", |
| 1447 | "gpio30"; |
| 1448 | function = "qup2"; |
| 1449 | }; |
| 1450 | |
| 1451 | config { |
| 1452 | pins = "gpio27", "gpio28", "gpio29", |
| 1453 | "gpio30"; |
| 1454 | drive-strength = <6>; |
| 1455 | bias-disable; |
| 1456 | }; |
| 1457 | }; |
| 1458 | |
| 1459 | qupv3_se2_spi_sleep: qupv3_se2_spi_sleep { |
| 1460 | mux { |
| 1461 | pins = "gpio27", "gpio28", "gpio29", |
| 1462 | "gpio30"; |
| 1463 | function = "gpio"; |
| 1464 | }; |
| 1465 | |
| 1466 | config { |
| 1467 | pins = "gpio27", "gpio28", "gpio29", |
| 1468 | "gpio30"; |
| 1469 | drive-strength = <6>; |
| 1470 | bias-disable; |
| 1471 | }; |
| 1472 | }; |
| 1473 | }; |
| 1474 | |
| 1475 | /* SE 3 pin mappings */ |
| 1476 | qupv3_se3_i2c_pins: qupv3_se3_i2c_pins { |
| 1477 | qupv3_se3_i2c_active: qupv3_se3_i2c_active { |
| 1478 | mux { |
| 1479 | pins = "gpio41", "gpio42"; |
| 1480 | function = "qup3"; |
| 1481 | }; |
| 1482 | |
| 1483 | config { |
| 1484 | pins = "gpio41", "gpio42"; |
| 1485 | drive-strength = <2>; |
| 1486 | bias-disable; |
| 1487 | }; |
| 1488 | }; |
| 1489 | |
| 1490 | qupv3_se3_i2c_sleep: qupv3_se3_i2c_sleep { |
| 1491 | mux { |
| 1492 | pins = "gpio41", "gpio42"; |
| 1493 | function = "gpio"; |
| 1494 | }; |
| 1495 | |
| 1496 | config { |
| 1497 | pins = "gpio41", "gpio42"; |
| 1498 | drive-strength = <2>; |
| 1499 | bias-pull-up; |
| 1500 | }; |
| 1501 | }; |
| 1502 | }; |
| 1503 | |
| 1504 | qupv3_se3_spi_pins: qupv3_se3_spi_pins { |
| 1505 | qupv3_se3_spi_active: qupv3_se3_spi_active { |
| 1506 | mux { |
| 1507 | pins = "gpio41", "gpio42", "gpio43", |
| 1508 | "gpio44"; |
| 1509 | function = "qup3"; |
| 1510 | }; |
| 1511 | |
| 1512 | config { |
| 1513 | pins = "gpio41", "gpio42", "gpio43", |
| 1514 | "gpio44"; |
| 1515 | drive-strength = <6>; |
| 1516 | bias-disable; |
| 1517 | }; |
| 1518 | }; |
| 1519 | |
| 1520 | qupv3_se3_spi_sleep: qupv3_se3_spi_sleep { |
| 1521 | mux { |
| 1522 | pins = "gpio41", "gpio42", "gpio43", |
| 1523 | "gpio44"; |
| 1524 | function = "gpio"; |
| 1525 | }; |
| 1526 | |
| 1527 | config { |
| 1528 | pins = "gpio41", "gpio42", "gpio43", |
| 1529 | "gpio44"; |
| 1530 | drive-strength = <6>; |
| 1531 | bias-disable; |
| 1532 | }; |
| 1533 | }; |
| 1534 | }; |
| 1535 | |
| 1536 | /* SE 4 pin mappings */ |
| 1537 | qupv3_se4_i2c_pins: qupv3_se4_i2c_pins { |
| 1538 | qupv3_se4_i2c_active: qupv3_se4_i2c_active { |
| 1539 | mux { |
| 1540 | pins = "gpio89", "gpio90"; |
| 1541 | function = "qup4"; |
| 1542 | }; |
| 1543 | |
| 1544 | config { |
| 1545 | pins = "gpio89", "gpio90"; |
| 1546 | drive-strength = <2>; |
| 1547 | bias-disable; |
| 1548 | }; |
| 1549 | }; |
| 1550 | |
| 1551 | qupv3_se4_i2c_sleep: qupv3_se4_i2c_sleep { |
| 1552 | mux { |
| 1553 | pins = "gpio89", "gpio90"; |
| 1554 | function = "gpio"; |
| 1555 | }; |
| 1556 | |
| 1557 | config { |
| 1558 | pins = "gpio89", "gpio90"; |
| 1559 | drive-strength = <2>; |
| 1560 | bias-pull-up; |
| 1561 | }; |
| 1562 | }; |
| 1563 | }; |
| 1564 | |
| 1565 | qupv3_se4_spi_pins: qupv3_se4_spi_pins { |
| 1566 | qupv3_se4_spi_active: qupv3_se4_spi_active { |
| 1567 | mux { |
| 1568 | pins = "gpio89", "gpio90", "gpio91", |
| 1569 | "gpio92"; |
| 1570 | function = "qup4"; |
| 1571 | }; |
| 1572 | |
| 1573 | config { |
| 1574 | pins = "gpio89", "gpio90", "gpio91", |
| 1575 | "gpio92"; |
| 1576 | drive-strength = <6>; |
| 1577 | bias-disable; |
| 1578 | }; |
| 1579 | }; |
| 1580 | |
| 1581 | qupv3_se4_spi_sleep: qupv3_se4_spi_sleep { |
| 1582 | mux { |
| 1583 | pins = "gpio89", "gpio90", "gpio91", |
| 1584 | "gpio92"; |
| 1585 | function = "gpio"; |
| 1586 | }; |
| 1587 | |
| 1588 | config { |
| 1589 | pins = "gpio89", "gpio90", "gpio91", |
| 1590 | "gpio92"; |
| 1591 | drive-strength = <6>; |
| 1592 | bias-disable; |
| 1593 | }; |
| 1594 | }; |
| 1595 | }; |
| 1596 | |
| 1597 | /* SE 5 pin mappings */ |
| 1598 | qupv3_se5_i2c_pins: qupv3_se5_i2c_pins { |
| 1599 | qupv3_se5_i2c_active: qupv3_se5_i2c_active { |
| 1600 | mux { |
| 1601 | pins = "gpio85", "gpio86"; |
| 1602 | function = "qup5"; |
| 1603 | }; |
| 1604 | |
| 1605 | config { |
| 1606 | pins = "gpio85", "gpio86"; |
| 1607 | drive-strength = <2>; |
| 1608 | bias-disable; |
| 1609 | }; |
| 1610 | }; |
| 1611 | |
| 1612 | qupv3_se5_i2c_sleep: qupv3_se5_i2c_sleep { |
| 1613 | mux { |
| 1614 | pins = "gpio85", "gpio86"; |
| 1615 | function = "gpio"; |
| 1616 | }; |
| 1617 | |
| 1618 | config { |
| 1619 | pins = "gpio85", "gpio86"; |
| 1620 | drive-strength = <2>; |
| 1621 | bias-pull-up; |
| 1622 | }; |
| 1623 | }; |
| 1624 | }; |
| 1625 | |
| 1626 | qupv3_se5_spi_pins: qupv3_se5_spi_pins { |
| 1627 | qupv3_se5_spi_active: qupv3_se5_spi_active { |
| 1628 | mux { |
| 1629 | pins = "gpio85", "gpio86", "gpio87", |
| 1630 | "gpio88"; |
| 1631 | function = "qup5"; |
| 1632 | }; |
| 1633 | |
| 1634 | config { |
| 1635 | pins = "gpio85", "gpio86", "gpio87", |
| 1636 | "gpio88"; |
| 1637 | drive-strength = <6>; |
| 1638 | bias-disable; |
| 1639 | }; |
| 1640 | }; |
| 1641 | |
| 1642 | qupv3_se5_spi_sleep: qupv3_se5_spi_sleep { |
| 1643 | mux { |
| 1644 | pins = "gpio85", "gpio86", "gpio87", |
| 1645 | "gpio88"; |
| 1646 | function = "gpio"; |
| 1647 | }; |
| 1648 | |
| 1649 | config { |
| 1650 | pins = "gpio85", "gpio86", "gpio87", |
| 1651 | "gpio88"; |
| 1652 | drive-strength = <6>; |
| 1653 | bias-disable; |
| 1654 | }; |
| 1655 | }; |
| 1656 | }; |
| 1657 | |
| 1658 | /* SE 6 pin mappings */ |
| 1659 | qupv3_se6_i2c_pins: qupv3_se6_i2c_pins { |
| 1660 | qupv3_se6_i2c_active: qupv3_se6_i2c_active { |
| 1661 | mux { |
| 1662 | pins = "gpio45", "gpio46"; |
| 1663 | function = "qup6"; |
| 1664 | }; |
| 1665 | |
| 1666 | config { |
| 1667 | pins = "gpio45", "gpio46"; |
| 1668 | drive-strength = <2>; |
| 1669 | bias-disable; |
| 1670 | }; |
| 1671 | }; |
| 1672 | |
| 1673 | qupv3_se6_i2c_sleep: qupv3_se6_i2c_sleep { |
| 1674 | mux { |
| 1675 | pins = "gpio45", "gpio46"; |
| 1676 | function = "gpio"; |
| 1677 | }; |
| 1678 | |
| 1679 | config { |
| 1680 | pins = "gpio45", "gpio46"; |
| 1681 | drive-strength = <2>; |
| 1682 | bias-pull-up; |
| 1683 | }; |
| 1684 | }; |
| 1685 | }; |
| 1686 | |
| 1687 | qupv3_se6_4uart_pins: qupv3_se6_4uart_pins { |
| 1688 | qupv3_se6_4uart_active: qupv3_se6_4uart_active { |
| 1689 | mux { |
| 1690 | pins = "gpio45", "gpio46", "gpio47", |
| 1691 | "gpio48"; |
| 1692 | function = "qup6"; |
| 1693 | }; |
| 1694 | |
| 1695 | config { |
| 1696 | pins = "gpio45", "gpio46", "gpio47", |
| 1697 | "gpio48"; |
| 1698 | drive-strength = <2>; |
| 1699 | bias-disable; |
| 1700 | }; |
| 1701 | }; |
| 1702 | |
| 1703 | qupv3_se6_4uart_sleep: qupv3_se6_4uart_sleep { |
| 1704 | mux { |
| 1705 | pins = "gpio45", "gpio46", "gpio47", |
| 1706 | "gpio48"; |
| 1707 | function = "gpio"; |
| 1708 | }; |
| 1709 | |
| 1710 | config { |
| 1711 | pins = "gpio45", "gpio46", "gpio47", |
| 1712 | "gpio48"; |
| 1713 | drive-strength = <2>; |
| 1714 | bias-disable; |
| 1715 | }; |
| 1716 | }; |
| 1717 | }; |
| 1718 | |
| 1719 | qupv3_se6_spi_pins: qupv3_se6_spi_pins { |
| 1720 | qupv3_se6_spi_active: qupv3_se6_spi_active { |
| 1721 | mux { |
| 1722 | pins = "gpio45", "gpio46", "gpio47", |
| 1723 | "gpio48"; |
| 1724 | function = "qup6"; |
| 1725 | }; |
| 1726 | |
| 1727 | config { |
| 1728 | pins = "gpio45", "gpio46", "gpio47", |
| 1729 | "gpio48"; |
| 1730 | drive-strength = <6>; |
| 1731 | bias-disable; |
| 1732 | }; |
| 1733 | }; |
| 1734 | |
| 1735 | qupv3_se6_spi_sleep: qupv3_se6_spi_sleep { |
| 1736 | mux { |
| 1737 | pins = "gpio45", "gpio46", "gpio47", |
| 1738 | "gpio48"; |
| 1739 | function = "gpio"; |
| 1740 | }; |
| 1741 | |
| 1742 | config { |
| 1743 | pins = "gpio45", "gpio46", "gpio47", |
| 1744 | "gpio48"; |
| 1745 | drive-strength = <6>; |
| 1746 | bias-disable; |
| 1747 | }; |
| 1748 | }; |
| 1749 | }; |
| 1750 | |
| 1751 | /* SE 7 pin mappings */ |
| 1752 | qupv3_se7_i2c_pins: qupv3_se7_i2c_pins { |
| 1753 | qupv3_se7_i2c_active: qupv3_se7_i2c_active { |
| 1754 | mux { |
| 1755 | pins = "gpio93", "gpio94"; |
| 1756 | function = "qup7"; |
| 1757 | }; |
| 1758 | |
| 1759 | config { |
| 1760 | pins = "gpio93", "gpio94"; |
| 1761 | drive-strength = <2>; |
| 1762 | bias-disable; |
| 1763 | }; |
| 1764 | }; |
| 1765 | |
| 1766 | qupv3_se7_i2c_sleep: qupv3_se7_i2c_sleep { |
| 1767 | mux { |
| 1768 | pins = "gpio93", "gpio94"; |
| 1769 | function = "gpio"; |
| 1770 | }; |
| 1771 | |
| 1772 | config { |
| 1773 | pins = "gpio93", "gpio94"; |
| 1774 | drive-strength = <2>; |
| 1775 | bias-pull-up; |
| 1776 | }; |
| 1777 | }; |
| 1778 | }; |
| 1779 | |
| 1780 | qupv3_se7_4uart_pins: qupv3_se7_4uart_pins { |
| 1781 | qupv3_se7_4uart_active: qupv3_se7_4uart_active { |
| 1782 | mux { |
| 1783 | pins = "gpio93", "gpio94", "gpio95", |
| 1784 | "gpio96"; |
| 1785 | function = "qup7"; |
| 1786 | }; |
| 1787 | |
| 1788 | config { |
| 1789 | pins = "gpio93", "gpio94", "gpio95", |
| 1790 | "gpio96"; |
| 1791 | drive-strength = <2>; |
| 1792 | bias-disable; |
| 1793 | }; |
| 1794 | }; |
| 1795 | |
| 1796 | qupv3_se7_4uart_sleep: qupv3_se7_4uart_sleep { |
| 1797 | mux { |
| 1798 | pins = "gpio93", "gpio94", "gpio95", |
| 1799 | "gpio96"; |
| 1800 | function = "gpio"; |
| 1801 | }; |
| 1802 | |
| 1803 | config { |
| 1804 | pins = "gpio93", "gpio94", "gpio95", |
| 1805 | "gpio96"; |
| 1806 | drive-strength = <2>; |
| 1807 | bias-disable; |
| 1808 | }; |
| 1809 | }; |
| 1810 | }; |
| 1811 | |
| 1812 | qupv3_se7_spi_pins: qupv3_se7_spi_pins { |
| 1813 | qupv3_se7_spi_active: qupv3_se7_spi_active { |
| 1814 | mux { |
| 1815 | pins = "gpio93", "gpio94", "gpio95", |
| 1816 | "gpio96"; |
| 1817 | function = "qup7"; |
| 1818 | }; |
| 1819 | |
| 1820 | config { |
| 1821 | pins = "gpio93", "gpio94", "gpio95", |
| 1822 | "gpio96"; |
| 1823 | drive-strength = <6>; |
| 1824 | bias-disable; |
| 1825 | }; |
| 1826 | }; |
| 1827 | |
| 1828 | qupv3_se7_spi_sleep: qupv3_se7_spi_sleep { |
| 1829 | mux { |
| 1830 | pins = "gpio93", "gpio94", "gpio95", |
| 1831 | "gpio96"; |
| 1832 | function = "gpio"; |
| 1833 | }; |
| 1834 | |
| 1835 | config { |
| 1836 | pins = "gpio93", "gpio94", "gpio95", |
| 1837 | "gpio96"; |
| 1838 | drive-strength = <6>; |
| 1839 | bias-disable; |
| 1840 | }; |
| 1841 | }; |
| 1842 | }; |
| 1843 | |
| 1844 | /* QUPv3 North instances */ |
| 1845 | /* SE 8 pin mappings */ |
| 1846 | qupv3_se8_i2c_pins: qupv3_se8_i2c_pins { |
| 1847 | qupv3_se8_i2c_active: qupv3_se8_i2c_active { |
| 1848 | mux { |
| 1849 | pins = "gpio65", "gpio66"; |
| 1850 | function = "qup8"; |
| 1851 | }; |
| 1852 | |
| 1853 | config { |
| 1854 | pins = "gpio65", "gpio66"; |
| 1855 | drive-strength = <2>; |
| 1856 | bias-disable; |
| 1857 | }; |
| 1858 | }; |
| 1859 | |
| 1860 | qupv3_se8_i2c_sleep: qupv3_se8_i2c_sleep { |
| 1861 | mux { |
| 1862 | pins = "gpio65", "gpio66"; |
| 1863 | function = "gpio"; |
| 1864 | }; |
| 1865 | |
| 1866 | config { |
| 1867 | pins = "gpio65", "gpio66"; |
| 1868 | drive-strength = <2>; |
| 1869 | bias-pull-up; |
| 1870 | }; |
| 1871 | }; |
| 1872 | }; |
| 1873 | |
| 1874 | qupv3_se8_spi_pins: qupv3_se8_spi_pins { |
| 1875 | qupv3_se8_spi_active: qupv3_se8_spi_active { |
| 1876 | mux { |
| 1877 | pins = "gpio65", "gpio66", "gpio67", |
| 1878 | "gpio68"; |
| 1879 | function = "qup8"; |
| 1880 | }; |
| 1881 | |
| 1882 | config { |
| 1883 | pins = "gpio65", "gpio66", "gpio67", |
| 1884 | "gpio68"; |
| 1885 | drive-strength = <6>; |
| 1886 | bias-disable; |
| 1887 | }; |
| 1888 | }; |
| 1889 | |
| 1890 | qupv3_se8_spi_sleep: qupv3_se8_spi_sleep { |
| 1891 | mux { |
| 1892 | pins = "gpio65", "gpio66", "gpio67", |
| 1893 | "gpio68"; |
| 1894 | function = "gpio"; |
| 1895 | }; |
| 1896 | |
| 1897 | config { |
| 1898 | pins = "gpio65", "gpio66", "gpio67", |
| 1899 | "gpio68"; |
| 1900 | drive-strength = <6>; |
| 1901 | bias-disable; |
| 1902 | }; |
| 1903 | }; |
| 1904 | }; |
| 1905 | |
| 1906 | /* SE 9 pin mappings */ |
| 1907 | qupv3_se9_i2c_pins: qupv3_se9_i2c_pins { |
| 1908 | qupv3_se9_i2c_active: qupv3_se9_i2c_active { |
| 1909 | mux { |
| 1910 | pins = "gpio6", "gpio7"; |
| 1911 | function = "qup9"; |
| 1912 | }; |
| 1913 | |
| 1914 | config { |
| 1915 | pins = "gpio6", "gpio7"; |
| 1916 | drive-strength = <2>; |
| 1917 | bias-disable; |
| 1918 | }; |
| 1919 | }; |
| 1920 | |
| 1921 | qupv3_se9_i2c_sleep: qupv3_se9_i2c_sleep { |
| 1922 | mux { |
| 1923 | pins = "gpio6", "gpio7"; |
| 1924 | function = "gpio"; |
| 1925 | }; |
| 1926 | |
| 1927 | config { |
| 1928 | pins = "gpio6", "gpio7"; |
| 1929 | drive-strength = <2>; |
| 1930 | bias-pull-up; |
| 1931 | }; |
| 1932 | }; |
| 1933 | }; |
| 1934 | |
| 1935 | qupv3_se9_2uart_pins: qupv3_se9_2uart_pins { |
| 1936 | qupv3_se9_2uart_active: qupv3_se9_2uart_active { |
| 1937 | mux { |
| 1938 | pins = "gpio4", "gpio5"; |
| 1939 | function = "qup9"; |
| 1940 | }; |
| 1941 | |
| 1942 | config { |
| 1943 | pins = "gpio4", "gpio5"; |
| 1944 | drive-strength = <2>; |
| 1945 | bias-disable; |
| 1946 | }; |
| 1947 | }; |
| 1948 | |
| 1949 | qupv3_se9_2uart_sleep: qupv3_se9_2uart_sleep { |
| 1950 | mux { |
| 1951 | pins = "gpio4", "gpio5"; |
| 1952 | function = "gpio"; |
| 1953 | }; |
| 1954 | |
| 1955 | config { |
| 1956 | pins = "gpio4", "gpio5"; |
| 1957 | drive-strength = <2>; |
| 1958 | bias-disable; |
| 1959 | }; |
| 1960 | }; |
| 1961 | }; |
| 1962 | |
| 1963 | qupv3_se9_spi_pins: qupv3_se9_spi_pins { |
| 1964 | qupv3_se9_spi_active: qupv3_se9_spi_active { |
| 1965 | mux { |
| 1966 | pins = "gpio4", "gpio5", "gpio6", |
| 1967 | "gpio7"; |
| 1968 | function = "qup9"; |
| 1969 | }; |
| 1970 | |
| 1971 | config { |
| 1972 | pins = "gpio4", "gpio5", "gpio6", |
| 1973 | "gpio7"; |
| 1974 | drive-strength = <6>; |
| 1975 | bias-disable; |
| 1976 | }; |
| 1977 | }; |
| 1978 | |
| 1979 | qupv3_se9_spi_sleep: qupv3_se9_spi_sleep { |
| 1980 | mux { |
| 1981 | pins = "gpio4", "gpio5", "gpio6", |
| 1982 | "gpio7"; |
| 1983 | function = "gpio"; |
| 1984 | }; |
| 1985 | |
| 1986 | config { |
| 1987 | pins = "gpio4", "gpio5", "gpio6", |
| 1988 | "gpio7"; |
| 1989 | drive-strength = <6>; |
| 1990 | bias-disable; |
| 1991 | }; |
| 1992 | }; |
| 1993 | }; |
| 1994 | |
| 1995 | /* SE 10 pin mappings */ |
| 1996 | qupv3_se10_i2c_pins: qupv3_se10_i2c_pins { |
| 1997 | qupv3_se10_i2c_active: qupv3_se10_i2c_active { |
| 1998 | mux { |
| 1999 | pins = "gpio55", "gpio56"; |
| 2000 | function = "qup10"; |
| 2001 | }; |
| 2002 | |
| 2003 | config { |
| 2004 | pins = "gpio55", "gpio56"; |
| 2005 | drive-strength = <2>; |
| 2006 | bias-disable; |
| 2007 | }; |
| 2008 | }; |
| 2009 | |
| 2010 | qupv3_se10_i2c_sleep: qupv3_se10_i2c_sleep { |
| 2011 | mux { |
| 2012 | pins = "gpio55", "gpio56"; |
| 2013 | function = "gpio"; |
| 2014 | }; |
| 2015 | |
| 2016 | config { |
| 2017 | pins = "gpio55", "gpio56"; |
| 2018 | drive-strength = <2>; |
| 2019 | bias-pull-up; |
| 2020 | }; |
| 2021 | }; |
| 2022 | }; |
| 2023 | |
| 2024 | qupv3_se10_2uart_pins: qupv3_se10_2uart_pins { |
| 2025 | qupv3_se10_2uart_active: qupv3_se10_2uart_active { |
| 2026 | mux { |
| 2027 | pins = "gpio53", "gpio54"; |
| 2028 | function = "qup10"; |
| 2029 | }; |
| 2030 | |
| 2031 | config { |
| 2032 | pins = "gpio53", "gpio54"; |
| 2033 | drive-strength = <2>; |
| 2034 | bias-disable; |
| 2035 | }; |
| 2036 | }; |
| 2037 | |
| 2038 | qupv3_se10_2uart_sleep: qupv3_se10_2uart_sleep { |
| 2039 | mux { |
| 2040 | pins = "gpio53", "gpio54"; |
| 2041 | function = "gpio"; |
| 2042 | }; |
| 2043 | |
| 2044 | config { |
| 2045 | pins = "gpio53", "gpio54"; |
| 2046 | drive-strength = <2>; |
| 2047 | bias-disable; |
| 2048 | }; |
| 2049 | }; |
| 2050 | }; |
| 2051 | |
| 2052 | qupv3_se10_spi_pins: qupv3_se10_spi_pins { |
| 2053 | qupv3_se10_spi_active: qupv3_se10_spi_active { |
| 2054 | mux { |
| 2055 | pins = "gpio53", "gpio54", "gpio55", |
| 2056 | "gpio56"; |
| 2057 | function = "qup10"; |
| 2058 | }; |
| 2059 | |
| 2060 | config { |
| 2061 | pins = "gpio53", "gpio54", "gpio55", |
| 2062 | "gpio56"; |
| 2063 | drive-strength = <6>; |
| 2064 | bias-disable; |
| 2065 | }; |
| 2066 | }; |
| 2067 | |
| 2068 | qupv3_se10_spi_sleep: qupv3_se10_spi_sleep { |
| 2069 | mux { |
| 2070 | pins = "gpio53", "gpio54", "gpio55", |
| 2071 | "gpio56"; |
| 2072 | function = "gpio"; |
| 2073 | }; |
| 2074 | |
| 2075 | config { |
| 2076 | pins = "gpio53", "gpio54", "gpio55", |
| 2077 | "gpio56"; |
| 2078 | drive-strength = <6>; |
| 2079 | bias-disable; |
| 2080 | }; |
| 2081 | }; |
| 2082 | }; |
| 2083 | |
| 2084 | /* SE 11 pin mappings */ |
| 2085 | qupv3_se11_i2c_pins: qupv3_se11_i2c_pins { |
| 2086 | qupv3_se11_i2c_active: qupv3_se11_i2c_active { |
| 2087 | mux { |
| 2088 | pins = "gpio31", "gpio32"; |
| 2089 | function = "qup11"; |
| 2090 | }; |
| 2091 | |
| 2092 | config { |
| 2093 | pins = "gpio31", "gpio32"; |
| 2094 | drive-strength = <2>; |
| 2095 | bias-disable; |
| 2096 | }; |
| 2097 | }; |
| 2098 | |
| 2099 | qupv3_se11_i2c_sleep: qupv3_se11_i2c_sleep { |
| 2100 | mux { |
| 2101 | pins = "gpio31", "gpio32"; |
| 2102 | function = "gpio"; |
| 2103 | }; |
| 2104 | |
| 2105 | config { |
| 2106 | pins = "gpio31", "gpio32"; |
| 2107 | drive-strength = <2>; |
| 2108 | bias-pull-up; |
| 2109 | }; |
| 2110 | }; |
| 2111 | }; |
| 2112 | |
| 2113 | qupv3_se11_spi_pins: qupv3_se11_spi_pins { |
| 2114 | qupv3_se11_spi_active: qupv3_se11_spi_active { |
| 2115 | mux { |
| 2116 | pins = "gpio31", "gpio32", "gpio33", |
| 2117 | "gpio34"; |
| 2118 | function = "qup11"; |
| 2119 | }; |
| 2120 | |
| 2121 | config { |
| 2122 | pins = "gpio31", "gpio32", "gpio33", |
| 2123 | "gpio34"; |
| 2124 | drive-strength = <6>; |
| 2125 | bias-disable; |
| 2126 | }; |
| 2127 | }; |
| 2128 | |
| 2129 | qupv3_se11_spi_sleep: qupv3_se11_spi_sleep { |
| 2130 | mux { |
| 2131 | pins = "gpio31", "gpio32", "gpio33", |
| 2132 | "gpio34"; |
| 2133 | function = "gpio"; |
| 2134 | }; |
| 2135 | |
| 2136 | config { |
| 2137 | pins = "gpio31", "gpio32", "gpio33", |
| 2138 | "gpio34"; |
| 2139 | drive-strength = <6>; |
| 2140 | bias-disable; |
| 2141 | }; |
| 2142 | }; |
| 2143 | }; |
| 2144 | |
| 2145 | /* SE 12 pin mappings */ |
| 2146 | qupv3_se12_i2c_pins: qupv3_se12_i2c_pins { |
| 2147 | qupv3_se12_i2c_active: qupv3_se12_i2c_active { |
| 2148 | mux { |
| 2149 | pins = "gpio49", "gpio50"; |
| 2150 | function = "qup12"; |
| 2151 | }; |
| 2152 | |
| 2153 | config { |
| 2154 | pins = "gpio49", "gpio50"; |
| 2155 | drive-strength = <2>; |
| 2156 | bias-disable; |
| 2157 | }; |
| 2158 | }; |
| 2159 | |
| 2160 | qupv3_se12_i2c_sleep: qupv3_se12_i2c_sleep { |
| 2161 | mux { |
| 2162 | pins = "gpio49", "gpio50"; |
| 2163 | function = "gpio"; |
| 2164 | }; |
| 2165 | |
| 2166 | config { |
| 2167 | pins = "gpio49", "gpio50"; |
| 2168 | drive-strength = <2>; |
| 2169 | bias-pull-up; |
| 2170 | }; |
| 2171 | }; |
| 2172 | }; |
| 2173 | |
| 2174 | qupv3_se12_spi_pins: qupv3_se12_spi_pins { |
| 2175 | qupv3_se12_spi_active: qupv3_se12_spi_active { |
| 2176 | mux { |
| 2177 | pins = "gpio49", "gpio50", "gpio51", |
| 2178 | "gpio52"; |
| 2179 | function = "qup12"; |
| 2180 | }; |
| 2181 | |
| 2182 | config { |
| 2183 | pins = "gpio49", "gpio50", "gpio51", |
| 2184 | "gpio52"; |
| 2185 | drive-strength = <6>; |
| 2186 | bias-disable; |
| 2187 | }; |
| 2188 | }; |
| 2189 | |
| 2190 | qupv3_se12_spi_sleep: qupv3_se12_spi_sleep { |
| 2191 | mux { |
| 2192 | pins = "gpio49", "gpio50", "gpio51", |
| 2193 | "gpio52"; |
| 2194 | function = "gpio"; |
| 2195 | }; |
| 2196 | |
| 2197 | config { |
| 2198 | pins = "gpio49", "gpio50", "gpio51", |
| 2199 | "gpio52"; |
| 2200 | drive-strength = <6>; |
| 2201 | bias-disable; |
| 2202 | }; |
| 2203 | }; |
| 2204 | }; |
| 2205 | |
| 2206 | /* SE 13 pin mappings */ |
| 2207 | qupv3_se13_i2c_pins: qupv3_se13_i2c_pins { |
| 2208 | qupv3_se13_i2c_active: qupv3_se13_i2c_active { |
| 2209 | mux { |
| 2210 | pins = "gpio105", "gpio106"; |
| 2211 | function = "qup13"; |
| 2212 | }; |
| 2213 | |
| 2214 | config { |
| 2215 | pins = "gpio105", "gpio106"; |
| 2216 | drive-strength = <2>; |
| 2217 | bias-disable; |
| 2218 | }; |
| 2219 | }; |
| 2220 | |
| 2221 | qupv3_se13_i2c_sleep: qupv3_se13_i2c_sleep { |
| 2222 | mux { |
| 2223 | pins = "gpio105", "gpio106"; |
| 2224 | function = "gpio"; |
| 2225 | }; |
| 2226 | |
| 2227 | config { |
| 2228 | pins = "gpio105", "gpio106"; |
| 2229 | drive-strength = <2>; |
| 2230 | bias-pull-up; |
| 2231 | }; |
| 2232 | }; |
| 2233 | }; |
| 2234 | |
| 2235 | qupv3_se13_spi_pins: qupv3_se13_spi_pins { |
| 2236 | qupv3_se13_spi_active: qupv3_se13_spi_active { |
| 2237 | mux { |
| 2238 | pins = "gpio105", "gpio106", "gpio107", |
| 2239 | "gpio108"; |
| 2240 | function = "qup13"; |
| 2241 | }; |
| 2242 | |
| 2243 | config { |
| 2244 | pins = "gpio105", "gpio106", "gpio107", |
| 2245 | "gpio108"; |
| 2246 | drive-strength = <6>; |
| 2247 | bias-disable; |
| 2248 | }; |
| 2249 | }; |
| 2250 | |
| 2251 | qupv3_se13_spi_sleep: qupv3_se13_spi_sleep { |
| 2252 | mux { |
| 2253 | pins = "gpio105", "gpio106", "gpio107", |
| 2254 | "gpio108"; |
| 2255 | function = "gpio"; |
| 2256 | }; |
| 2257 | |
| 2258 | config { |
| 2259 | pins = "gpio105", "gpio106", "gpio107", |
| 2260 | "gpio108"; |
| 2261 | drive-strength = <6>; |
| 2262 | bias-disable; |
| 2263 | }; |
| 2264 | }; |
| 2265 | }; |
| 2266 | |
| 2267 | /* SE 14 pin mappings */ |
| 2268 | qupv3_se14_i2c_pins: qupv3_se14_i2c_pins { |
| 2269 | qupv3_se14_i2c_active: qupv3_se14_i2c_active { |
| 2270 | mux { |
| 2271 | pins = "gpio33", "gpio34"; |
| 2272 | function = "qup14"; |
| 2273 | }; |
| 2274 | |
| 2275 | config { |
| 2276 | pins = "gpio33", "gpio34"; |
| 2277 | drive-strength = <2>; |
| 2278 | bias-disable; |
| 2279 | }; |
| 2280 | }; |
| 2281 | |
| 2282 | qupv3_se14_i2c_sleep: qupv3_se14_i2c_sleep { |
| 2283 | mux { |
| 2284 | pins = "gpio33", "gpio34"; |
| 2285 | function = "gpio"; |
| 2286 | }; |
| 2287 | |
| 2288 | config { |
| 2289 | pins = "gpio33", "gpio34"; |
| 2290 | drive-strength = <2>; |
| 2291 | bias-pull-up; |
| 2292 | }; |
| 2293 | }; |
| 2294 | }; |
| 2295 | |
| 2296 | qupv3_se14_spi_pins: qupv3_se14_spi_pins { |
| 2297 | qupv3_se14_spi_active: qupv3_se14_spi_active { |
| 2298 | mux { |
| 2299 | pins = "gpio31", "gpio32", "gpio33", |
| 2300 | "gpio34"; |
| 2301 | function = "qup14"; |
| 2302 | }; |
| 2303 | |
| 2304 | config { |
| 2305 | pins = "gpio31", "gpio32", "gpio33", |
| 2306 | "gpio34"; |
| 2307 | drive-strength = <6>; |
| 2308 | bias-disable; |
| 2309 | }; |
| 2310 | }; |
| 2311 | |
| 2312 | qupv3_se14_spi_sleep: qupv3_se14_spi_sleep { |
| 2313 | mux { |
| 2314 | pins = "gpio31", "gpio32", "gpio33", |
| 2315 | "gpio34"; |
| 2316 | function = "gpio"; |
| 2317 | }; |
| 2318 | |
| 2319 | config { |
| 2320 | pins = "gpio31", "gpio32", "gpio33", |
| 2321 | "gpio34"; |
| 2322 | drive-strength = <6>; |
| 2323 | bias-disable; |
| 2324 | }; |
| 2325 | }; |
| 2326 | }; |
| 2327 | |
| 2328 | /* SE 15 pin mappings */ |
| 2329 | qupv3_se15_i2c_pins: qupv3_se15_i2c_pins { |
| 2330 | qupv3_se15_i2c_active: qupv3_se15_i2c_active { |
| 2331 | mux { |
| 2332 | pins = "gpio81", "gpio82"; |
| 2333 | function = "qup15"; |
| 2334 | }; |
| 2335 | |
| 2336 | config { |
| 2337 | pins = "gpio81", "gpio82"; |
| 2338 | drive-strength = <2>; |
| 2339 | bias-disable; |
| 2340 | }; |
| 2341 | }; |
| 2342 | |
| 2343 | qupv3_se15_i2c_sleep: qupv3_se15_i2c_sleep { |
| 2344 | mux { |
| 2345 | pins = "gpio81", "gpio82"; |
| 2346 | function = "gpio"; |
| 2347 | }; |
| 2348 | |
| 2349 | config { |
| 2350 | pins = "gpio81", "gpio82"; |
| 2351 | drive-strength = <2>; |
| 2352 | bias-pull-up; |
| 2353 | }; |
| 2354 | }; |
| 2355 | }; |
| 2356 | |
| 2357 | qupv3_se15_spi_pins: qupv3_se15_spi_pins { |
| 2358 | qupv3_se15_spi_active: qupv3_se15_spi_active { |
| 2359 | mux { |
| 2360 | pins = "gpio81", "gpio82", "gpio83", |
| 2361 | "gpio84"; |
| 2362 | function = "qup15"; |
| 2363 | }; |
| 2364 | |
| 2365 | config { |
| 2366 | pins = "gpio81", "gpio82", "gpio83", |
| 2367 | "gpio84"; |
| 2368 | drive-strength = <6>; |
| 2369 | bias-disable; |
| 2370 | }; |
| 2371 | }; |
| 2372 | |
| 2373 | qupv3_se15_spi_sleep: qupv3_se15_spi_sleep { |
| 2374 | mux { |
| 2375 | pins = "gpio81", "gpio82", "gpio83", |
| 2376 | "gpio84"; |
| 2377 | function = "gpio"; |
| 2378 | }; |
| 2379 | |
| 2380 | config { |
| 2381 | pins = "gpio81", "gpio82", "gpio83", |
| 2382 | "gpio84"; |
| 2383 | drive-strength = <6>; |
| 2384 | bias-disable; |
| 2385 | }; |
| 2386 | }; |
| 2387 | }; |
Jigarkumar Zala | 86123115 | 2017-02-28 14:05:11 -0800 | [diff] [blame] | 2388 | |
| 2389 | cci0_active: cci0_active { |
| 2390 | mux { |
| 2391 | /* CLK, DATA */ |
| 2392 | pins = "gpio17","gpio18"; // Only 2 |
| 2393 | function = "cci_i2c"; |
| 2394 | }; |
| 2395 | |
| 2396 | config { |
| 2397 | pins = "gpio17","gpio18"; |
| 2398 | bias-pull-up; /* PULL UP*/ |
| 2399 | drive-strength = <2>; /* 2 MA */ |
| 2400 | }; |
| 2401 | }; |
| 2402 | |
| 2403 | cci0_suspend: cci0_suspend { |
| 2404 | mux { |
| 2405 | /* CLK, DATA */ |
| 2406 | pins = "gpio17","gpio18"; |
| 2407 | function = "cci_i2c"; |
| 2408 | }; |
| 2409 | |
| 2410 | config { |
| 2411 | pins = "gpio17","gpio18"; |
| 2412 | bias-pull-down; /* PULL DOWN */ |
| 2413 | drive-strength = <2>; /* 2 MA */ |
| 2414 | }; |
| 2415 | }; |
| 2416 | |
| 2417 | cci1_active: cci1_active { |
| 2418 | mux { |
| 2419 | /* CLK, DATA */ |
| 2420 | pins = "gpio19","gpio20"; |
| 2421 | function = "cci_i2c"; |
| 2422 | }; |
| 2423 | |
| 2424 | config { |
| 2425 | pins = "gpio19","gpio20"; |
| 2426 | bias-pull-up; /* PULL UP*/ |
| 2427 | drive-strength = <2>; /* 2 MA */ |
| 2428 | }; |
| 2429 | }; |
| 2430 | |
| 2431 | cci1_suspend: cci1_suspend { |
| 2432 | mux { |
| 2433 | /* CLK, DATA */ |
| 2434 | pins = "gpio19","gpio20"; |
| 2435 | function = "cci_i2c"; |
| 2436 | }; |
| 2437 | |
| 2438 | config { |
| 2439 | pins = "gpio19","gpio20"; |
| 2440 | bias-pull-down; /* PULL DOWN */ |
| 2441 | drive-strength = <2>; /* 2 MA */ |
| 2442 | }; |
| 2443 | }; |
| 2444 | |
| 2445 | cam_sensor_mclk0_active: cam_sensor_mclk0_active { |
| 2446 | /* MCLK0 */ |
| 2447 | mux { |
| 2448 | pins = "gpio13"; |
| 2449 | function = "cam_mclk"; |
| 2450 | }; |
| 2451 | |
| 2452 | config { |
| 2453 | pins = "gpio13"; |
| 2454 | bias-disable; /* No PULL */ |
| 2455 | drive-strength = <2>; /* 2 MA */ |
| 2456 | }; |
| 2457 | }; |
| 2458 | |
| 2459 | cam_sensor_mclk0_suspend: cam_sensor_mclk0_suspend { |
| 2460 | /* MCLK0 */ |
| 2461 | mux { |
| 2462 | pins = "gpio13"; |
| 2463 | function = "cam_mclk"; |
| 2464 | }; |
| 2465 | |
| 2466 | config { |
| 2467 | pins = "gpio13"; |
| 2468 | bias-pull-down; /* PULL DOWN */ |
| 2469 | drive-strength = <2>; /* 2 MA */ |
| 2470 | }; |
| 2471 | }; |
| 2472 | |
| 2473 | cam_sensor_rear_active: cam_sensor_rear_active { |
| 2474 | /* RESET, AVDD LDO */ |
| 2475 | mux { |
| 2476 | pins = "gpio80","gpio79"; |
| 2477 | function = "gpio"; |
| 2478 | }; |
| 2479 | |
| 2480 | config { |
| 2481 | pins = "gpio80","gpio79"; |
| 2482 | bias-disable; /* No PULL */ |
| 2483 | drive-strength = <2>; /* 2 MA */ |
| 2484 | }; |
| 2485 | }; |
| 2486 | |
| 2487 | cam_sensor_rear_suspend: cam_sensor_rear_suspend { |
| 2488 | /* RESET, AVDD LDO */ |
| 2489 | mux { |
| 2490 | pins = "gpio80","gpio79"; |
| 2491 | function = "gpio"; |
| 2492 | }; |
| 2493 | |
| 2494 | config { |
| 2495 | pins = "gpio80","gpio79"; |
| 2496 | bias-disable; /* No PULL */ |
| 2497 | drive-strength = <2>; /* 2 MA */ |
| 2498 | }; |
| 2499 | }; |
| 2500 | |
| 2501 | cam_sensor_mclk1_active: cam_sensor_mclk1_active { |
| 2502 | /* MCLK1 */ |
| 2503 | mux { |
| 2504 | pins = "gpio14"; |
| 2505 | function = "cam_mclk"; |
| 2506 | }; |
| 2507 | |
| 2508 | config { |
| 2509 | pins = "gpio14"; |
| 2510 | bias-disable; /* No PULL */ |
| 2511 | drive-strength = <2>; /* 2 MA */ |
| 2512 | }; |
| 2513 | }; |
| 2514 | |
| 2515 | cam_sensor_mclk1_suspend: cam_sensor_mclk1_suspend { |
| 2516 | /* MCLK1 */ |
| 2517 | mux { |
| 2518 | pins = "gpio14"; |
| 2519 | function = "cam_mclk"; |
| 2520 | }; |
| 2521 | |
| 2522 | config { |
| 2523 | pins = "gpio14"; |
| 2524 | bias-pull-down; /* PULL DOWN */ |
| 2525 | drive-strength = <2>; /* 2 MA */ |
| 2526 | }; |
| 2527 | }; |
| 2528 | |
| 2529 | cam_sensor_front_active: cam_sensor_front_active { |
| 2530 | /* RESET AVDD_LDO*/ |
| 2531 | mux { |
| 2532 | pins = "gpio28", "gpio8"; |
| 2533 | function = "gpio"; |
| 2534 | }; |
| 2535 | |
| 2536 | config { |
| 2537 | pins = "gpio28", "gpio8"; |
| 2538 | bias-disable; /* No PULL */ |
| 2539 | drive-strength = <2>; /* 2 MA */ |
| 2540 | }; |
| 2541 | }; |
| 2542 | |
| 2543 | cam_sensor_front_suspend: cam_sensor_front_suspend { |
| 2544 | /* RESET */ |
| 2545 | mux { |
| 2546 | pins = "gpio28"; |
| 2547 | function = "gpio"; |
| 2548 | }; |
| 2549 | |
| 2550 | config { |
| 2551 | pins = "gpio28"; |
| 2552 | bias-disable; /* No PULL */ |
| 2553 | drive-strength = <2>; /* 2 MA */ |
| 2554 | }; |
| 2555 | }; |
| 2556 | |
| 2557 | cam_sensor_mclk2_active: cam_sensor_mclk2_active { |
| 2558 | /* MCLK1 */ |
| 2559 | mux { |
| 2560 | /* CLK, DATA */ |
| 2561 | pins = "gpio15"; |
| 2562 | function = "cam_mclk"; |
| 2563 | }; |
| 2564 | |
| 2565 | config { |
| 2566 | pins = "gpio15"; |
| 2567 | bias-disable; /* No PULL */ |
| 2568 | drive-strength = <2>; /* 2 MA */ |
| 2569 | }; |
| 2570 | }; |
| 2571 | |
| 2572 | cam_sensor_mclk2_suspend: cam_sensor_mclk2_suspend { |
| 2573 | /* MCLK1 */ |
| 2574 | mux { |
| 2575 | /* CLK, DATA */ |
| 2576 | pins = "gpio15"; |
| 2577 | function = "cam_mclk"; |
| 2578 | }; |
| 2579 | |
| 2580 | config { |
| 2581 | pins = "gpio15"; |
| 2582 | bias-pull-down; /* PULL DOWN */ |
| 2583 | drive-strength = <2>; /* 2 MA */ |
| 2584 | }; |
| 2585 | }; |
| 2586 | |
| 2587 | cam_sensor_rear2_active: cam_sensor_rear2_active { |
| 2588 | /* RESET, STANDBY */ |
| 2589 | mux { |
| 2590 | pins = "gpio9","gpio8"; |
| 2591 | function = "gpio"; |
| 2592 | }; |
| 2593 | |
| 2594 | config { |
| 2595 | pins = "gpio9","gpio8"; |
| 2596 | bias-disable; /* No PULL */ |
| 2597 | drive-strength = <2>; /* 2 MA */ |
| 2598 | }; |
| 2599 | }; |
| 2600 | |
| 2601 | cam_sensor_rear2_suspend: cam_sensor_rear2_suspend { |
| 2602 | /* RESET, STANDBY */ |
| 2603 | mux { |
| 2604 | pins = "gpio9","gpio8"; |
| 2605 | function = "gpio"; |
| 2606 | }; |
| 2607 | config { |
| 2608 | pins = "gpio9","gpio8"; |
| 2609 | bias-disable; /* No PULL */ |
| 2610 | drive-strength = <2>; /* 2 MA */ |
| 2611 | }; |
| 2612 | }; |
Kyle Yan | 679cbee | 2016-07-27 16:55:20 -0700 | [diff] [blame] | 2613 | }; |
| 2614 | }; |
David Collins | c668625 | 2017-03-31 14:23:09 -0700 | [diff] [blame] | 2615 | |
| 2616 | &pm8998_gpios { |
| 2617 | key_home { |
| 2618 | key_home_default: key_home_default { |
| 2619 | pins = "gpio5"; |
| 2620 | function = "normal"; |
| 2621 | input-enable; |
| 2622 | bias-pull-up; |
| 2623 | power-source = <0>; |
| 2624 | }; |
| 2625 | }; |
| 2626 | |
| 2627 | key_vol_up { |
| 2628 | key_vol_up_default: key_vol_up_default { |
| 2629 | pins = "gpio6"; |
| 2630 | function = "normal"; |
| 2631 | input-enable; |
| 2632 | bias-pull-up; |
| 2633 | power-source = <0>; |
| 2634 | }; |
| 2635 | }; |
| 2636 | |
| 2637 | key_cam_snapshot { |
| 2638 | key_cam_snapshot_default: key_cam_snapshot_default { |
| 2639 | pins = "gpio7"; |
| 2640 | function = "normal"; |
| 2641 | input-enable; |
| 2642 | bias-pull-up; |
| 2643 | power-source = <0>; |
| 2644 | }; |
| 2645 | }; |
| 2646 | |
| 2647 | key_cam_focus { |
| 2648 | key_cam_focus_default: key_cam_focus_default { |
| 2649 | pins = "gpio8"; |
| 2650 | function = "normal"; |
| 2651 | input-enable; |
| 2652 | bias-pull-up; |
| 2653 | power-source = <0>; |
| 2654 | }; |
| 2655 | }; |
Jigarkumar Zala | 86123115 | 2017-02-28 14:05:11 -0800 | [diff] [blame] | 2656 | |
| 2657 | camera_dvdd_en { |
| 2658 | camera_dvdd_en_default: camera_dvdd_en_default { |
| 2659 | pins = "gpio9"; |
| 2660 | function = "normal"; |
| 2661 | power-source = <0>; |
| 2662 | output-low; |
| 2663 | }; |
| 2664 | }; |
| 2665 | |
| 2666 | camera_rear_dvdd_en { |
| 2667 | camera_rear_dvdd_en_default: camera_rear_dvdd_en_default { |
| 2668 | pins = "gpio12"; |
| 2669 | function = "normal"; |
| 2670 | power-source = <0>; |
| 2671 | output-low; |
| 2672 | }; |
| 2673 | }; |
David Collins | c668625 | 2017-03-31 14:23:09 -0700 | [diff] [blame] | 2674 | }; |
Jack Pham | c2160c84 | 2017-04-05 09:48:59 -0700 | [diff] [blame] | 2675 | |
| 2676 | &pmi8998_gpios { |
| 2677 | usb2_vbus_boost { |
| 2678 | usb2_vbus_boost_default: usb2_vbus_boost_default { |
| 2679 | pins = "gpio2"; |
| 2680 | function = "normal"; |
| 2681 | output-low; |
| 2682 | power-source = <0>; |
| 2683 | }; |
| 2684 | }; |
| 2685 | |
| 2686 | usb2_vbus_det { |
| 2687 | usb2_vbus_det_default: usb2_vbus_det_default { |
| 2688 | pins = "gpio8"; |
| 2689 | function = "normal"; |
| 2690 | input-enable; |
| 2691 | bias-pull-down; |
| 2692 | power-source = <1>; /* VPH input supply */ |
| 2693 | }; |
| 2694 | }; |
| 2695 | |
| 2696 | usb2_id_det { |
| 2697 | usb2_id_det_default: usb2_id_det_default { |
| 2698 | pins = "gpio9"; |
| 2699 | function = "normal"; |
| 2700 | input-enable; |
| 2701 | bias-pull-up; |
| 2702 | power-source = <0>; |
| 2703 | }; |
| 2704 | }; |
| 2705 | }; |