blob: 9674cc007c15cb5d5103fcdb349639308301b66e [file] [log] [blame]
Clarence Ipaac9f332016-08-31 15:46:35 -04001/* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved.
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07002 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
Alan Kwong1a00e4d2016-07-18 09:42:30 -040012
13#define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
14
Clarence Ip4ce59322016-06-26 22:27:51 -040015#include <linux/debugfs.h>
Clarence Ip5e2a9222016-06-26 22:38:24 -040016#include <uapi/drm/sde_drm.h>
Clarence Ipaa0faf42016-05-30 12:07:48 -040017
18#include "msm_prop.h"
19
Narendra Muppalla1b0b3352015-09-29 10:16:51 -070020#include "sde_kms.h"
Clarence Ipae4e60c2016-06-26 22:44:04 -040021#include "sde_fence.h"
Clarence Ipc475b082016-06-26 09:27:23 -040022#include "sde_formats.h"
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -040023#include "sde_hw_sspp.h"
Alan Kwong1a00e4d2016-07-18 09:42:30 -040024#include "sde_trace.h"
Dhaval Patel48c76022016-09-01 17:51:23 -070025#include "sde_crtc.h"
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -040026
Clarence Ip13a8cf42016-09-29 17:27:47 -040027#define SDE_DEBUG_PLANE(pl, fmt, ...) SDE_DEBUG("plane%d " fmt,\
28 (pl) ? (pl)->base.base.id : -1, ##__VA_ARGS__)
29
30#define SDE_ERROR_PLANE(pl, fmt, ...) SDE_ERROR("plane%d " fmt,\
31 (pl) ? (pl)->base.base.id : -1, ##__VA_ARGS__)
32
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -040033#define DECIMATED_DIMENSION(dim, deci) (((dim) + ((1 << (deci)) - 1)) >> (deci))
34#define PHASE_STEP_SHIFT 21
35#define PHASE_STEP_UNIT_SCALE ((int) (1 << PHASE_STEP_SHIFT))
36#define PHASE_RESIDUAL 15
37
Clarence Ipe78efb72016-06-24 18:35:21 -040038#define SHARP_STRENGTH_DEFAULT 32
39#define SHARP_EDGE_THR_DEFAULT 112
40#define SHARP_SMOOTH_THR_DEFAULT 8
41#define SHARP_NOISE_THR_DEFAULT 2
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -040042
Clarence Ip5e2a9222016-06-26 22:38:24 -040043#define SDE_NAME_SIZE 12
Narendra Muppalla1b0b3352015-09-29 10:16:51 -070044
Clarence Ipcae1bb62016-07-07 12:07:13 -040045#define SDE_PLANE_COLOR_FILL_FLAG BIT(31)
46
Clarence Ip282dad62016-09-27 17:07:35 -040047/* dirty bits for update function */
48#define SDE_PLANE_DIRTY_RECTS 0x1
49#define SDE_PLANE_DIRTY_FORMAT 0x2
50#define SDE_PLANE_DIRTY_SHARPEN 0x4
51#define SDE_PLANE_DIRTY_ALL 0xFFFFFFFF
52
Alan Kwong1a00e4d2016-07-18 09:42:30 -040053/**
54 * enum sde_plane_qos - Different qos configurations for each pipe
55 *
56 * @SDE_PLANE_QOS_VBLANK_CTRL: Setup VBLANK qos for the pipe.
57 * @SDE_PLANE_QOS_VBLANK_AMORTIZE: Enables Amortization within pipe.
58 * this configuration is mutually exclusive from VBLANK_CTRL.
59 * @SDE_PLANE_QOS_PANIC_CTRL: Setup panic for the pipe.
60 */
61enum sde_plane_qos {
62 SDE_PLANE_QOS_VBLANK_CTRL = BIT(0),
63 SDE_PLANE_QOS_VBLANK_AMORTIZE = BIT(1),
64 SDE_PLANE_QOS_PANIC_CTRL = BIT(2),
65};
66
Clarence Ip5fc00c52016-09-23 15:03:34 -040067/*
68 * struct sde_plane - local sde plane structure
69 * @csc_cfg: Decoded user configuration for csc
70 * @csc_usr_ptr: Points to csc_cfg if valid user config available
71 * @csc_ptr: Points to sde_csc_cfg structure to use for current
72 */
Narendra Muppalla1b0b3352015-09-29 10:16:51 -070073struct sde_plane {
74 struct drm_plane base;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -040075
76 int mmu_id;
77
Clarence Ip730e7192016-06-26 22:45:09 -040078 struct mutex lock;
79
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -040080 enum sde_sspp pipe;
81 uint32_t features; /* capabilities from catalog */
Narendra Muppalla1b0b3352015-09-29 10:16:51 -070082 uint32_t nformats;
Lloyd Atkinsonfa2489c2016-05-25 15:16:03 -040083 uint32_t formats[64];
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -040084
85 struct sde_hw_pipe *pipe_hw;
86 struct sde_hw_pipe_cfg pipe_cfg;
Clarence Ipe78efb72016-06-24 18:35:21 -040087 struct sde_hw_sharp_cfg sharp_cfg;
Clarence Ip5e2a9222016-06-26 22:38:24 -040088 struct sde_hw_scaler3_cfg scaler3_cfg;
Alan Kwong1a00e4d2016-07-18 09:42:30 -040089 struct sde_hw_pipe_qos_cfg pipe_qos_cfg;
Clarence Ipcae1bb62016-07-07 12:07:13 -040090 uint32_t color_fill;
91 bool is_error;
Alan Kwong1a00e4d2016-07-18 09:42:30 -040092 bool is_rt_pipe;
Clarence Ip4ce59322016-06-26 22:27:51 -040093
Clarence Ipb43d4592016-09-08 14:21:35 -040094 struct sde_hw_pixel_ext pixel_ext;
95 bool pixel_ext_usr;
96
Clarence Ip373f8592016-05-26 00:58:42 -040097 struct sde_csc_cfg csc_cfg;
Clarence Ip5fc00c52016-09-23 15:03:34 -040098 struct sde_csc_cfg *csc_usr_ptr;
Clarence Ip373f8592016-05-26 00:58:42 -040099 struct sde_csc_cfg *csc_ptr;
100
Clarence Ip4c1d9772016-06-26 09:35:38 -0400101 const struct sde_sspp_sub_blks *pipe_sblk;
102
Clarence Ip5e2a9222016-06-26 22:38:24 -0400103 char pipe_name[SDE_NAME_SIZE];
Clarence Ip4ce59322016-06-26 22:27:51 -0400104
Clarence Ipaa0faf42016-05-30 12:07:48 -0400105 struct msm_property_info property_info;
106 struct msm_property_data property_data[PLANE_PROP_COUNT];
Dhaval Patel4e574842016-08-23 15:11:37 -0700107 struct drm_property_blob *blob_info;
Clarence Ip730e7192016-06-26 22:45:09 -0400108
Clarence Ip4ce59322016-06-26 22:27:51 -0400109 /* debugfs related stuff */
110 struct dentry *debugfs_root;
111 struct sde_debugfs_regset32 debugfs_src;
112 struct sde_debugfs_regset32 debugfs_scaler;
113 struct sde_debugfs_regset32 debugfs_csc;
Narendra Muppalla1b0b3352015-09-29 10:16:51 -0700114};
Dhaval Patel47302cf2016-08-18 15:04:28 -0700115
Narendra Muppalla1b0b3352015-09-29 10:16:51 -0700116#define to_sde_plane(x) container_of(x, struct sde_plane, base)
117
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400118static bool sde_plane_enabled(struct drm_plane_state *state)
119{
Clarence Ipdbde9832016-06-26 09:48:36 -0400120 return state && state->fb && state->crtc;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400121}
122
Alan Kwong1a00e4d2016-07-18 09:42:30 -0400123/**
124 * _sde_plane_calc_fill_level - calculate fill level of the given source format
125 * @plane: Pointer to drm plane
126 * @fmt: Pointer to source buffer format
127 * @src_wdith: width of source buffer
128 * Return: fill level corresponding to the source buffer/format or 0 if error
129 */
130static inline int _sde_plane_calc_fill_level(struct drm_plane *plane,
131 const struct sde_format *fmt, u32 src_width)
132{
133 struct sde_plane *psde;
134 u32 fixed_buff_size;
135 u32 total_fl;
136
137 if (!plane || !fmt) {
138 SDE_ERROR("invalid arguments\n");
139 return 0;
140 }
141
142 psde = to_sde_plane(plane);
143 fixed_buff_size = psde->pipe_sblk->pixel_ram_size;
144
145 if (fmt->fetch_planes == SDE_PLANE_PSEUDO_PLANAR) {
146 if (fmt->chroma_sample == SDE_CHROMA_420) {
147 /* NV12 */
148 total_fl = (fixed_buff_size / 2) /
149 ((src_width + 32) * fmt->bpp);
150 } else {
151 /* non NV12 */
152 total_fl = (fixed_buff_size) /
153 ((src_width + 32) * fmt->bpp);
154 }
155 } else {
156 total_fl = (fixed_buff_size * 2) /
157 ((src_width + 32) * fmt->bpp);
158 }
159
160 SDE_DEBUG("plane%u: pnum:%d fmt:%x w:%u fl:%u\n",
161 plane->base.id, psde->pipe - SSPP_VIG0,
162 fmt->base.pixel_format, src_width, total_fl);
163
164 return total_fl;
165}
166
167/**
168 * _sde_plane_get_qos_lut_linear - get linear LUT mapping
169 * @total_fl: fill level
170 * Return: LUT setting corresponding to the fill level
171 */
172static inline u32 _sde_plane_get_qos_lut_linear(u32 total_fl)
173{
174 u32 qos_lut;
175
176 if (total_fl <= 4)
177 qos_lut = 0x1B;
178 else if (total_fl <= 5)
179 qos_lut = 0x5B;
180 else if (total_fl <= 6)
181 qos_lut = 0x15B;
182 else if (total_fl <= 7)
183 qos_lut = 0x55B;
184 else if (total_fl <= 8)
185 qos_lut = 0x155B;
186 else if (total_fl <= 9)
187 qos_lut = 0x555B;
188 else if (total_fl <= 10)
189 qos_lut = 0x1555B;
190 else if (total_fl <= 11)
191 qos_lut = 0x5555B;
192 else if (total_fl <= 12)
193 qos_lut = 0x15555B;
194 else
195 qos_lut = 0x55555B;
196
197 return qos_lut;
198}
199
200/**
201 * _sde_plane_get_qos_lut_macrotile - get macrotile LUT mapping
202 * @total_fl: fill level
203 * Return: LUT setting corresponding to the fill level
204 */
205static inline u32 _sde_plane_get_qos_lut_macrotile(u32 total_fl)
206{
207 u32 qos_lut;
208
209 if (total_fl <= 10)
210 qos_lut = 0x1AAff;
211 else if (total_fl <= 11)
212 qos_lut = 0x5AAFF;
213 else if (total_fl <= 12)
214 qos_lut = 0x15AAFF;
215 else
216 qos_lut = 0x55AAFF;
217
218 return qos_lut;
219}
220
221/**
222 * _sde_plane_is_rt_pipe - check if the given plane requires real-time QoS
223 * @plane: Pointer to drm plane
224 * @crtc: Pointer to drm crtc associated with the given plane
225 */
226static bool _sde_plane_is_rt_pipe(struct drm_plane *plane,
227 struct drm_crtc *crtc)
228{
229 struct sde_plane *psde = to_sde_plane(plane);
230 struct drm_connector *connector;
231 bool is_rt = false;
232
233 /* check if this plane has a physical connector interface */
234 drm_for_each_connector(connector, plane->dev)
235 if (connector->state &&
236 (connector->state->crtc == crtc) &&
237 (connector->connector_type
238 != DRM_MODE_CONNECTOR_VIRTUAL)) {
239 is_rt = true;
240 break;
241 }
242
243 SDE_DEBUG("plane%u: pnum:%d rt:%d\n",
244 plane->base.id, psde->pipe - SSPP_VIG0, is_rt);
245
246 return is_rt;
247}
248
249/**
250 * _sde_plane_set_qos_lut - set QoS LUT of the given plane
251 * @plane: Pointer to drm plane
252 * @fb: Pointer to framebuffer associated with the given plane
253 */
254static void _sde_plane_set_qos_lut(struct drm_plane *plane,
255 struct drm_framebuffer *fb)
256{
257 struct sde_plane *psde;
258 const struct sde_format *fmt = NULL;
259 u32 qos_lut;
260 u32 total_fl = 0;
261
262 if (!plane || !fb) {
263 SDE_ERROR("invalid arguments plane %d fb %d\n",
264 plane != 0, fb != 0);
265 return;
266 }
267
268 psde = to_sde_plane(plane);
269
270 if (!psde->pipe_hw || !psde->pipe_sblk) {
271 SDE_ERROR("invalid arguments\n");
272 return;
273 } else if (!psde->pipe_hw->ops.setup_creq_lut) {
274 return;
275 }
276
277 if (!psde->is_rt_pipe) {
278 qos_lut = psde->pipe_sblk->creq_lut_nrt;
279 } else {
280 fmt = sde_get_sde_format_ext(
281 fb->pixel_format,
282 fb->modifier,
283 drm_format_num_planes(fb->pixel_format));
284 total_fl = _sde_plane_calc_fill_level(plane, fmt,
285 psde->pipe_cfg.src_rect.w);
286
287 if (SDE_FORMAT_IS_LINEAR(fmt))
288 qos_lut = _sde_plane_get_qos_lut_linear(total_fl);
289 else
290 qos_lut = _sde_plane_get_qos_lut_macrotile(total_fl);
291 }
292
293 psde->pipe_qos_cfg.creq_lut = qos_lut;
294
295 trace_sde_perf_set_qos_luts(psde->pipe - SSPP_VIG0,
296 (fmt) ? fmt->base.pixel_format : 0,
297 psde->is_rt_pipe, total_fl, qos_lut,
298 (fmt) ? SDE_FORMAT_IS_LINEAR(fmt) : 0);
299
300 SDE_DEBUG("plane%u: pnum:%d fmt:%x rt:%d fl:%u lut:0x%x\n",
301 plane->base.id,
302 psde->pipe - SSPP_VIG0,
303 (fmt) ? fmt->base.pixel_format : 0,
304 psde->is_rt_pipe, total_fl, qos_lut);
305
306 psde->pipe_hw->ops.setup_creq_lut(psde->pipe_hw, &psde->pipe_qos_cfg);
307}
308
309/**
310 * _sde_plane_set_panic_lut - set danger/safe LUT of the given plane
311 * @plane: Pointer to drm plane
312 * @fb: Pointer to framebuffer associated with the given plane
313 */
314static void _sde_plane_set_danger_lut(struct drm_plane *plane,
315 struct drm_framebuffer *fb)
316{
317 struct sde_plane *psde;
318 const struct sde_format *fmt = NULL;
319 u32 danger_lut, safe_lut;
320
321 if (!plane || !fb) {
322 SDE_ERROR("invalid arguments\n");
323 return;
324 }
325
326 psde = to_sde_plane(plane);
327
328 if (!psde->pipe_hw || !psde->pipe_sblk) {
329 SDE_ERROR("invalid arguments\n");
330 return;
331 } else if (!psde->pipe_hw->ops.setup_danger_safe_lut) {
332 return;
333 }
334
335 if (!psde->is_rt_pipe) {
336 danger_lut = psde->pipe_sblk->danger_lut_nrt;
337 safe_lut = psde->pipe_sblk->safe_lut_nrt;
338 } else {
339 fmt = sde_get_sde_format_ext(
340 fb->pixel_format,
341 fb->modifier,
342 drm_format_num_planes(fb->pixel_format));
343
344 if (SDE_FORMAT_IS_LINEAR(fmt)) {
345 danger_lut = psde->pipe_sblk->danger_lut_linear;
346 safe_lut = psde->pipe_sblk->safe_lut_linear;
347 } else {
348 danger_lut = psde->pipe_sblk->danger_lut_tile;
349 safe_lut = psde->pipe_sblk->safe_lut_tile;
350 }
351 }
352
353 psde->pipe_qos_cfg.danger_lut = danger_lut;
354 psde->pipe_qos_cfg.safe_lut = safe_lut;
355
356 trace_sde_perf_set_danger_luts(psde->pipe - SSPP_VIG0,
357 (fmt) ? fmt->base.pixel_format : 0,
358 (fmt) ? fmt->fetch_mode : 0,
359 psde->pipe_qos_cfg.danger_lut,
360 psde->pipe_qos_cfg.safe_lut);
361
362 SDE_DEBUG("plane%u: pnum:%d fmt:%x mode:%d luts[0x%x, 0x%x]\n",
363 plane->base.id,
364 psde->pipe - SSPP_VIG0,
365 fmt ? fmt->base.pixel_format : 0,
366 fmt ? fmt->fetch_mode : -1,
367 psde->pipe_qos_cfg.danger_lut,
368 psde->pipe_qos_cfg.safe_lut);
369
370 psde->pipe_hw->ops.setup_danger_safe_lut(psde->pipe_hw,
371 &psde->pipe_qos_cfg);
372}
373
374/**
375 * _sde_plane_set_qos_ctrl - set QoS control of the given plane
376 * @plane: Pointer to drm plane
377 * @enable: true to enable QoS control
378 * @flags: QoS control mode (enum sde_plane_qos)
379 */
380static void _sde_plane_set_qos_ctrl(struct drm_plane *plane,
381 bool enable, u32 flags)
382{
383 struct sde_plane *psde;
384
385 if (!plane) {
386 SDE_ERROR("invalid arguments\n");
387 return;
388 }
389
390 psde = to_sde_plane(plane);
391
392 if (!psde->pipe_hw || !psde->pipe_sblk) {
393 SDE_ERROR("invalid arguments\n");
394 return;
395 } else if (!psde->pipe_hw->ops.setup_qos_ctrl) {
396 return;
397 }
398
399 if (flags & SDE_PLANE_QOS_VBLANK_CTRL) {
400 psde->pipe_qos_cfg.creq_vblank = psde->pipe_sblk->creq_vblank;
401 psde->pipe_qos_cfg.danger_vblank =
402 psde->pipe_sblk->danger_vblank;
403 psde->pipe_qos_cfg.vblank_en = enable;
404 }
405
406 if (flags & SDE_PLANE_QOS_VBLANK_AMORTIZE) {
407 /* this feature overrules previous VBLANK_CTRL */
408 psde->pipe_qos_cfg.vblank_en = false;
409 psde->pipe_qos_cfg.creq_vblank = 0; /* clear vblank bits */
410 }
411
412 if (flags & SDE_PLANE_QOS_PANIC_CTRL)
413 psde->pipe_qos_cfg.danger_safe_en = enable;
414
415 if (!psde->is_rt_pipe) {
416 psde->pipe_qos_cfg.vblank_en = false;
417 psde->pipe_qos_cfg.danger_safe_en = false;
418 }
419
420 SDE_DEBUG("plane%u: pnum:%d ds:%d vb:%d pri[0x%x, 0x%x]\n",
421 plane->base.id,
422 psde->pipe - SSPP_VIG0,
423 psde->pipe_qos_cfg.danger_safe_en,
424 psde->pipe_qos_cfg.vblank_en,
425 psde->pipe_qos_cfg.creq_vblank,
426 psde->pipe_qos_cfg.danger_vblank);
427
428 psde->pipe_hw->ops.setup_qos_ctrl(psde->pipe_hw,
429 &psde->pipe_qos_cfg);
430}
431
Alan Kwong5d324e42016-07-28 22:56:18 -0400432/**
433 * _sde_plane_set_ot_limit - set OT limit for the given plane
434 * @plane: Pointer to drm plane
435 * @crtc: Pointer to drm crtc
436 */
437static void _sde_plane_set_ot_limit(struct drm_plane *plane,
438 struct drm_crtc *crtc)
439{
440 struct sde_plane *psde;
441 struct sde_vbif_set_ot_params ot_params;
442 struct msm_drm_private *priv;
443 struct sde_kms *sde_kms;
444
445 if (!plane || !plane->dev || !crtc) {
446 SDE_ERROR("invalid arguments plane %d crtc %d\n",
447 plane != 0, crtc != 0);
448 return;
449 }
450
451 priv = plane->dev->dev_private;
452 if (!priv || !priv->kms) {
453 SDE_ERROR("invalid KMS reference\n");
454 return;
455 }
456
457 sde_kms = to_sde_kms(priv->kms);
458 psde = to_sde_plane(plane);
459 if (!psde->pipe_hw) {
460 SDE_ERROR("invalid pipe reference\n");
461 return;
462 }
463
464 memset(&ot_params, 0, sizeof(ot_params));
465 ot_params.xin_id = psde->pipe_hw->cap->xin_id;
466 ot_params.num = psde->pipe_hw->idx - SSPP_NONE;
467 ot_params.width = psde->pipe_cfg.src_rect.w;
468 ot_params.height = psde->pipe_cfg.src_rect.h;
469 ot_params.is_wfd = !psde->is_rt_pipe;
470 ot_params.frame_rate = crtc->mode.vrefresh;
471 ot_params.vbif_idx = VBIF_RT;
472 ot_params.clk_ctrl = psde->pipe_hw->cap->clk_ctrl;
473 ot_params.rd = true;
474
475 sde_vbif_set_ot_limit(sde_kms, &ot_params);
476}
477
Clarence Ipcae1bb62016-07-07 12:07:13 -0400478/* helper to update a state's input fence pointer from the property */
Clarence Ip13a8cf42016-09-29 17:27:47 -0400479static void _sde_plane_set_input_fence(struct sde_plane *psde,
Clarence Ipae4e60c2016-06-26 22:44:04 -0400480 struct sde_plane_state *pstate, uint64_t fd)
481{
Clarence Ip13a8cf42016-09-29 17:27:47 -0400482 if (!psde || !pstate) {
483 SDE_ERROR("invalid arg(s), plane %d state %d\n",
484 psde != 0, pstate != 0);
Clarence Ipae4e60c2016-06-26 22:44:04 -0400485 return;
Clarence Ip13a8cf42016-09-29 17:27:47 -0400486 }
Clarence Ipae4e60c2016-06-26 22:44:04 -0400487
488 /* clear previous reference */
Clarence Ipcae1bb62016-07-07 12:07:13 -0400489 if (pstate->input_fence)
490 sde_sync_put(pstate->input_fence);
Clarence Ipae4e60c2016-06-26 22:44:04 -0400491
492 /* get fence pointer for later */
Clarence Ipcae1bb62016-07-07 12:07:13 -0400493 pstate->input_fence = sde_sync_get(fd);
Clarence Ipae4e60c2016-06-26 22:44:04 -0400494
Clarence Ip13a8cf42016-09-29 17:27:47 -0400495 SDE_DEBUG_PLANE(psde, "0x%llX\n", fd);
Clarence Ipae4e60c2016-06-26 22:44:04 -0400496}
497
Clarence Ipcae1bb62016-07-07 12:07:13 -0400498int sde_plane_wait_input_fence(struct drm_plane *plane, uint32_t wait_ms)
Clarence Ipae4e60c2016-06-26 22:44:04 -0400499{
Clarence Ipcae1bb62016-07-07 12:07:13 -0400500 struct sde_plane *psde;
Clarence Ipae4e60c2016-06-26 22:44:04 -0400501 struct sde_plane_state *pstate;
Clarence Ipcae1bb62016-07-07 12:07:13 -0400502 void *input_fence;
Clarence Ipcb410d42016-06-26 22:52:33 -0400503 int ret = -EINVAL;
Clarence Ipae4e60c2016-06-26 22:44:04 -0400504
505 if (!plane) {
Dhaval Patel47302cf2016-08-18 15:04:28 -0700506 SDE_ERROR("invalid plane\n");
Clarence Ipae4e60c2016-06-26 22:44:04 -0400507 } else if (!plane->state) {
Clarence Ip13a8cf42016-09-29 17:27:47 -0400508 SDE_ERROR_PLANE(to_sde_plane(plane), "invalid state\n");
Clarence Ipae4e60c2016-06-26 22:44:04 -0400509 } else {
Clarence Ipcae1bb62016-07-07 12:07:13 -0400510 psde = to_sde_plane(plane);
Clarence Ipae4e60c2016-06-26 22:44:04 -0400511 pstate = to_sde_plane_state(plane->state);
Clarence Ipcae1bb62016-07-07 12:07:13 -0400512 input_fence = pstate->input_fence;
Clarence Ipae4e60c2016-06-26 22:44:04 -0400513
Clarence Ipcae1bb62016-07-07 12:07:13 -0400514 if (input_fence) {
515 ret = sde_sync_wait(input_fence, wait_ms);
516 switch (ret) {
517 case 0:
Clarence Ip13a8cf42016-09-29 17:27:47 -0400518 SDE_DEBUG_PLANE(psde, "signaled\n");
Clarence Ipcae1bb62016-07-07 12:07:13 -0400519 break;
520 case -ETIME:
Clarence Ip13a8cf42016-09-29 17:27:47 -0400521 SDE_ERROR_PLANE(psde, "timeout, %ums\n",
522 wait_ms);
Clarence Ipcae1bb62016-07-07 12:07:13 -0400523 psde->is_error = true;
524 break;
525 default:
Clarence Ip13a8cf42016-09-29 17:27:47 -0400526 SDE_ERROR_PLANE(psde, "error, %d\n", ret);
Clarence Ipcae1bb62016-07-07 12:07:13 -0400527 psde->is_error = true;
528 break;
529 }
Clarence Ipcb410d42016-06-26 22:52:33 -0400530 } else {
531 ret = 0;
532 }
Clarence Ipae4e60c2016-06-26 22:44:04 -0400533 }
Clarence Ipae4e60c2016-06-26 22:44:04 -0400534 return ret;
535}
536
Clarence Ip282dad62016-09-27 17:07:35 -0400537static inline void _sde_plane_set_scanout(struct drm_plane *plane,
Clarence Ip5e2a9222016-06-26 22:38:24 -0400538 struct sde_plane_state *pstate,
Lloyd Atkinsonfa2489c2016-05-25 15:16:03 -0400539 struct sde_hw_pipe_cfg *pipe_cfg,
540 struct drm_framebuffer *fb)
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400541{
Clarence Ipae4e60c2016-06-26 22:44:04 -0400542 struct sde_plane *psde;
Clarence Ip282dad62016-09-27 17:07:35 -0400543 int ret;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400544
Clarence Ip13a8cf42016-09-29 17:27:47 -0400545 if (!plane || !pstate || !pipe_cfg || !fb) {
546 SDE_ERROR(
547 "invalid arg(s), plane %d state %d cfg %d fb %d\n",
548 plane != 0, pstate != 0, pipe_cfg != 0, fb != 0);
Clarence Ipae4e60c2016-06-26 22:44:04 -0400549 return;
Clarence Ip13a8cf42016-09-29 17:27:47 -0400550 }
Clarence Ipae4e60c2016-06-26 22:44:04 -0400551
552 psde = to_sde_plane(plane);
Clarence Ipb6eb2362016-09-08 16:18:13 -0400553 if (!psde->pipe_hw) {
554 SDE_ERROR_PLANE(psde, "invalid pipe_hw\n");
Lloyd Atkinsonfa2489c2016-05-25 15:16:03 -0400555 return;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400556 }
Lloyd Atkinsonfa2489c2016-05-25 15:16:03 -0400557
Clarence Ipb6eb2362016-09-08 16:18:13 -0400558 ret = sde_format_populate_layout(psde->mmu_id, fb, &pipe_cfg->layout);
559 if (ret == -EAGAIN)
560 SDE_DEBUG_PLANE(psde, "not updating same src addrs\n");
561 else if (ret)
562 SDE_ERROR_PLANE(psde, "failed to get format layout, %d\n", ret);
563 else if (psde->pipe_hw->ops.setup_sourceaddress)
Lloyd Atkinsonfa2489c2016-05-25 15:16:03 -0400564 psde->pipe_hw->ops.setup_sourceaddress(psde->pipe_hw, pipe_cfg);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400565}
566
Clarence Ipcb410d42016-06-26 22:52:33 -0400567static void _sde_plane_setup_scaler3(struct sde_plane *psde,
Clarence Ip5e2a9222016-06-26 22:38:24 -0400568 uint32_t src_w, uint32_t src_h, uint32_t dst_w, uint32_t dst_h,
569 struct sde_hw_scaler3_cfg *scale_cfg,
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400570 const struct sde_format *fmt,
Clarence Ip5e2a9222016-06-26 22:38:24 -0400571 uint32_t chroma_subsmpl_h, uint32_t chroma_subsmpl_v)
572{
573}
574
Clarence Ipcb410d42016-06-26 22:52:33 -0400575/**
Clarence Ip13a8cf42016-09-29 17:27:47 -0400576 * _sde_plane_setup_scaler2 - determine default scaler phase steps/filter type
Clarence Ipcb410d42016-06-26 22:52:33 -0400577 * @psde: Pointer to SDE plane object
578 * @src: Source size
579 * @dst: Destination size
580 * @phase_steps: Pointer to output array for phase steps
581 * @filter: Pointer to output array for filter type
582 * @fmt: Pointer to format definition
583 * @chroma_subsampling: Subsampling amount for chroma channel
584 *
585 * Returns: 0 on success
586 */
587static int _sde_plane_setup_scaler2(struct sde_plane *psde,
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400588 uint32_t src, uint32_t dst, uint32_t *phase_steps,
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400589 enum sde_hw_filter *filter, const struct sde_format *fmt,
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400590 uint32_t chroma_subsampling)
591{
Clarence Ipcb410d42016-06-26 22:52:33 -0400592 if (!psde || !phase_steps || !filter || !fmt) {
Clarence Ip13a8cf42016-09-29 17:27:47 -0400593 SDE_ERROR(
594 "invalid arg(s), plane %d phase %d filter %d fmt %d\n",
595 psde != 0, phase_steps != 0, filter != 0, fmt != 0);
Clarence Ipcb410d42016-06-26 22:52:33 -0400596 return -EINVAL;
597 }
598
Clarence Ip4c1d9772016-06-26 09:35:38 -0400599 /* calculate phase steps, leave init phase as zero */
Clarence Ipe78efb72016-06-24 18:35:21 -0400600 phase_steps[SDE_SSPP_COMP_0] =
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400601 mult_frac(1 << PHASE_STEP_SHIFT, src, dst);
Clarence Ipe78efb72016-06-24 18:35:21 -0400602 phase_steps[SDE_SSPP_COMP_1_2] =
603 phase_steps[SDE_SSPP_COMP_0] / chroma_subsampling;
604 phase_steps[SDE_SSPP_COMP_2] = phase_steps[SDE_SSPP_COMP_1_2];
605 phase_steps[SDE_SSPP_COMP_3] = phase_steps[SDE_SSPP_COMP_0];
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400606
607 /* calculate scaler config, if necessary */
Clarence Ipdbde9832016-06-26 09:48:36 -0400608 if (SDE_FORMAT_IS_YUV(fmt) || src != dst) {
Clarence Ipe78efb72016-06-24 18:35:21 -0400609 filter[SDE_SSPP_COMP_3] =
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400610 (src <= dst) ? SDE_SCALE_FILTER_BIL :
611 SDE_SCALE_FILTER_PCMN;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400612
Clarence Ipdbde9832016-06-26 09:48:36 -0400613 if (SDE_FORMAT_IS_YUV(fmt)) {
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400614 filter[SDE_SSPP_COMP_0] = SDE_SCALE_FILTER_CA;
Clarence Ipe78efb72016-06-24 18:35:21 -0400615 filter[SDE_SSPP_COMP_1_2] = filter[SDE_SSPP_COMP_3];
616 } else {
617 filter[SDE_SSPP_COMP_0] = filter[SDE_SSPP_COMP_3];
618 filter[SDE_SSPP_COMP_1_2] =
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400619 SDE_SCALE_FILTER_NEAREST;
Clarence Ipe78efb72016-06-24 18:35:21 -0400620 }
621 } else {
622 /* disable scaler */
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400623 filter[SDE_SSPP_COMP_0] = SDE_SCALE_FILTER_MAX;
624 filter[SDE_SSPP_COMP_1_2] = SDE_SCALE_FILTER_MAX;
625 filter[SDE_SSPP_COMP_3] = SDE_SCALE_FILTER_MAX;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400626 }
Clarence Ipcb410d42016-06-26 22:52:33 -0400627 return 0;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400628}
629
Clarence Ipcb410d42016-06-26 22:52:33 -0400630/**
631 * _sde_plane_setup_pixel_ext - determine default pixel extension values
632 * @psde: Pointer to SDE plane object
633 * @src: Source size
634 * @dst: Destination size
635 * @decimated_src: Source size after decimation, if any
636 * @phase_steps: Pointer to output array for phase steps
637 * @out_src: Output array for pixel extension values
638 * @out_edge1: Output array for pixel extension first edge
639 * @out_edge2: Output array for pixel extension second edge
640 * @filter: Pointer to array for filter type
641 * @fmt: Pointer to format definition
642 * @chroma_subsampling: Subsampling amount for chroma channel
643 * @post_compare: Whether to chroma subsampled source size for comparisions
644 */
645static void _sde_plane_setup_pixel_ext(struct sde_plane *psde,
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400646 uint32_t src, uint32_t dst, uint32_t decimated_src,
647 uint32_t *phase_steps, uint32_t *out_src, int *out_edge1,
Clarence Ipe78efb72016-06-24 18:35:21 -0400648 int *out_edge2, enum sde_hw_filter *filter,
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400649 const struct sde_format *fmt, uint32_t chroma_subsampling,
Clarence Ipe78efb72016-06-24 18:35:21 -0400650 bool post_compare)
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400651{
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400652 int64_t edge1, edge2, caf;
653 uint32_t src_work;
654 int i, tmp;
655
Clarence Ipcb410d42016-06-26 22:52:33 -0400656 if (psde && phase_steps && out_src && out_edge1 &&
Clarence Ipe78efb72016-06-24 18:35:21 -0400657 out_edge2 && filter && fmt) {
658 /* handle CAF for YUV formats */
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400659 if (SDE_FORMAT_IS_YUV(fmt) && *filter == SDE_SCALE_FILTER_CA)
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400660 caf = PHASE_STEP_UNIT_SCALE;
661 else
662 caf = 0;
663
664 for (i = 0; i < SDE_MAX_PLANES; i++) {
665 src_work = decimated_src;
Clarence Ipe78efb72016-06-24 18:35:21 -0400666 if (i == SDE_SSPP_COMP_1_2 || i == SDE_SSPP_COMP_2)
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400667 src_work /= chroma_subsampling;
668 if (post_compare)
669 src = src_work;
Clarence Ipdbde9832016-06-26 09:48:36 -0400670 if (!SDE_FORMAT_IS_YUV(fmt) && (src == dst)) {
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400671 /* unity */
672 edge1 = 0;
673 edge2 = 0;
674 } else if (dst >= src) {
675 /* upscale */
676 edge1 = (1 << PHASE_RESIDUAL);
677 edge1 -= caf;
678 edge2 = (1 << PHASE_RESIDUAL);
679 edge2 += (dst - 1) * *(phase_steps + i);
680 edge2 -= (src_work - 1) * PHASE_STEP_UNIT_SCALE;
681 edge2 += caf;
682 edge2 = -(edge2);
683 } else {
684 /* downscale */
685 edge1 = 0;
686 edge2 = (dst - 1) * *(phase_steps + i);
687 edge2 -= (src_work - 1) * PHASE_STEP_UNIT_SCALE;
688 edge2 += *(phase_steps + i);
689 edge2 = -(edge2);
690 }
691
692 /* only enable CAF for luma plane */
693 caf = 0;
694
695 /* populate output arrays */
696 *(out_src + i) = src_work;
697
698 /* edge updates taken from __pxl_extn_helper */
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400699 if (edge1 >= 0) {
700 tmp = (uint32_t)edge1;
701 tmp >>= PHASE_STEP_SHIFT;
702 *(out_edge1 + i) = -tmp;
703 } else {
704 tmp = (uint32_t)(-edge1);
Clarence Ipe78efb72016-06-24 18:35:21 -0400705 *(out_edge1 + i) =
706 (tmp + PHASE_STEP_UNIT_SCALE - 1) >>
707 PHASE_STEP_SHIFT;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400708 }
709 if (edge2 >= 0) {
710 tmp = (uint32_t)edge2;
711 tmp >>= PHASE_STEP_SHIFT;
712 *(out_edge2 + i) = -tmp;
713 } else {
714 tmp = (uint32_t)(-edge2);
Clarence Ipe78efb72016-06-24 18:35:21 -0400715 *(out_edge2 + i) =
716 (tmp + PHASE_STEP_UNIT_SCALE - 1) >>
717 PHASE_STEP_SHIFT;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400718 }
719 }
720 }
721}
722
Clarence Ip5fc00c52016-09-23 15:03:34 -0400723static inline void _sde_plane_setup_csc(struct sde_plane *psde)
Clarence Ipe78efb72016-06-24 18:35:21 -0400724{
725 static const struct sde_csc_cfg sde_csc_YUV2RGB_601L = {
726 {
Clarence Ip373f8592016-05-26 00:58:42 -0400727 /* S15.16 format */
728 0x00012A00, 0x00000000, 0x00019880,
729 0x00012A00, 0xFFFF9B80, 0xFFFF3000,
730 0x00012A00, 0x00020480, 0x00000000,
Clarence Ipe78efb72016-06-24 18:35:21 -0400731 },
Clarence Ip373f8592016-05-26 00:58:42 -0400732 /* signed bias */
Clarence Ipe78efb72016-06-24 18:35:21 -0400733 { 0xfff0, 0xff80, 0xff80,},
734 { 0x0, 0x0, 0x0,},
Clarence Ip373f8592016-05-26 00:58:42 -0400735 /* unsigned clamp */
Clarence Ipe78efb72016-06-24 18:35:21 -0400736 { 0x10, 0xeb, 0x10, 0xf0, 0x10, 0xf0,},
Clarence Ip373f8592016-05-26 00:58:42 -0400737 { 0x00, 0xff, 0x00, 0xff, 0x00, 0xff,},
Clarence Ipe78efb72016-06-24 18:35:21 -0400738 };
Clarence Ipe78efb72016-06-24 18:35:21 -0400739
Clarence Ip5fc00c52016-09-23 15:03:34 -0400740 if (!psde) {
741 SDE_ERROR("invalid plane\n");
Clarence Ipaa0faf42016-05-30 12:07:48 -0400742 return;
743 }
Clarence Ip5e2a9222016-06-26 22:38:24 -0400744
Clarence Ipcae1bb62016-07-07 12:07:13 -0400745 /* revert to kernel default if override not available */
Clarence Ip5fc00c52016-09-23 15:03:34 -0400746 if (psde->csc_usr_ptr)
747 psde->csc_ptr = psde->csc_usr_ptr;
748 else
Clarence Ip373f8592016-05-26 00:58:42 -0400749 psde->csc_ptr = (struct sde_csc_cfg *)&sde_csc_YUV2RGB_601L;
Clarence Ip5fc00c52016-09-23 15:03:34 -0400750
Clarence Ip13a8cf42016-09-29 17:27:47 -0400751 SDE_DEBUG_PLANE(psde, "using 0x%X 0x%X 0x%X...\n",
Clarence Ip5fc00c52016-09-23 15:03:34 -0400752 psde->csc_ptr->csc_mv[0],
753 psde->csc_ptr->csc_mv[1],
754 psde->csc_ptr->csc_mv[2]);
Clarence Ipe78efb72016-06-24 18:35:21 -0400755}
756
Clarence Ipcb410d42016-06-26 22:52:33 -0400757static void _sde_plane_setup_scaler(struct sde_plane *psde,
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400758 const struct sde_format *fmt,
Clarence Ipcb410d42016-06-26 22:52:33 -0400759 struct sde_plane_state *pstate)
Narendra Muppalla1b0b3352015-09-29 10:16:51 -0700760{
Clarence Ipb43d4592016-09-08 14:21:35 -0400761 struct sde_hw_pixel_ext *pe;
Clarence Ipcb410d42016-06-26 22:52:33 -0400762 uint32_t chroma_subsmpl_h, chroma_subsmpl_v;
Clarence Ipb43d4592016-09-08 14:21:35 -0400763 uint32_t tmp, i;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400764
Clarence Ipb43d4592016-09-08 14:21:35 -0400765 if (!psde || !fmt) {
766 SDE_ERROR("invalid arg(s), plane %d fmt %d state %d\n",
767 psde != 0, fmt != 0, pstate != 0);
Clarence Ipcb410d42016-06-26 22:52:33 -0400768 return;
Clarence Ipb43d4592016-09-08 14:21:35 -0400769 }
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400770
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400771 pe = &(psde->pixel_ext);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400772
Clarence Ipdedbba92016-09-27 17:43:10 -0400773 psde->pipe_cfg.horz_decimation =
774 sde_plane_get_property(pstate, PLANE_PROP_H_DECIMATE);
775 psde->pipe_cfg.vert_decimation =
776 sde_plane_get_property(pstate, PLANE_PROP_V_DECIMATE);
Clarence Ip04ec67d2016-05-26 01:16:15 -0400777
778 /* don't chroma subsample if decimating */
779 chroma_subsmpl_h = psde->pipe_cfg.horz_decimation ? 1 :
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400780 drm_format_horz_chroma_subsampling(fmt->base.pixel_format);
Clarence Ip04ec67d2016-05-26 01:16:15 -0400781 chroma_subsmpl_v = psde->pipe_cfg.vert_decimation ? 1 :
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400782 drm_format_vert_chroma_subsampling(fmt->base.pixel_format);
Clarence Ip04ec67d2016-05-26 01:16:15 -0400783
Clarence Ip5e2a9222016-06-26 22:38:24 -0400784 /* update scaler */
785 if (psde->features & BIT(SDE_SSPP_SCALER_QSEED3)) {
Clarence Ipb43d4592016-09-08 14:21:35 -0400786 if (!psde->pixel_ext_usr) {
787 /* calculate default config for QSEED3 */
Clarence Ipcb410d42016-06-26 22:52:33 -0400788 _sde_plane_setup_scaler3(psde,
789 psde->pipe_cfg.src_rect.w,
790 psde->pipe_cfg.src_rect.h,
791 psde->pipe_cfg.dst_rect.w,
792 psde->pipe_cfg.dst_rect.h,
793 &psde->scaler3_cfg, fmt,
Clarence Ip5e2a9222016-06-26 22:38:24 -0400794 chroma_subsmpl_h, chroma_subsmpl_v);
Clarence Ip5e2a9222016-06-26 22:38:24 -0400795 }
Clarence Ipb43d4592016-09-08 14:21:35 -0400796 } else if (!psde->pixel_ext_usr) {
797 /* calculate default configuration for QSEED2 */
798 memset(pe, 0, sizeof(struct sde_hw_pixel_ext));
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400799
Clarence Ip13a8cf42016-09-29 17:27:47 -0400800 SDE_DEBUG_PLANE(psde, "default config\n");
Clarence Ipb43d4592016-09-08 14:21:35 -0400801 _sde_plane_setup_scaler2(psde,
802 psde->pipe_cfg.src_rect.w,
803 psde->pipe_cfg.dst_rect.w,
804 pe->phase_step_x,
805 pe->horz_filter, fmt, chroma_subsmpl_h);
806 _sde_plane_setup_scaler2(psde,
807 psde->pipe_cfg.src_rect.h,
808 psde->pipe_cfg.dst_rect.h,
809 pe->phase_step_y,
810 pe->vert_filter, fmt, chroma_subsmpl_v);
Clarence Ip5e2a9222016-06-26 22:38:24 -0400811
Clarence Ip5e2a9222016-06-26 22:38:24 -0400812 /* calculate left/right/top/bottom pixel extensions */
Clarence Ipcb410d42016-06-26 22:52:33 -0400813 tmp = DECIMATED_DIMENSION(psde->pipe_cfg.src_rect.w,
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400814 psde->pipe_cfg.horz_decimation);
Clarence Ipdbde9832016-06-26 09:48:36 -0400815 if (SDE_FORMAT_IS_YUV(fmt))
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400816 tmp &= ~0x1;
Clarence Ipcb410d42016-06-26 22:52:33 -0400817 _sde_plane_setup_pixel_ext(psde, psde->pipe_cfg.src_rect.w,
818 psde->pipe_cfg.dst_rect.w, tmp,
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400819 pe->phase_step_x,
820 pe->roi_w,
821 pe->num_ext_pxls_left,
Clarence Ipe78efb72016-06-24 18:35:21 -0400822 pe->num_ext_pxls_right, pe->horz_filter, fmt,
Clarence Ip5e2a9222016-06-26 22:38:24 -0400823 chroma_subsmpl_h, 0);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400824
Clarence Ipcb410d42016-06-26 22:52:33 -0400825 tmp = DECIMATED_DIMENSION(psde->pipe_cfg.src_rect.h,
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400826 psde->pipe_cfg.vert_decimation);
Clarence Ipcb410d42016-06-26 22:52:33 -0400827 _sde_plane_setup_pixel_ext(psde, psde->pipe_cfg.src_rect.h,
828 psde->pipe_cfg.dst_rect.h, tmp,
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400829 pe->phase_step_y,
830 pe->roi_h,
831 pe->num_ext_pxls_top,
Clarence Ipe78efb72016-06-24 18:35:21 -0400832 pe->num_ext_pxls_btm, pe->vert_filter, fmt,
Clarence Ip5e2a9222016-06-26 22:38:24 -0400833 chroma_subsmpl_v, 1);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400834
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400835 for (i = 0; i < SDE_MAX_PLANES; i++) {
836 if (pe->num_ext_pxls_left[i] >= 0)
Clarence Ipb43d4592016-09-08 14:21:35 -0400837 pe->left_rpt[i] = pe->num_ext_pxls_left[i];
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400838 else
Clarence Ipb43d4592016-09-08 14:21:35 -0400839 pe->left_ftch[i] = pe->num_ext_pxls_left[i];
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400840
841 if (pe->num_ext_pxls_right[i] >= 0)
Clarence Ipb43d4592016-09-08 14:21:35 -0400842 pe->right_rpt[i] = pe->num_ext_pxls_right[i];
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400843 else
Clarence Ipb43d4592016-09-08 14:21:35 -0400844 pe->right_ftch[i] = pe->num_ext_pxls_right[i];
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400845
846 if (pe->num_ext_pxls_top[i] >= 0)
Clarence Ipb43d4592016-09-08 14:21:35 -0400847 pe->top_rpt[i] = pe->num_ext_pxls_top[i];
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400848 else
Clarence Ipb43d4592016-09-08 14:21:35 -0400849 pe->top_ftch[i] = pe->num_ext_pxls_top[i];
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400850
851 if (pe->num_ext_pxls_btm[i] >= 0)
Clarence Ipb43d4592016-09-08 14:21:35 -0400852 pe->btm_rpt[i] = pe->num_ext_pxls_btm[i];
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400853 else
Clarence Ipb43d4592016-09-08 14:21:35 -0400854 pe->btm_ftch[i] = pe->num_ext_pxls_btm[i];
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400855 }
856 }
Clarence Ipcb410d42016-06-26 22:52:33 -0400857}
858
Clarence Ipcae1bb62016-07-07 12:07:13 -0400859/**
860 * _sde_plane_color_fill - enables color fill on plane
Clarence Ip13a8cf42016-09-29 17:27:47 -0400861 * @psde: Pointer to SDE plane object
Clarence Ipcae1bb62016-07-07 12:07:13 -0400862 * @color: RGB fill color value, [23..16] Blue, [15..8] Green, [7..0] Red
863 * @alpha: 8-bit fill alpha value, 255 selects 100% alpha
864 * Returns: 0 on success
865 */
Clarence Ip13a8cf42016-09-29 17:27:47 -0400866static int _sde_plane_color_fill(struct sde_plane *psde,
Clarence Ipcb410d42016-06-26 22:52:33 -0400867 uint32_t color, uint32_t alpha)
868{
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400869 const struct sde_format *fmt;
Clarence Ipcb410d42016-06-26 22:52:33 -0400870
Clarence Ip13a8cf42016-09-29 17:27:47 -0400871 if (!psde) {
Dhaval Patel47302cf2016-08-18 15:04:28 -0700872 SDE_ERROR("invalid plane\n");
Clarence Ipcb410d42016-06-26 22:52:33 -0400873 return -EINVAL;
874 }
875
Clarence Ipcb410d42016-06-26 22:52:33 -0400876 if (!psde->pipe_hw) {
Clarence Ip13a8cf42016-09-29 17:27:47 -0400877 SDE_ERROR_PLANE(psde, "invalid plane h/w pointer\n");
Clarence Ipcb410d42016-06-26 22:52:33 -0400878 return -EINVAL;
879 }
880
Clarence Ip13a8cf42016-09-29 17:27:47 -0400881 SDE_DEBUG_PLANE(psde, "\n");
Clarence Ipcae1bb62016-07-07 12:07:13 -0400882
Clarence Ipcb410d42016-06-26 22:52:33 -0400883 /*
884 * select fill format to match user property expectation,
885 * h/w only supports RGB variants
886 */
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400887 fmt = sde_get_sde_format(DRM_FORMAT_ABGR8888);
Clarence Ipcb410d42016-06-26 22:52:33 -0400888
889 /* update sspp */
890 if (fmt && psde->pipe_hw->ops.setup_solidfill) {
891 psde->pipe_hw->ops.setup_solidfill(psde->pipe_hw,
892 (color & 0xFFFFFF) | ((alpha & 0xFF) << 24));
893
894 /* override scaler/decimation if solid fill */
895 psde->pipe_cfg.src_rect.x = 0;
896 psde->pipe_cfg.src_rect.y = 0;
897 psde->pipe_cfg.src_rect.w = psde->pipe_cfg.dst_rect.w;
898 psde->pipe_cfg.src_rect.h = psde->pipe_cfg.dst_rect.h;
899
900 _sde_plane_setup_scaler(psde, fmt, 0);
901
902 if (psde->pipe_hw->ops.setup_format)
903 psde->pipe_hw->ops.setup_format(psde->pipe_hw,
904 fmt, SDE_SSPP_SOLID_FILL);
905
906 if (psde->pipe_hw->ops.setup_rects)
907 psde->pipe_hw->ops.setup_rects(psde->pipe_hw,
908 &psde->pipe_cfg, &psde->pixel_ext);
909 }
910
911 return 0;
912}
913
914static int _sde_plane_mode_set(struct drm_plane *plane,
Dhaval Patel47302cf2016-08-18 15:04:28 -0700915 struct drm_plane_state *state)
Clarence Ipcb410d42016-06-26 22:52:33 -0400916{
Clarence Ip282dad62016-09-27 17:07:35 -0400917 uint32_t nplanes, src_flags, zpos, split_w;
Clarence Ipcb410d42016-06-26 22:52:33 -0400918 struct sde_plane *psde;
919 struct sde_plane_state *pstate;
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400920 const struct sde_format *fmt;
Dhaval Patel47302cf2016-08-18 15:04:28 -0700921 struct drm_crtc *crtc;
922 struct drm_framebuffer *fb;
923 struct sde_rect src, dst;
924 bool q16_data = true;
Clarence Ip282dad62016-09-27 17:07:35 -0400925 int idx;
Clarence Ipcb410d42016-06-26 22:52:33 -0400926
Clarence Ip13a8cf42016-09-29 17:27:47 -0400927 if (!plane) {
Clarence Ip282dad62016-09-27 17:07:35 -0400928 SDE_ERROR("invalid plane\n");
929 return -EINVAL;
930 } else if (!plane->state) {
931 SDE_ERROR("invalid plane state\n");
Clarence Ipcb410d42016-06-26 22:52:33 -0400932 return -EINVAL;
933 }
934
935 psde = to_sde_plane(plane);
936 pstate = to_sde_plane_state(plane->state);
Clarence Ipcb410d42016-06-26 22:52:33 -0400937
Dhaval Patel47302cf2016-08-18 15:04:28 -0700938 crtc = state->crtc;
939 fb = state->fb;
940 if (!crtc || !fb) {
Clarence Ip13a8cf42016-09-29 17:27:47 -0400941 SDE_ERROR_PLANE(psde, "invalid crtc %d or fb %d\n",
942 crtc != 0, fb != 0);
Dhaval Patel47302cf2016-08-18 15:04:28 -0700943 return -EINVAL;
944 }
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400945 fmt = to_sde_format(msm_framebuffer_format(fb));
Lloyd Atkinsonfa2489c2016-05-25 15:16:03 -0400946 nplanes = fmt->num_planes;
Clarence Ipcb410d42016-06-26 22:52:33 -0400947
Clarence Ip282dad62016-09-27 17:07:35 -0400948 /* determine what needs to be refreshed */
949 while ((idx = msm_property_pop_dirty(&psde->property_info)) >= 0) {
950 switch (idx) {
Clarence Ipb43d4592016-09-08 14:21:35 -0400951 case PLANE_PROP_SCALER_V1:
Clarence Ipdedbba92016-09-27 17:43:10 -0400952 case PLANE_PROP_H_DECIMATE:
953 case PLANE_PROP_V_DECIMATE:
954 case PLANE_PROP_SRC_CONFIG:
955 case PLANE_PROP_ZPOS:
Clarence Ip282dad62016-09-27 17:07:35 -0400956 pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
957 break;
Clarence Ip5fc00c52016-09-23 15:03:34 -0400958 case PLANE_PROP_CSC_V1:
Clarence Ip282dad62016-09-27 17:07:35 -0400959 pstate->dirty |= SDE_PLANE_DIRTY_FORMAT;
960 break;
961 case PLANE_PROP_COLOR_FILL:
962 /* potentially need to refresh everything */
963 pstate->dirty = SDE_PLANE_DIRTY_ALL;
964 break;
965 case PLANE_PROP_ROTATION:
966 pstate->dirty |= SDE_PLANE_DIRTY_FORMAT;
967 break;
Clarence Ip282dad62016-09-27 17:07:35 -0400968 case PLANE_PROP_INFO:
969 case PLANE_PROP_ALPHA:
970 case PLANE_PROP_INPUT_FENCE:
971 case PLANE_PROP_BLEND_OP:
972 /* no special action required */
973 break;
974 default:
975 /* unknown property, refresh everything */
976 pstate->dirty |= SDE_PLANE_DIRTY_ALL;
977 SDE_ERROR("executing full mode set, prp_idx %d\n", idx);
978 break;
979 }
Clarence Ipcb410d42016-06-26 22:52:33 -0400980 }
981
Clarence Ip282dad62016-09-27 17:07:35 -0400982 if (pstate->dirty & SDE_PLANE_DIRTY_RECTS)
983 memset(&(psde->pipe_cfg), 0, sizeof(struct sde_hw_pipe_cfg));
Clarence Ipcb410d42016-06-26 22:52:33 -0400984
985 _sde_plane_set_scanout(plane, pstate, &psde->pipe_cfg, fb);
986
Clarence Ip282dad62016-09-27 17:07:35 -0400987 /* early out if nothing dirty */
988 if (!pstate->dirty)
989 return 0;
990 pstate->pending = true;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400991
Clarence Ip282dad62016-09-27 17:07:35 -0400992 psde->is_rt_pipe = _sde_plane_is_rt_pipe(plane, crtc);
993 _sde_plane_set_qos_ctrl(plane, false, SDE_PLANE_QOS_PANIC_CTRL);
994
995 /* update roi config */
996 if (pstate->dirty & SDE_PLANE_DIRTY_RECTS) {
997 POPULATE_RECT(&src, state->src_x, state->src_y,
998 state->src_w, state->src_h, q16_data);
999 POPULATE_RECT(&dst, state->crtc_x, state->crtc_y,
1000 state->crtc_w, state->crtc_h, !q16_data);
1001
Clarence Ip13a8cf42016-09-29 17:27:47 -04001002 SDE_DEBUG_PLANE(psde,
1003 "FB[%u] %u,%u,%ux%u->crtc%u %d,%d,%ux%u, %s ubwc %d\n",
Clarence Ip282dad62016-09-27 17:07:35 -04001004 fb->base.id, src.x, src.y, src.w, src.h,
1005 crtc->base.id, dst.x, dst.y, dst.w, dst.h,
1006 drm_get_format_name(fmt->base.pixel_format),
1007 SDE_FORMAT_IS_UBWC(fmt));
1008
1009 if (sde_plane_get_property(pstate, PLANE_PROP_SRC_CONFIG) &
1010 BIT(SDE_DRM_DEINTERLACE)) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001011 SDE_DEBUG_PLANE(psde, "deinterlace\n");
Clarence Ip282dad62016-09-27 17:07:35 -04001012 for (idx = 0; idx < SDE_MAX_PLANES; ++idx)
1013 psde->pipe_cfg.layout.plane_pitch[idx] <<= 1;
1014 src.h /= 2;
1015 src.y = DIV_ROUND_UP(src.y, 2);
1016 src.y &= ~0x1;
1017 }
1018
1019 psde->pipe_cfg.src_rect = src;
1020 psde->pipe_cfg.dst_rect = dst;
1021
1022 /* check for color fill */
1023 psde->color_fill = (uint32_t)sde_plane_get_property(pstate,
1024 PLANE_PROP_COLOR_FILL);
1025 if (psde->color_fill & SDE_PLANE_COLOR_FILL_FLAG) {
1026 /* skip remaining processing on color fill */
1027 pstate->dirty = 0x0;
1028 } else if (psde->pipe_hw->ops.setup_rects) {
1029 _sde_plane_setup_scaler(psde, fmt, pstate);
1030
1031 /* base layer source split needs update */
1032 zpos = sde_plane_get_property(pstate, PLANE_PROP_ZPOS);
1033 if (zpos == SDE_STAGE_BASE) {
1034 split_w = get_crtc_split_width(crtc);
1035 if (psde->pipe_cfg.dst_rect.x >= split_w)
1036 psde->pipe_cfg.dst_rect.x -= split_w;
1037 }
1038 psde->pipe_hw->ops.setup_rects(psde->pipe_hw,
1039 &psde->pipe_cfg, &psde->pixel_ext);
1040 }
Dhaval Patel48c76022016-09-01 17:51:23 -07001041 }
1042
Clarence Ip282dad62016-09-27 17:07:35 -04001043 if ((pstate->dirty & SDE_PLANE_DIRTY_FORMAT) &&
1044 psde->pipe_hw->ops.setup_format) {
1045 src_flags = 0x0;
Clarence Ip13a8cf42016-09-29 17:27:47 -04001046 SDE_DEBUG_PLANE(psde, "rotation 0x%llX\n",
Clarence Ip282dad62016-09-27 17:07:35 -04001047 sde_plane_get_property(pstate, PLANE_PROP_ROTATION));
1048 if (sde_plane_get_property(pstate, PLANE_PROP_ROTATION) &
1049 BIT(DRM_REFLECT_X))
1050 src_flags |= SDE_SSPP_FLIP_LR;
1051 if (sde_plane_get_property(pstate, PLANE_PROP_ROTATION) &
1052 BIT(DRM_REFLECT_Y))
1053 src_flags |= SDE_SSPP_FLIP_UD;
1054
1055 /* update format */
1056 psde->pipe_hw->ops.setup_format(psde->pipe_hw, fmt, src_flags);
1057
1058 /* update csc */
1059 if (SDE_FORMAT_IS_YUV(fmt))
Clarence Ip5fc00c52016-09-23 15:03:34 -04001060 _sde_plane_setup_csc(psde);
Clarence Ip282dad62016-09-27 17:07:35 -04001061 else
1062 psde->csc_ptr = 0;
1063 }
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001064
Clarence Ipe78efb72016-06-24 18:35:21 -04001065 /* update sharpening */
Clarence Ip282dad62016-09-27 17:07:35 -04001066 if ((pstate->dirty & SDE_PLANE_DIRTY_SHARPEN) &&
1067 psde->pipe_hw->ops.setup_sharpening) {
1068 psde->sharp_cfg.strength = SHARP_STRENGTH_DEFAULT;
1069 psde->sharp_cfg.edge_thr = SHARP_EDGE_THR_DEFAULT;
1070 psde->sharp_cfg.smooth_thr = SHARP_SMOOTH_THR_DEFAULT;
1071 psde->sharp_cfg.noise_thr = SHARP_NOISE_THR_DEFAULT;
Clarence Ipe78efb72016-06-24 18:35:21 -04001072
Clarence Ipe78efb72016-06-24 18:35:21 -04001073 psde->pipe_hw->ops.setup_sharpening(psde->pipe_hw,
Clarence Ip282dad62016-09-27 17:07:35 -04001074 &psde->sharp_cfg);
1075 }
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001076
Alan Kwong1a00e4d2016-07-18 09:42:30 -04001077 _sde_plane_set_qos_lut(plane, fb);
1078 _sde_plane_set_danger_lut(plane, fb);
1079
Alan Kwong5d324e42016-07-28 22:56:18 -04001080 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
Alan Kwong1a00e4d2016-07-18 09:42:30 -04001081 _sde_plane_set_qos_ctrl(plane, true, SDE_PLANE_QOS_PANIC_CTRL);
Alan Kwong5d324e42016-07-28 22:56:18 -04001082 _sde_plane_set_ot_limit(plane, crtc);
1083 }
Alan Kwong1a00e4d2016-07-18 09:42:30 -04001084
Clarence Ip282dad62016-09-27 17:07:35 -04001085 /* clear dirty */
1086 pstate->dirty = 0x0;
1087
Clarence Ip5e2a9222016-06-26 22:38:24 -04001088 return 0;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001089}
1090
1091static int sde_plane_prepare_fb(struct drm_plane *plane,
1092 const struct drm_plane_state *new_state)
1093{
1094 struct drm_framebuffer *fb = new_state->fb;
1095 struct sde_plane *psde = to_sde_plane(plane);
1096
1097 if (!new_state->fb)
1098 return 0;
1099
Clarence Ip13a8cf42016-09-29 17:27:47 -04001100 SDE_DEBUG_PLANE(psde, "FB[%u]\n", fb->base.id);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001101 return msm_framebuffer_prepare(fb, psde->mmu_id);
1102}
1103
1104static void sde_plane_cleanup_fb(struct drm_plane *plane,
1105 const struct drm_plane_state *old_state)
1106{
Clarence Ip13a8cf42016-09-29 17:27:47 -04001107 struct drm_framebuffer *fb = old_state ? old_state->fb : NULL;
1108 struct sde_plane *psde = plane ? to_sde_plane(plane) : NULL;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001109
1110 if (!fb)
1111 return;
1112
Clarence Ip13a8cf42016-09-29 17:27:47 -04001113 SDE_DEBUG_PLANE(psde, "FB[%u]\n", fb->base.id);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001114 msm_framebuffer_cleanup(fb, psde->mmu_id);
1115}
1116
Lloyd Atkinsonfa2489c2016-05-25 15:16:03 -04001117static void _sde_plane_atomic_check_mode_changed(struct sde_plane *psde,
1118 struct drm_plane_state *state,
1119 struct drm_plane_state *old_state)
1120{
1121 struct sde_plane_state *pstate = to_sde_plane_state(state);
1122
Dhaval Patel47302cf2016-08-18 15:04:28 -07001123 /* no need to check it again */
Clarence Ip282dad62016-09-27 17:07:35 -04001124 if (pstate->dirty == SDE_PLANE_DIRTY_ALL)
Dhaval Patel47302cf2016-08-18 15:04:28 -07001125 return;
1126
Clarence Ip282dad62016-09-27 17:07:35 -04001127 if (!sde_plane_enabled(state) || !sde_plane_enabled(old_state)
1128 || psde->is_error) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001129 SDE_DEBUG_PLANE(psde,
1130 "enabling/disabling full modeset required\n");
Clarence Ip282dad62016-09-27 17:07:35 -04001131 pstate->dirty |= SDE_PLANE_DIRTY_ALL;
Lloyd Atkinsonfa2489c2016-05-25 15:16:03 -04001132 } else if (to_sde_plane_state(old_state)->pending) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001133 SDE_DEBUG_PLANE(psde, "still pending\n");
Clarence Ip282dad62016-09-27 17:07:35 -04001134 pstate->dirty |= SDE_PLANE_DIRTY_ALL;
Lloyd Atkinsonfa2489c2016-05-25 15:16:03 -04001135 } else if (state->src_w != old_state->src_w ||
Dhaval Patel47302cf2016-08-18 15:04:28 -07001136 state->src_h != old_state->src_h ||
1137 state->src_x != old_state->src_x ||
1138 state->src_y != old_state->src_y) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001139 SDE_DEBUG_PLANE(psde, "src rect updated\n");
Clarence Ip282dad62016-09-27 17:07:35 -04001140 pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
Dhaval Patel47302cf2016-08-18 15:04:28 -07001141 } else if (state->crtc_w != old_state->crtc_w ||
1142 state->crtc_h != old_state->crtc_h ||
1143 state->crtc_x != old_state->crtc_x ||
1144 state->crtc_y != old_state->crtc_y) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001145 SDE_DEBUG_PLANE(psde, "crtc rect updated\n");
Clarence Ip282dad62016-09-27 17:07:35 -04001146 pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
1147 }
1148
1149 if (!state->fb || !old_state->fb) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001150 SDE_DEBUG_PLANE(psde, "can't compare fb handles\n");
Lloyd Atkinsonfa2489c2016-05-25 15:16:03 -04001151 } else if (state->fb->pixel_format != old_state->fb->pixel_format) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001152 SDE_DEBUG_PLANE(psde, "format change\n");
Clarence Ip282dad62016-09-27 17:07:35 -04001153 pstate->dirty |= SDE_PLANE_DIRTY_FORMAT | SDE_PLANE_DIRTY_RECTS;
Dhaval Patel47302cf2016-08-18 15:04:28 -07001154 } else {
Lloyd Atkinsonfa2489c2016-05-25 15:16:03 -04001155 uint64_t *new_mods = state->fb->modifier;
1156 uint64_t *old_mods = old_state->fb->modifier;
Dhaval Patel47302cf2016-08-18 15:04:28 -07001157 uint32_t *new_pitches = state->fb->pitches;
1158 uint32_t *old_pitches = old_state->fb->pitches;
1159 uint32_t *new_offset = state->fb->offsets;
1160 uint32_t *old_offset = old_state->fb->offsets;
Lloyd Atkinsonfa2489c2016-05-25 15:16:03 -04001161 int i;
1162
1163 for (i = 0; i < ARRAY_SIZE(state->fb->modifier); i++) {
1164 if (new_mods[i] != old_mods[i]) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001165 SDE_DEBUG_PLANE(psde,
1166 "format modifiers change\"\
Dhaval Patel47302cf2016-08-18 15:04:28 -07001167 plane:%d new_mode:%llu old_mode:%llu\n",
Clarence Ip13a8cf42016-09-29 17:27:47 -04001168 i, new_mods[i], old_mods[i]);
Clarence Ip282dad62016-09-27 17:07:35 -04001169 pstate->dirty |= SDE_PLANE_DIRTY_FORMAT |
1170 SDE_PLANE_DIRTY_RECTS;
Lloyd Atkinsonfa2489c2016-05-25 15:16:03 -04001171 break;
1172 }
1173 }
Lloyd Atkinson3ab9ef72016-07-14 17:42:41 -04001174 for (i = 0; i < ARRAY_SIZE(state->fb->pitches); i++) {
1175 if (new_pitches[i] != old_pitches[i]) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001176 SDE_DEBUG_PLANE(psde,
1177 "pitches change plane:%d\"\
Dhaval Patel47302cf2016-08-18 15:04:28 -07001178 old_pitches:%u new_pitches:%u\n",
Clarence Ip13a8cf42016-09-29 17:27:47 -04001179 i, old_pitches[i], new_pitches[i]);
Clarence Ip282dad62016-09-27 17:07:35 -04001180 pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
Lloyd Atkinson3ab9ef72016-07-14 17:42:41 -04001181 break;
1182 }
1183 }
Dhaval Patel47302cf2016-08-18 15:04:28 -07001184 for (i = 0; i < ARRAY_SIZE(state->fb->offsets); i++) {
1185 if (new_offset[i] != old_offset[i]) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001186 SDE_DEBUG_PLANE(psde,
1187 "offset change plane:%d\"\
Dhaval Patel47302cf2016-08-18 15:04:28 -07001188 old_offset:%u new_offset:%u\n",
Clarence Ip13a8cf42016-09-29 17:27:47 -04001189 i, old_offset[i], new_offset[i]);
Clarence Ip282dad62016-09-27 17:07:35 -04001190 pstate->dirty |= SDE_PLANE_DIRTY_FORMAT |
1191 SDE_PLANE_DIRTY_RECTS;
Dhaval Patel47302cf2016-08-18 15:04:28 -07001192 break;
1193 }
1194 }
Lloyd Atkinson3ab9ef72016-07-14 17:42:41 -04001195 }
Lloyd Atkinsonfa2489c2016-05-25 15:16:03 -04001196}
1197
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001198static int sde_plane_atomic_check(struct drm_plane *plane,
1199 struct drm_plane_state *state)
1200{
Clarence Ipdedbba92016-09-27 17:43:10 -04001201 int ret = 0;
Clarence Ipdbde9832016-06-26 09:48:36 -04001202 struct sde_plane *psde;
1203 struct sde_plane_state *pstate;
Lloyd Atkinson9a673492016-07-05 11:41:57 -04001204 const struct sde_format *fmt;
Dhaval Patel47302cf2016-08-18 15:04:28 -07001205 struct sde_rect src, dst;
Clarence Ipdbde9832016-06-26 09:48:36 -04001206 uint32_t deci_w, deci_h, src_deci_w, src_deci_h;
Dhaval Patel47302cf2016-08-18 15:04:28 -07001207 uint32_t max_upscale, max_downscale, min_src_size, max_linewidth;
1208 bool q16_data = true;
Clarence Ipdbde9832016-06-26 09:48:36 -04001209
1210 if (!plane || !state) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001211 SDE_ERROR("invalid arg(s), plane %d state %d\n",
1212 plane != 0, state != 0);
Clarence Ipdbde9832016-06-26 09:48:36 -04001213 ret = -EINVAL;
1214 goto exit;
1215 }
1216
1217 psde = to_sde_plane(plane);
1218 pstate = to_sde_plane_state(state);
Clarence Ipdbde9832016-06-26 09:48:36 -04001219
1220 if (!psde->pipe_sblk) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001221 SDE_ERROR_PLANE(psde, "invalid catalog\n");
Clarence Ipdbde9832016-06-26 09:48:36 -04001222 ret = -EINVAL;
1223 goto exit;
1224 }
1225
Clarence Ipdedbba92016-09-27 17:43:10 -04001226 deci_w = sde_plane_get_property(pstate, PLANE_PROP_H_DECIMATE);
1227 deci_h = sde_plane_get_property(pstate, PLANE_PROP_V_DECIMATE);
Clarence Ipdbde9832016-06-26 09:48:36 -04001228
1229 /* src values are in Q16 fixed point, convert to integer */
Dhaval Patel47302cf2016-08-18 15:04:28 -07001230 POPULATE_RECT(&src, state->src_x, state->src_y, state->src_w,
1231 state->src_h, q16_data);
1232 POPULATE_RECT(&dst, state->crtc_x, state->crtc_y, state->crtc_w,
1233 state->crtc_h, !q16_data);
Clarence Ipdbde9832016-06-26 09:48:36 -04001234
Dhaval Patel47302cf2016-08-18 15:04:28 -07001235 src_deci_w = DECIMATED_DIMENSION(src.w, deci_w);
1236 src_deci_h = DECIMATED_DIMENSION(src.h, deci_h);
Clarence Ipdbde9832016-06-26 09:48:36 -04001237
Dhaval Patel47302cf2016-08-18 15:04:28 -07001238 max_upscale = psde->pipe_sblk->maxupscale;
1239 max_downscale = psde->pipe_sblk->maxdwnscale;
1240 max_linewidth = psde->pipe_sblk->maxlinewidth;
Clarence Ipdbde9832016-06-26 09:48:36 -04001241
Clarence Ip13a8cf42016-09-29 17:27:47 -04001242 SDE_DEBUG_PLANE(psde, "check %d -> %d\n",
Dhaval Patel47302cf2016-08-18 15:04:28 -07001243 sde_plane_enabled(plane->state), sde_plane_enabled(state));
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001244
Dhaval Patel47302cf2016-08-18 15:04:28 -07001245 if (!sde_plane_enabled(state))
1246 goto modeset_update;
Clarence Ipdbde9832016-06-26 09:48:36 -04001247
Dhaval Patel47302cf2016-08-18 15:04:28 -07001248 fmt = to_sde_format(msm_framebuffer_format(state->fb));
1249
1250 min_src_size = SDE_FORMAT_IS_YUV(fmt) ? 2 : 1;
1251
1252 if (SDE_FORMAT_IS_YUV(fmt) &&
1253 (!(psde->features & SDE_SSPP_SCALER) ||
1254 !(psde->features & BIT(SDE_SSPP_CSC)))) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001255 SDE_ERROR_PLANE(psde,
1256 "plane doesn't have scaler/csc for yuv\n");
Dhaval Patel47302cf2016-08-18 15:04:28 -07001257 ret = -EINVAL;
1258
1259 /* check src bounds */
1260 } else if (state->fb->width > MAX_IMG_WIDTH ||
1261 state->fb->height > MAX_IMG_HEIGHT ||
1262 src.w < min_src_size || src.h < min_src_size ||
1263 CHECK_LAYER_BOUNDS(src.x, src.w, state->fb->width) ||
1264 CHECK_LAYER_BOUNDS(src.y, src.h, state->fb->height)) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001265 SDE_ERROR_PLANE(psde, "invalid source %u, %u, %ux%u\n",
Dhaval Patel47302cf2016-08-18 15:04:28 -07001266 src.x, src.y, src.w, src.h);
1267 ret = -E2BIG;
1268
1269 /* valid yuv image */
1270 } else if (SDE_FORMAT_IS_YUV(fmt) && ((src.x & 0x1) || (src.y & 0x1) ||
1271 (src.w & 0x1) || (src.h & 0x1))) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001272 SDE_ERROR_PLANE(psde, "invalid yuv source %u, %u, %ux%u\n",
Dhaval Patel47302cf2016-08-18 15:04:28 -07001273 src.x, src.y, src.w, src.h);
1274 ret = -EINVAL;
1275
1276 /* min dst support */
1277 } else if (dst.w < 0x1 || dst.h < 0x1) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001278 SDE_ERROR_PLANE(psde, "invalid dest rect %u, %u, %ux%u\n",
Dhaval Patel47302cf2016-08-18 15:04:28 -07001279 dst.x, dst.y, dst.w, dst.h);
1280 ret = -EINVAL;
1281
1282 /* decimation validation */
1283 } else if (deci_w || deci_h) {
1284 if ((deci_w > psde->pipe_sblk->maxhdeciexp) ||
1285 (deci_h > psde->pipe_sblk->maxvdeciexp)) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001286 SDE_ERROR_PLANE(psde,
1287 "too much decimation requested\n");
Clarence Ipdbde9832016-06-26 09:48:36 -04001288 ret = -EINVAL;
Dhaval Patel47302cf2016-08-18 15:04:28 -07001289 } else if (fmt->fetch_mode != SDE_FETCH_LINEAR) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001290 SDE_ERROR_PLANE(psde,
1291 "decimation requires linear fetch\n");
Clarence Ipdbde9832016-06-26 09:48:36 -04001292 ret = -EINVAL;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001293 }
1294
Dhaval Patel47302cf2016-08-18 15:04:28 -07001295 } else if (!(psde->features & SDE_SSPP_SCALER) &&
1296 ((src.w != dst.w) || (src.h != dst.h))) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001297 SDE_ERROR_PLANE(psde,
1298 "pipe doesn't support scaling %ux%u->%ux%u\n",
Dhaval Patel47302cf2016-08-18 15:04:28 -07001299 src.w, src.h, dst.w, dst.h);
1300 ret = -EINVAL;
1301
1302 /* check decimated source width */
1303 } else if (src_deci_w > max_linewidth) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001304 SDE_ERROR_PLANE(psde,
1305 "invalid src w:%u, deci w:%u, line w:%u\n",
Dhaval Patel47302cf2016-08-18 15:04:28 -07001306 src.w, src_deci_w, max_linewidth);
1307 ret = -E2BIG;
1308
1309 /* check max scaler capability */
1310 } else if (((src_deci_w * max_upscale) < dst.w) ||
1311 ((src_deci_h * max_upscale) < dst.h) ||
1312 ((dst.w * max_downscale) < src_deci_w) ||
1313 ((dst.h * max_downscale) < src_deci_h)) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001314 SDE_ERROR_PLANE(psde,
1315 "too much scaling requested %ux%u->%ux%u\n",
Dhaval Patel47302cf2016-08-18 15:04:28 -07001316 src_deci_w, src_deci_h, dst.w, dst.h);
1317 ret = -E2BIG;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001318 }
1319
Dhaval Patel47302cf2016-08-18 15:04:28 -07001320modeset_update:
Lloyd Atkinsonfa2489c2016-05-25 15:16:03 -04001321 if (!ret)
Dhaval Patel47302cf2016-08-18 15:04:28 -07001322 _sde_plane_atomic_check_mode_changed(psde, state, plane->state);
Clarence Ipdbde9832016-06-26 09:48:36 -04001323exit:
1324 return ret;
1325}
1326
Clarence Ipcae1bb62016-07-07 12:07:13 -04001327/**
1328 * sde_plane_flush - final plane operations before commit flush
1329 * @plane: Pointer to drm plane structure
1330 */
1331void sde_plane_flush(struct drm_plane *plane)
Clarence Ipdbde9832016-06-26 09:48:36 -04001332{
Clarence Ipcae1bb62016-07-07 12:07:13 -04001333 struct sde_plane *psde;
1334
Clarence Ip13a8cf42016-09-29 17:27:47 -04001335 if (!plane) {
1336 SDE_ERROR("invalid plane\n");
Clarence Ipcae1bb62016-07-07 12:07:13 -04001337 return;
Clarence Ip13a8cf42016-09-29 17:27:47 -04001338 }
Clarence Ipcae1bb62016-07-07 12:07:13 -04001339
1340 psde = to_sde_plane(plane);
1341
1342 /*
1343 * These updates have to be done immediately before the plane flush
1344 * timing, and may not be moved to the atomic_update/mode_set functions.
1345 */
1346 if (psde->is_error)
1347 /* force white frame with 0% alpha pipe output on error */
Clarence Ip13a8cf42016-09-29 17:27:47 -04001348 _sde_plane_color_fill(psde, 0xFFFFFF, 0x0);
Clarence Ipcae1bb62016-07-07 12:07:13 -04001349 else if (psde->color_fill & SDE_PLANE_COLOR_FILL_FLAG)
1350 /* force 100% alpha */
Clarence Ip13a8cf42016-09-29 17:27:47 -04001351 _sde_plane_color_fill(psde, psde->color_fill, 0xFF);
Clarence Ipcae1bb62016-07-07 12:07:13 -04001352 else if (psde->pipe_hw && psde->csc_ptr && psde->pipe_hw->ops.setup_csc)
1353 psde->pipe_hw->ops.setup_csc(psde->pipe_hw, psde->csc_ptr);
1354
1355 /* flag h/w flush complete */
1356 if (plane->state)
Clarence Ipdbde9832016-06-26 09:48:36 -04001357 to_sde_plane_state(plane->state)->pending = false;
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001358}
1359
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001360static void sde_plane_atomic_update(struct drm_plane *plane,
Clarence Ipe78efb72016-06-24 18:35:21 -04001361 struct drm_plane_state *old_state)
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001362{
Clarence Ip13a8cf42016-09-29 17:27:47 -04001363 struct sde_plane *psde;
Clarence Ip5e2a9222016-06-26 22:38:24 -04001364 struct drm_plane_state *state;
1365 struct sde_plane_state *pstate;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001366
Clarence Ip13a8cf42016-09-29 17:27:47 -04001367 if (!plane) {
1368 SDE_ERROR("invalid plane\n");
1369 return;
1370 } else if (!plane->state) {
1371 SDE_ERROR("invalid plane state\n");
Clarence Ip5e2a9222016-06-26 22:38:24 -04001372 return;
1373 }
1374
Clarence Ip13a8cf42016-09-29 17:27:47 -04001375 psde = to_sde_plane(plane);
1376 psde->is_error = false;
Clarence Ip5e2a9222016-06-26 22:38:24 -04001377 state = plane->state;
1378 pstate = to_sde_plane_state(state);
1379
Clarence Ip13a8cf42016-09-29 17:27:47 -04001380 SDE_DEBUG_PLANE(psde, "\n");
Clarence Ipae4e60c2016-06-26 22:44:04 -04001381
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001382 if (!sde_plane_enabled(state)) {
Clarence Ip5e2a9222016-06-26 22:38:24 -04001383 pstate->pending = true;
Clarence Ip282dad62016-09-27 17:07:35 -04001384 } else {
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001385 int ret;
1386
Dhaval Patel47302cf2016-08-18 15:04:28 -07001387 ret = _sde_plane_mode_set(plane, state);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001388 /* atomic_check should have ensured that this doesn't fail */
1389 WARN_ON(ret < 0);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001390 }
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001391}
1392
Dhaval Patel47302cf2016-08-18 15:04:28 -07001393
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001394/* helper to install properties which are common to planes and crtcs */
Dhaval Patel47302cf2016-08-18 15:04:28 -07001395static void _sde_plane_install_properties(struct drm_plane *plane,
1396 u32 max_blendstages)
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001397{
Clarence Ip5e2a9222016-06-26 22:38:24 -04001398 static const struct drm_prop_enum_list e_blend_op[] = {
1399 {SDE_DRM_BLEND_OP_NOT_DEFINED, "not_defined"},
1400 {SDE_DRM_BLEND_OP_OPAQUE, "opaque"},
1401 {SDE_DRM_BLEND_OP_PREMULTIPLIED, "premultiplied"},
1402 {SDE_DRM_BLEND_OP_COVERAGE, "coverage"}
1403 };
1404 static const struct drm_prop_enum_list e_src_config[] = {
1405 {SDE_DRM_DEINTERLACE, "deinterlace"}
1406 };
Clarence Ipea3d6262016-07-15 16:20:11 -04001407 const struct sde_format_extended *format_list;
Dhaval Patel4e574842016-08-23 15:11:37 -07001408 struct sde_kms_info *info;
Clarence Ip5e2a9222016-06-26 22:38:24 -04001409 struct sde_plane *psde = to_sde_plane(plane);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001410
Clarence Ip13a8cf42016-09-29 17:27:47 -04001411 if (!plane || !psde) {
1412 SDE_ERROR("invalid plane\n");
1413 return;
1414 } else if (!psde->pipe_hw || !psde->pipe_sblk) {
1415 SDE_ERROR("invalid plane, pipe_hw %d pipe_sblk %d\n",
1416 psde->pipe_hw != 0, psde->pipe_sblk != 0);
Clarence Ip5e2a9222016-06-26 22:38:24 -04001417 return;
1418 }
1419
Dhaval Patel47302cf2016-08-18 15:04:28 -07001420 msm_property_install_range(&psde->property_info, "zpos", 0x0, 0,
Dhaval Patel48c76022016-09-01 17:51:23 -07001421 max_blendstages, SDE_STAGE_BASE, PLANE_PROP_ZPOS);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001422
Lloyd Atkinson38ad8c92016-07-06 10:39:32 -04001423 msm_property_install_range(&psde->property_info, "alpha",
Dhaval Patel47302cf2016-08-18 15:04:28 -07001424 0x0, 0, 255, 255, PLANE_PROP_ALPHA);
Clarence Ip5e2a9222016-06-26 22:38:24 -04001425
Dhaval Patel47302cf2016-08-18 15:04:28 -07001426 /* linux default file descriptor range on each process */
Clarence Ipcae1bb62016-07-07 12:07:13 -04001427 msm_property_install_range(&psde->property_info, "input_fence",
Dhaval Patel4e574842016-08-23 15:11:37 -07001428 0x0, 0, INR_OPEN_MAX, 0, PLANE_PROP_INPUT_FENCE);
Clarence Ip5e2a9222016-06-26 22:38:24 -04001429
Clarence Ipdedbba92016-09-27 17:43:10 -04001430 if (psde->pipe_sblk->maxhdeciexp) {
1431 msm_property_install_range(&psde->property_info, "h_decimate",
1432 0x0, 0, psde->pipe_sblk->maxhdeciexp, 0,
1433 PLANE_PROP_H_DECIMATE);
1434 }
1435
1436 if (psde->pipe_sblk->maxvdeciexp) {
1437 msm_property_install_range(&psde->property_info, "v_decimate",
1438 0x0, 0, psde->pipe_sblk->maxvdeciexp, 0,
1439 PLANE_PROP_V_DECIMATE);
1440 }
1441
Clarence Ipb43d4592016-09-08 14:21:35 -04001442 if (psde->features & SDE_SSPP_SCALER) {
1443 msm_property_install_volatile_range(&psde->property_info,
1444 "scaler_v1", 0x0, 0, ~0, 0, PLANE_PROP_SCALER_V1);
1445 }
1446
Clarence Ip5fc00c52016-09-23 15:03:34 -04001447 if (psde->features & BIT(SDE_SSPP_CSC)) {
1448 msm_property_install_volatile_range(&psde->property_info,
1449 "csc_v1", 0x0, 0, ~0, 0, PLANE_PROP_CSC_V1);
1450 }
1451
Clarence Ip5e2a9222016-06-26 22:38:24 -04001452 /* standard properties */
Clarence Ipaa0faf42016-05-30 12:07:48 -04001453 msm_property_install_rotation(&psde->property_info,
Dhaval Patel47302cf2016-08-18 15:04:28 -07001454 BIT(DRM_REFLECT_X) | BIT(DRM_REFLECT_Y), PLANE_PROP_ROTATION);
Clarence Ip5e2a9222016-06-26 22:38:24 -04001455
Lloyd Atkinson38ad8c92016-07-06 10:39:32 -04001456 msm_property_install_enum(&psde->property_info, "blend_op", 0x0, 0,
Dhaval Patel47302cf2016-08-18 15:04:28 -07001457 e_blend_op, ARRAY_SIZE(e_blend_op), PLANE_PROP_BLEND_OP);
Clarence Ip5e2a9222016-06-26 22:38:24 -04001458
Dhaval Patel47302cf2016-08-18 15:04:28 -07001459 msm_property_install_enum(&psde->property_info, "src_config", 0x0, 1,
1460 e_src_config, ARRAY_SIZE(e_src_config), PLANE_PROP_SRC_CONFIG);
1461
1462 if (psde->pipe_hw->ops.setup_solidfill)
1463 msm_property_install_range(&psde->property_info, "color_fill",
1464 0, 0, 0xFFFFFFFF, 0, PLANE_PROP_COLOR_FILL);
1465
Dhaval Patel4e574842016-08-23 15:11:37 -07001466 info = kzalloc(sizeof(struct sde_kms_info), GFP_KERNEL);
Clarence Ip13a8cf42016-09-29 17:27:47 -04001467 if (!info) {
1468 SDE_ERROR("failed to allocate info memory\n");
Dhaval Patel4e574842016-08-23 15:11:37 -07001469 return;
Clarence Ip13a8cf42016-09-29 17:27:47 -04001470 }
Dhaval Patel4e574842016-08-23 15:11:37 -07001471
1472 msm_property_install_blob(&psde->property_info, "capabilities",
1473 DRM_MODE_PROP_IMMUTABLE, PLANE_PROP_INFO);
1474 sde_kms_info_reset(info);
1475
Clarence Ipea3d6262016-07-15 16:20:11 -04001476 format_list = psde->pipe_sblk->format_list;
1477 if (format_list) {
Clarence Ipea3d6262016-07-15 16:20:11 -04001478 sde_kms_info_start(info, "pixel_formats");
1479 while (format_list->fourcc_format) {
1480 sde_kms_info_append_format(info,
1481 format_list->fourcc_format,
1482 format_list->modifier);
1483 ++format_list;
1484 }
1485 sde_kms_info_stop(info);
Clarence Ipea3d6262016-07-15 16:20:11 -04001486 }
Dhaval Patel4e574842016-08-23 15:11:37 -07001487
1488 sde_kms_info_add_keyint(info, "max_linewidth",
1489 psde->pipe_sblk->maxlinewidth);
1490 sde_kms_info_add_keyint(info, "max_upscale",
1491 psde->pipe_sblk->maxupscale);
1492 sde_kms_info_add_keyint(info, "max_downscale",
1493 psde->pipe_sblk->maxdwnscale);
1494 sde_kms_info_add_keyint(info, "max_horizontal_deci",
1495 psde->pipe_sblk->maxhdeciexp);
1496 sde_kms_info_add_keyint(info, "max_vertical_deci",
1497 psde->pipe_sblk->maxvdeciexp);
1498 msm_property_set_blob(&psde->property_info, &psde->blob_info,
1499 info->data, info->len, PLANE_PROP_INFO);
1500
1501 kfree(info);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001502}
1503
Clarence Ip5fc00c52016-09-23 15:03:34 -04001504static inline void _sde_plane_set_csc_v1(struct sde_plane *psde, void *usr_ptr)
1505{
1506 struct sde_drm_csc_v1 csc_v1;
1507 int i;
1508
1509 if (!psde) {
1510 SDE_ERROR("invalid plane\n");
1511 return;
1512 }
1513
1514 psde->csc_usr_ptr = NULL;
1515 if (!usr_ptr) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001516 SDE_DEBUG_PLANE(psde, "csc data removed\n");
Clarence Ip5fc00c52016-09-23 15:03:34 -04001517 return;
1518 }
1519
1520 if (copy_from_user(&csc_v1, usr_ptr, sizeof(csc_v1))) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001521 SDE_ERROR_PLANE(psde, "failed to copy csc data\n");
Clarence Ip5fc00c52016-09-23 15:03:34 -04001522 return;
1523 }
1524
Clarence Ipb43d4592016-09-08 14:21:35 -04001525 /* populate from user space */
Clarence Ip5fc00c52016-09-23 15:03:34 -04001526 for (i = 0; i < SDE_CSC_MATRIX_COEFF_SIZE; ++i)
1527 psde->csc_cfg.csc_mv[i] = csc_v1.ctm_coeff[i] >> 16;
1528 for (i = 0; i < SDE_CSC_BIAS_SIZE; ++i) {
1529 psde->csc_cfg.csc_pre_bv[i] = csc_v1.pre_bias[i];
1530 psde->csc_cfg.csc_post_bv[i] = csc_v1.post_bias[i];
1531 }
1532 for (i = 0; i < SDE_CSC_CLAMP_SIZE; ++i) {
1533 psde->csc_cfg.csc_pre_lv[i] = csc_v1.pre_clamp[i];
1534 psde->csc_cfg.csc_post_lv[i] = csc_v1.post_clamp[i];
1535 }
1536 psde->csc_usr_ptr = &psde->csc_cfg;
1537}
1538
Clarence Ipb43d4592016-09-08 14:21:35 -04001539static inline void _sde_plane_set_scaler_v1(struct sde_plane *psde, void *usr)
1540{
1541 struct sde_drm_scaler_v1 scale_v1;
1542 struct sde_hw_pixel_ext *pe;
1543 int i;
1544
1545 if (!psde) {
1546 SDE_ERROR("invalid plane\n");
1547 return;
1548 }
1549
1550 psde->pixel_ext_usr = false;
1551 if (!usr) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001552 SDE_DEBUG_PLANE(psde, "scale data removed\n");
Clarence Ipb43d4592016-09-08 14:21:35 -04001553 return;
1554 }
1555
1556 if (copy_from_user(&scale_v1, usr, sizeof(scale_v1))) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001557 SDE_ERROR_PLANE(psde, "failed to copy scale data\n");
Clarence Ipb43d4592016-09-08 14:21:35 -04001558 return;
1559 }
1560
1561 /* populate from user space */
1562 pe = &(psde->pixel_ext);
1563 memset(pe, 0, sizeof(struct sde_hw_pixel_ext));
1564 for (i = 0; i < SDE_MAX_PLANES; i++) {
1565 pe->init_phase_x[i] = scale_v1.init_phase_x[i];
1566 pe->phase_step_x[i] = scale_v1.phase_step_x[i];
1567 pe->init_phase_y[i] = scale_v1.init_phase_y[i];
1568 pe->phase_step_y[i] = scale_v1.phase_step_y[i];
1569
1570 pe->horz_filter[i] = scale_v1.horz_filter[i];
1571 pe->vert_filter[i] = scale_v1.vert_filter[i];
1572 }
1573 for (i = 0; i < SDE_MAX_PLANES; i++) {
1574 pe->num_ext_pxls_left[i] = scale_v1.lr.num_pxls_start[i];
1575 pe->num_ext_pxls_right[i] = scale_v1.lr.num_pxls_end[i];
1576 pe->left_ftch[i] = scale_v1.lr.ftch_start[i];
1577 pe->right_ftch[i] = scale_v1.lr.ftch_end[i];
1578 pe->left_rpt[i] = scale_v1.lr.rpt_start[i];
1579 pe->right_rpt[i] = scale_v1.lr.rpt_end[i];
1580 pe->roi_w[i] = scale_v1.lr.roi[i];
1581
1582 pe->num_ext_pxls_top[i] = scale_v1.tb.num_pxls_start[i];
1583 pe->num_ext_pxls_btm[i] = scale_v1.tb.num_pxls_end[i];
1584 pe->top_ftch[i] = scale_v1.tb.ftch_start[i];
1585 pe->btm_ftch[i] = scale_v1.tb.ftch_end[i];
1586 pe->top_rpt[i] = scale_v1.tb.rpt_start[i];
1587 pe->btm_rpt[i] = scale_v1.tb.rpt_end[i];
1588 pe->roi_h[i] = scale_v1.tb.roi[i];
1589 }
1590 psde->pixel_ext_usr = true;
1591
Clarence Ip13a8cf42016-09-29 17:27:47 -04001592 SDE_DEBUG_PLANE(psde, "user property data copied\n");
Clarence Ipb43d4592016-09-08 14:21:35 -04001593}
1594
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001595static int sde_plane_atomic_set_property(struct drm_plane *plane,
1596 struct drm_plane_state *state, struct drm_property *property,
1597 uint64_t val)
1598{
Clarence Ip13a8cf42016-09-29 17:27:47 -04001599 struct sde_plane *psde = plane ? to_sde_plane(plane) : NULL;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001600 struct sde_plane_state *pstate;
Clarence Ipe78efb72016-06-24 18:35:21 -04001601 int idx, ret = -EINVAL;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001602
Clarence Ip13a8cf42016-09-29 17:27:47 -04001603 SDE_DEBUG_PLANE(psde, "\n");
Clarence Ipaa0faf42016-05-30 12:07:48 -04001604
1605 if (!plane) {
Dhaval Patel47302cf2016-08-18 15:04:28 -07001606 SDE_ERROR("invalid plane\n");
Clarence Ipaa0faf42016-05-30 12:07:48 -04001607 } else if (!state) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001608 SDE_ERROR_PLANE(psde, "invalid state\n");
Clarence Ip730e7192016-06-26 22:45:09 -04001609 } else {
Clarence Ip4c1d9772016-06-26 09:35:38 -04001610 pstate = to_sde_plane_state(state);
Clarence Ipaa0faf42016-05-30 12:07:48 -04001611 ret = msm_property_atomic_set(&psde->property_info,
1612 pstate->property_values, pstate->property_blobs,
1613 property, val);
1614 if (!ret) {
1615 idx = msm_property_index(&psde->property_info,
1616 property);
Clarence Ip5fc00c52016-09-23 15:03:34 -04001617 switch (idx) {
1618 case PLANE_PROP_INPUT_FENCE:
Clarence Ip13a8cf42016-09-29 17:27:47 -04001619 _sde_plane_set_input_fence(psde, pstate, val);
Clarence Ip5fc00c52016-09-23 15:03:34 -04001620 break;
1621 case PLANE_PROP_CSC_V1:
1622 _sde_plane_set_csc_v1(psde, (void *)val);
1623 break;
Clarence Ipb43d4592016-09-08 14:21:35 -04001624 case PLANE_PROP_SCALER_V1:
1625 _sde_plane_set_scaler_v1(psde, (void *)val);
1626 break;
Clarence Ip5fc00c52016-09-23 15:03:34 -04001627 default:
1628 /* nothing to do */
1629 break;
1630 }
Clarence Ipe78efb72016-06-24 18:35:21 -04001631 }
1632 }
1633
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001634 return ret;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001635}
1636
1637static int sde_plane_set_property(struct drm_plane *plane,
1638 struct drm_property *property, uint64_t val)
1639{
Clarence Ip13a8cf42016-09-29 17:27:47 -04001640 SDE_DEBUG("\n");
Clarence Ip4c1d9772016-06-26 09:35:38 -04001641
Clarence Ipae4e60c2016-06-26 22:44:04 -04001642 return sde_plane_atomic_set_property(plane,
1643 plane->state, property, val);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001644}
1645
1646static int sde_plane_atomic_get_property(struct drm_plane *plane,
1647 const struct drm_plane_state *state,
1648 struct drm_property *property, uint64_t *val)
1649{
Clarence Ip13a8cf42016-09-29 17:27:47 -04001650 struct sde_plane *psde = plane ? to_sde_plane(plane) : NULL;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001651 struct sde_plane_state *pstate;
Clarence Ipaa0faf42016-05-30 12:07:48 -04001652 int ret = -EINVAL;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001653
Clarence Ipaa0faf42016-05-30 12:07:48 -04001654 if (!plane) {
Dhaval Patel47302cf2016-08-18 15:04:28 -07001655 SDE_ERROR("invalid plane\n");
Clarence Ipaa0faf42016-05-30 12:07:48 -04001656 } else if (!state) {
Dhaval Patel47302cf2016-08-18 15:04:28 -07001657 SDE_ERROR("invalid state\n");
Clarence Ipaa0faf42016-05-30 12:07:48 -04001658 } else {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001659 SDE_DEBUG_PLANE(psde, "\n");
Clarence Ip4c1d9772016-06-26 09:35:38 -04001660 pstate = to_sde_plane_state(state);
Clarence Ipaa0faf42016-05-30 12:07:48 -04001661 ret = msm_property_atomic_get(&psde->property_info,
1662 pstate->property_values, pstate->property_blobs,
1663 property, val);
Clarence Ipe78efb72016-06-24 18:35:21 -04001664 }
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001665
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001666 return ret;
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001667}
1668
1669static void sde_plane_destroy(struct drm_plane *plane)
1670{
Clarence Ip13a8cf42016-09-29 17:27:47 -04001671 struct sde_plane *psde = plane ? to_sde_plane(plane) : NULL;
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001672
Clarence Ip13a8cf42016-09-29 17:27:47 -04001673 SDE_DEBUG_PLANE(psde, "\n");
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001674
Clarence Ip13a8cf42016-09-29 17:27:47 -04001675 if (psde) {
Alan Kwong1a00e4d2016-07-18 09:42:30 -04001676 _sde_plane_set_qos_ctrl(plane, false, SDE_PLANE_QOS_PANIC_CTRL);
1677
Clarence Ip4ce59322016-06-26 22:27:51 -04001678 debugfs_remove_recursive(psde->debugfs_root);
Clarence Ipe78efb72016-06-24 18:35:21 -04001679
Dhaval Patel4e574842016-08-23 15:11:37 -07001680 if (psde->blob_info)
1681 drm_property_unreference_blob(psde->blob_info);
Clarence Ipaa0faf42016-05-30 12:07:48 -04001682 msm_property_destroy(&psde->property_info);
Clarence Ip730e7192016-06-26 22:45:09 -04001683 mutex_destroy(&psde->lock);
1684
Clarence Ip4ce59322016-06-26 22:27:51 -04001685 drm_plane_helper_disable(plane);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001686
Clarence Ip4ce59322016-06-26 22:27:51 -04001687 /* this will destroy the states as well */
1688 drm_plane_cleanup(plane);
1689
Clarence Ip4c1d9772016-06-26 09:35:38 -04001690 if (psde->pipe_hw)
1691 sde_hw_sspp_destroy(psde->pipe_hw);
1692
Clarence Ip4ce59322016-06-26 22:27:51 -04001693 kfree(psde);
1694 }
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001695}
1696
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001697static void sde_plane_destroy_state(struct drm_plane *plane,
1698 struct drm_plane_state *state)
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001699{
Clarence Ipaa0faf42016-05-30 12:07:48 -04001700 struct sde_plane *psde;
Clarence Ipe78efb72016-06-24 18:35:21 -04001701 struct sde_plane_state *pstate;
Clarence Ipe78efb72016-06-24 18:35:21 -04001702
Clarence Ipae4e60c2016-06-26 22:44:04 -04001703 if (!plane || !state) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001704 SDE_ERROR("invalid arg(s), plane %d state %d\n",
1705 plane != 0, state != 0);
Clarence Ipae4e60c2016-06-26 22:44:04 -04001706 return;
1707 }
1708
Clarence Ipaa0faf42016-05-30 12:07:48 -04001709 psde = to_sde_plane(plane);
Clarence Ip730e7192016-06-26 22:45:09 -04001710 pstate = to_sde_plane_state(state);
1711
Clarence Ip13a8cf42016-09-29 17:27:47 -04001712 SDE_DEBUG_PLANE(psde, "\n");
Clarence Ip730e7192016-06-26 22:45:09 -04001713
Clarence Ipe78efb72016-06-24 18:35:21 -04001714 /* remove ref count for frame buffers */
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001715 if (state->fb)
1716 drm_framebuffer_unreference(state->fb);
1717
Clarence Ipae4e60c2016-06-26 22:44:04 -04001718 /* remove ref count for fence */
Clarence Ipcae1bb62016-07-07 12:07:13 -04001719 if (pstate->input_fence)
1720 sde_sync_put(pstate->input_fence);
Clarence Ipae4e60c2016-06-26 22:44:04 -04001721
Clarence Ipaa0faf42016-05-30 12:07:48 -04001722 /* destroy value helper */
1723 msm_property_destroy_state(&psde->property_info, pstate,
1724 pstate->property_values, pstate->property_blobs);
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001725}
1726
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001727static struct drm_plane_state *
1728sde_plane_duplicate_state(struct drm_plane *plane)
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001729{
Clarence Ipaa0faf42016-05-30 12:07:48 -04001730 struct sde_plane *psde;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001731 struct sde_plane_state *pstate;
Clarence Ip730e7192016-06-26 22:45:09 -04001732 struct sde_plane_state *old_state;
Clarence Ip17e908b2016-09-29 15:58:00 -04001733 uint64_t input_fence_default;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001734
Clarence Ip13a8cf42016-09-29 17:27:47 -04001735 if (!plane) {
1736 SDE_ERROR("invalid plane\n");
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001737 return NULL;
Clarence Ip13a8cf42016-09-29 17:27:47 -04001738 } else if (!plane->state) {
1739 SDE_ERROR("invalid plane state\n");
1740 return NULL;
1741 }
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001742
Clarence Ip730e7192016-06-26 22:45:09 -04001743 old_state = to_sde_plane_state(plane->state);
Clarence Ipaa0faf42016-05-30 12:07:48 -04001744 psde = to_sde_plane(plane);
1745 pstate = msm_property_alloc_state(&psde->property_info);
Clarence Ip13a8cf42016-09-29 17:27:47 -04001746 if (!pstate) {
1747 SDE_ERROR_PLANE(psde, "failed to allocate state\n");
Clarence Ip730e7192016-06-26 22:45:09 -04001748 return NULL;
Clarence Ip13a8cf42016-09-29 17:27:47 -04001749 }
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001750
Clarence Ip13a8cf42016-09-29 17:27:47 -04001751 SDE_DEBUG_PLANE(psde, "\n");
Clarence Ipaa0faf42016-05-30 12:07:48 -04001752
1753 /* duplicate value helper */
1754 msm_property_duplicate_state(&psde->property_info, old_state, pstate,
1755 pstate->property_values, pstate->property_blobs);
Clarence Ipae4e60c2016-06-26 22:44:04 -04001756
Clarence Ip730e7192016-06-26 22:45:09 -04001757 /* add ref count for frame buffer */
1758 if (pstate->base.fb)
1759 drm_framebuffer_reference(pstate->base.fb);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001760
Clarence Ip17e908b2016-09-29 15:58:00 -04001761 /* clear out any input fence */
1762 pstate->input_fence = 0;
1763 input_fence_default = msm_property_get_default(
1764 &psde->property_info, PLANE_PROP_INPUT_FENCE);
1765 msm_property_set_property(&psde->property_info, pstate->property_values,
1766 PLANE_PROP_INPUT_FENCE, input_fence_default);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001767
Clarence Ip282dad62016-09-27 17:07:35 -04001768 pstate->dirty = 0x0;
Clarence Ip730e7192016-06-26 22:45:09 -04001769 pstate->pending = false;
1770
1771 return &pstate->base;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001772}
1773
1774static void sde_plane_reset(struct drm_plane *plane)
1775{
Clarence Ipae4e60c2016-06-26 22:44:04 -04001776 struct sde_plane *psde;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001777 struct sde_plane_state *pstate;
1778
Clarence Ipae4e60c2016-06-26 22:44:04 -04001779 if (!plane) {
Dhaval Patel47302cf2016-08-18 15:04:28 -07001780 SDE_ERROR("invalid plane\n");
Clarence Ipae4e60c2016-06-26 22:44:04 -04001781 return;
1782 }
1783
Clarence Ip730e7192016-06-26 22:45:09 -04001784 psde = to_sde_plane(plane);
Clarence Ip13a8cf42016-09-29 17:27:47 -04001785 SDE_DEBUG_PLANE(psde, "\n");
Clarence Ip730e7192016-06-26 22:45:09 -04001786
Clarence Ipae4e60c2016-06-26 22:44:04 -04001787 /* remove previous state, if present */
Clarence Ipaa0faf42016-05-30 12:07:48 -04001788 if (plane->state) {
Clarence Ipae4e60c2016-06-26 22:44:04 -04001789 sde_plane_destroy_state(plane, plane->state);
Clarence Ipaa0faf42016-05-30 12:07:48 -04001790 plane->state = 0;
Clarence Ipae4e60c2016-06-26 22:44:04 -04001791 }
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001792
Clarence Ipaa0faf42016-05-30 12:07:48 -04001793 pstate = msm_property_alloc_state(&psde->property_info);
Clarence Ip13a8cf42016-09-29 17:27:47 -04001794 if (!pstate) {
1795 SDE_ERROR_PLANE(psde, "failed to allocate state\n");
Clarence Ipaa0faf42016-05-30 12:07:48 -04001796 return;
Clarence Ip13a8cf42016-09-29 17:27:47 -04001797 }
Clarence Ip730e7192016-06-26 22:45:09 -04001798
Clarence Ipaa0faf42016-05-30 12:07:48 -04001799 /* reset value helper */
1800 msm_property_reset_state(&psde->property_info, pstate,
1801 pstate->property_values, pstate->property_blobs);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001802
1803 pstate->base.plane = plane;
1804
1805 plane->state = &pstate->base;
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001806}
1807
1808static const struct drm_plane_funcs sde_plane_funcs = {
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001809 .update_plane = drm_atomic_helper_update_plane,
1810 .disable_plane = drm_atomic_helper_disable_plane,
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001811 .destroy = sde_plane_destroy,
1812 .set_property = sde_plane_set_property,
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001813 .atomic_set_property = sde_plane_atomic_set_property,
1814 .atomic_get_property = sde_plane_atomic_get_property,
1815 .reset = sde_plane_reset,
1816 .atomic_duplicate_state = sde_plane_duplicate_state,
1817 .atomic_destroy_state = sde_plane_destroy_state,
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001818};
1819
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001820static const struct drm_plane_helper_funcs sde_plane_helper_funcs = {
1821 .prepare_fb = sde_plane_prepare_fb,
1822 .cleanup_fb = sde_plane_cleanup_fb,
1823 .atomic_check = sde_plane_atomic_check,
1824 .atomic_update = sde_plane_atomic_update,
1825};
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001826
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001827enum sde_sspp sde_plane_pipe(struct drm_plane *plane)
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001828{
Clarence Ip13a8cf42016-09-29 17:27:47 -04001829 return plane ? to_sde_plane(plane)->pipe : SSPP_NONE;
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001830}
1831
Clarence Ip4ce59322016-06-26 22:27:51 -04001832static void _sde_plane_init_debugfs(struct sde_plane *psde, struct sde_kms *kms)
1833{
1834 const struct sde_sspp_sub_blks *sblk = 0;
1835 const struct sde_sspp_cfg *cfg = 0;
1836
1837 if (psde && psde->pipe_hw)
1838 cfg = psde->pipe_hw->cap;
1839 if (cfg)
1840 sblk = cfg->sblk;
1841
1842 if (kms && sblk) {
1843 /* create overall sub-directory for the pipe */
1844 psde->debugfs_root =
1845 debugfs_create_dir(psde->pipe_name,
1846 sde_debugfs_get_root(kms));
1847 if (psde->debugfs_root) {
1848 /* don't error check these */
Clarence Ip4c1d9772016-06-26 09:35:38 -04001849 debugfs_create_x32("features", 0644,
Clarence Ip4ce59322016-06-26 22:27:51 -04001850 psde->debugfs_root, &psde->features);
1851
1852 /* add register dump support */
1853 sde_debugfs_setup_regset32(&psde->debugfs_src,
1854 sblk->src_blk.base + cfg->base,
1855 sblk->src_blk.len,
Clarence Ipaac9f332016-08-31 15:46:35 -04001856 kms);
Clarence Ip4ce59322016-06-26 22:27:51 -04001857 sde_debugfs_create_regset32("src_blk", 0444,
1858 psde->debugfs_root, &psde->debugfs_src);
1859
1860 sde_debugfs_setup_regset32(&psde->debugfs_scaler,
1861 sblk->scaler_blk.base + cfg->base,
1862 sblk->scaler_blk.len,
Clarence Ipaac9f332016-08-31 15:46:35 -04001863 kms);
Clarence Ip4ce59322016-06-26 22:27:51 -04001864 sde_debugfs_create_regset32("scaler_blk", 0444,
1865 psde->debugfs_root,
1866 &psde->debugfs_scaler);
1867
1868 sde_debugfs_setup_regset32(&psde->debugfs_csc,
1869 sblk->csc_blk.base + cfg->base,
1870 sblk->csc_blk.len,
Clarence Ipaac9f332016-08-31 15:46:35 -04001871 kms);
Clarence Ip4ce59322016-06-26 22:27:51 -04001872 sde_debugfs_create_regset32("csc_blk", 0444,
1873 psde->debugfs_root, &psde->debugfs_csc);
1874 }
1875 }
1876}
1877
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001878/* initialize plane */
Clarence Ipe78efb72016-06-24 18:35:21 -04001879struct drm_plane *sde_plane_init(struct drm_device *dev,
Clarence Ip4c1d9772016-06-26 09:35:38 -04001880 uint32_t pipe, bool primary_plane)
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001881{
1882 struct drm_plane *plane = NULL;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001883 struct sde_plane *psde;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001884 struct msm_drm_private *priv;
1885 struct sde_kms *kms;
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001886 enum drm_plane_type type;
Dhaval Patel47302cf2016-08-18 15:04:28 -07001887 int ret = -EINVAL, max_blendstages = 255;
Clarence Ip4c1d9772016-06-26 09:35:38 -04001888
1889 if (!dev) {
Dhaval Patel47302cf2016-08-18 15:04:28 -07001890 SDE_ERROR("[%u]device is NULL\n", pipe);
Clarence Ip4c1d9772016-06-26 09:35:38 -04001891 goto exit;
1892 }
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001893
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001894 priv = dev->dev_private;
Ben Chan78647cd2016-06-26 22:02:47 -04001895 if (!priv) {
Dhaval Patel47302cf2016-08-18 15:04:28 -07001896 SDE_ERROR("[%u]private data is NULL\n", pipe);
Ben Chan78647cd2016-06-26 22:02:47 -04001897 goto exit;
1898 }
1899
1900 if (!priv->kms) {
Dhaval Patel47302cf2016-08-18 15:04:28 -07001901 SDE_ERROR("[%u]invalid KMS reference\n", pipe);
Ben Chan78647cd2016-06-26 22:02:47 -04001902 goto exit;
1903 }
1904 kms = to_sde_kms(priv->kms);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001905
Clarence Ip4c1d9772016-06-26 09:35:38 -04001906 if (!kms->catalog) {
Dhaval Patel47302cf2016-08-18 15:04:28 -07001907 SDE_ERROR("[%u]invalid catalog reference\n", pipe);
Clarence Ip4c1d9772016-06-26 09:35:38 -04001908 goto exit;
1909 }
1910
Clarence Ip4ce59322016-06-26 22:27:51 -04001911 /* create and zero local structure */
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001912 psde = kzalloc(sizeof(*psde), GFP_KERNEL);
1913 if (!psde) {
Dhaval Patel47302cf2016-08-18 15:04:28 -07001914 SDE_ERROR("[%u]failed to allocate local plane struct\n", pipe);
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001915 ret = -ENOMEM;
Clarence Ip4c1d9772016-06-26 09:35:38 -04001916 goto exit;
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001917 }
1918
Clarence Ip4c1d9772016-06-26 09:35:38 -04001919 /* cache local stuff for later */
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001920 plane = &psde->base;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001921 psde->pipe = pipe;
Alan Kwong112a84f2016-05-24 20:49:21 -04001922 psde->mmu_id = kms->mmu_id[MSM_SMMU_DOMAIN_UNSECURE];
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001923
Clarence Ip4c1d9772016-06-26 09:35:38 -04001924 /* initialize underlying h/w driver */
1925 psde->pipe_hw = sde_hw_sspp_init(pipe, kms->mmio, kms->catalog);
1926 if (IS_ERR(psde->pipe_hw)) {
Dhaval Patel47302cf2016-08-18 15:04:28 -07001927 SDE_ERROR("[%u]SSPP init failed\n", pipe);
Clarence Ip4c1d9772016-06-26 09:35:38 -04001928 ret = PTR_ERR(psde->pipe_hw);
1929 goto clean_plane;
1930 } else if (!psde->pipe_hw->cap || !psde->pipe_hw->cap->sblk) {
Dhaval Patel47302cf2016-08-18 15:04:28 -07001931 SDE_ERROR("[%u]SSPP init returned invalid cfg\n", pipe);
Clarence Ip4c1d9772016-06-26 09:35:38 -04001932 goto clean_sspp;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001933 }
Clarence Ip4c1d9772016-06-26 09:35:38 -04001934
1935 /* cache features mask for later */
1936 psde->features = psde->pipe_hw->cap->features;
1937 psde->pipe_sblk = psde->pipe_hw->cap->sblk;
Clarence Ipea3d6262016-07-15 16:20:11 -04001938 if (!psde->pipe_sblk) {
Clarence Ip13a8cf42016-09-29 17:27:47 -04001939 SDE_ERROR("[%u]invalid sblk\n", pipe);
Clarence Ipea3d6262016-07-15 16:20:11 -04001940 goto clean_sspp;
1941 }
Clarence Ip4c1d9772016-06-26 09:35:38 -04001942
Dhaval Patel47302cf2016-08-18 15:04:28 -07001943 if (kms->catalog && kms->catalog->mixer_count && kms->catalog->mixer)
1944 max_blendstages = kms->catalog->mixer[0].sblk->maxblendstages;
1945
Clarence Ip4c1d9772016-06-26 09:35:38 -04001946 /* add plane to DRM framework */
Clarence Ipea3d6262016-07-15 16:20:11 -04001947 psde->nformats = sde_populate_formats(psde->pipe_sblk->format_list,
1948 psde->formats,
1949 0,
1950 ARRAY_SIZE(psde->formats));
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001951
Clarence Ip4c1d9772016-06-26 09:35:38 -04001952 if (!psde->nformats) {
Dhaval Patel47302cf2016-08-18 15:04:28 -07001953 SDE_ERROR("[%u]no valid formats for plane\n", pipe);
Clarence Ip4c1d9772016-06-26 09:35:38 -04001954 goto clean_sspp;
1955 }
1956
1957 if (psde->features & BIT(SDE_SSPP_CURSOR))
1958 type = DRM_PLANE_TYPE_CURSOR;
1959 else if (primary_plane)
1960 type = DRM_PLANE_TYPE_PRIMARY;
1961 else
1962 type = DRM_PLANE_TYPE_OVERLAY;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001963 ret = drm_universal_plane_init(dev, plane, 0xff, &sde_plane_funcs,
1964 psde->formats, psde->nformats,
1965 type);
1966 if (ret)
Clarence Ip4c1d9772016-06-26 09:35:38 -04001967 goto clean_sspp;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001968
Clarence Ip4c1d9772016-06-26 09:35:38 -04001969 /* success! finalize initialization */
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001970 drm_plane_helper_add(plane, &sde_plane_helper_funcs);
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001971
Clarence Ipaa0faf42016-05-30 12:07:48 -04001972 msm_property_init(&psde->property_info, &plane->base, dev,
1973 priv->plane_property, psde->property_data,
1974 PLANE_PROP_COUNT, PLANE_PROP_BLOBCOUNT,
1975 sizeof(struct sde_plane_state));
1976
Dhaval Patel47302cf2016-08-18 15:04:28 -07001977 _sde_plane_install_properties(plane, max_blendstages);
Clarence Ip5e2a9222016-06-26 22:38:24 -04001978
Clarence Ip4ce59322016-06-26 22:27:51 -04001979 /* save user friendly pipe name for later */
Clarence Ip5e2a9222016-06-26 22:38:24 -04001980 snprintf(psde->pipe_name, SDE_NAME_SIZE, "plane%u", plane->base.id);
Clarence Ip4ce59322016-06-26 22:27:51 -04001981
Clarence Ip730e7192016-06-26 22:45:09 -04001982 mutex_init(&psde->lock);
1983
Clarence Ip4ce59322016-06-26 22:27:51 -04001984 _sde_plane_init_debugfs(psde, kms);
1985
Clarence Ip13a8cf42016-09-29 17:27:47 -04001986 DRM_INFO("%s created for pipe %u\n", psde->pipe_name, pipe);
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001987 return plane;
1988
Clarence Ip4c1d9772016-06-26 09:35:38 -04001989clean_sspp:
1990 if (psde && psde->pipe_hw)
1991 sde_hw_sspp_destroy(psde->pipe_hw);
1992clean_plane:
1993 kfree(psde);
Ben Chan78647cd2016-06-26 22:02:47 -04001994exit:
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001995 return ERR_PTR(ret);
1996}