blob: 665668b6f2b14f7d6df5179d5ae37576336d1ea6 [file] [log] [blame]
Boojin Kimb7d861d2011-12-26 18:49:52 +09001/*
2 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
Jassi Brarb3040e42010-05-23 20:28:19 -07004 *
5 * Copyright (C) 2010 Samsung Electronics Co. Ltd.
6 * Jaswinder Singh <jassi.brar@samsung.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
Boojin Kimb7d861d2011-12-26 18:49:52 +090014#include <linux/kernel.h>
Jassi Brarb3040e42010-05-23 20:28:19 -070015#include <linux/io.h>
16#include <linux/init.h>
17#include <linux/slab.h>
18#include <linux/module.h>
Boojin Kimb7d861d2011-12-26 18:49:52 +090019#include <linux/string.h>
20#include <linux/delay.h>
21#include <linux/interrupt.h>
22#include <linux/dma-mapping.h>
Jassi Brarb3040e42010-05-23 20:28:19 -070023#include <linux/dmaengine.h>
Jassi Brarb3040e42010-05-23 20:28:19 -070024#include <linux/amba/bus.h>
25#include <linux/amba/pl330.h>
Boojin Kim1b9bb712011-09-02 09:44:30 +090026#include <linux/scatterlist.h>
Thomas Abraham93ed5542011-10-24 11:43:31 +020027#include <linux/of.h>
Jassi Brarb3040e42010-05-23 20:28:19 -070028
Russell King - ARM Linuxd2ebfb32012-03-06 22:34:26 +000029#include "dmaengine.h"
Boojin Kimb7d861d2011-12-26 18:49:52 +090030#define PL330_MAX_CHAN 8
31#define PL330_MAX_IRQS 32
32#define PL330_MAX_PERI 32
33
34enum pl330_srccachectrl {
35 SCCTRL0, /* Noncacheable and nonbufferable */
36 SCCTRL1, /* Bufferable only */
37 SCCTRL2, /* Cacheable, but do not allocate */
38 SCCTRL3, /* Cacheable and bufferable, but do not allocate */
39 SINVALID1,
40 SINVALID2,
41 SCCTRL6, /* Cacheable write-through, allocate on reads only */
42 SCCTRL7, /* Cacheable write-back, allocate on reads only */
43};
44
45enum pl330_dstcachectrl {
46 DCCTRL0, /* Noncacheable and nonbufferable */
47 DCCTRL1, /* Bufferable only */
48 DCCTRL2, /* Cacheable, but do not allocate */
49 DCCTRL3, /* Cacheable and bufferable, but do not allocate */
Linus Torvaldsef08e782012-03-29 15:34:57 -070050 DINVALID1, /* AWCACHE = 0x1000 */
Boojin Kimb7d861d2011-12-26 18:49:52 +090051 DINVALID2,
52 DCCTRL6, /* Cacheable write-through, allocate on writes only */
53 DCCTRL7, /* Cacheable write-back, allocate on writes only */
54};
55
56enum pl330_byteswap {
57 SWAP_NO,
58 SWAP_2,
59 SWAP_4,
60 SWAP_8,
61 SWAP_16,
62};
63
64enum pl330_reqtype {
65 MEMTOMEM,
66 MEMTODEV,
67 DEVTOMEM,
68 DEVTODEV,
69};
70
71/* Register and Bit field Definitions */
72#define DS 0x0
73#define DS_ST_STOP 0x0
74#define DS_ST_EXEC 0x1
75#define DS_ST_CMISS 0x2
76#define DS_ST_UPDTPC 0x3
77#define DS_ST_WFE 0x4
78#define DS_ST_ATBRR 0x5
79#define DS_ST_QBUSY 0x6
80#define DS_ST_WFP 0x7
81#define DS_ST_KILL 0x8
82#define DS_ST_CMPLT 0x9
83#define DS_ST_FLTCMP 0xe
84#define DS_ST_FAULT 0xf
85
86#define DPC 0x4
87#define INTEN 0x20
88#define ES 0x24
89#define INTSTATUS 0x28
90#define INTCLR 0x2c
91#define FSM 0x30
92#define FSC 0x34
93#define FTM 0x38
94
95#define _FTC 0x40
96#define FTC(n) (_FTC + (n)*0x4)
97
98#define _CS 0x100
99#define CS(n) (_CS + (n)*0x8)
100#define CS_CNS (1 << 21)
101
102#define _CPC 0x104
103#define CPC(n) (_CPC + (n)*0x8)
104
105#define _SA 0x400
106#define SA(n) (_SA + (n)*0x20)
107
108#define _DA 0x404
109#define DA(n) (_DA + (n)*0x20)
110
111#define _CC 0x408
112#define CC(n) (_CC + (n)*0x20)
113
114#define CC_SRCINC (1 << 0)
115#define CC_DSTINC (1 << 14)
116#define CC_SRCPRI (1 << 8)
117#define CC_DSTPRI (1 << 22)
118#define CC_SRCNS (1 << 9)
119#define CC_DSTNS (1 << 23)
120#define CC_SRCIA (1 << 10)
121#define CC_DSTIA (1 << 24)
122#define CC_SRCBRSTLEN_SHFT 4
123#define CC_DSTBRSTLEN_SHFT 18
124#define CC_SRCBRSTSIZE_SHFT 1
125#define CC_DSTBRSTSIZE_SHFT 15
126#define CC_SRCCCTRL_SHFT 11
127#define CC_SRCCCTRL_MASK 0x7
128#define CC_DSTCCTRL_SHFT 25
129#define CC_DRCCCTRL_MASK 0x7
130#define CC_SWAP_SHFT 28
131
132#define _LC0 0x40c
133#define LC0(n) (_LC0 + (n)*0x20)
134
135#define _LC1 0x410
136#define LC1(n) (_LC1 + (n)*0x20)
137
138#define DBGSTATUS 0xd00
139#define DBG_BUSY (1 << 0)
140
141#define DBGCMD 0xd04
142#define DBGINST0 0xd08
143#define DBGINST1 0xd0c
144
145#define CR0 0xe00
146#define CR1 0xe04
147#define CR2 0xe08
148#define CR3 0xe0c
149#define CR4 0xe10
150#define CRD 0xe14
151
152#define PERIPH_ID 0xfe0
Boojin Kim3ecf51a2011-12-26 18:55:47 +0900153#define PERIPH_REV_SHIFT 20
154#define PERIPH_REV_MASK 0xf
155#define PERIPH_REV_R0P0 0
156#define PERIPH_REV_R1P0 1
157#define PERIPH_REV_R1P1 2
Boojin Kimb7d861d2011-12-26 18:49:52 +0900158#define PCELL_ID 0xff0
159
160#define CR0_PERIPH_REQ_SET (1 << 0)
161#define CR0_BOOT_EN_SET (1 << 1)
162#define CR0_BOOT_MAN_NS (1 << 2)
163#define CR0_NUM_CHANS_SHIFT 4
164#define CR0_NUM_CHANS_MASK 0x7
165#define CR0_NUM_PERIPH_SHIFT 12
166#define CR0_NUM_PERIPH_MASK 0x1f
167#define CR0_NUM_EVENTS_SHIFT 17
168#define CR0_NUM_EVENTS_MASK 0x1f
169
170#define CR1_ICACHE_LEN_SHIFT 0
171#define CR1_ICACHE_LEN_MASK 0x7
172#define CR1_NUM_ICACHELINES_SHIFT 4
173#define CR1_NUM_ICACHELINES_MASK 0xf
174
175#define CRD_DATA_WIDTH_SHIFT 0
176#define CRD_DATA_WIDTH_MASK 0x7
177#define CRD_WR_CAP_SHIFT 4
178#define CRD_WR_CAP_MASK 0x7
179#define CRD_WR_Q_DEP_SHIFT 8
180#define CRD_WR_Q_DEP_MASK 0xf
181#define CRD_RD_CAP_SHIFT 12
182#define CRD_RD_CAP_MASK 0x7
183#define CRD_RD_Q_DEP_SHIFT 16
184#define CRD_RD_Q_DEP_MASK 0xf
185#define CRD_DATA_BUFF_SHIFT 20
186#define CRD_DATA_BUFF_MASK 0x3ff
187
188#define PART 0x330
189#define DESIGNER 0x41
190#define REVISION 0x0
191#define INTEG_CFG 0x0
192#define PERIPH_ID_VAL ((PART << 0) | (DESIGNER << 12))
193
194#define PCELL_ID_VAL 0xb105f00d
195
196#define PL330_STATE_STOPPED (1 << 0)
197#define PL330_STATE_EXECUTING (1 << 1)
198#define PL330_STATE_WFE (1 << 2)
199#define PL330_STATE_FAULTING (1 << 3)
200#define PL330_STATE_COMPLETING (1 << 4)
201#define PL330_STATE_WFP (1 << 5)
202#define PL330_STATE_KILLING (1 << 6)
203#define PL330_STATE_FAULT_COMPLETING (1 << 7)
204#define PL330_STATE_CACHEMISS (1 << 8)
205#define PL330_STATE_UPDTPC (1 << 9)
206#define PL330_STATE_ATBARRIER (1 << 10)
207#define PL330_STATE_QUEUEBUSY (1 << 11)
208#define PL330_STATE_INVALID (1 << 15)
209
210#define PL330_STABLE_STATES (PL330_STATE_STOPPED | PL330_STATE_EXECUTING \
211 | PL330_STATE_WFE | PL330_STATE_FAULTING)
212
213#define CMD_DMAADDH 0x54
214#define CMD_DMAEND 0x00
215#define CMD_DMAFLUSHP 0x35
216#define CMD_DMAGO 0xa0
217#define CMD_DMALD 0x04
218#define CMD_DMALDP 0x25
219#define CMD_DMALP 0x20
220#define CMD_DMALPEND 0x28
221#define CMD_DMAKILL 0x01
222#define CMD_DMAMOV 0xbc
223#define CMD_DMANOP 0x18
224#define CMD_DMARMB 0x12
225#define CMD_DMASEV 0x34
226#define CMD_DMAST 0x08
227#define CMD_DMASTP 0x29
228#define CMD_DMASTZ 0x0c
229#define CMD_DMAWFE 0x36
230#define CMD_DMAWFP 0x30
231#define CMD_DMAWMB 0x13
232
233#define SZ_DMAADDH 3
234#define SZ_DMAEND 1
235#define SZ_DMAFLUSHP 2
236#define SZ_DMALD 1
237#define SZ_DMALDP 2
238#define SZ_DMALP 2
239#define SZ_DMALPEND 2
240#define SZ_DMAKILL 1
241#define SZ_DMAMOV 6
242#define SZ_DMANOP 1
243#define SZ_DMARMB 1
244#define SZ_DMASEV 2
245#define SZ_DMAST 1
246#define SZ_DMASTP 2
247#define SZ_DMASTZ 1
248#define SZ_DMAWFE 2
249#define SZ_DMAWFP 2
250#define SZ_DMAWMB 1
251#define SZ_DMAGO 6
252
253#define BRST_LEN(ccr) ((((ccr) >> CC_SRCBRSTLEN_SHFT) & 0xf) + 1)
254#define BRST_SIZE(ccr) (1 << (((ccr) >> CC_SRCBRSTSIZE_SHFT) & 0x7))
255
256#define BYTE_TO_BURST(b, ccr) ((b) / BRST_SIZE(ccr) / BRST_LEN(ccr))
257#define BURST_TO_BYTE(c, ccr) ((c) * BRST_SIZE(ccr) * BRST_LEN(ccr))
258
259/*
260 * With 256 bytes, we can do more than 2.5MB and 5MB xfers per req
261 * at 1byte/burst for P<->M and M<->M respectively.
262 * For typical scenario, at 1word/burst, 10MB and 20MB xfers per req
263 * should be enough for P<->M and M<->M respectively.
264 */
265#define MCODE_BUFF_PER_REQ 256
266
267/* If the _pl330_req is available to the client */
268#define IS_FREE(req) (*((u8 *)((req)->mc_cpu)) == CMD_DMAEND)
269
270/* Use this _only_ to wait on transient states */
271#define UNTIL(t, s) while (!(_state(t) & (s))) cpu_relax();
272
273#ifdef PL330_DEBUG_MCGEN
274static unsigned cmd_line;
275#define PL330_DBGCMD_DUMP(off, x...) do { \
276 printk("%x:", cmd_line); \
277 printk(x); \
278 cmd_line += off; \
279 } while (0)
280#define PL330_DBGMC_START(addr) (cmd_line = addr)
281#else
282#define PL330_DBGCMD_DUMP(off, x...) do {} while (0)
283#define PL330_DBGMC_START(addr) do {} while (0)
284#endif
285
286/* The number of default descriptors */
Russell King - ARM Linuxd2ebfb32012-03-06 22:34:26 +0000287
Jassi Brarb3040e42010-05-23 20:28:19 -0700288#define NR_DEFAULT_DESC 16
289
Boojin Kimb7d861d2011-12-26 18:49:52 +0900290/* Populated by the PL330 core driver for DMA API driver's info */
291struct pl330_config {
292 u32 periph_id;
293 u32 pcell_id;
294#define DMAC_MODE_NS (1 << 0)
295 unsigned int mode;
296 unsigned int data_bus_width:10; /* In number of bits */
297 unsigned int data_buf_dep:10;
298 unsigned int num_chan:4;
299 unsigned int num_peri:6;
300 u32 peri_ns;
301 unsigned int num_events:6;
302 u32 irq_ns;
303};
304
305/* Handle to the DMAC provided to the PL330 core */
306struct pl330_info {
307 /* Owning device */
308 struct device *dev;
309 /* Size of MicroCode buffers for each channel. */
310 unsigned mcbufsz;
311 /* ioremap'ed address of PL330 registers. */
312 void __iomem *base;
313 /* Client can freely use it. */
314 void *client_data;
315 /* PL330 core data, Client must not touch it. */
316 void *pl330_data;
317 /* Populated by the PL330 core driver during pl330_add */
318 struct pl330_config pcfg;
319 /*
320 * If the DMAC has some reset mechanism, then the
321 * client may want to provide pointer to the method.
322 */
323 void (*dmac_reset)(struct pl330_info *pi);
324};
325
326/**
327 * Request Configuration.
328 * The PL330 core does not modify this and uses the last
329 * working configuration if the request doesn't provide any.
330 *
331 * The Client may want to provide this info only for the
332 * first request and a request with new settings.
333 */
334struct pl330_reqcfg {
335 /* Address Incrementing */
336 unsigned dst_inc:1;
337 unsigned src_inc:1;
338
339 /*
340 * For now, the SRC & DST protection levels
341 * and burst size/length are assumed same.
342 */
343 bool nonsecure;
344 bool privileged;
345 bool insnaccess;
346 unsigned brst_len:5;
347 unsigned brst_size:3; /* in power of 2 */
348
349 enum pl330_dstcachectrl dcctl;
350 enum pl330_srccachectrl scctl;
351 enum pl330_byteswap swap;
Boojin Kim3ecf51a2011-12-26 18:55:47 +0900352 struct pl330_config *pcfg;
Boojin Kimb7d861d2011-12-26 18:49:52 +0900353};
354
355/*
356 * One cycle of DMAC operation.
357 * There may be more than one xfer in a request.
358 */
359struct pl330_xfer {
360 u32 src_addr;
361 u32 dst_addr;
362 /* Size to xfer */
363 u32 bytes;
364 /*
365 * Pointer to next xfer in the list.
366 * The last xfer in the req must point to NULL.
367 */
368 struct pl330_xfer *next;
369};
370
371/* The xfer callbacks are made with one of these arguments. */
372enum pl330_op_err {
373 /* The all xfers in the request were success. */
374 PL330_ERR_NONE,
375 /* If req aborted due to global error. */
376 PL330_ERR_ABORT,
377 /* If req failed due to problem with Channel. */
378 PL330_ERR_FAIL,
379};
380
381/* A request defining Scatter-Gather List ending with NULL xfer. */
382struct pl330_req {
383 enum pl330_reqtype rqtype;
384 /* Index of peripheral for the xfer. */
385 unsigned peri:5;
386 /* Unique token for this xfer, set by the client. */
387 void *token;
388 /* Callback to be called after xfer. */
389 void (*xfer_cb)(void *token, enum pl330_op_err err);
390 /* If NULL, req will be done at last set parameters. */
391 struct pl330_reqcfg *cfg;
392 /* Pointer to first xfer in the request. */
393 struct pl330_xfer *x;
Javi Merinofdec53d2012-06-13 15:07:00 +0100394 /* Hook to attach to DMAC's list of reqs with due callback */
395 struct list_head rqd;
Boojin Kimb7d861d2011-12-26 18:49:52 +0900396};
397
398/*
399 * To know the status of the channel and DMAC, the client
400 * provides a pointer to this structure. The PL330 core
401 * fills it with current information.
402 */
403struct pl330_chanstatus {
404 /*
405 * If the DMAC engine halted due to some error,
406 * the client should remove-add DMAC.
407 */
408 bool dmac_halted;
409 /*
410 * If channel is halted due to some error,
411 * the client should ABORT/FLUSH and START the channel.
412 */
413 bool faulting;
414 /* Location of last load */
415 u32 src_addr;
416 /* Location of last store */
417 u32 dst_addr;
418 /*
419 * Pointer to the currently active req, NULL if channel is
420 * inactive, even though the requests may be present.
421 */
422 struct pl330_req *top_req;
423 /* Pointer to req waiting second in the queue if any. */
424 struct pl330_req *wait_req;
425};
426
427enum pl330_chan_op {
428 /* Start the channel */
429 PL330_OP_START,
430 /* Abort the active xfer */
431 PL330_OP_ABORT,
432 /* Stop xfer and flush queue */
433 PL330_OP_FLUSH,
434};
435
436struct _xfer_spec {
437 u32 ccr;
438 struct pl330_req *r;
439 struct pl330_xfer *x;
440};
441
442enum dmamov_dst {
443 SAR = 0,
444 CCR,
445 DAR,
446};
447
448enum pl330_dst {
449 SRC = 0,
450 DST,
451};
452
453enum pl330_cond {
454 SINGLE,
455 BURST,
456 ALWAYS,
457};
458
459struct _pl330_req {
460 u32 mc_bus;
461 void *mc_cpu;
462 /* Number of bytes taken to setup MC for the req */
463 u32 mc_len;
464 struct pl330_req *r;
Boojin Kimb7d861d2011-12-26 18:49:52 +0900465};
466
467/* ToBeDone for tasklet */
468struct _pl330_tbd {
469 bool reset_dmac;
470 bool reset_mngr;
471 u8 reset_chan;
472};
473
474/* A DMAC Thread */
475struct pl330_thread {
476 u8 id;
477 int ev;
478 /* If the channel is not yet acquired by any client */
479 bool free;
480 /* Parent DMAC */
481 struct pl330_dmac *dmac;
482 /* Only two at a time */
483 struct _pl330_req req[2];
484 /* Index of the last enqueued request */
485 unsigned lstenq;
486 /* Index of the last submitted request or -1 if the DMA is stopped */
487 int req_running;
488};
489
490enum pl330_dmac_state {
491 UNINIT,
492 INIT,
493 DYING,
494};
495
496/* A DMAC */
497struct pl330_dmac {
498 spinlock_t lock;
499 /* Holds list of reqs with due callbacks */
500 struct list_head req_done;
501 /* Pointer to platform specific stuff */
502 struct pl330_info *pinfo;
503 /* Maximum possible events/irqs */
504 int events[32];
505 /* BUS address of MicroCode buffer */
506 u32 mcode_bus;
507 /* CPU address of MicroCode buffer */
508 void *mcode_cpu;
509 /* List of all Channel threads */
510 struct pl330_thread *channels;
511 /* Pointer to the MANAGER thread */
512 struct pl330_thread *manager;
513 /* To handle bad news in interrupt */
514 struct tasklet_struct tasks;
515 struct _pl330_tbd dmac_tbd;
516 /* State of DMAC operation */
517 enum pl330_dmac_state state;
518};
519
Jassi Brarb3040e42010-05-23 20:28:19 -0700520enum desc_status {
521 /* In the DMAC pool */
522 FREE,
523 /*
Masanari Iidad73111c2012-08-04 23:37:53 +0900524 * Allocated to some channel during prep_xxx
Jassi Brarb3040e42010-05-23 20:28:19 -0700525 * Also may be sitting on the work_list.
526 */
527 PREP,
528 /*
529 * Sitting on the work_list and already submitted
530 * to the PL330 core. Not more than two descriptors
531 * of a channel can be BUSY at any time.
532 */
533 BUSY,
534 /*
535 * Sitting on the channel work_list but xfer done
536 * by PL330 core
537 */
538 DONE,
539};
540
541struct dma_pl330_chan {
542 /* Schedule desc completion */
543 struct tasklet_struct task;
544
545 /* DMA-Engine Channel */
546 struct dma_chan chan;
547
Jassi Brarb3040e42010-05-23 20:28:19 -0700548 /* List of to be xfered descriptors */
549 struct list_head work_list;
550
551 /* Pointer to the DMAC that manages this channel,
552 * NULL if the channel is available to be acquired.
553 * As the parent, this DMAC also provides descriptors
554 * to the channel.
555 */
556 struct dma_pl330_dmac *dmac;
557
558 /* To protect channel manipulation */
559 spinlock_t lock;
560
561 /* Token of a hardware channel thread of PL330 DMAC
562 * NULL if the channel is available to be acquired.
563 */
564 void *pl330_chid;
Boojin Kim1b9bb712011-09-02 09:44:30 +0900565
566 /* For D-to-M and M-to-D channels */
567 int burst_sz; /* the peripheral fifo width */
Boojin Kim1d0c1d62011-09-02 09:44:31 +0900568 int burst_len; /* the number of burst */
Boojin Kim1b9bb712011-09-02 09:44:30 +0900569 dma_addr_t fifo_addr;
Boojin Kim42bc9cf2011-09-02 09:44:33 +0900570
571 /* for cyclic capability */
572 bool cyclic;
Jassi Brarb3040e42010-05-23 20:28:19 -0700573};
574
575struct dma_pl330_dmac {
576 struct pl330_info pif;
577
578 /* DMA-Engine Device */
579 struct dma_device ddma;
580
581 /* Pool of descriptors available for the DMAC's channels */
582 struct list_head desc_pool;
583 /* To protect desc_pool manipulation */
584 spinlock_t pool_lock;
585
586 /* Peripheral channels connected to this DMAC */
Rob Herring4e0e6102011-07-25 16:05:04 -0500587 struct dma_pl330_chan *peripherals; /* keep at end */
Jassi Brarb3040e42010-05-23 20:28:19 -0700588};
589
590struct dma_pl330_desc {
591 /* To attach to a queue as child */
592 struct list_head node;
593
594 /* Descriptor for the DMA Engine API */
595 struct dma_async_tx_descriptor txd;
596
597 /* Xfer for PL330 core */
598 struct pl330_xfer px;
599
600 struct pl330_reqcfg rqcfg;
601 struct pl330_req req;
602
603 enum desc_status status;
604
605 /* The channel which currently holds this desc */
606 struct dma_pl330_chan *pchan;
607};
608
Boojin Kimb7d861d2011-12-26 18:49:52 +0900609static inline void _callback(struct pl330_req *r, enum pl330_op_err err)
610{
611 if (r && r->xfer_cb)
612 r->xfer_cb(r->token, err);
613}
614
615static inline bool _queue_empty(struct pl330_thread *thrd)
616{
617 return (IS_FREE(&thrd->req[0]) && IS_FREE(&thrd->req[1]))
618 ? true : false;
619}
620
621static inline bool _queue_full(struct pl330_thread *thrd)
622{
623 return (IS_FREE(&thrd->req[0]) || IS_FREE(&thrd->req[1]))
624 ? false : true;
625}
626
627static inline bool is_manager(struct pl330_thread *thrd)
628{
629 struct pl330_dmac *pl330 = thrd->dmac;
630
631 /* MANAGER is indexed at the end */
632 if (thrd->id == pl330->pinfo->pcfg.num_chan)
633 return true;
634 else
635 return false;
636}
637
638/* If manager of the thread is in Non-Secure mode */
639static inline bool _manager_ns(struct pl330_thread *thrd)
640{
641 struct pl330_dmac *pl330 = thrd->dmac;
642
643 return (pl330->pinfo->pcfg.mode & DMAC_MODE_NS) ? true : false;
644}
645
646static inline u32 get_id(struct pl330_info *pi, u32 off)
647{
648 void __iomem *regs = pi->base;
649 u32 id = 0;
650
651 id |= (readb(regs + off + 0x0) << 0);
652 id |= (readb(regs + off + 0x4) << 8);
653 id |= (readb(regs + off + 0x8) << 16);
654 id |= (readb(regs + off + 0xc) << 24);
655
656 return id;
657}
658
Boojin Kim3ecf51a2011-12-26 18:55:47 +0900659static inline u32 get_revision(u32 periph_id)
660{
661 return (periph_id >> PERIPH_REV_SHIFT) & PERIPH_REV_MASK;
662}
663
Boojin Kimb7d861d2011-12-26 18:49:52 +0900664static inline u32 _emit_ADDH(unsigned dry_run, u8 buf[],
665 enum pl330_dst da, u16 val)
666{
667 if (dry_run)
668 return SZ_DMAADDH;
669
670 buf[0] = CMD_DMAADDH;
671 buf[0] |= (da << 1);
672 *((u16 *)&buf[1]) = val;
673
674 PL330_DBGCMD_DUMP(SZ_DMAADDH, "\tDMAADDH %s %u\n",
675 da == 1 ? "DA" : "SA", val);
676
677 return SZ_DMAADDH;
678}
679
680static inline u32 _emit_END(unsigned dry_run, u8 buf[])
681{
682 if (dry_run)
683 return SZ_DMAEND;
684
685 buf[0] = CMD_DMAEND;
686
687 PL330_DBGCMD_DUMP(SZ_DMAEND, "\tDMAEND\n");
688
689 return SZ_DMAEND;
690}
691
692static inline u32 _emit_FLUSHP(unsigned dry_run, u8 buf[], u8 peri)
693{
694 if (dry_run)
695 return SZ_DMAFLUSHP;
696
697 buf[0] = CMD_DMAFLUSHP;
698
699 peri &= 0x1f;
700 peri <<= 3;
701 buf[1] = peri;
702
703 PL330_DBGCMD_DUMP(SZ_DMAFLUSHP, "\tDMAFLUSHP %u\n", peri >> 3);
704
705 return SZ_DMAFLUSHP;
706}
707
708static inline u32 _emit_LD(unsigned dry_run, u8 buf[], enum pl330_cond cond)
709{
710 if (dry_run)
711 return SZ_DMALD;
712
713 buf[0] = CMD_DMALD;
714
715 if (cond == SINGLE)
716 buf[0] |= (0 << 1) | (1 << 0);
717 else if (cond == BURST)
718 buf[0] |= (1 << 1) | (1 << 0);
719
720 PL330_DBGCMD_DUMP(SZ_DMALD, "\tDMALD%c\n",
721 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'));
722
723 return SZ_DMALD;
724}
725
726static inline u32 _emit_LDP(unsigned dry_run, u8 buf[],
727 enum pl330_cond cond, u8 peri)
728{
729 if (dry_run)
730 return SZ_DMALDP;
731
732 buf[0] = CMD_DMALDP;
733
734 if (cond == BURST)
735 buf[0] |= (1 << 1);
736
737 peri &= 0x1f;
738 peri <<= 3;
739 buf[1] = peri;
740
741 PL330_DBGCMD_DUMP(SZ_DMALDP, "\tDMALDP%c %u\n",
742 cond == SINGLE ? 'S' : 'B', peri >> 3);
743
744 return SZ_DMALDP;
745}
746
747static inline u32 _emit_LP(unsigned dry_run, u8 buf[],
748 unsigned loop, u8 cnt)
749{
750 if (dry_run)
751 return SZ_DMALP;
752
753 buf[0] = CMD_DMALP;
754
755 if (loop)
756 buf[0] |= (1 << 1);
757
758 cnt--; /* DMAC increments by 1 internally */
759 buf[1] = cnt;
760
761 PL330_DBGCMD_DUMP(SZ_DMALP, "\tDMALP_%c %u\n", loop ? '1' : '0', cnt);
762
763 return SZ_DMALP;
764}
765
766struct _arg_LPEND {
767 enum pl330_cond cond;
768 bool forever;
769 unsigned loop;
770 u8 bjump;
771};
772
773static inline u32 _emit_LPEND(unsigned dry_run, u8 buf[],
774 const struct _arg_LPEND *arg)
775{
776 enum pl330_cond cond = arg->cond;
777 bool forever = arg->forever;
778 unsigned loop = arg->loop;
779 u8 bjump = arg->bjump;
780
781 if (dry_run)
782 return SZ_DMALPEND;
783
784 buf[0] = CMD_DMALPEND;
785
786 if (loop)
787 buf[0] |= (1 << 2);
788
789 if (!forever)
790 buf[0] |= (1 << 4);
791
792 if (cond == SINGLE)
793 buf[0] |= (0 << 1) | (1 << 0);
794 else if (cond == BURST)
795 buf[0] |= (1 << 1) | (1 << 0);
796
797 buf[1] = bjump;
798
799 PL330_DBGCMD_DUMP(SZ_DMALPEND, "\tDMALP%s%c_%c bjmpto_%x\n",
800 forever ? "FE" : "END",
801 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'),
802 loop ? '1' : '0',
803 bjump);
804
805 return SZ_DMALPEND;
806}
807
808static inline u32 _emit_KILL(unsigned dry_run, u8 buf[])
809{
810 if (dry_run)
811 return SZ_DMAKILL;
812
813 buf[0] = CMD_DMAKILL;
814
815 return SZ_DMAKILL;
816}
817
818static inline u32 _emit_MOV(unsigned dry_run, u8 buf[],
819 enum dmamov_dst dst, u32 val)
820{
821 if (dry_run)
822 return SZ_DMAMOV;
823
824 buf[0] = CMD_DMAMOV;
825 buf[1] = dst;
826 *((u32 *)&buf[2]) = val;
827
828 PL330_DBGCMD_DUMP(SZ_DMAMOV, "\tDMAMOV %s 0x%x\n",
829 dst == SAR ? "SAR" : (dst == DAR ? "DAR" : "CCR"), val);
830
831 return SZ_DMAMOV;
832}
833
834static inline u32 _emit_NOP(unsigned dry_run, u8 buf[])
835{
836 if (dry_run)
837 return SZ_DMANOP;
838
839 buf[0] = CMD_DMANOP;
840
841 PL330_DBGCMD_DUMP(SZ_DMANOP, "\tDMANOP\n");
842
843 return SZ_DMANOP;
844}
845
846static inline u32 _emit_RMB(unsigned dry_run, u8 buf[])
847{
848 if (dry_run)
849 return SZ_DMARMB;
850
851 buf[0] = CMD_DMARMB;
852
853 PL330_DBGCMD_DUMP(SZ_DMARMB, "\tDMARMB\n");
854
855 return SZ_DMARMB;
856}
857
858static inline u32 _emit_SEV(unsigned dry_run, u8 buf[], u8 ev)
859{
860 if (dry_run)
861 return SZ_DMASEV;
862
863 buf[0] = CMD_DMASEV;
864
865 ev &= 0x1f;
866 ev <<= 3;
867 buf[1] = ev;
868
869 PL330_DBGCMD_DUMP(SZ_DMASEV, "\tDMASEV %u\n", ev >> 3);
870
871 return SZ_DMASEV;
872}
873
874static inline u32 _emit_ST(unsigned dry_run, u8 buf[], enum pl330_cond cond)
875{
876 if (dry_run)
877 return SZ_DMAST;
878
879 buf[0] = CMD_DMAST;
880
881 if (cond == SINGLE)
882 buf[0] |= (0 << 1) | (1 << 0);
883 else if (cond == BURST)
884 buf[0] |= (1 << 1) | (1 << 0);
885
886 PL330_DBGCMD_DUMP(SZ_DMAST, "\tDMAST%c\n",
887 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'));
888
889 return SZ_DMAST;
890}
891
892static inline u32 _emit_STP(unsigned dry_run, u8 buf[],
893 enum pl330_cond cond, u8 peri)
894{
895 if (dry_run)
896 return SZ_DMASTP;
897
898 buf[0] = CMD_DMASTP;
899
900 if (cond == BURST)
901 buf[0] |= (1 << 1);
902
903 peri &= 0x1f;
904 peri <<= 3;
905 buf[1] = peri;
906
907 PL330_DBGCMD_DUMP(SZ_DMASTP, "\tDMASTP%c %u\n",
908 cond == SINGLE ? 'S' : 'B', peri >> 3);
909
910 return SZ_DMASTP;
911}
912
913static inline u32 _emit_STZ(unsigned dry_run, u8 buf[])
914{
915 if (dry_run)
916 return SZ_DMASTZ;
917
918 buf[0] = CMD_DMASTZ;
919
920 PL330_DBGCMD_DUMP(SZ_DMASTZ, "\tDMASTZ\n");
921
922 return SZ_DMASTZ;
923}
924
925static inline u32 _emit_WFE(unsigned dry_run, u8 buf[], u8 ev,
926 unsigned invalidate)
927{
928 if (dry_run)
929 return SZ_DMAWFE;
930
931 buf[0] = CMD_DMAWFE;
932
933 ev &= 0x1f;
934 ev <<= 3;
935 buf[1] = ev;
936
937 if (invalidate)
938 buf[1] |= (1 << 1);
939
940 PL330_DBGCMD_DUMP(SZ_DMAWFE, "\tDMAWFE %u%s\n",
941 ev >> 3, invalidate ? ", I" : "");
942
943 return SZ_DMAWFE;
944}
945
946static inline u32 _emit_WFP(unsigned dry_run, u8 buf[],
947 enum pl330_cond cond, u8 peri)
948{
949 if (dry_run)
950 return SZ_DMAWFP;
951
952 buf[0] = CMD_DMAWFP;
953
954 if (cond == SINGLE)
955 buf[0] |= (0 << 1) | (0 << 0);
956 else if (cond == BURST)
957 buf[0] |= (1 << 1) | (0 << 0);
958 else
959 buf[0] |= (0 << 1) | (1 << 0);
960
961 peri &= 0x1f;
962 peri <<= 3;
963 buf[1] = peri;
964
965 PL330_DBGCMD_DUMP(SZ_DMAWFP, "\tDMAWFP%c %u\n",
966 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'P'), peri >> 3);
967
968 return SZ_DMAWFP;
969}
970
971static inline u32 _emit_WMB(unsigned dry_run, u8 buf[])
972{
973 if (dry_run)
974 return SZ_DMAWMB;
975
976 buf[0] = CMD_DMAWMB;
977
978 PL330_DBGCMD_DUMP(SZ_DMAWMB, "\tDMAWMB\n");
979
980 return SZ_DMAWMB;
981}
982
983struct _arg_GO {
984 u8 chan;
985 u32 addr;
986 unsigned ns;
987};
988
989static inline u32 _emit_GO(unsigned dry_run, u8 buf[],
990 const struct _arg_GO *arg)
991{
992 u8 chan = arg->chan;
993 u32 addr = arg->addr;
994 unsigned ns = arg->ns;
995
996 if (dry_run)
997 return SZ_DMAGO;
998
999 buf[0] = CMD_DMAGO;
1000 buf[0] |= (ns << 1);
1001
1002 buf[1] = chan & 0x7;
1003
1004 *((u32 *)&buf[2]) = addr;
1005
1006 return SZ_DMAGO;
1007}
1008
1009#define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
1010
1011/* Returns Time-Out */
1012static bool _until_dmac_idle(struct pl330_thread *thrd)
1013{
1014 void __iomem *regs = thrd->dmac->pinfo->base;
1015 unsigned long loops = msecs_to_loops(5);
1016
1017 do {
1018 /* Until Manager is Idle */
1019 if (!(readl(regs + DBGSTATUS) & DBG_BUSY))
1020 break;
1021
1022 cpu_relax();
1023 } while (--loops);
1024
1025 if (!loops)
1026 return true;
1027
1028 return false;
1029}
1030
1031static inline void _execute_DBGINSN(struct pl330_thread *thrd,
1032 u8 insn[], bool as_manager)
1033{
1034 void __iomem *regs = thrd->dmac->pinfo->base;
1035 u32 val;
1036
1037 val = (insn[0] << 16) | (insn[1] << 24);
1038 if (!as_manager) {
1039 val |= (1 << 0);
1040 val |= (thrd->id << 8); /* Channel Number */
1041 }
1042 writel(val, regs + DBGINST0);
1043
1044 val = *((u32 *)&insn[2]);
1045 writel(val, regs + DBGINST1);
1046
1047 /* If timed out due to halted state-machine */
1048 if (_until_dmac_idle(thrd)) {
1049 dev_err(thrd->dmac->pinfo->dev, "DMAC halted!\n");
1050 return;
1051 }
1052
1053 /* Get going */
1054 writel(0, regs + DBGCMD);
1055}
1056
1057/*
1058 * Mark a _pl330_req as free.
1059 * We do it by writing DMAEND as the first instruction
1060 * because no valid request is going to have DMAEND as
1061 * its first instruction to execute.
1062 */
1063static void mark_free(struct pl330_thread *thrd, int idx)
1064{
1065 struct _pl330_req *req = &thrd->req[idx];
1066
1067 _emit_END(0, req->mc_cpu);
1068 req->mc_len = 0;
1069
1070 thrd->req_running = -1;
1071}
1072
1073static inline u32 _state(struct pl330_thread *thrd)
1074{
1075 void __iomem *regs = thrd->dmac->pinfo->base;
1076 u32 val;
1077
1078 if (is_manager(thrd))
1079 val = readl(regs + DS) & 0xf;
1080 else
1081 val = readl(regs + CS(thrd->id)) & 0xf;
1082
1083 switch (val) {
1084 case DS_ST_STOP:
1085 return PL330_STATE_STOPPED;
1086 case DS_ST_EXEC:
1087 return PL330_STATE_EXECUTING;
1088 case DS_ST_CMISS:
1089 return PL330_STATE_CACHEMISS;
1090 case DS_ST_UPDTPC:
1091 return PL330_STATE_UPDTPC;
1092 case DS_ST_WFE:
1093 return PL330_STATE_WFE;
1094 case DS_ST_FAULT:
1095 return PL330_STATE_FAULTING;
1096 case DS_ST_ATBRR:
1097 if (is_manager(thrd))
1098 return PL330_STATE_INVALID;
1099 else
1100 return PL330_STATE_ATBARRIER;
1101 case DS_ST_QBUSY:
1102 if (is_manager(thrd))
1103 return PL330_STATE_INVALID;
1104 else
1105 return PL330_STATE_QUEUEBUSY;
1106 case DS_ST_WFP:
1107 if (is_manager(thrd))
1108 return PL330_STATE_INVALID;
1109 else
1110 return PL330_STATE_WFP;
1111 case DS_ST_KILL:
1112 if (is_manager(thrd))
1113 return PL330_STATE_INVALID;
1114 else
1115 return PL330_STATE_KILLING;
1116 case DS_ST_CMPLT:
1117 if (is_manager(thrd))
1118 return PL330_STATE_INVALID;
1119 else
1120 return PL330_STATE_COMPLETING;
1121 case DS_ST_FLTCMP:
1122 if (is_manager(thrd))
1123 return PL330_STATE_INVALID;
1124 else
1125 return PL330_STATE_FAULT_COMPLETING;
1126 default:
1127 return PL330_STATE_INVALID;
1128 }
1129}
1130
1131static void _stop(struct pl330_thread *thrd)
1132{
1133 void __iomem *regs = thrd->dmac->pinfo->base;
1134 u8 insn[6] = {0, 0, 0, 0, 0, 0};
1135
1136 if (_state(thrd) == PL330_STATE_FAULT_COMPLETING)
1137 UNTIL(thrd, PL330_STATE_FAULTING | PL330_STATE_KILLING);
1138
1139 /* Return if nothing needs to be done */
1140 if (_state(thrd) == PL330_STATE_COMPLETING
1141 || _state(thrd) == PL330_STATE_KILLING
1142 || _state(thrd) == PL330_STATE_STOPPED)
1143 return;
1144
1145 _emit_KILL(0, insn);
1146
1147 /* Stop generating interrupts for SEV */
1148 writel(readl(regs + INTEN) & ~(1 << thrd->ev), regs + INTEN);
1149
1150 _execute_DBGINSN(thrd, insn, is_manager(thrd));
1151}
1152
1153/* Start doing req 'idx' of thread 'thrd' */
1154static bool _trigger(struct pl330_thread *thrd)
1155{
1156 void __iomem *regs = thrd->dmac->pinfo->base;
1157 struct _pl330_req *req;
1158 struct pl330_req *r;
1159 struct _arg_GO go;
1160 unsigned ns;
1161 u8 insn[6] = {0, 0, 0, 0, 0, 0};
1162 int idx;
1163
1164 /* Return if already ACTIVE */
1165 if (_state(thrd) != PL330_STATE_STOPPED)
1166 return true;
1167
1168 idx = 1 - thrd->lstenq;
1169 if (!IS_FREE(&thrd->req[idx]))
1170 req = &thrd->req[idx];
1171 else {
1172 idx = thrd->lstenq;
1173 if (!IS_FREE(&thrd->req[idx]))
1174 req = &thrd->req[idx];
1175 else
1176 req = NULL;
1177 }
1178
1179 /* Return if no request */
1180 if (!req || !req->r)
1181 return true;
1182
1183 r = req->r;
1184
1185 if (r->cfg)
1186 ns = r->cfg->nonsecure ? 1 : 0;
1187 else if (readl(regs + CS(thrd->id)) & CS_CNS)
1188 ns = 1;
1189 else
1190 ns = 0;
1191
1192 /* See 'Abort Sources' point-4 at Page 2-25 */
1193 if (_manager_ns(thrd) && !ns)
1194 dev_info(thrd->dmac->pinfo->dev, "%s:%d Recipe for ABORT!\n",
1195 __func__, __LINE__);
1196
1197 go.chan = thrd->id;
1198 go.addr = req->mc_bus;
1199 go.ns = ns;
1200 _emit_GO(0, insn, &go);
1201
1202 /* Set to generate interrupts for SEV */
1203 writel(readl(regs + INTEN) | (1 << thrd->ev), regs + INTEN);
1204
1205 /* Only manager can execute GO */
1206 _execute_DBGINSN(thrd, insn, true);
1207
1208 thrd->req_running = idx;
1209
1210 return true;
1211}
1212
1213static bool _start(struct pl330_thread *thrd)
1214{
1215 switch (_state(thrd)) {
1216 case PL330_STATE_FAULT_COMPLETING:
1217 UNTIL(thrd, PL330_STATE_FAULTING | PL330_STATE_KILLING);
1218
1219 if (_state(thrd) == PL330_STATE_KILLING)
1220 UNTIL(thrd, PL330_STATE_STOPPED)
1221
1222 case PL330_STATE_FAULTING:
1223 _stop(thrd);
1224
1225 case PL330_STATE_KILLING:
1226 case PL330_STATE_COMPLETING:
1227 UNTIL(thrd, PL330_STATE_STOPPED)
1228
1229 case PL330_STATE_STOPPED:
1230 return _trigger(thrd);
1231
1232 case PL330_STATE_WFP:
1233 case PL330_STATE_QUEUEBUSY:
1234 case PL330_STATE_ATBARRIER:
1235 case PL330_STATE_UPDTPC:
1236 case PL330_STATE_CACHEMISS:
1237 case PL330_STATE_EXECUTING:
1238 return true;
1239
1240 case PL330_STATE_WFE: /* For RESUME, nothing yet */
1241 default:
1242 return false;
1243 }
1244}
1245
1246static inline int _ldst_memtomem(unsigned dry_run, u8 buf[],
1247 const struct _xfer_spec *pxs, int cyc)
1248{
1249 int off = 0;
Boojin Kim3ecf51a2011-12-26 18:55:47 +09001250 struct pl330_config *pcfg = pxs->r->cfg->pcfg;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001251
Boojin Kim3ecf51a2011-12-26 18:55:47 +09001252 /* check lock-up free version */
1253 if (get_revision(pcfg->periph_id) >= PERIPH_REV_R1P0) {
1254 while (cyc--) {
1255 off += _emit_LD(dry_run, &buf[off], ALWAYS);
1256 off += _emit_ST(dry_run, &buf[off], ALWAYS);
1257 }
1258 } else {
1259 while (cyc--) {
1260 off += _emit_LD(dry_run, &buf[off], ALWAYS);
1261 off += _emit_RMB(dry_run, &buf[off]);
1262 off += _emit_ST(dry_run, &buf[off], ALWAYS);
1263 off += _emit_WMB(dry_run, &buf[off]);
1264 }
Boojin Kimb7d861d2011-12-26 18:49:52 +09001265 }
1266
1267 return off;
1268}
1269
1270static inline int _ldst_devtomem(unsigned dry_run, u8 buf[],
1271 const struct _xfer_spec *pxs, int cyc)
1272{
1273 int off = 0;
1274
1275 while (cyc--) {
1276 off += _emit_WFP(dry_run, &buf[off], SINGLE, pxs->r->peri);
1277 off += _emit_LDP(dry_run, &buf[off], SINGLE, pxs->r->peri);
1278 off += _emit_ST(dry_run, &buf[off], ALWAYS);
1279 off += _emit_FLUSHP(dry_run, &buf[off], pxs->r->peri);
1280 }
1281
1282 return off;
1283}
1284
1285static inline int _ldst_memtodev(unsigned dry_run, u8 buf[],
1286 const struct _xfer_spec *pxs, int cyc)
1287{
1288 int off = 0;
1289
1290 while (cyc--) {
1291 off += _emit_WFP(dry_run, &buf[off], SINGLE, pxs->r->peri);
1292 off += _emit_LD(dry_run, &buf[off], ALWAYS);
1293 off += _emit_STP(dry_run, &buf[off], SINGLE, pxs->r->peri);
1294 off += _emit_FLUSHP(dry_run, &buf[off], pxs->r->peri);
1295 }
1296
1297 return off;
1298}
1299
1300static int _bursts(unsigned dry_run, u8 buf[],
1301 const struct _xfer_spec *pxs, int cyc)
1302{
1303 int off = 0;
1304
1305 switch (pxs->r->rqtype) {
1306 case MEMTODEV:
1307 off += _ldst_memtodev(dry_run, &buf[off], pxs, cyc);
1308 break;
1309 case DEVTOMEM:
1310 off += _ldst_devtomem(dry_run, &buf[off], pxs, cyc);
1311 break;
1312 case MEMTOMEM:
1313 off += _ldst_memtomem(dry_run, &buf[off], pxs, cyc);
1314 break;
1315 default:
1316 off += 0x40000000; /* Scare off the Client */
1317 break;
1318 }
1319
1320 return off;
1321}
1322
1323/* Returns bytes consumed and updates bursts */
1324static inline int _loop(unsigned dry_run, u8 buf[],
1325 unsigned long *bursts, const struct _xfer_spec *pxs)
1326{
1327 int cyc, cycmax, szlp, szlpend, szbrst, off;
1328 unsigned lcnt0, lcnt1, ljmp0, ljmp1;
1329 struct _arg_LPEND lpend;
1330
1331 /* Max iterations possible in DMALP is 256 */
1332 if (*bursts >= 256*256) {
1333 lcnt1 = 256;
1334 lcnt0 = 256;
1335 cyc = *bursts / lcnt1 / lcnt0;
1336 } else if (*bursts > 256) {
1337 lcnt1 = 256;
1338 lcnt0 = *bursts / lcnt1;
1339 cyc = 1;
1340 } else {
1341 lcnt1 = *bursts;
1342 lcnt0 = 0;
1343 cyc = 1;
1344 }
1345
1346 szlp = _emit_LP(1, buf, 0, 0);
1347 szbrst = _bursts(1, buf, pxs, 1);
1348
1349 lpend.cond = ALWAYS;
1350 lpend.forever = false;
1351 lpend.loop = 0;
1352 lpend.bjump = 0;
1353 szlpend = _emit_LPEND(1, buf, &lpend);
1354
1355 if (lcnt0) {
1356 szlp *= 2;
1357 szlpend *= 2;
1358 }
1359
1360 /*
1361 * Max bursts that we can unroll due to limit on the
1362 * size of backward jump that can be encoded in DMALPEND
1363 * which is 8-bits and hence 255
1364 */
1365 cycmax = (255 - (szlp + szlpend)) / szbrst;
1366
1367 cyc = (cycmax < cyc) ? cycmax : cyc;
1368
1369 off = 0;
1370
1371 if (lcnt0) {
1372 off += _emit_LP(dry_run, &buf[off], 0, lcnt0);
1373 ljmp0 = off;
1374 }
1375
1376 off += _emit_LP(dry_run, &buf[off], 1, lcnt1);
1377 ljmp1 = off;
1378
1379 off += _bursts(dry_run, &buf[off], pxs, cyc);
1380
1381 lpend.cond = ALWAYS;
1382 lpend.forever = false;
1383 lpend.loop = 1;
1384 lpend.bjump = off - ljmp1;
1385 off += _emit_LPEND(dry_run, &buf[off], &lpend);
1386
1387 if (lcnt0) {
1388 lpend.cond = ALWAYS;
1389 lpend.forever = false;
1390 lpend.loop = 0;
1391 lpend.bjump = off - ljmp0;
1392 off += _emit_LPEND(dry_run, &buf[off], &lpend);
1393 }
1394
1395 *bursts = lcnt1 * cyc;
1396 if (lcnt0)
1397 *bursts *= lcnt0;
1398
1399 return off;
1400}
1401
1402static inline int _setup_loops(unsigned dry_run, u8 buf[],
1403 const struct _xfer_spec *pxs)
1404{
1405 struct pl330_xfer *x = pxs->x;
1406 u32 ccr = pxs->ccr;
1407 unsigned long c, bursts = BYTE_TO_BURST(x->bytes, ccr);
1408 int off = 0;
1409
1410 while (bursts) {
1411 c = bursts;
1412 off += _loop(dry_run, &buf[off], &c, pxs);
1413 bursts -= c;
1414 }
1415
1416 return off;
1417}
1418
1419static inline int _setup_xfer(unsigned dry_run, u8 buf[],
1420 const struct _xfer_spec *pxs)
1421{
1422 struct pl330_xfer *x = pxs->x;
1423 int off = 0;
1424
1425 /* DMAMOV SAR, x->src_addr */
1426 off += _emit_MOV(dry_run, &buf[off], SAR, x->src_addr);
1427 /* DMAMOV DAR, x->dst_addr */
1428 off += _emit_MOV(dry_run, &buf[off], DAR, x->dst_addr);
1429
1430 /* Setup Loop(s) */
1431 off += _setup_loops(dry_run, &buf[off], pxs);
1432
1433 return off;
1434}
1435
1436/*
1437 * A req is a sequence of one or more xfer units.
1438 * Returns the number of bytes taken to setup the MC for the req.
1439 */
1440static int _setup_req(unsigned dry_run, struct pl330_thread *thrd,
1441 unsigned index, struct _xfer_spec *pxs)
1442{
1443 struct _pl330_req *req = &thrd->req[index];
1444 struct pl330_xfer *x;
1445 u8 *buf = req->mc_cpu;
1446 int off = 0;
1447
1448 PL330_DBGMC_START(req->mc_bus);
1449
1450 /* DMAMOV CCR, ccr */
1451 off += _emit_MOV(dry_run, &buf[off], CCR, pxs->ccr);
1452
1453 x = pxs->r->x;
1454 do {
1455 /* Error if xfer length is not aligned at burst size */
1456 if (x->bytes % (BRST_SIZE(pxs->ccr) * BRST_LEN(pxs->ccr)))
1457 return -EINVAL;
1458
1459 pxs->x = x;
1460 off += _setup_xfer(dry_run, &buf[off], pxs);
1461
1462 x = x->next;
1463 } while (x);
1464
1465 /* DMASEV peripheral/event */
1466 off += _emit_SEV(dry_run, &buf[off], thrd->ev);
1467 /* DMAEND */
1468 off += _emit_END(dry_run, &buf[off]);
1469
1470 return off;
1471}
1472
1473static inline u32 _prepare_ccr(const struct pl330_reqcfg *rqc)
1474{
1475 u32 ccr = 0;
1476
1477 if (rqc->src_inc)
1478 ccr |= CC_SRCINC;
1479
1480 if (rqc->dst_inc)
1481 ccr |= CC_DSTINC;
1482
1483 /* We set same protection levels for Src and DST for now */
1484 if (rqc->privileged)
1485 ccr |= CC_SRCPRI | CC_DSTPRI;
1486 if (rqc->nonsecure)
1487 ccr |= CC_SRCNS | CC_DSTNS;
1488 if (rqc->insnaccess)
1489 ccr |= CC_SRCIA | CC_DSTIA;
1490
1491 ccr |= (((rqc->brst_len - 1) & 0xf) << CC_SRCBRSTLEN_SHFT);
1492 ccr |= (((rqc->brst_len - 1) & 0xf) << CC_DSTBRSTLEN_SHFT);
1493
1494 ccr |= (rqc->brst_size << CC_SRCBRSTSIZE_SHFT);
1495 ccr |= (rqc->brst_size << CC_DSTBRSTSIZE_SHFT);
1496
1497 ccr |= (rqc->scctl << CC_SRCCCTRL_SHFT);
1498 ccr |= (rqc->dcctl << CC_DSTCCTRL_SHFT);
1499
1500 ccr |= (rqc->swap << CC_SWAP_SHFT);
1501
1502 return ccr;
1503}
1504
1505static inline bool _is_valid(u32 ccr)
1506{
1507 enum pl330_dstcachectrl dcctl;
1508 enum pl330_srccachectrl scctl;
1509
1510 dcctl = (ccr >> CC_DSTCCTRL_SHFT) & CC_DRCCCTRL_MASK;
1511 scctl = (ccr >> CC_SRCCCTRL_SHFT) & CC_SRCCCTRL_MASK;
1512
1513 if (dcctl == DINVALID1 || dcctl == DINVALID2
1514 || scctl == SINVALID1 || scctl == SINVALID2)
1515 return false;
1516 else
1517 return true;
1518}
1519
1520/*
1521 * Submit a list of xfers after which the client wants notification.
1522 * Client is not notified after each xfer unit, just once after all
1523 * xfer units are done or some error occurs.
1524 */
1525static int pl330_submit_req(void *ch_id, struct pl330_req *r)
1526{
1527 struct pl330_thread *thrd = ch_id;
1528 struct pl330_dmac *pl330;
1529 struct pl330_info *pi;
1530 struct _xfer_spec xs;
1531 unsigned long flags;
1532 void __iomem *regs;
1533 unsigned idx;
1534 u32 ccr;
1535 int ret = 0;
1536
1537 /* No Req or Unacquired Channel or DMAC */
1538 if (!r || !thrd || thrd->free)
1539 return -EINVAL;
1540
1541 pl330 = thrd->dmac;
1542 pi = pl330->pinfo;
1543 regs = pi->base;
1544
1545 if (pl330->state == DYING
1546 || pl330->dmac_tbd.reset_chan & (1 << thrd->id)) {
1547 dev_info(thrd->dmac->pinfo->dev, "%s:%d\n",
1548 __func__, __LINE__);
1549 return -EAGAIN;
1550 }
1551
1552 /* If request for non-existing peripheral */
1553 if (r->rqtype != MEMTOMEM && r->peri >= pi->pcfg.num_peri) {
1554 dev_info(thrd->dmac->pinfo->dev,
1555 "%s:%d Invalid peripheral(%u)!\n",
1556 __func__, __LINE__, r->peri);
1557 return -EINVAL;
1558 }
1559
1560 spin_lock_irqsave(&pl330->lock, flags);
1561
1562 if (_queue_full(thrd)) {
1563 ret = -EAGAIN;
1564 goto xfer_exit;
1565 }
1566
Boojin Kimb7d861d2011-12-26 18:49:52 +09001567
1568 /* Use last settings, if not provided */
Sachin Kamat2e2c6822012-09-17 15:20:22 +05301569 if (r->cfg) {
1570 /* Prefer Secure Channel */
1571 if (!_manager_ns(thrd))
1572 r->cfg->nonsecure = 0;
1573 else
1574 r->cfg->nonsecure = 1;
1575
Boojin Kimb7d861d2011-12-26 18:49:52 +09001576 ccr = _prepare_ccr(r->cfg);
Sachin Kamat2e2c6822012-09-17 15:20:22 +05301577 } else {
Boojin Kimb7d861d2011-12-26 18:49:52 +09001578 ccr = readl(regs + CC(thrd->id));
Sachin Kamat2e2c6822012-09-17 15:20:22 +05301579 }
Boojin Kimb7d861d2011-12-26 18:49:52 +09001580
1581 /* If this req doesn't have valid xfer settings */
1582 if (!_is_valid(ccr)) {
1583 ret = -EINVAL;
1584 dev_info(thrd->dmac->pinfo->dev, "%s:%d Invalid CCR(%x)!\n",
1585 __func__, __LINE__, ccr);
1586 goto xfer_exit;
1587 }
1588
1589 idx = IS_FREE(&thrd->req[0]) ? 0 : 1;
1590
1591 xs.ccr = ccr;
1592 xs.r = r;
1593
1594 /* First dry run to check if req is acceptable */
1595 ret = _setup_req(1, thrd, idx, &xs);
1596 if (ret < 0)
1597 goto xfer_exit;
1598
1599 if (ret > pi->mcbufsz / 2) {
1600 dev_info(thrd->dmac->pinfo->dev,
1601 "%s:%d Trying increasing mcbufsz\n",
1602 __func__, __LINE__);
1603 ret = -ENOMEM;
1604 goto xfer_exit;
1605 }
1606
1607 /* Hook the request */
1608 thrd->lstenq = idx;
1609 thrd->req[idx].mc_len = _setup_req(0, thrd, idx, &xs);
1610 thrd->req[idx].r = r;
1611
1612 ret = 0;
1613
1614xfer_exit:
1615 spin_unlock_irqrestore(&pl330->lock, flags);
1616
1617 return ret;
1618}
1619
1620static void pl330_dotask(unsigned long data)
1621{
1622 struct pl330_dmac *pl330 = (struct pl330_dmac *) data;
1623 struct pl330_info *pi = pl330->pinfo;
1624 unsigned long flags;
1625 int i;
1626
1627 spin_lock_irqsave(&pl330->lock, flags);
1628
1629 /* The DMAC itself gone nuts */
1630 if (pl330->dmac_tbd.reset_dmac) {
1631 pl330->state = DYING;
1632 /* Reset the manager too */
1633 pl330->dmac_tbd.reset_mngr = true;
1634 /* Clear the reset flag */
1635 pl330->dmac_tbd.reset_dmac = false;
1636 }
1637
1638 if (pl330->dmac_tbd.reset_mngr) {
1639 _stop(pl330->manager);
1640 /* Reset all channels */
1641 pl330->dmac_tbd.reset_chan = (1 << pi->pcfg.num_chan) - 1;
1642 /* Clear the reset flag */
1643 pl330->dmac_tbd.reset_mngr = false;
1644 }
1645
1646 for (i = 0; i < pi->pcfg.num_chan; i++) {
1647
1648 if (pl330->dmac_tbd.reset_chan & (1 << i)) {
1649 struct pl330_thread *thrd = &pl330->channels[i];
1650 void __iomem *regs = pi->base;
1651 enum pl330_op_err err;
1652
1653 _stop(thrd);
1654
1655 if (readl(regs + FSC) & (1 << thrd->id))
1656 err = PL330_ERR_FAIL;
1657 else
1658 err = PL330_ERR_ABORT;
1659
1660 spin_unlock_irqrestore(&pl330->lock, flags);
1661
1662 _callback(thrd->req[1 - thrd->lstenq].r, err);
1663 _callback(thrd->req[thrd->lstenq].r, err);
1664
1665 spin_lock_irqsave(&pl330->lock, flags);
1666
1667 thrd->req[0].r = NULL;
1668 thrd->req[1].r = NULL;
1669 mark_free(thrd, 0);
1670 mark_free(thrd, 1);
1671
1672 /* Clear the reset flag */
1673 pl330->dmac_tbd.reset_chan &= ~(1 << i);
1674 }
1675 }
1676
1677 spin_unlock_irqrestore(&pl330->lock, flags);
1678
1679 return;
1680}
1681
1682/* Returns 1 if state was updated, 0 otherwise */
1683static int pl330_update(const struct pl330_info *pi)
1684{
Javi Merinofdec53d2012-06-13 15:07:00 +01001685 struct pl330_req *rqdone, *tmp;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001686 struct pl330_dmac *pl330;
1687 unsigned long flags;
1688 void __iomem *regs;
1689 u32 val;
1690 int id, ev, ret = 0;
1691
1692 if (!pi || !pi->pl330_data)
1693 return 0;
1694
1695 regs = pi->base;
1696 pl330 = pi->pl330_data;
1697
1698 spin_lock_irqsave(&pl330->lock, flags);
1699
1700 val = readl(regs + FSM) & 0x1;
1701 if (val)
1702 pl330->dmac_tbd.reset_mngr = true;
1703 else
1704 pl330->dmac_tbd.reset_mngr = false;
1705
1706 val = readl(regs + FSC) & ((1 << pi->pcfg.num_chan) - 1);
1707 pl330->dmac_tbd.reset_chan |= val;
1708 if (val) {
1709 int i = 0;
1710 while (i < pi->pcfg.num_chan) {
1711 if (val & (1 << i)) {
1712 dev_info(pi->dev,
1713 "Reset Channel-%d\t CS-%x FTC-%x\n",
1714 i, readl(regs + CS(i)),
1715 readl(regs + FTC(i)));
1716 _stop(&pl330->channels[i]);
1717 }
1718 i++;
1719 }
1720 }
1721
1722 /* Check which event happened i.e, thread notified */
1723 val = readl(regs + ES);
1724 if (pi->pcfg.num_events < 32
1725 && val & ~((1 << pi->pcfg.num_events) - 1)) {
1726 pl330->dmac_tbd.reset_dmac = true;
1727 dev_err(pi->dev, "%s:%d Unexpected!\n", __func__, __LINE__);
1728 ret = 1;
1729 goto updt_exit;
1730 }
1731
1732 for (ev = 0; ev < pi->pcfg.num_events; ev++) {
1733 if (val & (1 << ev)) { /* Event occurred */
1734 struct pl330_thread *thrd;
1735 u32 inten = readl(regs + INTEN);
1736 int active;
1737
1738 /* Clear the event */
1739 if (inten & (1 << ev))
1740 writel(1 << ev, regs + INTCLR);
1741
1742 ret = 1;
1743
1744 id = pl330->events[ev];
1745
1746 thrd = &pl330->channels[id];
1747
1748 active = thrd->req_running;
1749 if (active == -1) /* Aborted */
1750 continue;
1751
Javi Merinofdec53d2012-06-13 15:07:00 +01001752 /* Detach the req */
1753 rqdone = thrd->req[active].r;
1754 thrd->req[active].r = NULL;
1755
Boojin Kimb7d861d2011-12-26 18:49:52 +09001756 mark_free(thrd, active);
1757
1758 /* Get going again ASAP */
1759 _start(thrd);
1760
1761 /* For now, just make a list of callbacks to be done */
1762 list_add_tail(&rqdone->rqd, &pl330->req_done);
1763 }
1764 }
1765
1766 /* Now that we are in no hurry, do the callbacks */
Javi Merinofdec53d2012-06-13 15:07:00 +01001767 list_for_each_entry_safe(rqdone, tmp, &pl330->req_done, rqd) {
1768 list_del(&rqdone->rqd);
Boojin Kimb7d861d2011-12-26 18:49:52 +09001769
1770 spin_unlock_irqrestore(&pl330->lock, flags);
Javi Merinofdec53d2012-06-13 15:07:00 +01001771 _callback(rqdone, PL330_ERR_NONE);
Boojin Kimb7d861d2011-12-26 18:49:52 +09001772 spin_lock_irqsave(&pl330->lock, flags);
1773 }
1774
1775updt_exit:
1776 spin_unlock_irqrestore(&pl330->lock, flags);
1777
1778 if (pl330->dmac_tbd.reset_dmac
1779 || pl330->dmac_tbd.reset_mngr
1780 || pl330->dmac_tbd.reset_chan) {
1781 ret = 1;
1782 tasklet_schedule(&pl330->tasks);
1783 }
1784
1785 return ret;
1786}
1787
1788static int pl330_chan_ctrl(void *ch_id, enum pl330_chan_op op)
1789{
1790 struct pl330_thread *thrd = ch_id;
1791 struct pl330_dmac *pl330;
1792 unsigned long flags;
Linus Torvaldsef08e782012-03-29 15:34:57 -07001793 int ret = 0, active;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001794
1795 if (!thrd || thrd->free || thrd->dmac->state == DYING)
1796 return -EINVAL;
1797
1798 pl330 = thrd->dmac;
Linus Torvaldsef08e782012-03-29 15:34:57 -07001799 active = thrd->req_running;
Boojin Kimb7d861d2011-12-26 18:49:52 +09001800
1801 spin_lock_irqsave(&pl330->lock, flags);
1802
1803 switch (op) {
1804 case PL330_OP_FLUSH:
1805 /* Make sure the channel is stopped */
1806 _stop(thrd);
1807
1808 thrd->req[0].r = NULL;
1809 thrd->req[1].r = NULL;
1810 mark_free(thrd, 0);
1811 mark_free(thrd, 1);
1812 break;
1813
1814 case PL330_OP_ABORT:
1815 /* Make sure the channel is stopped */
1816 _stop(thrd);
1817
1818 /* ABORT is only for the active req */
1819 if (active == -1)
1820 break;
1821
1822 thrd->req[active].r = NULL;
1823 mark_free(thrd, active);
1824
1825 /* Start the next */
1826 case PL330_OP_START:
1827 if ((active == -1) && !_start(thrd))
1828 ret = -EIO;
1829 break;
1830
1831 default:
1832 ret = -EINVAL;
1833 }
1834
1835 spin_unlock_irqrestore(&pl330->lock, flags);
1836 return ret;
1837}
1838
Boojin Kimb7d861d2011-12-26 18:49:52 +09001839/* Reserve an event */
1840static inline int _alloc_event(struct pl330_thread *thrd)
1841{
1842 struct pl330_dmac *pl330 = thrd->dmac;
1843 struct pl330_info *pi = pl330->pinfo;
1844 int ev;
1845
1846 for (ev = 0; ev < pi->pcfg.num_events; ev++)
1847 if (pl330->events[ev] == -1) {
1848 pl330->events[ev] = thrd->id;
1849 return ev;
1850 }
1851
1852 return -1;
1853}
1854
1855static bool _chan_ns(const struct pl330_info *pi, int i)
1856{
1857 return pi->pcfg.irq_ns & (1 << i);
1858}
1859
1860/* Upon success, returns IdentityToken for the
1861 * allocated channel, NULL otherwise.
1862 */
1863static void *pl330_request_channel(const struct pl330_info *pi)
1864{
1865 struct pl330_thread *thrd = NULL;
1866 struct pl330_dmac *pl330;
1867 unsigned long flags;
1868 int chans, i;
1869
1870 if (!pi || !pi->pl330_data)
1871 return NULL;
1872
1873 pl330 = pi->pl330_data;
1874
1875 if (pl330->state == DYING)
1876 return NULL;
1877
1878 chans = pi->pcfg.num_chan;
1879
1880 spin_lock_irqsave(&pl330->lock, flags);
1881
1882 for (i = 0; i < chans; i++) {
1883 thrd = &pl330->channels[i];
1884 if ((thrd->free) && (!_manager_ns(thrd) ||
1885 _chan_ns(pi, i))) {
1886 thrd->ev = _alloc_event(thrd);
1887 if (thrd->ev >= 0) {
1888 thrd->free = false;
1889 thrd->lstenq = 1;
1890 thrd->req[0].r = NULL;
1891 mark_free(thrd, 0);
1892 thrd->req[1].r = NULL;
1893 mark_free(thrd, 1);
1894 break;
1895 }
1896 }
1897 thrd = NULL;
1898 }
1899
1900 spin_unlock_irqrestore(&pl330->lock, flags);
1901
1902 return thrd;
1903}
1904
1905/* Release an event */
1906static inline void _free_event(struct pl330_thread *thrd, int ev)
1907{
1908 struct pl330_dmac *pl330 = thrd->dmac;
1909 struct pl330_info *pi = pl330->pinfo;
1910
1911 /* If the event is valid and was held by the thread */
1912 if (ev >= 0 && ev < pi->pcfg.num_events
1913 && pl330->events[ev] == thrd->id)
1914 pl330->events[ev] = -1;
1915}
1916
1917static void pl330_release_channel(void *ch_id)
1918{
1919 struct pl330_thread *thrd = ch_id;
1920 struct pl330_dmac *pl330;
1921 unsigned long flags;
1922
1923 if (!thrd || thrd->free)
1924 return;
1925
1926 _stop(thrd);
1927
1928 _callback(thrd->req[1 - thrd->lstenq].r, PL330_ERR_ABORT);
1929 _callback(thrd->req[thrd->lstenq].r, PL330_ERR_ABORT);
1930
1931 pl330 = thrd->dmac;
1932
1933 spin_lock_irqsave(&pl330->lock, flags);
1934 _free_event(thrd, thrd->ev);
1935 thrd->free = true;
1936 spin_unlock_irqrestore(&pl330->lock, flags);
1937}
1938
1939/* Initialize the structure for PL330 configuration, that can be used
1940 * by the client driver the make best use of the DMAC
1941 */
1942static void read_dmac_config(struct pl330_info *pi)
1943{
1944 void __iomem *regs = pi->base;
1945 u32 val;
1946
1947 val = readl(regs + CRD) >> CRD_DATA_WIDTH_SHIFT;
1948 val &= CRD_DATA_WIDTH_MASK;
1949 pi->pcfg.data_bus_width = 8 * (1 << val);
1950
1951 val = readl(regs + CRD) >> CRD_DATA_BUFF_SHIFT;
1952 val &= CRD_DATA_BUFF_MASK;
1953 pi->pcfg.data_buf_dep = val + 1;
1954
1955 val = readl(regs + CR0) >> CR0_NUM_CHANS_SHIFT;
1956 val &= CR0_NUM_CHANS_MASK;
1957 val += 1;
1958 pi->pcfg.num_chan = val;
1959
1960 val = readl(regs + CR0);
1961 if (val & CR0_PERIPH_REQ_SET) {
1962 val = (val >> CR0_NUM_PERIPH_SHIFT) & CR0_NUM_PERIPH_MASK;
1963 val += 1;
1964 pi->pcfg.num_peri = val;
1965 pi->pcfg.peri_ns = readl(regs + CR4);
1966 } else {
1967 pi->pcfg.num_peri = 0;
1968 }
1969
1970 val = readl(regs + CR0);
1971 if (val & CR0_BOOT_MAN_NS)
1972 pi->pcfg.mode |= DMAC_MODE_NS;
1973 else
1974 pi->pcfg.mode &= ~DMAC_MODE_NS;
1975
1976 val = readl(regs + CR0) >> CR0_NUM_EVENTS_SHIFT;
1977 val &= CR0_NUM_EVENTS_MASK;
1978 val += 1;
1979 pi->pcfg.num_events = val;
1980
1981 pi->pcfg.irq_ns = readl(regs + CR3);
1982
1983 pi->pcfg.periph_id = get_id(pi, PERIPH_ID);
1984 pi->pcfg.pcell_id = get_id(pi, PCELL_ID);
1985}
1986
1987static inline void _reset_thread(struct pl330_thread *thrd)
1988{
1989 struct pl330_dmac *pl330 = thrd->dmac;
1990 struct pl330_info *pi = pl330->pinfo;
1991
1992 thrd->req[0].mc_cpu = pl330->mcode_cpu
1993 + (thrd->id * pi->mcbufsz);
1994 thrd->req[0].mc_bus = pl330->mcode_bus
1995 + (thrd->id * pi->mcbufsz);
1996 thrd->req[0].r = NULL;
1997 mark_free(thrd, 0);
1998
1999 thrd->req[1].mc_cpu = thrd->req[0].mc_cpu
2000 + pi->mcbufsz / 2;
2001 thrd->req[1].mc_bus = thrd->req[0].mc_bus
2002 + pi->mcbufsz / 2;
2003 thrd->req[1].r = NULL;
2004 mark_free(thrd, 1);
2005}
2006
2007static int dmac_alloc_threads(struct pl330_dmac *pl330)
2008{
2009 struct pl330_info *pi = pl330->pinfo;
2010 int chans = pi->pcfg.num_chan;
2011 struct pl330_thread *thrd;
2012 int i;
2013
2014 /* Allocate 1 Manager and 'chans' Channel threads */
2015 pl330->channels = kzalloc((1 + chans) * sizeof(*thrd),
2016 GFP_KERNEL);
2017 if (!pl330->channels)
2018 return -ENOMEM;
2019
2020 /* Init Channel threads */
2021 for (i = 0; i < chans; i++) {
2022 thrd = &pl330->channels[i];
2023 thrd->id = i;
2024 thrd->dmac = pl330;
2025 _reset_thread(thrd);
2026 thrd->free = true;
2027 }
2028
2029 /* MANAGER is indexed at the end */
2030 thrd = &pl330->channels[chans];
2031 thrd->id = chans;
2032 thrd->dmac = pl330;
2033 thrd->free = false;
2034 pl330->manager = thrd;
2035
2036 return 0;
2037}
2038
2039static int dmac_alloc_resources(struct pl330_dmac *pl330)
2040{
2041 struct pl330_info *pi = pl330->pinfo;
2042 int chans = pi->pcfg.num_chan;
2043 int ret;
2044
2045 /*
2046 * Alloc MicroCode buffer for 'chans' Channel threads.
2047 * A channel's buffer offset is (Channel_Id * MCODE_BUFF_PERCHAN)
2048 */
2049 pl330->mcode_cpu = dma_alloc_coherent(pi->dev,
2050 chans * pi->mcbufsz,
2051 &pl330->mcode_bus, GFP_KERNEL);
2052 if (!pl330->mcode_cpu) {
2053 dev_err(pi->dev, "%s:%d Can't allocate memory!\n",
2054 __func__, __LINE__);
2055 return -ENOMEM;
2056 }
2057
2058 ret = dmac_alloc_threads(pl330);
2059 if (ret) {
2060 dev_err(pi->dev, "%s:%d Can't to create channels for DMAC!\n",
2061 __func__, __LINE__);
2062 dma_free_coherent(pi->dev,
2063 chans * pi->mcbufsz,
2064 pl330->mcode_cpu, pl330->mcode_bus);
2065 return ret;
2066 }
2067
2068 return 0;
2069}
2070
2071static int pl330_add(struct pl330_info *pi)
2072{
2073 struct pl330_dmac *pl330;
2074 void __iomem *regs;
2075 int i, ret;
2076
2077 if (!pi || !pi->dev)
2078 return -EINVAL;
2079
2080 /* If already added */
2081 if (pi->pl330_data)
2082 return -EINVAL;
2083
2084 /*
2085 * If the SoC can perform reset on the DMAC, then do it
2086 * before reading its configuration.
2087 */
2088 if (pi->dmac_reset)
2089 pi->dmac_reset(pi);
2090
2091 regs = pi->base;
2092
2093 /* Check if we can handle this DMAC */
2094 if ((get_id(pi, PERIPH_ID) & 0xfffff) != PERIPH_ID_VAL
2095 || get_id(pi, PCELL_ID) != PCELL_ID_VAL) {
2096 dev_err(pi->dev, "PERIPH_ID 0x%x, PCELL_ID 0x%x !\n",
2097 get_id(pi, PERIPH_ID), get_id(pi, PCELL_ID));
2098 return -EINVAL;
2099 }
2100
2101 /* Read the configuration of the DMAC */
2102 read_dmac_config(pi);
2103
2104 if (pi->pcfg.num_events == 0) {
2105 dev_err(pi->dev, "%s:%d Can't work without events!\n",
2106 __func__, __LINE__);
2107 return -EINVAL;
2108 }
2109
2110 pl330 = kzalloc(sizeof(*pl330), GFP_KERNEL);
2111 if (!pl330) {
2112 dev_err(pi->dev, "%s:%d Can't allocate memory!\n",
2113 __func__, __LINE__);
2114 return -ENOMEM;
2115 }
2116
2117 /* Assign the info structure and private data */
2118 pl330->pinfo = pi;
2119 pi->pl330_data = pl330;
2120
2121 spin_lock_init(&pl330->lock);
2122
2123 INIT_LIST_HEAD(&pl330->req_done);
2124
2125 /* Use default MC buffer size if not provided */
2126 if (!pi->mcbufsz)
2127 pi->mcbufsz = MCODE_BUFF_PER_REQ * 2;
2128
2129 /* Mark all events as free */
2130 for (i = 0; i < pi->pcfg.num_events; i++)
2131 pl330->events[i] = -1;
2132
2133 /* Allocate resources needed by the DMAC */
2134 ret = dmac_alloc_resources(pl330);
2135 if (ret) {
2136 dev_err(pi->dev, "Unable to create channels for DMAC\n");
2137 kfree(pl330);
2138 return ret;
2139 }
2140
2141 tasklet_init(&pl330->tasks, pl330_dotask, (unsigned long) pl330);
2142
2143 pl330->state = INIT;
2144
2145 return 0;
2146}
2147
2148static int dmac_free_threads(struct pl330_dmac *pl330)
2149{
2150 struct pl330_info *pi = pl330->pinfo;
2151 int chans = pi->pcfg.num_chan;
2152 struct pl330_thread *thrd;
2153 int i;
2154
2155 /* Release Channel threads */
2156 for (i = 0; i < chans; i++) {
2157 thrd = &pl330->channels[i];
2158 pl330_release_channel((void *)thrd);
2159 }
2160
2161 /* Free memory */
2162 kfree(pl330->channels);
2163
2164 return 0;
2165}
2166
2167static void dmac_free_resources(struct pl330_dmac *pl330)
2168{
2169 struct pl330_info *pi = pl330->pinfo;
2170 int chans = pi->pcfg.num_chan;
2171
2172 dmac_free_threads(pl330);
2173
2174 dma_free_coherent(pi->dev, chans * pi->mcbufsz,
2175 pl330->mcode_cpu, pl330->mcode_bus);
2176}
2177
2178static void pl330_del(struct pl330_info *pi)
2179{
2180 struct pl330_dmac *pl330;
2181
2182 if (!pi || !pi->pl330_data)
2183 return;
2184
2185 pl330 = pi->pl330_data;
2186
2187 pl330->state = UNINIT;
2188
2189 tasklet_kill(&pl330->tasks);
2190
2191 /* Free DMAC resources */
2192 dmac_free_resources(pl330);
2193
2194 kfree(pl330);
2195 pi->pl330_data = NULL;
2196}
2197
Thomas Abraham3e2ec132011-10-24 11:43:02 +02002198/* forward declaration */
2199static struct amba_driver pl330_driver;
2200
Jassi Brarb3040e42010-05-23 20:28:19 -07002201static inline struct dma_pl330_chan *
2202to_pchan(struct dma_chan *ch)
2203{
2204 if (!ch)
2205 return NULL;
2206
2207 return container_of(ch, struct dma_pl330_chan, chan);
2208}
2209
2210static inline struct dma_pl330_desc *
2211to_desc(struct dma_async_tx_descriptor *tx)
2212{
2213 return container_of(tx, struct dma_pl330_desc, txd);
2214}
2215
2216static inline void free_desc_list(struct list_head *list)
2217{
2218 struct dma_pl330_dmac *pdmac;
2219 struct dma_pl330_desc *desc;
Olof Johanssonc8473822012-04-08 16:26:19 -07002220 struct dma_pl330_chan *pch = NULL;
Jassi Brarb3040e42010-05-23 20:28:19 -07002221 unsigned long flags;
2222
Jassi Brarb3040e42010-05-23 20:28:19 -07002223 /* Finish off the work list */
2224 list_for_each_entry(desc, list, node) {
2225 dma_async_tx_callback callback;
2226 void *param;
2227
2228 /* All desc in a list belong to same channel */
2229 pch = desc->pchan;
2230 callback = desc->txd.callback;
2231 param = desc->txd.callback_param;
2232
2233 if (callback)
2234 callback(param);
2235
2236 desc->pchan = NULL;
2237 }
2238
Olof Johanssonc8473822012-04-08 16:26:19 -07002239 /* pch will be unset if list was empty */
2240 if (!pch)
2241 return;
2242
Jassi Brarb3040e42010-05-23 20:28:19 -07002243 pdmac = pch->dmac;
2244
2245 spin_lock_irqsave(&pdmac->pool_lock, flags);
2246 list_splice_tail_init(list, &pdmac->desc_pool);
2247 spin_unlock_irqrestore(&pdmac->pool_lock, flags);
2248}
2249
Boojin Kim42bc9cf2011-09-02 09:44:33 +09002250static inline void handle_cyclic_desc_list(struct list_head *list)
2251{
2252 struct dma_pl330_desc *desc;
Olof Johanssonc8473822012-04-08 16:26:19 -07002253 struct dma_pl330_chan *pch = NULL;
Boojin Kim42bc9cf2011-09-02 09:44:33 +09002254 unsigned long flags;
2255
Boojin Kim42bc9cf2011-09-02 09:44:33 +09002256 list_for_each_entry(desc, list, node) {
2257 dma_async_tx_callback callback;
2258
2259 /* Change status to reload it */
2260 desc->status = PREP;
2261 pch = desc->pchan;
2262 callback = desc->txd.callback;
2263 if (callback)
2264 callback(desc->txd.callback_param);
2265 }
2266
Olof Johanssonc8473822012-04-08 16:26:19 -07002267 /* pch will be unset if list was empty */
2268 if (!pch)
2269 return;
2270
Boojin Kim42bc9cf2011-09-02 09:44:33 +09002271 spin_lock_irqsave(&pch->lock, flags);
2272 list_splice_tail_init(list, &pch->work_list);
2273 spin_unlock_irqrestore(&pch->lock, flags);
2274}
2275
Jassi Brarb3040e42010-05-23 20:28:19 -07002276static inline void fill_queue(struct dma_pl330_chan *pch)
2277{
2278 struct dma_pl330_desc *desc;
2279 int ret;
2280
2281 list_for_each_entry(desc, &pch->work_list, node) {
2282
2283 /* If already submitted */
2284 if (desc->status == BUSY)
2285 break;
2286
2287 ret = pl330_submit_req(pch->pl330_chid,
2288 &desc->req);
2289 if (!ret) {
2290 desc->status = BUSY;
2291 break;
2292 } else if (ret == -EAGAIN) {
2293 /* QFull or DMAC Dying */
2294 break;
2295 } else {
2296 /* Unacceptable request */
2297 desc->status = DONE;
2298 dev_err(pch->dmac->pif.dev, "%s:%d Bad Desc(%d)\n",
2299 __func__, __LINE__, desc->txd.cookie);
2300 tasklet_schedule(&pch->task);
2301 }
2302 }
2303}
2304
2305static void pl330_tasklet(unsigned long data)
2306{
2307 struct dma_pl330_chan *pch = (struct dma_pl330_chan *)data;
2308 struct dma_pl330_desc *desc, *_dt;
2309 unsigned long flags;
2310 LIST_HEAD(list);
2311
2312 spin_lock_irqsave(&pch->lock, flags);
2313
2314 /* Pick up ripe tomatoes */
2315 list_for_each_entry_safe(desc, _dt, &pch->work_list, node)
2316 if (desc->status == DONE) {
Tushar Behera30c1dc02012-05-23 16:47:31 +05302317 if (!pch->cyclic)
Vinod Kouleab21582012-05-11 11:24:41 +05302318 dma_cookie_complete(&desc->txd);
Jassi Brarb3040e42010-05-23 20:28:19 -07002319 list_move_tail(&desc->node, &list);
2320 }
2321
2322 /* Try to submit a req imm. next to the last completed cookie */
2323 fill_queue(pch);
2324
2325 /* Make sure the PL330 Channel thread is active */
2326 pl330_chan_ctrl(pch->pl330_chid, PL330_OP_START);
2327
2328 spin_unlock_irqrestore(&pch->lock, flags);
2329
Boojin Kim42bc9cf2011-09-02 09:44:33 +09002330 if (pch->cyclic)
2331 handle_cyclic_desc_list(&list);
2332 else
2333 free_desc_list(&list);
Jassi Brarb3040e42010-05-23 20:28:19 -07002334}
2335
2336static void dma_pl330_rqcb(void *token, enum pl330_op_err err)
2337{
2338 struct dma_pl330_desc *desc = token;
2339 struct dma_pl330_chan *pch = desc->pchan;
2340 unsigned long flags;
2341
2342 /* If desc aborted */
2343 if (!pch)
2344 return;
2345
2346 spin_lock_irqsave(&pch->lock, flags);
2347
2348 desc->status = DONE;
2349
2350 spin_unlock_irqrestore(&pch->lock, flags);
2351
2352 tasklet_schedule(&pch->task);
2353}
2354
Thomas Abraham3e2ec132011-10-24 11:43:02 +02002355bool pl330_filter(struct dma_chan *chan, void *param)
2356{
Thomas Abrahamcd072512011-10-24 11:43:11 +02002357 u8 *peri_id;
Thomas Abraham3e2ec132011-10-24 11:43:02 +02002358
2359 if (chan->device->dev->driver != &pl330_driver.drv)
2360 return false;
2361
Thomas Abraham93ed5542011-10-24 11:43:31 +02002362#ifdef CONFIG_OF
2363 if (chan->device->dev->of_node) {
2364 const __be32 *prop_value;
2365 phandle phandle;
2366 struct device_node *node;
2367
2368 prop_value = ((struct property *)param)->value;
2369 phandle = be32_to_cpup(prop_value++);
2370 node = of_find_node_by_phandle(phandle);
2371 return ((chan->private == node) &&
2372 (chan->chan_id == be32_to_cpup(prop_value)));
2373 }
2374#endif
2375
Thomas Abrahamcd072512011-10-24 11:43:11 +02002376 peri_id = chan->private;
2377 return *peri_id == (unsigned)param;
Thomas Abraham3e2ec132011-10-24 11:43:02 +02002378}
2379EXPORT_SYMBOL(pl330_filter);
2380
Jassi Brarb3040e42010-05-23 20:28:19 -07002381static int pl330_alloc_chan_resources(struct dma_chan *chan)
2382{
2383 struct dma_pl330_chan *pch = to_pchan(chan);
2384 struct dma_pl330_dmac *pdmac = pch->dmac;
2385 unsigned long flags;
2386
2387 spin_lock_irqsave(&pch->lock, flags);
2388
Russell King - ARM Linuxd3ee98cdc2012-03-06 22:35:47 +00002389 dma_cookie_init(chan);
Boojin Kim42bc9cf2011-09-02 09:44:33 +09002390 pch->cyclic = false;
Jassi Brarb3040e42010-05-23 20:28:19 -07002391
2392 pch->pl330_chid = pl330_request_channel(&pdmac->pif);
2393 if (!pch->pl330_chid) {
2394 spin_unlock_irqrestore(&pch->lock, flags);
Inderpal Singh02747882012-09-17 09:57:45 +05302395 return -ENOMEM;
Jassi Brarb3040e42010-05-23 20:28:19 -07002396 }
2397
2398 tasklet_init(&pch->task, pl330_tasklet, (unsigned long) pch);
2399
2400 spin_unlock_irqrestore(&pch->lock, flags);
2401
2402 return 1;
2403}
2404
2405static int pl330_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, unsigned long arg)
2406{
2407 struct dma_pl330_chan *pch = to_pchan(chan);
Boojin Kimae43b882011-09-02 09:44:32 +09002408 struct dma_pl330_desc *desc, *_dt;
Jassi Brarb3040e42010-05-23 20:28:19 -07002409 unsigned long flags;
Boojin Kim1d0c1d62011-09-02 09:44:31 +09002410 struct dma_pl330_dmac *pdmac = pch->dmac;
2411 struct dma_slave_config *slave_config;
Boojin Kimae43b882011-09-02 09:44:32 +09002412 LIST_HEAD(list);
Jassi Brarb3040e42010-05-23 20:28:19 -07002413
Boojin Kim1d0c1d62011-09-02 09:44:31 +09002414 switch (cmd) {
2415 case DMA_TERMINATE_ALL:
2416 spin_lock_irqsave(&pch->lock, flags);
2417
2418 /* FLUSH the PL330 Channel thread */
2419 pl330_chan_ctrl(pch->pl330_chid, PL330_OP_FLUSH);
2420
2421 /* Mark all desc done */
Boojin Kimae43b882011-09-02 09:44:32 +09002422 list_for_each_entry_safe(desc, _dt, &pch->work_list , node) {
Boojin Kim1d0c1d62011-09-02 09:44:31 +09002423 desc->status = DONE;
Boojin Kimae43b882011-09-02 09:44:32 +09002424 list_move_tail(&desc->node, &list);
2425 }
Boojin Kim1d0c1d62011-09-02 09:44:31 +09002426
Boojin Kimae43b882011-09-02 09:44:32 +09002427 list_splice_tail_init(&list, &pdmac->desc_pool);
Boojin Kim1d0c1d62011-09-02 09:44:31 +09002428 spin_unlock_irqrestore(&pch->lock, flags);
Boojin Kim1d0c1d62011-09-02 09:44:31 +09002429 break;
2430 case DMA_SLAVE_CONFIG:
2431 slave_config = (struct dma_slave_config *)arg;
2432
Vinod Kouldb8196d2011-10-13 22:34:23 +05302433 if (slave_config->direction == DMA_MEM_TO_DEV) {
Boojin Kim1d0c1d62011-09-02 09:44:31 +09002434 if (slave_config->dst_addr)
2435 pch->fifo_addr = slave_config->dst_addr;
2436 if (slave_config->dst_addr_width)
2437 pch->burst_sz = __ffs(slave_config->dst_addr_width);
2438 if (slave_config->dst_maxburst)
2439 pch->burst_len = slave_config->dst_maxburst;
Vinod Kouldb8196d2011-10-13 22:34:23 +05302440 } else if (slave_config->direction == DMA_DEV_TO_MEM) {
Boojin Kim1d0c1d62011-09-02 09:44:31 +09002441 if (slave_config->src_addr)
2442 pch->fifo_addr = slave_config->src_addr;
2443 if (slave_config->src_addr_width)
2444 pch->burst_sz = __ffs(slave_config->src_addr_width);
2445 if (slave_config->src_maxburst)
2446 pch->burst_len = slave_config->src_maxburst;
2447 }
2448 break;
2449 default:
2450 dev_err(pch->dmac->pif.dev, "Not supported command.\n");
Jassi Brarb3040e42010-05-23 20:28:19 -07002451 return -ENXIO;
Boojin Kim1d0c1d62011-09-02 09:44:31 +09002452 }
Jassi Brarb3040e42010-05-23 20:28:19 -07002453
2454 return 0;
2455}
2456
2457static void pl330_free_chan_resources(struct dma_chan *chan)
2458{
2459 struct dma_pl330_chan *pch = to_pchan(chan);
2460 unsigned long flags;
2461
2462 spin_lock_irqsave(&pch->lock, flags);
2463
2464 tasklet_kill(&pch->task);
2465
2466 pl330_release_channel(pch->pl330_chid);
2467 pch->pl330_chid = NULL;
2468
Boojin Kim42bc9cf2011-09-02 09:44:33 +09002469 if (pch->cyclic)
2470 list_splice_tail_init(&pch->work_list, &pch->dmac->desc_pool);
2471
Jassi Brarb3040e42010-05-23 20:28:19 -07002472 spin_unlock_irqrestore(&pch->lock, flags);
2473}
2474
2475static enum dma_status
2476pl330_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
2477 struct dma_tx_state *txstate)
2478{
Russell King - ARM Linux96a2af42012-03-06 22:35:27 +00002479 return dma_cookie_status(chan, cookie, txstate);
Jassi Brarb3040e42010-05-23 20:28:19 -07002480}
2481
2482static void pl330_issue_pending(struct dma_chan *chan)
2483{
2484 pl330_tasklet((unsigned long) to_pchan(chan));
2485}
2486
2487/*
2488 * We returned the last one of the circular list of descriptor(s)
2489 * from prep_xxx, so the argument to submit corresponds to the last
2490 * descriptor of the list.
2491 */
2492static dma_cookie_t pl330_tx_submit(struct dma_async_tx_descriptor *tx)
2493{
2494 struct dma_pl330_desc *desc, *last = to_desc(tx);
2495 struct dma_pl330_chan *pch = to_pchan(tx->chan);
2496 dma_cookie_t cookie;
2497 unsigned long flags;
2498
2499 spin_lock_irqsave(&pch->lock, flags);
2500
2501 /* Assign cookies to all nodes */
Jassi Brarb3040e42010-05-23 20:28:19 -07002502 while (!list_empty(&last->node)) {
2503 desc = list_entry(last->node.next, struct dma_pl330_desc, node);
2504
Russell King - ARM Linux884485e2012-03-06 22:34:46 +00002505 dma_cookie_assign(&desc->txd);
Jassi Brarb3040e42010-05-23 20:28:19 -07002506
2507 list_move_tail(&desc->node, &pch->work_list);
2508 }
2509
Russell King - ARM Linux884485e2012-03-06 22:34:46 +00002510 cookie = dma_cookie_assign(&last->txd);
Jassi Brarb3040e42010-05-23 20:28:19 -07002511 list_add_tail(&last->node, &pch->work_list);
Jassi Brarb3040e42010-05-23 20:28:19 -07002512 spin_unlock_irqrestore(&pch->lock, flags);
2513
2514 return cookie;
2515}
2516
2517static inline void _init_desc(struct dma_pl330_desc *desc)
2518{
2519 desc->pchan = NULL;
2520 desc->req.x = &desc->px;
2521 desc->req.token = desc;
2522 desc->rqcfg.swap = SWAP_NO;
2523 desc->rqcfg.privileged = 0;
2524 desc->rqcfg.insnaccess = 0;
2525 desc->rqcfg.scctl = SCCTRL0;
2526 desc->rqcfg.dcctl = DCCTRL0;
2527 desc->req.cfg = &desc->rqcfg;
2528 desc->req.xfer_cb = dma_pl330_rqcb;
2529 desc->txd.tx_submit = pl330_tx_submit;
2530
2531 INIT_LIST_HEAD(&desc->node);
2532}
2533
2534/* Returns the number of descriptors added to the DMAC pool */
Sachin Kamat5a67ac52012-06-04 17:09:45 +05302535static int add_desc(struct dma_pl330_dmac *pdmac, gfp_t flg, int count)
Jassi Brarb3040e42010-05-23 20:28:19 -07002536{
2537 struct dma_pl330_desc *desc;
2538 unsigned long flags;
2539 int i;
2540
2541 if (!pdmac)
2542 return 0;
2543
2544 desc = kmalloc(count * sizeof(*desc), flg);
2545 if (!desc)
2546 return 0;
2547
2548 spin_lock_irqsave(&pdmac->pool_lock, flags);
2549
2550 for (i = 0; i < count; i++) {
2551 _init_desc(&desc[i]);
2552 list_add_tail(&desc[i].node, &pdmac->desc_pool);
2553 }
2554
2555 spin_unlock_irqrestore(&pdmac->pool_lock, flags);
2556
2557 return count;
2558}
2559
2560static struct dma_pl330_desc *
2561pluck_desc(struct dma_pl330_dmac *pdmac)
2562{
2563 struct dma_pl330_desc *desc = NULL;
2564 unsigned long flags;
2565
2566 if (!pdmac)
2567 return NULL;
2568
2569 spin_lock_irqsave(&pdmac->pool_lock, flags);
2570
2571 if (!list_empty(&pdmac->desc_pool)) {
2572 desc = list_entry(pdmac->desc_pool.next,
2573 struct dma_pl330_desc, node);
2574
2575 list_del_init(&desc->node);
2576
2577 desc->status = PREP;
2578 desc->txd.callback = NULL;
2579 }
2580
2581 spin_unlock_irqrestore(&pdmac->pool_lock, flags);
2582
2583 return desc;
2584}
2585
2586static struct dma_pl330_desc *pl330_get_desc(struct dma_pl330_chan *pch)
2587{
2588 struct dma_pl330_dmac *pdmac = pch->dmac;
Thomas Abrahamcd072512011-10-24 11:43:11 +02002589 u8 *peri_id = pch->chan.private;
Jassi Brarb3040e42010-05-23 20:28:19 -07002590 struct dma_pl330_desc *desc;
2591
2592 /* Pluck one desc from the pool of DMAC */
2593 desc = pluck_desc(pdmac);
2594
2595 /* If the DMAC pool is empty, alloc new */
2596 if (!desc) {
2597 if (!add_desc(pdmac, GFP_ATOMIC, 1))
2598 return NULL;
2599
2600 /* Try again */
2601 desc = pluck_desc(pdmac);
2602 if (!desc) {
2603 dev_err(pch->dmac->pif.dev,
2604 "%s:%d ALERT!\n", __func__, __LINE__);
2605 return NULL;
2606 }
2607 }
2608
2609 /* Initialize the descriptor */
2610 desc->pchan = pch;
2611 desc->txd.cookie = 0;
2612 async_tx_ack(&desc->txd);
2613
Thomas Abrahamcd072512011-10-24 11:43:11 +02002614 desc->req.peri = peri_id ? pch->chan.chan_id : 0;
Boojin Kim3ecf51a2011-12-26 18:55:47 +09002615 desc->rqcfg.pcfg = &pch->dmac->pif.pcfg;
Jassi Brarb3040e42010-05-23 20:28:19 -07002616
2617 dma_async_tx_descriptor_init(&desc->txd, &pch->chan);
2618
2619 return desc;
2620}
2621
2622static inline void fill_px(struct pl330_xfer *px,
2623 dma_addr_t dst, dma_addr_t src, size_t len)
2624{
2625 px->next = NULL;
2626 px->bytes = len;
2627 px->dst_addr = dst;
2628 px->src_addr = src;
2629}
2630
2631static struct dma_pl330_desc *
2632__pl330_prep_dma_memcpy(struct dma_pl330_chan *pch, dma_addr_t dst,
2633 dma_addr_t src, size_t len)
2634{
2635 struct dma_pl330_desc *desc = pl330_get_desc(pch);
2636
2637 if (!desc) {
2638 dev_err(pch->dmac->pif.dev, "%s:%d Unable to fetch desc\n",
2639 __func__, __LINE__);
2640 return NULL;
2641 }
2642
2643 /*
2644 * Ideally we should lookout for reqs bigger than
2645 * those that can be programmed with 256 bytes of
2646 * MC buffer, but considering a req size is seldom
2647 * going to be word-unaligned and more than 200MB,
2648 * we take it easy.
2649 * Also, should the limit is reached we'd rather
2650 * have the platform increase MC buffer size than
2651 * complicating this API driver.
2652 */
2653 fill_px(&desc->px, dst, src, len);
2654
2655 return desc;
2656}
2657
2658/* Call after fixing burst size */
2659static inline int get_burst_len(struct dma_pl330_desc *desc, size_t len)
2660{
2661 struct dma_pl330_chan *pch = desc->pchan;
2662 struct pl330_info *pi = &pch->dmac->pif;
2663 int burst_len;
2664
2665 burst_len = pi->pcfg.data_bus_width / 8;
2666 burst_len *= pi->pcfg.data_buf_dep;
2667 burst_len >>= desc->rqcfg.brst_size;
2668
2669 /* src/dst_burst_len can't be more than 16 */
2670 if (burst_len > 16)
2671 burst_len = 16;
2672
2673 while (burst_len > 1) {
2674 if (!(len % (burst_len << desc->rqcfg.brst_size)))
2675 break;
2676 burst_len--;
2677 }
2678
2679 return burst_len;
2680}
2681
Boojin Kim42bc9cf2011-09-02 09:44:33 +09002682static struct dma_async_tx_descriptor *pl330_prep_dma_cyclic(
2683 struct dma_chan *chan, dma_addr_t dma_addr, size_t len,
Alexandre Bounine185ecb52012-03-08 15:35:13 -05002684 size_t period_len, enum dma_transfer_direction direction,
Peter Ujfalusiec8b5e42012-09-14 15:05:47 +03002685 unsigned long flags, void *context)
Boojin Kim42bc9cf2011-09-02 09:44:33 +09002686{
2687 struct dma_pl330_desc *desc;
2688 struct dma_pl330_chan *pch = to_pchan(chan);
2689 dma_addr_t dst;
2690 dma_addr_t src;
2691
2692 desc = pl330_get_desc(pch);
2693 if (!desc) {
2694 dev_err(pch->dmac->pif.dev, "%s:%d Unable to fetch desc\n",
2695 __func__, __LINE__);
2696 return NULL;
2697 }
2698
2699 switch (direction) {
Vinod Kouldb8196d2011-10-13 22:34:23 +05302700 case DMA_MEM_TO_DEV:
Boojin Kim42bc9cf2011-09-02 09:44:33 +09002701 desc->rqcfg.src_inc = 1;
2702 desc->rqcfg.dst_inc = 0;
Thomas Abrahamcd072512011-10-24 11:43:11 +02002703 desc->req.rqtype = MEMTODEV;
Boojin Kim42bc9cf2011-09-02 09:44:33 +09002704 src = dma_addr;
2705 dst = pch->fifo_addr;
2706 break;
Vinod Kouldb8196d2011-10-13 22:34:23 +05302707 case DMA_DEV_TO_MEM:
Boojin Kim42bc9cf2011-09-02 09:44:33 +09002708 desc->rqcfg.src_inc = 0;
2709 desc->rqcfg.dst_inc = 1;
Thomas Abrahamcd072512011-10-24 11:43:11 +02002710 desc->req.rqtype = DEVTOMEM;
Boojin Kim42bc9cf2011-09-02 09:44:33 +09002711 src = pch->fifo_addr;
2712 dst = dma_addr;
2713 break;
2714 default:
2715 dev_err(pch->dmac->pif.dev, "%s:%d Invalid dma direction\n",
2716 __func__, __LINE__);
2717 return NULL;
2718 }
2719
2720 desc->rqcfg.brst_size = pch->burst_sz;
2721 desc->rqcfg.brst_len = 1;
2722
2723 pch->cyclic = true;
2724
2725 fill_px(&desc->px, dst, src, period_len);
2726
2727 return &desc->txd;
2728}
2729
Jassi Brarb3040e42010-05-23 20:28:19 -07002730static struct dma_async_tx_descriptor *
2731pl330_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dst,
2732 dma_addr_t src, size_t len, unsigned long flags)
2733{
2734 struct dma_pl330_desc *desc;
2735 struct dma_pl330_chan *pch = to_pchan(chan);
Jassi Brarb3040e42010-05-23 20:28:19 -07002736 struct pl330_info *pi;
2737 int burst;
2738
Rob Herring4e0e6102011-07-25 16:05:04 -05002739 if (unlikely(!pch || !len))
Jassi Brarb3040e42010-05-23 20:28:19 -07002740 return NULL;
2741
Jassi Brarb3040e42010-05-23 20:28:19 -07002742 pi = &pch->dmac->pif;
2743
2744 desc = __pl330_prep_dma_memcpy(pch, dst, src, len);
2745 if (!desc)
2746 return NULL;
2747
2748 desc->rqcfg.src_inc = 1;
2749 desc->rqcfg.dst_inc = 1;
Thomas Abrahamcd072512011-10-24 11:43:11 +02002750 desc->req.rqtype = MEMTOMEM;
Jassi Brarb3040e42010-05-23 20:28:19 -07002751
2752 /* Select max possible burst size */
2753 burst = pi->pcfg.data_bus_width / 8;
2754
2755 while (burst > 1) {
2756 if (!(len % burst))
2757 break;
2758 burst /= 2;
2759 }
2760
2761 desc->rqcfg.brst_size = 0;
2762 while (burst != (1 << desc->rqcfg.brst_size))
2763 desc->rqcfg.brst_size++;
2764
2765 desc->rqcfg.brst_len = get_burst_len(desc, len);
2766
2767 desc->txd.flags = flags;
2768
2769 return &desc->txd;
2770}
2771
2772static struct dma_async_tx_descriptor *
2773pl330_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
Vinod Kouldb8196d2011-10-13 22:34:23 +05302774 unsigned int sg_len, enum dma_transfer_direction direction,
Alexandre Bounine185ecb52012-03-08 15:35:13 -05002775 unsigned long flg, void *context)
Jassi Brarb3040e42010-05-23 20:28:19 -07002776{
2777 struct dma_pl330_desc *first, *desc = NULL;
2778 struct dma_pl330_chan *pch = to_pchan(chan);
Jassi Brarb3040e42010-05-23 20:28:19 -07002779 struct scatterlist *sg;
2780 unsigned long flags;
Boojin Kim1b9bb712011-09-02 09:44:30 +09002781 int i;
Jassi Brarb3040e42010-05-23 20:28:19 -07002782 dma_addr_t addr;
2783
Thomas Abrahamcd072512011-10-24 11:43:11 +02002784 if (unlikely(!pch || !sgl || !sg_len))
Jassi Brarb3040e42010-05-23 20:28:19 -07002785 return NULL;
2786
Boojin Kim1b9bb712011-09-02 09:44:30 +09002787 addr = pch->fifo_addr;
Jassi Brarb3040e42010-05-23 20:28:19 -07002788
2789 first = NULL;
2790
2791 for_each_sg(sgl, sg, sg_len, i) {
2792
2793 desc = pl330_get_desc(pch);
2794 if (!desc) {
2795 struct dma_pl330_dmac *pdmac = pch->dmac;
2796
2797 dev_err(pch->dmac->pif.dev,
2798 "%s:%d Unable to fetch desc\n",
2799 __func__, __LINE__);
2800 if (!first)
2801 return NULL;
2802
2803 spin_lock_irqsave(&pdmac->pool_lock, flags);
2804
2805 while (!list_empty(&first->node)) {
2806 desc = list_entry(first->node.next,
2807 struct dma_pl330_desc, node);
2808 list_move_tail(&desc->node, &pdmac->desc_pool);
2809 }
2810
2811 list_move_tail(&first->node, &pdmac->desc_pool);
2812
2813 spin_unlock_irqrestore(&pdmac->pool_lock, flags);
2814
2815 return NULL;
2816 }
2817
2818 if (!first)
2819 first = desc;
2820 else
2821 list_add_tail(&desc->node, &first->node);
2822
Vinod Kouldb8196d2011-10-13 22:34:23 +05302823 if (direction == DMA_MEM_TO_DEV) {
Jassi Brarb3040e42010-05-23 20:28:19 -07002824 desc->rqcfg.src_inc = 1;
2825 desc->rqcfg.dst_inc = 0;
Thomas Abrahamcd072512011-10-24 11:43:11 +02002826 desc->req.rqtype = MEMTODEV;
Jassi Brarb3040e42010-05-23 20:28:19 -07002827 fill_px(&desc->px,
2828 addr, sg_dma_address(sg), sg_dma_len(sg));
2829 } else {
2830 desc->rqcfg.src_inc = 0;
2831 desc->rqcfg.dst_inc = 1;
Thomas Abrahamcd072512011-10-24 11:43:11 +02002832 desc->req.rqtype = DEVTOMEM;
Jassi Brarb3040e42010-05-23 20:28:19 -07002833 fill_px(&desc->px,
2834 sg_dma_address(sg), addr, sg_dma_len(sg));
2835 }
2836
Boojin Kim1b9bb712011-09-02 09:44:30 +09002837 desc->rqcfg.brst_size = pch->burst_sz;
Jassi Brarb3040e42010-05-23 20:28:19 -07002838 desc->rqcfg.brst_len = 1;
2839 }
2840
2841 /* Return the last desc in the chain */
2842 desc->txd.flags = flg;
2843 return &desc->txd;
2844}
2845
2846static irqreturn_t pl330_irq_handler(int irq, void *data)
2847{
2848 if (pl330_update(data))
2849 return IRQ_HANDLED;
2850 else
2851 return IRQ_NONE;
2852}
2853
2854static int __devinit
Russell Kingaa25afa2011-02-19 15:55:00 +00002855pl330_probe(struct amba_device *adev, const struct amba_id *id)
Jassi Brarb3040e42010-05-23 20:28:19 -07002856{
2857 struct dma_pl330_platdata *pdat;
2858 struct dma_pl330_dmac *pdmac;
2859 struct dma_pl330_chan *pch;
2860 struct pl330_info *pi;
2861 struct dma_device *pd;
2862 struct resource *res;
2863 int i, ret, irq;
Rob Herring4e0e6102011-07-25 16:05:04 -05002864 int num_chan;
Jassi Brarb3040e42010-05-23 20:28:19 -07002865
2866 pdat = adev->dev.platform_data;
2867
Jassi Brarb3040e42010-05-23 20:28:19 -07002868 /* Allocate a new DMAC and its Channels */
Rob Herring4e0e6102011-07-25 16:05:04 -05002869 pdmac = kzalloc(sizeof(*pdmac), GFP_KERNEL);
Jassi Brarb3040e42010-05-23 20:28:19 -07002870 if (!pdmac) {
2871 dev_err(&adev->dev, "unable to allocate mem\n");
2872 return -ENOMEM;
2873 }
2874
2875 pi = &pdmac->pif;
2876 pi->dev = &adev->dev;
2877 pi->pl330_data = NULL;
Rob Herring4e0e6102011-07-25 16:05:04 -05002878 pi->mcbufsz = pdat ? pdat->mcbuf_sz : 0;
Jassi Brarb3040e42010-05-23 20:28:19 -07002879
2880 res = &adev->res;
2881 request_mem_region(res->start, resource_size(res), "dma-pl330");
2882
2883 pi->base = ioremap(res->start, resource_size(res));
2884 if (!pi->base) {
2885 ret = -ENXIO;
2886 goto probe_err1;
2887 }
2888
Boojin Kima2f52032011-09-02 09:44:29 +09002889 amba_set_drvdata(adev, pdmac);
2890
Jassi Brarb3040e42010-05-23 20:28:19 -07002891 irq = adev->irq[0];
2892 ret = request_irq(irq, pl330_irq_handler, 0,
2893 dev_name(&adev->dev), pi);
2894 if (ret)
Inderpal Singh7c71b8e2012-09-07 12:14:48 +05302895 goto probe_err2;
Jassi Brarb3040e42010-05-23 20:28:19 -07002896
2897 ret = pl330_add(pi);
2898 if (ret)
Inderpal Singh7c71b8e2012-09-07 12:14:48 +05302899 goto probe_err3;
Jassi Brarb3040e42010-05-23 20:28:19 -07002900
2901 INIT_LIST_HEAD(&pdmac->desc_pool);
2902 spin_lock_init(&pdmac->pool_lock);
2903
2904 /* Create a descriptor pool of default size */
2905 if (!add_desc(pdmac, GFP_KERNEL, NR_DEFAULT_DESC))
2906 dev_warn(&adev->dev, "unable to allocate desc\n");
2907
2908 pd = &pdmac->ddma;
2909 INIT_LIST_HEAD(&pd->channels);
2910
2911 /* Initialize channel parameters */
Olof Johanssonc8473822012-04-08 16:26:19 -07002912 if (pdat)
2913 num_chan = max_t(int, pdat->nr_valid_peri, pi->pcfg.num_chan);
2914 else
2915 num_chan = max_t(int, pi->pcfg.num_peri, pi->pcfg.num_chan);
2916
Rob Herring4e0e6102011-07-25 16:05:04 -05002917 pdmac->peripherals = kzalloc(num_chan * sizeof(*pch), GFP_KERNEL);
Sachin Kamat61c6e752012-09-17 15:20:23 +05302918 if (!pdmac->peripherals) {
2919 ret = -ENOMEM;
2920 dev_err(&adev->dev, "unable to allocate pdmac->peripherals\n");
Linus Torvaldsb7e97d22012-10-10 11:10:41 +09002921 goto probe_err4;
Sachin Kamat61c6e752012-09-17 15:20:23 +05302922 }
Jassi Brarb3040e42010-05-23 20:28:19 -07002923
Rob Herring4e0e6102011-07-25 16:05:04 -05002924 for (i = 0; i < num_chan; i++) {
2925 pch = &pdmac->peripherals[i];
Thomas Abraham93ed5542011-10-24 11:43:31 +02002926 if (!adev->dev.of_node)
2927 pch->chan.private = pdat ? &pdat->peri_id[i] : NULL;
2928 else
2929 pch->chan.private = adev->dev.of_node;
Jassi Brarb3040e42010-05-23 20:28:19 -07002930
2931 INIT_LIST_HEAD(&pch->work_list);
2932 spin_lock_init(&pch->lock);
2933 pch->pl330_chid = NULL;
Jassi Brarb3040e42010-05-23 20:28:19 -07002934 pch->chan.device = pd;
Jassi Brarb3040e42010-05-23 20:28:19 -07002935 pch->dmac = pdmac;
2936
2937 /* Add the channel to the DMAC list */
Jassi Brarb3040e42010-05-23 20:28:19 -07002938 list_add_tail(&pch->chan.device_node, &pd->channels);
2939 }
2940
2941 pd->dev = &adev->dev;
Thomas Abraham93ed5542011-10-24 11:43:31 +02002942 if (pdat) {
Thomas Abrahamcd072512011-10-24 11:43:11 +02002943 pd->cap_mask = pdat->cap_mask;
Thomas Abraham93ed5542011-10-24 11:43:31 +02002944 } else {
Thomas Abrahamcd072512011-10-24 11:43:11 +02002945 dma_cap_set(DMA_MEMCPY, pd->cap_mask);
Thomas Abraham93ed5542011-10-24 11:43:31 +02002946 if (pi->pcfg.num_peri) {
2947 dma_cap_set(DMA_SLAVE, pd->cap_mask);
2948 dma_cap_set(DMA_CYCLIC, pd->cap_mask);
Tushar Behera5557a412012-08-29 10:16:25 +05302949 dma_cap_set(DMA_PRIVATE, pd->cap_mask);
Thomas Abraham93ed5542011-10-24 11:43:31 +02002950 }
2951 }
Jassi Brarb3040e42010-05-23 20:28:19 -07002952
2953 pd->device_alloc_chan_resources = pl330_alloc_chan_resources;
2954 pd->device_free_chan_resources = pl330_free_chan_resources;
2955 pd->device_prep_dma_memcpy = pl330_prep_dma_memcpy;
Boojin Kim42bc9cf2011-09-02 09:44:33 +09002956 pd->device_prep_dma_cyclic = pl330_prep_dma_cyclic;
Jassi Brarb3040e42010-05-23 20:28:19 -07002957 pd->device_tx_status = pl330_tx_status;
2958 pd->device_prep_slave_sg = pl330_prep_slave_sg;
2959 pd->device_control = pl330_control;
2960 pd->device_issue_pending = pl330_issue_pending;
2961
2962 ret = dma_async_device_register(pd);
2963 if (ret) {
2964 dev_err(&adev->dev, "unable to register DMAC\n");
Inderpal Singh7c71b8e2012-09-07 12:14:48 +05302965 goto probe_err4;
Jassi Brarb3040e42010-05-23 20:28:19 -07002966 }
2967
Jassi Brarb3040e42010-05-23 20:28:19 -07002968 dev_info(&adev->dev,
2969 "Loaded driver for PL330 DMAC-%d\n", adev->periphid);
2970 dev_info(&adev->dev,
2971 "\tDBUFF-%ux%ubytes Num_Chans-%u Num_Peri-%u Num_Events-%u\n",
2972 pi->pcfg.data_buf_dep,
2973 pi->pcfg.data_bus_width / 8, pi->pcfg.num_chan,
2974 pi->pcfg.num_peri, pi->pcfg.num_events);
2975
2976 return 0;
2977
Julia Lawall7bec78e2012-01-12 10:55:06 +01002978probe_err4:
Inderpal Singh7c71b8e2012-09-07 12:14:48 +05302979 pl330_del(pi);
Julia Lawall7bec78e2012-01-12 10:55:06 +01002980probe_err3:
Inderpal Singh7c71b8e2012-09-07 12:14:48 +05302981 free_irq(irq, pi);
Jassi Brarb3040e42010-05-23 20:28:19 -07002982probe_err2:
2983 iounmap(pi->base);
2984probe_err1:
2985 release_mem_region(res->start, resource_size(res));
2986 kfree(pdmac);
2987
2988 return ret;
2989}
2990
2991static int __devexit pl330_remove(struct amba_device *adev)
2992{
2993 struct dma_pl330_dmac *pdmac = amba_get_drvdata(adev);
2994 struct dma_pl330_chan *pch, *_p;
2995 struct pl330_info *pi;
2996 struct resource *res;
2997 int irq;
2998
2999 if (!pdmac)
3000 return 0;
3001
3002 amba_set_drvdata(adev, NULL);
3003
3004 /* Idle the DMAC */
3005 list_for_each_entry_safe(pch, _p, &pdmac->ddma.channels,
3006 chan.device_node) {
3007
3008 /* Remove the channel */
3009 list_del(&pch->chan.device_node);
3010
3011 /* Flush the channel */
3012 pl330_control(&pch->chan, DMA_TERMINATE_ALL, 0);
3013 pl330_free_chan_resources(&pch->chan);
3014 }
3015
3016 pi = &pdmac->pif;
3017
3018 pl330_del(pi);
3019
3020 irq = adev->irq[0];
3021 free_irq(irq, pi);
3022
3023 iounmap(pi->base);
3024
3025 res = &adev->res;
3026 release_mem_region(res->start, resource_size(res));
3027
3028 kfree(pdmac);
3029
3030 return 0;
3031}
3032
3033static struct amba_id pl330_ids[] = {
3034 {
3035 .id = 0x00041330,
3036 .mask = 0x000fffff,
3037 },
3038 { 0, 0 },
3039};
3040
Dave Martine8fa5162011-10-05 15:15:20 +01003041MODULE_DEVICE_TABLE(amba, pl330_ids);
3042
Jassi Brarb3040e42010-05-23 20:28:19 -07003043static struct amba_driver pl330_driver = {
3044 .drv = {
3045 .owner = THIS_MODULE,
3046 .name = "dma-pl330",
Jassi Brarb3040e42010-05-23 20:28:19 -07003047 },
3048 .id_table = pl330_ids,
3049 .probe = pl330_probe,
3050 .remove = pl330_remove,
3051};
3052
viresh kumar9e5ed092012-03-15 10:40:38 +01003053module_amba_driver(pl330_driver);
Jassi Brarb3040e42010-05-23 20:28:19 -07003054
3055MODULE_AUTHOR("Jaswinder Singh <jassi.brar@samsung.com>");
3056MODULE_DESCRIPTION("API Driver for PL330 DMAC");
3057MODULE_LICENSE("GPL");