| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /****************************************************************************/ |
| 2 | |
| 3 | /* |
| 4 | * m527xsim.h -- ColdFire 5270/5271 System Integration Module support. |
| 5 | * |
| 6 | * (C) Copyright 2004, Greg Ungerer (gerg@snapgear.com) |
| 7 | */ |
| 8 | |
| 9 | /****************************************************************************/ |
| 10 | #ifndef m527xsim_h |
| 11 | #define m527xsim_h |
| 12 | /****************************************************************************/ |
| 13 | |
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 14 | |
| 15 | /* |
| 16 | * Define the 5270/5271 SIM register set addresses. |
| 17 | */ |
| 18 | #define MCFICM_INTC0 0x0c00 /* Base for Interrupt Ctrl 0 */ |
| 19 | #define MCFICM_INTC1 0x0d00 /* Base for Interrupt Ctrl 1 */ |
| 20 | #define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */ |
| 21 | #define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */ |
| 22 | #define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */ |
| 23 | #define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */ |
| 24 | #define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */ |
| 25 | #define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */ |
| 26 | #define MCFINTC_IRLR 0x18 /* */ |
| 27 | #define MCFINTC_IACKL 0x19 /* */ |
| 28 | #define MCFINTC_ICR0 0x40 /* Base ICR register */ |
| 29 | |
| 30 | #define MCFINT_VECBASE 64 /* Vector base number */ |
| 31 | #define MCFINT_UART0 13 /* Interrupt number for UART0 */ |
| 32 | #define MCFINT_UART1 14 /* Interrupt number for UART1 */ |
| 33 | #define MCFINT_UART2 15 /* Interrupt number for UART2 */ |
| 34 | #define MCFINT_PIT1 36 /* Interrupt number for PIT1 */ |
| 35 | |
| 36 | /* |
| 37 | * SDRAM configuration registers. |
| 38 | */ |
| Greg Ungerer | d871629 | 2005-09-12 11:18:10 +1000 | [diff] [blame] | 39 | #ifdef CONFIG_M5271 |
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 40 | #define MCFSIM_DCR 0x40 /* SDRAM control */ |
| 41 | #define MCFSIM_DACR0 0x48 /* SDRAM base address 0 */ |
| 42 | #define MCFSIM_DMR0 0x4c /* SDRAM address mask 0 */ |
| 43 | #define MCFSIM_DACR1 0x50 /* SDRAM base address 1 */ |
| 44 | #define MCFSIM_DMR1 0x54 /* SDRAM address mask 1 */ |
| Greg Ungerer | d871629 | 2005-09-12 11:18:10 +1000 | [diff] [blame] | 45 | #endif |
| 46 | #ifdef CONFIG_M5275 |
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 47 | #define MCFSIM_DMR 0x40 /* SDRAM mode */ |
| 48 | #define MCFSIM_DCR 0x44 /* SDRAM control */ |
| 49 | #define MCFSIM_DCFG1 0x48 /* SDRAM configuration 1 */ |
| 50 | #define MCFSIM_DCFG2 0x4c /* SDRAM configuration 2 */ |
| 51 | #define MCFSIM_DBAR0 0x50 /* SDRAM base address 0 */ |
| 52 | #define MCFSIM_DMR0 0x54 /* SDRAM address mask 0 */ |
| 53 | #define MCFSIM_DBAR1 0x58 /* SDRAM base address 1 */ |
| 54 | #define MCFSIM_DMR1 0x5c /* SDRAM address mask 1 */ |
| 55 | #endif |
| 56 | |
| sfking@fdwdc.com | f1554da | 2009-06-19 18:11:06 -0700 | [diff] [blame] | 57 | |
| 58 | #ifdef CONFIG_M5271 |
| 59 | #define MCFGPIO_PODR_ADDR (MCF_IPSBAR + 0x100000) |
| 60 | #define MCFGPIO_PODR_DATAH (MCF_IPSBAR + 0x100001) |
| 61 | #define MCFGPIO_PODR_DATAL (MCF_IPSBAR + 0x100002) |
| 62 | #define MCFGPIO_PODR_BUSCTL (MCF_IPSBAR + 0x100003) |
| 63 | #define MCFGPIO_PODR_BS (MCF_IPSBAR + 0x100004) |
| 64 | #define MCFGPIO_PODR_CS (MCF_IPSBAR + 0x100005) |
| 65 | #define MCFGPIO_PODR_SDRAM (MCF_IPSBAR + 0x100006) |
| 66 | #define MCFGPIO_PODR_FECI2C (MCF_IPSBAR + 0x100007) |
| 67 | #define MCFGPIO_PODR_UARTH (MCF_IPSBAR + 0x100008) |
| 68 | #define MCFGPIO_PODR_UARTL (MCF_IPSBAR + 0x100009) |
| 69 | #define MCFGPIO_PODR_QSPI (MCF_IPSBAR + 0x10000A) |
| 70 | #define MCFGPIO_PODR_TIMER (MCF_IPSBAR + 0x10000B) |
| 71 | |
| 72 | #define MCFGPIO_PDDR_ADDR (MCF_IPSBAR + 0x100010) |
| 73 | #define MCFGPIO_PDDR_DATAH (MCF_IPSBAR + 0x100011) |
| 74 | #define MCFGPIO_PDDR_DATAL (MCF_IPSBAR + 0x100012) |
| 75 | #define MCFGPIO_PDDR_BUSCTL (MCF_IPSBAR + 0x100013) |
| 76 | #define MCFGPIO_PDDR_BS (MCF_IPSBAR + 0x100014) |
| 77 | #define MCFGPIO_PDDR_CS (MCF_IPSBAR + 0x100015) |
| 78 | #define MCFGPIO_PDDR_SDRAM (MCF_IPSBAR + 0x100016) |
| 79 | #define MCFGPIO_PDDR_FECI2C (MCF_IPSBAR + 0x100017) |
| 80 | #define MCFGPIO_PDDR_UARTH (MCF_IPSBAR + 0x100018) |
| 81 | #define MCFGPIO_PDDR_UARTL (MCF_IPSBAR + 0x100019) |
| 82 | #define MCFGPIO_PDDR_QSPI (MCF_IPSBAR + 0x10001A) |
| 83 | #define MCFGPIO_PDDR_TIMER (MCF_IPSBAR + 0x10001B) |
| 84 | |
| 85 | #define MCFGPIO_PPDSDR_ADDR (MCF_IPSBAR + 0x100020) |
| 86 | #define MCFGPIO_PPDSDR_DATAH (MCF_IPSBAR + 0x100021) |
| 87 | #define MCFGPIO_PPDSDR_DATAL (MCF_IPSBAR + 0x100022) |
| 88 | #define MCFGPIO_PPDSDR_BUSCTL (MCF_IPSBAR + 0x100023) |
| 89 | #define MCFGPIO_PPDSDR_BS (MCF_IPSBAR + 0x100024) |
| 90 | #define MCFGPIO_PPDSDR_CS (MCF_IPSBAR + 0x100025) |
| 91 | #define MCFGPIO_PPDSDR_SDRAM (MCF_IPSBAR + 0x100026) |
| 92 | #define MCFGPIO_PPDSDR_FECI2C (MCF_IPSBAR + 0x100027) |
| 93 | #define MCFGPIO_PPDSDR_UARTH (MCF_IPSBAR + 0x100028) |
| 94 | #define MCFGPIO_PPDSDR_UARTL (MCF_IPSBAR + 0x100029) |
| 95 | #define MCFGPIO_PPDSDR_QSPI (MCF_IPSBAR + 0x10002A) |
| 96 | #define MCFGPIO_PPDSDR_TIMER (MCF_IPSBAR + 0x10002B) |
| 97 | |
| 98 | #define MCFGPIO_PCLRR_ADDR (MCF_IPSBAR + 0x100030) |
| 99 | #define MCFGPIO_PCLRR_DATAH (MCF_IPSBAR + 0x100031) |
| 100 | #define MCFGPIO_PCLRR_DATAL (MCF_IPSBAR + 0x100032) |
| 101 | #define MCFGPIO_PCLRR_BUSCTL (MCF_IPSBAR + 0x100033) |
| 102 | #define MCFGPIO_PCLRR_BS (MCF_IPSBAR + 0x100034) |
| 103 | #define MCFGPIO_PCLRR_CS (MCF_IPSBAR + 0x100035) |
| 104 | #define MCFGPIO_PCLRR_SDRAM (MCF_IPSBAR + 0x100036) |
| 105 | #define MCFGPIO_PCLRR_FECI2C (MCF_IPSBAR + 0x100037) |
| 106 | #define MCFGPIO_PCLRR_UARTH (MCF_IPSBAR + 0x100038) |
| 107 | #define MCFGPIO_PCLRR_UARTL (MCF_IPSBAR + 0x100039) |
| 108 | #define MCFGPIO_PCLRR_QSPI (MCF_IPSBAR + 0x10003A) |
| 109 | #define MCFGPIO_PCLRR_TIMER (MCF_IPSBAR + 0x10003B) |
| 110 | |
| 111 | /* |
| 112 | * Generic GPIO support |
| 113 | */ |
| 114 | #define MCFGPIO_PODR MCFGPIO_PODR_ADDR |
| 115 | #define MCFGPIO_PDDR MCFGPIO_PDDR_ADDR |
| 116 | #define MCFGPIO_PPDR MCFGPIO_PPDSDR_ADDR |
| 117 | #define MCFGPIO_SETR MCFGPIO_PPDSDR_ADDR |
| 118 | #define MCFGPIO_CLRR MCFGPIO_PCLRR_ADDR |
| 119 | |
| 120 | #define MCFGPIO_PIN_MAX 100 |
| 121 | #define MCFGPIO_IRQ_MAX 8 |
| 122 | #define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE |
| 123 | #endif |
| 124 | |
| 125 | #ifdef CONFIG_M5275 |
| 126 | #define MCFGPIO_PODR_BUSCTL (MCF_IPSBAR + 0x100004) |
| 127 | #define MCFGPIO_PODR_ADDR (MCF_IPSBAR + 0x100005) |
| 128 | #define MCFGPIO_PODR_CS (MCF_IPSBAR + 0x100008) |
| 129 | #define MCFGPIO_PODR_FEC0H (MCF_IPSBAR + 0x10000A) |
| 130 | #define MCFGPIO_PODR_FEC0L (MCF_IPSBAR + 0x10000B) |
| 131 | #define MCFGPIO_PODR_FECI2C (MCF_IPSBAR + 0x10000C) |
| 132 | #define MCFGPIO_PODR_QSPI (MCF_IPSBAR + 0x10000D) |
| 133 | #define MCFGPIO_PODR_SDRAM (MCF_IPSBAR + 0x10000E) |
| 134 | #define MCFGPIO_PODR_TIMERH (MCF_IPSBAR + 0x10000F) |
| 135 | #define MCFGPIO_PODR_TIMERL (MCF_IPSBAR + 0x100010) |
| 136 | #define MCFGPIO_PODR_UARTL (MCF_IPSBAR + 0x100011) |
| 137 | #define MCFGPIO_PODR_FEC1H (MCF_IPSBAR + 0x100012) |
| 138 | #define MCFGPIO_PODR_FEC1L (MCF_IPSBAR + 0x100013) |
| 139 | #define MCFGPIO_PODR_BS (MCF_IPSBAR + 0x100014) |
| 140 | #define MCFGPIO_PODR_IRQ (MCF_IPSBAR + 0x100015) |
| 141 | #define MCFGPIO_PODR_USBH (MCF_IPSBAR + 0x100016) |
| 142 | #define MCFGPIO_PODR_USBL (MCF_IPSBAR + 0x100017) |
| 143 | #define MCFGPIO_PODR_UARTH (MCF_IPSBAR + 0x100018) |
| 144 | |
| 145 | #define MCFGPIO_PDDR_BUSCTL (MCF_IPSBAR + 0x100020) |
| 146 | #define MCFGPIO_PDDR_ADDR (MCF_IPSBAR + 0x100021) |
| 147 | #define MCFGPIO_PDDR_CS (MCF_IPSBAR + 0x100024) |
| 148 | #define MCFGPIO_PDDR_FEC0H (MCF_IPSBAR + 0x100026) |
| 149 | #define MCFGPIO_PDDR_FEC0L (MCF_IPSBAR + 0x100027) |
| 150 | #define MCFGPIO_PDDR_FECI2C (MCF_IPSBAR + 0x100028) |
| 151 | #define MCFGPIO_PDDR_QSPI (MCF_IPSBAR + 0x100029) |
| 152 | #define MCFGPIO_PDDR_SDRAM (MCF_IPSBAR + 0x10002A) |
| 153 | #define MCFGPIO_PDDR_TIMERH (MCF_IPSBAR + 0x10002B) |
| 154 | #define MCFGPIO_PDDR_TIMERL (MCF_IPSBAR + 0x10002C) |
| 155 | #define MCFGPIO_PDDR_UARTL (MCF_IPSBAR + 0x10002D) |
| 156 | #define MCFGPIO_PDDR_FEC1H (MCF_IPSBAR + 0x10002E) |
| 157 | #define MCFGPIO_PDDR_FEC1L (MCF_IPSBAR + 0x10002F) |
| 158 | #define MCFGPIO_PDDR_BS (MCF_IPSBAR + 0x100030) |
| 159 | #define MCFGPIO_PDDR_IRQ (MCF_IPSBAR + 0x100031) |
| 160 | #define MCFGPIO_PDDR_USBH (MCF_IPSBAR + 0x100032) |
| 161 | #define MCFGPIO_PDDR_USBL (MCF_IPSBAR + 0x100033) |
| 162 | #define MCFGPIO_PDDR_UARTH (MCF_IPSBAR + 0x100034) |
| 163 | |
| 164 | #define MCFGPIO_PPDSDR_BUSCTL (MCF_IPSBAR + 0x10003C) |
| 165 | #define MCFGPIO_PPDSDR_ADDR (MCF_IPSBAR + 0x10003D) |
| 166 | #define MCFGPIO_PPDSDR_CS (MCF_IPSBAR + 0x100040) |
| 167 | #define MCFGPIO_PPDSDR_FEC0H (MCF_IPSBAR + 0x100042) |
| 168 | #define MCFGPIO_PPDSDR_FEC0L (MCF_IPSBAR + 0x100043) |
| 169 | #define MCFGPIO_PPDSDR_FECI2C (MCF_IPSBAR + 0x100044) |
| 170 | #define MCFGPIO_PPDSDR_QSPI (MCF_IPSBAR + 0x100045) |
| 171 | #define MCFGPIO_PPDSDR_SDRAM (MCF_IPSBAR + 0x100046) |
| 172 | #define MCFGPIO_PPDSDR_TIMERH (MCF_IPSBAR + 0x100047) |
| 173 | #define MCFGPIO_PPDSDR_TIMERL (MCF_IPSBAR + 0x100048) |
| 174 | #define MCFGPIO_PPDSDR_UARTL (MCF_IPSBAR + 0x100049) |
| 175 | #define MCFGPIO_PPDSDR_FEC1H (MCF_IPSBAR + 0x10004A) |
| 176 | #define MCFGPIO_PPDSDR_FEC1L (MCF_IPSBAR + 0x10004B) |
| 177 | #define MCFGPIO_PPDSDR_BS (MCF_IPSBAR + 0x10004C) |
| 178 | #define MCFGPIO_PPDSDR_IRQ (MCF_IPSBAR + 0x10004D) |
| 179 | #define MCFGPIO_PPDSDR_USBH (MCF_IPSBAR + 0x10004E) |
| 180 | #define MCFGPIO_PPDSDR_USBL (MCF_IPSBAR + 0x10004F) |
| 181 | #define MCFGPIO_PPDSDR_UARTH (MCF_IPSBAR + 0x100050) |
| 182 | |
| 183 | #define MCFGPIO_PCLRR_BUSCTL (MCF_IPSBAR + 0x100058) |
| 184 | #define MCFGPIO_PCLRR_ADDR (MCF_IPSBAR + 0x100059) |
| 185 | #define MCFGPIO_PCLRR_CS (MCF_IPSBAR + 0x10005C) |
| 186 | #define MCFGPIO_PCLRR_FEC0H (MCF_IPSBAR + 0x10005E) |
| 187 | #define MCFGPIO_PCLRR_FEC0L (MCF_IPSBAR + 0x10005F) |
| 188 | #define MCFGPIO_PCLRR_FECI2C (MCF_IPSBAR + 0x100060) |
| 189 | #define MCFGPIO_PCLRR_QSPI (MCF_IPSBAR + 0x100061) |
| 190 | #define MCFGPIO_PCLRR_SDRAM (MCF_IPSBAR + 0x100062) |
| 191 | #define MCFGPIO_PCLRR_TIMERH (MCF_IPSBAR + 0x100063) |
| 192 | #define MCFGPIO_PCLRR_TIMERL (MCF_IPSBAR + 0x100064) |
| 193 | #define MCFGPIO_PCLRR_UARTL (MCF_IPSBAR + 0x100065) |
| 194 | #define MCFGPIO_PCLRR_FEC1H (MCF_IPSBAR + 0x100066) |
| 195 | #define MCFGPIO_PCLRR_FEC1L (MCF_IPSBAR + 0x100067) |
| 196 | #define MCFGPIO_PCLRR_BS (MCF_IPSBAR + 0x100068) |
| 197 | #define MCFGPIO_PCLRR_IRQ (MCF_IPSBAR + 0x100069) |
| 198 | #define MCFGPIO_PCLRR_USBH (MCF_IPSBAR + 0x10006A) |
| 199 | #define MCFGPIO_PCLRR_USBL (MCF_IPSBAR + 0x10006B) |
| 200 | #define MCFGPIO_PCLRR_UARTH (MCF_IPSBAR + 0x10006C) |
| 201 | |
| 202 | |
| 203 | /* |
| 204 | * Generic GPIO support |
| 205 | */ |
| 206 | #define MCFGPIO_PODR MCFGPIO_PODR_BUSCTL |
| 207 | #define MCFGPIO_PDDR MCFGPIO_PDDR_BUSCTL |
| 208 | #define MCFGPIO_PPDR MCFGPIO_PPDSDR_BUSCTL |
| 209 | #define MCFGPIO_SETR MCFGPIO_PPDSDR_BUSCTL |
| 210 | #define MCFGPIO_CLRR MCFGPIO_PCLRR_BUSCTL |
| 211 | |
| 212 | #define MCFGPIO_PIN_MAX 148 |
| 213 | #define MCFGPIO_IRQ_MAX 8 |
| 214 | #define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE |
| 215 | #endif |
| 216 | |
| 217 | /* |
| 218 | * EPort |
| 219 | */ |
| 220 | |
| 221 | #define MCFEPORT_EPDDR (MCF_IPSBAR + 0x130002) |
| 222 | #define MCFEPORT_EPDR (MCF_IPSBAR + 0x130004) |
| 223 | #define MCFEPORT_EPPDR (MCF_IPSBAR + 0x130005) |
| 224 | |
| 225 | |
| Greg Ungerer | d871629 | 2005-09-12 11:18:10 +1000 | [diff] [blame] | 226 | /* |
| 227 | * GPIO pins setups to enable the UARTs. |
| 228 | */ |
| 229 | #ifdef CONFIG_M5271 |
| 230 | #define MCF_GPIO_PAR_UART 0x100048 /* PAR UART address */ |
| 231 | #define UART0_ENABLE_MASK 0x000f |
| 232 | #define UART1_ENABLE_MASK 0x0ff0 |
| 233 | #define UART2_ENABLE_MASK 0x3000 |
| 234 | #endif |
| 235 | #ifdef CONFIG_M5275 |
| 236 | #define MCF_GPIO_PAR_UART 0x10007c /* PAR UART address */ |
| 237 | #define UART0_ENABLE_MASK 0x000f |
| 238 | #define UART1_ENABLE_MASK 0x00f0 |
| 239 | #define UART2_ENABLE_MASK 0x3f00 |
| 240 | #endif |
| 241 | |
| Greg Ungerer | 4c0b008 | 2009-04-30 23:06:45 +1000 | [diff] [blame] | 242 | /* |
| 243 | * Reset Controll Unit (relative to IPSBAR). |
| 244 | */ |
| 245 | #define MCF_RCR 0x110000 |
| 246 | #define MCF_RSR 0x110001 |
| 247 | |
| 248 | #define MCF_RCR_SWRESET 0x80 /* Software reset bit */ |
| 249 | #define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */ |
| 250 | |
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 251 | /****************************************************************************/ |
| 252 | #endif /* m527xsim_h */ |