blob: fdffa1beca17288eeab2055d25382545c3dbbdcf [file] [log] [blame]
Alan Coxda9bb1d2006-01-18 17:44:13 -08001#
2# EDAC Kconfig
Doug Thompson4577ca52009-04-02 16:58:43 -07003# Copyright (c) 2008 Doug Thompson www.softwarebitmaker.com
Alan Coxda9bb1d2006-01-18 17:44:13 -08004# Licensed and distributed under the GPL
5#
Alan Coxda9bb1d2006-01-18 17:44:13 -08006
Jan Engelhardt751cb5e2007-07-15 23:39:27 -07007menuconfig EDAC
GeunSik Lime24aca62009-06-17 16:28:02 -07008 bool "EDAC (Error Detection And Correction) reporting"
Martin Schwidefskye25df122007-05-10 15:45:57 +02009 depends on HAS_IOMEM
Chris Metcalf5c770752011-03-01 13:01:49 -050010 depends on X86 || PPC || TILE
Alan Coxda9bb1d2006-01-18 17:44:13 -080011 help
12 EDAC is designed to report errors in the core system.
13 These are low-level errors that are reported in the CPU or
Douglas Thompson8cb2a392007-07-19 01:50:12 -070014 supporting chipset or other subsystems:
15 memory errors, cache errors, PCI errors, thermal throttling, etc..
16 If unsure, select 'Y'.
Alan Coxda9bb1d2006-01-18 17:44:13 -080017
Tim Small57c432b2006-03-09 17:33:50 -080018 If this code is reporting problems on your system, please
19 see the EDAC project web pages for more information at:
20
21 <http://bluesmoke.sourceforge.net/>
22
23 and:
24
25 <http://buttersideup.com/edacwiki>
26
27 There is also a mailing list for the EDAC project, which can
28 be found via the sourceforge page.
29
Jan Engelhardt751cb5e2007-07-15 23:39:27 -070030if EDAC
Alan Coxda9bb1d2006-01-18 17:44:13 -080031
32comment "Reporting subsystems"
Alan Coxda9bb1d2006-01-18 17:44:13 -080033
34config EDAC_DEBUG
35 bool "Debugging"
Alan Coxda9bb1d2006-01-18 17:44:13 -080036 help
37 This turns on debugging information for the entire EDAC
38 sub-system. You can insert module with "debug_level=x", current
39 there're four debug levels (x=0,1,2,3 from low to high).
40 Usually you should select 'N'.
41
Borislav Petkov9cdeb402010-09-02 18:33:24 +020042config EDAC_DECODE_MCE
Borislav Petkov0d18b2e2009-10-02 15:31:48 +020043 tristate "Decode MCEs in human-readable form (only on AMD for now)"
Borislav Petkov168eb342011-08-10 09:43:30 -030044 depends on CPU_SUP_AMD && X86_MCE_AMD
Borislav Petkov0d18b2e2009-10-02 15:31:48 +020045 default y
46 ---help---
47 Enable this option if you want to decode Machine Check Exceptions
Lucas De Marchi25985ed2011-03-30 22:57:33 -030048 occurring on your machine in human-readable form.
Borislav Petkov0d18b2e2009-10-02 15:31:48 +020049
50 You should definitely say Y here in case you want to decode MCEs
51 which occur really early upon boot, before the module infrastructure
52 has been initialized.
53
Borislav Petkov9cdeb402010-09-02 18:33:24 +020054config EDAC_MCE_INJ
55 tristate "Simple MCE injection interface over /sysfs"
56 depends on EDAC_DECODE_MCE
57 default n
58 help
59 This is a simple interface to inject MCEs over /sysfs and test
60 the MCE decoding code in EDAC.
61
62 This is currently AMD-only.
63
Alan Coxda9bb1d2006-01-18 17:44:13 -080064config EDAC_MM_EDAC
65 tristate "Main Memory EDAC (Error Detection And Correction) reporting"
Alan Coxda9bb1d2006-01-18 17:44:13 -080066 help
67 Some systems are able to detect and correct errors in main
68 memory. EDAC can report statistics on memory error
69 detection and correction (EDAC - or commonly referred to ECC
70 errors). EDAC will also try to decode where these errors
71 occurred so that a particular failing memory module can be
72 replaced. If unsure, select 'Y'.
73
Doug Thompson7d6034d2009-04-27 20:01:01 +020074config EDAC_AMD64
Borislav Petkov027dbd62010-10-13 22:12:15 +020075 tristate "AMD64 (Opteron, Athlon64) K8, F10h"
76 depends on EDAC_MM_EDAC && AMD_NB && X86_64 && EDAC_DECODE_MCE
Doug Thompson7d6034d2009-04-27 20:01:01 +020077 help
Borislav Petkov027dbd62010-10-13 22:12:15 +020078 Support for error detection and correction of DRAM ECC errors on
79 the AMD64 families of memory controllers (K8 and F10h)
Doug Thompson7d6034d2009-04-27 20:01:01 +020080
81config EDAC_AMD64_ERROR_INJECTION
Borislav Petkov9cdeb402010-09-02 18:33:24 +020082 bool "Sysfs HW Error injection facilities"
Doug Thompson7d6034d2009-04-27 20:01:01 +020083 depends on EDAC_AMD64
84 help
85 Recent Opterons (Family 10h and later) provide for Memory Error
86 Injection into the ECC detection circuits. The amd64_edac module
87 allows the operator/user to inject Uncorrectable and Correctable
88 errors into DRAM.
89
90 When enabled, in each of the respective memory controller directories
91 (/sys/devices/system/edac/mc/mcX), there are 3 input files:
92
93 - inject_section (0..3, 16-byte section of 64-byte cacheline),
94 - inject_word (0..8, 16-bit word of 16-byte section),
95 - inject_ecc_vector (hex ecc vector: select bits of inject word)
96
97 In addition, there are two control files, inject_read and inject_write,
98 which trigger the DRAM ECC Read and Write respectively.
Alan Coxda9bb1d2006-01-18 17:44:13 -080099
100config EDAC_AMD76X
101 tristate "AMD 76x (760, 762, 768)"
Dave Jones90cbc452006-02-03 03:04:11 -0800102 depends on EDAC_MM_EDAC && PCI && X86_32
Alan Coxda9bb1d2006-01-18 17:44:13 -0800103 help
104 Support for error detection and correction on the AMD 76x
105 series of chipsets used with the Athlon processor.
106
107config EDAC_E7XXX
108 tristate "Intel e7xxx (e7205, e7500, e7501, e7505)"
Dave Peterson39f1d8d2006-03-26 01:38:50 -0800109 depends on EDAC_MM_EDAC && PCI && X86_32
Alan Coxda9bb1d2006-01-18 17:44:13 -0800110 help
111 Support for error detection and correction on the Intel
112 E7205, E7500, E7501 and E7505 server chipsets.
113
114config EDAC_E752X
Andrei Konovalov5135b792008-04-29 01:03:13 -0700115 tristate "Intel e752x (e7520, e7525, e7320) and 3100"
Randy Dunlapda960a62006-03-31 02:30:34 -0800116 depends on EDAC_MM_EDAC && PCI && X86 && HOTPLUG
Alan Coxda9bb1d2006-01-18 17:44:13 -0800117 help
118 Support for error detection and correction on the Intel
119 E7520, E7525, E7320 server chipsets.
120
Tim Small5a2c6752007-07-19 01:49:42 -0700121config EDAC_I82443BXGX
122 tristate "Intel 82443BX/GX (440BX/GX)"
123 depends on EDAC_MM_EDAC && PCI && X86_32
Andrew Morton28f96eea2007-07-19 01:49:45 -0700124 depends on BROKEN
Tim Small5a2c6752007-07-19 01:49:42 -0700125 help
126 Support for error detection and correction on the Intel
127 82443BX/GX memory controllers (440BX/GX chipsets).
128
Alan Coxda9bb1d2006-01-18 17:44:13 -0800129config EDAC_I82875P
130 tristate "Intel 82875p (D82875P, E7210)"
Dave Peterson39f1d8d2006-03-26 01:38:50 -0800131 depends on EDAC_MM_EDAC && PCI && X86_32
Alan Coxda9bb1d2006-01-18 17:44:13 -0800132 help
133 Support for error detection and correction on the Intel
134 DP82785P and E7210 server chipsets.
135
Ranganathan Desikan420390f2007-07-19 01:50:31 -0700136config EDAC_I82975X
137 tristate "Intel 82975x (D82975x)"
138 depends on EDAC_MM_EDAC && PCI && X86
139 help
140 Support for error detection and correction on the Intel
141 DP82975x server chipsets.
142
Jason Uhlenkott535c6a52007-07-19 01:49:48 -0700143config EDAC_I3000
144 tristate "Intel 3000/3010"
Jason Uhlenkottf5c04542008-02-07 00:15:01 -0800145 depends on EDAC_MM_EDAC && PCI && X86
Jason Uhlenkott535c6a52007-07-19 01:49:48 -0700146 help
147 Support for error detection and correction on the Intel
148 3000 and 3010 server chipsets.
149
Jason Uhlenkottdd8ef1d2009-09-23 15:57:27 -0700150config EDAC_I3200
151 tristate "Intel 3200"
152 depends on EDAC_MM_EDAC && PCI && X86 && EXPERIMENTAL
153 help
154 Support for error detection and correction on the Intel
155 3200 and 3210 server chipsets.
156
Hitoshi Mitakedf8bc08c2008-10-29 14:00:50 -0700157config EDAC_X38
158 tristate "Intel X38"
159 depends on EDAC_MM_EDAC && PCI && X86
160 help
161 Support for error detection and correction on the Intel
162 X38 server chipsets.
163
Mauro Carvalho Chehab920c8df2009-01-06 14:43:00 -0800164config EDAC_I5400
165 tristate "Intel 5400 (Seaburg) chipsets"
166 depends on EDAC_MM_EDAC && PCI && X86
167 help
168 Support for error detection and correction the Intel
169 i5400 MCH chipset (Seaburg).
170
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300171config EDAC_I7CORE
172 tristate "Intel i7 Core (Nehalem) processors"
Borislav Petkov168eb342011-08-10 09:43:30 -0300173 depends on EDAC_MM_EDAC && PCI && X86 && X86_MCE_INTEL
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300174 help
175 Support for error detection and correction the Intel
Mauro Carvalho Chehab696e4092009-07-23 06:57:45 -0300176 i7 Core (Nehalem) Integrated Memory Controller that exists on
177 newer processors like i7 Core, i7 Core Extreme, Xeon 35xx
178 and Xeon 55xx processors.
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300179
Alan Coxda9bb1d2006-01-18 17:44:13 -0800180config EDAC_I82860
181 tristate "Intel 82860"
Dave Peterson39f1d8d2006-03-26 01:38:50 -0800182 depends on EDAC_MM_EDAC && PCI && X86_32
Alan Coxda9bb1d2006-01-18 17:44:13 -0800183 help
184 Support for error detection and correction on the Intel
185 82860 chipset.
186
187config EDAC_R82600
188 tristate "Radisys 82600 embedded chipset"
Dave Peterson39f1d8d2006-03-26 01:38:50 -0800189 depends on EDAC_MM_EDAC && PCI && X86_32
Alan Coxda9bb1d2006-01-18 17:44:13 -0800190 help
191 Support for error detection and correction on the Radisys
192 82600 embedded chipset.
193
Eric Wolleseneb607052007-07-19 01:49:39 -0700194config EDAC_I5000
195 tristate "Intel Greencreek/Blackford chipset"
196 depends on EDAC_MM_EDAC && X86 && PCI
197 help
198 Support for error detection and correction the Intel
199 Greekcreek/Blackford chipsets.
200
Arthur Jones8f421c592008-07-25 01:49:04 -0700201config EDAC_I5100
202 tristate "Intel San Clemente MCH"
203 depends on EDAC_MM_EDAC && X86 && PCI
204 help
205 Support for error detection and correction the Intel
206 San Clemente MCH.
207
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300208config EDAC_I7300
209 tristate "Intel Clarksboro MCH"
210 depends on EDAC_MM_EDAC && X86 && PCI
211 help
212 Support for error detection and correction the Intel
213 Clarksboro MCH (Intel 7300 chipset).
214
Mauro Carvalho Chehab3d78c9a2011-10-20 19:33:46 -0200215config EDAC_SBRIDGE
216 tristate "Intel Sandy-Bridge Integrated MC"
Hui Wang22a5c272012-02-06 04:10:59 -0300217 depends on EDAC_MM_EDAC && PCI && X86_64 && X86_MCE_INTEL
218 depends on PCI_MMCONFIG && EXPERIMENTAL
Mauro Carvalho Chehab3d78c9a2011-10-20 19:33:46 -0200219 help
220 Support for error detection and correction the Intel
221 Sandy Bridge Integrated Memory Controller.
222
Dave Jianga9a753d2008-02-07 00:14:55 -0800223config EDAC_MPC85XX
Ira W. Snyderb4846252009-09-23 15:57:25 -0700224 tristate "Freescale MPC83xx / MPC85xx"
Anton Vorontsov1cd85212010-07-20 13:24:27 -0700225 depends on EDAC_MM_EDAC && FSL_SOC && (PPC_83xx || PPC_85xx)
Dave Jianga9a753d2008-02-07 00:14:55 -0800226 help
227 Support for error detection and correction on the Freescale
Ira W. Snyderb4846252009-09-23 15:57:25 -0700228 MPC8349, MPC8560, MPC8540, MPC8548
Dave Jianga9a753d2008-02-07 00:14:55 -0800229
Dave Jiang4f4aeea2008-02-07 00:14:56 -0800230config EDAC_MV64X60
231 tristate "Marvell MV64x60"
232 depends on EDAC_MM_EDAC && MV64X60
233 help
234 Support for error detection and correction on the Marvell
235 MV64360 and MV64460 chipsets.
236
Egor Martovetsky7d8536f2007-07-19 01:50:24 -0700237config EDAC_PASEMI
238 tristate "PA Semi PWRficient"
239 depends on EDAC_MM_EDAC && PCI
Doug Thompsonddcc3052007-07-26 10:41:16 -0700240 depends on PPC_PASEMI
Egor Martovetsky7d8536f2007-07-19 01:50:24 -0700241 help
242 Support for error detection and correction on PA Semi
243 PWRficient.
244
Benjamin Herrenschmidt48764e42008-02-07 00:14:53 -0800245config EDAC_CELL
246 tristate "Cell Broadband Engine memory controller"
Benjamin Krilldef434c2008-11-27 16:15:44 +0100247 depends on EDAC_MM_EDAC && PPC_CELL_COMMON
Benjamin Herrenschmidt48764e42008-02-07 00:14:53 -0800248 help
249 Support for error detection and correction on the
250 Cell Broadband Engine internal memory controller
251 on platform without a hypervisor
Egor Martovetsky7d8536f2007-07-19 01:50:24 -0700252
Grant Ericksondba7a772009-04-02 16:58:45 -0700253config EDAC_PPC4XX
254 tristate "PPC4xx IBM DDR2 Memory Controller"
255 depends on EDAC_MM_EDAC && 4xx
256 help
257 This enables support for EDAC on the ECC memory used
258 with the IBM DDR2 memory controller found in various
259 PowerPC 4xx embedded processors such as the 405EX[r],
260 440SP, 440SPe, 460EX, 460GT and 460SX.
261
Harry Ciaoe8765582009-04-02 16:58:51 -0700262config EDAC_AMD8131
263 tristate "AMD8131 HyperTransport PCI-X Tunnel"
Harry Ciao715fe7a2009-05-28 14:34:43 -0700264 depends on EDAC_MM_EDAC && PCI && PPC_MAPLE
Harry Ciaoe8765582009-04-02 16:58:51 -0700265 help
266 Support for error detection and correction on the
267 AMD8131 HyperTransport PCI-X Tunnel chip.
Harry Ciao715fe7a2009-05-28 14:34:43 -0700268 Note, add more Kconfig dependency if it's adopted
269 on some machine other than Maple.
Harry Ciaoe8765582009-04-02 16:58:51 -0700270
Harry Ciao58b4ce62009-04-02 16:58:51 -0700271config EDAC_AMD8111
272 tristate "AMD8111 HyperTransport I/O Hub"
Harry Ciao715fe7a2009-05-28 14:34:43 -0700273 depends on EDAC_MM_EDAC && PCI && PPC_MAPLE
Harry Ciao58b4ce62009-04-02 16:58:51 -0700274 help
275 Support for error detection and correction on the
276 AMD8111 HyperTransport I/O Hub chip.
Harry Ciao715fe7a2009-05-28 14:34:43 -0700277 Note, add more Kconfig dependency if it's adopted
278 on some machine other than Maple.
Harry Ciao58b4ce62009-04-02 16:58:51 -0700279
Harry Ciao2a9036a2009-06-17 16:27:58 -0700280config EDAC_CPC925
281 tristate "IBM CPC925 Memory Controller (PPC970FX)"
282 depends on EDAC_MM_EDAC && PPC64
283 help
284 Support for error detection and correction on the
285 IBM CPC925 Bridge and Memory Controller, which is
286 a companion chip to the PowerPC 970 family of
287 processors.
288
Chris Metcalf5c770752011-03-01 13:01:49 -0500289config EDAC_TILE
290 tristate "Tilera Memory Controller"
291 depends on EDAC_MM_EDAC && TILE
292 default y
293 help
294 Support for error detection and correction on the
295 Tilera memory controller.
296
Jan Engelhardt751cb5e2007-07-15 23:39:27 -0700297endif # EDAC